2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/appdomain.h>
21 #include <mono/metadata/debug-helpers.h>
22 #include <mono/metadata/threads.h>
23 #include <mono/metadata/profiler-private.h>
24 #include <mono/metadata/mono-debug.h>
25 #include <mono/metadata/gc-internal.h>
26 #include <mono/utils/mono-math.h>
27 #include <mono/utils/mono-counters.h>
28 #include <mono/utils/mono-mmap.h>
29 #include <mono/utils/mono-memory-model.h>
30 #include <mono/utils/mono-hwcap-x86.h>
38 /* On windows, these hold the key returned by TlsAlloc () */
39 static gint lmf_tls_offset = -1;
41 static gint jit_tls_offset = -1;
43 static gint lmf_addr_tls_offset = -1;
45 static gint appdomain_tls_offset = -1;
48 static gboolean optimize_for_xen = TRUE;
50 #define optimize_for_xen 0
54 static gboolean is_win32 = TRUE;
56 static gboolean is_win32 = FALSE;
59 /* This mutex protects architecture specific caches */
60 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
61 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
62 static CRITICAL_SECTION mini_arch_mutex;
64 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
69 /* Under windows, the default pinvoke calling convention is stdcall */
70 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
72 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
75 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
78 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
81 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
83 #ifdef __native_client_codegen__
85 /* Default alignment for Native Client is 32-byte. */
86 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
88 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
89 /* Check that alignment doesn't cross an alignment boundary. */
91 mono_arch_nacl_pad (guint8 *code, int pad)
93 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
95 if (pad == 0) return code;
96 /* assertion: alignment cannot cross a block boundary */
97 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
98 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
99 while (pad >= kMaxPadding) {
100 x86_padding (code, kMaxPadding);
103 if (pad != 0) x86_padding (code, pad);
108 mono_arch_nacl_skip_nops (guint8 *code)
110 x86_skip_nops (code);
114 #endif /* __native_client_codegen__ */
117 * The code generated for sequence points reads from this location, which is
118 * made read-only when single stepping is enabled.
120 static gpointer ss_trigger_page;
122 /* Enabled breakpoints read from this trigger page */
123 static gpointer bp_trigger_page;
126 mono_arch_regname (int reg)
129 case X86_EAX: return "%eax";
130 case X86_EBX: return "%ebx";
131 case X86_ECX: return "%ecx";
132 case X86_EDX: return "%edx";
133 case X86_ESP: return "%esp";
134 case X86_EBP: return "%ebp";
135 case X86_EDI: return "%edi";
136 case X86_ESI: return "%esi";
142 mono_arch_fregname (int reg)
167 mono_arch_xregname (int reg)
192 mono_x86_patch (unsigned char* code, gpointer target)
194 x86_patch (code, (unsigned char*)target);
205 /* gsharedvt argument passed by addr */
217 /* Only if storage == ArgValuetypeInReg */
218 ArgStorage pair_storage [2];
227 gboolean need_stack_align;
228 guint32 stack_align_amount;
229 gboolean vtype_retaddr;
230 /* The index of the vret arg in the argument list */
238 #define FLOAT_PARAM_REGS 0
240 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
242 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
247 switch (sig->call_convention) {
248 case MONO_CALL_THISCALL:
249 return thiscall_param_regs;
255 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
256 #define SMALL_STRUCTS_IN_REGS
257 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
261 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
263 ainfo->offset = *stack_size;
265 if (!param_regs || param_regs [*gr] == X86_NREG) {
266 ainfo->storage = ArgOnStack;
268 (*stack_size) += sizeof (gpointer);
271 ainfo->storage = ArgInIReg;
272 ainfo->reg = param_regs [*gr];
278 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
280 ainfo->offset = *stack_size;
282 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
284 ainfo->storage = ArgOnStack;
285 (*stack_size) += sizeof (gpointer) * 2;
290 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
292 ainfo->offset = *stack_size;
294 if (*gr >= FLOAT_PARAM_REGS) {
295 ainfo->storage = ArgOnStack;
296 (*stack_size) += is_double ? 8 : 4;
297 ainfo->nslots = is_double ? 2 : 1;
300 /* A double register */
302 ainfo->storage = ArgInDoubleSSEReg;
304 ainfo->storage = ArgInFloatSSEReg;
312 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
314 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
319 klass = mono_class_from_mono_type (type);
320 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
322 #ifdef SMALL_STRUCTS_IN_REGS
323 if (sig->pinvoke && is_return) {
324 MonoMarshalType *info;
327 * the exact rules are not very well documented, the code below seems to work with the
328 * code generated by gcc 3.3.3 -mno-cygwin.
330 info = mono_marshal_load_type_info (klass);
333 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
335 /* Special case structs with only a float member */
336 if (info->num_fields == 1) {
337 int ftype = info->fields [0].field->type->type;
338 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
339 ainfo->storage = ArgValuetypeInReg;
340 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
343 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
344 ainfo->storage = ArgValuetypeInReg;
345 ainfo->pair_storage [0] = ArgOnFloatFpStack;
349 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
350 ainfo->storage = ArgValuetypeInReg;
351 ainfo->pair_storage [0] = ArgInIReg;
352 ainfo->pair_regs [0] = return_regs [0];
353 if (info->native_size > 4) {
354 ainfo->pair_storage [1] = ArgInIReg;
355 ainfo->pair_regs [1] = return_regs [1];
362 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
363 g_assert (size <= 4);
364 ainfo->storage = ArgValuetypeInReg;
365 ainfo->reg = param_regs [*gr];
370 ainfo->offset = *stack_size;
371 ainfo->storage = ArgOnStack;
372 *stack_size += ALIGN_TO (size, sizeof (gpointer));
373 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
379 * Obtain information about a call according to the calling convention.
380 * For x86 ELF, see the "System V Application Binary Interface Intel386
381 * Architecture Processor Supplment, Fourth Edition" document for more
383 * For x86 win32, see ???.
386 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
388 guint32 i, gr, fr, pstart;
389 const guint32 *param_regs;
391 int n = sig->hasthis + sig->param_count;
392 guint32 stack_size = 0;
393 gboolean is_pinvoke = sig->pinvoke;
399 param_regs = callconv_param_regs(sig);
403 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
404 switch (ret_type->type) {
405 case MONO_TYPE_BOOLEAN:
416 case MONO_TYPE_FNPTR:
417 case MONO_TYPE_CLASS:
418 case MONO_TYPE_OBJECT:
419 case MONO_TYPE_SZARRAY:
420 case MONO_TYPE_ARRAY:
421 case MONO_TYPE_STRING:
422 cinfo->ret.storage = ArgInIReg;
423 cinfo->ret.reg = X86_EAX;
427 cinfo->ret.storage = ArgInIReg;
428 cinfo->ret.reg = X86_EAX;
429 cinfo->ret.is_pair = TRUE;
432 cinfo->ret.storage = ArgOnFloatFpStack;
435 cinfo->ret.storage = ArgOnDoubleFpStack;
437 case MONO_TYPE_GENERICINST:
438 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
439 cinfo->ret.storage = ArgInIReg;
440 cinfo->ret.reg = X86_EAX;
443 if (mini_is_gsharedvt_type_gsctx (gsctx, ret_type)) {
444 cinfo->ret.storage = ArgOnStack;
445 cinfo->vtype_retaddr = TRUE;
449 case MONO_TYPE_VALUETYPE:
450 case MONO_TYPE_TYPEDBYREF: {
451 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
453 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
454 if (cinfo->ret.storage == ArgOnStack) {
455 cinfo->vtype_retaddr = TRUE;
456 /* The caller passes the address where the value is stored */
462 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ret_type));
463 cinfo->ret.storage = ArgOnStack;
464 cinfo->vtype_retaddr = TRUE;
467 cinfo->ret.storage = ArgNone;
470 g_error ("Can't handle as return value 0x%x", ret_type->type);
476 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
477 * the first argument, allowing 'this' to be always passed in the first arg reg.
478 * Also do this if the first argument is a reference type, since virtual calls
479 * are sometimes made using calli without sig->hasthis set, like in the delegate
482 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
484 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
486 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
489 cinfo->vret_arg_offset = stack_size;
490 add_general (&gr, NULL, &stack_size, &cinfo->ret);
491 cinfo->vret_arg_index = 1;
495 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
497 if (cinfo->vtype_retaddr)
498 add_general (&gr, NULL, &stack_size, &cinfo->ret);
501 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
502 fr = FLOAT_PARAM_REGS;
504 /* Emit the signature cookie just before the implicit arguments */
505 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
508 for (i = pstart; i < sig->param_count; ++i) {
509 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
512 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
513 /* We allways pass the sig cookie on the stack for simplicity */
515 * Prevent implicit arguments + the sig cookie from being passed
518 fr = FLOAT_PARAM_REGS;
520 /* Emit the signature cookie just before the implicit arguments */
521 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
524 if (sig->params [i]->byref) {
525 add_general (&gr, param_regs, &stack_size, ainfo);
528 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
529 switch (ptype->type) {
530 case MONO_TYPE_BOOLEAN:
533 add_general (&gr, param_regs, &stack_size, ainfo);
538 add_general (&gr, param_regs, &stack_size, ainfo);
542 add_general (&gr, param_regs, &stack_size, ainfo);
547 case MONO_TYPE_FNPTR:
548 case MONO_TYPE_CLASS:
549 case MONO_TYPE_OBJECT:
550 case MONO_TYPE_STRING:
551 case MONO_TYPE_SZARRAY:
552 case MONO_TYPE_ARRAY:
553 add_general (&gr, param_regs, &stack_size, ainfo);
555 case MONO_TYPE_GENERICINST:
556 if (!mono_type_generic_inst_is_valuetype (ptype)) {
557 add_general (&gr, param_regs, &stack_size, ainfo);
560 if (mini_is_gsharedvt_type_gsctx (gsctx, ptype)) {
561 /* gsharedvt arguments are passed by ref */
562 add_general (&gr, param_regs, &stack_size, ainfo);
563 g_assert (ainfo->storage == ArgOnStack);
564 ainfo->storage = ArgGSharedVt;
568 case MONO_TYPE_VALUETYPE:
569 case MONO_TYPE_TYPEDBYREF:
570 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
574 add_general_pair (&gr, param_regs, &stack_size, ainfo);
577 add_float (&fr, &stack_size, ainfo, FALSE);
580 add_float (&fr, &stack_size, ainfo, TRUE);
584 /* gsharedvt arguments are passed by ref */
585 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ptype));
586 add_general (&gr, param_regs, &stack_size, ainfo);
587 g_assert (ainfo->storage == ArgOnStack);
588 ainfo->storage = ArgGSharedVt;
591 g_error ("unexpected type 0x%x", ptype->type);
592 g_assert_not_reached ();
596 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
597 fr = FLOAT_PARAM_REGS;
599 /* Emit the signature cookie just before the implicit arguments */
600 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
603 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
604 cinfo->need_stack_align = TRUE;
605 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
606 stack_size += cinfo->stack_align_amount;
609 cinfo->stack_usage = stack_size;
610 cinfo->reg_usage = gr;
611 cinfo->freg_usage = fr;
616 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
618 int n = sig->hasthis + sig->param_count;
622 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
624 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
626 return get_call_info_internal (gsctx, cinfo, sig);
630 * mono_arch_get_argument_info:
631 * @csig: a method signature
632 * @param_count: the number of parameters to consider
633 * @arg_info: an array to store the result infos
635 * Gathers information on parameters such as size, alignment and
636 * padding. arg_info should be large enought to hold param_count + 1 entries.
638 * Returns the size of the argument area on the stack.
639 * This should be signal safe, since it is called from
640 * mono_arch_find_jit_info ().
641 * FIXME: The metadata calls might not be signal safe.
644 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
646 int len, k, args_size = 0;
652 /* Avoid g_malloc as it is not signal safe */
653 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
654 cinfo = (CallInfo*)g_newa (guint8*, len);
655 memset (cinfo, 0, len);
657 cinfo = get_call_info_internal (gsctx, cinfo, csig);
659 arg_info [0].offset = offset;
661 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
662 args_size += sizeof (gpointer);
667 args_size += sizeof (gpointer);
671 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
672 /* Emitted after this */
673 args_size += sizeof (gpointer);
677 arg_info [0].size = args_size;
679 for (k = 0; k < param_count; k++) {
680 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
682 /* ignore alignment for now */
685 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
686 arg_info [k].pad = pad;
688 arg_info [k + 1].pad = 0;
689 arg_info [k + 1].size = size;
691 arg_info [k + 1].offset = offset;
694 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
695 /* Emitted after the first arg */
696 args_size += sizeof (gpointer);
701 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
702 align = MONO_ARCH_FRAME_ALIGNMENT;
705 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
706 arg_info [k].pad = pad;
712 mono_arch_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
714 MonoType *callee_ret;
718 c1 = get_call_info (NULL, NULL, caller_sig);
719 c2 = get_call_info (NULL, NULL, callee_sig);
721 * Tail calls with more callee stack usage than the caller cannot be supported, since
722 * the extra stack space would be left on the stack after the tail call.
724 res = c1->stack_usage >= c2->stack_usage;
725 callee_ret = callee_sig->ret;
726 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
727 /* An address on the callee's stack is passed as the first argument */
737 * Initialize the cpu to execute managed code.
740 mono_arch_cpu_init (void)
742 /* spec compliance requires running with double precision */
746 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
747 fpcw &= ~X86_FPCW_PRECC_MASK;
748 fpcw |= X86_FPCW_PREC_DOUBLE;
749 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
750 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
752 _control87 (_PC_53, MCW_PC);
757 * Initialize architecture specific code.
760 mono_arch_init (void)
762 InitializeCriticalSection (&mini_arch_mutex);
764 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
765 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
766 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
768 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
769 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
770 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
771 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
776 * Cleanup architecture specific code.
779 mono_arch_cleanup (void)
782 mono_vfree (ss_trigger_page, mono_pagesize ());
784 mono_vfree (bp_trigger_page, mono_pagesize ());
785 DeleteCriticalSection (&mini_arch_mutex);
789 * This function returns the optimizations supported on this cpu.
792 mono_arch_cpu_optimizations (guint32 *exclude_mask)
794 #if !defined(__native_client__)
799 if (mono_hwcap_x86_has_cmov) {
800 opts |= MONO_OPT_CMOV;
802 if (mono_hwcap_x86_has_fcmov)
803 opts |= MONO_OPT_FCMOV;
805 *exclude_mask |= MONO_OPT_FCMOV;
807 *exclude_mask |= MONO_OPT_CMOV;
810 if (mono_hwcap_x86_has_sse2)
811 opts |= MONO_OPT_SSE2;
813 *exclude_mask |= MONO_OPT_SSE2;
815 #ifdef MONO_ARCH_SIMD_INTRINSICS
816 /*SIMD intrinsics require at least SSE2.*/
817 if (!mono_hwcap_x86_has_sse2)
818 *exclude_mask |= MONO_OPT_SIMD;
823 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
828 * This function test for all SSE functions supported.
830 * Returns a bitmask corresponding to all supported versions.
834 mono_arch_cpu_enumerate_simd_versions (void)
836 guint32 sse_opts = 0;
838 if (mono_hwcap_x86_has_sse1)
839 sse_opts |= SIMD_VERSION_SSE1;
841 if (mono_hwcap_x86_has_sse2)
842 sse_opts |= SIMD_VERSION_SSE2;
844 if (mono_hwcap_x86_has_sse3)
845 sse_opts |= SIMD_VERSION_SSE3;
847 if (mono_hwcap_x86_has_ssse3)
848 sse_opts |= SIMD_VERSION_SSSE3;
850 if (mono_hwcap_x86_has_sse41)
851 sse_opts |= SIMD_VERSION_SSE41;
853 if (mono_hwcap_x86_has_sse42)
854 sse_opts |= SIMD_VERSION_SSE42;
856 if (mono_hwcap_x86_has_sse4a)
857 sse_opts |= SIMD_VERSION_SSE4a;
863 * Determine whenever the trap whose info is in SIGINFO is caused by
867 mono_arch_is_int_overflow (void *sigctx, void *info)
872 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
874 ip = (guint8*)ctx.eip;
876 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
880 switch (x86_modrm_rm (ip [1])) {
900 g_assert_not_reached ();
912 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
917 for (i = 0; i < cfg->num_varinfo; i++) {
918 MonoInst *ins = cfg->varinfo [i];
919 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
922 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
925 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
926 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
929 /* we dont allocate I1 to registers because there is no simply way to sign extend
930 * 8bit quantities in caller saved registers on x86 */
931 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
932 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
933 g_assert (i == vmv->idx);
934 vars = g_list_prepend (vars, vmv);
938 vars = mono_varlist_sort (cfg, vars, 0);
944 mono_arch_get_global_int_regs (MonoCompile *cfg)
948 /* we can use 3 registers for global allocation */
949 regs = g_list_prepend (regs, (gpointer)X86_EBX);
950 regs = g_list_prepend (regs, (gpointer)X86_ESI);
951 regs = g_list_prepend (regs, (gpointer)X86_EDI);
957 * mono_arch_regalloc_cost:
959 * Return the cost, in number of memory references, of the action of
960 * allocating the variable VMV into a register during global register
964 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
966 MonoInst *ins = cfg->varinfo [vmv->idx];
968 if (cfg->method->save_lmf)
969 /* The register is already saved */
970 return (ins->opcode == OP_ARG) ? 1 : 0;
972 /* push+pop+possible load if it is an argument */
973 return (ins->opcode == OP_ARG) ? 3 : 2;
977 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
979 static int inited = FALSE;
980 static int count = 0;
982 if (cfg->arch.need_stack_frame_inited) {
983 g_assert (cfg->arch.need_stack_frame == flag);
987 cfg->arch.need_stack_frame = flag;
988 cfg->arch.need_stack_frame_inited = TRUE;
994 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
999 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
1003 needs_stack_frame (MonoCompile *cfg)
1005 MonoMethodSignature *sig;
1006 MonoMethodHeader *header;
1007 gboolean result = FALSE;
1009 #if defined(__APPLE__)
1010 /*OSX requires stack frame code to have the correct alignment. */
1014 if (cfg->arch.need_stack_frame_inited)
1015 return cfg->arch.need_stack_frame;
1017 header = cfg->header;
1018 sig = mono_method_signature (cfg->method);
1020 if (cfg->disable_omit_fp)
1022 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1024 else if (cfg->method->save_lmf)
1026 else if (cfg->stack_offset)
1028 else if (cfg->param_area)
1030 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1032 else if (header->num_clauses)
1034 else if (sig->param_count + sig->hasthis)
1036 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1038 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1039 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1042 set_needs_stack_frame (cfg, result);
1044 return cfg->arch.need_stack_frame;
1048 * Set var information according to the calling convention. X86 version.
1049 * The locals var stuff should most likely be split in another method.
1052 mono_arch_allocate_vars (MonoCompile *cfg)
1054 MonoMethodSignature *sig;
1055 MonoMethodHeader *header;
1057 guint32 locals_stack_size, locals_stack_align;
1062 header = cfg->header;
1063 sig = mono_method_signature (cfg->method);
1065 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1067 cfg->frame_reg = X86_EBP;
1070 /* Reserve space to save LMF and caller saved registers */
1072 if (cfg->method->save_lmf) {
1073 /* The LMF var is allocated normally */
1075 if (cfg->used_int_regs & (1 << X86_EBX)) {
1079 if (cfg->used_int_regs & (1 << X86_EDI)) {
1083 if (cfg->used_int_regs & (1 << X86_ESI)) {
1088 switch (cinfo->ret.storage) {
1089 case ArgValuetypeInReg:
1090 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1092 cfg->ret->opcode = OP_REGOFFSET;
1093 cfg->ret->inst_basereg = X86_EBP;
1094 cfg->ret->inst_offset = - offset;
1100 /* Allocate locals */
1101 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1102 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1103 char *mname = mono_method_full_name (cfg->method, TRUE);
1104 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1105 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1109 if (locals_stack_align) {
1110 int prev_offset = offset;
1112 offset += (locals_stack_align - 1);
1113 offset &= ~(locals_stack_align - 1);
1115 while (prev_offset < offset) {
1117 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1120 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1121 cfg->locals_max_stack_offset = - offset;
1123 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1124 * have locals larger than 8 bytes we need to make sure that
1125 * they have the appropriate offset.
1127 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1128 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1129 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1130 if (offsets [i] != -1) {
1131 MonoInst *inst = cfg->varinfo [i];
1132 inst->opcode = OP_REGOFFSET;
1133 inst->inst_basereg = X86_EBP;
1134 inst->inst_offset = - (offset + offsets [i]);
1135 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1138 offset += locals_stack_size;
1142 * Allocate arguments+return value
1145 switch (cinfo->ret.storage) {
1147 if (cfg->vret_addr) {
1149 * In the new IR, the cfg->vret_addr variable represents the
1150 * vtype return value.
1152 cfg->vret_addr->opcode = OP_REGOFFSET;
1153 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1154 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1155 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1156 printf ("vret_addr =");
1157 mono_print_ins (cfg->vret_addr);
1160 cfg->ret->opcode = OP_REGOFFSET;
1161 cfg->ret->inst_basereg = X86_EBP;
1162 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1165 case ArgValuetypeInReg:
1168 cfg->ret->opcode = OP_REGVAR;
1169 cfg->ret->inst_c0 = cinfo->ret.reg;
1170 cfg->ret->dreg = cinfo->ret.reg;
1173 case ArgOnFloatFpStack:
1174 case ArgOnDoubleFpStack:
1177 g_assert_not_reached ();
1180 if (sig->call_convention == MONO_CALL_VARARG) {
1181 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1182 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1185 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1186 ArgInfo *ainfo = &cinfo->args [i];
1187 inst = cfg->args [i];
1188 if (inst->opcode != OP_REGVAR) {
1189 inst->opcode = OP_REGOFFSET;
1190 inst->inst_basereg = X86_EBP;
1192 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1195 cfg->stack_offset = offset;
1199 mono_arch_create_vars (MonoCompile *cfg)
1202 MonoMethodSignature *sig;
1205 sig = mono_method_signature (cfg->method);
1207 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1210 if (cinfo->ret.storage == ArgValuetypeInReg)
1211 cfg->ret_var_is_local = TRUE;
1212 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (cfg, sig_ret))) {
1213 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1216 if (cfg->method->save_lmf)
1217 cfg->create_lmf_var = TRUE;
1219 cfg->arch_eh_jit_info = 1;
1223 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1224 * so we try to do it just once when we have multiple fp arguments in a row.
1225 * We don't use this mechanism generally because for int arguments the generated code
1226 * is slightly bigger and new generation cpus optimize away the dependency chains
1227 * created by push instructions on the esp value.
1228 * fp_arg_setup is the first argument in the execution sequence where the esp register
1231 static G_GNUC_UNUSED int
1232 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1237 for (; start_arg < sig->param_count; ++start_arg) {
1238 t = mini_type_get_underlying_type (NULL, sig->params [start_arg]);
1239 if (!t->byref && t->type == MONO_TYPE_R8) {
1240 fp_space += sizeof (double);
1241 *fp_arg_setup = start_arg;
1250 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1252 MonoMethodSignature *tmp_sig;
1256 * mono_ArgIterator_Setup assumes the signature cookie is
1257 * passed first and all the arguments which were before it are
1258 * passed on the stack after the signature. So compensate by
1259 * passing a different signature.
1261 tmp_sig = mono_metadata_signature_dup (call->signature);
1262 tmp_sig->param_count -= call->signature->sentinelpos;
1263 tmp_sig->sentinelpos = 0;
1264 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1266 if (cfg->compile_aot) {
1267 sig_reg = mono_alloc_ireg (cfg);
1268 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1269 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, sig_reg);
1271 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1277 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1282 LLVMCallInfo *linfo;
1283 MonoType *t, *sig_ret;
1285 n = sig->param_count + sig->hasthis;
1287 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1290 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1293 * LLVM always uses the native ABI while we use our own ABI, the
1294 * only difference is the handling of vtypes:
1295 * - we only pass/receive them in registers in some cases, and only
1296 * in 1 or 2 integer registers.
1298 if (cinfo->ret.storage == ArgValuetypeInReg) {
1300 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1301 cfg->disable_llvm = TRUE;
1305 cfg->exception_message = g_strdup ("vtype ret in call");
1306 cfg->disable_llvm = TRUE;
1308 linfo->ret.storage = LLVMArgVtypeInReg;
1309 for (j = 0; j < 2; ++j)
1310 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1314 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage == ArgInIReg) {
1315 /* Vtype returned using a hidden argument */
1316 linfo->ret.storage = LLVMArgVtypeRetAddr;
1317 linfo->vret_arg_index = cinfo->vret_arg_index;
1320 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage != ArgInIReg) {
1322 cfg->exception_message = g_strdup ("vtype ret in call");
1323 cfg->disable_llvm = TRUE;
1326 for (i = 0; i < n; ++i) {
1327 ainfo = cinfo->args + i;
1329 if (i >= sig->hasthis)
1330 t = sig->params [i - sig->hasthis];
1332 t = &mono_defaults.int_class->byval_arg;
1334 linfo->args [i].storage = LLVMArgNone;
1336 switch (ainfo->storage) {
1338 linfo->args [i].storage = LLVMArgInIReg;
1340 case ArgInDoubleSSEReg:
1341 case ArgInFloatSSEReg:
1342 linfo->args [i].storage = LLVMArgInFPReg;
1345 if (mini_type_is_vtype (cfg, t)) {
1346 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1347 /* LLVM seems to allocate argument space for empty structures too */
1348 linfo->args [i].storage = LLVMArgNone;
1350 linfo->args [i].storage = LLVMArgVtypeByVal;
1352 linfo->args [i].storage = LLVMArgInIReg;
1354 if (t->type == MONO_TYPE_R4)
1355 linfo->args [i].storage = LLVMArgInFPReg;
1356 else if (t->type == MONO_TYPE_R8)
1357 linfo->args [i].storage = LLVMArgInFPReg;
1361 case ArgValuetypeInReg:
1363 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1364 cfg->disable_llvm = TRUE;
1368 cfg->exception_message = g_strdup ("vtype arg");
1369 cfg->disable_llvm = TRUE;
1371 linfo->args [i].storage = LLVMArgVtypeInReg;
1372 for (j = 0; j < 2; ++j)
1373 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1377 linfo->args [i].storage = LLVMArgGSharedVt;
1380 cfg->exception_message = g_strdup ("ainfo->storage");
1381 cfg->disable_llvm = TRUE;
1391 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1393 if (cfg->compute_gc_maps) {
1396 /* On x86, the offsets are from the sp value before the start of the call sequence */
1398 t = &mono_defaults.int_class->byval_arg;
1399 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1404 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1408 MonoMethodSignature *sig;
1411 int sentinelpos = 0, sp_offset = 0;
1413 sig = call->signature;
1414 n = sig->param_count + sig->hasthis;
1417 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1419 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1420 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1422 if (cinfo->need_stack_align) {
1423 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1424 arg->dreg = X86_ESP;
1425 arg->sreg1 = X86_ESP;
1426 arg->inst_imm = cinfo->stack_align_amount;
1427 MONO_ADD_INS (cfg->cbb, arg);
1428 for (i = 0; i < cinfo->stack_align_amount; i += sizeof (mgreg_t)) {
1431 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1435 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1436 if (cinfo->ret.storage == ArgValuetypeInReg) {
1438 * Tell the JIT to use a more efficient calling convention: call using
1439 * OP_CALL, compute the result location after the call, and save the
1442 call->vret_in_reg = TRUE;
1444 NULLIFY_INS (call->vret_var);
1448 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1450 /* Handle the case where there are no implicit arguments */
1451 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1452 emit_sig_cookie (cfg, call, cinfo);
1454 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1457 /* Arguments are pushed in the reverse order */
1458 for (i = n - 1; i >= 0; i --) {
1459 ArgInfo *ainfo = cinfo->args + i;
1460 MonoType *orig_type, *t;
1463 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1464 /* Push the vret arg before the first argument */
1466 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1467 vtarg->type = STACK_MP;
1468 vtarg->sreg1 = call->vret_var->dreg;
1469 MONO_ADD_INS (cfg->cbb, vtarg);
1471 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1474 if (i >= sig->hasthis)
1475 t = sig->params [i - sig->hasthis];
1477 t = &mono_defaults.int_class->byval_arg;
1479 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1481 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1483 in = call->args [i];
1484 arg->cil_code = in->cil_code;
1485 arg->sreg1 = in->dreg;
1486 arg->type = in->type;
1488 g_assert (in->dreg != -1);
1490 if (ainfo->storage == ArgGSharedVt) {
1491 arg->opcode = OP_OUTARG_VT;
1492 arg->sreg1 = in->dreg;
1493 arg->klass = in->klass;
1494 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1495 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1497 MONO_ADD_INS (cfg->cbb, arg);
1498 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1502 g_assert (in->klass);
1504 if (t->type == MONO_TYPE_TYPEDBYREF) {
1505 size = sizeof (MonoTypedRef);
1506 align = sizeof (gpointer);
1509 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1513 arg->opcode = OP_OUTARG_VT;
1514 arg->sreg1 = in->dreg;
1515 arg->klass = in->klass;
1516 arg->backend.size = size;
1517 arg->inst_p0 = call;
1518 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1519 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1521 MONO_ADD_INS (cfg->cbb, arg);
1522 if (ainfo->storage != ArgValuetypeInReg) {
1524 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1530 switch (ainfo->storage) {
1532 arg->opcode = OP_X86_PUSH;
1534 if (t->type == MONO_TYPE_R4) {
1535 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1536 arg->opcode = OP_STORER4_MEMBASE_REG;
1537 arg->inst_destbasereg = X86_ESP;
1538 arg->inst_offset = 0;
1540 } else if (t->type == MONO_TYPE_R8) {
1541 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1542 arg->opcode = OP_STORER8_MEMBASE_REG;
1543 arg->inst_destbasereg = X86_ESP;
1544 arg->inst_offset = 0;
1546 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1548 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1554 arg->opcode = OP_MOVE;
1555 arg->dreg = ainfo->reg;
1559 g_assert_not_reached ();
1562 MONO_ADD_INS (cfg->cbb, arg);
1564 sp_offset += argsize;
1566 if (cfg->compute_gc_maps) {
1568 /* FIXME: The == STACK_OBJ check might be fragile ? */
1569 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1571 if (call->need_unbox_trampoline)
1572 /* The unbox trampoline transforms this into a managed pointer */
1573 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.int_class->this_arg);
1575 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.object_class->byval_arg);
1577 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1581 for (j = 0; j < argsize; j += 4)
1582 emit_gc_param_slot_def (cfg, sp_offset - j, NULL);
1587 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1588 /* Emit the signature cookie just before the implicit arguments */
1589 emit_sig_cookie (cfg, call, cinfo);
1591 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1595 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1598 if (cinfo->ret.storage == ArgValuetypeInReg) {
1601 else if (cinfo->ret.storage == ArgInIReg) {
1603 /* The return address is passed in a register */
1604 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1605 vtarg->sreg1 = call->inst.dreg;
1606 vtarg->dreg = mono_alloc_ireg (cfg);
1607 MONO_ADD_INS (cfg->cbb, vtarg);
1609 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1610 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1612 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1613 vtarg->type = STACK_MP;
1614 vtarg->sreg1 = call->vret_var->dreg;
1615 MONO_ADD_INS (cfg->cbb, vtarg);
1617 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1620 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1621 if (cinfo->ret.storage != ArgValuetypeInReg)
1622 cinfo->stack_usage -= 4;
1625 call->stack_usage = cinfo->stack_usage;
1626 call->stack_align_amount = cinfo->stack_align_amount;
1627 cfg->arch.param_area_size = MAX (cfg->arch.param_area_size, sp_offset);
1631 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1633 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1634 ArgInfo *ainfo = ins->inst_p1;
1636 int size = ins->backend.size;
1638 if (ainfo->storage == ArgValuetypeInReg) {
1639 int dreg = mono_alloc_ireg (cfg);
1642 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1645 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1648 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1652 g_assert_not_reached ();
1654 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1657 if (cfg->gsharedvt && mini_is_gsharedvt_klass (cfg, ins->klass)) {
1659 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1660 arg->sreg1 = src->dreg;
1661 MONO_ADD_INS (cfg->cbb, arg);
1662 } else if (size <= 4) {
1663 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1664 arg->sreg1 = src->dreg;
1666 MONO_ADD_INS (cfg->cbb, arg);
1667 } else if (size <= 20) {
1668 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1669 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1671 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1672 arg->inst_basereg = src->dreg;
1673 arg->inst_offset = 0;
1674 arg->inst_imm = size;
1676 MONO_ADD_INS (cfg->cbb, arg);
1682 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1684 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1687 if (ret->type == MONO_TYPE_R4) {
1688 if (COMPILE_LLVM (cfg))
1689 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1692 } else if (ret->type == MONO_TYPE_R8) {
1693 if (COMPILE_LLVM (cfg))
1694 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1697 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1698 if (COMPILE_LLVM (cfg))
1699 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1701 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1702 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1708 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1712 * Allow tracing to work with this interface (with an optional argument)
1715 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1719 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1720 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1722 /* if some args are passed in registers, we need to save them here */
1723 x86_push_reg (code, X86_EBP);
1725 if (cfg->compile_aot) {
1726 x86_push_imm (code, cfg->method);
1727 x86_mov_reg_imm (code, X86_EAX, func);
1728 x86_call_reg (code, X86_EAX);
1730 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1731 x86_push_imm (code, cfg->method);
1732 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1733 x86_call_code (code, 0);
1735 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1749 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1752 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1753 MonoMethod *method = cfg->method;
1754 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1756 switch (ret_type->type) {
1757 case MONO_TYPE_VOID:
1758 /* special case string .ctor icall */
1759 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1760 save_mode = SAVE_EAX;
1761 stack_usage = enable_arguments ? 8 : 4;
1763 save_mode = SAVE_NONE;
1767 save_mode = SAVE_EAX_EDX;
1768 stack_usage = enable_arguments ? 16 : 8;
1772 save_mode = SAVE_FP;
1773 stack_usage = enable_arguments ? 16 : 8;
1775 case MONO_TYPE_GENERICINST:
1776 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1777 save_mode = SAVE_EAX;
1778 stack_usage = enable_arguments ? 8 : 4;
1782 case MONO_TYPE_VALUETYPE:
1783 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1784 save_mode = SAVE_STRUCT;
1785 stack_usage = enable_arguments ? 4 : 0;
1788 save_mode = SAVE_EAX;
1789 stack_usage = enable_arguments ? 8 : 4;
1793 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1795 switch (save_mode) {
1797 x86_push_reg (code, X86_EDX);
1798 x86_push_reg (code, X86_EAX);
1799 if (enable_arguments) {
1800 x86_push_reg (code, X86_EDX);
1801 x86_push_reg (code, X86_EAX);
1806 x86_push_reg (code, X86_EAX);
1807 if (enable_arguments) {
1808 x86_push_reg (code, X86_EAX);
1813 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1814 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1815 if (enable_arguments) {
1816 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1817 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1822 if (enable_arguments) {
1823 x86_push_membase (code, X86_EBP, 8);
1832 if (cfg->compile_aot) {
1833 x86_push_imm (code, method);
1834 x86_mov_reg_imm (code, X86_EAX, func);
1835 x86_call_reg (code, X86_EAX);
1837 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1838 x86_push_imm (code, method);
1839 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1840 x86_call_code (code, 0);
1843 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1845 switch (save_mode) {
1847 x86_pop_reg (code, X86_EAX);
1848 x86_pop_reg (code, X86_EDX);
1851 x86_pop_reg (code, X86_EAX);
1854 x86_fld_membase (code, X86_ESP, 0, TRUE);
1855 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1862 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1867 #define EMIT_COND_BRANCH(ins,cond,sign) \
1868 if (ins->inst_true_bb->native_offset) { \
1869 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1871 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1872 if ((cfg->opt & MONO_OPT_BRANCH) && \
1873 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1874 x86_branch8 (code, cond, 0, sign); \
1876 x86_branch32 (code, cond, 0, sign); \
1880 * Emit an exception if condition is fail and
1881 * if possible do a directly branch to target
1883 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1885 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1886 if (tins == NULL) { \
1887 mono_add_patch_info (cfg, code - cfg->native_code, \
1888 MONO_PATCH_INFO_EXC, exc_name); \
1889 x86_branch32 (code, cond, 0, signed); \
1891 EMIT_COND_BRANCH (tins, cond, signed); \
1895 #define EMIT_FPCOMPARE(code) do { \
1896 x86_fcompp (code); \
1897 x86_fnstsw (code); \
1902 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1904 gboolean needs_paddings = TRUE;
1906 MonoJumpInfo *jinfo = NULL;
1908 if (cfg->abs_patches) {
1909 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1910 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1911 needs_paddings = FALSE;
1914 if (cfg->compile_aot)
1915 needs_paddings = FALSE;
1916 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1917 This is required for code patching to be safe on SMP machines.
1919 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1920 #ifndef __native_client_codegen__
1921 if (needs_paddings && pad_size)
1922 x86_padding (code, 4 - pad_size);
1925 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1926 x86_call_code (code, 0);
1931 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1934 * mono_peephole_pass_1:
1936 * Perform peephole opts which should/can be performed before local regalloc
1939 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1943 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1944 MonoInst *last_ins = ins->prev;
1946 switch (ins->opcode) {
1949 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1951 * X86_LEA is like ADD, but doesn't have the
1952 * sreg1==dreg restriction.
1954 ins->opcode = OP_X86_LEA_MEMBASE;
1955 ins->inst_basereg = ins->sreg1;
1956 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1957 ins->opcode = OP_X86_INC_REG;
1961 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1962 ins->opcode = OP_X86_LEA_MEMBASE;
1963 ins->inst_basereg = ins->sreg1;
1964 ins->inst_imm = -ins->inst_imm;
1965 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1966 ins->opcode = OP_X86_DEC_REG;
1968 case OP_COMPARE_IMM:
1969 case OP_ICOMPARE_IMM:
1970 /* OP_COMPARE_IMM (reg, 0)
1972 * OP_X86_TEST_NULL (reg)
1975 ins->opcode = OP_X86_TEST_NULL;
1977 case OP_X86_COMPARE_MEMBASE_IMM:
1979 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1980 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1982 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1983 * OP_COMPARE_IMM reg, imm
1985 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1987 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1988 ins->inst_basereg == last_ins->inst_destbasereg &&
1989 ins->inst_offset == last_ins->inst_offset) {
1990 ins->opcode = OP_COMPARE_IMM;
1991 ins->sreg1 = last_ins->sreg1;
1993 /* check if we can remove cmp reg,0 with test null */
1995 ins->opcode = OP_X86_TEST_NULL;
1999 case OP_X86_PUSH_MEMBASE:
2000 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
2001 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2002 ins->inst_basereg == last_ins->inst_destbasereg &&
2003 ins->inst_offset == last_ins->inst_offset) {
2004 ins->opcode = OP_X86_PUSH;
2005 ins->sreg1 = last_ins->sreg1;
2010 mono_peephole_ins (bb, ins);
2015 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2019 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2020 switch (ins->opcode) {
2022 /* reg = 0 -> XOR (reg, reg) */
2023 /* XOR sets cflags on x86, so we cant do it always */
2024 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2027 ins->opcode = OP_IXOR;
2028 ins->sreg1 = ins->dreg;
2029 ins->sreg2 = ins->dreg;
2032 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2033 * since it takes 3 bytes instead of 7.
2035 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2036 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2037 ins2->opcode = OP_STORE_MEMBASE_REG;
2038 ins2->sreg1 = ins->dreg;
2040 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2041 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2042 ins2->sreg1 = ins->dreg;
2044 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2045 /* Continue iteration */
2054 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2055 ins->opcode = OP_X86_INC_REG;
2059 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2060 ins->opcode = OP_X86_DEC_REG;
2064 mono_peephole_ins (bb, ins);
2069 * mono_arch_lowering_pass:
2071 * Converts complex opcodes into simpler ones so that each IR instruction
2072 * corresponds to one machine instruction.
2075 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2077 MonoInst *ins, *next;
2080 * FIXME: Need to add more instructions, but the current machine
2081 * description can't model some parts of the composite instructions like
2084 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2085 switch (ins->opcode) {
2088 case OP_IDIV_UN_IMM:
2089 case OP_IREM_UN_IMM:
2091 * Keep the cases where we could generated optimized code, otherwise convert
2092 * to the non-imm variant.
2094 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2096 mono_decompose_op_imm (cfg, bb, ins);
2103 bb->max_vreg = cfg->next_vreg;
2107 branch_cc_table [] = {
2108 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2109 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2110 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2113 /* Maps CMP_... constants to X86_CC_... constants */
2116 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2117 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2121 cc_signed_table [] = {
2122 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2123 FALSE, FALSE, FALSE, FALSE
2126 static unsigned char*
2127 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2129 #define XMM_TEMP_REG 0
2130 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2131 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2132 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2133 /* optimize by assigning a local var for this use so we avoid
2134 * the stack manipulations */
2135 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2136 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2137 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2138 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2139 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2141 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2143 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2146 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2147 x86_fnstcw_membase(code, X86_ESP, 0);
2148 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2149 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2150 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2151 x86_fldcw_membase (code, X86_ESP, 2);
2153 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2154 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2155 x86_pop_reg (code, dreg);
2156 /* FIXME: need the high register
2157 * x86_pop_reg (code, dreg_high);
2160 x86_push_reg (code, X86_EAX); // SP = SP - 4
2161 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2162 x86_pop_reg (code, dreg);
2164 x86_fldcw_membase (code, X86_ESP, 0);
2165 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2168 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2170 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2174 static unsigned char*
2175 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2177 int sreg = tree->sreg1;
2178 int need_touch = FALSE;
2180 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2189 * If requested stack size is larger than one page,
2190 * perform stack-touch operation
2193 * Generate stack probe code.
2194 * Under Windows, it is necessary to allocate one page at a time,
2195 * "touching" stack after each successful sub-allocation. This is
2196 * because of the way stack growth is implemented - there is a
2197 * guard page before the lowest stack page that is currently commited.
2198 * Stack normally grows sequentially so OS traps access to the
2199 * guard page and commits more pages when needed.
2201 x86_test_reg_imm (code, sreg, ~0xFFF);
2202 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2204 br[2] = code; /* loop */
2205 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2206 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2209 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2210 * that follows only initializes the last part of the area.
2212 /* Same as the init code below with size==0x1000 */
2213 if (tree->flags & MONO_INST_INIT) {
2214 x86_push_reg (code, X86_EAX);
2215 x86_push_reg (code, X86_ECX);
2216 x86_push_reg (code, X86_EDI);
2217 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2218 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2219 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2221 x86_prefix (code, X86_REP_PREFIX);
2223 x86_pop_reg (code, X86_EDI);
2224 x86_pop_reg (code, X86_ECX);
2225 x86_pop_reg (code, X86_EAX);
2228 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2229 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2230 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2231 x86_patch (br[3], br[2]);
2232 x86_test_reg_reg (code, sreg, sreg);
2233 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2234 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2236 br[1] = code; x86_jump8 (code, 0);
2238 x86_patch (br[0], code);
2239 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2240 x86_patch (br[1], code);
2241 x86_patch (br[4], code);
2244 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2246 if (tree->flags & MONO_INST_INIT) {
2248 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2249 x86_push_reg (code, X86_EAX);
2252 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2253 x86_push_reg (code, X86_ECX);
2256 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2257 x86_push_reg (code, X86_EDI);
2261 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2262 if (sreg != X86_ECX)
2263 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2264 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2266 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2268 x86_prefix (code, X86_REP_PREFIX);
2271 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2272 x86_pop_reg (code, X86_EDI);
2273 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2274 x86_pop_reg (code, X86_ECX);
2275 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2276 x86_pop_reg (code, X86_EAX);
2283 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2285 /* Move return value to the target register */
2286 switch (ins->opcode) {
2289 case OP_CALL_MEMBASE:
2290 if (ins->dreg != X86_EAX)
2291 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2301 static int tls_gs_offset;
2305 mono_x86_have_tls_get (void)
2308 static gboolean have_tls_get = FALSE;
2309 static gboolean inited = FALSE;
2313 return have_tls_get;
2315 ins = (guint32*)pthread_getspecific;
2317 * We're looking for these two instructions:
2319 * mov 0x4(%esp),%eax
2320 * mov %gs:[offset](,%eax,4),%eax
2322 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2323 tls_gs_offset = ins [2];
2327 return have_tls_get;
2328 #elif defined(TARGET_ANDROID)
2336 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2338 #if defined(__APPLE__)
2339 x86_prefix (code, X86_GS_PREFIX);
2340 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2341 #elif defined(TARGET_WIN32)
2342 g_assert_not_reached ();
2344 x86_prefix (code, X86_GS_PREFIX);
2345 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2351 * mono_x86_emit_tls_get:
2352 * @code: buffer to store code to
2353 * @dreg: hard register where to place the result
2354 * @tls_offset: offset info
2356 * mono_x86_emit_tls_get emits in @code the native code that puts in
2357 * the dreg register the item in the thread local storage identified
2360 * Returns: a pointer to the end of the stored code
2363 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2365 #if defined(__APPLE__)
2366 x86_prefix (code, X86_GS_PREFIX);
2367 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2368 #elif defined(TARGET_WIN32)
2370 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2371 * Journal and/or a disassembly of the TlsGet () function.
2373 g_assert (tls_offset < 64);
2374 x86_prefix (code, X86_FS_PREFIX);
2375 x86_mov_reg_mem (code, dreg, 0x18, 4);
2376 /* Dunno what this does but TlsGetValue () contains it */
2377 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2378 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2380 if (optimize_for_xen) {
2381 x86_prefix (code, X86_GS_PREFIX);
2382 x86_mov_reg_mem (code, dreg, 0, 4);
2383 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2385 x86_prefix (code, X86_GS_PREFIX);
2386 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2393 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2395 #if defined(__APPLE__)
2396 // FIXME: tls_gs_offset can change too, do these when calculating the tls offset
2397 if (dreg != offset_reg)
2398 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2399 x86_shift_reg_imm (code, X86_SHL, dreg, 2);
2401 x86_alu_reg_imm (code, X86_ADD, dreg, tls_gs_offset);
2402 x86_prefix (code, X86_GS_PREFIX);
2403 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2404 #elif defined(__linux__)
2405 if (dreg != offset_reg)
2406 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2407 x86_prefix (code, X86_GS_PREFIX);
2408 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2411 g_assert_not_reached ();
2417 * emit_load_volatile_arguments:
2419 * Load volatile arguments from the stack to the original input registers.
2420 * Required before a tail call.
2423 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2425 MonoMethod *method = cfg->method;
2426 MonoMethodSignature *sig;
2431 /* FIXME: Generate intermediate code instead */
2433 sig = mono_method_signature (method);
2435 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2437 /* This is the opposite of the code in emit_prolog */
2439 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2440 ArgInfo *ainfo = cinfo->args + i;
2442 inst = cfg->args [i];
2444 if (sig->hasthis && (i == 0))
2445 arg_type = &mono_defaults.object_class->byval_arg;
2447 arg_type = sig->params [i - sig->hasthis];
2450 * On x86, the arguments are either in their original stack locations, or in
2453 if (inst->opcode == OP_REGVAR) {
2454 g_assert (ainfo->storage == ArgOnStack);
2456 x86_mov_membase_reg (code, X86_EBP, inst->inst_offset, inst->dreg, 4);
2466 * Emit code to initialize an LMF structure at LMF_OFFSET.
2469 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2471 /* save all caller saved regs */
2472 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2473 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx));
2474 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2475 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi));
2476 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2477 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi));
2478 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2480 /* save the current IP */
2481 if (cfg->compile_aot) {
2482 /* This pushes the current ip */
2483 x86_call_imm (code, 0);
2484 x86_pop_reg (code, X86_EAX);
2486 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2487 x86_mov_reg_imm (code, X86_EAX, 0);
2489 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2491 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2492 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2493 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2494 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2495 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2496 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2497 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2498 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2499 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2507 * Emit code to push an LMF structure on the LMF stack.
2510 emit_push_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
2512 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
2514 * Optimized version which uses the mono_lmf TLS variable instead of indirection
2515 * through the mono_lmf_addr TLS variable.
2517 /* %eax = previous_lmf */
2518 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_tls_offset);
2519 /* set previous_lmf */
2520 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), X86_EAX, sizeof (mgreg_t));
2521 x86_lea_membase (code, X86_EAX, cfg->frame_reg, lmf_offset);
2523 code = mono_x86_emit_tls_set (code, X86_EAX, lmf_tls_offset);
2525 /* get the address of lmf for the current thread */
2527 * This is performance critical so we try to use some tricks to make
2530 gboolean have_fastpath = FALSE;
2533 if (jit_tls_offset != -1) {
2534 code = mono_x86_emit_tls_get (code, X86_EAX, jit_tls_offset);
2535 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
2536 have_fastpath = TRUE;
2539 if (lmf_addr_tls_offset != -1) {
2540 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
2541 have_fastpath = TRUE;
2544 if (!have_fastpath) {
2545 if (cfg->compile_aot)
2546 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
2547 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
2551 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), X86_EAX, sizeof (mgreg_t));
2552 /* save previous_lmf */
2553 x86_mov_reg_membase (code, X86_ECX, X86_EAX, 0, sizeof (mgreg_t));
2554 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), X86_ECX, sizeof (mgreg_t));
2556 x86_lea_membase (code, X86_ECX, cfg->frame_reg, lmf_offset);
2557 x86_mov_membase_reg (code, X86_EAX, 0, X86_ECX, sizeof (mgreg_t));
2565 * Emit code to pop an LMF structure from the LMF stack.
2566 * Preserves the return registers.
2569 emit_pop_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
2571 MonoMethodSignature *sig = mono_method_signature (cfg->method);
2574 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
2576 * Optimized version which uses the mono_lmf TLS variable instead of indirection
2577 * through the mono_lmf_addr TLS variable.
2579 /* reg = previous_lmf */
2580 x86_mov_reg_membase (code, X86_ECX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
2582 /* lmf = previous_lmf */
2583 code = mono_x86_emit_tls_set (code, X86_ECX, lmf_tls_offset);
2585 /* Find a spare register */
2586 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
2589 prev_lmf_reg = X86_EDI;
2590 cfg->used_int_regs |= (1 << X86_EDI);
2593 prev_lmf_reg = X86_EDX;
2597 /* reg = previous_lmf */
2598 x86_mov_reg_membase (code, prev_lmf_reg, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
2601 x86_mov_reg_membase (code, X86_ECX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
2603 /* *(lmf) = previous_lmf */
2604 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
2609 #define REAL_PRINT_REG(text,reg) \
2610 mono_assert (reg >= 0); \
2611 x86_push_reg (code, X86_EAX); \
2612 x86_push_reg (code, X86_EDX); \
2613 x86_push_reg (code, X86_ECX); \
2614 x86_push_reg (code, reg); \
2615 x86_push_imm (code, reg); \
2616 x86_push_imm (code, text " %d %p\n"); \
2617 x86_mov_reg_imm (code, X86_EAX, printf); \
2618 x86_call_reg (code, X86_EAX); \
2619 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2620 x86_pop_reg (code, X86_ECX); \
2621 x86_pop_reg (code, X86_EDX); \
2622 x86_pop_reg (code, X86_EAX);
2624 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2625 #ifdef __native__client_codegen__
2626 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2629 /* benchmark and set based on cpu */
2630 #define LOOP_ALIGNMENT 8
2631 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2635 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2640 guint8 *code = cfg->native_code + cfg->code_len;
2643 if (cfg->opt & MONO_OPT_LOOP) {
2644 int pad, align = LOOP_ALIGNMENT;
2645 /* set alignment depending on cpu */
2646 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2648 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2649 x86_padding (code, pad);
2650 cfg->code_len += pad;
2651 bb->native_offset = cfg->code_len;
2654 #ifdef __native_client_codegen__
2656 /* For Native Client, all indirect call/jump targets must be */
2657 /* 32-byte aligned. Exception handler blocks are jumped to */
2658 /* indirectly as well. */
2659 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2660 (bb->flags & BB_EXCEPTION_HANDLER);
2662 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2663 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2664 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2665 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2666 cfg->code_len += pad;
2667 bb->native_offset = cfg->code_len;
2670 #endif /* __native_client_codegen__ */
2671 if (cfg->verbose_level > 2)
2672 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2674 cpos = bb->max_offset;
2676 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2677 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2678 g_assert (!cfg->compile_aot);
2681 cov->data [bb->dfn].cil_code = bb->cil_code;
2682 /* this is not thread save, but good enough */
2683 x86_inc_mem (code, &cov->data [bb->dfn].count);
2686 offset = code - cfg->native_code;
2688 mono_debug_open_block (cfg, bb, offset);
2690 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2691 x86_breakpoint (code);
2693 MONO_BB_FOR_EACH_INS (bb, ins) {
2694 offset = code - cfg->native_code;
2696 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2698 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2700 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2701 cfg->code_size *= 2;
2702 cfg->native_code = mono_realloc_native_code(cfg);
2703 code = cfg->native_code + offset;
2704 cfg->stat_code_reallocs++;
2707 if (cfg->debug_info)
2708 mono_debug_record_line_number (cfg, ins, offset);
2710 switch (ins->opcode) {
2712 x86_mul_reg (code, ins->sreg2, TRUE);
2715 x86_mul_reg (code, ins->sreg2, FALSE);
2717 case OP_X86_SETEQ_MEMBASE:
2718 case OP_X86_SETNE_MEMBASE:
2719 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2720 ins->inst_basereg, ins->inst_offset, TRUE);
2722 case OP_STOREI1_MEMBASE_IMM:
2723 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2725 case OP_STOREI2_MEMBASE_IMM:
2726 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2728 case OP_STORE_MEMBASE_IMM:
2729 case OP_STOREI4_MEMBASE_IMM:
2730 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2732 case OP_STOREI1_MEMBASE_REG:
2733 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2735 case OP_STOREI2_MEMBASE_REG:
2736 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2738 case OP_STORE_MEMBASE_REG:
2739 case OP_STOREI4_MEMBASE_REG:
2740 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2742 case OP_STORE_MEM_IMM:
2743 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2746 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2750 /* These are created by the cprop pass so they use inst_imm as the source */
2751 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2754 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2757 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2759 case OP_LOAD_MEMBASE:
2760 case OP_LOADI4_MEMBASE:
2761 case OP_LOADU4_MEMBASE:
2762 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2764 case OP_LOADU1_MEMBASE:
2765 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2767 case OP_LOADI1_MEMBASE:
2768 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2770 case OP_LOADU2_MEMBASE:
2771 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2773 case OP_LOADI2_MEMBASE:
2774 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2776 case OP_ICONV_TO_I1:
2778 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2780 case OP_ICONV_TO_I2:
2782 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2784 case OP_ICONV_TO_U1:
2785 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2787 case OP_ICONV_TO_U2:
2788 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2792 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2794 case OP_COMPARE_IMM:
2795 case OP_ICOMPARE_IMM:
2796 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2798 case OP_X86_COMPARE_MEMBASE_REG:
2799 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2801 case OP_X86_COMPARE_MEMBASE_IMM:
2802 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2804 case OP_X86_COMPARE_MEMBASE8_IMM:
2805 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2807 case OP_X86_COMPARE_REG_MEMBASE:
2808 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2810 case OP_X86_COMPARE_MEM_IMM:
2811 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2813 case OP_X86_TEST_NULL:
2814 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2816 case OP_X86_ADD_MEMBASE_IMM:
2817 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2819 case OP_X86_ADD_REG_MEMBASE:
2820 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2822 case OP_X86_SUB_MEMBASE_IMM:
2823 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2825 case OP_X86_SUB_REG_MEMBASE:
2826 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2828 case OP_X86_AND_MEMBASE_IMM:
2829 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2831 case OP_X86_OR_MEMBASE_IMM:
2832 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2834 case OP_X86_XOR_MEMBASE_IMM:
2835 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2837 case OP_X86_ADD_MEMBASE_REG:
2838 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2840 case OP_X86_SUB_MEMBASE_REG:
2841 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2843 case OP_X86_AND_MEMBASE_REG:
2844 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2846 case OP_X86_OR_MEMBASE_REG:
2847 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2849 case OP_X86_XOR_MEMBASE_REG:
2850 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2852 case OP_X86_INC_MEMBASE:
2853 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2855 case OP_X86_INC_REG:
2856 x86_inc_reg (code, ins->dreg);
2858 case OP_X86_DEC_MEMBASE:
2859 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2861 case OP_X86_DEC_REG:
2862 x86_dec_reg (code, ins->dreg);
2864 case OP_X86_MUL_REG_MEMBASE:
2865 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2867 case OP_X86_AND_REG_MEMBASE:
2868 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2870 case OP_X86_OR_REG_MEMBASE:
2871 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2873 case OP_X86_XOR_REG_MEMBASE:
2874 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2877 x86_breakpoint (code);
2879 case OP_RELAXED_NOP:
2880 x86_prefix (code, X86_REP_PREFIX);
2888 case OP_DUMMY_STORE:
2889 case OP_NOT_REACHED:
2892 case OP_SEQ_POINT: {
2895 if (cfg->compile_aot)
2899 * Read from the single stepping trigger page. This will cause a
2900 * SIGSEGV when single stepping is enabled.
2901 * We do this _before_ the breakpoint, so single stepping after
2902 * a breakpoint is hit will step to the next IL offset.
2904 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2905 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2907 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2910 * A placeholder for a possible breakpoint inserted by
2911 * mono_arch_set_breakpoint ().
2913 for (i = 0; i < 6; ++i)
2916 * Add an additional nop so skipping the bp doesn't cause the ip to point
2917 * to another IL offset.
2925 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2929 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2934 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2938 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2943 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2947 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2952 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2956 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2959 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2963 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2967 #if defined( __native_client_codegen__ )
2968 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2969 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2972 * The code is the same for div/rem, the allocator will allocate dreg
2973 * to RAX/RDX as appropriate.
2975 if (ins->sreg2 == X86_EDX) {
2976 /* cdq clobbers this */
2977 x86_push_reg (code, ins->sreg2);
2979 x86_div_membase (code, X86_ESP, 0, TRUE);
2980 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2983 x86_div_reg (code, ins->sreg2, TRUE);
2988 #if defined( __native_client_codegen__ )
2989 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2990 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2992 if (ins->sreg2 == X86_EDX) {
2993 x86_push_reg (code, ins->sreg2);
2994 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2995 x86_div_membase (code, X86_ESP, 0, FALSE);
2996 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2998 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2999 x86_div_reg (code, ins->sreg2, FALSE);
3003 #if defined( __native_client_codegen__ )
3004 if (ins->inst_imm == 0) {
3005 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
3006 x86_jump32 (code, 0);
3010 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
3012 x86_div_reg (code, ins->sreg2, TRUE);
3015 int power = mono_is_power_of_two (ins->inst_imm);
3017 g_assert (ins->sreg1 == X86_EAX);
3018 g_assert (ins->dreg == X86_EAX);
3019 g_assert (power >= 0);
3022 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
3024 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
3026 * If the divident is >= 0, this does not nothing. If it is positive, it
3027 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
3029 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
3030 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
3031 } else if (power == 0) {
3032 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3034 /* Based on gcc code */
3036 /* Add compensation for negative dividents */
3038 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
3039 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
3040 /* Compute remainder */
3041 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
3042 /* Remove compensation */
3043 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
3048 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3052 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3055 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3059 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3062 g_assert (ins->sreg2 == X86_ECX);
3063 x86_shift_reg (code, X86_SHL, ins->dreg);
3066 g_assert (ins->sreg2 == X86_ECX);
3067 x86_shift_reg (code, X86_SAR, ins->dreg);
3071 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3074 case OP_ISHR_UN_IMM:
3075 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3078 g_assert (ins->sreg2 == X86_ECX);
3079 x86_shift_reg (code, X86_SHR, ins->dreg);
3083 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3086 guint8 *jump_to_end;
3088 /* handle shifts below 32 bits */
3089 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
3090 x86_shift_reg (code, X86_SHL, ins->sreg1);
3092 x86_test_reg_imm (code, X86_ECX, 32);
3093 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3095 /* handle shift over 32 bit */
3096 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3097 x86_clear_reg (code, ins->sreg1);
3099 x86_patch (jump_to_end, code);
3103 guint8 *jump_to_end;
3105 /* handle shifts below 32 bits */
3106 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3107 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
3109 x86_test_reg_imm (code, X86_ECX, 32);
3110 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3112 /* handle shifts over 31 bits */
3113 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3114 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
3116 x86_patch (jump_to_end, code);
3120 guint8 *jump_to_end;
3122 /* handle shifts below 32 bits */
3123 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3124 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
3126 x86_test_reg_imm (code, X86_ECX, 32);
3127 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3129 /* handle shifts over 31 bits */
3130 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3131 x86_clear_reg (code, ins->backend.reg3);
3133 x86_patch (jump_to_end, code);
3137 if (ins->inst_imm >= 32) {
3138 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3139 x86_clear_reg (code, ins->sreg1);
3140 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
3142 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
3143 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
3147 if (ins->inst_imm >= 32) {
3148 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3149 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
3150 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
3152 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3153 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3156 case OP_LSHR_UN_IMM:
3157 if (ins->inst_imm >= 32) {
3158 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3159 x86_clear_reg (code, ins->backend.reg3);
3160 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3162 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3163 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3167 x86_not_reg (code, ins->sreg1);
3170 x86_neg_reg (code, ins->sreg1);
3174 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3178 switch (ins->inst_imm) {
3182 if (ins->dreg != ins->sreg1)
3183 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3184 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3187 /* LEA r1, [r2 + r2*2] */
3188 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3191 /* LEA r1, [r2 + r2*4] */
3192 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3195 /* LEA r1, [r2 + r2*2] */
3197 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3198 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3201 /* LEA r1, [r2 + r2*8] */
3202 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3205 /* LEA r1, [r2 + r2*4] */
3207 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3208 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3211 /* LEA r1, [r2 + r2*2] */
3213 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3214 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3217 /* LEA r1, [r2 + r2*4] */
3218 /* LEA r1, [r1 + r1*4] */
3219 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3220 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3223 /* LEA r1, [r2 + r2*4] */
3225 /* LEA r1, [r1 + r1*4] */
3226 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3227 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3228 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3231 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3236 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3237 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3239 case OP_IMUL_OVF_UN: {
3240 /* the mul operation and the exception check should most likely be split */
3241 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3242 /*g_assert (ins->sreg2 == X86_EAX);
3243 g_assert (ins->dreg == X86_EAX);*/
3244 if (ins->sreg2 == X86_EAX) {
3245 non_eax_reg = ins->sreg1;
3246 } else if (ins->sreg1 == X86_EAX) {
3247 non_eax_reg = ins->sreg2;
3249 /* no need to save since we're going to store to it anyway */
3250 if (ins->dreg != X86_EAX) {
3252 x86_push_reg (code, X86_EAX);
3254 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3255 non_eax_reg = ins->sreg2;
3257 if (ins->dreg == X86_EDX) {
3260 x86_push_reg (code, X86_EAX);
3262 } else if (ins->dreg != X86_EAX) {
3264 x86_push_reg (code, X86_EDX);
3266 x86_mul_reg (code, non_eax_reg, FALSE);
3267 /* save before the check since pop and mov don't change the flags */
3268 if (ins->dreg != X86_EAX)
3269 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3271 x86_pop_reg (code, X86_EDX);
3273 x86_pop_reg (code, X86_EAX);
3274 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3278 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3281 g_assert_not_reached ();
3282 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3283 x86_mov_reg_imm (code, ins->dreg, 0);
3286 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3287 x86_mov_reg_imm (code, ins->dreg, 0);
3289 case OP_LOAD_GOTADDR:
3290 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3291 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3294 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3295 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3297 case OP_X86_PUSH_GOT_ENTRY:
3298 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3299 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3302 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3305 MonoCallInst *call = (MonoCallInst*)ins;
3308 ins->flags |= MONO_INST_GC_CALLSITE;
3309 ins->backend.pc_offset = code - cfg->native_code;
3311 /* FIXME: no tracing support... */
3312 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3313 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3314 /* reset offset to make max_len work */
3315 offset = code - cfg->native_code;
3317 g_assert (!cfg->method->save_lmf);
3319 //code = emit_load_volatile_arguments (cfg, code);
3321 /* restore callee saved registers */
3322 for (i = 0; i < X86_NREG; ++i)
3323 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3325 if (cfg->used_int_regs & (1 << X86_ESI)) {
3326 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3329 if (cfg->used_int_regs & (1 << X86_EDI)) {
3330 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3333 if (cfg->used_int_regs & (1 << X86_EBX)) {
3334 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3338 /* Copy arguments on the stack to our argument area */
3339 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3340 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3341 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3344 /* restore ESP/EBP */
3346 offset = code - cfg->native_code;
3347 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3348 x86_jump32 (code, 0);
3350 ins->flags |= MONO_INST_GC_CALLSITE;
3351 cfg->disable_aot = TRUE;
3355 /* ensure ins->sreg1 is not NULL
3356 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3357 * cmp DWORD PTR [eax], 0
3359 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3362 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3363 x86_push_reg (code, hreg);
3364 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3365 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3366 x86_pop_reg (code, hreg);
3375 call = (MonoCallInst*)ins;
3376 if (ins->flags & MONO_INST_HAS_METHOD)
3377 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3379 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3380 ins->flags |= MONO_INST_GC_CALLSITE;
3381 ins->backend.pc_offset = code - cfg->native_code;
3382 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3383 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
3384 * bytes to pop, we want to use pops. GCC does this (note it won't happen
3385 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
3386 * smart enough to do that optimization yet
3388 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
3389 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
3390 * (most likely from locality benefits). People with other processors should
3391 * check on theirs to see what happens.
3393 if (call->stack_usage == 4) {
3394 /* we want to use registers that won't get used soon, so use
3395 * ecx, as eax will get allocated first. edx is used by long calls,
3396 * so we can't use that.
3399 x86_pop_reg (code, X86_ECX);
3401 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3404 code = emit_move_return_value (cfg, ins, code);
3410 case OP_VOIDCALL_REG:
3412 call = (MonoCallInst*)ins;
3413 x86_call_reg (code, ins->sreg1);
3414 ins->flags |= MONO_INST_GC_CALLSITE;
3415 ins->backend.pc_offset = code - cfg->native_code;
3416 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3417 if (call->stack_usage == 4)
3418 x86_pop_reg (code, X86_ECX);
3420 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3422 code = emit_move_return_value (cfg, ins, code);
3424 case OP_FCALL_MEMBASE:
3425 case OP_LCALL_MEMBASE:
3426 case OP_VCALL_MEMBASE:
3427 case OP_VCALL2_MEMBASE:
3428 case OP_VOIDCALL_MEMBASE:
3429 case OP_CALL_MEMBASE:
3430 call = (MonoCallInst*)ins;
3432 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3433 ins->flags |= MONO_INST_GC_CALLSITE;
3434 ins->backend.pc_offset = code - cfg->native_code;
3435 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3436 if (call->stack_usage == 4)
3437 x86_pop_reg (code, X86_ECX);
3439 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3441 code = emit_move_return_value (cfg, ins, code);
3444 x86_push_reg (code, ins->sreg1);
3446 case OP_X86_PUSH_IMM:
3447 x86_push_imm (code, ins->inst_imm);
3449 case OP_X86_PUSH_MEMBASE:
3450 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
3452 case OP_X86_PUSH_OBJ:
3453 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
3454 x86_push_reg (code, X86_EDI);
3455 x86_push_reg (code, X86_ESI);
3456 x86_push_reg (code, X86_ECX);
3457 if (ins->inst_offset)
3458 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
3460 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
3461 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
3462 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
3464 x86_prefix (code, X86_REP_PREFIX);
3466 x86_pop_reg (code, X86_ECX);
3467 x86_pop_reg (code, X86_ESI);
3468 x86_pop_reg (code, X86_EDI);
3471 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3473 case OP_X86_LEA_MEMBASE:
3474 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3477 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3480 /* keep alignment */
3481 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3482 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3483 code = mono_emit_stack_alloc (code, ins);
3484 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3486 case OP_LOCALLOC_IMM: {
3487 guint32 size = ins->inst_imm;
3488 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3490 if (ins->flags & MONO_INST_INIT) {
3491 /* FIXME: Optimize this */
3492 x86_mov_reg_imm (code, ins->dreg, size);
3493 ins->sreg1 = ins->dreg;
3495 code = mono_emit_stack_alloc (code, ins);
3496 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3498 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3499 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3504 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3505 x86_push_reg (code, ins->sreg1);
3506 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3507 (gpointer)"mono_arch_throw_exception");
3508 ins->flags |= MONO_INST_GC_CALLSITE;
3509 ins->backend.pc_offset = code - cfg->native_code;
3513 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3514 x86_push_reg (code, ins->sreg1);
3515 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3516 (gpointer)"mono_arch_rethrow_exception");
3517 ins->flags |= MONO_INST_GC_CALLSITE;
3518 ins->backend.pc_offset = code - cfg->native_code;
3521 case OP_CALL_HANDLER:
3522 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3523 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3524 x86_call_imm (code, 0);
3525 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3526 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3528 case OP_START_HANDLER: {
3529 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3530 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3533 case OP_ENDFINALLY: {
3534 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3535 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3539 case OP_ENDFILTER: {
3540 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3541 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3542 /* The local allocator will put the result into EAX */
3548 ins->inst_c0 = code - cfg->native_code;
3551 if (ins->inst_target_bb->native_offset) {
3552 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3554 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3555 if ((cfg->opt & MONO_OPT_BRANCH) &&
3556 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3557 x86_jump8 (code, 0);
3559 x86_jump32 (code, 0);
3563 x86_jump_reg (code, ins->sreg1);
3582 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3583 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3585 case OP_COND_EXC_EQ:
3586 case OP_COND_EXC_NE_UN:
3587 case OP_COND_EXC_LT:
3588 case OP_COND_EXC_LT_UN:
3589 case OP_COND_EXC_GT:
3590 case OP_COND_EXC_GT_UN:
3591 case OP_COND_EXC_GE:
3592 case OP_COND_EXC_GE_UN:
3593 case OP_COND_EXC_LE:
3594 case OP_COND_EXC_LE_UN:
3595 case OP_COND_EXC_IEQ:
3596 case OP_COND_EXC_INE_UN:
3597 case OP_COND_EXC_ILT:
3598 case OP_COND_EXC_ILT_UN:
3599 case OP_COND_EXC_IGT:
3600 case OP_COND_EXC_IGT_UN:
3601 case OP_COND_EXC_IGE:
3602 case OP_COND_EXC_IGE_UN:
3603 case OP_COND_EXC_ILE:
3604 case OP_COND_EXC_ILE_UN:
3605 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3607 case OP_COND_EXC_OV:
3608 case OP_COND_EXC_NO:
3610 case OP_COND_EXC_NC:
3611 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3613 case OP_COND_EXC_IOV:
3614 case OP_COND_EXC_INO:
3615 case OP_COND_EXC_IC:
3616 case OP_COND_EXC_INC:
3617 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3629 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3637 case OP_CMOV_INE_UN:
3638 case OP_CMOV_IGE_UN:
3639 case OP_CMOV_IGT_UN:
3640 case OP_CMOV_ILE_UN:
3641 case OP_CMOV_ILT_UN:
3642 g_assert (ins->dreg == ins->sreg1);
3643 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3646 /* floating point opcodes */
3648 double d = *(double *)ins->inst_p0;
3650 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3652 } else if (d == 1.0) {
3655 if (cfg->compile_aot) {
3656 guint32 *val = (guint32*)&d;
3657 x86_push_imm (code, val [1]);
3658 x86_push_imm (code, val [0]);
3659 x86_fld_membase (code, X86_ESP, 0, TRUE);
3660 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3663 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3664 x86_fld (code, NULL, TRUE);
3670 float f = *(float *)ins->inst_p0;
3672 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3674 } else if (f == 1.0) {
3677 if (cfg->compile_aot) {
3678 guint32 val = *(guint32*)&f;
3679 x86_push_imm (code, val);
3680 x86_fld_membase (code, X86_ESP, 0, FALSE);
3681 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3684 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3685 x86_fld (code, NULL, FALSE);
3690 case OP_STORER8_MEMBASE_REG:
3691 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3693 case OP_LOADR8_MEMBASE:
3694 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3696 case OP_STORER4_MEMBASE_REG:
3697 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3699 case OP_LOADR4_MEMBASE:
3700 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3702 case OP_ICONV_TO_R4:
3703 x86_push_reg (code, ins->sreg1);
3704 x86_fild_membase (code, X86_ESP, 0, FALSE);
3705 /* Change precision */
3706 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3707 x86_fld_membase (code, X86_ESP, 0, FALSE);
3708 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3710 case OP_ICONV_TO_R8:
3711 x86_push_reg (code, ins->sreg1);
3712 x86_fild_membase (code, X86_ESP, 0, FALSE);
3713 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3715 case OP_ICONV_TO_R_UN:
3716 x86_push_imm (code, 0);
3717 x86_push_reg (code, ins->sreg1);
3718 x86_fild_membase (code, X86_ESP, 0, TRUE);
3719 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3721 case OP_X86_FP_LOAD_I8:
3722 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3724 case OP_X86_FP_LOAD_I4:
3725 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3727 case OP_FCONV_TO_R4:
3728 /* Change precision */
3729 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3730 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3731 x86_fld_membase (code, X86_ESP, 0, FALSE);
3732 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3734 case OP_FCONV_TO_I1:
3735 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3737 case OP_FCONV_TO_U1:
3738 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3740 case OP_FCONV_TO_I2:
3741 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3743 case OP_FCONV_TO_U2:
3744 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3746 case OP_FCONV_TO_I4:
3748 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3750 case OP_FCONV_TO_I8:
3751 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3752 x86_fnstcw_membase(code, X86_ESP, 0);
3753 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3754 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3755 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3756 x86_fldcw_membase (code, X86_ESP, 2);
3757 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3758 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3759 x86_pop_reg (code, ins->dreg);
3760 x86_pop_reg (code, ins->backend.reg3);
3761 x86_fldcw_membase (code, X86_ESP, 0);
3762 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3764 case OP_LCONV_TO_R8_2:
3765 x86_push_reg (code, ins->sreg2);
3766 x86_push_reg (code, ins->sreg1);
3767 x86_fild_membase (code, X86_ESP, 0, TRUE);
3768 /* Change precision */
3769 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3770 x86_fld_membase (code, X86_ESP, 0, TRUE);
3771 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3773 case OP_LCONV_TO_R4_2:
3774 x86_push_reg (code, ins->sreg2);
3775 x86_push_reg (code, ins->sreg1);
3776 x86_fild_membase (code, X86_ESP, 0, TRUE);
3777 /* Change precision */
3778 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3779 x86_fld_membase (code, X86_ESP, 0, FALSE);
3780 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3782 case OP_LCONV_TO_R_UN_2: {
3783 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3786 /* load 64bit integer to FP stack */
3787 x86_push_reg (code, ins->sreg2);
3788 x86_push_reg (code, ins->sreg1);
3789 x86_fild_membase (code, X86_ESP, 0, TRUE);
3791 /* test if lreg is negative */
3792 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3793 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3795 /* add correction constant mn */
3796 if (cfg->compile_aot) {
3797 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3798 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3799 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3800 x86_fld80_membase (code, X86_ESP, 2);
3801 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3803 x86_fld80_mem (code, mn);
3805 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3807 x86_patch (br, code);
3809 /* Change precision */
3810 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3811 x86_fld_membase (code, X86_ESP, 0, TRUE);
3813 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3817 case OP_LCONV_TO_OVF_I:
3818 case OP_LCONV_TO_OVF_I4_2: {
3819 guint8 *br [3], *label [1];
3823 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3825 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3827 /* If the low word top bit is set, see if we are negative */
3828 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3829 /* We are not negative (no top bit set, check for our top word to be zero */
3830 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3831 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3834 /* throw exception */
3835 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3837 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3838 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3839 x86_jump8 (code, 0);
3841 x86_jump32 (code, 0);
3843 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3844 x86_jump32 (code, 0);
3848 x86_patch (br [0], code);
3849 /* our top bit is set, check that top word is 0xfffffff */
3850 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3852 x86_patch (br [1], code);
3853 /* nope, emit exception */
3854 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3855 x86_patch (br [2], label [0]);
3857 if (ins->dreg != ins->sreg1)
3858 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3862 /* Not needed on the fp stack */
3865 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3868 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3871 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3874 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3882 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3887 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3894 * it really doesn't make sense to inline all this code,
3895 * it's here just to show that things may not be as simple
3898 guchar *check_pos, *end_tan, *pop_jump;
3899 x86_push_reg (code, X86_EAX);
3902 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3904 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3905 x86_fstp (code, 0); /* pop the 1.0 */
3907 x86_jump8 (code, 0);
3909 x86_fp_op (code, X86_FADD, 0);
3913 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3915 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3918 x86_patch (pop_jump, code);
3919 x86_fstp (code, 0); /* pop the 1.0 */
3920 x86_patch (check_pos, code);
3921 x86_patch (end_tan, code);
3923 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3924 x86_pop_reg (code, X86_EAX);
3931 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3940 g_assert (cfg->opt & MONO_OPT_CMOV);
3941 g_assert (ins->dreg == ins->sreg1);
3942 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3943 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3946 g_assert (cfg->opt & MONO_OPT_CMOV);
3947 g_assert (ins->dreg == ins->sreg1);
3948 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3949 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3952 g_assert (cfg->opt & MONO_OPT_CMOV);
3953 g_assert (ins->dreg == ins->sreg1);
3954 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3955 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3958 g_assert (cfg->opt & MONO_OPT_CMOV);
3959 g_assert (ins->dreg == ins->sreg1);
3960 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3961 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3967 x86_fxch (code, ins->inst_imm);
3972 x86_push_reg (code, X86_EAX);
3973 /* we need to exchange ST(0) with ST(1) */
3976 /* this requires a loop, because fprem somtimes
3977 * returns a partial remainder */
3979 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3980 /* x86_fprem1 (code); */
3983 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3985 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3991 x86_pop_reg (code, X86_EAX);
3995 if (cfg->opt & MONO_OPT_FCMOV) {
3996 x86_fcomip (code, 1);
4000 /* this overwrites EAX */
4001 EMIT_FPCOMPARE(code);
4002 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4006 if (cfg->opt & MONO_OPT_FCMOV) {
4007 /* zeroing the register at the start results in
4008 * shorter and faster code (we can also remove the widening op)
4010 guchar *unordered_check;
4011 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4012 x86_fcomip (code, 1);
4014 unordered_check = code;
4015 x86_branch8 (code, X86_CC_P, 0, FALSE);
4016 if (ins->opcode == OP_FCEQ) {
4017 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4018 x86_patch (unordered_check, code);
4020 guchar *jump_to_end;
4021 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
4023 x86_jump8 (code, 0);
4024 x86_patch (unordered_check, code);
4025 x86_inc_reg (code, ins->dreg);
4026 x86_patch (jump_to_end, code);
4031 if (ins->dreg != X86_EAX)
4032 x86_push_reg (code, X86_EAX);
4034 EMIT_FPCOMPARE(code);
4035 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4036 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4037 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
4038 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4040 if (ins->dreg != X86_EAX)
4041 x86_pop_reg (code, X86_EAX);
4045 if (cfg->opt & MONO_OPT_FCMOV) {
4046 /* zeroing the register at the start results in
4047 * shorter and faster code (we can also remove the widening op)
4049 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4050 x86_fcomip (code, 1);
4052 if (ins->opcode == OP_FCLT_UN) {
4053 guchar *unordered_check = code;
4054 guchar *jump_to_end;
4055 x86_branch8 (code, X86_CC_P, 0, FALSE);
4056 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4058 x86_jump8 (code, 0);
4059 x86_patch (unordered_check, code);
4060 x86_inc_reg (code, ins->dreg);
4061 x86_patch (jump_to_end, code);
4063 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4067 if (ins->dreg != X86_EAX)
4068 x86_push_reg (code, X86_EAX);
4070 EMIT_FPCOMPARE(code);
4071 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4072 if (ins->opcode == OP_FCLT_UN) {
4073 guchar *is_not_zero_check, *end_jump;
4074 is_not_zero_check = code;
4075 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4077 x86_jump8 (code, 0);
4078 x86_patch (is_not_zero_check, code);
4079 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4081 x86_patch (end_jump, code);
4083 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4084 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4086 if (ins->dreg != X86_EAX)
4087 x86_pop_reg (code, X86_EAX);
4090 guchar *unordered_check;
4091 guchar *jump_to_end;
4092 if (cfg->opt & MONO_OPT_FCMOV) {
4093 /* zeroing the register at the start results in
4094 * shorter and faster code (we can also remove the widening op)
4096 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4097 x86_fcomip (code, 1);
4099 unordered_check = code;
4100 x86_branch8 (code, X86_CC_P, 0, FALSE);
4101 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
4102 x86_patch (unordered_check, code);
4105 if (ins->dreg != X86_EAX)
4106 x86_push_reg (code, X86_EAX);
4108 EMIT_FPCOMPARE(code);
4109 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4110 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4111 unordered_check = code;
4112 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4114 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4115 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
4116 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4118 x86_jump8 (code, 0);
4119 x86_patch (unordered_check, code);
4120 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4121 x86_patch (jump_to_end, code);
4123 if (ins->dreg != X86_EAX)
4124 x86_pop_reg (code, X86_EAX);
4129 if (cfg->opt & MONO_OPT_FCMOV) {
4130 /* zeroing the register at the start results in
4131 * shorter and faster code (we can also remove the widening op)
4133 guchar *unordered_check;
4134 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4135 x86_fcomip (code, 1);
4137 if (ins->opcode == OP_FCGT) {
4138 unordered_check = code;
4139 x86_branch8 (code, X86_CC_P, 0, FALSE);
4140 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4141 x86_patch (unordered_check, code);
4143 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4147 if (ins->dreg != X86_EAX)
4148 x86_push_reg (code, X86_EAX);
4150 EMIT_FPCOMPARE(code);
4151 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4152 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4153 if (ins->opcode == OP_FCGT_UN) {
4154 guchar *is_not_zero_check, *end_jump;
4155 is_not_zero_check = code;
4156 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4158 x86_jump8 (code, 0);
4159 x86_patch (is_not_zero_check, code);
4160 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4162 x86_patch (end_jump, code);
4164 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4165 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4167 if (ins->dreg != X86_EAX)
4168 x86_pop_reg (code, X86_EAX);
4171 guchar *unordered_check;
4172 guchar *jump_to_end;
4173 if (cfg->opt & MONO_OPT_FCMOV) {
4174 /* zeroing the register at the start results in
4175 * shorter and faster code (we can also remove the widening op)
4177 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4178 x86_fcomip (code, 1);
4180 unordered_check = code;
4181 x86_branch8 (code, X86_CC_P, 0, FALSE);
4182 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4183 x86_patch (unordered_check, code);
4186 if (ins->dreg != X86_EAX)
4187 x86_push_reg (code, X86_EAX);
4189 EMIT_FPCOMPARE(code);
4190 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4191 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4192 unordered_check = code;
4193 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4195 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4196 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4197 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4199 x86_jump8 (code, 0);
4200 x86_patch (unordered_check, code);
4201 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4202 x86_patch (jump_to_end, code);
4204 if (ins->dreg != X86_EAX)
4205 x86_pop_reg (code, X86_EAX);
4209 if (cfg->opt & MONO_OPT_FCMOV) {
4210 guchar *jump = code;
4211 x86_branch8 (code, X86_CC_P, 0, TRUE);
4212 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4213 x86_patch (jump, code);
4216 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4217 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4220 /* Branch if C013 != 100 */
4221 if (cfg->opt & MONO_OPT_FCMOV) {
4222 /* branch if !ZF or (PF|CF) */
4223 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4224 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4225 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4228 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4229 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4232 if (cfg->opt & MONO_OPT_FCMOV) {
4233 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4236 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4239 if (cfg->opt & MONO_OPT_FCMOV) {
4240 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4241 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4244 if (ins->opcode == OP_FBLT_UN) {
4245 guchar *is_not_zero_check, *end_jump;
4246 is_not_zero_check = code;
4247 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4249 x86_jump8 (code, 0);
4250 x86_patch (is_not_zero_check, code);
4251 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4253 x86_patch (end_jump, code);
4255 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4259 if (cfg->opt & MONO_OPT_FCMOV) {
4260 if (ins->opcode == OP_FBGT) {
4263 /* skip branch if C1=1 */
4265 x86_branch8 (code, X86_CC_P, 0, FALSE);
4266 /* branch if (C0 | C3) = 1 */
4267 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4268 x86_patch (br1, code);
4270 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4274 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4275 if (ins->opcode == OP_FBGT_UN) {
4276 guchar *is_not_zero_check, *end_jump;
4277 is_not_zero_check = code;
4278 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4280 x86_jump8 (code, 0);
4281 x86_patch (is_not_zero_check, code);
4282 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4284 x86_patch (end_jump, code);
4286 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4289 /* Branch if C013 == 100 or 001 */
4290 if (cfg->opt & MONO_OPT_FCMOV) {
4293 /* skip branch if C1=1 */
4295 x86_branch8 (code, X86_CC_P, 0, FALSE);
4296 /* branch if (C0 | C3) = 1 */
4297 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4298 x86_patch (br1, code);
4301 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4302 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4303 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4304 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4307 /* Branch if C013 == 000 */
4308 if (cfg->opt & MONO_OPT_FCMOV) {
4309 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4312 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4315 /* Branch if C013=000 or 100 */
4316 if (cfg->opt & MONO_OPT_FCMOV) {
4319 /* skip branch if C1=1 */
4321 x86_branch8 (code, X86_CC_P, 0, FALSE);
4322 /* branch if C0=0 */
4323 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4324 x86_patch (br1, code);
4327 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4328 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4329 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4332 /* Branch if C013 != 001 */
4333 if (cfg->opt & MONO_OPT_FCMOV) {
4334 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4335 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4338 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4339 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4343 x86_push_reg (code, X86_EAX);
4346 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4347 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4348 x86_pop_reg (code, X86_EAX);
4350 /* Have to clean up the fp stack before throwing the exception */
4352 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4355 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4357 x86_patch (br1, code);
4361 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4364 case OP_TLS_GET_REG: {
4365 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4368 case OP_MEMORY_BARRIER: {
4369 /* x86 only needs barrier for StoreLoad and FullBarrier */
4370 switch (ins->backend.memory_barrier_kind) {
4371 case StoreLoadBarrier:
4373 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4374 x86_prefix (code, X86_LOCK_PREFIX);
4375 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4380 case OP_ATOMIC_ADD_I4: {
4381 int dreg = ins->dreg;
4383 if (dreg == ins->inst_basereg) {
4384 x86_push_reg (code, ins->sreg2);
4388 if (dreg != ins->sreg2)
4389 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
4391 x86_prefix (code, X86_LOCK_PREFIX);
4392 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4394 if (dreg != ins->dreg) {
4395 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4396 x86_pop_reg (code, dreg);
4401 case OP_ATOMIC_ADD_NEW_I4: {
4402 int dreg = ins->dreg;
4404 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4405 if (ins->sreg2 == dreg) {
4406 if (dreg == X86_EBX) {
4408 if (ins->inst_basereg == X86_EDI)
4412 if (ins->inst_basereg == X86_EBX)
4415 } else if (ins->inst_basereg == dreg) {
4416 if (dreg == X86_EBX) {
4418 if (ins->sreg2 == X86_EDI)
4422 if (ins->sreg2 == X86_EBX)
4427 if (dreg != ins->dreg) {
4428 x86_push_reg (code, dreg);
4431 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4432 x86_prefix (code, X86_LOCK_PREFIX);
4433 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4434 /* dreg contains the old value, add with sreg2 value */
4435 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4437 if (ins->dreg != dreg) {
4438 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4439 x86_pop_reg (code, dreg);
4444 case OP_ATOMIC_EXCHANGE_I4: {
4446 int sreg2 = ins->sreg2;
4447 int breg = ins->inst_basereg;
4449 /* cmpxchg uses eax as comperand, need to make sure we can use it
4450 * hack to overcome limits in x86 reg allocator
4451 * (req: dreg == eax and sreg2 != eax and breg != eax)
4453 g_assert (ins->dreg == X86_EAX);
4455 /* We need the EAX reg for the cmpxchg */
4456 if (ins->sreg2 == X86_EAX) {
4457 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4458 x86_push_reg (code, sreg2);
4459 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4462 if (breg == X86_EAX) {
4463 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4464 x86_push_reg (code, breg);
4465 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4468 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4470 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4471 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4472 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4473 x86_patch (br [1], br [0]);
4475 if (breg != ins->inst_basereg)
4476 x86_pop_reg (code, breg);
4478 if (ins->sreg2 != sreg2)
4479 x86_pop_reg (code, sreg2);
4483 case OP_ATOMIC_CAS_I4: {
4484 g_assert (ins->dreg == X86_EAX);
4485 g_assert (ins->sreg3 == X86_EAX);
4486 g_assert (ins->sreg1 != X86_EAX);
4487 g_assert (ins->sreg1 != ins->sreg2);
4489 x86_prefix (code, X86_LOCK_PREFIX);
4490 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4493 case OP_CARD_TABLE_WBARRIER: {
4494 int ptr = ins->sreg1;
4495 int value = ins->sreg2;
4497 int nursery_shift, card_table_shift;
4498 gpointer card_table_mask;
4499 size_t nursery_size;
4500 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4501 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4502 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4505 * We need one register we can clobber, we choose EDX and make sreg1
4506 * fixed EAX to work around limitations in the local register allocator.
4507 * sreg2 might get allocated to EDX, but that is not a problem since
4508 * we use it before clobbering EDX.
4510 g_assert (ins->sreg1 == X86_EAX);
4513 * This is the code we produce:
4516 * edx >>= nursery_shift
4517 * cmp edx, (nursery_start >> nursery_shift)
4520 * edx >>= card_table_shift
4521 * card_table[edx] = 1
4525 if (card_table_nursery_check) {
4526 if (value != X86_EDX)
4527 x86_mov_reg_reg (code, X86_EDX, value, 4);
4528 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4529 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4530 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4532 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4533 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4534 if (card_table_mask)
4535 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4536 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4537 if (card_table_nursery_check)
4538 x86_patch (br, code);
4541 #ifdef MONO_ARCH_SIMD_INTRINSICS
4543 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4546 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4549 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4552 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4555 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4558 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4561 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4562 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4565 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4568 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4571 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4574 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4577 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4580 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4583 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4586 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4589 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4592 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4595 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4598 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4601 case OP_PSHUFLEW_HIGH:
4602 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4603 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4605 case OP_PSHUFLEW_LOW:
4606 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4607 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4610 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4611 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4614 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4615 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4618 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4619 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4623 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4626 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4629 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4632 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4635 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4638 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4641 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4642 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4645 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4648 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4651 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4654 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4657 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4660 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4663 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4666 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4669 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4672 case OP_EXTRACT_MASK:
4673 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4677 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4680 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4683 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4687 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4690 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4693 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4696 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4700 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4703 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4706 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4709 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4713 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4716 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4719 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4723 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4726 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4729 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4733 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4736 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4740 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4743 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4746 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4750 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4753 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4756 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4760 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4763 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4766 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4769 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4773 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4776 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4779 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4782 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4785 case OP_PSUM_ABS_DIFF:
4786 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4789 case OP_UNPACK_LOWB:
4790 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4792 case OP_UNPACK_LOWW:
4793 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4795 case OP_UNPACK_LOWD:
4796 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4798 case OP_UNPACK_LOWQ:
4799 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4801 case OP_UNPACK_LOWPS:
4802 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4804 case OP_UNPACK_LOWPD:
4805 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4808 case OP_UNPACK_HIGHB:
4809 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4811 case OP_UNPACK_HIGHW:
4812 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4814 case OP_UNPACK_HIGHD:
4815 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4817 case OP_UNPACK_HIGHQ:
4818 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4820 case OP_UNPACK_HIGHPS:
4821 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4823 case OP_UNPACK_HIGHPD:
4824 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4828 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4831 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4834 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4837 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4840 case OP_PADDB_SAT_UN:
4841 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4843 case OP_PSUBB_SAT_UN:
4844 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4846 case OP_PADDW_SAT_UN:
4847 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4849 case OP_PSUBW_SAT_UN:
4850 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4854 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4857 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4860 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4863 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4867 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4870 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4873 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4875 case OP_PMULW_HIGH_UN:
4876 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4879 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4883 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4886 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4890 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4893 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4897 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4900 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4904 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4907 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4911 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4914 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4918 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4921 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4925 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4928 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4932 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4935 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4939 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4942 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4946 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4948 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4949 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4953 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4955 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4956 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4960 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4962 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4963 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4967 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4969 case OP_EXTRACTX_U2:
4970 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4972 case OP_INSERTX_U1_SLOW:
4973 /*sreg1 is the extracted ireg (scratch)
4974 /sreg2 is the to be inserted ireg (scratch)
4975 /dreg is the xreg to receive the value*/
4977 /*clear the bits from the extracted word*/
4978 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4979 /*shift the value to insert if needed*/
4980 if (ins->inst_c0 & 1)
4981 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4982 /*join them together*/
4983 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4984 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4986 case OP_INSERTX_I4_SLOW:
4987 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4988 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4989 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4992 case OP_INSERTX_R4_SLOW:
4993 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4994 /*TODO if inst_c0 == 0 use movss*/
4995 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4996 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4998 case OP_INSERTX_R8_SLOW:
4999 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
5000 if (cfg->verbose_level)
5001 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
5003 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5005 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5008 case OP_STOREX_MEMBASE_REG:
5009 case OP_STOREX_MEMBASE:
5010 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5012 case OP_LOADX_MEMBASE:
5013 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5015 case OP_LOADX_ALIGNED_MEMBASE:
5016 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5018 case OP_STOREX_ALIGNED_MEMBASE_REG:
5019 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5021 case OP_STOREX_NTA_MEMBASE_REG:
5022 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
5024 case OP_PREFETCH_MEMBASE:
5025 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5029 /*FIXME the peephole pass should have killed this*/
5030 if (ins->dreg != ins->sreg1)
5031 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5034 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
5036 case OP_ICONV_TO_R8_RAW:
5037 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
5038 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
5041 case OP_FCONV_TO_R8_X:
5042 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
5043 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5046 case OP_XCONV_R8_TO_I4:
5047 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
5048 switch (ins->backend.source_opcode) {
5049 case OP_FCONV_TO_I1:
5050 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5052 case OP_FCONV_TO_U1:
5053 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5055 case OP_FCONV_TO_I2:
5056 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5058 case OP_FCONV_TO_U2:
5059 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5065 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
5066 /*The +4 is to get a mov ?h, ?l over the same reg.*/
5067 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
5068 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
5069 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
5070 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5073 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
5074 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
5075 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5078 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
5079 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5082 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
5083 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5084 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5087 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
5088 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5089 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
5093 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
5096 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
5099 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
5102 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
5105 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
5108 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
5111 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
5114 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
5118 case OP_LIVERANGE_START: {
5119 if (cfg->verbose_level > 1)
5120 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5121 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5124 case OP_LIVERANGE_END: {
5125 if (cfg->verbose_level > 1)
5126 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5127 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5130 case OP_NACL_GC_SAFE_POINT: {
5131 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
5132 if (cfg->compile_aot)
5133 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5137 x86_test_mem_imm8 (code, (gpointer)&__nacl_thread_suspension_needed, 0xFFFFFFFF);
5138 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
5139 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5140 x86_patch (br[0], code);
5145 case OP_GC_LIVENESS_DEF:
5146 case OP_GC_LIVENESS_USE:
5147 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5148 ins->backend.pc_offset = code - cfg->native_code;
5150 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5151 ins->backend.pc_offset = code - cfg->native_code;
5152 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5155 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
5156 g_assert_not_reached ();
5159 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
5160 #ifndef __native_client_codegen__
5161 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5162 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5163 g_assert_not_reached ();
5164 #endif /* __native_client_codegen__ */
5170 cfg->code_len = code - cfg->native_code;
5173 #endif /* DISABLE_JIT */
5176 mono_arch_register_lowlevel_calls (void)
5181 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
5183 MonoJumpInfo *patch_info;
5184 gboolean compile_aot = !run_cctors;
5186 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5187 unsigned char *ip = patch_info->ip.i + code;
5188 const unsigned char *target;
5191 switch (patch_info->type) {
5192 case MONO_PATCH_INFO_BB:
5193 case MONO_PATCH_INFO_LABEL:
5196 /* No need to patch these */
5201 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5203 switch (patch_info->type) {
5204 case MONO_PATCH_INFO_IP:
5205 *((gconstpointer *)(ip)) = target;
5207 case MONO_PATCH_INFO_CLASS_INIT: {
5209 /* Might already been changed to a nop */
5210 x86_call_code (code, 0);
5211 x86_patch (ip, target);
5214 case MONO_PATCH_INFO_ABS:
5215 case MONO_PATCH_INFO_METHOD:
5216 case MONO_PATCH_INFO_METHOD_JUMP:
5217 case MONO_PATCH_INFO_INTERNAL_METHOD:
5218 case MONO_PATCH_INFO_BB:
5219 case MONO_PATCH_INFO_LABEL:
5220 case MONO_PATCH_INFO_RGCTX_FETCH:
5221 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
5222 case MONO_PATCH_INFO_MONITOR_ENTER:
5223 case MONO_PATCH_INFO_MONITOR_EXIT:
5224 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5225 #if defined(__native_client_codegen__) && defined(__native_client__)
5226 if (nacl_is_code_address (code)) {
5227 /* For tail calls, code is patched after being installed */
5228 /* but not through the normal "patch callsite" method. */
5229 unsigned char buf[kNaClAlignment];
5230 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5231 unsigned char *_target = target;
5233 /* All patch targets modified in x86_patch */
5234 /* are IP relative. */
5235 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5236 memcpy (buf, aligned_code, kNaClAlignment);
5237 /* Patch a temp buffer of bundle size, */
5238 /* then install to actual location. */
5239 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5240 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5241 g_assert (ret == 0);
5244 x86_patch (ip, target);
5247 x86_patch (ip, target);
5250 case MONO_PATCH_INFO_NONE:
5252 case MONO_PATCH_INFO_R4:
5253 case MONO_PATCH_INFO_R8: {
5254 guint32 offset = mono_arch_get_patch_offset (ip);
5255 *((gconstpointer *)(ip + offset)) = target;
5259 guint32 offset = mono_arch_get_patch_offset (ip);
5260 #if !defined(__native_client__)
5261 *((gconstpointer *)(ip + offset)) = target;
5263 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5271 static G_GNUC_UNUSED void
5272 stack_unaligned (MonoMethod *m, gpointer caller)
5274 printf ("%s\n", mono_method_full_name (m, TRUE));
5275 g_assert_not_reached ();
5279 mono_arch_emit_prolog (MonoCompile *cfg)
5281 MonoMethod *method = cfg->method;
5283 MonoMethodSignature *sig;
5285 int alloc_size, pos, max_offset, i, cfa_offset;
5287 gboolean need_stack_frame;
5288 #ifdef __native_client_codegen__
5289 guint alignment_check;
5292 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5294 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5295 cfg->code_size += 512;
5297 #if defined(__default_codegen__)
5298 code = cfg->native_code = g_malloc (cfg->code_size);
5299 #elif defined(__native_client_codegen__)
5300 /* native_code_alloc is not 32-byte aligned, native_code is. */
5301 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5302 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5304 /* Align native_code to next nearest kNaclAlignment byte. */
5305 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5306 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5308 code = cfg->native_code;
5310 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5311 g_assert(alignment_check == 0);
5318 /* Check that the stack is aligned on osx */
5319 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5320 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5321 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5323 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5324 x86_push_membase (code, X86_ESP, 0);
5325 x86_push_imm (code, cfg->method);
5326 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5327 x86_call_reg (code, X86_EAX);
5328 x86_patch (br [0], code);
5332 /* Offset between RSP and the CFA */
5336 cfa_offset = sizeof (gpointer);
5337 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5338 // IP saved at CFA - 4
5339 /* There is no IP reg on x86 */
5340 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5341 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5343 need_stack_frame = needs_stack_frame (cfg);
5345 if (need_stack_frame) {
5346 x86_push_reg (code, X86_EBP);
5347 cfa_offset += sizeof (gpointer);
5348 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5349 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5350 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5351 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5352 /* These are handled automatically by the stack marking code */
5353 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5355 cfg->frame_reg = X86_ESP;
5358 alloc_size = cfg->stack_offset;
5361 if (!method->save_lmf) {
5362 for (i = 0; i < X86_NREG; ++i) {
5363 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5364 x86_push_reg (code, i);
5366 cfa_offset += sizeof (gpointer);
5367 mono_emit_unwind_op_offset (cfg, code, i, - cfa_offset);
5368 /* These are handled automatically by the stack marking code */
5369 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5376 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5377 if (mono_do_x86_stack_align && need_stack_frame) {
5378 int tot = alloc_size + pos + 4; /* ret ip */
5379 if (need_stack_frame)
5381 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5383 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5384 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5385 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5389 cfg->arch.sp_fp_offset = alloc_size + pos;
5392 /* See mono_emit_stack_alloc */
5393 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5394 guint32 remaining_size = alloc_size;
5395 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5396 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5397 guint32 offset = code - cfg->native_code;
5398 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5399 while (required_code_size >= (cfg->code_size - offset))
5400 cfg->code_size *= 2;
5401 cfg->native_code = mono_realloc_native_code(cfg);
5402 code = cfg->native_code + offset;
5403 cfg->stat_code_reallocs++;
5405 while (remaining_size >= 0x1000) {
5406 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5407 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5408 remaining_size -= 0x1000;
5411 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5413 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5416 g_assert (need_stack_frame);
5419 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5420 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5421 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5424 #if DEBUG_STACK_ALIGNMENT
5425 /* check the stack is aligned */
5426 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5427 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5428 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5429 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5430 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5431 x86_breakpoint (code);
5435 /* compute max_offset in order to use short forward jumps */
5437 if (cfg->opt & MONO_OPT_BRANCH) {
5438 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5440 bb->max_offset = max_offset;
5442 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5444 /* max alignment for loops */
5445 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5446 max_offset += LOOP_ALIGNMENT;
5447 #ifdef __native_client_codegen__
5448 /* max alignment for native client */
5449 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5450 max_offset += kNaClAlignment;
5452 MONO_BB_FOR_EACH_INS (bb, ins) {
5453 if (ins->opcode == OP_LABEL)
5454 ins->inst_c1 = max_offset;
5455 #ifdef __native_client_codegen__
5456 switch (ins->opcode)
5468 case OP_VOIDCALL_REG:
5470 case OP_FCALL_MEMBASE:
5471 case OP_LCALL_MEMBASE:
5472 case OP_VCALL_MEMBASE:
5473 case OP_VCALL2_MEMBASE:
5474 case OP_VOIDCALL_MEMBASE:
5475 case OP_CALL_MEMBASE:
5476 max_offset += kNaClAlignment;
5479 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5482 #endif /* __native_client_codegen__ */
5483 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5488 /* store runtime generic context */
5489 if (cfg->rgctx_var) {
5490 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5492 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5495 if (method->save_lmf) {
5496 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5497 code = emit_push_lmf (cfg, code, cfg->lmf_var->inst_offset);
5500 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5501 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5503 /* load arguments allocated to register from the stack */
5504 sig = mono_method_signature (method);
5507 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5508 inst = cfg->args [pos];
5509 if (inst->opcode == OP_REGVAR) {
5510 g_assert (need_stack_frame);
5511 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5512 if (cfg->verbose_level > 2)
5513 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5518 cfg->code_len = code - cfg->native_code;
5520 g_assert (cfg->code_len < cfg->code_size);
5526 mono_arch_emit_epilog (MonoCompile *cfg)
5528 MonoMethod *method = cfg->method;
5529 MonoMethodSignature *sig = mono_method_signature (method);
5531 guint32 stack_to_pop;
5533 int max_epilog_size = 16;
5535 gboolean need_stack_frame = needs_stack_frame (cfg);
5537 if (cfg->method->save_lmf)
5538 max_epilog_size += 128;
5540 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5541 cfg->code_size *= 2;
5542 cfg->native_code = mono_realloc_native_code(cfg);
5543 cfg->stat_code_reallocs++;
5546 code = cfg->native_code + cfg->code_len;
5548 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5549 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5551 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5554 if (method->save_lmf) {
5555 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5557 gboolean supported = FALSE;
5559 if (cfg->compile_aot) {
5560 #if defined(__APPLE__) || defined(__linux__)
5563 } else if (mono_get_jit_tls_offset () != -1) {
5567 /* check if we need to restore protection of the stack after a stack overflow */
5569 if (cfg->compile_aot) {
5570 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5572 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5574 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5577 /* we load the value in a separate instruction: this mechanism may be
5578 * used later as a safer way to do thread interruption
5580 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5581 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5583 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5584 /* note that the call trampoline will preserve eax/edx */
5585 x86_call_reg (code, X86_ECX);
5586 x86_patch (patch, code);
5588 /* FIXME: maybe save the jit tls in the prolog */
5591 code = emit_pop_lmf (cfg, code, lmf_offset);
5593 /* restore caller saved regs */
5594 if (cfg->used_int_regs & (1 << X86_EBX)) {
5595 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
5598 if (cfg->used_int_regs & (1 << X86_EDI)) {
5599 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
5601 if (cfg->used_int_regs & (1 << X86_ESI)) {
5602 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
5605 /* EBP is restored by LEAVE */
5607 for (i = 0; i < X86_NREG; ++i) {
5608 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5614 g_assert (need_stack_frame);
5615 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5618 for (i = X86_NREG - 1; i >= 0; --i) {
5619 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP))
5620 x86_pop_reg (code, i);
5624 /* Load returned vtypes into registers if needed */
5625 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5626 if (cinfo->ret.storage == ArgValuetypeInReg) {
5627 for (quad = 0; quad < 2; quad ++) {
5628 switch (cinfo->ret.pair_storage [quad]) {
5630 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5632 case ArgOnFloatFpStack:
5633 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5635 case ArgOnDoubleFpStack:
5636 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5641 g_assert_not_reached ();
5646 if (need_stack_frame)
5649 if (CALLCONV_IS_STDCALL (sig)) {
5650 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5652 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5653 } else if (cinfo->vtype_retaddr)
5659 g_assert (need_stack_frame);
5660 x86_ret_imm (code, stack_to_pop);
5665 cfg->code_len = code - cfg->native_code;
5667 g_assert (cfg->code_len < cfg->code_size);
5671 mono_arch_emit_exceptions (MonoCompile *cfg)
5673 MonoJumpInfo *patch_info;
5676 MonoClass *exc_classes [16];
5677 guint8 *exc_throw_start [16], *exc_throw_end [16];
5681 /* Compute needed space */
5682 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5683 if (patch_info->type == MONO_PATCH_INFO_EXC)
5688 * make sure we have enough space for exceptions
5689 * 16 is the size of two push_imm instructions and a call
5691 if (cfg->compile_aot)
5692 code_size = exc_count * 32;
5694 code_size = exc_count * 16;
5696 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5697 cfg->code_size *= 2;
5698 cfg->native_code = mono_realloc_native_code(cfg);
5699 cfg->stat_code_reallocs++;
5702 code = cfg->native_code + cfg->code_len;
5705 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5706 switch (patch_info->type) {
5707 case MONO_PATCH_INFO_EXC: {
5708 MonoClass *exc_class;
5712 x86_patch (patch_info->ip.i + cfg->native_code, code);
5714 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5715 g_assert (exc_class);
5716 throw_ip = patch_info->ip.i;
5718 /* Find a throw sequence for the same exception class */
5719 for (i = 0; i < nthrows; ++i)
5720 if (exc_classes [i] == exc_class)
5723 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5724 x86_jump_code (code, exc_throw_start [i]);
5725 patch_info->type = MONO_PATCH_INFO_NONE;
5730 /* Compute size of code following the push <OFFSET> */
5731 #if defined(__default_codegen__)
5733 #elif defined(__native_client_codegen__)
5734 code = mono_nacl_align (code);
5735 size = kNaClAlignment;
5737 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5739 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5740 /* Use the shorter form */
5742 x86_push_imm (code, 0);
5746 x86_push_imm (code, 0xf0f0f0f0);
5751 exc_classes [nthrows] = exc_class;
5752 exc_throw_start [nthrows] = code;
5755 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5756 patch_info->data.name = "mono_arch_throw_corlib_exception";
5757 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5758 patch_info->ip.i = code - cfg->native_code;
5759 x86_call_code (code, 0);
5760 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5765 exc_throw_end [nthrows] = code;
5777 cfg->code_len = code - cfg->native_code;
5779 g_assert (cfg->code_len < cfg->code_size);
5783 mono_arch_flush_icache (guint8 *code, gint size)
5789 mono_arch_flush_register_windows (void)
5794 mono_arch_is_inst_imm (gint64 imm)
5800 mono_arch_finish_init (void)
5802 if (!g_getenv ("MONO_NO_TLS")) {
5805 * We need to init this multiple times, since when we are first called, the key might not
5806 * be initialized yet.
5808 appdomain_tls_offset = mono_domain_get_tls_key ();
5809 jit_tls_offset = mono_get_jit_tls_key ();
5811 /* Only 64 tls entries can be accessed using inline code */
5812 if (appdomain_tls_offset >= 64)
5813 appdomain_tls_offset = -1;
5814 if (jit_tls_offset >= 64)
5815 jit_tls_offset = -1;
5818 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5820 appdomain_tls_offset = mono_domain_get_tls_offset ();
5821 lmf_tls_offset = mono_get_lmf_tls_offset ();
5822 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5828 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5832 #ifdef MONO_ARCH_HAVE_IMT
5834 // Linear handler, the bsearch head compare is shorter
5835 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5836 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5837 // x86_patch(ins,target)
5838 //[1 + 5] x86_jump_mem(inst,mem)
5841 #if defined(__default_codegen__)
5842 #define BR_SMALL_SIZE 2
5843 #define BR_LARGE_SIZE 5
5844 #elif defined(__native_client_codegen__)
5845 /* I suspect the size calculation below is actually incorrect. */
5846 /* TODO: fix the calculation that uses these sizes. */
5847 #define BR_SMALL_SIZE 16
5848 #define BR_LARGE_SIZE 12
5849 #endif /*__native_client_codegen__*/
5850 #define JUMP_IMM_SIZE 6
5851 #define ENABLE_WRONG_METHOD_CHECK 0
5855 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5857 int i, distance = 0;
5858 for (i = start; i < target; ++i)
5859 distance += imt_entries [i]->chunk_size;
5864 * LOCKING: called with the domain lock held
5867 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5868 gpointer fail_tramp)
5872 guint8 *code, *start;
5874 for (i = 0; i < count; ++i) {
5875 MonoIMTCheckItem *item = imt_entries [i];
5876 if (item->is_equals) {
5877 if (item->check_target_idx) {
5878 if (!item->compare_done)
5879 item->chunk_size += CMP_SIZE;
5880 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5883 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5885 item->chunk_size += JUMP_IMM_SIZE;
5886 #if ENABLE_WRONG_METHOD_CHECK
5887 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5892 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5893 imt_entries [item->check_target_idx]->compare_done = TRUE;
5895 size += item->chunk_size;
5897 #if defined(__native_client__) && defined(__native_client_codegen__)
5898 /* In Native Client, we don't re-use thunks, allocate from the */
5899 /* normal code manager paths. */
5900 size = NACL_BUNDLE_ALIGN_UP (size);
5901 code = mono_domain_code_reserve (domain, size);
5904 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5906 code = mono_domain_code_reserve (domain, size);
5909 for (i = 0; i < count; ++i) {
5910 MonoIMTCheckItem *item = imt_entries [i];
5911 item->code_target = code;
5912 if (item->is_equals) {
5913 if (item->check_target_idx) {
5914 if (!item->compare_done)
5915 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5916 item->jmp_code = code;
5917 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5918 if (item->has_target_code)
5919 x86_jump_code (code, item->value.target_code);
5921 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5924 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5925 item->jmp_code = code;
5926 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5927 if (item->has_target_code)
5928 x86_jump_code (code, item->value.target_code);
5930 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5931 x86_patch (item->jmp_code, code);
5932 x86_jump_code (code, fail_tramp);
5933 item->jmp_code = NULL;
5935 /* enable the commented code to assert on wrong method */
5936 #if ENABLE_WRONG_METHOD_CHECK
5937 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5938 item->jmp_code = code;
5939 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5941 if (item->has_target_code)
5942 x86_jump_code (code, item->value.target_code);
5944 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5945 #if ENABLE_WRONG_METHOD_CHECK
5946 x86_patch (item->jmp_code, code);
5947 x86_breakpoint (code);
5948 item->jmp_code = NULL;
5953 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5954 item->jmp_code = code;
5955 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5956 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5958 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5961 /* patch the branches to get to the target items */
5962 for (i = 0; i < count; ++i) {
5963 MonoIMTCheckItem *item = imt_entries [i];
5964 if (item->jmp_code) {
5965 if (item->check_target_idx) {
5966 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5972 mono_stats.imt_thunks_size += code - start;
5973 g_assert (code - start <= size);
5977 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5978 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5982 if (mono_jit_map_is_enabled ()) {
5985 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5987 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5988 mono_emit_jit_tramp (start, code - start, buff);
5992 nacl_domain_code_validate (domain, &start, size, &code);
5998 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6000 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
6005 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6007 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6011 mono_arch_get_cie_program (void)
6015 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
6016 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
6022 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6024 MonoInst *ins = NULL;
6027 if (cmethod->klass == mono_defaults.math_class) {
6028 if (strcmp (cmethod->name, "Sin") == 0) {
6030 } else if (strcmp (cmethod->name, "Cos") == 0) {
6032 } else if (strcmp (cmethod->name, "Tan") == 0) {
6034 } else if (strcmp (cmethod->name, "Atan") == 0) {
6036 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6038 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6040 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
6045 MONO_INST_NEW (cfg, ins, opcode);
6046 ins->type = STACK_R8;
6047 ins->dreg = mono_alloc_freg (cfg);
6048 ins->sreg1 = args [0]->dreg;
6049 MONO_ADD_INS (cfg->cbb, ins);
6052 if (cfg->opt & MONO_OPT_CMOV) {
6055 if (strcmp (cmethod->name, "Min") == 0) {
6056 if (fsig->params [0]->type == MONO_TYPE_I4)
6058 } else if (strcmp (cmethod->name, "Max") == 0) {
6059 if (fsig->params [0]->type == MONO_TYPE_I4)
6064 MONO_INST_NEW (cfg, ins, opcode);
6065 ins->type = STACK_I4;
6066 ins->dreg = mono_alloc_ireg (cfg);
6067 ins->sreg1 = args [0]->dreg;
6068 ins->sreg2 = args [1]->dreg;
6069 MONO_ADD_INS (cfg->cbb, ins);
6074 /* OP_FREM is not IEEE compatible */
6075 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6076 MONO_INST_NEW (cfg, ins, OP_FREM);
6077 ins->inst_i0 = args [0];
6078 ins->inst_i1 = args [1];
6087 mono_arch_print_tree (MonoInst *tree, int arity)
6092 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6098 if (appdomain_tls_offset == -1)
6101 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6102 ins->inst_offset = appdomain_tls_offset;
6107 mono_arch_get_patch_offset (guint8 *code)
6109 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
6111 else if (code [0] == 0xba)
6113 else if (code [0] == 0x68)
6116 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
6117 /* push <OFFSET>(<REG>) */
6119 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
6120 /* call *<OFFSET>(<REG>) */
6122 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
6125 else if ((code [0] == 0x58) && (code [1] == 0x05))
6126 /* pop %eax; add <OFFSET>, %eax */
6128 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6129 /* pop <REG>; add <OFFSET>, <REG> */
6131 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6132 /* mov <REG>, imm */
6135 g_assert_not_reached ();
6141 * mono_breakpoint_clean_code:
6143 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6144 * breakpoints in the original code, they are removed in the copy.
6146 * Returns TRUE if no sw breakpoint was present.
6149 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6152 gboolean can_write = TRUE;
6154 * If method_start is non-NULL we need to perform bound checks, since we access memory
6155 * at code - offset we could go before the start of the method and end up in a different
6156 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6159 if (!method_start || code - offset >= method_start) {
6160 memcpy (buf, code - offset, size);
6162 int diff = code - method_start;
6163 memset (buf, 0, size);
6164 memcpy (buf + offset - diff, method_start, diff + size - offset);
6167 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6168 int idx = mono_breakpoint_info_index [i];
6172 ptr = mono_breakpoint_info [idx].address;
6173 if (ptr >= code && ptr < code + size) {
6174 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6176 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6177 buf [ptr - code] = saved_byte;
6184 * mono_x86_get_this_arg_offset:
6186 * Return the offset of the stack location where this is passed during a virtual
6190 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6196 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6198 guint32 esp = regs [X86_ESP];
6199 CallInfo *cinfo = NULL;
6206 * The stack looks like:
6210 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
6212 res = (((MonoObject**)esp) [5 + (offset / 4)]);
6218 #define MAX_ARCH_DELEGATE_PARAMS 10
6221 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6223 guint8 *code, *start;
6224 int code_reserve = 64;
6227 * The stack contains:
6233 start = code = mono_global_codeman_reserve (code_reserve);
6235 /* Replace the this argument with the target */
6236 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6237 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
6238 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6239 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6241 g_assert ((code - start) < code_reserve);
6244 /* 8 for mov_reg and jump, plus 8 for each parameter */
6245 #ifdef __native_client_codegen__
6246 /* TODO: calculate this size correctly */
6247 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6249 code_reserve = 8 + (param_count * 8);
6250 #endif /* __native_client_codegen__ */
6252 * The stack contains:
6253 * <args in reverse order>
6258 * <args in reverse order>
6261 * without unbalancing the stack.
6262 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6263 * and leaving original spot of first arg as placeholder in stack so
6264 * when callee pops stack everything works.
6267 start = code = mono_global_codeman_reserve (code_reserve);
6269 /* store delegate for access to method_ptr */
6270 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6273 for (i = 0; i < param_count; ++i) {
6274 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6275 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6278 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6280 g_assert ((code - start) < code_reserve);
6283 nacl_global_codeman_validate(&start, code_reserve, &code);
6284 mono_debug_add_delegate_trampoline (start, code - start);
6287 *code_len = code - start;
6289 if (mono_jit_map_is_enabled ()) {
6292 buff = (char*)"delegate_invoke_has_target";
6294 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6295 mono_emit_jit_tramp (start, code - start, buff);
6304 mono_arch_get_delegate_invoke_impls (void)
6312 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6313 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
6315 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6316 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6317 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
6318 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
6319 g_free (tramp_name);
6326 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6328 guint8 *code, *start;
6330 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6333 /* FIXME: Support more cases */
6334 if (MONO_TYPE_ISSTRUCT (sig->ret))
6338 * The stack contains:
6344 static guint8* cached = NULL;
6349 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6351 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6353 mono_memory_barrier ();
6357 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6360 for (i = 0; i < sig->param_count; ++i)
6361 if (!mono_is_regsize_var (sig->params [i]))
6364 code = cache [sig->param_count];
6368 if (mono_aot_only) {
6369 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6370 start = mono_aot_get_trampoline (name);
6373 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6376 mono_memory_barrier ();
6378 cache [sig->param_count] = start;
6385 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6388 case X86_EAX: return ctx->eax;
6389 case X86_EBX: return ctx->ebx;
6390 case X86_ECX: return ctx->ecx;
6391 case X86_EDX: return ctx->edx;
6392 case X86_ESP: return ctx->esp;
6393 case X86_EBP: return ctx->ebp;
6394 case X86_ESI: return ctx->esi;
6395 case X86_EDI: return ctx->edi;
6397 g_assert_not_reached ();
6403 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6431 g_assert_not_reached ();
6435 #ifdef MONO_ARCH_SIMD_INTRINSICS
6438 get_float_to_x_spill_area (MonoCompile *cfg)
6440 if (!cfg->fconv_to_r8_x_var) {
6441 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6442 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6444 return cfg->fconv_to_r8_x_var;
6448 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6451 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6454 int dreg, src_opcode;
6456 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6459 switch (src_opcode = ins->opcode) {
6460 case OP_FCONV_TO_I1:
6461 case OP_FCONV_TO_U1:
6462 case OP_FCONV_TO_I2:
6463 case OP_FCONV_TO_U2:
6464 case OP_FCONV_TO_I4:
6471 /* dreg is the IREG and sreg1 is the FREG */
6472 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6473 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6474 fconv->sreg1 = ins->sreg1;
6475 fconv->dreg = mono_alloc_ireg (cfg);
6476 fconv->type = STACK_VTYPE;
6477 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6479 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6483 ins->opcode = OP_XCONV_R8_TO_I4;
6485 ins->klass = mono_defaults.int32_class;
6486 ins->sreg1 = fconv->dreg;
6488 ins->type = STACK_I4;
6489 ins->backend.source_opcode = src_opcode;
6492 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6495 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6500 if (long_ins->opcode == OP_LNEG) {
6502 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6503 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6504 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6509 #ifdef MONO_ARCH_SIMD_INTRINSICS
6511 if (!(cfg->opt & MONO_OPT_SIMD))
6514 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6515 switch (long_ins->opcode) {
6517 vreg = long_ins->sreg1;
6519 if (long_ins->inst_c0) {
6520 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6521 ins->klass = long_ins->klass;
6522 ins->sreg1 = long_ins->sreg1;
6524 ins->type = STACK_VTYPE;
6525 ins->dreg = vreg = alloc_ireg (cfg);
6526 MONO_ADD_INS (cfg->cbb, ins);
6529 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6530 ins->klass = mono_defaults.int32_class;
6532 ins->type = STACK_I4;
6533 ins->dreg = long_ins->dreg + 1;
6534 MONO_ADD_INS (cfg->cbb, ins);
6536 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6537 ins->klass = long_ins->klass;
6538 ins->sreg1 = long_ins->sreg1;
6539 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6540 ins->type = STACK_VTYPE;
6541 ins->dreg = vreg = alloc_ireg (cfg);
6542 MONO_ADD_INS (cfg->cbb, ins);
6544 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6545 ins->klass = mono_defaults.int32_class;
6547 ins->type = STACK_I4;
6548 ins->dreg = long_ins->dreg + 2;
6549 MONO_ADD_INS (cfg->cbb, ins);
6551 long_ins->opcode = OP_NOP;
6553 case OP_INSERTX_I8_SLOW:
6554 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6555 ins->dreg = long_ins->dreg;
6556 ins->sreg1 = long_ins->dreg;
6557 ins->sreg2 = long_ins->sreg2 + 1;
6558 ins->inst_c0 = long_ins->inst_c0 * 2;
6559 MONO_ADD_INS (cfg->cbb, ins);
6561 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6562 ins->dreg = long_ins->dreg;
6563 ins->sreg1 = long_ins->dreg;
6564 ins->sreg2 = long_ins->sreg2 + 2;
6565 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6566 MONO_ADD_INS (cfg->cbb, ins);
6568 long_ins->opcode = OP_NOP;
6571 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6572 ins->dreg = long_ins->dreg;
6573 ins->sreg1 = long_ins->sreg1 + 1;
6574 ins->klass = long_ins->klass;
6575 ins->type = STACK_VTYPE;
6576 MONO_ADD_INS (cfg->cbb, ins);
6578 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6579 ins->dreg = long_ins->dreg;
6580 ins->sreg1 = long_ins->dreg;
6581 ins->sreg2 = long_ins->sreg1 + 2;
6583 ins->klass = long_ins->klass;
6584 ins->type = STACK_VTYPE;
6585 MONO_ADD_INS (cfg->cbb, ins);
6587 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6588 ins->dreg = long_ins->dreg;
6589 ins->sreg1 = long_ins->dreg;;
6590 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6591 ins->klass = long_ins->klass;
6592 ins->type = STACK_VTYPE;
6593 MONO_ADD_INS (cfg->cbb, ins);
6595 long_ins->opcode = OP_NOP;
6598 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6601 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6603 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6606 gpointer *sp, old_value;
6608 const unsigned char *handler;
6610 /*Decode the first instruction to figure out where did we store the spvar*/
6611 /*Our jit MUST generate the following:
6613 Which is encoded as: 0x89 mod_rm.
6614 mod_rm (esp, ebp, imm) which can be: (imm will never be zero)
6615 mod (reg + imm8): 01 reg(esp): 100 rm(ebp): 101 -> 01100101 (0x65)
6616 mod (reg + imm32): 10 reg(esp): 100 rm(ebp): 101 -> 10100101 (0xA5)
6618 handler = clause->handler_start;
6620 if (*handler != 0x89)
6625 if (*handler == 0x65)
6626 offset = *(signed char*)(handler + 1);
6627 else if (*handler == 0xA5)
6628 offset = *(int*)(handler + 1);
6633 bp = MONO_CONTEXT_GET_BP (ctx);
6634 sp = *(gpointer*)(bp + offset);
6637 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6646 * mono_aot_emit_load_got_addr:
6648 * Emit code to load the got address.
6649 * On x86, the result is placed into EBX.
6652 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6654 x86_call_imm (code, 0);
6656 * The patch needs to point to the pop, since the GOT offset needs
6657 * to be added to that address.
6660 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6662 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6663 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6664 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6670 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6673 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6675 g_assert_not_reached ();
6676 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6681 * mono_arch_emit_load_aotconst:
6683 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6684 * TARGET from the mscorlib GOT in full-aot code.
6685 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6689 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6691 /* Load the mscorlib got address */
6692 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6693 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6694 /* arch_emit_got_access () patches this */
6695 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6700 /* Can't put this into mini-x86.h */
6702 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6705 mono_arch_get_trampolines (gboolean aot)
6707 MonoTrampInfo *info;
6708 GSList *tramps = NULL;
6710 mono_x86_get_signal_exception_trampoline (&info, aot);
6712 tramps = g_slist_append (tramps, info);
6719 #define DBG_SIGNAL SIGBUS
6721 #define DBG_SIGNAL SIGSEGV
6724 /* Soft Debug support */
6725 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6728 * mono_arch_set_breakpoint:
6730 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6731 * The location should contain code emitted by OP_SEQ_POINT.
6734 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6739 * In production, we will use int3 (has to fix the size in the md
6740 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6743 g_assert (code [0] == 0x90);
6744 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6748 * mono_arch_clear_breakpoint:
6750 * Clear the breakpoint at IP.
6753 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6758 for (i = 0; i < 6; ++i)
6763 * mono_arch_start_single_stepping:
6765 * Start single stepping.
6768 mono_arch_start_single_stepping (void)
6770 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6774 * mono_arch_stop_single_stepping:
6776 * Stop single stepping.
6779 mono_arch_stop_single_stepping (void)
6781 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6785 * mono_arch_is_single_step_event:
6787 * Return whenever the machine state in SIGCTX corresponds to a single
6791 mono_arch_is_single_step_event (void *info, void *sigctx)
6794 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6796 if (((gpointer)einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6801 siginfo_t* sinfo = (siginfo_t*) info;
6802 /* Sometimes the address is off by 4 */
6803 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6811 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6814 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6815 if (((gpointer)einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6820 siginfo_t* sinfo = (siginfo_t*)info;
6821 /* Sometimes the address is off by 4 */
6822 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6829 #define BREAKPOINT_SIZE 6
6832 * mono_arch_skip_breakpoint:
6834 * See mini-amd64.c for docs.
6837 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6839 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6843 * mono_arch_skip_single_step:
6845 * See mini-amd64.c for docs.
6848 mono_arch_skip_single_step (MonoContext *ctx)
6850 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6854 * mono_arch_get_seq_point_info:
6856 * See mini-amd64.c for docs.
6859 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6866 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6868 ext->lmf.previous_lmf = (gsize)prev_lmf;
6869 /* Mark that this is a MonoLMFExt */
6870 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6871 ext->lmf.ebp = (gssize)ext;
6876 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
6878 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6880 #endif /* !MONOTOUCH */