2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/abi-details.h>
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/metadata/gc-internal.h>
27 #include <mono/utils/mono-math.h>
28 #include <mono/utils/mono-counters.h>
29 #include <mono/utils/mono-mmap.h>
30 #include <mono/utils/mono-memory-model.h>
31 #include <mono/utils/mono-hwcap-x86.h>
41 static gboolean optimize_for_xen = TRUE;
43 #define optimize_for_xen 0
47 /* This mutex protects architecture specific caches */
48 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
49 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
50 static mono_mutex_t mini_arch_mutex;
52 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
57 /* Under windows, the default pinvoke calling convention is stdcall */
58 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
60 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
63 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
66 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
69 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
71 #ifdef __native_client_codegen__
73 /* Default alignment for Native Client is 32-byte. */
74 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
76 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
77 /* Check that alignment doesn't cross an alignment boundary. */
79 mono_arch_nacl_pad (guint8 *code, int pad)
81 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
83 if (pad == 0) return code;
84 /* assertion: alignment cannot cross a block boundary */
85 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
86 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
87 while (pad >= kMaxPadding) {
88 x86_padding (code, kMaxPadding);
91 if (pad != 0) x86_padding (code, pad);
96 mono_arch_nacl_skip_nops (guint8 *code)
102 #endif /* __native_client_codegen__ */
105 * The code generated for sequence points reads from this location, which is
106 * made read-only when single stepping is enabled.
108 static gpointer ss_trigger_page;
110 /* Enabled breakpoints read from this trigger page */
111 static gpointer bp_trigger_page;
114 mono_arch_regname (int reg)
117 case X86_EAX: return "%eax";
118 case X86_EBX: return "%ebx";
119 case X86_ECX: return "%ecx";
120 case X86_EDX: return "%edx";
121 case X86_ESP: return "%esp";
122 case X86_EBP: return "%ebp";
123 case X86_EDI: return "%edi";
124 case X86_ESI: return "%esi";
130 mono_arch_fregname (int reg)
155 mono_arch_xregname (int reg)
180 mono_x86_patch (unsigned char* code, gpointer target)
182 x86_patch (code, (unsigned char*)target);
193 /* gsharedvt argument passed by addr */
205 /* Only if storage == ArgValuetypeInReg */
206 ArgStorage pair_storage [2];
215 gboolean need_stack_align;
216 guint32 stack_align_amount;
217 gboolean vtype_retaddr;
218 /* The index of the vret arg in the argument list */
221 /* Argument space popped by the callee */
222 int callee_stack_pop;
228 #define FLOAT_PARAM_REGS 0
230 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
232 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
237 switch (sig->call_convention) {
238 case MONO_CALL_THISCALL:
239 return thiscall_param_regs;
245 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
246 #define SMALL_STRUCTS_IN_REGS
247 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
251 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
253 ainfo->offset = *stack_size;
255 if (!param_regs || param_regs [*gr] == X86_NREG) {
256 ainfo->storage = ArgOnStack;
258 (*stack_size) += sizeof (gpointer);
261 ainfo->storage = ArgInIReg;
262 ainfo->reg = param_regs [*gr];
268 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
270 ainfo->offset = *stack_size;
272 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
274 ainfo->storage = ArgOnStack;
275 (*stack_size) += sizeof (gpointer) * 2;
280 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
282 ainfo->offset = *stack_size;
284 if (*gr >= FLOAT_PARAM_REGS) {
285 ainfo->storage = ArgOnStack;
286 (*stack_size) += is_double ? 8 : 4;
287 ainfo->nslots = is_double ? 2 : 1;
290 /* A double register */
292 ainfo->storage = ArgInDoubleSSEReg;
294 ainfo->storage = ArgInFloatSSEReg;
302 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
304 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
309 klass = mono_class_from_mono_type (type);
310 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
312 #ifdef SMALL_STRUCTS_IN_REGS
313 if (sig->pinvoke && is_return) {
314 MonoMarshalType *info;
317 * the exact rules are not very well documented, the code below seems to work with the
318 * code generated by gcc 3.3.3 -mno-cygwin.
320 info = mono_marshal_load_type_info (klass);
323 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
325 /* Special case structs with only a float member */
326 if (info->num_fields == 1) {
327 int ftype = mini_replace_type (info->fields [0].field->type)->type;
328 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
329 ainfo->storage = ArgValuetypeInReg;
330 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
333 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
334 ainfo->storage = ArgValuetypeInReg;
335 ainfo->pair_storage [0] = ArgOnFloatFpStack;
339 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
340 ainfo->storage = ArgValuetypeInReg;
341 ainfo->pair_storage [0] = ArgInIReg;
342 ainfo->pair_regs [0] = return_regs [0];
343 if (info->native_size > 4) {
344 ainfo->pair_storage [1] = ArgInIReg;
345 ainfo->pair_regs [1] = return_regs [1];
352 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
353 g_assert (size <= 4);
354 ainfo->storage = ArgValuetypeInReg;
355 ainfo->reg = param_regs [*gr];
360 ainfo->offset = *stack_size;
361 ainfo->storage = ArgOnStack;
362 *stack_size += ALIGN_TO (size, sizeof (gpointer));
363 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
369 * Obtain information about a call according to the calling convention.
370 * For x86 ELF, see the "System V Application Binary Interface Intel386
371 * Architecture Processor Supplment, Fourth Edition" document for more
373 * For x86 win32, see ???.
376 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
378 guint32 i, gr, fr, pstart;
379 const guint32 *param_regs;
381 int n = sig->hasthis + sig->param_count;
382 guint32 stack_size = 0;
383 gboolean is_pinvoke = sig->pinvoke;
389 param_regs = callconv_param_regs(sig);
393 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
394 switch (ret_type->type) {
395 case MONO_TYPE_BOOLEAN:
406 case MONO_TYPE_FNPTR:
407 case MONO_TYPE_CLASS:
408 case MONO_TYPE_OBJECT:
409 case MONO_TYPE_SZARRAY:
410 case MONO_TYPE_ARRAY:
411 case MONO_TYPE_STRING:
412 cinfo->ret.storage = ArgInIReg;
413 cinfo->ret.reg = X86_EAX;
417 cinfo->ret.storage = ArgInIReg;
418 cinfo->ret.reg = X86_EAX;
419 cinfo->ret.is_pair = TRUE;
422 cinfo->ret.storage = ArgOnFloatFpStack;
425 cinfo->ret.storage = ArgOnDoubleFpStack;
427 case MONO_TYPE_GENERICINST:
428 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
429 cinfo->ret.storage = ArgInIReg;
430 cinfo->ret.reg = X86_EAX;
433 if (mini_is_gsharedvt_type_gsctx (gsctx, ret_type)) {
434 cinfo->ret.storage = ArgOnStack;
435 cinfo->vtype_retaddr = TRUE;
439 case MONO_TYPE_VALUETYPE:
440 case MONO_TYPE_TYPEDBYREF: {
441 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
443 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
444 if (cinfo->ret.storage == ArgOnStack) {
445 cinfo->vtype_retaddr = TRUE;
446 /* The caller passes the address where the value is stored */
452 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ret_type));
453 cinfo->ret.storage = ArgOnStack;
454 cinfo->vtype_retaddr = TRUE;
457 cinfo->ret.storage = ArgNone;
460 g_error ("Can't handle as return value 0x%x", ret_type->type);
466 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
467 * the first argument, allowing 'this' to be always passed in the first arg reg.
468 * Also do this if the first argument is a reference type, since virtual calls
469 * are sometimes made using calli without sig->hasthis set, like in the delegate
472 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
474 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
476 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
479 cinfo->vret_arg_offset = stack_size;
480 add_general (&gr, NULL, &stack_size, &cinfo->ret);
481 cinfo->vret_arg_index = 1;
485 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
487 if (cinfo->vtype_retaddr)
488 add_general (&gr, NULL, &stack_size, &cinfo->ret);
491 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
492 fr = FLOAT_PARAM_REGS;
494 /* Emit the signature cookie just before the implicit arguments */
495 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
498 for (i = pstart; i < sig->param_count; ++i) {
499 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
502 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
503 /* We allways pass the sig cookie on the stack for simplicity */
505 * Prevent implicit arguments + the sig cookie from being passed
508 fr = FLOAT_PARAM_REGS;
510 /* Emit the signature cookie just before the implicit arguments */
511 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
514 if (sig->params [i]->byref) {
515 add_general (&gr, param_regs, &stack_size, ainfo);
518 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
519 switch (ptype->type) {
520 case MONO_TYPE_BOOLEAN:
523 add_general (&gr, param_regs, &stack_size, ainfo);
528 add_general (&gr, param_regs, &stack_size, ainfo);
532 add_general (&gr, param_regs, &stack_size, ainfo);
537 case MONO_TYPE_FNPTR:
538 case MONO_TYPE_CLASS:
539 case MONO_TYPE_OBJECT:
540 case MONO_TYPE_STRING:
541 case MONO_TYPE_SZARRAY:
542 case MONO_TYPE_ARRAY:
543 add_general (&gr, param_regs, &stack_size, ainfo);
545 case MONO_TYPE_GENERICINST:
546 if (!mono_type_generic_inst_is_valuetype (ptype)) {
547 add_general (&gr, param_regs, &stack_size, ainfo);
550 if (mini_is_gsharedvt_type_gsctx (gsctx, ptype)) {
551 /* gsharedvt arguments are passed by ref */
552 add_general (&gr, param_regs, &stack_size, ainfo);
553 g_assert (ainfo->storage == ArgOnStack);
554 ainfo->storage = ArgGSharedVt;
558 case MONO_TYPE_VALUETYPE:
559 case MONO_TYPE_TYPEDBYREF:
560 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
564 add_general_pair (&gr, param_regs, &stack_size, ainfo);
567 add_float (&fr, &stack_size, ainfo, FALSE);
570 add_float (&fr, &stack_size, ainfo, TRUE);
574 /* gsharedvt arguments are passed by ref */
575 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ptype));
576 add_general (&gr, param_regs, &stack_size, ainfo);
577 g_assert (ainfo->storage == ArgOnStack);
578 ainfo->storage = ArgGSharedVt;
581 g_error ("unexpected type 0x%x", ptype->type);
582 g_assert_not_reached ();
586 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
587 fr = FLOAT_PARAM_REGS;
589 /* Emit the signature cookie just before the implicit arguments */
590 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
593 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
594 cinfo->need_stack_align = TRUE;
595 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
596 stack_size += cinfo->stack_align_amount;
599 if (cinfo->vtype_retaddr) {
600 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
601 cinfo->callee_stack_pop = 4;
604 cinfo->stack_usage = stack_size;
605 cinfo->reg_usage = gr;
606 cinfo->freg_usage = fr;
611 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
613 int n = sig->hasthis + sig->param_count;
617 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
619 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
621 return get_call_info_internal (gsctx, cinfo, sig);
625 * mono_arch_get_argument_info:
626 * @csig: a method signature
627 * @param_count: the number of parameters to consider
628 * @arg_info: an array to store the result infos
630 * Gathers information on parameters such as size, alignment and
631 * padding. arg_info should be large enought to hold param_count + 1 entries.
633 * Returns the size of the argument area on the stack.
634 * This should be signal safe, since it is called from
635 * mono_arch_find_jit_info ().
636 * FIXME: The metadata calls might not be signal safe.
639 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
641 int len, k, args_size = 0;
647 /* Avoid g_malloc as it is not signal safe */
648 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
649 cinfo = (CallInfo*)g_newa (guint8*, len);
650 memset (cinfo, 0, len);
652 cinfo = get_call_info_internal (gsctx, cinfo, csig);
654 arg_info [0].offset = offset;
656 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
657 args_size += sizeof (gpointer);
662 args_size += sizeof (gpointer);
666 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
667 /* Emitted after this */
668 args_size += sizeof (gpointer);
672 arg_info [0].size = args_size;
674 for (k = 0; k < param_count; k++) {
675 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
677 /* ignore alignment for now */
680 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
681 arg_info [k].pad = pad;
683 arg_info [k + 1].pad = 0;
684 arg_info [k + 1].size = size;
686 arg_info [k + 1].offset = offset;
689 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
690 /* Emitted after the first arg */
691 args_size += sizeof (gpointer);
696 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
697 align = MONO_ARCH_FRAME_ALIGNMENT;
700 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
701 arg_info [k].pad = pad;
707 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
709 MonoType *callee_ret;
713 if (cfg->compile_aot && !cfg->full_aot)
714 /* OP_TAILCALL doesn't work with AOT */
717 c1 = get_call_info (NULL, NULL, caller_sig);
718 c2 = get_call_info (NULL, NULL, callee_sig);
720 * Tail calls with more callee stack usage than the caller cannot be supported, since
721 * the extra stack space would be left on the stack after the tail call.
723 res = c1->stack_usage >= c2->stack_usage;
724 callee_ret = mini_replace_type (callee_sig->ret);
725 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
726 /* An address on the callee's stack is passed as the first argument */
736 * Initialize the cpu to execute managed code.
739 mono_arch_cpu_init (void)
741 /* spec compliance requires running with double precision */
745 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
746 fpcw &= ~X86_FPCW_PRECC_MASK;
747 fpcw |= X86_FPCW_PREC_DOUBLE;
748 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
749 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
751 _control87 (_PC_53, MCW_PC);
756 * Initialize architecture specific code.
759 mono_arch_init (void)
761 mono_mutex_init_recursive (&mini_arch_mutex);
763 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
764 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
765 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
767 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
768 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
769 #if defined(ENABLE_GSHAREDVT)
770 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
775 * Cleanup architecture specific code.
778 mono_arch_cleanup (void)
781 mono_vfree (ss_trigger_page, mono_pagesize ());
783 mono_vfree (bp_trigger_page, mono_pagesize ());
784 mono_mutex_destroy (&mini_arch_mutex);
788 * This function returns the optimizations supported on this cpu.
791 mono_arch_cpu_optimizations (guint32 *exclude_mask)
793 #if !defined(__native_client__)
798 if (mono_hwcap_x86_has_cmov) {
799 opts |= MONO_OPT_CMOV;
801 if (mono_hwcap_x86_has_fcmov)
802 opts |= MONO_OPT_FCMOV;
804 *exclude_mask |= MONO_OPT_FCMOV;
806 *exclude_mask |= MONO_OPT_CMOV;
809 if (mono_hwcap_x86_has_sse2)
810 opts |= MONO_OPT_SSE2;
812 *exclude_mask |= MONO_OPT_SSE2;
814 #ifdef MONO_ARCH_SIMD_INTRINSICS
815 /*SIMD intrinsics require at least SSE2.*/
816 if (!mono_hwcap_x86_has_sse2)
817 *exclude_mask |= MONO_OPT_SIMD;
822 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
827 * This function test for all SSE functions supported.
829 * Returns a bitmask corresponding to all supported versions.
833 mono_arch_cpu_enumerate_simd_versions (void)
835 guint32 sse_opts = 0;
837 if (mono_hwcap_x86_has_sse1)
838 sse_opts |= SIMD_VERSION_SSE1;
840 if (mono_hwcap_x86_has_sse2)
841 sse_opts |= SIMD_VERSION_SSE2;
843 if (mono_hwcap_x86_has_sse3)
844 sse_opts |= SIMD_VERSION_SSE3;
846 if (mono_hwcap_x86_has_ssse3)
847 sse_opts |= SIMD_VERSION_SSSE3;
849 if (mono_hwcap_x86_has_sse41)
850 sse_opts |= SIMD_VERSION_SSE41;
852 if (mono_hwcap_x86_has_sse42)
853 sse_opts |= SIMD_VERSION_SSE42;
855 if (mono_hwcap_x86_has_sse4a)
856 sse_opts |= SIMD_VERSION_SSE4a;
862 * Determine whenever the trap whose info is in SIGINFO is caused by
866 mono_arch_is_int_overflow (void *sigctx, void *info)
871 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
873 ip = (guint8*)ctx.eip;
875 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
879 switch (x86_modrm_rm (ip [1])) {
899 g_assert_not_reached ();
911 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
916 for (i = 0; i < cfg->num_varinfo; i++) {
917 MonoInst *ins = cfg->varinfo [i];
918 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
921 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
924 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
925 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
928 /* we dont allocate I1 to registers because there is no simply way to sign extend
929 * 8bit quantities in caller saved registers on x86 */
930 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
931 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
932 g_assert (i == vmv->idx);
933 vars = g_list_prepend (vars, vmv);
937 vars = mono_varlist_sort (cfg, vars, 0);
943 mono_arch_get_global_int_regs (MonoCompile *cfg)
947 /* we can use 3 registers for global allocation */
948 regs = g_list_prepend (regs, (gpointer)X86_EBX);
949 regs = g_list_prepend (regs, (gpointer)X86_ESI);
950 regs = g_list_prepend (regs, (gpointer)X86_EDI);
956 * mono_arch_regalloc_cost:
958 * Return the cost, in number of memory references, of the action of
959 * allocating the variable VMV into a register during global register
963 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
965 MonoInst *ins = cfg->varinfo [vmv->idx];
967 if (cfg->method->save_lmf)
968 /* The register is already saved */
969 return (ins->opcode == OP_ARG) ? 1 : 0;
971 /* push+pop+possible load if it is an argument */
972 return (ins->opcode == OP_ARG) ? 3 : 2;
976 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
978 static int inited = FALSE;
979 static int count = 0;
981 if (cfg->arch.need_stack_frame_inited) {
982 g_assert (cfg->arch.need_stack_frame == flag);
986 cfg->arch.need_stack_frame = flag;
987 cfg->arch.need_stack_frame_inited = TRUE;
993 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
998 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
1002 needs_stack_frame (MonoCompile *cfg)
1004 MonoMethodSignature *sig;
1005 MonoMethodHeader *header;
1006 gboolean result = FALSE;
1008 #if defined(__APPLE__)
1009 /*OSX requires stack frame code to have the correct alignment. */
1013 if (cfg->arch.need_stack_frame_inited)
1014 return cfg->arch.need_stack_frame;
1016 header = cfg->header;
1017 sig = mono_method_signature (cfg->method);
1019 if (cfg->disable_omit_fp)
1021 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1023 else if (cfg->method->save_lmf)
1025 else if (cfg->stack_offset)
1027 else if (cfg->param_area)
1029 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1031 else if (header->num_clauses)
1033 else if (sig->param_count + sig->hasthis)
1035 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1037 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1038 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1041 set_needs_stack_frame (cfg, result);
1043 return cfg->arch.need_stack_frame;
1047 * Set var information according to the calling convention. X86 version.
1048 * The locals var stuff should most likely be split in another method.
1051 mono_arch_allocate_vars (MonoCompile *cfg)
1053 MonoMethodSignature *sig;
1054 MonoMethodHeader *header;
1056 guint32 locals_stack_size, locals_stack_align;
1061 header = cfg->header;
1062 sig = mono_method_signature (cfg->method);
1064 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1066 cfg->frame_reg = X86_EBP;
1069 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1070 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1071 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1074 /* Reserve space to save LMF and caller saved registers */
1076 if (cfg->method->save_lmf) {
1077 /* The LMF var is allocated normally */
1079 if (cfg->used_int_regs & (1 << X86_EBX)) {
1083 if (cfg->used_int_regs & (1 << X86_EDI)) {
1087 if (cfg->used_int_regs & (1 << X86_ESI)) {
1092 switch (cinfo->ret.storage) {
1093 case ArgValuetypeInReg:
1094 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1096 cfg->ret->opcode = OP_REGOFFSET;
1097 cfg->ret->inst_basereg = X86_EBP;
1098 cfg->ret->inst_offset = - offset;
1104 /* Allocate locals */
1105 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1106 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1107 char *mname = mono_method_full_name (cfg->method, TRUE);
1108 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1109 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1113 if (locals_stack_align) {
1114 int prev_offset = offset;
1116 offset += (locals_stack_align - 1);
1117 offset &= ~(locals_stack_align - 1);
1119 while (prev_offset < offset) {
1121 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1124 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1125 cfg->locals_max_stack_offset = - offset;
1127 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1128 * have locals larger than 8 bytes we need to make sure that
1129 * they have the appropriate offset.
1131 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1132 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1133 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1134 if (offsets [i] != -1) {
1135 MonoInst *inst = cfg->varinfo [i];
1136 inst->opcode = OP_REGOFFSET;
1137 inst->inst_basereg = X86_EBP;
1138 inst->inst_offset = - (offset + offsets [i]);
1139 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1142 offset += locals_stack_size;
1146 * Allocate arguments+return value
1149 switch (cinfo->ret.storage) {
1151 if (cfg->vret_addr) {
1153 * In the new IR, the cfg->vret_addr variable represents the
1154 * vtype return value.
1156 cfg->vret_addr->opcode = OP_REGOFFSET;
1157 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1158 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1159 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1160 printf ("vret_addr =");
1161 mono_print_ins (cfg->vret_addr);
1164 cfg->ret->opcode = OP_REGOFFSET;
1165 cfg->ret->inst_basereg = X86_EBP;
1166 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1169 case ArgValuetypeInReg:
1172 cfg->ret->opcode = OP_REGVAR;
1173 cfg->ret->inst_c0 = cinfo->ret.reg;
1174 cfg->ret->dreg = cinfo->ret.reg;
1177 case ArgOnFloatFpStack:
1178 case ArgOnDoubleFpStack:
1181 g_assert_not_reached ();
1184 if (sig->call_convention == MONO_CALL_VARARG) {
1185 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1186 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1189 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1190 ArgInfo *ainfo = &cinfo->args [i];
1191 inst = cfg->args [i];
1192 if (inst->opcode != OP_REGVAR) {
1193 inst->opcode = OP_REGOFFSET;
1194 inst->inst_basereg = X86_EBP;
1196 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1199 cfg->stack_offset = offset;
1203 mono_arch_create_vars (MonoCompile *cfg)
1206 MonoMethodSignature *sig;
1209 sig = mono_method_signature (cfg->method);
1211 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1212 sig_ret = mini_replace_type (sig->ret);
1214 if (cinfo->ret.storage == ArgValuetypeInReg)
1215 cfg->ret_var_is_local = TRUE;
1216 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (cfg, sig_ret))) {
1217 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1220 if (cfg->method->save_lmf) {
1221 cfg->create_lmf_var = TRUE;
1224 cfg->lmf_ir_mono_lmf = TRUE;
1228 cfg->arch_eh_jit_info = 1;
1232 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1233 * so we try to do it just once when we have multiple fp arguments in a row.
1234 * We don't use this mechanism generally because for int arguments the generated code
1235 * is slightly bigger and new generation cpus optimize away the dependency chains
1236 * created by push instructions on the esp value.
1237 * fp_arg_setup is the first argument in the execution sequence where the esp register
1240 static G_GNUC_UNUSED int
1241 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1246 for (; start_arg < sig->param_count; ++start_arg) {
1247 t = mini_replace_type (sig->params [start_arg]);
1248 if (!t->byref && t->type == MONO_TYPE_R8) {
1249 fp_space += sizeof (double);
1250 *fp_arg_setup = start_arg;
1259 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1261 MonoMethodSignature *tmp_sig;
1265 * mono_ArgIterator_Setup assumes the signature cookie is
1266 * passed first and all the arguments which were before it are
1267 * passed on the stack after the signature. So compensate by
1268 * passing a different signature.
1270 tmp_sig = mono_metadata_signature_dup (call->signature);
1271 tmp_sig->param_count -= call->signature->sentinelpos;
1272 tmp_sig->sentinelpos = 0;
1273 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1275 if (cfg->compile_aot) {
1276 sig_reg = mono_alloc_ireg (cfg);
1277 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1278 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1280 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1286 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1291 LLVMCallInfo *linfo;
1292 MonoType *t, *sig_ret;
1294 n = sig->param_count + sig->hasthis;
1296 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1299 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1302 * LLVM always uses the native ABI while we use our own ABI, the
1303 * only difference is the handling of vtypes:
1304 * - we only pass/receive them in registers in some cases, and only
1305 * in 1 or 2 integer registers.
1307 if (cinfo->ret.storage == ArgValuetypeInReg) {
1309 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1310 cfg->disable_llvm = TRUE;
1314 cfg->exception_message = g_strdup ("vtype ret in call");
1315 cfg->disable_llvm = TRUE;
1317 linfo->ret.storage = LLVMArgVtypeInReg;
1318 for (j = 0; j < 2; ++j)
1319 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1323 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage == ArgInIReg) {
1324 /* Vtype returned using a hidden argument */
1325 linfo->ret.storage = LLVMArgVtypeRetAddr;
1326 linfo->vret_arg_index = cinfo->vret_arg_index;
1329 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage != ArgInIReg) {
1331 cfg->exception_message = g_strdup ("vtype ret in call");
1332 cfg->disable_llvm = TRUE;
1335 for (i = 0; i < n; ++i) {
1336 ainfo = cinfo->args + i;
1338 if (i >= sig->hasthis)
1339 t = sig->params [i - sig->hasthis];
1341 t = &mono_defaults.int_class->byval_arg;
1343 linfo->args [i].storage = LLVMArgNone;
1345 switch (ainfo->storage) {
1347 linfo->args [i].storage = LLVMArgInIReg;
1349 case ArgInDoubleSSEReg:
1350 case ArgInFloatSSEReg:
1351 linfo->args [i].storage = LLVMArgInFPReg;
1354 if (mini_type_is_vtype (cfg, t)) {
1355 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1356 /* LLVM seems to allocate argument space for empty structures too */
1357 linfo->args [i].storage = LLVMArgNone;
1359 linfo->args [i].storage = LLVMArgVtypeByVal;
1361 linfo->args [i].storage = LLVMArgInIReg;
1363 if (t->type == MONO_TYPE_R4)
1364 linfo->args [i].storage = LLVMArgInFPReg;
1365 else if (t->type == MONO_TYPE_R8)
1366 linfo->args [i].storage = LLVMArgInFPReg;
1370 case ArgValuetypeInReg:
1372 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1373 cfg->disable_llvm = TRUE;
1377 cfg->exception_message = g_strdup ("vtype arg");
1378 cfg->disable_llvm = TRUE;
1380 linfo->args [i].storage = LLVMArgVtypeInReg;
1381 for (j = 0; j < 2; ++j)
1382 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1386 linfo->args [i].storage = LLVMArgGSharedVt;
1389 cfg->exception_message = g_strdup ("ainfo->storage");
1390 cfg->disable_llvm = TRUE;
1400 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1402 if (cfg->compute_gc_maps) {
1405 /* Needs checking if the feature will be enabled again */
1406 g_assert_not_reached ();
1408 /* On x86, the offsets are from the sp value before the start of the call sequence */
1410 t = &mono_defaults.int_class->byval_arg;
1411 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1416 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1420 MonoMethodSignature *sig;
1423 int sentinelpos = 0, sp_offset = 0;
1425 sig = call->signature;
1426 n = sig->param_count + sig->hasthis;
1427 sig_ret = mini_replace_type (sig->ret);
1429 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1430 call->call_info = cinfo;
1432 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1433 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1435 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1436 if (cinfo->ret.storage == ArgValuetypeInReg) {
1438 * Tell the JIT to use a more efficient calling convention: call using
1439 * OP_CALL, compute the result location after the call, and save the
1442 call->vret_in_reg = TRUE;
1444 NULLIFY_INS (call->vret_var);
1448 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1450 /* Handle the case where there are no implicit arguments */
1451 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1452 emit_sig_cookie (cfg, call, cinfo);
1453 sp_offset = cinfo->sig_cookie.offset;
1454 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1457 /* Arguments are pushed in the reverse order */
1458 for (i = n - 1; i >= 0; i --) {
1459 ArgInfo *ainfo = cinfo->args + i;
1460 MonoType *orig_type, *t;
1463 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1466 /* Push the vret arg before the first argument */
1467 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1468 vtarg->type = STACK_MP;
1469 vtarg->inst_destbasereg = X86_ESP;
1470 vtarg->sreg1 = call->vret_var->dreg;
1471 vtarg->inst_offset = cinfo->ret.offset;
1472 MONO_ADD_INS (cfg->cbb, vtarg);
1473 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1476 if (i >= sig->hasthis)
1477 t = sig->params [i - sig->hasthis];
1479 t = &mono_defaults.int_class->byval_arg;
1481 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1483 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1485 in = call->args [i];
1486 arg->cil_code = in->cil_code;
1487 arg->sreg1 = in->dreg;
1488 arg->type = in->type;
1490 g_assert (in->dreg != -1);
1492 if (ainfo->storage == ArgGSharedVt) {
1493 arg->opcode = OP_OUTARG_VT;
1494 arg->sreg1 = in->dreg;
1495 arg->klass = in->klass;
1496 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1497 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1499 MONO_ADD_INS (cfg->cbb, arg);
1500 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1504 g_assert (in->klass);
1506 if (t->type == MONO_TYPE_TYPEDBYREF) {
1507 size = sizeof (MonoTypedRef);
1508 align = sizeof (gpointer);
1511 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1515 arg->opcode = OP_OUTARG_VT;
1516 arg->sreg1 = in->dreg;
1517 arg->klass = in->klass;
1518 arg->backend.size = size;
1519 arg->inst_p0 = call;
1520 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1521 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1523 MONO_ADD_INS (cfg->cbb, arg);
1524 if (ainfo->storage != ArgValuetypeInReg) {
1525 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1529 switch (ainfo->storage) {
1532 if (t->type == MONO_TYPE_R4) {
1533 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1535 } else if (t->type == MONO_TYPE_R8) {
1536 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1538 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1539 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, in->dreg + 2);
1540 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg + 1);
1543 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1547 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1552 arg->opcode = OP_MOVE;
1553 arg->dreg = ainfo->reg;
1554 MONO_ADD_INS (cfg->cbb, arg);
1558 g_assert_not_reached ();
1561 if (cfg->compute_gc_maps) {
1563 /* FIXME: The == STACK_OBJ check might be fragile ? */
1564 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1566 if (call->need_unbox_trampoline)
1567 /* The unbox trampoline transforms this into a managed pointer */
1568 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.int_class->this_arg);
1570 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.object_class->byval_arg);
1572 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1576 for (j = 0; j < argsize; j += 4)
1577 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1582 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1583 /* Emit the signature cookie just before the implicit arguments */
1584 emit_sig_cookie (cfg, call, cinfo);
1585 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1589 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1592 if (cinfo->ret.storage == ArgValuetypeInReg) {
1595 else if (cinfo->ret.storage == ArgInIReg) {
1597 /* The return address is passed in a register */
1598 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1599 vtarg->sreg1 = call->inst.dreg;
1600 vtarg->dreg = mono_alloc_ireg (cfg);
1601 MONO_ADD_INS (cfg->cbb, vtarg);
1603 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1604 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1605 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1606 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1610 call->stack_usage = cinfo->stack_usage;
1611 call->stack_align_amount = cinfo->stack_align_amount;
1615 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1617 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1618 ArgInfo *ainfo = ins->inst_p1;
1619 int size = ins->backend.size;
1621 if (ainfo->storage == ArgValuetypeInReg) {
1622 int dreg = mono_alloc_ireg (cfg);
1625 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1628 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1631 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1635 g_assert_not_reached ();
1637 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1640 if (cfg->gsharedvt && mini_is_gsharedvt_klass (cfg, ins->klass)) {
1642 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1643 } else if (size <= 4) {
1644 int dreg = mono_alloc_ireg (cfg);
1645 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1646 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1647 } else if (size <= 20) {
1648 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1650 // FIXME: Code growth
1651 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1657 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1659 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1662 if (ret->type == MONO_TYPE_R4) {
1663 if (COMPILE_LLVM (cfg))
1664 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1667 } else if (ret->type == MONO_TYPE_R8) {
1668 if (COMPILE_LLVM (cfg))
1669 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1672 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1673 if (COMPILE_LLVM (cfg))
1674 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1676 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1677 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1683 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1687 * Allow tracing to work with this interface (with an optional argument)
1690 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1694 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1695 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1697 /* if some args are passed in registers, we need to save them here */
1698 x86_push_reg (code, X86_EBP);
1700 if (cfg->compile_aot) {
1701 x86_push_imm (code, cfg->method);
1702 x86_mov_reg_imm (code, X86_EAX, func);
1703 x86_call_reg (code, X86_EAX);
1705 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1706 x86_push_imm (code, cfg->method);
1707 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1708 x86_call_code (code, 0);
1710 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1724 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1727 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1728 MonoMethod *method = cfg->method;
1729 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1731 switch (ret_type->type) {
1732 case MONO_TYPE_VOID:
1733 /* special case string .ctor icall */
1734 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1735 save_mode = SAVE_EAX;
1736 stack_usage = enable_arguments ? 8 : 4;
1738 save_mode = SAVE_NONE;
1742 save_mode = SAVE_EAX_EDX;
1743 stack_usage = enable_arguments ? 16 : 8;
1747 save_mode = SAVE_FP;
1748 stack_usage = enable_arguments ? 16 : 8;
1750 case MONO_TYPE_GENERICINST:
1751 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1752 save_mode = SAVE_EAX;
1753 stack_usage = enable_arguments ? 8 : 4;
1757 case MONO_TYPE_VALUETYPE:
1758 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1759 save_mode = SAVE_STRUCT;
1760 stack_usage = enable_arguments ? 4 : 0;
1763 save_mode = SAVE_EAX;
1764 stack_usage = enable_arguments ? 8 : 4;
1768 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1770 switch (save_mode) {
1772 x86_push_reg (code, X86_EDX);
1773 x86_push_reg (code, X86_EAX);
1774 if (enable_arguments) {
1775 x86_push_reg (code, X86_EDX);
1776 x86_push_reg (code, X86_EAX);
1781 x86_push_reg (code, X86_EAX);
1782 if (enable_arguments) {
1783 x86_push_reg (code, X86_EAX);
1788 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1789 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1790 if (enable_arguments) {
1791 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1792 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1797 if (enable_arguments) {
1798 x86_push_membase (code, X86_EBP, 8);
1807 if (cfg->compile_aot) {
1808 x86_push_imm (code, method);
1809 x86_mov_reg_imm (code, X86_EAX, func);
1810 x86_call_reg (code, X86_EAX);
1812 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1813 x86_push_imm (code, method);
1814 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1815 x86_call_code (code, 0);
1818 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1820 switch (save_mode) {
1822 x86_pop_reg (code, X86_EAX);
1823 x86_pop_reg (code, X86_EDX);
1826 x86_pop_reg (code, X86_EAX);
1829 x86_fld_membase (code, X86_ESP, 0, TRUE);
1830 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1837 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1842 #define EMIT_COND_BRANCH(ins,cond,sign) \
1843 if (ins->inst_true_bb->native_offset) { \
1844 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1846 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1847 if ((cfg->opt & MONO_OPT_BRANCH) && \
1848 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1849 x86_branch8 (code, cond, 0, sign); \
1851 x86_branch32 (code, cond, 0, sign); \
1855 * Emit an exception if condition is fail and
1856 * if possible do a directly branch to target
1858 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1860 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1861 if (tins == NULL) { \
1862 mono_add_patch_info (cfg, code - cfg->native_code, \
1863 MONO_PATCH_INFO_EXC, exc_name); \
1864 x86_branch32 (code, cond, 0, signed); \
1866 EMIT_COND_BRANCH (tins, cond, signed); \
1870 #define EMIT_FPCOMPARE(code) do { \
1871 x86_fcompp (code); \
1872 x86_fnstsw (code); \
1877 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1879 gboolean needs_paddings = TRUE;
1881 MonoJumpInfo *jinfo = NULL;
1883 if (cfg->abs_patches) {
1884 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1885 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1886 needs_paddings = FALSE;
1889 if (cfg->compile_aot)
1890 needs_paddings = FALSE;
1891 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1892 This is required for code patching to be safe on SMP machines.
1894 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1895 #ifndef __native_client_codegen__
1896 if (needs_paddings && pad_size)
1897 x86_padding (code, 4 - pad_size);
1900 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1901 x86_call_code (code, 0);
1906 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1909 * mono_peephole_pass_1:
1911 * Perform peephole opts which should/can be performed before local regalloc
1914 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1918 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1919 MonoInst *last_ins = ins->prev;
1921 switch (ins->opcode) {
1924 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1926 * X86_LEA is like ADD, but doesn't have the
1927 * sreg1==dreg restriction.
1929 ins->opcode = OP_X86_LEA_MEMBASE;
1930 ins->inst_basereg = ins->sreg1;
1931 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1932 ins->opcode = OP_X86_INC_REG;
1936 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1937 ins->opcode = OP_X86_LEA_MEMBASE;
1938 ins->inst_basereg = ins->sreg1;
1939 ins->inst_imm = -ins->inst_imm;
1940 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1941 ins->opcode = OP_X86_DEC_REG;
1943 case OP_COMPARE_IMM:
1944 case OP_ICOMPARE_IMM:
1945 /* OP_COMPARE_IMM (reg, 0)
1947 * OP_X86_TEST_NULL (reg)
1950 ins->opcode = OP_X86_TEST_NULL;
1952 case OP_X86_COMPARE_MEMBASE_IMM:
1954 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1955 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1957 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1958 * OP_COMPARE_IMM reg, imm
1960 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1962 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1963 ins->inst_basereg == last_ins->inst_destbasereg &&
1964 ins->inst_offset == last_ins->inst_offset) {
1965 ins->opcode = OP_COMPARE_IMM;
1966 ins->sreg1 = last_ins->sreg1;
1968 /* check if we can remove cmp reg,0 with test null */
1970 ins->opcode = OP_X86_TEST_NULL;
1974 case OP_X86_PUSH_MEMBASE:
1975 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1976 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1977 ins->inst_basereg == last_ins->inst_destbasereg &&
1978 ins->inst_offset == last_ins->inst_offset) {
1979 ins->opcode = OP_X86_PUSH;
1980 ins->sreg1 = last_ins->sreg1;
1985 mono_peephole_ins (bb, ins);
1990 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1994 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1995 switch (ins->opcode) {
1997 /* reg = 0 -> XOR (reg, reg) */
1998 /* XOR sets cflags on x86, so we cant do it always */
1999 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2002 ins->opcode = OP_IXOR;
2003 ins->sreg1 = ins->dreg;
2004 ins->sreg2 = ins->dreg;
2007 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2008 * since it takes 3 bytes instead of 7.
2010 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2011 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2012 ins2->opcode = OP_STORE_MEMBASE_REG;
2013 ins2->sreg1 = ins->dreg;
2015 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2016 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2017 ins2->sreg1 = ins->dreg;
2019 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2020 /* Continue iteration */
2029 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2030 ins->opcode = OP_X86_INC_REG;
2034 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2035 ins->opcode = OP_X86_DEC_REG;
2039 mono_peephole_ins (bb, ins);
2044 * mono_arch_lowering_pass:
2046 * Converts complex opcodes into simpler ones so that each IR instruction
2047 * corresponds to one machine instruction.
2050 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2052 MonoInst *ins, *next;
2055 * FIXME: Need to add more instructions, but the current machine
2056 * description can't model some parts of the composite instructions like
2059 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2060 switch (ins->opcode) {
2063 case OP_IDIV_UN_IMM:
2064 case OP_IREM_UN_IMM:
2066 * Keep the cases where we could generated optimized code, otherwise convert
2067 * to the non-imm variant.
2069 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2071 mono_decompose_op_imm (cfg, bb, ins);
2078 bb->max_vreg = cfg->next_vreg;
2082 branch_cc_table [] = {
2083 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2084 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2085 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2088 /* Maps CMP_... constants to X86_CC_... constants */
2091 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2092 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2096 cc_signed_table [] = {
2097 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2098 FALSE, FALSE, FALSE, FALSE
2101 static unsigned char*
2102 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2104 #define XMM_TEMP_REG 0
2105 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2106 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2107 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2108 /* optimize by assigning a local var for this use so we avoid
2109 * the stack manipulations */
2110 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2111 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2112 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2113 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2114 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2116 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2118 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2121 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2122 x86_fnstcw_membase(code, X86_ESP, 0);
2123 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2124 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2125 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2126 x86_fldcw_membase (code, X86_ESP, 2);
2128 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2129 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2130 x86_pop_reg (code, dreg);
2131 /* FIXME: need the high register
2132 * x86_pop_reg (code, dreg_high);
2135 x86_push_reg (code, X86_EAX); // SP = SP - 4
2136 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2137 x86_pop_reg (code, dreg);
2139 x86_fldcw_membase (code, X86_ESP, 0);
2140 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2143 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2145 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2149 static unsigned char*
2150 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2152 int sreg = tree->sreg1;
2153 int need_touch = FALSE;
2155 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2164 * If requested stack size is larger than one page,
2165 * perform stack-touch operation
2168 * Generate stack probe code.
2169 * Under Windows, it is necessary to allocate one page at a time,
2170 * "touching" stack after each successful sub-allocation. This is
2171 * because of the way stack growth is implemented - there is a
2172 * guard page before the lowest stack page that is currently commited.
2173 * Stack normally grows sequentially so OS traps access to the
2174 * guard page and commits more pages when needed.
2176 x86_test_reg_imm (code, sreg, ~0xFFF);
2177 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2179 br[2] = code; /* loop */
2180 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2181 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2184 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2185 * that follows only initializes the last part of the area.
2187 /* Same as the init code below with size==0x1000 */
2188 if (tree->flags & MONO_INST_INIT) {
2189 x86_push_reg (code, X86_EAX);
2190 x86_push_reg (code, X86_ECX);
2191 x86_push_reg (code, X86_EDI);
2192 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2193 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2194 if (cfg->param_area)
2195 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2197 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2199 x86_prefix (code, X86_REP_PREFIX);
2201 x86_pop_reg (code, X86_EDI);
2202 x86_pop_reg (code, X86_ECX);
2203 x86_pop_reg (code, X86_EAX);
2206 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2207 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2208 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2209 x86_patch (br[3], br[2]);
2210 x86_test_reg_reg (code, sreg, sreg);
2211 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2212 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2214 br[1] = code; x86_jump8 (code, 0);
2216 x86_patch (br[0], code);
2217 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2218 x86_patch (br[1], code);
2219 x86_patch (br[4], code);
2222 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2224 if (tree->flags & MONO_INST_INIT) {
2226 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2227 x86_push_reg (code, X86_EAX);
2230 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2231 x86_push_reg (code, X86_ECX);
2234 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2235 x86_push_reg (code, X86_EDI);
2239 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2240 if (sreg != X86_ECX)
2241 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2242 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2244 if (cfg->param_area)
2245 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2247 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2249 x86_prefix (code, X86_REP_PREFIX);
2252 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2253 x86_pop_reg (code, X86_EDI);
2254 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2255 x86_pop_reg (code, X86_ECX);
2256 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2257 x86_pop_reg (code, X86_EAX);
2264 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2266 /* Move return value to the target register */
2267 switch (ins->opcode) {
2270 case OP_CALL_MEMBASE:
2271 if (ins->dreg != X86_EAX)
2272 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2282 static int tls_gs_offset;
2286 mono_x86_have_tls_get (void)
2289 static gboolean have_tls_get = FALSE;
2290 static gboolean inited = FALSE;
2294 return have_tls_get;
2296 ins = (guint32*)pthread_getspecific;
2298 * We're looking for these two instructions:
2300 * mov 0x4(%esp),%eax
2301 * mov %gs:[offset](,%eax,4),%eax
2303 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2304 tls_gs_offset = ins [2];
2308 return have_tls_get;
2309 #elif defined(TARGET_ANDROID)
2317 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2319 #if defined(__APPLE__)
2320 x86_prefix (code, X86_GS_PREFIX);
2321 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2322 #elif defined(TARGET_WIN32)
2323 g_assert_not_reached ();
2325 x86_prefix (code, X86_GS_PREFIX);
2326 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2332 * mono_x86_emit_tls_get:
2333 * @code: buffer to store code to
2334 * @dreg: hard register where to place the result
2335 * @tls_offset: offset info
2337 * mono_x86_emit_tls_get emits in @code the native code that puts in
2338 * the dreg register the item in the thread local storage identified
2341 * Returns: a pointer to the end of the stored code
2344 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2346 #if defined(__APPLE__)
2347 x86_prefix (code, X86_GS_PREFIX);
2348 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2349 #elif defined(TARGET_WIN32)
2351 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2352 * Journal and/or a disassembly of the TlsGet () function.
2354 x86_prefix (code, X86_FS_PREFIX);
2355 x86_mov_reg_mem (code, dreg, 0x18, 4);
2356 if (tls_offset < 64) {
2357 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2361 g_assert (tls_offset < 0x440);
2362 /* Load TEB->TlsExpansionSlots */
2363 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2364 x86_test_reg_reg (code, dreg, dreg);
2366 x86_branch (code, X86_CC_EQ, code, TRUE);
2367 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2368 x86_patch (buf [0], code);
2371 if (optimize_for_xen) {
2372 x86_prefix (code, X86_GS_PREFIX);
2373 x86_mov_reg_mem (code, dreg, 0, 4);
2374 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2376 x86_prefix (code, X86_GS_PREFIX);
2377 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2384 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2386 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2387 #if defined(__APPLE__) || defined(__linux__)
2388 if (dreg != offset_reg)
2389 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2390 x86_prefix (code, X86_GS_PREFIX);
2391 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2393 g_assert_not_reached ();
2399 mono_x86_emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2401 return emit_tls_get_reg (code, dreg, offset_reg);
2405 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2407 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2409 g_assert_not_reached ();
2410 #elif defined(__APPLE__) || defined(__linux__)
2411 x86_prefix (code, X86_GS_PREFIX);
2412 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2414 g_assert_not_reached ();
2420 * mono_arch_translate_tls_offset:
2422 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2425 mono_arch_translate_tls_offset (int offset)
2428 return tls_gs_offset + (offset * 4);
2437 * Emit code to initialize an LMF structure at LMF_OFFSET.
2440 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2442 /* save all caller saved regs */
2443 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2444 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2445 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2446 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2447 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2448 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2449 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2451 /* save the current IP */
2452 if (cfg->compile_aot) {
2453 /* This pushes the current ip */
2454 x86_call_imm (code, 0);
2455 x86_pop_reg (code, X86_EAX);
2457 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2458 x86_mov_reg_imm (code, X86_EAX, 0);
2460 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2462 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2463 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2464 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2465 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2466 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2467 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2468 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2469 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2470 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2475 #define REAL_PRINT_REG(text,reg) \
2476 mono_assert (reg >= 0); \
2477 x86_push_reg (code, X86_EAX); \
2478 x86_push_reg (code, X86_EDX); \
2479 x86_push_reg (code, X86_ECX); \
2480 x86_push_reg (code, reg); \
2481 x86_push_imm (code, reg); \
2482 x86_push_imm (code, text " %d %p\n"); \
2483 x86_mov_reg_imm (code, X86_EAX, printf); \
2484 x86_call_reg (code, X86_EAX); \
2485 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2486 x86_pop_reg (code, X86_ECX); \
2487 x86_pop_reg (code, X86_EDX); \
2488 x86_pop_reg (code, X86_EAX);
2490 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2491 #ifdef __native__client_codegen__
2492 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2495 /* benchmark and set based on cpu */
2496 #define LOOP_ALIGNMENT 8
2497 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2501 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2506 guint8 *code = cfg->native_code + cfg->code_len;
2509 if (cfg->opt & MONO_OPT_LOOP) {
2510 int pad, align = LOOP_ALIGNMENT;
2511 /* set alignment depending on cpu */
2512 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2514 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2515 x86_padding (code, pad);
2516 cfg->code_len += pad;
2517 bb->native_offset = cfg->code_len;
2520 #ifdef __native_client_codegen__
2522 /* For Native Client, all indirect call/jump targets must be */
2523 /* 32-byte aligned. Exception handler blocks are jumped to */
2524 /* indirectly as well. */
2525 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2526 (bb->flags & BB_EXCEPTION_HANDLER);
2528 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2529 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2530 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2531 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2532 cfg->code_len += pad;
2533 bb->native_offset = cfg->code_len;
2536 #endif /* __native_client_codegen__ */
2537 if (cfg->verbose_level > 2)
2538 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2540 cpos = bb->max_offset;
2542 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2543 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2544 g_assert (!cfg->compile_aot);
2547 cov->data [bb->dfn].cil_code = bb->cil_code;
2548 /* this is not thread save, but good enough */
2549 x86_inc_mem (code, &cov->data [bb->dfn].count);
2552 offset = code - cfg->native_code;
2554 mono_debug_open_block (cfg, bb, offset);
2556 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2557 x86_breakpoint (code);
2559 MONO_BB_FOR_EACH_INS (bb, ins) {
2560 offset = code - cfg->native_code;
2562 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2564 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2566 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2567 cfg->code_size *= 2;
2568 cfg->native_code = mono_realloc_native_code(cfg);
2569 code = cfg->native_code + offset;
2570 cfg->stat_code_reallocs++;
2573 if (cfg->debug_info)
2574 mono_debug_record_line_number (cfg, ins, offset);
2576 switch (ins->opcode) {
2578 x86_mul_reg (code, ins->sreg2, TRUE);
2581 x86_mul_reg (code, ins->sreg2, FALSE);
2583 case OP_X86_SETEQ_MEMBASE:
2584 case OP_X86_SETNE_MEMBASE:
2585 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2586 ins->inst_basereg, ins->inst_offset, TRUE);
2588 case OP_STOREI1_MEMBASE_IMM:
2589 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2591 case OP_STOREI2_MEMBASE_IMM:
2592 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2594 case OP_STORE_MEMBASE_IMM:
2595 case OP_STOREI4_MEMBASE_IMM:
2596 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2598 case OP_STOREI1_MEMBASE_REG:
2599 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2601 case OP_STOREI2_MEMBASE_REG:
2602 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2604 case OP_STORE_MEMBASE_REG:
2605 case OP_STOREI4_MEMBASE_REG:
2606 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2608 case OP_STORE_MEM_IMM:
2609 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2612 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2616 /* These are created by the cprop pass so they use inst_imm as the source */
2617 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2620 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2623 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2625 case OP_LOAD_MEMBASE:
2626 case OP_LOADI4_MEMBASE:
2627 case OP_LOADU4_MEMBASE:
2628 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2630 case OP_LOADU1_MEMBASE:
2631 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2633 case OP_LOADI1_MEMBASE:
2634 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2636 case OP_LOADU2_MEMBASE:
2637 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2639 case OP_LOADI2_MEMBASE:
2640 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2642 case OP_ICONV_TO_I1:
2644 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2646 case OP_ICONV_TO_I2:
2648 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2650 case OP_ICONV_TO_U1:
2651 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2653 case OP_ICONV_TO_U2:
2654 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2658 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2660 case OP_COMPARE_IMM:
2661 case OP_ICOMPARE_IMM:
2662 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2664 case OP_X86_COMPARE_MEMBASE_REG:
2665 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2667 case OP_X86_COMPARE_MEMBASE_IMM:
2668 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2670 case OP_X86_COMPARE_MEMBASE8_IMM:
2671 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2673 case OP_X86_COMPARE_REG_MEMBASE:
2674 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2676 case OP_X86_COMPARE_MEM_IMM:
2677 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2679 case OP_X86_TEST_NULL:
2680 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2682 case OP_X86_ADD_MEMBASE_IMM:
2683 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2685 case OP_X86_ADD_REG_MEMBASE:
2686 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2688 case OP_X86_SUB_MEMBASE_IMM:
2689 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2691 case OP_X86_SUB_REG_MEMBASE:
2692 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2694 case OP_X86_AND_MEMBASE_IMM:
2695 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2697 case OP_X86_OR_MEMBASE_IMM:
2698 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2700 case OP_X86_XOR_MEMBASE_IMM:
2701 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2703 case OP_X86_ADD_MEMBASE_REG:
2704 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2706 case OP_X86_SUB_MEMBASE_REG:
2707 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2709 case OP_X86_AND_MEMBASE_REG:
2710 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2712 case OP_X86_OR_MEMBASE_REG:
2713 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2715 case OP_X86_XOR_MEMBASE_REG:
2716 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2718 case OP_X86_INC_MEMBASE:
2719 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2721 case OP_X86_INC_REG:
2722 x86_inc_reg (code, ins->dreg);
2724 case OP_X86_DEC_MEMBASE:
2725 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2727 case OP_X86_DEC_REG:
2728 x86_dec_reg (code, ins->dreg);
2730 case OP_X86_MUL_REG_MEMBASE:
2731 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2733 case OP_X86_AND_REG_MEMBASE:
2734 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2736 case OP_X86_OR_REG_MEMBASE:
2737 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2739 case OP_X86_XOR_REG_MEMBASE:
2740 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2743 x86_breakpoint (code);
2745 case OP_RELAXED_NOP:
2746 x86_prefix (code, X86_REP_PREFIX);
2754 case OP_DUMMY_STORE:
2755 case OP_DUMMY_ICONST:
2756 case OP_DUMMY_R8CONST:
2757 case OP_NOT_REACHED:
2760 case OP_SEQ_POINT: {
2763 if (cfg->compile_aot)
2767 * Read from the single stepping trigger page. This will cause a
2768 * SIGSEGV when single stepping is enabled.
2769 * We do this _before_ the breakpoint, so single stepping after
2770 * a breakpoint is hit will step to the next IL offset.
2772 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2773 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2775 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2778 * A placeholder for a possible breakpoint inserted by
2779 * mono_arch_set_breakpoint ().
2781 for (i = 0; i < 6; ++i)
2784 * Add an additional nop so skipping the bp doesn't cause the ip to point
2785 * to another IL offset.
2793 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2797 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2802 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2806 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2811 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2815 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2820 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2824 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2827 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2831 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2835 #if defined( __native_client_codegen__ )
2836 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2837 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2840 * The code is the same for div/rem, the allocator will allocate dreg
2841 * to RAX/RDX as appropriate.
2843 if (ins->sreg2 == X86_EDX) {
2844 /* cdq clobbers this */
2845 x86_push_reg (code, ins->sreg2);
2847 x86_div_membase (code, X86_ESP, 0, TRUE);
2848 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2851 x86_div_reg (code, ins->sreg2, TRUE);
2856 #if defined( __native_client_codegen__ )
2857 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2858 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2860 if (ins->sreg2 == X86_EDX) {
2861 x86_push_reg (code, ins->sreg2);
2862 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2863 x86_div_membase (code, X86_ESP, 0, FALSE);
2864 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2866 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2867 x86_div_reg (code, ins->sreg2, FALSE);
2871 #if defined( __native_client_codegen__ )
2872 if (ins->inst_imm == 0) {
2873 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2874 x86_jump32 (code, 0);
2878 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2880 x86_div_reg (code, ins->sreg2, TRUE);
2883 int power = mono_is_power_of_two (ins->inst_imm);
2885 g_assert (ins->sreg1 == X86_EAX);
2886 g_assert (ins->dreg == X86_EAX);
2887 g_assert (power >= 0);
2890 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2892 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2894 * If the divident is >= 0, this does not nothing. If it is positive, it
2895 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2897 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2898 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2899 } else if (power == 0) {
2900 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2902 /* Based on gcc code */
2904 /* Add compensation for negative dividents */
2906 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2907 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2908 /* Compute remainder */
2909 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2910 /* Remove compensation */
2911 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2916 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2920 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2923 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2927 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2930 g_assert (ins->sreg2 == X86_ECX);
2931 x86_shift_reg (code, X86_SHL, ins->dreg);
2934 g_assert (ins->sreg2 == X86_ECX);
2935 x86_shift_reg (code, X86_SAR, ins->dreg);
2939 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2942 case OP_ISHR_UN_IMM:
2943 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2946 g_assert (ins->sreg2 == X86_ECX);
2947 x86_shift_reg (code, X86_SHR, ins->dreg);
2951 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2954 guint8 *jump_to_end;
2956 /* handle shifts below 32 bits */
2957 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2958 x86_shift_reg (code, X86_SHL, ins->sreg1);
2960 x86_test_reg_imm (code, X86_ECX, 32);
2961 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2963 /* handle shift over 32 bit */
2964 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2965 x86_clear_reg (code, ins->sreg1);
2967 x86_patch (jump_to_end, code);
2971 guint8 *jump_to_end;
2973 /* handle shifts below 32 bits */
2974 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2975 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2977 x86_test_reg_imm (code, X86_ECX, 32);
2978 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2980 /* handle shifts over 31 bits */
2981 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2982 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2984 x86_patch (jump_to_end, code);
2988 guint8 *jump_to_end;
2990 /* handle shifts below 32 bits */
2991 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2992 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2994 x86_test_reg_imm (code, X86_ECX, 32);
2995 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2997 /* handle shifts over 31 bits */
2998 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2999 x86_clear_reg (code, ins->backend.reg3);
3001 x86_patch (jump_to_end, code);
3005 if (ins->inst_imm >= 32) {
3006 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3007 x86_clear_reg (code, ins->sreg1);
3008 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
3010 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
3011 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
3015 if (ins->inst_imm >= 32) {
3016 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3017 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
3018 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
3020 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3021 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3024 case OP_LSHR_UN_IMM:
3025 if (ins->inst_imm >= 32) {
3026 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3027 x86_clear_reg (code, ins->backend.reg3);
3028 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3030 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3031 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3035 x86_not_reg (code, ins->sreg1);
3038 x86_neg_reg (code, ins->sreg1);
3042 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3046 switch (ins->inst_imm) {
3050 if (ins->dreg != ins->sreg1)
3051 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3052 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3055 /* LEA r1, [r2 + r2*2] */
3056 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3059 /* LEA r1, [r2 + r2*4] */
3060 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3063 /* LEA r1, [r2 + r2*2] */
3065 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3066 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3069 /* LEA r1, [r2 + r2*8] */
3070 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3073 /* LEA r1, [r2 + r2*4] */
3075 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3076 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3079 /* LEA r1, [r2 + r2*2] */
3081 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3082 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3085 /* LEA r1, [r2 + r2*4] */
3086 /* LEA r1, [r1 + r1*4] */
3087 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3088 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3091 /* LEA r1, [r2 + r2*4] */
3093 /* LEA r1, [r1 + r1*4] */
3094 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3095 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3096 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3099 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3104 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3105 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3107 case OP_IMUL_OVF_UN: {
3108 /* the mul operation and the exception check should most likely be split */
3109 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3110 /*g_assert (ins->sreg2 == X86_EAX);
3111 g_assert (ins->dreg == X86_EAX);*/
3112 if (ins->sreg2 == X86_EAX) {
3113 non_eax_reg = ins->sreg1;
3114 } else if (ins->sreg1 == X86_EAX) {
3115 non_eax_reg = ins->sreg2;
3117 /* no need to save since we're going to store to it anyway */
3118 if (ins->dreg != X86_EAX) {
3120 x86_push_reg (code, X86_EAX);
3122 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3123 non_eax_reg = ins->sreg2;
3125 if (ins->dreg == X86_EDX) {
3128 x86_push_reg (code, X86_EAX);
3130 } else if (ins->dreg != X86_EAX) {
3132 x86_push_reg (code, X86_EDX);
3134 x86_mul_reg (code, non_eax_reg, FALSE);
3135 /* save before the check since pop and mov don't change the flags */
3136 if (ins->dreg != X86_EAX)
3137 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3139 x86_pop_reg (code, X86_EDX);
3141 x86_pop_reg (code, X86_EAX);
3142 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3146 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3149 g_assert_not_reached ();
3150 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3151 x86_mov_reg_imm (code, ins->dreg, 0);
3154 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3155 x86_mov_reg_imm (code, ins->dreg, 0);
3157 case OP_LOAD_GOTADDR:
3158 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3159 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3162 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3163 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3165 case OP_X86_PUSH_GOT_ENTRY:
3166 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3167 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3170 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3173 MonoCallInst *call = (MonoCallInst*)ins;
3176 ins->flags |= MONO_INST_GC_CALLSITE;
3177 ins->backend.pc_offset = code - cfg->native_code;
3179 /* reset offset to make max_len work */
3180 offset = code - cfg->native_code;
3182 g_assert (!cfg->method->save_lmf);
3184 /* restore callee saved registers */
3185 for (i = 0; i < X86_NREG; ++i)
3186 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3188 if (cfg->used_int_regs & (1 << X86_ESI)) {
3189 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3192 if (cfg->used_int_regs & (1 << X86_EDI)) {
3193 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3196 if (cfg->used_int_regs & (1 << X86_EBX)) {
3197 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3201 /* Copy arguments on the stack to our argument area */
3202 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3203 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3204 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3207 /* restore ESP/EBP */
3209 offset = code - cfg->native_code;
3210 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3211 x86_jump32 (code, 0);
3213 ins->flags |= MONO_INST_GC_CALLSITE;
3214 cfg->disable_aot = TRUE;
3218 /* ensure ins->sreg1 is not NULL
3219 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3220 * cmp DWORD PTR [eax], 0
3222 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3225 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3226 x86_push_reg (code, hreg);
3227 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3228 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3229 x86_pop_reg (code, hreg);
3242 case OP_VOIDCALL_REG:
3244 case OP_FCALL_MEMBASE:
3245 case OP_LCALL_MEMBASE:
3246 case OP_VCALL_MEMBASE:
3247 case OP_VCALL2_MEMBASE:
3248 case OP_VOIDCALL_MEMBASE:
3249 case OP_CALL_MEMBASE: {
3252 call = (MonoCallInst*)ins;
3253 cinfo = (CallInfo*)call->call_info;
3255 switch (ins->opcode) {
3262 if (ins->flags & MONO_INST_HAS_METHOD)
3263 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3265 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3271 case OP_VOIDCALL_REG:
3273 x86_call_reg (code, ins->sreg1);
3275 case OP_FCALL_MEMBASE:
3276 case OP_LCALL_MEMBASE:
3277 case OP_VCALL_MEMBASE:
3278 case OP_VCALL2_MEMBASE:
3279 case OP_VOIDCALL_MEMBASE:
3280 case OP_CALL_MEMBASE:
3281 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3284 g_assert_not_reached ();
3287 ins->flags |= MONO_INST_GC_CALLSITE;
3288 ins->backend.pc_offset = code - cfg->native_code;
3289 if (cinfo->callee_stack_pop) {
3290 /* Have to compensate for the stack space popped by the callee */
3291 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3293 code = emit_move_return_value (cfg, ins, code);
3297 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3299 case OP_X86_LEA_MEMBASE:
3300 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3303 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3306 /* keep alignment */
3307 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3308 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3309 code = mono_emit_stack_alloc (cfg, code, ins);
3310 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3311 if (cfg->param_area)
3312 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3314 case OP_LOCALLOC_IMM: {
3315 guint32 size = ins->inst_imm;
3316 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3318 if (ins->flags & MONO_INST_INIT) {
3319 /* FIXME: Optimize this */
3320 x86_mov_reg_imm (code, ins->dreg, size);
3321 ins->sreg1 = ins->dreg;
3323 code = mono_emit_stack_alloc (cfg, code, ins);
3324 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3326 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3327 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3329 if (cfg->param_area)
3330 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3334 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3335 x86_push_reg (code, ins->sreg1);
3336 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3337 (gpointer)"mono_arch_throw_exception");
3338 ins->flags |= MONO_INST_GC_CALLSITE;
3339 ins->backend.pc_offset = code - cfg->native_code;
3343 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3344 x86_push_reg (code, ins->sreg1);
3345 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3346 (gpointer)"mono_arch_rethrow_exception");
3347 ins->flags |= MONO_INST_GC_CALLSITE;
3348 ins->backend.pc_offset = code - cfg->native_code;
3351 case OP_CALL_HANDLER:
3352 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3353 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3354 x86_call_imm (code, 0);
3355 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3356 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3358 case OP_START_HANDLER: {
3359 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3360 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3361 if (cfg->param_area)
3362 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3365 case OP_ENDFINALLY: {
3366 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3367 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3371 case OP_ENDFILTER: {
3372 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3373 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3374 /* The local allocator will put the result into EAX */
3380 ins->inst_c0 = code - cfg->native_code;
3383 if (ins->inst_target_bb->native_offset) {
3384 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3386 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3387 if ((cfg->opt & MONO_OPT_BRANCH) &&
3388 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3389 x86_jump8 (code, 0);
3391 x86_jump32 (code, 0);
3395 x86_jump_reg (code, ins->sreg1);
3414 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3415 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3417 case OP_COND_EXC_EQ:
3418 case OP_COND_EXC_NE_UN:
3419 case OP_COND_EXC_LT:
3420 case OP_COND_EXC_LT_UN:
3421 case OP_COND_EXC_GT:
3422 case OP_COND_EXC_GT_UN:
3423 case OP_COND_EXC_GE:
3424 case OP_COND_EXC_GE_UN:
3425 case OP_COND_EXC_LE:
3426 case OP_COND_EXC_LE_UN:
3427 case OP_COND_EXC_IEQ:
3428 case OP_COND_EXC_INE_UN:
3429 case OP_COND_EXC_ILT:
3430 case OP_COND_EXC_ILT_UN:
3431 case OP_COND_EXC_IGT:
3432 case OP_COND_EXC_IGT_UN:
3433 case OP_COND_EXC_IGE:
3434 case OP_COND_EXC_IGE_UN:
3435 case OP_COND_EXC_ILE:
3436 case OP_COND_EXC_ILE_UN:
3437 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3439 case OP_COND_EXC_OV:
3440 case OP_COND_EXC_NO:
3442 case OP_COND_EXC_NC:
3443 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3445 case OP_COND_EXC_IOV:
3446 case OP_COND_EXC_INO:
3447 case OP_COND_EXC_IC:
3448 case OP_COND_EXC_INC:
3449 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3461 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3469 case OP_CMOV_INE_UN:
3470 case OP_CMOV_IGE_UN:
3471 case OP_CMOV_IGT_UN:
3472 case OP_CMOV_ILE_UN:
3473 case OP_CMOV_ILT_UN:
3474 g_assert (ins->dreg == ins->sreg1);
3475 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3478 /* floating point opcodes */
3480 double d = *(double *)ins->inst_p0;
3482 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3484 } else if (d == 1.0) {
3487 if (cfg->compile_aot) {
3488 guint32 *val = (guint32*)&d;
3489 x86_push_imm (code, val [1]);
3490 x86_push_imm (code, val [0]);
3491 x86_fld_membase (code, X86_ESP, 0, TRUE);
3492 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3495 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3496 x86_fld (code, NULL, TRUE);
3502 float f = *(float *)ins->inst_p0;
3504 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3506 } else if (f == 1.0) {
3509 if (cfg->compile_aot) {
3510 guint32 val = *(guint32*)&f;
3511 x86_push_imm (code, val);
3512 x86_fld_membase (code, X86_ESP, 0, FALSE);
3513 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3516 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3517 x86_fld (code, NULL, FALSE);
3522 case OP_STORER8_MEMBASE_REG:
3523 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3525 case OP_LOADR8_MEMBASE:
3526 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3528 case OP_STORER4_MEMBASE_REG:
3529 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3531 case OP_LOADR4_MEMBASE:
3532 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3534 case OP_ICONV_TO_R4:
3535 x86_push_reg (code, ins->sreg1);
3536 x86_fild_membase (code, X86_ESP, 0, FALSE);
3537 /* Change precision */
3538 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3539 x86_fld_membase (code, X86_ESP, 0, FALSE);
3540 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3542 case OP_ICONV_TO_R8:
3543 x86_push_reg (code, ins->sreg1);
3544 x86_fild_membase (code, X86_ESP, 0, FALSE);
3545 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3547 case OP_ICONV_TO_R_UN:
3548 x86_push_imm (code, 0);
3549 x86_push_reg (code, ins->sreg1);
3550 x86_fild_membase (code, X86_ESP, 0, TRUE);
3551 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3553 case OP_X86_FP_LOAD_I8:
3554 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3556 case OP_X86_FP_LOAD_I4:
3557 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3559 case OP_FCONV_TO_R4:
3560 /* Change precision */
3561 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3562 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3563 x86_fld_membase (code, X86_ESP, 0, FALSE);
3564 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3566 case OP_FCONV_TO_I1:
3567 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3569 case OP_FCONV_TO_U1:
3570 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3572 case OP_FCONV_TO_I2:
3573 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3575 case OP_FCONV_TO_U2:
3576 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3578 case OP_FCONV_TO_I4:
3580 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3582 case OP_FCONV_TO_I8:
3583 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3584 x86_fnstcw_membase(code, X86_ESP, 0);
3585 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3586 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3587 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3588 x86_fldcw_membase (code, X86_ESP, 2);
3589 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3590 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3591 x86_pop_reg (code, ins->dreg);
3592 x86_pop_reg (code, ins->backend.reg3);
3593 x86_fldcw_membase (code, X86_ESP, 0);
3594 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3596 case OP_LCONV_TO_R8_2:
3597 x86_push_reg (code, ins->sreg2);
3598 x86_push_reg (code, ins->sreg1);
3599 x86_fild_membase (code, X86_ESP, 0, TRUE);
3600 /* Change precision */
3601 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3602 x86_fld_membase (code, X86_ESP, 0, TRUE);
3603 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3605 case OP_LCONV_TO_R4_2:
3606 x86_push_reg (code, ins->sreg2);
3607 x86_push_reg (code, ins->sreg1);
3608 x86_fild_membase (code, X86_ESP, 0, TRUE);
3609 /* Change precision */
3610 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3611 x86_fld_membase (code, X86_ESP, 0, FALSE);
3612 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3614 case OP_LCONV_TO_R_UN_2: {
3615 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3618 /* load 64bit integer to FP stack */
3619 x86_push_reg (code, ins->sreg2);
3620 x86_push_reg (code, ins->sreg1);
3621 x86_fild_membase (code, X86_ESP, 0, TRUE);
3623 /* test if lreg is negative */
3624 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3625 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3627 /* add correction constant mn */
3628 if (cfg->compile_aot) {
3629 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3630 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3631 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3632 x86_fld80_membase (code, X86_ESP, 2);
3633 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3635 x86_fld80_mem (code, mn);
3637 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3639 x86_patch (br, code);
3641 /* Change precision */
3642 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3643 x86_fld_membase (code, X86_ESP, 0, TRUE);
3645 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3649 case OP_LCONV_TO_OVF_I:
3650 case OP_LCONV_TO_OVF_I4_2: {
3651 guint8 *br [3], *label [1];
3655 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3657 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3659 /* If the low word top bit is set, see if we are negative */
3660 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3661 /* We are not negative (no top bit set, check for our top word to be zero */
3662 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3663 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3666 /* throw exception */
3667 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3669 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3670 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3671 x86_jump8 (code, 0);
3673 x86_jump32 (code, 0);
3675 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3676 x86_jump32 (code, 0);
3680 x86_patch (br [0], code);
3681 /* our top bit is set, check that top word is 0xfffffff */
3682 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3684 x86_patch (br [1], code);
3685 /* nope, emit exception */
3686 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3687 x86_patch (br [2], label [0]);
3689 if (ins->dreg != ins->sreg1)
3690 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3694 /* Not needed on the fp stack */
3697 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3700 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3703 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3706 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3714 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3719 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3726 * it really doesn't make sense to inline all this code,
3727 * it's here just to show that things may not be as simple
3730 guchar *check_pos, *end_tan, *pop_jump;
3731 x86_push_reg (code, X86_EAX);
3734 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3736 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3737 x86_fstp (code, 0); /* pop the 1.0 */
3739 x86_jump8 (code, 0);
3741 x86_fp_op (code, X86_FADD, 0);
3745 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3747 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3750 x86_patch (pop_jump, code);
3751 x86_fstp (code, 0); /* pop the 1.0 */
3752 x86_patch (check_pos, code);
3753 x86_patch (end_tan, code);
3755 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3756 x86_pop_reg (code, X86_EAX);
3763 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3772 g_assert (cfg->opt & MONO_OPT_CMOV);
3773 g_assert (ins->dreg == ins->sreg1);
3774 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3775 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3778 g_assert (cfg->opt & MONO_OPT_CMOV);
3779 g_assert (ins->dreg == ins->sreg1);
3780 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3781 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3784 g_assert (cfg->opt & MONO_OPT_CMOV);
3785 g_assert (ins->dreg == ins->sreg1);
3786 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3787 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3790 g_assert (cfg->opt & MONO_OPT_CMOV);
3791 g_assert (ins->dreg == ins->sreg1);
3792 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3793 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3799 x86_fxch (code, ins->inst_imm);
3804 x86_push_reg (code, X86_EAX);
3805 /* we need to exchange ST(0) with ST(1) */
3808 /* this requires a loop, because fprem somtimes
3809 * returns a partial remainder */
3811 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3812 /* x86_fprem1 (code); */
3815 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3817 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3823 x86_pop_reg (code, X86_EAX);
3827 if (cfg->opt & MONO_OPT_FCMOV) {
3828 x86_fcomip (code, 1);
3832 /* this overwrites EAX */
3833 EMIT_FPCOMPARE(code);
3834 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3838 if (cfg->opt & MONO_OPT_FCMOV) {
3839 /* zeroing the register at the start results in
3840 * shorter and faster code (we can also remove the widening op)
3842 guchar *unordered_check;
3843 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3844 x86_fcomip (code, 1);
3846 unordered_check = code;
3847 x86_branch8 (code, X86_CC_P, 0, FALSE);
3848 if (ins->opcode == OP_FCEQ) {
3849 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3850 x86_patch (unordered_check, code);
3852 guchar *jump_to_end;
3853 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3855 x86_jump8 (code, 0);
3856 x86_patch (unordered_check, code);
3857 x86_inc_reg (code, ins->dreg);
3858 x86_patch (jump_to_end, code);
3863 if (ins->dreg != X86_EAX)
3864 x86_push_reg (code, X86_EAX);
3866 EMIT_FPCOMPARE(code);
3867 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3868 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3869 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3870 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3872 if (ins->dreg != X86_EAX)
3873 x86_pop_reg (code, X86_EAX);
3877 if (cfg->opt & MONO_OPT_FCMOV) {
3878 /* zeroing the register at the start results in
3879 * shorter and faster code (we can also remove the widening op)
3881 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3882 x86_fcomip (code, 1);
3884 if (ins->opcode == OP_FCLT_UN) {
3885 guchar *unordered_check = code;
3886 guchar *jump_to_end;
3887 x86_branch8 (code, X86_CC_P, 0, FALSE);
3888 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3890 x86_jump8 (code, 0);
3891 x86_patch (unordered_check, code);
3892 x86_inc_reg (code, ins->dreg);
3893 x86_patch (jump_to_end, code);
3895 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3899 if (ins->dreg != X86_EAX)
3900 x86_push_reg (code, X86_EAX);
3902 EMIT_FPCOMPARE(code);
3903 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3904 if (ins->opcode == OP_FCLT_UN) {
3905 guchar *is_not_zero_check, *end_jump;
3906 is_not_zero_check = code;
3907 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3909 x86_jump8 (code, 0);
3910 x86_patch (is_not_zero_check, code);
3911 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3913 x86_patch (end_jump, code);
3915 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3916 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3918 if (ins->dreg != X86_EAX)
3919 x86_pop_reg (code, X86_EAX);
3922 guchar *unordered_check;
3923 guchar *jump_to_end;
3924 if (cfg->opt & MONO_OPT_FCMOV) {
3925 /* zeroing the register at the start results in
3926 * shorter and faster code (we can also remove the widening op)
3928 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3929 x86_fcomip (code, 1);
3931 unordered_check = code;
3932 x86_branch8 (code, X86_CC_P, 0, FALSE);
3933 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3934 x86_patch (unordered_check, code);
3937 if (ins->dreg != X86_EAX)
3938 x86_push_reg (code, X86_EAX);
3940 EMIT_FPCOMPARE(code);
3941 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3942 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3943 unordered_check = code;
3944 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3946 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3947 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3948 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3950 x86_jump8 (code, 0);
3951 x86_patch (unordered_check, code);
3952 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3953 x86_patch (jump_to_end, code);
3955 if (ins->dreg != X86_EAX)
3956 x86_pop_reg (code, X86_EAX);
3961 if (cfg->opt & MONO_OPT_FCMOV) {
3962 /* zeroing the register at the start results in
3963 * shorter and faster code (we can also remove the widening op)
3965 guchar *unordered_check;
3966 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3967 x86_fcomip (code, 1);
3969 if (ins->opcode == OP_FCGT) {
3970 unordered_check = code;
3971 x86_branch8 (code, X86_CC_P, 0, FALSE);
3972 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3973 x86_patch (unordered_check, code);
3975 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3979 if (ins->dreg != X86_EAX)
3980 x86_push_reg (code, X86_EAX);
3982 EMIT_FPCOMPARE(code);
3983 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3984 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3985 if (ins->opcode == OP_FCGT_UN) {
3986 guchar *is_not_zero_check, *end_jump;
3987 is_not_zero_check = code;
3988 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3990 x86_jump8 (code, 0);
3991 x86_patch (is_not_zero_check, code);
3992 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3994 x86_patch (end_jump, code);
3996 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3997 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3999 if (ins->dreg != X86_EAX)
4000 x86_pop_reg (code, X86_EAX);
4003 guchar *unordered_check;
4004 guchar *jump_to_end;
4005 if (cfg->opt & MONO_OPT_FCMOV) {
4006 /* zeroing the register at the start results in
4007 * shorter and faster code (we can also remove the widening op)
4009 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4010 x86_fcomip (code, 1);
4012 unordered_check = code;
4013 x86_branch8 (code, X86_CC_P, 0, FALSE);
4014 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4015 x86_patch (unordered_check, code);
4018 if (ins->dreg != X86_EAX)
4019 x86_push_reg (code, X86_EAX);
4021 EMIT_FPCOMPARE(code);
4022 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4023 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4024 unordered_check = code;
4025 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4027 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4028 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4029 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4031 x86_jump8 (code, 0);
4032 x86_patch (unordered_check, code);
4033 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4034 x86_patch (jump_to_end, code);
4036 if (ins->dreg != X86_EAX)
4037 x86_pop_reg (code, X86_EAX);
4041 if (cfg->opt & MONO_OPT_FCMOV) {
4042 guchar *jump = code;
4043 x86_branch8 (code, X86_CC_P, 0, TRUE);
4044 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4045 x86_patch (jump, code);
4048 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4049 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4052 /* Branch if C013 != 100 */
4053 if (cfg->opt & MONO_OPT_FCMOV) {
4054 /* branch if !ZF or (PF|CF) */
4055 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4056 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4057 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4060 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4061 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4064 if (cfg->opt & MONO_OPT_FCMOV) {
4065 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4068 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4071 if (cfg->opt & MONO_OPT_FCMOV) {
4072 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4073 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4076 if (ins->opcode == OP_FBLT_UN) {
4077 guchar *is_not_zero_check, *end_jump;
4078 is_not_zero_check = code;
4079 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4081 x86_jump8 (code, 0);
4082 x86_patch (is_not_zero_check, code);
4083 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4085 x86_patch (end_jump, code);
4087 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4091 if (cfg->opt & MONO_OPT_FCMOV) {
4092 if (ins->opcode == OP_FBGT) {
4095 /* skip branch if C1=1 */
4097 x86_branch8 (code, X86_CC_P, 0, FALSE);
4098 /* branch if (C0 | C3) = 1 */
4099 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4100 x86_patch (br1, code);
4102 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4106 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4107 if (ins->opcode == OP_FBGT_UN) {
4108 guchar *is_not_zero_check, *end_jump;
4109 is_not_zero_check = code;
4110 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4112 x86_jump8 (code, 0);
4113 x86_patch (is_not_zero_check, code);
4114 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4116 x86_patch (end_jump, code);
4118 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4121 /* Branch if C013 == 100 or 001 */
4122 if (cfg->opt & MONO_OPT_FCMOV) {
4125 /* skip branch if C1=1 */
4127 x86_branch8 (code, X86_CC_P, 0, FALSE);
4128 /* branch if (C0 | C3) = 1 */
4129 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4130 x86_patch (br1, code);
4133 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4134 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4135 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4136 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4139 /* Branch if C013 == 000 */
4140 if (cfg->opt & MONO_OPT_FCMOV) {
4141 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4144 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4147 /* Branch if C013=000 or 100 */
4148 if (cfg->opt & MONO_OPT_FCMOV) {
4151 /* skip branch if C1=1 */
4153 x86_branch8 (code, X86_CC_P, 0, FALSE);
4154 /* branch if C0=0 */
4155 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4156 x86_patch (br1, code);
4159 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4160 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4161 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4164 /* Branch if C013 != 001 */
4165 if (cfg->opt & MONO_OPT_FCMOV) {
4166 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4167 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4170 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4171 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4175 x86_push_reg (code, X86_EAX);
4178 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4179 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4180 x86_pop_reg (code, X86_EAX);
4182 /* Have to clean up the fp stack before throwing the exception */
4184 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4187 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4189 x86_patch (br1, code);
4193 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4196 case OP_TLS_GET_REG: {
4197 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4201 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4204 case OP_TLS_SET_REG: {
4205 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4208 case OP_MEMORY_BARRIER: {
4209 /* x86 only needs barrier for StoreLoad and FullBarrier */
4210 switch (ins->backend.memory_barrier_kind) {
4211 case StoreLoadBarrier:
4213 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4214 x86_prefix (code, X86_LOCK_PREFIX);
4215 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4220 case OP_ATOMIC_ADD_I4: {
4221 int dreg = ins->dreg;
4223 g_assert (cfg->has_atomic_add_i4);
4225 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4226 if (ins->sreg2 == dreg) {
4227 if (dreg == X86_EBX) {
4229 if (ins->inst_basereg == X86_EDI)
4233 if (ins->inst_basereg == X86_EBX)
4236 } else if (ins->inst_basereg == dreg) {
4237 if (dreg == X86_EBX) {
4239 if (ins->sreg2 == X86_EDI)
4243 if (ins->sreg2 == X86_EBX)
4248 if (dreg != ins->dreg) {
4249 x86_push_reg (code, dreg);
4252 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4253 x86_prefix (code, X86_LOCK_PREFIX);
4254 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4255 /* dreg contains the old value, add with sreg2 value */
4256 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4258 if (ins->dreg != dreg) {
4259 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4260 x86_pop_reg (code, dreg);
4265 case OP_ATOMIC_EXCHANGE_I4: {
4267 int sreg2 = ins->sreg2;
4268 int breg = ins->inst_basereg;
4270 g_assert (cfg->has_atomic_exchange_i4);
4272 /* cmpxchg uses eax as comperand, need to make sure we can use it
4273 * hack to overcome limits in x86 reg allocator
4274 * (req: dreg == eax and sreg2 != eax and breg != eax)
4276 g_assert (ins->dreg == X86_EAX);
4278 /* We need the EAX reg for the cmpxchg */
4279 if (ins->sreg2 == X86_EAX) {
4280 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4281 x86_push_reg (code, sreg2);
4282 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4285 if (breg == X86_EAX) {
4286 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4287 x86_push_reg (code, breg);
4288 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4291 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4293 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4294 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4295 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4296 x86_patch (br [1], br [0]);
4298 if (breg != ins->inst_basereg)
4299 x86_pop_reg (code, breg);
4301 if (ins->sreg2 != sreg2)
4302 x86_pop_reg (code, sreg2);
4306 case OP_ATOMIC_CAS_I4: {
4307 g_assert (ins->dreg == X86_EAX);
4308 g_assert (ins->sreg3 == X86_EAX);
4309 g_assert (ins->sreg1 != X86_EAX);
4310 g_assert (ins->sreg1 != ins->sreg2);
4312 x86_prefix (code, X86_LOCK_PREFIX);
4313 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4316 case OP_CARD_TABLE_WBARRIER: {
4317 int ptr = ins->sreg1;
4318 int value = ins->sreg2;
4320 int nursery_shift, card_table_shift;
4321 gpointer card_table_mask;
4322 size_t nursery_size;
4323 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4324 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4325 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4328 * We need one register we can clobber, we choose EDX and make sreg1
4329 * fixed EAX to work around limitations in the local register allocator.
4330 * sreg2 might get allocated to EDX, but that is not a problem since
4331 * we use it before clobbering EDX.
4333 g_assert (ins->sreg1 == X86_EAX);
4336 * This is the code we produce:
4339 * edx >>= nursery_shift
4340 * cmp edx, (nursery_start >> nursery_shift)
4343 * edx >>= card_table_shift
4344 * card_table[edx] = 1
4348 if (card_table_nursery_check) {
4349 if (value != X86_EDX)
4350 x86_mov_reg_reg (code, X86_EDX, value, 4);
4351 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4352 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4353 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4355 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4356 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4357 if (card_table_mask)
4358 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4359 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4360 if (card_table_nursery_check)
4361 x86_patch (br, code);
4364 #ifdef MONO_ARCH_SIMD_INTRINSICS
4366 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4369 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4372 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4375 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4378 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4381 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4384 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4385 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4388 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4391 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4394 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4397 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4400 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4403 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4406 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4409 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4412 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4415 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4418 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4421 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4424 case OP_PSHUFLEW_HIGH:
4425 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4426 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4428 case OP_PSHUFLEW_LOW:
4429 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4430 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4433 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4434 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4437 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4438 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4441 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4442 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4446 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4449 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4452 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4455 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4458 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4461 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4464 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4465 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4468 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4471 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4474 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4477 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4480 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4483 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4486 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4489 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4492 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4495 case OP_EXTRACT_MASK:
4496 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4500 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4503 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4506 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4510 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4513 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4516 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4519 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4523 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4526 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4529 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4532 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4536 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4539 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4542 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4546 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4549 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4552 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4556 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4559 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4563 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4566 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4569 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4573 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4576 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4579 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4583 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4586 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4589 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4592 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4596 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4599 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4602 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4605 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4608 case OP_PSUM_ABS_DIFF:
4609 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4612 case OP_UNPACK_LOWB:
4613 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4615 case OP_UNPACK_LOWW:
4616 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4618 case OP_UNPACK_LOWD:
4619 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4621 case OP_UNPACK_LOWQ:
4622 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4624 case OP_UNPACK_LOWPS:
4625 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4627 case OP_UNPACK_LOWPD:
4628 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4631 case OP_UNPACK_HIGHB:
4632 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4634 case OP_UNPACK_HIGHW:
4635 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4637 case OP_UNPACK_HIGHD:
4638 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4640 case OP_UNPACK_HIGHQ:
4641 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4643 case OP_UNPACK_HIGHPS:
4644 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4646 case OP_UNPACK_HIGHPD:
4647 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4651 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4654 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4657 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4660 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4663 case OP_PADDB_SAT_UN:
4664 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4666 case OP_PSUBB_SAT_UN:
4667 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4669 case OP_PADDW_SAT_UN:
4670 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4672 case OP_PSUBW_SAT_UN:
4673 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4677 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4680 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4683 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4686 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4690 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4693 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4696 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4698 case OP_PMULW_HIGH_UN:
4699 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4702 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4706 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4709 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4713 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4716 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4720 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4723 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4727 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4730 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4734 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4737 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4741 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4744 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4748 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4751 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4755 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4758 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4762 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4765 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4769 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4771 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4772 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4776 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4778 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4779 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4783 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4785 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4786 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4790 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4792 case OP_EXTRACTX_U2:
4793 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4795 case OP_INSERTX_U1_SLOW:
4796 /*sreg1 is the extracted ireg (scratch)
4797 /sreg2 is the to be inserted ireg (scratch)
4798 /dreg is the xreg to receive the value*/
4800 /*clear the bits from the extracted word*/
4801 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4802 /*shift the value to insert if needed*/
4803 if (ins->inst_c0 & 1)
4804 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4805 /*join them together*/
4806 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4807 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4809 case OP_INSERTX_I4_SLOW:
4810 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4811 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4812 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4815 case OP_INSERTX_R4_SLOW:
4816 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4817 /*TODO if inst_c0 == 0 use movss*/
4818 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4819 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4821 case OP_INSERTX_R8_SLOW:
4822 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4823 if (cfg->verbose_level)
4824 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4826 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4828 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4831 case OP_STOREX_MEMBASE_REG:
4832 case OP_STOREX_MEMBASE:
4833 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4835 case OP_LOADX_MEMBASE:
4836 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4838 case OP_LOADX_ALIGNED_MEMBASE:
4839 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4841 case OP_STOREX_ALIGNED_MEMBASE_REG:
4842 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4844 case OP_STOREX_NTA_MEMBASE_REG:
4845 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4847 case OP_PREFETCH_MEMBASE:
4848 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4852 /*FIXME the peephole pass should have killed this*/
4853 if (ins->dreg != ins->sreg1)
4854 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4857 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4859 case OP_ICONV_TO_R8_RAW:
4860 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4861 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4864 case OP_FCONV_TO_R8_X:
4865 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4866 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4869 case OP_XCONV_R8_TO_I4:
4870 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4871 switch (ins->backend.source_opcode) {
4872 case OP_FCONV_TO_I1:
4873 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4875 case OP_FCONV_TO_U1:
4876 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4878 case OP_FCONV_TO_I2:
4879 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4881 case OP_FCONV_TO_U2:
4882 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4888 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4889 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4890 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4891 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4892 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4893 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4896 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4897 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4898 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4901 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4902 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4905 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4906 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4907 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4910 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4911 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4912 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4916 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4919 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4922 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4925 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4928 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4931 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4934 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4937 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4941 case OP_LIVERANGE_START: {
4942 if (cfg->verbose_level > 1)
4943 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4944 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4947 case OP_LIVERANGE_END: {
4948 if (cfg->verbose_level > 1)
4949 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4950 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4953 case OP_NACL_GC_SAFE_POINT: {
4954 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
4955 if (cfg->compile_aot)
4956 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
4960 x86_test_mem_imm8 (code, (gpointer)&__nacl_thread_suspension_needed, 0xFFFFFFFF);
4961 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4962 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
4963 x86_patch (br[0], code);
4968 case OP_GC_LIVENESS_DEF:
4969 case OP_GC_LIVENESS_USE:
4970 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4971 ins->backend.pc_offset = code - cfg->native_code;
4973 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4974 ins->backend.pc_offset = code - cfg->native_code;
4975 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4978 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
4981 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
4984 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4985 g_assert_not_reached ();
4988 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4989 #ifndef __native_client_codegen__
4990 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4991 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4992 g_assert_not_reached ();
4993 #endif /* __native_client_codegen__ */
4999 cfg->code_len = code - cfg->native_code;
5002 #endif /* DISABLE_JIT */
5005 mono_arch_register_lowlevel_calls (void)
5010 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
5012 MonoJumpInfo *patch_info;
5013 gboolean compile_aot = !run_cctors;
5015 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5016 unsigned char *ip = patch_info->ip.i + code;
5017 const unsigned char *target;
5020 switch (patch_info->type) {
5021 case MONO_PATCH_INFO_BB:
5022 case MONO_PATCH_INFO_LABEL:
5025 /* No need to patch these */
5030 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5032 switch (patch_info->type) {
5033 case MONO_PATCH_INFO_IP:
5034 *((gconstpointer *)(ip)) = target;
5036 case MONO_PATCH_INFO_CLASS_INIT: {
5038 /* Might already been changed to a nop */
5039 x86_call_code (code, 0);
5040 x86_patch (ip, target);
5043 case MONO_PATCH_INFO_ABS:
5044 case MONO_PATCH_INFO_METHOD:
5045 case MONO_PATCH_INFO_METHOD_JUMP:
5046 case MONO_PATCH_INFO_INTERNAL_METHOD:
5047 case MONO_PATCH_INFO_BB:
5048 case MONO_PATCH_INFO_LABEL:
5049 case MONO_PATCH_INFO_RGCTX_FETCH:
5050 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
5051 case MONO_PATCH_INFO_MONITOR_ENTER:
5052 case MONO_PATCH_INFO_MONITOR_EXIT:
5053 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5054 #if defined(__native_client_codegen__) && defined(__native_client__)
5055 if (nacl_is_code_address (code)) {
5056 /* For tail calls, code is patched after being installed */
5057 /* but not through the normal "patch callsite" method. */
5058 unsigned char buf[kNaClAlignment];
5059 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5060 unsigned char *_target = target;
5062 /* All patch targets modified in x86_patch */
5063 /* are IP relative. */
5064 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5065 memcpy (buf, aligned_code, kNaClAlignment);
5066 /* Patch a temp buffer of bundle size, */
5067 /* then install to actual location. */
5068 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5069 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5070 g_assert (ret == 0);
5073 x86_patch (ip, target);
5076 x86_patch (ip, target);
5079 case MONO_PATCH_INFO_NONE:
5081 case MONO_PATCH_INFO_R4:
5082 case MONO_PATCH_INFO_R8: {
5083 guint32 offset = mono_arch_get_patch_offset (ip);
5084 *((gconstpointer *)(ip + offset)) = target;
5088 guint32 offset = mono_arch_get_patch_offset (ip);
5089 #if !defined(__native_client__)
5090 *((gconstpointer *)(ip + offset)) = target;
5092 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5100 static G_GNUC_UNUSED void
5101 stack_unaligned (MonoMethod *m, gpointer caller)
5103 printf ("%s\n", mono_method_full_name (m, TRUE));
5104 g_assert_not_reached ();
5108 mono_arch_emit_prolog (MonoCompile *cfg)
5110 MonoMethod *method = cfg->method;
5112 MonoMethodSignature *sig;
5114 int alloc_size, pos, max_offset, i, cfa_offset;
5116 gboolean need_stack_frame;
5117 #ifdef __native_client_codegen__
5118 guint alignment_check;
5121 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5123 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5124 cfg->code_size += 512;
5126 #if defined(__default_codegen__)
5127 code = cfg->native_code = g_malloc (cfg->code_size);
5128 #elif defined(__native_client_codegen__)
5129 /* native_code_alloc is not 32-byte aligned, native_code is. */
5130 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5131 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5133 /* Align native_code to next nearest kNaclAlignment byte. */
5134 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5135 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5137 code = cfg->native_code;
5139 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5140 g_assert(alignment_check == 0);
5147 /* Check that the stack is aligned on osx */
5148 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5149 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5150 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5152 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5153 x86_push_membase (code, X86_ESP, 0);
5154 x86_push_imm (code, cfg->method);
5155 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5156 x86_call_reg (code, X86_EAX);
5157 x86_patch (br [0], code);
5161 /* Offset between RSP and the CFA */
5165 cfa_offset = sizeof (gpointer);
5166 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5167 // IP saved at CFA - 4
5168 /* There is no IP reg on x86 */
5169 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5170 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5172 need_stack_frame = needs_stack_frame (cfg);
5174 if (need_stack_frame) {
5175 x86_push_reg (code, X86_EBP);
5176 cfa_offset += sizeof (gpointer);
5177 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5178 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5179 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5180 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5181 /* These are handled automatically by the stack marking code */
5182 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5184 cfg->frame_reg = X86_ESP;
5187 cfg->stack_offset += cfg->param_area;
5188 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5190 alloc_size = cfg->stack_offset;
5193 if (!method->save_lmf) {
5194 if (cfg->used_int_regs & (1 << X86_EBX)) {
5195 x86_push_reg (code, X86_EBX);
5197 cfa_offset += sizeof (gpointer);
5198 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5199 /* These are handled automatically by the stack marking code */
5200 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5203 if (cfg->used_int_regs & (1 << X86_EDI)) {
5204 x86_push_reg (code, X86_EDI);
5206 cfa_offset += sizeof (gpointer);
5207 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5208 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5211 if (cfg->used_int_regs & (1 << X86_ESI)) {
5212 x86_push_reg (code, X86_ESI);
5214 cfa_offset += sizeof (gpointer);
5215 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5216 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5222 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5223 if (mono_do_x86_stack_align && need_stack_frame) {
5224 int tot = alloc_size + pos + 4; /* ret ip */
5225 if (need_stack_frame)
5227 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5229 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5230 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5231 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5235 cfg->arch.sp_fp_offset = alloc_size + pos;
5238 /* See mono_emit_stack_alloc */
5239 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5240 guint32 remaining_size = alloc_size;
5241 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5242 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5243 guint32 offset = code - cfg->native_code;
5244 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5245 while (required_code_size >= (cfg->code_size - offset))
5246 cfg->code_size *= 2;
5247 cfg->native_code = mono_realloc_native_code(cfg);
5248 code = cfg->native_code + offset;
5249 cfg->stat_code_reallocs++;
5251 while (remaining_size >= 0x1000) {
5252 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5253 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5254 remaining_size -= 0x1000;
5257 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5259 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5262 g_assert (need_stack_frame);
5265 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5266 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5267 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5270 #if DEBUG_STACK_ALIGNMENT
5271 /* check the stack is aligned */
5272 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5273 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5274 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5275 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5276 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5277 x86_breakpoint (code);
5281 /* compute max_offset in order to use short forward jumps */
5283 if (cfg->opt & MONO_OPT_BRANCH) {
5284 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5286 bb->max_offset = max_offset;
5288 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5290 /* max alignment for loops */
5291 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5292 max_offset += LOOP_ALIGNMENT;
5293 #ifdef __native_client_codegen__
5294 /* max alignment for native client */
5295 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5296 max_offset += kNaClAlignment;
5298 MONO_BB_FOR_EACH_INS (bb, ins) {
5299 if (ins->opcode == OP_LABEL)
5300 ins->inst_c1 = max_offset;
5301 #ifdef __native_client_codegen__
5302 switch (ins->opcode)
5314 case OP_VOIDCALL_REG:
5316 case OP_FCALL_MEMBASE:
5317 case OP_LCALL_MEMBASE:
5318 case OP_VCALL_MEMBASE:
5319 case OP_VCALL2_MEMBASE:
5320 case OP_VOIDCALL_MEMBASE:
5321 case OP_CALL_MEMBASE:
5322 max_offset += kNaClAlignment;
5325 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5328 #endif /* __native_client_codegen__ */
5329 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5334 /* store runtime generic context */
5335 if (cfg->rgctx_var) {
5336 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5338 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5341 if (method->save_lmf)
5342 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5344 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5345 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5347 /* load arguments allocated to register from the stack */
5348 sig = mono_method_signature (method);
5351 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5352 inst = cfg->args [pos];
5353 if (inst->opcode == OP_REGVAR) {
5354 g_assert (need_stack_frame);
5355 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5356 if (cfg->verbose_level > 2)
5357 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5362 cfg->code_len = code - cfg->native_code;
5364 g_assert (cfg->code_len < cfg->code_size);
5370 mono_arch_emit_epilog (MonoCompile *cfg)
5372 MonoMethod *method = cfg->method;
5373 MonoMethodSignature *sig = mono_method_signature (method);
5375 guint32 stack_to_pop;
5377 int max_epilog_size = 16;
5379 gboolean need_stack_frame = needs_stack_frame (cfg);
5381 if (cfg->method->save_lmf)
5382 max_epilog_size += 128;
5384 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5385 cfg->code_size *= 2;
5386 cfg->native_code = mono_realloc_native_code(cfg);
5387 cfg->stat_code_reallocs++;
5390 code = cfg->native_code + cfg->code_len;
5392 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5393 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5395 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5398 if (method->save_lmf) {
5399 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5401 gboolean supported = FALSE;
5403 if (cfg->compile_aot) {
5404 #if defined(__APPLE__) || defined(__linux__)
5407 } else if (mono_get_jit_tls_offset () != -1) {
5411 /* check if we need to restore protection of the stack after a stack overflow */
5413 if (cfg->compile_aot) {
5414 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5416 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5418 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5421 /* we load the value in a separate instruction: this mechanism may be
5422 * used later as a safer way to do thread interruption
5424 x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5425 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5427 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5428 /* note that the call trampoline will preserve eax/edx */
5429 x86_call_reg (code, X86_ECX);
5430 x86_patch (patch, code);
5432 /* FIXME: maybe save the jit tls in the prolog */
5435 /* restore caller saved regs */
5436 if (cfg->used_int_regs & (1 << X86_EBX)) {
5437 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5440 if (cfg->used_int_regs & (1 << X86_EDI)) {
5441 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5443 if (cfg->used_int_regs & (1 << X86_ESI)) {
5444 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5447 /* EBP is restored by LEAVE */
5449 for (i = 0; i < X86_NREG; ++i) {
5450 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5456 g_assert (need_stack_frame);
5457 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5461 g_assert (need_stack_frame);
5462 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5465 if (cfg->used_int_regs & (1 << X86_ESI)) {
5466 x86_pop_reg (code, X86_ESI);
5468 if (cfg->used_int_regs & (1 << X86_EDI)) {
5469 x86_pop_reg (code, X86_EDI);
5471 if (cfg->used_int_regs & (1 << X86_EBX)) {
5472 x86_pop_reg (code, X86_EBX);
5476 /* Load returned vtypes into registers if needed */
5477 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5478 if (cinfo->ret.storage == ArgValuetypeInReg) {
5479 for (quad = 0; quad < 2; quad ++) {
5480 switch (cinfo->ret.pair_storage [quad]) {
5482 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5484 case ArgOnFloatFpStack:
5485 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5487 case ArgOnDoubleFpStack:
5488 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5493 g_assert_not_reached ();
5498 if (need_stack_frame)
5501 if (CALLCONV_IS_STDCALL (sig)) {
5502 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5504 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5505 } else if (cinfo->callee_stack_pop)
5506 stack_to_pop = cinfo->callee_stack_pop;
5511 g_assert (need_stack_frame);
5512 x86_ret_imm (code, stack_to_pop);
5517 cfg->code_len = code - cfg->native_code;
5519 g_assert (cfg->code_len < cfg->code_size);
5523 mono_arch_emit_exceptions (MonoCompile *cfg)
5525 MonoJumpInfo *patch_info;
5528 MonoClass *exc_classes [16];
5529 guint8 *exc_throw_start [16], *exc_throw_end [16];
5533 /* Compute needed space */
5534 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5535 if (patch_info->type == MONO_PATCH_INFO_EXC)
5540 * make sure we have enough space for exceptions
5541 * 16 is the size of two push_imm instructions and a call
5543 if (cfg->compile_aot)
5544 code_size = exc_count * 32;
5546 code_size = exc_count * 16;
5548 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5549 cfg->code_size *= 2;
5550 cfg->native_code = mono_realloc_native_code(cfg);
5551 cfg->stat_code_reallocs++;
5554 code = cfg->native_code + cfg->code_len;
5557 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5558 switch (patch_info->type) {
5559 case MONO_PATCH_INFO_EXC: {
5560 MonoClass *exc_class;
5564 x86_patch (patch_info->ip.i + cfg->native_code, code);
5566 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5567 g_assert (exc_class);
5568 throw_ip = patch_info->ip.i;
5570 /* Find a throw sequence for the same exception class */
5571 for (i = 0; i < nthrows; ++i)
5572 if (exc_classes [i] == exc_class)
5575 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5576 x86_jump_code (code, exc_throw_start [i]);
5577 patch_info->type = MONO_PATCH_INFO_NONE;
5582 /* Compute size of code following the push <OFFSET> */
5583 #if defined(__default_codegen__)
5585 #elif defined(__native_client_codegen__)
5586 code = mono_nacl_align (code);
5587 size = kNaClAlignment;
5589 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5591 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5592 /* Use the shorter form */
5594 x86_push_imm (code, 0);
5598 x86_push_imm (code, 0xf0f0f0f0);
5603 exc_classes [nthrows] = exc_class;
5604 exc_throw_start [nthrows] = code;
5607 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5608 patch_info->data.name = "mono_arch_throw_corlib_exception";
5609 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5610 patch_info->ip.i = code - cfg->native_code;
5611 x86_call_code (code, 0);
5612 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5617 exc_throw_end [nthrows] = code;
5629 cfg->code_len = code - cfg->native_code;
5631 g_assert (cfg->code_len < cfg->code_size);
5635 mono_arch_flush_icache (guint8 *code, gint size)
5641 mono_arch_flush_register_windows (void)
5646 mono_arch_is_inst_imm (gint64 imm)
5652 mono_arch_finish_init (void)
5654 if (!g_getenv ("MONO_NO_TLS")) {
5655 #ifndef TARGET_WIN32
5657 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5664 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5668 // Linear handler, the bsearch head compare is shorter
5669 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5670 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5671 // x86_patch(ins,target)
5672 //[1 + 5] x86_jump_mem(inst,mem)
5675 #if defined(__default_codegen__)
5676 #define BR_SMALL_SIZE 2
5677 #define BR_LARGE_SIZE 5
5678 #elif defined(__native_client_codegen__)
5679 /* I suspect the size calculation below is actually incorrect. */
5680 /* TODO: fix the calculation that uses these sizes. */
5681 #define BR_SMALL_SIZE 16
5682 #define BR_LARGE_SIZE 12
5683 #endif /*__native_client_codegen__*/
5684 #define JUMP_IMM_SIZE 6
5685 #define ENABLE_WRONG_METHOD_CHECK 0
5689 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5691 int i, distance = 0;
5692 for (i = start; i < target; ++i)
5693 distance += imt_entries [i]->chunk_size;
5698 * LOCKING: called with the domain lock held
5701 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5702 gpointer fail_tramp)
5706 guint8 *code, *start;
5708 for (i = 0; i < count; ++i) {
5709 MonoIMTCheckItem *item = imt_entries [i];
5710 if (item->is_equals) {
5711 if (item->check_target_idx) {
5712 if (!item->compare_done)
5713 item->chunk_size += CMP_SIZE;
5714 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5717 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5719 item->chunk_size += JUMP_IMM_SIZE;
5720 #if ENABLE_WRONG_METHOD_CHECK
5721 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5726 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5727 imt_entries [item->check_target_idx]->compare_done = TRUE;
5729 size += item->chunk_size;
5731 #if defined(__native_client__) && defined(__native_client_codegen__)
5732 /* In Native Client, we don't re-use thunks, allocate from the */
5733 /* normal code manager paths. */
5734 size = NACL_BUNDLE_ALIGN_UP (size);
5735 code = mono_domain_code_reserve (domain, size);
5738 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5740 code = mono_domain_code_reserve (domain, size);
5743 for (i = 0; i < count; ++i) {
5744 MonoIMTCheckItem *item = imt_entries [i];
5745 item->code_target = code;
5746 if (item->is_equals) {
5747 if (item->check_target_idx) {
5748 if (!item->compare_done)
5749 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5750 item->jmp_code = code;
5751 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5752 if (item->has_target_code)
5753 x86_jump_code (code, item->value.target_code);
5755 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5758 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5759 item->jmp_code = code;
5760 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5761 if (item->has_target_code)
5762 x86_jump_code (code, item->value.target_code);
5764 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5765 x86_patch (item->jmp_code, code);
5766 x86_jump_code (code, fail_tramp);
5767 item->jmp_code = NULL;
5769 /* enable the commented code to assert on wrong method */
5770 #if ENABLE_WRONG_METHOD_CHECK
5771 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5772 item->jmp_code = code;
5773 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5775 if (item->has_target_code)
5776 x86_jump_code (code, item->value.target_code);
5778 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5779 #if ENABLE_WRONG_METHOD_CHECK
5780 x86_patch (item->jmp_code, code);
5781 x86_breakpoint (code);
5782 item->jmp_code = NULL;
5787 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5788 item->jmp_code = code;
5789 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5790 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5792 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5795 /* patch the branches to get to the target items */
5796 for (i = 0; i < count; ++i) {
5797 MonoIMTCheckItem *item = imt_entries [i];
5798 if (item->jmp_code) {
5799 if (item->check_target_idx) {
5800 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5806 mono_stats.imt_thunks_size += code - start;
5807 g_assert (code - start <= size);
5811 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5812 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5816 if (mono_jit_map_is_enabled ()) {
5819 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5821 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5822 mono_emit_jit_tramp (start, code - start, buff);
5826 nacl_domain_code_validate (domain, &start, size, &code);
5832 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5834 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5838 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5840 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5844 mono_arch_get_cie_program (void)
5848 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5849 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5855 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5857 MonoInst *ins = NULL;
5860 if (cmethod->klass == mono_defaults.math_class) {
5861 if (strcmp (cmethod->name, "Sin") == 0) {
5863 } else if (strcmp (cmethod->name, "Cos") == 0) {
5865 } else if (strcmp (cmethod->name, "Tan") == 0) {
5867 } else if (strcmp (cmethod->name, "Atan") == 0) {
5869 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5871 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5873 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5878 MONO_INST_NEW (cfg, ins, opcode);
5879 ins->type = STACK_R8;
5880 ins->dreg = mono_alloc_freg (cfg);
5881 ins->sreg1 = args [0]->dreg;
5882 MONO_ADD_INS (cfg->cbb, ins);
5885 if (cfg->opt & MONO_OPT_CMOV) {
5888 if (strcmp (cmethod->name, "Min") == 0) {
5889 if (fsig->params [0]->type == MONO_TYPE_I4)
5891 } else if (strcmp (cmethod->name, "Max") == 0) {
5892 if (fsig->params [0]->type == MONO_TYPE_I4)
5897 MONO_INST_NEW (cfg, ins, opcode);
5898 ins->type = STACK_I4;
5899 ins->dreg = mono_alloc_ireg (cfg);
5900 ins->sreg1 = args [0]->dreg;
5901 ins->sreg2 = args [1]->dreg;
5902 MONO_ADD_INS (cfg->cbb, ins);
5907 /* OP_FREM is not IEEE compatible */
5908 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5909 MONO_INST_NEW (cfg, ins, OP_FREM);
5910 ins->inst_i0 = args [0];
5911 ins->inst_i1 = args [1];
5920 mono_arch_print_tree (MonoInst *tree, int arity)
5926 mono_arch_get_patch_offset (guint8 *code)
5928 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5930 else if (code [0] == 0xba)
5932 else if (code [0] == 0x68)
5935 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5936 /* push <OFFSET>(<REG>) */
5938 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5939 /* call *<OFFSET>(<REG>) */
5941 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5944 else if ((code [0] == 0x58) && (code [1] == 0x05))
5945 /* pop %eax; add <OFFSET>, %eax */
5947 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5948 /* pop <REG>; add <OFFSET>, <REG> */
5950 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5951 /* mov <REG>, imm */
5954 g_assert_not_reached ();
5960 * mono_breakpoint_clean_code:
5962 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5963 * breakpoints in the original code, they are removed in the copy.
5965 * Returns TRUE if no sw breakpoint was present.
5968 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5971 gboolean can_write = TRUE;
5973 * If method_start is non-NULL we need to perform bound checks, since we access memory
5974 * at code - offset we could go before the start of the method and end up in a different
5975 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5978 if (!method_start || code - offset >= method_start) {
5979 memcpy (buf, code - offset, size);
5981 int diff = code - method_start;
5982 memset (buf, 0, size);
5983 memcpy (buf + offset - diff, method_start, diff + size - offset);
5986 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5987 int idx = mono_breakpoint_info_index [i];
5991 ptr = mono_breakpoint_info [idx].address;
5992 if (ptr >= code && ptr < code + size) {
5993 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5995 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5996 buf [ptr - code] = saved_byte;
6003 * mono_x86_get_this_arg_offset:
6005 * Return the offset of the stack location where this is passed during a virtual
6009 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6015 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6017 guint32 esp = regs [X86_ESP];
6018 CallInfo *cinfo = NULL;
6025 * The stack looks like:
6029 res = ((MonoObject**)esp) [0];
6035 #define MAX_ARCH_DELEGATE_PARAMS 10
6038 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6040 guint8 *code, *start;
6041 int code_reserve = 64;
6044 * The stack contains:
6050 start = code = mono_global_codeman_reserve (code_reserve);
6052 /* Replace the this argument with the target */
6053 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6054 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6055 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6056 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6058 g_assert ((code - start) < code_reserve);
6061 /* 8 for mov_reg and jump, plus 8 for each parameter */
6062 #ifdef __native_client_codegen__
6063 /* TODO: calculate this size correctly */
6064 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6066 code_reserve = 8 + (param_count * 8);
6067 #endif /* __native_client_codegen__ */
6069 * The stack contains:
6070 * <args in reverse order>
6075 * <args in reverse order>
6078 * without unbalancing the stack.
6079 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6080 * and leaving original spot of first arg as placeholder in stack so
6081 * when callee pops stack everything works.
6084 start = code = mono_global_codeman_reserve (code_reserve);
6086 /* store delegate for access to method_ptr */
6087 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6090 for (i = 0; i < param_count; ++i) {
6091 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6092 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6095 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6097 g_assert ((code - start) < code_reserve);
6100 nacl_global_codeman_validate(&start, code_reserve, &code);
6101 mono_debug_add_delegate_trampoline (start, code - start);
6104 *code_len = code - start;
6106 if (mono_jit_map_is_enabled ()) {
6109 buff = (char*)"delegate_invoke_has_target";
6111 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6112 mono_emit_jit_tramp (start, code - start, buff);
6121 mono_arch_get_delegate_invoke_impls (void)
6129 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6130 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
6132 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6133 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6134 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
6135 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
6136 g_free (tramp_name);
6143 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6145 guint8 *code, *start;
6147 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6150 /* FIXME: Support more cases */
6151 if (MONO_TYPE_ISSTRUCT (sig->ret))
6155 * The stack contains:
6161 static guint8* cached = NULL;
6166 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6168 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6170 mono_memory_barrier ();
6174 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6177 for (i = 0; i < sig->param_count; ++i)
6178 if (!mono_is_regsize_var (sig->params [i]))
6181 code = cache [sig->param_count];
6185 if (mono_aot_only) {
6186 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6187 start = mono_aot_get_trampoline (name);
6190 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6193 mono_memory_barrier ();
6195 cache [sig->param_count] = start;
6202 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
6204 guint8 *code, *start;
6208 * The stack contains:
6212 start = code = mono_global_codeman_reserve (size);
6214 /* Replace the this argument with the target */
6215 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6216 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6217 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6220 /* Load the IMT reg */
6221 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
6224 /* Load the vtable */
6225 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
6226 x86_jump_membase (code, X86_EAX, offset);
6232 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6235 case X86_EAX: return ctx->eax;
6236 case X86_EBX: return ctx->ebx;
6237 case X86_ECX: return ctx->ecx;
6238 case X86_EDX: return ctx->edx;
6239 case X86_ESP: return ctx->esp;
6240 case X86_EBP: return ctx->ebp;
6241 case X86_ESI: return ctx->esi;
6242 case X86_EDI: return ctx->edi;
6244 g_assert_not_reached ();
6250 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6278 g_assert_not_reached ();
6282 #ifdef MONO_ARCH_SIMD_INTRINSICS
6285 get_float_to_x_spill_area (MonoCompile *cfg)
6287 if (!cfg->fconv_to_r8_x_var) {
6288 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6289 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6291 return cfg->fconv_to_r8_x_var;
6295 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6298 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6301 int dreg, src_opcode;
6303 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6306 switch (src_opcode = ins->opcode) {
6307 case OP_FCONV_TO_I1:
6308 case OP_FCONV_TO_U1:
6309 case OP_FCONV_TO_I2:
6310 case OP_FCONV_TO_U2:
6311 case OP_FCONV_TO_I4:
6318 /* dreg is the IREG and sreg1 is the FREG */
6319 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6320 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6321 fconv->sreg1 = ins->sreg1;
6322 fconv->dreg = mono_alloc_ireg (cfg);
6323 fconv->type = STACK_VTYPE;
6324 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6326 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6330 ins->opcode = OP_XCONV_R8_TO_I4;
6332 ins->klass = mono_defaults.int32_class;
6333 ins->sreg1 = fconv->dreg;
6335 ins->type = STACK_I4;
6336 ins->backend.source_opcode = src_opcode;
6339 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6342 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6347 if (long_ins->opcode == OP_LNEG) {
6349 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6350 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6351 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6356 #ifdef MONO_ARCH_SIMD_INTRINSICS
6358 if (!(cfg->opt & MONO_OPT_SIMD))
6361 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6362 switch (long_ins->opcode) {
6364 vreg = long_ins->sreg1;
6366 if (long_ins->inst_c0) {
6367 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6368 ins->klass = long_ins->klass;
6369 ins->sreg1 = long_ins->sreg1;
6371 ins->type = STACK_VTYPE;
6372 ins->dreg = vreg = alloc_ireg (cfg);
6373 MONO_ADD_INS (cfg->cbb, ins);
6376 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6377 ins->klass = mono_defaults.int32_class;
6379 ins->type = STACK_I4;
6380 ins->dreg = long_ins->dreg + 1;
6381 MONO_ADD_INS (cfg->cbb, ins);
6383 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6384 ins->klass = long_ins->klass;
6385 ins->sreg1 = long_ins->sreg1;
6386 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6387 ins->type = STACK_VTYPE;
6388 ins->dreg = vreg = alloc_ireg (cfg);
6389 MONO_ADD_INS (cfg->cbb, ins);
6391 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6392 ins->klass = mono_defaults.int32_class;
6394 ins->type = STACK_I4;
6395 ins->dreg = long_ins->dreg + 2;
6396 MONO_ADD_INS (cfg->cbb, ins);
6398 long_ins->opcode = OP_NOP;
6400 case OP_INSERTX_I8_SLOW:
6401 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6402 ins->dreg = long_ins->dreg;
6403 ins->sreg1 = long_ins->dreg;
6404 ins->sreg2 = long_ins->sreg2 + 1;
6405 ins->inst_c0 = long_ins->inst_c0 * 2;
6406 MONO_ADD_INS (cfg->cbb, ins);
6408 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6409 ins->dreg = long_ins->dreg;
6410 ins->sreg1 = long_ins->dreg;
6411 ins->sreg2 = long_ins->sreg2 + 2;
6412 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6413 MONO_ADD_INS (cfg->cbb, ins);
6415 long_ins->opcode = OP_NOP;
6418 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6419 ins->dreg = long_ins->dreg;
6420 ins->sreg1 = long_ins->sreg1 + 1;
6421 ins->klass = long_ins->klass;
6422 ins->type = STACK_VTYPE;
6423 MONO_ADD_INS (cfg->cbb, ins);
6425 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6426 ins->dreg = long_ins->dreg;
6427 ins->sreg1 = long_ins->dreg;
6428 ins->sreg2 = long_ins->sreg1 + 2;
6430 ins->klass = long_ins->klass;
6431 ins->type = STACK_VTYPE;
6432 MONO_ADD_INS (cfg->cbb, ins);
6434 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6435 ins->dreg = long_ins->dreg;
6436 ins->sreg1 = long_ins->dreg;;
6437 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6438 ins->klass = long_ins->klass;
6439 ins->type = STACK_VTYPE;
6440 MONO_ADD_INS (cfg->cbb, ins);
6442 long_ins->opcode = OP_NOP;
6445 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6448 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6450 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6453 gpointer *sp, old_value;
6456 offset = clause->exvar_offset;
6459 bp = MONO_CONTEXT_GET_BP (ctx);
6460 sp = *(gpointer*)(bp + offset);
6463 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6472 * mono_aot_emit_load_got_addr:
6474 * Emit code to load the got address.
6475 * On x86, the result is placed into EBX.
6478 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6480 x86_call_imm (code, 0);
6482 * The patch needs to point to the pop, since the GOT offset needs
6483 * to be added to that address.
6486 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6488 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6489 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6490 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6496 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6499 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6501 g_assert_not_reached ();
6502 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6507 * mono_arch_emit_load_aotconst:
6509 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6510 * TARGET from the mscorlib GOT in full-aot code.
6511 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6515 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6517 /* Load the mscorlib got address */
6518 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6519 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6520 /* arch_emit_got_access () patches this */
6521 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6526 /* Can't put this into mini-x86.h */
6528 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6531 mono_arch_get_trampolines (gboolean aot)
6533 MonoTrampInfo *info;
6534 GSList *tramps = NULL;
6536 mono_x86_get_signal_exception_trampoline (&info, aot);
6538 tramps = g_slist_append (tramps, info);
6545 #define DBG_SIGNAL SIGBUS
6547 #define DBG_SIGNAL SIGSEGV
6550 /* Soft Debug support */
6551 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6554 * mono_arch_set_breakpoint:
6556 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6557 * The location should contain code emitted by OP_SEQ_POINT.
6560 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6565 * In production, we will use int3 (has to fix the size in the md
6566 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6569 g_assert (code [0] == 0x90);
6570 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6574 * mono_arch_clear_breakpoint:
6576 * Clear the breakpoint at IP.
6579 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6584 for (i = 0; i < 6; ++i)
6589 * mono_arch_start_single_stepping:
6591 * Start single stepping.
6594 mono_arch_start_single_stepping (void)
6596 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6600 * mono_arch_stop_single_stepping:
6602 * Stop single stepping.
6605 mono_arch_stop_single_stepping (void)
6607 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6611 * mono_arch_is_single_step_event:
6613 * Return whenever the machine state in SIGCTX corresponds to a single
6617 mono_arch_is_single_step_event (void *info, void *sigctx)
6620 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6622 if (((gpointer)einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6627 siginfo_t* sinfo = (siginfo_t*) info;
6628 /* Sometimes the address is off by 4 */
6629 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6637 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6640 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6641 if (((gpointer)einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6646 siginfo_t* sinfo = (siginfo_t*)info;
6647 /* Sometimes the address is off by 4 */
6648 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6655 #define BREAKPOINT_SIZE 6
6658 * mono_arch_skip_breakpoint:
6660 * See mini-amd64.c for docs.
6663 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6665 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6669 * mono_arch_skip_single_step:
6671 * See mini-amd64.c for docs.
6674 mono_arch_skip_single_step (MonoContext *ctx)
6676 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6680 * mono_arch_get_seq_point_info:
6682 * See mini-amd64.c for docs.
6685 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6692 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6694 ext->lmf.previous_lmf = (gsize)prev_lmf;
6695 /* Mark that this is a MonoLMFExt */
6696 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6697 ext->lmf.ebp = (gssize)ext;
6703 mono_arch_opcode_supported (int opcode)
6706 case OP_ATOMIC_ADD_I4:
6707 case OP_ATOMIC_EXCHANGE_I4:
6708 case OP_ATOMIC_CAS_I4:
6715 #if defined(ENABLE_GSHAREDVT)
6717 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6719 #endif /* !MONOTOUCH */