2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
12 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
21 #include <mono/metadata/abi-details.h>
22 #include <mono/metadata/appdomain.h>
23 #include <mono/metadata/debug-helpers.h>
24 #include <mono/metadata/threads.h>
25 #include <mono/metadata/profiler-private.h>
26 #include <mono/metadata/mono-debug.h>
27 #include <mono/metadata/gc-internals.h>
28 #include <mono/utils/mono-math.h>
29 #include <mono/utils/mono-counters.h>
30 #include <mono/utils/mono-mmap.h>
31 #include <mono/utils/mono-memory-model.h>
32 #include <mono/utils/mono-hwcap-x86.h>
33 #include <mono/utils/mono-threads.h>
43 static gboolean optimize_for_xen = TRUE;
45 #define optimize_for_xen 0
49 /* The single step trampoline */
50 static gpointer ss_trampoline;
52 /* The breakpoint trampoline */
53 static gpointer bp_trampoline;
55 /* This mutex protects architecture specific caches */
56 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
57 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
58 static mono_mutex_t mini_arch_mutex;
60 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
65 /* Under windows, the default pinvoke calling convention is stdcall */
66 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
68 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
71 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
73 #define OP_SEQ_POINT_BP_OFFSET 7
76 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
78 #ifdef __native_client_codegen__
80 /* Default alignment for Native Client is 32-byte. */
81 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
83 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
84 /* Check that alignment doesn't cross an alignment boundary. */
86 mono_arch_nacl_pad (guint8 *code, int pad)
88 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
90 if (pad == 0) return code;
91 /* assertion: alignment cannot cross a block boundary */
92 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
93 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
94 while (pad >= kMaxPadding) {
95 x86_padding (code, kMaxPadding);
98 if (pad != 0) x86_padding (code, pad);
103 mono_arch_nacl_skip_nops (guint8 *code)
105 x86_skip_nops (code);
109 #endif /* __native_client_codegen__ */
112 mono_arch_regname (int reg)
115 case X86_EAX: return "%eax";
116 case X86_EBX: return "%ebx";
117 case X86_ECX: return "%ecx";
118 case X86_EDX: return "%edx";
119 case X86_ESP: return "%esp";
120 case X86_EBP: return "%ebp";
121 case X86_EDI: return "%edi";
122 case X86_ESI: return "%esi";
128 mono_arch_fregname (int reg)
153 mono_arch_xregname (int reg)
178 mono_x86_patch (unsigned char* code, gpointer target)
180 x86_patch (code, (unsigned char*)target);
183 #define FLOAT_PARAM_REGS 0
185 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
187 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
192 switch (sig->call_convention) {
193 case MONO_CALL_THISCALL:
194 return thiscall_param_regs;
200 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
201 #define SMALL_STRUCTS_IN_REGS
202 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
206 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
208 ainfo->offset = *stack_size;
210 if (!param_regs || param_regs [*gr] == X86_NREG) {
211 ainfo->storage = ArgOnStack;
213 (*stack_size) += sizeof (gpointer);
216 ainfo->storage = ArgInIReg;
217 ainfo->reg = param_regs [*gr];
223 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
225 ainfo->offset = *stack_size;
227 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
229 ainfo->storage = ArgOnStack;
230 (*stack_size) += sizeof (gpointer) * 2;
235 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
237 ainfo->offset = *stack_size;
239 if (*gr >= FLOAT_PARAM_REGS) {
240 ainfo->storage = ArgOnStack;
241 (*stack_size) += is_double ? 8 : 4;
242 ainfo->nslots = is_double ? 2 : 1;
245 /* A double register */
247 ainfo->storage = ArgInDoubleSSEReg;
249 ainfo->storage = ArgInFloatSSEReg;
257 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
259 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
264 klass = mono_class_from_mono_type (type);
265 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
267 #ifdef SMALL_STRUCTS_IN_REGS
268 if (sig->pinvoke && is_return) {
269 MonoMarshalType *info;
272 * the exact rules are not very well documented, the code below seems to work with the
273 * code generated by gcc 3.3.3 -mno-cygwin.
275 info = mono_marshal_load_type_info (klass);
278 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
280 /* Special case structs with only a float member */
281 if (info->num_fields == 1) {
282 int ftype = mini_get_underlying_type (info->fields [0].field->type)->type;
283 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
284 ainfo->storage = ArgValuetypeInReg;
285 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
288 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
289 ainfo->storage = ArgValuetypeInReg;
290 ainfo->pair_storage [0] = ArgOnFloatFpStack;
294 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
295 ainfo->storage = ArgValuetypeInReg;
296 ainfo->pair_storage [0] = ArgInIReg;
297 ainfo->pair_regs [0] = return_regs [0];
298 if (info->native_size > 4) {
299 ainfo->pair_storage [1] = ArgInIReg;
300 ainfo->pair_regs [1] = return_regs [1];
307 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
308 g_assert (size <= 4);
309 ainfo->storage = ArgValuetypeInReg;
310 ainfo->reg = param_regs [*gr];
315 ainfo->offset = *stack_size;
316 ainfo->storage = ArgOnStack;
317 *stack_size += ALIGN_TO (size, sizeof (gpointer));
318 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
324 * Obtain information about a call according to the calling convention.
325 * For x86 ELF, see the "System V Application Binary Interface Intel386
326 * Architecture Processor Supplment, Fourth Edition" document for more
328 * For x86 win32, see ???.
331 get_call_info_internal (CallInfo *cinfo, MonoMethodSignature *sig)
333 guint32 i, gr, fr, pstart;
334 const guint32 *param_regs;
336 int n = sig->hasthis + sig->param_count;
337 guint32 stack_size = 0;
338 gboolean is_pinvoke = sig->pinvoke;
344 param_regs = callconv_param_regs(sig);
348 ret_type = mini_get_underlying_type (sig->ret);
349 switch (ret_type->type) {
359 case MONO_TYPE_FNPTR:
360 case MONO_TYPE_CLASS:
361 case MONO_TYPE_OBJECT:
362 case MONO_TYPE_SZARRAY:
363 case MONO_TYPE_ARRAY:
364 case MONO_TYPE_STRING:
365 cinfo->ret.storage = ArgInIReg;
366 cinfo->ret.reg = X86_EAX;
370 cinfo->ret.storage = ArgInIReg;
371 cinfo->ret.reg = X86_EAX;
372 cinfo->ret.is_pair = TRUE;
375 cinfo->ret.storage = ArgOnFloatFpStack;
378 cinfo->ret.storage = ArgOnDoubleFpStack;
380 case MONO_TYPE_GENERICINST:
381 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
382 cinfo->ret.storage = ArgInIReg;
383 cinfo->ret.reg = X86_EAX;
386 if (mini_is_gsharedvt_type (ret_type)) {
387 cinfo->ret.storage = ArgOnStack;
388 cinfo->vtype_retaddr = TRUE;
392 case MONO_TYPE_VALUETYPE:
393 case MONO_TYPE_TYPEDBYREF: {
394 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
396 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
397 if (cinfo->ret.storage == ArgOnStack) {
398 cinfo->vtype_retaddr = TRUE;
399 /* The caller passes the address where the value is stored */
405 g_assert (mini_is_gsharedvt_type (ret_type));
406 cinfo->ret.storage = ArgOnStack;
407 cinfo->vtype_retaddr = TRUE;
410 cinfo->ret.storage = ArgNone;
413 g_error ("Can't handle as return value 0x%x", ret_type->type);
419 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
420 * the first argument, allowing 'this' to be always passed in the first arg reg.
421 * Also do this if the first argument is a reference type, since virtual calls
422 * are sometimes made using calli without sig->hasthis set, like in the delegate
425 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
427 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
429 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
432 cinfo->vret_arg_offset = stack_size;
433 add_general (&gr, NULL, &stack_size, &cinfo->ret);
434 cinfo->vret_arg_index = 1;
438 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
440 if (cinfo->vtype_retaddr)
441 add_general (&gr, NULL, &stack_size, &cinfo->ret);
444 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
445 fr = FLOAT_PARAM_REGS;
447 /* Emit the signature cookie just before the implicit arguments */
448 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
451 for (i = pstart; i < sig->param_count; ++i) {
452 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
455 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
456 /* We allways pass the sig cookie on the stack for simplicity */
458 * Prevent implicit arguments + the sig cookie from being passed
461 fr = FLOAT_PARAM_REGS;
463 /* Emit the signature cookie just before the implicit arguments */
464 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
467 if (sig->params [i]->byref) {
468 add_general (&gr, param_regs, &stack_size, ainfo);
471 ptype = mini_get_underlying_type (sig->params [i]);
472 switch (ptype->type) {
475 add_general (&gr, param_regs, &stack_size, ainfo);
479 add_general (&gr, param_regs, &stack_size, ainfo);
483 add_general (&gr, param_regs, &stack_size, ainfo);
488 case MONO_TYPE_FNPTR:
489 case MONO_TYPE_CLASS:
490 case MONO_TYPE_OBJECT:
491 case MONO_TYPE_STRING:
492 case MONO_TYPE_SZARRAY:
493 case MONO_TYPE_ARRAY:
494 add_general (&gr, param_regs, &stack_size, ainfo);
496 case MONO_TYPE_GENERICINST:
497 if (!mono_type_generic_inst_is_valuetype (ptype)) {
498 add_general (&gr, param_regs, &stack_size, ainfo);
501 if (mini_is_gsharedvt_type (ptype)) {
502 /* gsharedvt arguments are passed by ref */
503 add_general (&gr, param_regs, &stack_size, ainfo);
504 g_assert (ainfo->storage == ArgOnStack);
505 ainfo->storage = ArgGSharedVt;
509 case MONO_TYPE_VALUETYPE:
510 case MONO_TYPE_TYPEDBYREF:
511 add_valuetype (sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
515 add_general_pair (&gr, param_regs, &stack_size, ainfo);
518 add_float (&fr, &stack_size, ainfo, FALSE);
521 add_float (&fr, &stack_size, ainfo, TRUE);
525 /* gsharedvt arguments are passed by ref */
526 g_assert (mini_is_gsharedvt_type (ptype));
527 add_general (&gr, param_regs, &stack_size, ainfo);
528 g_assert (ainfo->storage == ArgOnStack);
529 ainfo->storage = ArgGSharedVt;
532 g_error ("unexpected type 0x%x", ptype->type);
533 g_assert_not_reached ();
537 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
538 fr = FLOAT_PARAM_REGS;
540 /* Emit the signature cookie just before the implicit arguments */
541 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
544 if (cinfo->vtype_retaddr) {
545 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
546 cinfo->callee_stack_pop = 4;
547 } else if (CALLCONV_IS_STDCALL (sig) && sig->pinvoke) {
548 /* Have to compensate for the stack space popped by the native callee */
549 cinfo->callee_stack_pop = stack_size;
552 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
553 cinfo->need_stack_align = TRUE;
554 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
555 stack_size += cinfo->stack_align_amount;
558 cinfo->stack_usage = stack_size;
559 cinfo->reg_usage = gr;
560 cinfo->freg_usage = fr;
565 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
567 int n = sig->hasthis + sig->param_count;
571 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
573 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
575 return get_call_info_internal (cinfo, sig);
579 * mono_arch_get_argument_info:
580 * @csig: a method signature
581 * @param_count: the number of parameters to consider
582 * @arg_info: an array to store the result infos
584 * Gathers information on parameters such as size, alignment and
585 * padding. arg_info should be large enought to hold param_count + 1 entries.
587 * Returns the size of the argument area on the stack.
588 * This should be signal safe, since it is called from
589 * mono_arch_unwind_frame ().
590 * FIXME: The metadata calls might not be signal safe.
593 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
595 int len, k, args_size = 0;
601 /* Avoid g_malloc as it is not signal safe */
602 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
603 cinfo = (CallInfo*)g_newa (guint8*, len);
604 memset (cinfo, 0, len);
606 cinfo = get_call_info_internal (cinfo, csig);
608 arg_info [0].offset = offset;
610 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
611 args_size += sizeof (gpointer);
616 args_size += sizeof (gpointer);
620 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
621 /* Emitted after this */
622 args_size += sizeof (gpointer);
626 arg_info [0].size = args_size;
628 for (k = 0; k < param_count; k++) {
629 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
631 /* ignore alignment for now */
634 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
635 arg_info [k].pad = pad;
637 arg_info [k + 1].pad = 0;
638 arg_info [k + 1].size = size;
640 arg_info [k + 1].offset = offset;
643 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
644 /* Emitted after the first arg */
645 args_size += sizeof (gpointer);
650 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
651 align = MONO_ARCH_FRAME_ALIGNMENT;
654 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
655 arg_info [k].pad = pad;
661 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
663 MonoType *callee_ret;
667 if (cfg->compile_aot && !cfg->full_aot)
668 /* OP_TAILCALL doesn't work with AOT */
671 c1 = get_call_info (NULL, caller_sig);
672 c2 = get_call_info (NULL, callee_sig);
674 * Tail calls with more callee stack usage than the caller cannot be supported, since
675 * the extra stack space would be left on the stack after the tail call.
677 res = c1->stack_usage >= c2->stack_usage;
678 callee_ret = mini_get_underlying_type (callee_sig->ret);
679 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
680 /* An address on the callee's stack is passed as the first argument */
690 * Initialize the cpu to execute managed code.
693 mono_arch_cpu_init (void)
695 /* spec compliance requires running with double precision */
699 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
700 fpcw &= ~X86_FPCW_PRECC_MASK;
701 fpcw |= X86_FPCW_PREC_DOUBLE;
702 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
703 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
705 _control87 (_PC_53, MCW_PC);
710 * Initialize architecture specific code.
713 mono_arch_init (void)
715 mono_os_mutex_init_recursive (&mini_arch_mutex);
718 bp_trampoline = mini_get_breakpoint_trampoline ();
720 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
721 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
722 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
723 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
728 * Cleanup architecture specific code.
731 mono_arch_cleanup (void)
733 mono_os_mutex_destroy (&mini_arch_mutex);
737 * This function returns the optimizations supported on this cpu.
740 mono_arch_cpu_optimizations (guint32 *exclude_mask)
742 #if !defined(__native_client__)
747 if (mono_hwcap_x86_has_cmov) {
748 opts |= MONO_OPT_CMOV;
750 if (mono_hwcap_x86_has_fcmov)
751 opts |= MONO_OPT_FCMOV;
753 *exclude_mask |= MONO_OPT_FCMOV;
755 *exclude_mask |= MONO_OPT_CMOV;
758 if (mono_hwcap_x86_has_sse2)
759 opts |= MONO_OPT_SSE2;
761 *exclude_mask |= MONO_OPT_SSE2;
763 #ifdef MONO_ARCH_SIMD_INTRINSICS
764 /*SIMD intrinsics require at least SSE2.*/
765 if (!mono_hwcap_x86_has_sse2)
766 *exclude_mask |= MONO_OPT_SIMD;
771 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
776 * This function test for all SSE functions supported.
778 * Returns a bitmask corresponding to all supported versions.
782 mono_arch_cpu_enumerate_simd_versions (void)
784 guint32 sse_opts = 0;
786 if (mono_hwcap_x86_has_sse1)
787 sse_opts |= SIMD_VERSION_SSE1;
789 if (mono_hwcap_x86_has_sse2)
790 sse_opts |= SIMD_VERSION_SSE2;
792 if (mono_hwcap_x86_has_sse3)
793 sse_opts |= SIMD_VERSION_SSE3;
795 if (mono_hwcap_x86_has_ssse3)
796 sse_opts |= SIMD_VERSION_SSSE3;
798 if (mono_hwcap_x86_has_sse41)
799 sse_opts |= SIMD_VERSION_SSE41;
801 if (mono_hwcap_x86_has_sse42)
802 sse_opts |= SIMD_VERSION_SSE42;
804 if (mono_hwcap_x86_has_sse4a)
805 sse_opts |= SIMD_VERSION_SSE4a;
811 * Determine whenever the trap whose info is in SIGINFO is caused by
815 mono_arch_is_int_overflow (void *sigctx, void *info)
820 mono_sigctx_to_monoctx (sigctx, &ctx);
822 ip = (guint8*)ctx.eip;
824 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
828 switch (x86_modrm_rm (ip [1])) {
848 g_assert_not_reached ();
860 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
865 for (i = 0; i < cfg->num_varinfo; i++) {
866 MonoInst *ins = cfg->varinfo [i];
867 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
870 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
873 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
874 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
877 /* we dont allocate I1 to registers because there is no simply way to sign extend
878 * 8bit quantities in caller saved registers on x86 */
879 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
880 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
881 g_assert (i == vmv->idx);
882 vars = g_list_prepend (vars, vmv);
886 vars = mono_varlist_sort (cfg, vars, 0);
892 mono_arch_get_global_int_regs (MonoCompile *cfg)
896 /* we can use 3 registers for global allocation */
897 regs = g_list_prepend (regs, (gpointer)X86_EBX);
898 regs = g_list_prepend (regs, (gpointer)X86_ESI);
899 regs = g_list_prepend (regs, (gpointer)X86_EDI);
905 * mono_arch_regalloc_cost:
907 * Return the cost, in number of memory references, of the action of
908 * allocating the variable VMV into a register during global register
912 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
914 MonoInst *ins = cfg->varinfo [vmv->idx];
916 if (cfg->method->save_lmf)
917 /* The register is already saved */
918 return (ins->opcode == OP_ARG) ? 1 : 0;
920 /* push+pop+possible load if it is an argument */
921 return (ins->opcode == OP_ARG) ? 3 : 2;
925 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
927 static int inited = FALSE;
928 static int count = 0;
930 if (cfg->arch.need_stack_frame_inited) {
931 g_assert (cfg->arch.need_stack_frame == flag);
935 cfg->arch.need_stack_frame = flag;
936 cfg->arch.need_stack_frame_inited = TRUE;
942 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
947 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
951 needs_stack_frame (MonoCompile *cfg)
953 MonoMethodSignature *sig;
954 MonoMethodHeader *header;
955 gboolean result = FALSE;
957 #if defined(__APPLE__)
958 /*OSX requires stack frame code to have the correct alignment. */
962 if (cfg->arch.need_stack_frame_inited)
963 return cfg->arch.need_stack_frame;
965 header = cfg->header;
966 sig = mono_method_signature (cfg->method);
968 if (cfg->disable_omit_fp)
970 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
972 else if (cfg->method->save_lmf)
974 else if (cfg->stack_offset)
976 else if (cfg->param_area)
978 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
980 else if (header->num_clauses)
982 else if (sig->param_count + sig->hasthis)
984 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
986 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
987 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
990 set_needs_stack_frame (cfg, result);
992 return cfg->arch.need_stack_frame;
996 * Set var information according to the calling convention. X86 version.
997 * The locals var stuff should most likely be split in another method.
1000 mono_arch_allocate_vars (MonoCompile *cfg)
1002 MonoMethodSignature *sig;
1003 MonoMethodHeader *header;
1005 guint32 locals_stack_size, locals_stack_align;
1010 header = cfg->header;
1011 sig = mono_method_signature (cfg->method);
1013 if (!cfg->arch.cinfo)
1014 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1015 cinfo = (CallInfo *)cfg->arch.cinfo;
1017 cfg->frame_reg = X86_EBP;
1020 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1021 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1022 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1025 /* Reserve space to save LMF and caller saved registers */
1027 if (cfg->method->save_lmf) {
1028 /* The LMF var is allocated normally */
1030 if (cfg->used_int_regs & (1 << X86_EBX)) {
1034 if (cfg->used_int_regs & (1 << X86_EDI)) {
1038 if (cfg->used_int_regs & (1 << X86_ESI)) {
1043 switch (cinfo->ret.storage) {
1044 case ArgValuetypeInReg:
1045 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1047 cfg->ret->opcode = OP_REGOFFSET;
1048 cfg->ret->inst_basereg = X86_EBP;
1049 cfg->ret->inst_offset = - offset;
1055 /* Allocate locals */
1056 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1057 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1058 char *mname = mono_method_full_name (cfg->method, TRUE);
1059 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1063 if (locals_stack_align) {
1064 int prev_offset = offset;
1066 offset += (locals_stack_align - 1);
1067 offset &= ~(locals_stack_align - 1);
1069 while (prev_offset < offset) {
1071 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1074 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1075 cfg->locals_max_stack_offset = - offset;
1077 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1078 * have locals larger than 8 bytes we need to make sure that
1079 * they have the appropriate offset.
1081 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1082 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1083 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1084 if (offsets [i] != -1) {
1085 MonoInst *inst = cfg->varinfo [i];
1086 inst->opcode = OP_REGOFFSET;
1087 inst->inst_basereg = X86_EBP;
1088 inst->inst_offset = - (offset + offsets [i]);
1089 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1092 offset += locals_stack_size;
1096 * Allocate arguments+return value
1099 switch (cinfo->ret.storage) {
1101 if (cfg->vret_addr) {
1103 * In the new IR, the cfg->vret_addr variable represents the
1104 * vtype return value.
1106 cfg->vret_addr->opcode = OP_REGOFFSET;
1107 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1108 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1109 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1110 printf ("vret_addr =");
1111 mono_print_ins (cfg->vret_addr);
1114 cfg->ret->opcode = OP_REGOFFSET;
1115 cfg->ret->inst_basereg = X86_EBP;
1116 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1119 case ArgValuetypeInReg:
1122 cfg->ret->opcode = OP_REGVAR;
1123 cfg->ret->inst_c0 = cinfo->ret.reg;
1124 cfg->ret->dreg = cinfo->ret.reg;
1127 case ArgOnFloatFpStack:
1128 case ArgOnDoubleFpStack:
1131 g_assert_not_reached ();
1134 if (sig->call_convention == MONO_CALL_VARARG) {
1135 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1136 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1139 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1140 ArgInfo *ainfo = &cinfo->args [i];
1141 inst = cfg->args [i];
1142 if (inst->opcode != OP_REGVAR) {
1143 inst->opcode = OP_REGOFFSET;
1144 inst->inst_basereg = X86_EBP;
1145 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1149 cfg->stack_offset = offset;
1153 mono_arch_create_vars (MonoCompile *cfg)
1156 MonoMethodSignature *sig;
1159 sig = mono_method_signature (cfg->method);
1161 if (!cfg->arch.cinfo)
1162 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1163 cinfo = (CallInfo *)cfg->arch.cinfo;
1165 sig_ret = mini_get_underlying_type (sig->ret);
1167 if (cinfo->ret.storage == ArgValuetypeInReg)
1168 cfg->ret_var_is_local = TRUE;
1169 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (sig_ret))) {
1170 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1173 if (cfg->gen_sdb_seq_points) {
1176 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1177 ins->flags |= MONO_INST_VOLATILE;
1178 cfg->arch.ss_tramp_var = ins;
1180 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1181 ins->flags |= MONO_INST_VOLATILE;
1182 cfg->arch.bp_tramp_var = ins;
1185 if (cfg->method->save_lmf) {
1186 cfg->create_lmf_var = TRUE;
1189 cfg->lmf_ir_mono_lmf = TRUE;
1193 cfg->arch_eh_jit_info = 1;
1197 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1198 * so we try to do it just once when we have multiple fp arguments in a row.
1199 * We don't use this mechanism generally because for int arguments the generated code
1200 * is slightly bigger and new generation cpus optimize away the dependency chains
1201 * created by push instructions on the esp value.
1202 * fp_arg_setup is the first argument in the execution sequence where the esp register
1205 static G_GNUC_UNUSED int
1206 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1211 for (; start_arg < sig->param_count; ++start_arg) {
1212 t = mini_get_underlying_type (sig->params [start_arg]);
1213 if (!t->byref && t->type == MONO_TYPE_R8) {
1214 fp_space += sizeof (double);
1215 *fp_arg_setup = start_arg;
1224 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1226 MonoMethodSignature *tmp_sig;
1230 * mono_ArgIterator_Setup assumes the signature cookie is
1231 * passed first and all the arguments which were before it are
1232 * passed on the stack after the signature. So compensate by
1233 * passing a different signature.
1235 tmp_sig = mono_metadata_signature_dup (call->signature);
1236 tmp_sig->param_count -= call->signature->sentinelpos;
1237 tmp_sig->sentinelpos = 0;
1238 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1240 if (cfg->compile_aot) {
1241 sig_reg = mono_alloc_ireg (cfg);
1242 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1243 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1245 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1251 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1256 LLVMCallInfo *linfo;
1257 MonoType *t, *sig_ret;
1259 n = sig->param_count + sig->hasthis;
1261 cinfo = get_call_info (cfg->mempool, sig);
1264 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1267 * LLVM always uses the native ABI while we use our own ABI, the
1268 * only difference is the handling of vtypes:
1269 * - we only pass/receive them in registers in some cases, and only
1270 * in 1 or 2 integer registers.
1272 if (cinfo->ret.storage == ArgValuetypeInReg) {
1274 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1275 cfg->disable_llvm = TRUE;
1279 cfg->exception_message = g_strdup ("vtype ret in call");
1280 cfg->disable_llvm = TRUE;
1282 linfo->ret.storage = LLVMArgVtypeInReg;
1283 for (j = 0; j < 2; ++j)
1284 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1288 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage == ArgInIReg) {
1289 /* Vtype returned using a hidden argument */
1290 linfo->ret.storage = LLVMArgVtypeRetAddr;
1291 linfo->vret_arg_index = cinfo->vret_arg_index;
1294 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage != ArgInIReg) {
1296 cfg->exception_message = g_strdup ("vtype ret in call");
1297 cfg->disable_llvm = TRUE;
1300 for (i = 0; i < n; ++i) {
1301 ainfo = cinfo->args + i;
1303 if (i >= sig->hasthis)
1304 t = sig->params [i - sig->hasthis];
1306 t = &mono_defaults.int_class->byval_arg;
1308 linfo->args [i].storage = LLVMArgNone;
1310 switch (ainfo->storage) {
1312 linfo->args [i].storage = LLVMArgNormal;
1314 case ArgInDoubleSSEReg:
1315 case ArgInFloatSSEReg:
1316 linfo->args [i].storage = LLVMArgNormal;
1319 if (mini_type_is_vtype (t)) {
1320 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1321 /* LLVM seems to allocate argument space for empty structures too */
1322 linfo->args [i].storage = LLVMArgNone;
1324 linfo->args [i].storage = LLVMArgVtypeByVal;
1326 linfo->args [i].storage = LLVMArgNormal;
1329 case ArgValuetypeInReg:
1331 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1332 cfg->disable_llvm = TRUE;
1336 cfg->exception_message = g_strdup ("vtype arg");
1337 cfg->disable_llvm = TRUE;
1339 linfo->args [i].storage = LLVMArgVtypeInReg;
1340 for (j = 0; j < 2; ++j)
1341 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1345 linfo->args [i].storage = LLVMArgGSharedVt;
1348 cfg->exception_message = g_strdup ("ainfo->storage");
1349 cfg->disable_llvm = TRUE;
1359 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1361 if (cfg->compute_gc_maps) {
1364 /* Needs checking if the feature will be enabled again */
1365 g_assert_not_reached ();
1367 /* On x86, the offsets are from the sp value before the start of the call sequence */
1369 t = &mono_defaults.int_class->byval_arg;
1370 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1375 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1379 MonoMethodSignature *sig;
1382 int sentinelpos = 0, sp_offset = 0;
1384 sig = call->signature;
1385 n = sig->param_count + sig->hasthis;
1386 sig_ret = mini_get_underlying_type (sig->ret);
1388 cinfo = get_call_info (cfg->mempool, sig);
1389 call->call_info = cinfo;
1391 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1392 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1394 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1395 if (cinfo->ret.storage == ArgValuetypeInReg) {
1397 * Tell the JIT to use a more efficient calling convention: call using
1398 * OP_CALL, compute the result location after the call, and save the
1401 call->vret_in_reg = TRUE;
1402 #if defined(__APPLE__)
1403 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1404 call->vret_in_reg_fp = TRUE;
1407 NULLIFY_INS (call->vret_var);
1411 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1413 /* Handle the case where there are no implicit arguments */
1414 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1415 emit_sig_cookie (cfg, call, cinfo);
1416 sp_offset = cinfo->sig_cookie.offset;
1417 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1420 /* Arguments are pushed in the reverse order */
1421 for (i = n - 1; i >= 0; i --) {
1422 ArgInfo *ainfo = cinfo->args + i;
1423 MonoType *orig_type, *t;
1426 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1429 /* Push the vret arg before the first argument */
1430 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1431 vtarg->type = STACK_MP;
1432 vtarg->inst_destbasereg = X86_ESP;
1433 vtarg->sreg1 = call->vret_var->dreg;
1434 vtarg->inst_offset = cinfo->ret.offset;
1435 MONO_ADD_INS (cfg->cbb, vtarg);
1436 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1439 if (i >= sig->hasthis)
1440 t = sig->params [i - sig->hasthis];
1442 t = &mono_defaults.int_class->byval_arg;
1444 t = mini_get_underlying_type (t);
1446 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1448 in = call->args [i];
1449 arg->cil_code = in->cil_code;
1450 arg->sreg1 = in->dreg;
1451 arg->type = in->type;
1453 g_assert (in->dreg != -1);
1455 if (ainfo->storage == ArgGSharedVt) {
1456 arg->opcode = OP_OUTARG_VT;
1457 arg->sreg1 = in->dreg;
1458 arg->klass = in->klass;
1459 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1460 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1462 MONO_ADD_INS (cfg->cbb, arg);
1463 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1467 g_assert (in->klass);
1469 if (t->type == MONO_TYPE_TYPEDBYREF) {
1470 size = sizeof (MonoTypedRef);
1471 align = sizeof (gpointer);
1474 size = mini_type_stack_size_full (&in->klass->byval_arg, &align, sig->pinvoke);
1478 arg->opcode = OP_OUTARG_VT;
1479 arg->sreg1 = in->dreg;
1480 arg->klass = in->klass;
1481 arg->backend.size = size;
1482 arg->inst_p0 = call;
1483 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1484 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1486 MONO_ADD_INS (cfg->cbb, arg);
1487 if (ainfo->storage != ArgValuetypeInReg) {
1488 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1492 switch (ainfo->storage) {
1495 if (t->type == MONO_TYPE_R4) {
1496 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1498 } else if (t->type == MONO_TYPE_R8) {
1499 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1501 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1502 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, MONO_LVREG_MS (in->dreg));
1503 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, MONO_LVREG_LS (in->dreg));
1506 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1510 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1515 arg->opcode = OP_MOVE;
1516 arg->dreg = ainfo->reg;
1517 MONO_ADD_INS (cfg->cbb, arg);
1521 g_assert_not_reached ();
1524 if (cfg->compute_gc_maps) {
1526 /* FIXME: The == STACK_OBJ check might be fragile ? */
1527 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1529 if (call->need_unbox_trampoline)
1530 /* The unbox trampoline transforms this into a managed pointer */
1531 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.int_class->this_arg);
1533 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.object_class->byval_arg);
1535 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1539 for (j = 0; j < argsize; j += 4)
1540 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1545 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1546 /* Emit the signature cookie just before the implicit arguments */
1547 emit_sig_cookie (cfg, call, cinfo);
1548 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1552 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1555 if (cinfo->ret.storage == ArgValuetypeInReg) {
1558 else if (cinfo->ret.storage == ArgInIReg) {
1560 /* The return address is passed in a register */
1561 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1562 vtarg->sreg1 = call->inst.dreg;
1563 vtarg->dreg = mono_alloc_ireg (cfg);
1564 MONO_ADD_INS (cfg->cbb, vtarg);
1566 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1567 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1568 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1569 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1573 call->stack_usage = cinfo->stack_usage;
1574 call->stack_align_amount = cinfo->stack_align_amount;
1578 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1580 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1581 ArgInfo *ainfo = ins->inst_p1;
1582 int size = ins->backend.size;
1584 if (ainfo->storage == ArgValuetypeInReg) {
1585 int dreg = mono_alloc_ireg (cfg);
1588 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1591 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1594 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1598 g_assert_not_reached ();
1600 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1603 if (cfg->gsharedvt && mini_is_gsharedvt_klass (ins->klass)) {
1605 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1606 } else if (size <= 4) {
1607 int dreg = mono_alloc_ireg (cfg);
1608 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1609 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1610 } else if (size <= 20) {
1611 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1613 // FIXME: Code growth
1614 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1620 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1622 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
1625 if (ret->type == MONO_TYPE_R4) {
1626 if (COMPILE_LLVM (cfg))
1627 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1630 } else if (ret->type == MONO_TYPE_R8) {
1631 if (COMPILE_LLVM (cfg))
1632 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1635 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1636 if (COMPILE_LLVM (cfg))
1637 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1639 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, MONO_LVREG_LS (val->dreg));
1640 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, MONO_LVREG_MS (val->dreg));
1646 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1650 * Allow tracing to work with this interface (with an optional argument)
1653 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1657 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1658 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1660 /* if some args are passed in registers, we need to save them here */
1661 x86_push_reg (code, X86_EBP);
1663 if (cfg->compile_aot) {
1664 x86_push_imm (code, cfg->method);
1665 x86_mov_reg_imm (code, X86_EAX, func);
1666 x86_call_reg (code, X86_EAX);
1668 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1669 x86_push_imm (code, cfg->method);
1670 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1671 x86_call_code (code, 0);
1673 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1687 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1690 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1691 MonoMethod *method = cfg->method;
1692 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
1694 switch (ret_type->type) {
1695 case MONO_TYPE_VOID:
1696 /* special case string .ctor icall */
1697 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1698 save_mode = SAVE_EAX;
1699 stack_usage = enable_arguments ? 8 : 4;
1701 save_mode = SAVE_NONE;
1705 save_mode = SAVE_EAX_EDX;
1706 stack_usage = enable_arguments ? 16 : 8;
1710 save_mode = SAVE_FP;
1711 stack_usage = enable_arguments ? 16 : 8;
1713 case MONO_TYPE_GENERICINST:
1714 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1715 save_mode = SAVE_EAX;
1716 stack_usage = enable_arguments ? 8 : 4;
1720 case MONO_TYPE_VALUETYPE:
1721 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1722 save_mode = SAVE_STRUCT;
1723 stack_usage = enable_arguments ? 4 : 0;
1726 save_mode = SAVE_EAX;
1727 stack_usage = enable_arguments ? 8 : 4;
1731 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1733 switch (save_mode) {
1735 x86_push_reg (code, X86_EDX);
1736 x86_push_reg (code, X86_EAX);
1737 if (enable_arguments) {
1738 x86_push_reg (code, X86_EDX);
1739 x86_push_reg (code, X86_EAX);
1744 x86_push_reg (code, X86_EAX);
1745 if (enable_arguments) {
1746 x86_push_reg (code, X86_EAX);
1751 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1752 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1753 if (enable_arguments) {
1754 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1755 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1760 if (enable_arguments) {
1761 x86_push_membase (code, X86_EBP, 8);
1770 if (cfg->compile_aot) {
1771 x86_push_imm (code, method);
1772 x86_mov_reg_imm (code, X86_EAX, func);
1773 x86_call_reg (code, X86_EAX);
1775 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1776 x86_push_imm (code, method);
1777 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1778 x86_call_code (code, 0);
1781 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1783 switch (save_mode) {
1785 x86_pop_reg (code, X86_EAX);
1786 x86_pop_reg (code, X86_EDX);
1789 x86_pop_reg (code, X86_EAX);
1792 x86_fld_membase (code, X86_ESP, 0, TRUE);
1793 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1800 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1805 #define EMIT_COND_BRANCH(ins,cond,sign) \
1806 if (ins->inst_true_bb->native_offset) { \
1807 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1809 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1810 if ((cfg->opt & MONO_OPT_BRANCH) && \
1811 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1812 x86_branch8 (code, cond, 0, sign); \
1814 x86_branch32 (code, cond, 0, sign); \
1818 * Emit an exception if condition is fail and
1819 * if possible do a directly branch to target
1821 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1823 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1824 if (tins == NULL) { \
1825 mono_add_patch_info (cfg, code - cfg->native_code, \
1826 MONO_PATCH_INFO_EXC, exc_name); \
1827 x86_branch32 (code, cond, 0, signed); \
1829 EMIT_COND_BRANCH (tins, cond, signed); \
1833 #define EMIT_FPCOMPARE(code) do { \
1834 x86_fcompp (code); \
1835 x86_fnstsw (code); \
1840 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1842 gboolean needs_paddings = TRUE;
1844 MonoJumpInfo *jinfo = NULL;
1846 if (cfg->abs_patches) {
1847 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1848 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1849 needs_paddings = FALSE;
1852 if (cfg->compile_aot)
1853 needs_paddings = FALSE;
1854 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1855 This is required for code patching to be safe on SMP machines.
1857 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1858 #ifndef __native_client_codegen__
1859 if (needs_paddings && pad_size)
1860 x86_padding (code, 4 - pad_size);
1863 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1864 x86_call_code (code, 0);
1869 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1872 * mono_peephole_pass_1:
1874 * Perform peephole opts which should/can be performed before local regalloc
1877 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1881 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1882 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1884 switch (ins->opcode) {
1887 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1889 * X86_LEA is like ADD, but doesn't have the
1890 * sreg1==dreg restriction.
1892 ins->opcode = OP_X86_LEA_MEMBASE;
1893 ins->inst_basereg = ins->sreg1;
1894 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1895 ins->opcode = OP_X86_INC_REG;
1899 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1900 ins->opcode = OP_X86_LEA_MEMBASE;
1901 ins->inst_basereg = ins->sreg1;
1902 ins->inst_imm = -ins->inst_imm;
1903 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1904 ins->opcode = OP_X86_DEC_REG;
1906 case OP_COMPARE_IMM:
1907 case OP_ICOMPARE_IMM:
1908 /* OP_COMPARE_IMM (reg, 0)
1910 * OP_X86_TEST_NULL (reg)
1913 ins->opcode = OP_X86_TEST_NULL;
1915 case OP_X86_COMPARE_MEMBASE_IMM:
1917 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1918 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1920 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1921 * OP_COMPARE_IMM reg, imm
1923 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1925 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1926 ins->inst_basereg == last_ins->inst_destbasereg &&
1927 ins->inst_offset == last_ins->inst_offset) {
1928 ins->opcode = OP_COMPARE_IMM;
1929 ins->sreg1 = last_ins->sreg1;
1931 /* check if we can remove cmp reg,0 with test null */
1933 ins->opcode = OP_X86_TEST_NULL;
1937 case OP_X86_PUSH_MEMBASE:
1938 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1939 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1940 ins->inst_basereg == last_ins->inst_destbasereg &&
1941 ins->inst_offset == last_ins->inst_offset) {
1942 ins->opcode = OP_X86_PUSH;
1943 ins->sreg1 = last_ins->sreg1;
1948 mono_peephole_ins (bb, ins);
1953 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1957 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1958 switch (ins->opcode) {
1960 /* reg = 0 -> XOR (reg, reg) */
1961 /* XOR sets cflags on x86, so we cant do it always */
1962 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1965 ins->opcode = OP_IXOR;
1966 ins->sreg1 = ins->dreg;
1967 ins->sreg2 = ins->dreg;
1970 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1971 * since it takes 3 bytes instead of 7.
1973 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
1974 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1975 ins2->opcode = OP_STORE_MEMBASE_REG;
1976 ins2->sreg1 = ins->dreg;
1978 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1979 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1980 ins2->sreg1 = ins->dreg;
1982 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1983 /* Continue iteration */
1992 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1993 ins->opcode = OP_X86_INC_REG;
1997 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1998 ins->opcode = OP_X86_DEC_REG;
2002 mono_peephole_ins (bb, ins);
2007 * mono_arch_lowering_pass:
2009 * Converts complex opcodes into simpler ones so that each IR instruction
2010 * corresponds to one machine instruction.
2013 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2015 MonoInst *ins, *next;
2018 * FIXME: Need to add more instructions, but the current machine
2019 * description can't model some parts of the composite instructions like
2022 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2023 switch (ins->opcode) {
2026 case OP_IDIV_UN_IMM:
2027 case OP_IREM_UN_IMM:
2029 * Keep the cases where we could generated optimized code, otherwise convert
2030 * to the non-imm variant.
2032 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2034 mono_decompose_op_imm (cfg, bb, ins);
2041 bb->max_vreg = cfg->next_vreg;
2045 branch_cc_table [] = {
2046 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2047 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2048 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2051 /* Maps CMP_... constants to X86_CC_... constants */
2054 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2055 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2059 cc_signed_table [] = {
2060 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2061 FALSE, FALSE, FALSE, FALSE
2064 static unsigned char*
2065 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2067 #define XMM_TEMP_REG 0
2068 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2069 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2070 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2071 /* optimize by assigning a local var for this use so we avoid
2072 * the stack manipulations */
2073 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2074 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2075 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2076 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2077 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2079 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2081 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2084 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2085 x86_fnstcw_membase(code, X86_ESP, 0);
2086 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2087 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2088 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2089 x86_fldcw_membase (code, X86_ESP, 2);
2091 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2092 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2093 x86_pop_reg (code, dreg);
2094 /* FIXME: need the high register
2095 * x86_pop_reg (code, dreg_high);
2098 x86_push_reg (code, X86_EAX); // SP = SP - 4
2099 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2100 x86_pop_reg (code, dreg);
2102 x86_fldcw_membase (code, X86_ESP, 0);
2103 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2106 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2108 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2112 static unsigned char*
2113 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2115 int sreg = tree->sreg1;
2116 int need_touch = FALSE;
2118 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2127 * If requested stack size is larger than one page,
2128 * perform stack-touch operation
2131 * Generate stack probe code.
2132 * Under Windows, it is necessary to allocate one page at a time,
2133 * "touching" stack after each successful sub-allocation. This is
2134 * because of the way stack growth is implemented - there is a
2135 * guard page before the lowest stack page that is currently commited.
2136 * Stack normally grows sequentially so OS traps access to the
2137 * guard page and commits more pages when needed.
2139 x86_test_reg_imm (code, sreg, ~0xFFF);
2140 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2142 br[2] = code; /* loop */
2143 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2144 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2147 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2148 * that follows only initializes the last part of the area.
2150 /* Same as the init code below with size==0x1000 */
2151 if (tree->flags & MONO_INST_INIT) {
2152 x86_push_reg (code, X86_EAX);
2153 x86_push_reg (code, X86_ECX);
2154 x86_push_reg (code, X86_EDI);
2155 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2156 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2157 if (cfg->param_area)
2158 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2160 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2162 x86_prefix (code, X86_REP_PREFIX);
2164 x86_pop_reg (code, X86_EDI);
2165 x86_pop_reg (code, X86_ECX);
2166 x86_pop_reg (code, X86_EAX);
2169 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2170 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2171 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2172 x86_patch (br[3], br[2]);
2173 x86_test_reg_reg (code, sreg, sreg);
2174 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2175 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2177 br[1] = code; x86_jump8 (code, 0);
2179 x86_patch (br[0], code);
2180 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2181 x86_patch (br[1], code);
2182 x86_patch (br[4], code);
2185 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2187 if (tree->flags & MONO_INST_INIT) {
2189 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2190 x86_push_reg (code, X86_EAX);
2193 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2194 x86_push_reg (code, X86_ECX);
2197 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2198 x86_push_reg (code, X86_EDI);
2202 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2203 if (sreg != X86_ECX)
2204 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2205 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2207 if (cfg->param_area)
2208 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2210 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2212 x86_prefix (code, X86_REP_PREFIX);
2215 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2216 x86_pop_reg (code, X86_EDI);
2217 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2218 x86_pop_reg (code, X86_ECX);
2219 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2220 x86_pop_reg (code, X86_EAX);
2227 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2229 /* Move return value to the target register */
2230 switch (ins->opcode) {
2233 case OP_CALL_MEMBASE:
2234 if (ins->dreg != X86_EAX)
2235 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2245 static int tls_gs_offset;
2249 mono_x86_have_tls_get (void)
2252 static gboolean have_tls_get = FALSE;
2253 static gboolean inited = FALSE;
2256 return have_tls_get;
2258 #ifdef MONO_HAVE_FAST_TLS
2261 ins = (guint32*)pthread_getspecific;
2263 * We're looking for these two instructions:
2265 * mov 0x4(%esp),%eax
2266 * mov %gs:[offset](,%eax,4),%eax
2268 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2269 tls_gs_offset = ins [2];
2274 return have_tls_get;
2275 #elif defined(TARGET_ANDROID)
2283 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2285 #if defined(__APPLE__)
2286 x86_prefix (code, X86_GS_PREFIX);
2287 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2288 #elif defined(TARGET_WIN32)
2289 g_assert_not_reached ();
2291 x86_prefix (code, X86_GS_PREFIX);
2292 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2298 * mono_x86_emit_tls_get:
2299 * @code: buffer to store code to
2300 * @dreg: hard register where to place the result
2301 * @tls_offset: offset info
2303 * mono_x86_emit_tls_get emits in @code the native code that puts in
2304 * the dreg register the item in the thread local storage identified
2307 * Returns: a pointer to the end of the stored code
2310 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2312 #if defined(__APPLE__)
2313 x86_prefix (code, X86_GS_PREFIX);
2314 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2315 #elif defined(TARGET_WIN32)
2317 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2318 * Journal and/or a disassembly of the TlsGet () function.
2320 x86_prefix (code, X86_FS_PREFIX);
2321 x86_mov_reg_mem (code, dreg, 0x18, 4);
2322 if (tls_offset < 64) {
2323 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2327 g_assert (tls_offset < 0x440);
2328 /* Load TEB->TlsExpansionSlots */
2329 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2330 x86_test_reg_reg (code, dreg, dreg);
2332 x86_branch (code, X86_CC_EQ, code, TRUE);
2333 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2334 x86_patch (buf [0], code);
2337 if (optimize_for_xen) {
2338 x86_prefix (code, X86_GS_PREFIX);
2339 x86_mov_reg_mem (code, dreg, 0, 4);
2340 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2342 x86_prefix (code, X86_GS_PREFIX);
2343 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2350 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2352 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2353 #if defined(__APPLE__) || defined(__linux__)
2354 if (dreg != offset_reg)
2355 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2356 x86_prefix (code, X86_GS_PREFIX);
2357 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2359 g_assert_not_reached ();
2365 mono_x86_emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2367 return emit_tls_get_reg (code, dreg, offset_reg);
2371 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2373 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2375 g_assert_not_reached ();
2376 #elif defined(__APPLE__) || defined(__linux__)
2377 x86_prefix (code, X86_GS_PREFIX);
2378 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2380 g_assert_not_reached ();
2386 * mono_arch_translate_tls_offset:
2388 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2391 mono_arch_translate_tls_offset (int offset)
2394 return tls_gs_offset + (offset * 4);
2403 * Emit code to initialize an LMF structure at LMF_OFFSET.
2406 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2408 /* save all caller saved regs */
2409 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2410 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2411 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2412 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2413 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2414 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2415 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2417 /* save the current IP */
2418 if (cfg->compile_aot) {
2419 /* This pushes the current ip */
2420 x86_call_imm (code, 0);
2421 x86_pop_reg (code, X86_EAX);
2423 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2424 x86_mov_reg_imm (code, X86_EAX, 0);
2426 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2428 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2429 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2430 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2431 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2432 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2433 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2434 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2435 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2436 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2441 /* benchmark and set based on cpu */
2442 #define LOOP_ALIGNMENT 8
2443 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2447 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2452 guint8 *code = cfg->native_code + cfg->code_len;
2455 if (cfg->opt & MONO_OPT_LOOP) {
2456 int pad, align = LOOP_ALIGNMENT;
2457 /* set alignment depending on cpu */
2458 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2460 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2461 x86_padding (code, pad);
2462 cfg->code_len += pad;
2463 bb->native_offset = cfg->code_len;
2466 #ifdef __native_client_codegen__
2468 /* For Native Client, all indirect call/jump targets must be */
2469 /* 32-byte aligned. Exception handler blocks are jumped to */
2470 /* indirectly as well. */
2471 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2472 (bb->flags & BB_EXCEPTION_HANDLER);
2474 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2475 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2476 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2477 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2478 cfg->code_len += pad;
2479 bb->native_offset = cfg->code_len;
2482 #endif /* __native_client_codegen__ */
2483 if (cfg->verbose_level > 2)
2484 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2486 cpos = bb->max_offset;
2488 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
2489 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2490 g_assert (!cfg->compile_aot);
2493 cov->data [bb->dfn].cil_code = bb->cil_code;
2494 /* this is not thread save, but good enough */
2495 x86_inc_mem (code, &cov->data [bb->dfn].count);
2498 offset = code - cfg->native_code;
2500 mono_debug_open_block (cfg, bb, offset);
2502 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2503 x86_breakpoint (code);
2505 MONO_BB_FOR_EACH_INS (bb, ins) {
2506 offset = code - cfg->native_code;
2508 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2510 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2512 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2513 cfg->code_size *= 2;
2514 cfg->native_code = mono_realloc_native_code(cfg);
2515 code = cfg->native_code + offset;
2516 cfg->stat_code_reallocs++;
2519 if (cfg->debug_info)
2520 mono_debug_record_line_number (cfg, ins, offset);
2522 switch (ins->opcode) {
2524 x86_mul_reg (code, ins->sreg2, TRUE);
2527 x86_mul_reg (code, ins->sreg2, FALSE);
2529 case OP_X86_SETEQ_MEMBASE:
2530 case OP_X86_SETNE_MEMBASE:
2531 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2532 ins->inst_basereg, ins->inst_offset, TRUE);
2534 case OP_STOREI1_MEMBASE_IMM:
2535 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2537 case OP_STOREI2_MEMBASE_IMM:
2538 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2540 case OP_STORE_MEMBASE_IMM:
2541 case OP_STOREI4_MEMBASE_IMM:
2542 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2544 case OP_STOREI1_MEMBASE_REG:
2545 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2547 case OP_STOREI2_MEMBASE_REG:
2548 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2550 case OP_STORE_MEMBASE_REG:
2551 case OP_STOREI4_MEMBASE_REG:
2552 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2554 case OP_STORE_MEM_IMM:
2555 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2558 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2562 /* These are created by the cprop pass so they use inst_imm as the source */
2563 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2566 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2569 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2571 case OP_LOAD_MEMBASE:
2572 case OP_LOADI4_MEMBASE:
2573 case OP_LOADU4_MEMBASE:
2574 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2576 case OP_LOADU1_MEMBASE:
2577 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2579 case OP_LOADI1_MEMBASE:
2580 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2582 case OP_LOADU2_MEMBASE:
2583 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2585 case OP_LOADI2_MEMBASE:
2586 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2588 case OP_ICONV_TO_I1:
2590 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2592 case OP_ICONV_TO_I2:
2594 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2596 case OP_ICONV_TO_U1:
2597 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2599 case OP_ICONV_TO_U2:
2600 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2604 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2606 case OP_COMPARE_IMM:
2607 case OP_ICOMPARE_IMM:
2608 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2610 case OP_X86_COMPARE_MEMBASE_REG:
2611 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2613 case OP_X86_COMPARE_MEMBASE_IMM:
2614 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2616 case OP_X86_COMPARE_MEMBASE8_IMM:
2617 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2619 case OP_X86_COMPARE_REG_MEMBASE:
2620 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2622 case OP_X86_COMPARE_MEM_IMM:
2623 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2625 case OP_X86_TEST_NULL:
2626 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2628 case OP_X86_ADD_MEMBASE_IMM:
2629 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2631 case OP_X86_ADD_REG_MEMBASE:
2632 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2634 case OP_X86_SUB_MEMBASE_IMM:
2635 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2637 case OP_X86_SUB_REG_MEMBASE:
2638 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2640 case OP_X86_AND_MEMBASE_IMM:
2641 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2643 case OP_X86_OR_MEMBASE_IMM:
2644 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2646 case OP_X86_XOR_MEMBASE_IMM:
2647 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2649 case OP_X86_ADD_MEMBASE_REG:
2650 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2652 case OP_X86_SUB_MEMBASE_REG:
2653 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2655 case OP_X86_AND_MEMBASE_REG:
2656 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2658 case OP_X86_OR_MEMBASE_REG:
2659 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2661 case OP_X86_XOR_MEMBASE_REG:
2662 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2664 case OP_X86_INC_MEMBASE:
2665 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2667 case OP_X86_INC_REG:
2668 x86_inc_reg (code, ins->dreg);
2670 case OP_X86_DEC_MEMBASE:
2671 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2673 case OP_X86_DEC_REG:
2674 x86_dec_reg (code, ins->dreg);
2676 case OP_X86_MUL_REG_MEMBASE:
2677 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2679 case OP_X86_AND_REG_MEMBASE:
2680 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2682 case OP_X86_OR_REG_MEMBASE:
2683 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2685 case OP_X86_XOR_REG_MEMBASE:
2686 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2689 x86_breakpoint (code);
2691 case OP_RELAXED_NOP:
2692 x86_prefix (code, X86_REP_PREFIX);
2700 case OP_DUMMY_STORE:
2701 case OP_DUMMY_ICONST:
2702 case OP_DUMMY_R8CONST:
2703 case OP_NOT_REACHED:
2706 case OP_IL_SEQ_POINT:
2707 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2709 case OP_SEQ_POINT: {
2712 if (cfg->compile_aot)
2715 /* Have to use ecx as a temp reg since this can occur after OP_SETRET */
2718 * We do this _before_ the breakpoint, so single stepping after
2719 * a breakpoint is hit will step to the next IL offset.
2721 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
2722 MonoInst *var = cfg->arch.ss_tramp_var;
2726 g_assert (var->opcode == OP_REGOFFSET);
2727 /* Load ss_tramp_var */
2728 /* This is equal to &ss_trampoline */
2729 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, sizeof (mgreg_t));
2730 x86_alu_membase_imm (code, X86_CMP, X86_ECX, 0, 0);
2731 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2732 x86_call_membase (code, X86_ECX, 0);
2733 x86_patch (br [0], code);
2737 * Many parts of sdb depend on the ip after the single step trampoline call to be equal to the seq point offset.
2738 * This means we have to put the loading of bp_tramp_var after the offset.
2741 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2743 MonoInst *var = cfg->arch.bp_tramp_var;
2746 g_assert (var->opcode == OP_REGOFFSET);
2747 /* Load the address of the bp trampoline */
2748 /* This needs to be constant size */
2749 guint8 *start = code;
2750 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, 4);
2751 if (code < start + OP_SEQ_POINT_BP_OFFSET) {
2752 int size = start + OP_SEQ_POINT_BP_OFFSET - code;
2753 x86_padding (code, size);
2756 * A placeholder for a possible breakpoint inserted by
2757 * mono_arch_set_breakpoint ().
2759 for (i = 0; i < 2; ++i)
2762 * Add an additional nop so skipping the bp doesn't cause the ip to point
2763 * to another IL offset.
2771 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2775 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2780 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2784 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2789 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2793 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2798 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2802 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2805 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2809 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2813 #if defined( __native_client_codegen__ )
2814 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2815 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2818 * The code is the same for div/rem, the allocator will allocate dreg
2819 * to RAX/RDX as appropriate.
2821 if (ins->sreg2 == X86_EDX) {
2822 /* cdq clobbers this */
2823 x86_push_reg (code, ins->sreg2);
2825 x86_div_membase (code, X86_ESP, 0, TRUE);
2826 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2829 x86_div_reg (code, ins->sreg2, TRUE);
2834 #if defined( __native_client_codegen__ )
2835 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2836 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2838 if (ins->sreg2 == X86_EDX) {
2839 x86_push_reg (code, ins->sreg2);
2840 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2841 x86_div_membase (code, X86_ESP, 0, FALSE);
2842 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2844 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2845 x86_div_reg (code, ins->sreg2, FALSE);
2849 #if defined( __native_client_codegen__ )
2850 if (ins->inst_imm == 0) {
2851 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2852 x86_jump32 (code, 0);
2856 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2858 x86_div_reg (code, ins->sreg2, TRUE);
2861 int power = mono_is_power_of_two (ins->inst_imm);
2863 g_assert (ins->sreg1 == X86_EAX);
2864 g_assert (ins->dreg == X86_EAX);
2865 g_assert (power >= 0);
2868 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2870 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2872 * If the divident is >= 0, this does not nothing. If it is positive, it
2873 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2875 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2876 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2877 } else if (power == 0) {
2878 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2880 /* Based on gcc code */
2882 /* Add compensation for negative dividents */
2884 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2885 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2886 /* Compute remainder */
2887 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2888 /* Remove compensation */
2889 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2894 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2898 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2901 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2905 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2908 g_assert (ins->sreg2 == X86_ECX);
2909 x86_shift_reg (code, X86_SHL, ins->dreg);
2912 g_assert (ins->sreg2 == X86_ECX);
2913 x86_shift_reg (code, X86_SAR, ins->dreg);
2917 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2920 case OP_ISHR_UN_IMM:
2921 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2924 g_assert (ins->sreg2 == X86_ECX);
2925 x86_shift_reg (code, X86_SHR, ins->dreg);
2929 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2932 guint8 *jump_to_end;
2934 /* handle shifts below 32 bits */
2935 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2936 x86_shift_reg (code, X86_SHL, ins->sreg1);
2938 x86_test_reg_imm (code, X86_ECX, 32);
2939 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2941 /* handle shift over 32 bit */
2942 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2943 x86_clear_reg (code, ins->sreg1);
2945 x86_patch (jump_to_end, code);
2949 guint8 *jump_to_end;
2951 /* handle shifts below 32 bits */
2952 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2953 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2955 x86_test_reg_imm (code, X86_ECX, 32);
2956 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2958 /* handle shifts over 31 bits */
2959 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2960 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2962 x86_patch (jump_to_end, code);
2966 guint8 *jump_to_end;
2968 /* handle shifts below 32 bits */
2969 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2970 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2972 x86_test_reg_imm (code, X86_ECX, 32);
2973 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2975 /* handle shifts over 31 bits */
2976 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2977 x86_clear_reg (code, ins->backend.reg3);
2979 x86_patch (jump_to_end, code);
2983 if (ins->inst_imm >= 32) {
2984 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2985 x86_clear_reg (code, ins->sreg1);
2986 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2988 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2989 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2993 if (ins->inst_imm >= 32) {
2994 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2995 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2996 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2998 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2999 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3002 case OP_LSHR_UN_IMM:
3003 if (ins->inst_imm >= 32) {
3004 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3005 x86_clear_reg (code, ins->backend.reg3);
3006 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3008 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3009 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3013 x86_not_reg (code, ins->sreg1);
3016 x86_neg_reg (code, ins->sreg1);
3020 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3024 switch (ins->inst_imm) {
3028 if (ins->dreg != ins->sreg1)
3029 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3030 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3033 /* LEA r1, [r2 + r2*2] */
3034 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3037 /* LEA r1, [r2 + r2*4] */
3038 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3041 /* LEA r1, [r2 + r2*2] */
3043 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3044 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3047 /* LEA r1, [r2 + r2*8] */
3048 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3051 /* LEA r1, [r2 + r2*4] */
3053 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3054 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3057 /* LEA r1, [r2 + r2*2] */
3059 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3060 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3063 /* LEA r1, [r2 + r2*4] */
3064 /* LEA r1, [r1 + r1*4] */
3065 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3066 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3069 /* LEA r1, [r2 + r2*4] */
3071 /* LEA r1, [r1 + r1*4] */
3072 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3073 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3074 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3077 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3082 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3083 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3085 case OP_IMUL_OVF_UN: {
3086 /* the mul operation and the exception check should most likely be split */
3087 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3088 /*g_assert (ins->sreg2 == X86_EAX);
3089 g_assert (ins->dreg == X86_EAX);*/
3090 if (ins->sreg2 == X86_EAX) {
3091 non_eax_reg = ins->sreg1;
3092 } else if (ins->sreg1 == X86_EAX) {
3093 non_eax_reg = ins->sreg2;
3095 /* no need to save since we're going to store to it anyway */
3096 if (ins->dreg != X86_EAX) {
3098 x86_push_reg (code, X86_EAX);
3100 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3101 non_eax_reg = ins->sreg2;
3103 if (ins->dreg == X86_EDX) {
3106 x86_push_reg (code, X86_EAX);
3110 x86_push_reg (code, X86_EDX);
3112 x86_mul_reg (code, non_eax_reg, FALSE);
3113 /* save before the check since pop and mov don't change the flags */
3114 if (ins->dreg != X86_EAX)
3115 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3117 x86_pop_reg (code, X86_EDX);
3119 x86_pop_reg (code, X86_EAX);
3120 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3124 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3127 g_assert_not_reached ();
3128 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3129 x86_mov_reg_imm (code, ins->dreg, 0);
3132 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3133 x86_mov_reg_imm (code, ins->dreg, 0);
3135 case OP_LOAD_GOTADDR:
3136 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3137 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3140 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3141 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3143 case OP_X86_PUSH_GOT_ENTRY:
3144 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3145 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3148 if (ins->dreg != ins->sreg1)
3149 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3152 MonoCallInst *call = (MonoCallInst*)ins;
3155 ins->flags |= MONO_INST_GC_CALLSITE;
3156 ins->backend.pc_offset = code - cfg->native_code;
3158 /* reset offset to make max_len work */
3159 offset = code - cfg->native_code;
3161 g_assert (!cfg->method->save_lmf);
3163 /* restore callee saved registers */
3164 for (i = 0; i < X86_NREG; ++i)
3165 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3167 if (cfg->used_int_regs & (1 << X86_ESI)) {
3168 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3171 if (cfg->used_int_regs & (1 << X86_EDI)) {
3172 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3175 if (cfg->used_int_regs & (1 << X86_EBX)) {
3176 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3180 /* Copy arguments on the stack to our argument area */
3181 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3182 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3183 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3186 /* restore ESP/EBP */
3188 offset = code - cfg->native_code;
3189 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3190 x86_jump32 (code, 0);
3192 ins->flags |= MONO_INST_GC_CALLSITE;
3193 cfg->disable_aot = TRUE;
3197 /* ensure ins->sreg1 is not NULL
3198 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3199 * cmp DWORD PTR [eax], 0
3201 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3204 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3205 x86_push_reg (code, hreg);
3206 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3207 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3208 x86_pop_reg (code, hreg);
3221 case OP_VOIDCALL_REG:
3223 case OP_FCALL_MEMBASE:
3224 case OP_LCALL_MEMBASE:
3225 case OP_VCALL_MEMBASE:
3226 case OP_VCALL2_MEMBASE:
3227 case OP_VOIDCALL_MEMBASE:
3228 case OP_CALL_MEMBASE: {
3231 call = (MonoCallInst*)ins;
3232 cinfo = (CallInfo*)call->call_info;
3234 switch (ins->opcode) {
3241 if (ins->flags & MONO_INST_HAS_METHOD)
3242 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3244 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3250 case OP_VOIDCALL_REG:
3252 x86_call_reg (code, ins->sreg1);
3254 case OP_FCALL_MEMBASE:
3255 case OP_LCALL_MEMBASE:
3256 case OP_VCALL_MEMBASE:
3257 case OP_VCALL2_MEMBASE:
3258 case OP_VOIDCALL_MEMBASE:
3259 case OP_CALL_MEMBASE:
3260 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3263 g_assert_not_reached ();
3266 ins->flags |= MONO_INST_GC_CALLSITE;
3267 ins->backend.pc_offset = code - cfg->native_code;
3268 if (cinfo->callee_stack_pop) {
3269 /* Have to compensate for the stack space popped by the callee */
3270 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3272 code = emit_move_return_value (cfg, ins, code);
3276 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3278 case OP_X86_LEA_MEMBASE:
3279 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3282 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3285 /* keep alignment */
3286 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3287 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3288 code = mono_emit_stack_alloc (cfg, code, ins);
3289 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3290 if (cfg->param_area)
3291 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3293 case OP_LOCALLOC_IMM: {
3294 guint32 size = ins->inst_imm;
3295 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3297 if (ins->flags & MONO_INST_INIT) {
3298 /* FIXME: Optimize this */
3299 x86_mov_reg_imm (code, ins->dreg, size);
3300 ins->sreg1 = ins->dreg;
3302 code = mono_emit_stack_alloc (cfg, code, ins);
3303 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3305 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3306 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3308 if (cfg->param_area)
3309 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3313 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3314 x86_push_reg (code, ins->sreg1);
3315 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3316 (gpointer)"mono_arch_throw_exception");
3317 ins->flags |= MONO_INST_GC_CALLSITE;
3318 ins->backend.pc_offset = code - cfg->native_code;
3322 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3323 x86_push_reg (code, ins->sreg1);
3324 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3325 (gpointer)"mono_arch_rethrow_exception");
3326 ins->flags |= MONO_INST_GC_CALLSITE;
3327 ins->backend.pc_offset = code - cfg->native_code;
3330 case OP_CALL_HANDLER:
3331 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3332 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3333 x86_call_imm (code, 0);
3334 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3335 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3337 case OP_START_HANDLER: {
3338 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3339 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3340 if (cfg->param_area)
3341 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3344 case OP_ENDFINALLY: {
3345 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3346 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3350 case OP_ENDFILTER: {
3351 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3352 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3353 /* The local allocator will put the result into EAX */
3358 if (ins->dreg != X86_EAX)
3359 x86_mov_reg_reg (code, ins->dreg, X86_EAX, sizeof (gpointer));
3363 ins->inst_c0 = code - cfg->native_code;
3366 if (ins->inst_target_bb->native_offset) {
3367 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3369 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3370 if ((cfg->opt & MONO_OPT_BRANCH) &&
3371 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3372 x86_jump8 (code, 0);
3374 x86_jump32 (code, 0);
3378 x86_jump_reg (code, ins->sreg1);
3397 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3398 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3400 case OP_COND_EXC_EQ:
3401 case OP_COND_EXC_NE_UN:
3402 case OP_COND_EXC_LT:
3403 case OP_COND_EXC_LT_UN:
3404 case OP_COND_EXC_GT:
3405 case OP_COND_EXC_GT_UN:
3406 case OP_COND_EXC_GE:
3407 case OP_COND_EXC_GE_UN:
3408 case OP_COND_EXC_LE:
3409 case OP_COND_EXC_LE_UN:
3410 case OP_COND_EXC_IEQ:
3411 case OP_COND_EXC_INE_UN:
3412 case OP_COND_EXC_ILT:
3413 case OP_COND_EXC_ILT_UN:
3414 case OP_COND_EXC_IGT:
3415 case OP_COND_EXC_IGT_UN:
3416 case OP_COND_EXC_IGE:
3417 case OP_COND_EXC_IGE_UN:
3418 case OP_COND_EXC_ILE:
3419 case OP_COND_EXC_ILE_UN:
3420 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3422 case OP_COND_EXC_OV:
3423 case OP_COND_EXC_NO:
3425 case OP_COND_EXC_NC:
3426 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3428 case OP_COND_EXC_IOV:
3429 case OP_COND_EXC_INO:
3430 case OP_COND_EXC_IC:
3431 case OP_COND_EXC_INC:
3432 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3444 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3452 case OP_CMOV_INE_UN:
3453 case OP_CMOV_IGE_UN:
3454 case OP_CMOV_IGT_UN:
3455 case OP_CMOV_ILE_UN:
3456 case OP_CMOV_ILT_UN:
3457 g_assert (ins->dreg == ins->sreg1);
3458 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3461 /* floating point opcodes */
3463 double d = *(double *)ins->inst_p0;
3465 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3467 } else if (d == 1.0) {
3470 if (cfg->compile_aot) {
3471 guint32 *val = (guint32*)&d;
3472 x86_push_imm (code, val [1]);
3473 x86_push_imm (code, val [0]);
3474 x86_fld_membase (code, X86_ESP, 0, TRUE);
3475 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3478 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3479 x86_fld (code, NULL, TRUE);
3485 float f = *(float *)ins->inst_p0;
3487 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3489 } else if (f == 1.0) {
3492 if (cfg->compile_aot) {
3493 guint32 val = *(guint32*)&f;
3494 x86_push_imm (code, val);
3495 x86_fld_membase (code, X86_ESP, 0, FALSE);
3496 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3499 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3500 x86_fld (code, NULL, FALSE);
3505 case OP_STORER8_MEMBASE_REG:
3506 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3508 case OP_LOADR8_MEMBASE:
3509 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3511 case OP_STORER4_MEMBASE_REG:
3512 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3514 case OP_LOADR4_MEMBASE:
3515 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3517 case OP_ICONV_TO_R4:
3518 x86_push_reg (code, ins->sreg1);
3519 x86_fild_membase (code, X86_ESP, 0, FALSE);
3520 /* Change precision */
3521 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3522 x86_fld_membase (code, X86_ESP, 0, FALSE);
3523 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3525 case OP_ICONV_TO_R8:
3526 x86_push_reg (code, ins->sreg1);
3527 x86_fild_membase (code, X86_ESP, 0, FALSE);
3528 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3530 case OP_ICONV_TO_R_UN:
3531 x86_push_imm (code, 0);
3532 x86_push_reg (code, ins->sreg1);
3533 x86_fild_membase (code, X86_ESP, 0, TRUE);
3534 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3536 case OP_X86_FP_LOAD_I8:
3537 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3539 case OP_X86_FP_LOAD_I4:
3540 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3542 case OP_FCONV_TO_R4:
3543 /* Change precision */
3544 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3545 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3546 x86_fld_membase (code, X86_ESP, 0, FALSE);
3547 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3549 case OP_FCONV_TO_I1:
3550 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3552 case OP_FCONV_TO_U1:
3553 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3555 case OP_FCONV_TO_I2:
3556 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3558 case OP_FCONV_TO_U2:
3559 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3561 case OP_FCONV_TO_I4:
3563 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3565 case OP_FCONV_TO_I8:
3566 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3567 x86_fnstcw_membase(code, X86_ESP, 0);
3568 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3569 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3570 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3571 x86_fldcw_membase (code, X86_ESP, 2);
3572 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3573 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3574 x86_pop_reg (code, ins->dreg);
3575 x86_pop_reg (code, ins->backend.reg3);
3576 x86_fldcw_membase (code, X86_ESP, 0);
3577 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3579 case OP_LCONV_TO_R8_2:
3580 x86_push_reg (code, ins->sreg2);
3581 x86_push_reg (code, ins->sreg1);
3582 x86_fild_membase (code, X86_ESP, 0, TRUE);
3583 /* Change precision */
3584 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3585 x86_fld_membase (code, X86_ESP, 0, TRUE);
3586 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3588 case OP_LCONV_TO_R4_2:
3589 x86_push_reg (code, ins->sreg2);
3590 x86_push_reg (code, ins->sreg1);
3591 x86_fild_membase (code, X86_ESP, 0, TRUE);
3592 /* Change precision */
3593 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3594 x86_fld_membase (code, X86_ESP, 0, FALSE);
3595 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3597 case OP_LCONV_TO_R_UN_2: {
3598 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3601 /* load 64bit integer to FP stack */
3602 x86_push_reg (code, ins->sreg2);
3603 x86_push_reg (code, ins->sreg1);
3604 x86_fild_membase (code, X86_ESP, 0, TRUE);
3606 /* test if lreg is negative */
3607 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3608 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3610 /* add correction constant mn */
3611 if (cfg->compile_aot) {
3612 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3613 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3614 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3615 x86_fld80_membase (code, X86_ESP, 2);
3616 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3618 x86_fld80_mem (code, mn);
3620 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3622 x86_patch (br, code);
3624 /* Change precision */
3625 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3626 x86_fld_membase (code, X86_ESP, 0, TRUE);
3628 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3632 case OP_LCONV_TO_OVF_I:
3633 case OP_LCONV_TO_OVF_I4_2: {
3634 guint8 *br [3], *label [1];
3638 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3640 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3642 /* If the low word top bit is set, see if we are negative */
3643 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3644 /* We are not negative (no top bit set, check for our top word to be zero */
3645 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3646 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3649 /* throw exception */
3650 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3652 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3653 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3654 x86_jump8 (code, 0);
3656 x86_jump32 (code, 0);
3658 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3659 x86_jump32 (code, 0);
3663 x86_patch (br [0], code);
3664 /* our top bit is set, check that top word is 0xfffffff */
3665 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3667 x86_patch (br [1], code);
3668 /* nope, emit exception */
3669 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3670 x86_patch (br [2], label [0]);
3672 if (ins->dreg != ins->sreg1)
3673 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3677 /* Not needed on the fp stack */
3679 case OP_MOVE_F_TO_I4:
3680 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
3681 x86_mov_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, 4);
3683 case OP_MOVE_I4_TO_F:
3684 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
3685 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
3688 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3691 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3694 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3697 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3705 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3710 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3717 * it really doesn't make sense to inline all this code,
3718 * it's here just to show that things may not be as simple
3721 guchar *check_pos, *end_tan, *pop_jump;
3722 x86_push_reg (code, X86_EAX);
3725 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3727 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3728 x86_fstp (code, 0); /* pop the 1.0 */
3730 x86_jump8 (code, 0);
3732 x86_fp_op (code, X86_FADD, 0);
3736 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3738 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3741 x86_patch (pop_jump, code);
3742 x86_fstp (code, 0); /* pop the 1.0 */
3743 x86_patch (check_pos, code);
3744 x86_patch (end_tan, code);
3746 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3747 x86_pop_reg (code, X86_EAX);
3754 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3763 g_assert (cfg->opt & MONO_OPT_CMOV);
3764 g_assert (ins->dreg == ins->sreg1);
3765 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3766 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3769 g_assert (cfg->opt & MONO_OPT_CMOV);
3770 g_assert (ins->dreg == ins->sreg1);
3771 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3772 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3775 g_assert (cfg->opt & MONO_OPT_CMOV);
3776 g_assert (ins->dreg == ins->sreg1);
3777 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3778 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3781 g_assert (cfg->opt & MONO_OPT_CMOV);
3782 g_assert (ins->dreg == ins->sreg1);
3783 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3784 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3790 x86_fxch (code, ins->inst_imm);
3795 x86_push_reg (code, X86_EAX);
3796 /* we need to exchange ST(0) with ST(1) */
3799 /* this requires a loop, because fprem somtimes
3800 * returns a partial remainder */
3802 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3803 /* x86_fprem1 (code); */
3806 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3808 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3814 x86_pop_reg (code, X86_EAX);
3818 if (cfg->opt & MONO_OPT_FCMOV) {
3819 x86_fcomip (code, 1);
3823 /* this overwrites EAX */
3824 EMIT_FPCOMPARE(code);
3825 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3829 if (cfg->opt & MONO_OPT_FCMOV) {
3830 /* zeroing the register at the start results in
3831 * shorter and faster code (we can also remove the widening op)
3833 guchar *unordered_check;
3834 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3835 x86_fcomip (code, 1);
3837 unordered_check = code;
3838 x86_branch8 (code, X86_CC_P, 0, FALSE);
3839 if (ins->opcode == OP_FCEQ) {
3840 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3841 x86_patch (unordered_check, code);
3843 guchar *jump_to_end;
3844 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3846 x86_jump8 (code, 0);
3847 x86_patch (unordered_check, code);
3848 x86_inc_reg (code, ins->dreg);
3849 x86_patch (jump_to_end, code);
3854 if (ins->dreg != X86_EAX)
3855 x86_push_reg (code, X86_EAX);
3857 EMIT_FPCOMPARE(code);
3858 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3859 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3860 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3861 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3863 if (ins->dreg != X86_EAX)
3864 x86_pop_reg (code, X86_EAX);
3868 if (cfg->opt & MONO_OPT_FCMOV) {
3869 /* zeroing the register at the start results in
3870 * shorter and faster code (we can also remove the widening op)
3872 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3873 x86_fcomip (code, 1);
3875 if (ins->opcode == OP_FCLT_UN) {
3876 guchar *unordered_check = code;
3877 guchar *jump_to_end;
3878 x86_branch8 (code, X86_CC_P, 0, FALSE);
3879 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3881 x86_jump8 (code, 0);
3882 x86_patch (unordered_check, code);
3883 x86_inc_reg (code, ins->dreg);
3884 x86_patch (jump_to_end, code);
3886 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3890 if (ins->dreg != X86_EAX)
3891 x86_push_reg (code, X86_EAX);
3893 EMIT_FPCOMPARE(code);
3894 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3895 if (ins->opcode == OP_FCLT_UN) {
3896 guchar *is_not_zero_check, *end_jump;
3897 is_not_zero_check = code;
3898 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3900 x86_jump8 (code, 0);
3901 x86_patch (is_not_zero_check, code);
3902 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3904 x86_patch (end_jump, code);
3906 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3907 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3909 if (ins->dreg != X86_EAX)
3910 x86_pop_reg (code, X86_EAX);
3913 guchar *unordered_check;
3914 guchar *jump_to_end;
3915 if (cfg->opt & MONO_OPT_FCMOV) {
3916 /* zeroing the register at the start results in
3917 * shorter and faster code (we can also remove the widening op)
3919 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3920 x86_fcomip (code, 1);
3922 unordered_check = code;
3923 x86_branch8 (code, X86_CC_P, 0, FALSE);
3924 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3925 x86_patch (unordered_check, code);
3928 if (ins->dreg != X86_EAX)
3929 x86_push_reg (code, X86_EAX);
3931 EMIT_FPCOMPARE(code);
3932 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3933 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3934 unordered_check = code;
3935 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3937 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3938 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3939 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3941 x86_jump8 (code, 0);
3942 x86_patch (unordered_check, code);
3943 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3944 x86_patch (jump_to_end, code);
3946 if (ins->dreg != X86_EAX)
3947 x86_pop_reg (code, X86_EAX);
3952 if (cfg->opt & MONO_OPT_FCMOV) {
3953 /* zeroing the register at the start results in
3954 * shorter and faster code (we can also remove the widening op)
3956 guchar *unordered_check;
3957 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3958 x86_fcomip (code, 1);
3960 if (ins->opcode == OP_FCGT) {
3961 unordered_check = code;
3962 x86_branch8 (code, X86_CC_P, 0, FALSE);
3963 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3964 x86_patch (unordered_check, code);
3966 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3970 if (ins->dreg != X86_EAX)
3971 x86_push_reg (code, X86_EAX);
3973 EMIT_FPCOMPARE(code);
3974 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3975 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3976 if (ins->opcode == OP_FCGT_UN) {
3977 guchar *is_not_zero_check, *end_jump;
3978 is_not_zero_check = code;
3979 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3981 x86_jump8 (code, 0);
3982 x86_patch (is_not_zero_check, code);
3983 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3985 x86_patch (end_jump, code);
3987 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3988 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3990 if (ins->dreg != X86_EAX)
3991 x86_pop_reg (code, X86_EAX);
3994 guchar *unordered_check;
3995 guchar *jump_to_end;
3996 if (cfg->opt & MONO_OPT_FCMOV) {
3997 /* zeroing the register at the start results in
3998 * shorter and faster code (we can also remove the widening op)
4000 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4001 x86_fcomip (code, 1);
4003 unordered_check = code;
4004 x86_branch8 (code, X86_CC_P, 0, FALSE);
4005 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4006 x86_patch (unordered_check, code);
4009 if (ins->dreg != X86_EAX)
4010 x86_push_reg (code, X86_EAX);
4012 EMIT_FPCOMPARE(code);
4013 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4014 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4015 unordered_check = code;
4016 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4018 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4019 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4020 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4022 x86_jump8 (code, 0);
4023 x86_patch (unordered_check, code);
4024 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4025 x86_patch (jump_to_end, code);
4027 if (ins->dreg != X86_EAX)
4028 x86_pop_reg (code, X86_EAX);
4032 if (cfg->opt & MONO_OPT_FCMOV) {
4033 guchar *jump = code;
4034 x86_branch8 (code, X86_CC_P, 0, TRUE);
4035 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4036 x86_patch (jump, code);
4039 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4040 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4043 /* Branch if C013 != 100 */
4044 if (cfg->opt & MONO_OPT_FCMOV) {
4045 /* branch if !ZF or (PF|CF) */
4046 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4047 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4048 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4051 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4052 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4055 if (cfg->opt & MONO_OPT_FCMOV) {
4056 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4059 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4062 if (cfg->opt & MONO_OPT_FCMOV) {
4063 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4064 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4067 if (ins->opcode == OP_FBLT_UN) {
4068 guchar *is_not_zero_check, *end_jump;
4069 is_not_zero_check = code;
4070 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4072 x86_jump8 (code, 0);
4073 x86_patch (is_not_zero_check, code);
4074 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4076 x86_patch (end_jump, code);
4078 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4082 if (cfg->opt & MONO_OPT_FCMOV) {
4083 if (ins->opcode == OP_FBGT) {
4086 /* skip branch if C1=1 */
4088 x86_branch8 (code, X86_CC_P, 0, FALSE);
4089 /* branch if (C0 | C3) = 1 */
4090 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4091 x86_patch (br1, code);
4093 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4097 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4098 if (ins->opcode == OP_FBGT_UN) {
4099 guchar *is_not_zero_check, *end_jump;
4100 is_not_zero_check = code;
4101 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4103 x86_jump8 (code, 0);
4104 x86_patch (is_not_zero_check, code);
4105 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4107 x86_patch (end_jump, code);
4109 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4112 /* Branch if C013 == 100 or 001 */
4113 if (cfg->opt & MONO_OPT_FCMOV) {
4116 /* skip branch if C1=1 */
4118 x86_branch8 (code, X86_CC_P, 0, FALSE);
4119 /* branch if (C0 | C3) = 1 */
4120 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4121 x86_patch (br1, code);
4124 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4125 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4126 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4127 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4130 /* Branch if C013 == 000 */
4131 if (cfg->opt & MONO_OPT_FCMOV) {
4132 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4135 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4138 /* Branch if C013=000 or 100 */
4139 if (cfg->opt & MONO_OPT_FCMOV) {
4142 /* skip branch if C1=1 */
4144 x86_branch8 (code, X86_CC_P, 0, FALSE);
4145 /* branch if C0=0 */
4146 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4147 x86_patch (br1, code);
4150 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4151 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4152 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4155 /* Branch if C013 != 001 */
4156 if (cfg->opt & MONO_OPT_FCMOV) {
4157 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4158 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4161 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4162 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4166 x86_push_reg (code, X86_EAX);
4169 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4170 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4171 x86_pop_reg (code, X86_EAX);
4173 /* Have to clean up the fp stack before throwing the exception */
4175 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4178 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
4180 x86_patch (br1, code);
4184 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4187 case OP_TLS_GET_REG: {
4188 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4192 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4195 case OP_TLS_SET_REG: {
4196 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4199 case OP_MEMORY_BARRIER: {
4200 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4201 x86_prefix (code, X86_LOCK_PREFIX);
4202 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4206 case OP_ATOMIC_ADD_I4: {
4207 int dreg = ins->dreg;
4209 g_assert (cfg->has_atomic_add_i4);
4211 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4212 if (ins->sreg2 == dreg) {
4213 if (dreg == X86_EBX) {
4215 if (ins->inst_basereg == X86_EDI)
4219 if (ins->inst_basereg == X86_EBX)
4222 } else if (ins->inst_basereg == dreg) {
4223 if (dreg == X86_EBX) {
4225 if (ins->sreg2 == X86_EDI)
4229 if (ins->sreg2 == X86_EBX)
4234 if (dreg != ins->dreg) {
4235 x86_push_reg (code, dreg);
4238 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4239 x86_prefix (code, X86_LOCK_PREFIX);
4240 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4241 /* dreg contains the old value, add with sreg2 value */
4242 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4244 if (ins->dreg != dreg) {
4245 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4246 x86_pop_reg (code, dreg);
4251 case OP_ATOMIC_EXCHANGE_I4: {
4253 int sreg2 = ins->sreg2;
4254 int breg = ins->inst_basereg;
4256 g_assert (cfg->has_atomic_exchange_i4);
4258 /* cmpxchg uses eax as comperand, need to make sure we can use it
4259 * hack to overcome limits in x86 reg allocator
4260 * (req: dreg == eax and sreg2 != eax and breg != eax)
4262 g_assert (ins->dreg == X86_EAX);
4264 /* We need the EAX reg for the cmpxchg */
4265 if (ins->sreg2 == X86_EAX) {
4266 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4267 x86_push_reg (code, sreg2);
4268 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4271 if (breg == X86_EAX) {
4272 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4273 x86_push_reg (code, breg);
4274 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4277 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4279 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4280 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4281 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4282 x86_patch (br [1], br [0]);
4284 if (breg != ins->inst_basereg)
4285 x86_pop_reg (code, breg);
4287 if (ins->sreg2 != sreg2)
4288 x86_pop_reg (code, sreg2);
4292 case OP_ATOMIC_CAS_I4: {
4293 g_assert (ins->dreg == X86_EAX);
4294 g_assert (ins->sreg3 == X86_EAX);
4295 g_assert (ins->sreg1 != X86_EAX);
4296 g_assert (ins->sreg1 != ins->sreg2);
4298 x86_prefix (code, X86_LOCK_PREFIX);
4299 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4302 case OP_ATOMIC_LOAD_I1: {
4303 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4306 case OP_ATOMIC_LOAD_U1: {
4307 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4310 case OP_ATOMIC_LOAD_I2: {
4311 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4314 case OP_ATOMIC_LOAD_U2: {
4315 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4318 case OP_ATOMIC_LOAD_I4:
4319 case OP_ATOMIC_LOAD_U4: {
4320 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4323 case OP_ATOMIC_LOAD_R4:
4324 case OP_ATOMIC_LOAD_R8: {
4325 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4328 case OP_ATOMIC_STORE_I1:
4329 case OP_ATOMIC_STORE_U1:
4330 case OP_ATOMIC_STORE_I2:
4331 case OP_ATOMIC_STORE_U2:
4332 case OP_ATOMIC_STORE_I4:
4333 case OP_ATOMIC_STORE_U4: {
4336 switch (ins->opcode) {
4337 case OP_ATOMIC_STORE_I1:
4338 case OP_ATOMIC_STORE_U1:
4341 case OP_ATOMIC_STORE_I2:
4342 case OP_ATOMIC_STORE_U2:
4345 case OP_ATOMIC_STORE_I4:
4346 case OP_ATOMIC_STORE_U4:
4351 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4353 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4357 case OP_ATOMIC_STORE_R4:
4358 case OP_ATOMIC_STORE_R8: {
4359 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4361 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4365 case OP_CARD_TABLE_WBARRIER: {
4366 int ptr = ins->sreg1;
4367 int value = ins->sreg2;
4369 int nursery_shift, card_table_shift;
4370 gpointer card_table_mask;
4371 size_t nursery_size;
4372 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4373 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4374 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4377 * We need one register we can clobber, we choose EDX and make sreg1
4378 * fixed EAX to work around limitations in the local register allocator.
4379 * sreg2 might get allocated to EDX, but that is not a problem since
4380 * we use it before clobbering EDX.
4382 g_assert (ins->sreg1 == X86_EAX);
4385 * This is the code we produce:
4388 * edx >>= nursery_shift
4389 * cmp edx, (nursery_start >> nursery_shift)
4392 * edx >>= card_table_shift
4393 * card_table[edx] = 1
4397 if (card_table_nursery_check) {
4398 if (value != X86_EDX)
4399 x86_mov_reg_reg (code, X86_EDX, value, 4);
4400 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4401 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4402 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4404 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4405 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4406 if (card_table_mask)
4407 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4408 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4409 if (card_table_nursery_check)
4410 x86_patch (br, code);
4413 #ifdef MONO_ARCH_SIMD_INTRINSICS
4415 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4418 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4421 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4424 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4427 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4430 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4433 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4434 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4437 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4440 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4443 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4446 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4449 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4452 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4455 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4458 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4461 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4464 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4467 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4470 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4473 case OP_PSHUFLEW_HIGH:
4474 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4475 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4477 case OP_PSHUFLEW_LOW:
4478 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4479 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4482 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4483 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4486 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4487 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4490 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4491 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4495 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4498 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4501 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4504 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4507 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4510 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4513 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4514 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4517 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4520 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4523 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4526 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4529 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4532 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4535 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4538 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4541 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4544 case OP_EXTRACT_MASK:
4545 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4549 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4552 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4555 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4559 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4562 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4565 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4568 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4572 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4575 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4578 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4581 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4585 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4588 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4591 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4595 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4598 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4601 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4605 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4608 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4612 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4615 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4618 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4622 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4625 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4628 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4632 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4635 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4638 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4641 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4645 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4648 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4651 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4654 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4657 case OP_PSUM_ABS_DIFF:
4658 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4661 case OP_UNPACK_LOWB:
4662 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4664 case OP_UNPACK_LOWW:
4665 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4667 case OP_UNPACK_LOWD:
4668 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4670 case OP_UNPACK_LOWQ:
4671 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4673 case OP_UNPACK_LOWPS:
4674 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4676 case OP_UNPACK_LOWPD:
4677 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4680 case OP_UNPACK_HIGHB:
4681 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4683 case OP_UNPACK_HIGHW:
4684 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4686 case OP_UNPACK_HIGHD:
4687 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4689 case OP_UNPACK_HIGHQ:
4690 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4692 case OP_UNPACK_HIGHPS:
4693 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4695 case OP_UNPACK_HIGHPD:
4696 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4700 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4703 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4706 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4709 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4712 case OP_PADDB_SAT_UN:
4713 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4715 case OP_PSUBB_SAT_UN:
4716 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4718 case OP_PADDW_SAT_UN:
4719 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4721 case OP_PSUBW_SAT_UN:
4722 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4726 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4729 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4732 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4735 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4739 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4742 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4745 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4747 case OP_PMULW_HIGH_UN:
4748 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4751 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4755 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4758 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4762 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4765 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4769 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4772 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4776 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4779 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4783 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4786 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4790 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4793 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4797 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4800 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4804 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4807 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4811 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4814 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4818 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4820 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4821 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4825 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4827 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4828 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4832 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4834 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4835 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4839 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4841 case OP_EXTRACTX_U2:
4842 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4844 case OP_INSERTX_U1_SLOW:
4845 /*sreg1 is the extracted ireg (scratch)
4846 /sreg2 is the to be inserted ireg (scratch)
4847 /dreg is the xreg to receive the value*/
4849 /*clear the bits from the extracted word*/
4850 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4851 /*shift the value to insert if needed*/
4852 if (ins->inst_c0 & 1)
4853 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4854 /*join them together*/
4855 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4856 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4858 case OP_INSERTX_I4_SLOW:
4859 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4860 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4861 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4864 case OP_INSERTX_R4_SLOW:
4865 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4866 /*TODO if inst_c0 == 0 use movss*/
4867 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4868 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4870 case OP_INSERTX_R8_SLOW:
4871 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4872 if (cfg->verbose_level)
4873 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4875 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4877 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4880 case OP_STOREX_MEMBASE_REG:
4881 case OP_STOREX_MEMBASE:
4882 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4884 case OP_LOADX_MEMBASE:
4885 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4887 case OP_LOADX_ALIGNED_MEMBASE:
4888 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4890 case OP_STOREX_ALIGNED_MEMBASE_REG:
4891 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4893 case OP_STOREX_NTA_MEMBASE_REG:
4894 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4896 case OP_PREFETCH_MEMBASE:
4897 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4901 /*FIXME the peephole pass should have killed this*/
4902 if (ins->dreg != ins->sreg1)
4903 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4906 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4909 case OP_FCONV_TO_R8_X:
4910 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4911 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4914 case OP_XCONV_R8_TO_I4:
4915 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4916 switch (ins->backend.source_opcode) {
4917 case OP_FCONV_TO_I1:
4918 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4920 case OP_FCONV_TO_U1:
4921 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4923 case OP_FCONV_TO_I2:
4924 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4926 case OP_FCONV_TO_U2:
4927 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4933 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4934 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4935 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4936 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4937 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4938 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4941 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4942 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4943 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4946 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4947 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4950 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4951 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4952 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4955 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4956 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4957 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4961 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4964 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4967 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4970 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4973 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4976 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4979 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4982 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4986 case OP_LIVERANGE_START: {
4987 if (cfg->verbose_level > 1)
4988 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4989 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4992 case OP_LIVERANGE_END: {
4993 if (cfg->verbose_level > 1)
4994 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4995 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4998 case OP_GC_SAFE_POINT: {
4999 const char *polling_func = NULL;
5000 int compare_val = 0;
5003 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
5004 polling_func = "mono_nacl_gc";
5005 compare_val = 0xFFFFFFFF;
5007 g_assert (mono_threads_is_coop_enabled ());
5008 polling_func = "mono_threads_state_poll";
5012 x86_test_membase_imm (code, ins->sreg1, 0, compare_val);
5013 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
5014 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
5015 x86_patch (br [0], code);
5019 case OP_GC_LIVENESS_DEF:
5020 case OP_GC_LIVENESS_USE:
5021 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5022 ins->backend.pc_offset = code - cfg->native_code;
5024 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5025 ins->backend.pc_offset = code - cfg->native_code;
5026 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5029 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
5032 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
5035 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
5036 g_assert_not_reached ();
5039 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
5040 #ifndef __native_client_codegen__
5041 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5042 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5043 g_assert_not_reached ();
5044 #endif /* __native_client_codegen__ */
5050 cfg->code_len = code - cfg->native_code;
5053 #endif /* DISABLE_JIT */
5056 mono_arch_register_lowlevel_calls (void)
5061 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5063 unsigned char *ip = ji->ip.i + code;
5066 case MONO_PATCH_INFO_IP:
5067 *((gconstpointer *)(ip)) = target;
5069 case MONO_PATCH_INFO_ABS:
5070 case MONO_PATCH_INFO_METHOD:
5071 case MONO_PATCH_INFO_METHOD_JUMP:
5072 case MONO_PATCH_INFO_INTERNAL_METHOD:
5073 case MONO_PATCH_INFO_BB:
5074 case MONO_PATCH_INFO_LABEL:
5075 case MONO_PATCH_INFO_RGCTX_FETCH:
5076 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5077 #if defined(__native_client_codegen__) && defined(__native_client__)
5078 if (nacl_is_code_address (code)) {
5079 /* For tail calls, code is patched after being installed */
5080 /* but not through the normal "patch callsite" method. */
5081 unsigned char buf[kNaClAlignment];
5082 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5083 unsigned char *_target = target;
5085 /* All patch targets modified in x86_patch */
5086 /* are IP relative. */
5087 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5088 memcpy (buf, aligned_code, kNaClAlignment);
5089 /* Patch a temp buffer of bundle size, */
5090 /* then install to actual location. */
5091 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5092 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5093 g_assert (ret == 0);
5096 x86_patch (ip, (unsigned char*)target);
5099 x86_patch (ip, (unsigned char*)target);
5102 case MONO_PATCH_INFO_NONE:
5104 case MONO_PATCH_INFO_R4:
5105 case MONO_PATCH_INFO_R8: {
5106 guint32 offset = mono_arch_get_patch_offset (ip);
5107 *((gconstpointer *)(ip + offset)) = target;
5111 guint32 offset = mono_arch_get_patch_offset (ip);
5112 #if !defined(__native_client__)
5113 *((gconstpointer *)(ip + offset)) = target;
5115 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5122 static G_GNUC_UNUSED void
5123 stack_unaligned (MonoMethod *m, gpointer caller)
5125 printf ("%s\n", mono_method_full_name (m, TRUE));
5126 g_assert_not_reached ();
5130 mono_arch_emit_prolog (MonoCompile *cfg)
5132 MonoMethod *method = cfg->method;
5134 MonoMethodSignature *sig;
5138 int alloc_size, pos, max_offset, i, cfa_offset;
5140 gboolean need_stack_frame;
5141 #ifdef __native_client_codegen__
5142 guint alignment_check;
5145 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5147 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5148 cfg->code_size += 512;
5150 #if defined(__default_codegen__)
5151 code = cfg->native_code = g_malloc (cfg->code_size);
5152 #elif defined(__native_client_codegen__)
5153 /* native_code_alloc is not 32-byte aligned, native_code is. */
5154 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5155 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5157 /* Align native_code to next nearest kNaclAlignment byte. */
5158 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5159 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5161 code = cfg->native_code;
5163 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5164 g_assert(alignment_check == 0);
5171 /* Check that the stack is aligned on osx */
5172 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5173 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5174 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5176 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5177 x86_push_membase (code, X86_ESP, 0);
5178 x86_push_imm (code, cfg->method);
5179 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5180 x86_call_reg (code, X86_EAX);
5181 x86_patch (br [0], code);
5185 /* Offset between RSP and the CFA */
5189 cfa_offset = sizeof (gpointer);
5190 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5191 // IP saved at CFA - 4
5192 /* There is no IP reg on x86 */
5193 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5194 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5196 need_stack_frame = needs_stack_frame (cfg);
5198 if (need_stack_frame) {
5199 x86_push_reg (code, X86_EBP);
5200 cfa_offset += sizeof (gpointer);
5201 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5202 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5203 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5204 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5205 /* These are handled automatically by the stack marking code */
5206 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5208 cfg->frame_reg = X86_ESP;
5211 cfg->stack_offset += cfg->param_area;
5212 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5214 alloc_size = cfg->stack_offset;
5217 if (!method->save_lmf) {
5218 if (cfg->used_int_regs & (1 << X86_EBX)) {
5219 x86_push_reg (code, X86_EBX);
5221 cfa_offset += sizeof (gpointer);
5222 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5223 /* These are handled automatically by the stack marking code */
5224 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5227 if (cfg->used_int_regs & (1 << X86_EDI)) {
5228 x86_push_reg (code, X86_EDI);
5230 cfa_offset += sizeof (gpointer);
5231 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5232 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5235 if (cfg->used_int_regs & (1 << X86_ESI)) {
5236 x86_push_reg (code, X86_ESI);
5238 cfa_offset += sizeof (gpointer);
5239 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5240 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5246 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5247 if (mono_do_x86_stack_align && need_stack_frame) {
5248 int tot = alloc_size + pos + 4; /* ret ip */
5249 if (need_stack_frame)
5251 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5253 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5254 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5255 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5259 cfg->arch.sp_fp_offset = alloc_size + pos;
5262 /* See mono_emit_stack_alloc */
5263 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5264 guint32 remaining_size = alloc_size;
5265 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5266 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5267 guint32 offset = code - cfg->native_code;
5268 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5269 while (required_code_size >= (cfg->code_size - offset))
5270 cfg->code_size *= 2;
5271 cfg->native_code = mono_realloc_native_code(cfg);
5272 code = cfg->native_code + offset;
5273 cfg->stat_code_reallocs++;
5275 while (remaining_size >= 0x1000) {
5276 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5277 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5278 remaining_size -= 0x1000;
5281 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5283 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5286 g_assert (need_stack_frame);
5289 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5290 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5291 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5294 #if DEBUG_STACK_ALIGNMENT
5295 /* check the stack is aligned */
5296 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5297 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5298 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5299 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5300 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5301 x86_breakpoint (code);
5305 /* compute max_offset in order to use short forward jumps */
5307 if (cfg->opt & MONO_OPT_BRANCH) {
5308 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5310 bb->max_offset = max_offset;
5312 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5314 /* max alignment for loops */
5315 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5316 max_offset += LOOP_ALIGNMENT;
5317 #ifdef __native_client_codegen__
5318 /* max alignment for native client */
5319 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5320 max_offset += kNaClAlignment;
5322 MONO_BB_FOR_EACH_INS (bb, ins) {
5323 if (ins->opcode == OP_LABEL)
5324 ins->inst_c1 = max_offset;
5325 #ifdef __native_client_codegen__
5326 switch (ins->opcode)
5338 case OP_VOIDCALL_REG:
5340 case OP_FCALL_MEMBASE:
5341 case OP_LCALL_MEMBASE:
5342 case OP_VCALL_MEMBASE:
5343 case OP_VCALL2_MEMBASE:
5344 case OP_VOIDCALL_MEMBASE:
5345 case OP_CALL_MEMBASE:
5346 max_offset += kNaClAlignment;
5349 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5352 #endif /* __native_client_codegen__ */
5353 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5358 /* store runtime generic context */
5359 if (cfg->rgctx_var) {
5360 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5362 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5365 if (method->save_lmf)
5366 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5368 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5369 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5374 if (cfg->arch.ss_tramp_var) {
5375 /* Initialize ss_tramp_var */
5376 ins = cfg->arch.ss_tramp_var;
5377 g_assert (ins->opcode == OP_REGOFFSET);
5379 g_assert (!cfg->compile_aot);
5380 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&ss_trampoline, 4);
5383 if (cfg->arch.bp_tramp_var) {
5384 /* Initialize bp_tramp_var */
5385 ins = cfg->arch.bp_tramp_var;
5386 g_assert (ins->opcode == OP_REGOFFSET);
5388 g_assert (!cfg->compile_aot);
5389 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&bp_trampoline, 4);
5393 /* load arguments allocated to register from the stack */
5394 sig = mono_method_signature (method);
5397 cinfo = (CallInfo *)cfg->arch.cinfo;
5399 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5400 inst = cfg->args [pos];
5401 ainfo = &cinfo->args [pos];
5402 if (inst->opcode == OP_REGVAR) {
5403 g_assert (need_stack_frame);
5404 x86_mov_reg_membase (code, inst->dreg, X86_EBP, ainfo->offset + ARGS_OFFSET, 4);
5405 if (cfg->verbose_level > 2)
5406 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5411 cfg->code_len = code - cfg->native_code;
5413 g_assert (cfg->code_len < cfg->code_size);
5419 mono_arch_emit_epilog (MonoCompile *cfg)
5421 MonoMethod *method = cfg->method;
5422 MonoMethodSignature *sig = mono_method_signature (method);
5424 guint32 stack_to_pop;
5426 int max_epilog_size = 16;
5428 gboolean need_stack_frame = needs_stack_frame (cfg);
5430 if (cfg->method->save_lmf)
5431 max_epilog_size += 128;
5433 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5434 cfg->code_size *= 2;
5435 cfg->native_code = mono_realloc_native_code(cfg);
5436 cfg->stat_code_reallocs++;
5439 code = cfg->native_code + cfg->code_len;
5441 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5442 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5444 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5447 if (method->save_lmf) {
5448 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5450 gboolean supported = FALSE;
5452 if (cfg->compile_aot) {
5453 #if defined(MONO_HAVE_FAST_TLS)
5456 } else if (mono_get_jit_tls_offset () != -1) {
5460 /* check if we need to restore protection of the stack after a stack overflow */
5462 if (cfg->compile_aot) {
5463 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5465 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5467 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5470 /* we load the value in a separate instruction: this mechanism may be
5471 * used later as a safer way to do thread interruption
5473 x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5474 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5476 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5477 /* note that the call trampoline will preserve eax/edx */
5478 x86_call_reg (code, X86_ECX);
5479 x86_patch (patch, code);
5481 /* FIXME: maybe save the jit tls in the prolog */
5484 /* restore caller saved regs */
5485 if (cfg->used_int_regs & (1 << X86_EBX)) {
5486 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5489 if (cfg->used_int_regs & (1 << X86_EDI)) {
5490 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5492 if (cfg->used_int_regs & (1 << X86_ESI)) {
5493 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5496 /* EBP is restored by LEAVE */
5498 for (i = 0; i < X86_NREG; ++i) {
5499 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5505 g_assert (need_stack_frame);
5506 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5510 g_assert (need_stack_frame);
5511 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5514 if (cfg->used_int_regs & (1 << X86_ESI)) {
5515 x86_pop_reg (code, X86_ESI);
5517 if (cfg->used_int_regs & (1 << X86_EDI)) {
5518 x86_pop_reg (code, X86_EDI);
5520 if (cfg->used_int_regs & (1 << X86_EBX)) {
5521 x86_pop_reg (code, X86_EBX);
5525 /* Load returned vtypes into registers if needed */
5526 cinfo = (CallInfo *)cfg->arch.cinfo;
5527 if (cinfo->ret.storage == ArgValuetypeInReg) {
5528 for (quad = 0; quad < 2; quad ++) {
5529 switch (cinfo->ret.pair_storage [quad]) {
5531 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5533 case ArgOnFloatFpStack:
5534 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5536 case ArgOnDoubleFpStack:
5537 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5542 g_assert_not_reached ();
5547 if (need_stack_frame)
5550 if (CALLCONV_IS_STDCALL (sig)) {
5551 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5553 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
5554 } else if (cinfo->callee_stack_pop)
5555 stack_to_pop = cinfo->callee_stack_pop;
5560 g_assert (need_stack_frame);
5561 x86_ret_imm (code, stack_to_pop);
5566 cfg->code_len = code - cfg->native_code;
5568 g_assert (cfg->code_len < cfg->code_size);
5572 mono_arch_emit_exceptions (MonoCompile *cfg)
5574 MonoJumpInfo *patch_info;
5577 MonoClass *exc_classes [16];
5578 guint8 *exc_throw_start [16], *exc_throw_end [16];
5582 /* Compute needed space */
5583 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5584 if (patch_info->type == MONO_PATCH_INFO_EXC)
5589 * make sure we have enough space for exceptions
5590 * 16 is the size of two push_imm instructions and a call
5592 if (cfg->compile_aot)
5593 code_size = exc_count * 32;
5595 code_size = exc_count * 16;
5597 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5598 cfg->code_size *= 2;
5599 cfg->native_code = mono_realloc_native_code(cfg);
5600 cfg->stat_code_reallocs++;
5603 code = cfg->native_code + cfg->code_len;
5606 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5607 switch (patch_info->type) {
5608 case MONO_PATCH_INFO_EXC: {
5609 MonoClass *exc_class;
5613 x86_patch (patch_info->ip.i + cfg->native_code, code);
5615 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5616 throw_ip = patch_info->ip.i;
5618 /* Find a throw sequence for the same exception class */
5619 for (i = 0; i < nthrows; ++i)
5620 if (exc_classes [i] == exc_class)
5623 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5624 x86_jump_code (code, exc_throw_start [i]);
5625 patch_info->type = MONO_PATCH_INFO_NONE;
5630 /* Compute size of code following the push <OFFSET> */
5631 #if defined(__default_codegen__)
5633 #elif defined(__native_client_codegen__)
5634 code = mono_nacl_align (code);
5635 size = kNaClAlignment;
5637 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5639 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5640 /* Use the shorter form */
5642 x86_push_imm (code, 0);
5646 x86_push_imm (code, 0xf0f0f0f0);
5651 exc_classes [nthrows] = exc_class;
5652 exc_throw_start [nthrows] = code;
5655 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5656 patch_info->data.name = "mono_arch_throw_corlib_exception";
5657 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5658 patch_info->ip.i = code - cfg->native_code;
5659 x86_call_code (code, 0);
5660 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5665 exc_throw_end [nthrows] = code;
5677 cfg->code_len = code - cfg->native_code;
5679 g_assert (cfg->code_len < cfg->code_size);
5683 mono_arch_flush_icache (guint8 *code, gint size)
5689 mono_arch_flush_register_windows (void)
5694 mono_arch_is_inst_imm (gint64 imm)
5700 mono_arch_finish_init (void)
5702 if (!g_getenv ("MONO_NO_TLS")) {
5703 #ifndef TARGET_WIN32
5705 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5712 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5716 // Linear handler, the bsearch head compare is shorter
5717 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5718 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5719 // x86_patch(ins,target)
5720 //[1 + 5] x86_jump_mem(inst,mem)
5723 #if defined(__default_codegen__)
5724 #define BR_SMALL_SIZE 2
5725 #define BR_LARGE_SIZE 5
5726 #elif defined(__native_client_codegen__)
5727 /* I suspect the size calculation below is actually incorrect. */
5728 /* TODO: fix the calculation that uses these sizes. */
5729 #define BR_SMALL_SIZE 16
5730 #define BR_LARGE_SIZE 12
5731 #endif /*__native_client_codegen__*/
5732 #define JUMP_IMM_SIZE 6
5733 #define ENABLE_WRONG_METHOD_CHECK 0
5737 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5739 int i, distance = 0;
5740 for (i = start; i < target; ++i)
5741 distance += imt_entries [i]->chunk_size;
5746 * LOCKING: called with the domain lock held
5749 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5750 gpointer fail_tramp)
5754 guint8 *code, *start;
5757 for (i = 0; i < count; ++i) {
5758 MonoIMTCheckItem *item = imt_entries [i];
5759 if (item->is_equals) {
5760 if (item->check_target_idx) {
5761 if (!item->compare_done)
5762 item->chunk_size += CMP_SIZE;
5763 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5766 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5768 item->chunk_size += JUMP_IMM_SIZE;
5769 #if ENABLE_WRONG_METHOD_CHECK
5770 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5775 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5776 imt_entries [item->check_target_idx]->compare_done = TRUE;
5778 size += item->chunk_size;
5780 #if defined(__native_client__) && defined(__native_client_codegen__)
5781 /* In Native Client, we don't re-use thunks, allocate from the */
5782 /* normal code manager paths. */
5783 size = NACL_BUNDLE_ALIGN_UP (size);
5784 code = mono_domain_code_reserve (domain, size);
5787 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5789 code = mono_domain_code_reserve (domain, size);
5793 unwind_ops = mono_arch_get_cie_program ();
5795 for (i = 0; i < count; ++i) {
5796 MonoIMTCheckItem *item = imt_entries [i];
5797 item->code_target = code;
5798 if (item->is_equals) {
5799 if (item->check_target_idx) {
5800 if (!item->compare_done)
5801 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5802 item->jmp_code = code;
5803 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5804 if (item->has_target_code)
5805 x86_jump_code (code, item->value.target_code);
5807 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5810 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5811 item->jmp_code = code;
5812 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5813 if (item->has_target_code)
5814 x86_jump_code (code, item->value.target_code);
5816 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5817 x86_patch (item->jmp_code, code);
5818 x86_jump_code (code, fail_tramp);
5819 item->jmp_code = NULL;
5821 /* enable the commented code to assert on wrong method */
5822 #if ENABLE_WRONG_METHOD_CHECK
5823 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5824 item->jmp_code = code;
5825 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5827 if (item->has_target_code)
5828 x86_jump_code (code, item->value.target_code);
5830 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5831 #if ENABLE_WRONG_METHOD_CHECK
5832 x86_patch (item->jmp_code, code);
5833 x86_breakpoint (code);
5834 item->jmp_code = NULL;
5839 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5840 item->jmp_code = code;
5841 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5842 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5844 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5847 /* patch the branches to get to the target items */
5848 for (i = 0; i < count; ++i) {
5849 MonoIMTCheckItem *item = imt_entries [i];
5850 if (item->jmp_code) {
5851 if (item->check_target_idx) {
5852 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5858 mono_stats.imt_thunks_size += code - start;
5859 g_assert (code - start <= size);
5863 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5864 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5868 if (mono_jit_map_is_enabled ()) {
5871 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5873 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5874 mono_emit_jit_tramp (start, code - start, buff);
5878 nacl_domain_code_validate (domain, &start, size, &code);
5879 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
5881 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
5887 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5889 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5893 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5895 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5899 mono_arch_get_cie_program (void)
5903 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5904 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5910 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5912 MonoInst *ins = NULL;
5915 if (cmethod->klass == mono_defaults.math_class) {
5916 if (strcmp (cmethod->name, "Sin") == 0) {
5918 } else if (strcmp (cmethod->name, "Cos") == 0) {
5920 } else if (strcmp (cmethod->name, "Tan") == 0) {
5922 } else if (strcmp (cmethod->name, "Atan") == 0) {
5924 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5926 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5928 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5932 if (opcode && fsig->param_count == 1) {
5933 MONO_INST_NEW (cfg, ins, opcode);
5934 ins->type = STACK_R8;
5935 ins->dreg = mono_alloc_freg (cfg);
5936 ins->sreg1 = args [0]->dreg;
5937 MONO_ADD_INS (cfg->cbb, ins);
5940 if (cfg->opt & MONO_OPT_CMOV) {
5943 if (strcmp (cmethod->name, "Min") == 0) {
5944 if (fsig->params [0]->type == MONO_TYPE_I4)
5946 } else if (strcmp (cmethod->name, "Max") == 0) {
5947 if (fsig->params [0]->type == MONO_TYPE_I4)
5951 if (opcode && fsig->param_count == 2) {
5952 MONO_INST_NEW (cfg, ins, opcode);
5953 ins->type = STACK_I4;
5954 ins->dreg = mono_alloc_ireg (cfg);
5955 ins->sreg1 = args [0]->dreg;
5956 ins->sreg2 = args [1]->dreg;
5957 MONO_ADD_INS (cfg->cbb, ins);
5962 /* OP_FREM is not IEEE compatible */
5963 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
5964 MONO_INST_NEW (cfg, ins, OP_FREM);
5965 ins->inst_i0 = args [0];
5966 ins->inst_i1 = args [1];
5975 mono_arch_print_tree (MonoInst *tree, int arity)
5981 mono_arch_get_patch_offset (guint8 *code)
5983 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5985 else if (code [0] == 0xba)
5987 else if (code [0] == 0x68)
5990 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5991 /* push <OFFSET>(<REG>) */
5993 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5994 /* call *<OFFSET>(<REG>) */
5996 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5999 else if ((code [0] == 0x58) && (code [1] == 0x05))
6000 /* pop %eax; add <OFFSET>, %eax */
6002 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6003 /* pop <REG>; add <OFFSET>, <REG> */
6005 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6006 /* mov <REG>, imm */
6009 g_assert_not_reached ();
6015 * mono_breakpoint_clean_code:
6017 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6018 * breakpoints in the original code, they are removed in the copy.
6020 * Returns TRUE if no sw breakpoint was present.
6023 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6026 * If method_start is non-NULL we need to perform bound checks, since we access memory
6027 * at code - offset we could go before the start of the method and end up in a different
6028 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6031 if (!method_start || code - offset >= method_start) {
6032 memcpy (buf, code - offset, size);
6034 int diff = code - method_start;
6035 memset (buf, 0, size);
6036 memcpy (buf + offset - diff, method_start, diff + size - offset);
6042 * mono_x86_get_this_arg_offset:
6044 * Return the offset of the stack location where this is passed during a virtual
6048 mono_x86_get_this_arg_offset (MonoMethodSignature *sig)
6054 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6056 guint32 esp = regs [X86_ESP];
6063 * The stack looks like:
6067 res = ((MonoObject**)esp) [0];
6071 #define MAX_ARCH_DELEGATE_PARAMS 10
6074 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
6076 guint8 *code, *start;
6077 int code_reserve = 64;
6080 unwind_ops = mono_arch_get_cie_program ();
6083 * The stack contains:
6089 start = code = mono_global_codeman_reserve (code_reserve);
6091 /* Replace the this argument with the target */
6092 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6093 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6094 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6095 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6097 g_assert ((code - start) < code_reserve);
6100 /* 8 for mov_reg and jump, plus 8 for each parameter */
6101 #ifdef __native_client_codegen__
6102 /* TODO: calculate this size correctly */
6103 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6105 code_reserve = 8 + (param_count * 8);
6106 #endif /* __native_client_codegen__ */
6108 * The stack contains:
6109 * <args in reverse order>
6114 * <args in reverse order>
6117 * without unbalancing the stack.
6118 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6119 * and leaving original spot of first arg as placeholder in stack so
6120 * when callee pops stack everything works.
6123 start = code = mono_global_codeman_reserve (code_reserve);
6125 /* store delegate for access to method_ptr */
6126 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6129 for (i = 0; i < param_count; ++i) {
6130 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6131 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6134 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6136 g_assert ((code - start) < code_reserve);
6139 nacl_global_codeman_validate (&start, code_reserve, &code);
6142 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
6144 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
6145 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
6149 if (mono_jit_map_is_enabled ()) {
6152 buff = (char*)"delegate_invoke_has_target";
6154 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6155 mono_emit_jit_tramp (start, code - start, buff);
6159 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6164 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
6167 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
6169 guint8 *code, *start;
6174 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
6178 * The stack contains:
6182 start = code = mono_global_codeman_reserve (size);
6184 unwind_ops = mono_arch_get_cie_program ();
6186 /* Replace the this argument with the target */
6187 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6188 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6189 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6192 /* Load the IMT reg */
6193 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
6196 /* Load the vtable */
6197 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
6198 x86_jump_membase (code, X86_EAX, offset);
6199 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6202 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
6204 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
6205 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
6206 g_free (tramp_name);
6213 mono_arch_get_delegate_invoke_impls (void)
6216 MonoTrampInfo *info;
6219 get_delegate_invoke_impl (&info, TRUE, 0);
6220 res = g_slist_prepend (res, info);
6222 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
6223 get_delegate_invoke_impl (&info, FALSE, i);
6224 res = g_slist_prepend (res, info);
6227 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
6228 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
6229 res = g_slist_prepend (res, info);
6231 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
6232 res = g_slist_prepend (res, info);
6239 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6241 guint8 *code, *start;
6243 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6246 /* FIXME: Support more cases */
6247 if (MONO_TYPE_ISSTRUCT (sig->ret))
6251 * The stack contains:
6257 static guint8* cached = NULL;
6261 if (mono_aot_only) {
6262 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6264 MonoTrampInfo *info;
6265 start = get_delegate_invoke_impl (&info, TRUE, 0);
6266 mono_tramp_info_register (info, NULL);
6269 mono_memory_barrier ();
6273 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6276 for (i = 0; i < sig->param_count; ++i)
6277 if (!mono_is_regsize_var (sig->params [i]))
6280 code = cache [sig->param_count];
6284 if (mono_aot_only) {
6285 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6286 start = mono_aot_get_trampoline (name);
6289 MonoTrampInfo *info;
6290 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
6291 mono_tramp_info_register (info, NULL);
6294 mono_memory_barrier ();
6296 cache [sig->param_count] = start;
6303 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
6305 MonoTrampInfo *info;
6308 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
6310 mono_tramp_info_register (info, NULL);
6315 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6318 case X86_EAX: return ctx->eax;
6319 case X86_EBX: return ctx->ebx;
6320 case X86_ECX: return ctx->ecx;
6321 case X86_EDX: return ctx->edx;
6322 case X86_ESP: return ctx->esp;
6323 case X86_EBP: return ctx->ebp;
6324 case X86_ESI: return ctx->esi;
6325 case X86_EDI: return ctx->edi;
6327 g_assert_not_reached ();
6333 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6361 g_assert_not_reached ();
6365 #ifdef MONO_ARCH_SIMD_INTRINSICS
6368 get_float_to_x_spill_area (MonoCompile *cfg)
6370 if (!cfg->fconv_to_r8_x_var) {
6371 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6372 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6374 return cfg->fconv_to_r8_x_var;
6378 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6381 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6384 int dreg, src_opcode;
6386 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6389 switch (src_opcode = ins->opcode) {
6390 case OP_FCONV_TO_I1:
6391 case OP_FCONV_TO_U1:
6392 case OP_FCONV_TO_I2:
6393 case OP_FCONV_TO_U2:
6394 case OP_FCONV_TO_I4:
6401 /* dreg is the IREG and sreg1 is the FREG */
6402 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6403 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6404 fconv->sreg1 = ins->sreg1;
6405 fconv->dreg = mono_alloc_ireg (cfg);
6406 fconv->type = STACK_VTYPE;
6407 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6409 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6413 ins->opcode = OP_XCONV_R8_TO_I4;
6415 ins->klass = mono_defaults.int32_class;
6416 ins->sreg1 = fconv->dreg;
6418 ins->type = STACK_I4;
6419 ins->backend.source_opcode = src_opcode;
6422 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6425 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6430 if (long_ins->opcode == OP_LNEG) {
6432 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
6433 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
6434 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->dreg));
6439 #ifdef MONO_ARCH_SIMD_INTRINSICS
6441 if (!(cfg->opt & MONO_OPT_SIMD))
6444 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6445 switch (long_ins->opcode) {
6447 vreg = long_ins->sreg1;
6449 if (long_ins->inst_c0) {
6450 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6451 ins->klass = long_ins->klass;
6452 ins->sreg1 = long_ins->sreg1;
6454 ins->type = STACK_VTYPE;
6455 ins->dreg = vreg = alloc_ireg (cfg);
6456 MONO_ADD_INS (cfg->cbb, ins);
6459 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6460 ins->klass = mono_defaults.int32_class;
6462 ins->type = STACK_I4;
6463 ins->dreg = MONO_LVREG_LS (long_ins->dreg);
6464 MONO_ADD_INS (cfg->cbb, ins);
6466 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6467 ins->klass = long_ins->klass;
6468 ins->sreg1 = long_ins->sreg1;
6469 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6470 ins->type = STACK_VTYPE;
6471 ins->dreg = vreg = alloc_ireg (cfg);
6472 MONO_ADD_INS (cfg->cbb, ins);
6474 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6475 ins->klass = mono_defaults.int32_class;
6477 ins->type = STACK_I4;
6478 ins->dreg = MONO_LVREG_MS (long_ins->dreg);
6479 MONO_ADD_INS (cfg->cbb, ins);
6481 long_ins->opcode = OP_NOP;
6483 case OP_INSERTX_I8_SLOW:
6484 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6485 ins->dreg = long_ins->dreg;
6486 ins->sreg1 = long_ins->dreg;
6487 ins->sreg2 = MONO_LVREG_LS (long_ins->sreg2);
6488 ins->inst_c0 = long_ins->inst_c0 * 2;
6489 MONO_ADD_INS (cfg->cbb, ins);
6491 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6492 ins->dreg = long_ins->dreg;
6493 ins->sreg1 = long_ins->dreg;
6494 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg2);
6495 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6496 MONO_ADD_INS (cfg->cbb, ins);
6498 long_ins->opcode = OP_NOP;
6501 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6502 ins->dreg = long_ins->dreg;
6503 ins->sreg1 = MONO_LVREG_LS (long_ins->sreg1);
6504 ins->klass = long_ins->klass;
6505 ins->type = STACK_VTYPE;
6506 MONO_ADD_INS (cfg->cbb, ins);
6508 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6509 ins->dreg = long_ins->dreg;
6510 ins->sreg1 = long_ins->dreg;
6511 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg1);
6513 ins->klass = long_ins->klass;
6514 ins->type = STACK_VTYPE;
6515 MONO_ADD_INS (cfg->cbb, ins);
6517 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6518 ins->dreg = long_ins->dreg;
6519 ins->sreg1 = long_ins->dreg;;
6520 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6521 ins->klass = long_ins->klass;
6522 ins->type = STACK_VTYPE;
6523 MONO_ADD_INS (cfg->cbb, ins);
6525 long_ins->opcode = OP_NOP;
6528 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6531 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6533 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6536 gpointer *sp, old_value;
6539 offset = clause->exvar_offset;
6542 bp = MONO_CONTEXT_GET_BP (ctx);
6543 sp = *(gpointer*)(bp + offset);
6546 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6555 * mono_aot_emit_load_got_addr:
6557 * Emit code to load the got address.
6558 * On x86, the result is placed into EBX.
6561 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6563 x86_call_imm (code, 0);
6565 * The patch needs to point to the pop, since the GOT offset needs
6566 * to be added to that address.
6569 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6571 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6572 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6573 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6579 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6582 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6584 g_assert_not_reached ();
6585 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6590 * mono_arch_emit_load_aotconst:
6592 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6593 * TARGET from the mscorlib GOT in full-aot code.
6594 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6598 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
6600 /* Load the mscorlib got address */
6601 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6602 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6603 /* arch_emit_got_access () patches this */
6604 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6609 /* Can't put this into mini-x86.h */
6611 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6614 mono_arch_get_trampolines (gboolean aot)
6616 MonoTrampInfo *info;
6617 GSList *tramps = NULL;
6619 mono_x86_get_signal_exception_trampoline (&info, aot);
6621 tramps = g_slist_append (tramps, info);
6626 /* Soft Debug support */
6627 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6630 * mono_arch_set_breakpoint:
6632 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6633 * The location should contain code emitted by OP_SEQ_POINT.
6636 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6638 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6640 g_assert (code [0] == 0x90);
6641 x86_call_membase (code, X86_ECX, 0);
6645 * mono_arch_clear_breakpoint:
6647 * Clear the breakpoint at IP.
6650 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6652 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6655 for (i = 0; i < 2; ++i)
6660 * mono_arch_start_single_stepping:
6662 * Start single stepping.
6665 mono_arch_start_single_stepping (void)
6667 ss_trampoline = mini_get_single_step_trampoline ();
6671 * mono_arch_stop_single_stepping:
6673 * Stop single stepping.
6676 mono_arch_stop_single_stepping (void)
6678 ss_trampoline = NULL;
6682 * mono_arch_is_single_step_event:
6684 * Return whenever the machine state in SIGCTX corresponds to a single
6688 mono_arch_is_single_step_event (void *info, void *sigctx)
6690 /* We use soft breakpoints */
6695 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6697 /* We use soft breakpoints */
6701 #define BREAKPOINT_SIZE 2
6704 * mono_arch_skip_breakpoint:
6706 * See mini-amd64.c for docs.
6709 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6711 g_assert_not_reached ();
6715 * mono_arch_skip_single_step:
6717 * See mini-amd64.c for docs.
6720 mono_arch_skip_single_step (MonoContext *ctx)
6722 g_assert_not_reached ();
6726 * mono_arch_get_seq_point_info:
6728 * See mini-amd64.c for docs.
6731 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6738 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6740 ext->lmf.previous_lmf = (gsize)prev_lmf;
6741 /* Mark that this is a MonoLMFExt */
6742 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6743 ext->lmf.ebp = (gssize)ext;
6749 mono_arch_opcode_supported (int opcode)
6752 case OP_ATOMIC_ADD_I4:
6753 case OP_ATOMIC_EXCHANGE_I4:
6754 case OP_ATOMIC_CAS_I4:
6755 case OP_ATOMIC_LOAD_I1:
6756 case OP_ATOMIC_LOAD_I2:
6757 case OP_ATOMIC_LOAD_I4:
6758 case OP_ATOMIC_LOAD_U1:
6759 case OP_ATOMIC_LOAD_U2:
6760 case OP_ATOMIC_LOAD_U4:
6761 case OP_ATOMIC_LOAD_R4:
6762 case OP_ATOMIC_LOAD_R8:
6763 case OP_ATOMIC_STORE_I1:
6764 case OP_ATOMIC_STORE_I2:
6765 case OP_ATOMIC_STORE_I4:
6766 case OP_ATOMIC_STORE_U1:
6767 case OP_ATOMIC_STORE_U2:
6768 case OP_ATOMIC_STORE_U4:
6769 case OP_ATOMIC_STORE_R4:
6770 case OP_ATOMIC_STORE_R8:
6778 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
6780 return get_call_info (mp, sig);