2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/abi-details.h>
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/metadata/gc-internal.h>
27 #include <mono/utils/mono-math.h>
28 #include <mono/utils/mono-counters.h>
29 #include <mono/utils/mono-mmap.h>
30 #include <mono/utils/mono-memory-model.h>
31 #include <mono/utils/mono-hwcap-x86.h>
41 static gboolean optimize_for_xen = TRUE;
43 #define optimize_for_xen 0
47 /* This mutex protects architecture specific caches */
48 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
49 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
50 static CRITICAL_SECTION mini_arch_mutex;
52 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
57 /* Under windows, the default pinvoke calling convention is stdcall */
58 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
60 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
63 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
66 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
69 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
71 #ifdef __native_client_codegen__
73 /* Default alignment for Native Client is 32-byte. */
74 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
76 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
77 /* Check that alignment doesn't cross an alignment boundary. */
79 mono_arch_nacl_pad (guint8 *code, int pad)
81 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
83 if (pad == 0) return code;
84 /* assertion: alignment cannot cross a block boundary */
85 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
86 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
87 while (pad >= kMaxPadding) {
88 x86_padding (code, kMaxPadding);
91 if (pad != 0) x86_padding (code, pad);
96 mono_arch_nacl_skip_nops (guint8 *code)
102 #endif /* __native_client_codegen__ */
105 * The code generated for sequence points reads from this location, which is
106 * made read-only when single stepping is enabled.
108 static gpointer ss_trigger_page;
110 /* Enabled breakpoints read from this trigger page */
111 static gpointer bp_trigger_page;
114 mono_arch_regname (int reg)
117 case X86_EAX: return "%eax";
118 case X86_EBX: return "%ebx";
119 case X86_ECX: return "%ecx";
120 case X86_EDX: return "%edx";
121 case X86_ESP: return "%esp";
122 case X86_EBP: return "%ebp";
123 case X86_EDI: return "%edi";
124 case X86_ESI: return "%esi";
130 mono_arch_fregname (int reg)
155 mono_arch_xregname (int reg)
180 mono_x86_patch (unsigned char* code, gpointer target)
182 x86_patch (code, (unsigned char*)target);
193 /* gsharedvt argument passed by addr */
205 /* Only if storage == ArgValuetypeInReg */
206 ArgStorage pair_storage [2];
215 gboolean need_stack_align;
216 guint32 stack_align_amount;
217 gboolean vtype_retaddr;
218 /* The index of the vret arg in the argument list */
221 /* Argument space popped by the callee */
222 int callee_stack_pop;
228 #define FLOAT_PARAM_REGS 0
230 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
232 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
237 switch (sig->call_convention) {
238 case MONO_CALL_THISCALL:
239 return thiscall_param_regs;
245 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
246 #define SMALL_STRUCTS_IN_REGS
247 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
251 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
253 ainfo->offset = *stack_size;
255 if (!param_regs || param_regs [*gr] == X86_NREG) {
256 ainfo->storage = ArgOnStack;
258 (*stack_size) += sizeof (gpointer);
261 ainfo->storage = ArgInIReg;
262 ainfo->reg = param_regs [*gr];
268 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
270 ainfo->offset = *stack_size;
272 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
274 ainfo->storage = ArgOnStack;
275 (*stack_size) += sizeof (gpointer) * 2;
280 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
282 ainfo->offset = *stack_size;
284 if (*gr >= FLOAT_PARAM_REGS) {
285 ainfo->storage = ArgOnStack;
286 (*stack_size) += is_double ? 8 : 4;
287 ainfo->nslots = is_double ? 2 : 1;
290 /* A double register */
292 ainfo->storage = ArgInDoubleSSEReg;
294 ainfo->storage = ArgInFloatSSEReg;
302 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
304 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
309 klass = mono_class_from_mono_type (type);
310 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
312 #ifdef SMALL_STRUCTS_IN_REGS
313 if (sig->pinvoke && is_return) {
314 MonoMarshalType *info;
317 * the exact rules are not very well documented, the code below seems to work with the
318 * code generated by gcc 3.3.3 -mno-cygwin.
320 info = mono_marshal_load_type_info (klass);
323 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
325 /* Special case structs with only a float member */
326 if (info->num_fields == 1) {
327 int ftype = mini_replace_type (info->fields [0].field->type)->type;
328 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
329 ainfo->storage = ArgValuetypeInReg;
330 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
333 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
334 ainfo->storage = ArgValuetypeInReg;
335 ainfo->pair_storage [0] = ArgOnFloatFpStack;
339 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
340 ainfo->storage = ArgValuetypeInReg;
341 ainfo->pair_storage [0] = ArgInIReg;
342 ainfo->pair_regs [0] = return_regs [0];
343 if (info->native_size > 4) {
344 ainfo->pair_storage [1] = ArgInIReg;
345 ainfo->pair_regs [1] = return_regs [1];
352 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
353 g_assert (size <= 4);
354 ainfo->storage = ArgValuetypeInReg;
355 ainfo->reg = param_regs [*gr];
360 ainfo->offset = *stack_size;
361 ainfo->storage = ArgOnStack;
362 *stack_size += ALIGN_TO (size, sizeof (gpointer));
363 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
369 * Obtain information about a call according to the calling convention.
370 * For x86 ELF, see the "System V Application Binary Interface Intel386
371 * Architecture Processor Supplment, Fourth Edition" document for more
373 * For x86 win32, see ???.
376 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
378 guint32 i, gr, fr, pstart;
379 const guint32 *param_regs;
381 int n = sig->hasthis + sig->param_count;
382 guint32 stack_size = 0;
383 gboolean is_pinvoke = sig->pinvoke;
389 param_regs = callconv_param_regs(sig);
393 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
394 switch (ret_type->type) {
395 case MONO_TYPE_BOOLEAN:
406 case MONO_TYPE_FNPTR:
407 case MONO_TYPE_CLASS:
408 case MONO_TYPE_OBJECT:
409 case MONO_TYPE_SZARRAY:
410 case MONO_TYPE_ARRAY:
411 case MONO_TYPE_STRING:
412 cinfo->ret.storage = ArgInIReg;
413 cinfo->ret.reg = X86_EAX;
417 cinfo->ret.storage = ArgInIReg;
418 cinfo->ret.reg = X86_EAX;
419 cinfo->ret.is_pair = TRUE;
422 cinfo->ret.storage = ArgOnFloatFpStack;
425 cinfo->ret.storage = ArgOnDoubleFpStack;
427 case MONO_TYPE_GENERICINST:
428 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
429 cinfo->ret.storage = ArgInIReg;
430 cinfo->ret.reg = X86_EAX;
433 if (mini_is_gsharedvt_type_gsctx (gsctx, ret_type)) {
434 cinfo->ret.storage = ArgOnStack;
435 cinfo->vtype_retaddr = TRUE;
439 case MONO_TYPE_VALUETYPE:
440 case MONO_TYPE_TYPEDBYREF: {
441 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
443 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
444 if (cinfo->ret.storage == ArgOnStack) {
445 cinfo->vtype_retaddr = TRUE;
446 /* The caller passes the address where the value is stored */
452 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ret_type));
453 cinfo->ret.storage = ArgOnStack;
454 cinfo->vtype_retaddr = TRUE;
457 cinfo->ret.storage = ArgNone;
460 g_error ("Can't handle as return value 0x%x", ret_type->type);
466 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
467 * the first argument, allowing 'this' to be always passed in the first arg reg.
468 * Also do this if the first argument is a reference type, since virtual calls
469 * are sometimes made using calli without sig->hasthis set, like in the delegate
472 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
474 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
476 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
479 cinfo->vret_arg_offset = stack_size;
480 add_general (&gr, NULL, &stack_size, &cinfo->ret);
481 cinfo->vret_arg_index = 1;
485 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
487 if (cinfo->vtype_retaddr)
488 add_general (&gr, NULL, &stack_size, &cinfo->ret);
491 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
492 fr = FLOAT_PARAM_REGS;
494 /* Emit the signature cookie just before the implicit arguments */
495 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
498 for (i = pstart; i < sig->param_count; ++i) {
499 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
502 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
503 /* We allways pass the sig cookie on the stack for simplicity */
505 * Prevent implicit arguments + the sig cookie from being passed
508 fr = FLOAT_PARAM_REGS;
510 /* Emit the signature cookie just before the implicit arguments */
511 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
514 if (sig->params [i]->byref) {
515 add_general (&gr, param_regs, &stack_size, ainfo);
518 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
519 switch (ptype->type) {
520 case MONO_TYPE_BOOLEAN:
523 add_general (&gr, param_regs, &stack_size, ainfo);
528 add_general (&gr, param_regs, &stack_size, ainfo);
532 add_general (&gr, param_regs, &stack_size, ainfo);
537 case MONO_TYPE_FNPTR:
538 case MONO_TYPE_CLASS:
539 case MONO_TYPE_OBJECT:
540 case MONO_TYPE_STRING:
541 case MONO_TYPE_SZARRAY:
542 case MONO_TYPE_ARRAY:
543 add_general (&gr, param_regs, &stack_size, ainfo);
545 case MONO_TYPE_GENERICINST:
546 if (!mono_type_generic_inst_is_valuetype (ptype)) {
547 add_general (&gr, param_regs, &stack_size, ainfo);
550 if (mini_is_gsharedvt_type_gsctx (gsctx, ptype)) {
551 /* gsharedvt arguments are passed by ref */
552 add_general (&gr, param_regs, &stack_size, ainfo);
553 g_assert (ainfo->storage == ArgOnStack);
554 ainfo->storage = ArgGSharedVt;
558 case MONO_TYPE_VALUETYPE:
559 case MONO_TYPE_TYPEDBYREF:
560 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
564 add_general_pair (&gr, param_regs, &stack_size, ainfo);
567 add_float (&fr, &stack_size, ainfo, FALSE);
570 add_float (&fr, &stack_size, ainfo, TRUE);
574 /* gsharedvt arguments are passed by ref */
575 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ptype));
576 add_general (&gr, param_regs, &stack_size, ainfo);
577 g_assert (ainfo->storage == ArgOnStack);
578 ainfo->storage = ArgGSharedVt;
581 g_error ("unexpected type 0x%x", ptype->type);
582 g_assert_not_reached ();
586 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
587 fr = FLOAT_PARAM_REGS;
589 /* Emit the signature cookie just before the implicit arguments */
590 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
593 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
594 cinfo->need_stack_align = TRUE;
595 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
596 stack_size += cinfo->stack_align_amount;
599 if (cinfo->vtype_retaddr) {
600 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
601 cinfo->callee_stack_pop = 4;
604 cinfo->stack_usage = stack_size;
605 cinfo->reg_usage = gr;
606 cinfo->freg_usage = fr;
611 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
613 int n = sig->hasthis + sig->param_count;
617 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
619 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
621 return get_call_info_internal (gsctx, cinfo, sig);
625 * mono_arch_get_argument_info:
626 * @csig: a method signature
627 * @param_count: the number of parameters to consider
628 * @arg_info: an array to store the result infos
630 * Gathers information on parameters such as size, alignment and
631 * padding. arg_info should be large enought to hold param_count + 1 entries.
633 * Returns the size of the argument area on the stack.
634 * This should be signal safe, since it is called from
635 * mono_arch_find_jit_info ().
636 * FIXME: The metadata calls might not be signal safe.
639 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
641 int len, k, args_size = 0;
647 /* Avoid g_malloc as it is not signal safe */
648 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
649 cinfo = (CallInfo*)g_newa (guint8*, len);
650 memset (cinfo, 0, len);
652 cinfo = get_call_info_internal (gsctx, cinfo, csig);
654 arg_info [0].offset = offset;
656 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
657 args_size += sizeof (gpointer);
662 args_size += sizeof (gpointer);
666 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
667 /* Emitted after this */
668 args_size += sizeof (gpointer);
672 arg_info [0].size = args_size;
674 for (k = 0; k < param_count; k++) {
675 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
677 /* ignore alignment for now */
680 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
681 arg_info [k].pad = pad;
683 arg_info [k + 1].pad = 0;
684 arg_info [k + 1].size = size;
686 arg_info [k + 1].offset = offset;
689 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
690 /* Emitted after the first arg */
691 args_size += sizeof (gpointer);
696 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
697 align = MONO_ARCH_FRAME_ALIGNMENT;
700 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
701 arg_info [k].pad = pad;
707 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
709 MonoType *callee_ret;
713 if (cfg->compile_aot && !cfg->full_aot)
714 /* OP_TAILCALL doesn't work with AOT */
717 c1 = get_call_info (NULL, NULL, caller_sig);
718 c2 = get_call_info (NULL, NULL, callee_sig);
720 * Tail calls with more callee stack usage than the caller cannot be supported, since
721 * the extra stack space would be left on the stack after the tail call.
723 res = c1->stack_usage >= c2->stack_usage;
724 callee_ret = mini_replace_type (callee_sig->ret);
725 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
726 /* An address on the callee's stack is passed as the first argument */
736 * Initialize the cpu to execute managed code.
739 mono_arch_cpu_init (void)
741 /* spec compliance requires running with double precision */
745 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
746 fpcw &= ~X86_FPCW_PRECC_MASK;
747 fpcw |= X86_FPCW_PREC_DOUBLE;
748 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
749 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
751 _control87 (_PC_53, MCW_PC);
756 * Initialize architecture specific code.
759 mono_arch_init (void)
761 InitializeCriticalSection (&mini_arch_mutex);
763 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
764 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
765 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
767 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
768 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
769 #if defined(ENABLE_GSHAREDVT)
770 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
775 * Cleanup architecture specific code.
778 mono_arch_cleanup (void)
781 mono_vfree (ss_trigger_page, mono_pagesize ());
783 mono_vfree (bp_trigger_page, mono_pagesize ());
784 DeleteCriticalSection (&mini_arch_mutex);
788 * This function returns the optimizations supported on this cpu.
791 mono_arch_cpu_optimizations (guint32 *exclude_mask)
793 #if !defined(__native_client__)
798 if (mono_hwcap_x86_has_cmov) {
799 opts |= MONO_OPT_CMOV;
801 if (mono_hwcap_x86_has_fcmov)
802 opts |= MONO_OPT_FCMOV;
804 *exclude_mask |= MONO_OPT_FCMOV;
806 *exclude_mask |= MONO_OPT_CMOV;
809 if (mono_hwcap_x86_has_sse2)
810 opts |= MONO_OPT_SSE2;
812 *exclude_mask |= MONO_OPT_SSE2;
814 #ifdef MONO_ARCH_SIMD_INTRINSICS
815 /*SIMD intrinsics require at least SSE2.*/
816 if (!mono_hwcap_x86_has_sse2)
817 *exclude_mask |= MONO_OPT_SIMD;
822 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
827 * This function test for all SSE functions supported.
829 * Returns a bitmask corresponding to all supported versions.
833 mono_arch_cpu_enumerate_simd_versions (void)
835 guint32 sse_opts = 0;
837 if (mono_hwcap_x86_has_sse1)
838 sse_opts |= SIMD_VERSION_SSE1;
840 if (mono_hwcap_x86_has_sse2)
841 sse_opts |= SIMD_VERSION_SSE2;
843 if (mono_hwcap_x86_has_sse3)
844 sse_opts |= SIMD_VERSION_SSE3;
846 if (mono_hwcap_x86_has_ssse3)
847 sse_opts |= SIMD_VERSION_SSSE3;
849 if (mono_hwcap_x86_has_sse41)
850 sse_opts |= SIMD_VERSION_SSE41;
852 if (mono_hwcap_x86_has_sse42)
853 sse_opts |= SIMD_VERSION_SSE42;
855 if (mono_hwcap_x86_has_sse4a)
856 sse_opts |= SIMD_VERSION_SSE4a;
862 * Determine whenever the trap whose info is in SIGINFO is caused by
866 mono_arch_is_int_overflow (void *sigctx, void *info)
871 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
873 ip = (guint8*)ctx.eip;
875 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
879 switch (x86_modrm_rm (ip [1])) {
899 g_assert_not_reached ();
911 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
916 for (i = 0; i < cfg->num_varinfo; i++) {
917 MonoInst *ins = cfg->varinfo [i];
918 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
921 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
924 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
925 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
928 /* we dont allocate I1 to registers because there is no simply way to sign extend
929 * 8bit quantities in caller saved registers on x86 */
930 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
931 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
932 g_assert (i == vmv->idx);
933 vars = g_list_prepend (vars, vmv);
937 vars = mono_varlist_sort (cfg, vars, 0);
943 mono_arch_get_global_int_regs (MonoCompile *cfg)
947 /* we can use 3 registers for global allocation */
948 regs = g_list_prepend (regs, (gpointer)X86_EBX);
949 regs = g_list_prepend (regs, (gpointer)X86_ESI);
950 regs = g_list_prepend (regs, (gpointer)X86_EDI);
956 * mono_arch_regalloc_cost:
958 * Return the cost, in number of memory references, of the action of
959 * allocating the variable VMV into a register during global register
963 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
965 MonoInst *ins = cfg->varinfo [vmv->idx];
967 if (cfg->method->save_lmf)
968 /* The register is already saved */
969 return (ins->opcode == OP_ARG) ? 1 : 0;
971 /* push+pop+possible load if it is an argument */
972 return (ins->opcode == OP_ARG) ? 3 : 2;
976 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
978 static int inited = FALSE;
979 static int count = 0;
981 if (cfg->arch.need_stack_frame_inited) {
982 g_assert (cfg->arch.need_stack_frame == flag);
986 cfg->arch.need_stack_frame = flag;
987 cfg->arch.need_stack_frame_inited = TRUE;
993 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
998 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
1002 needs_stack_frame (MonoCompile *cfg)
1004 MonoMethodSignature *sig;
1005 MonoMethodHeader *header;
1006 gboolean result = FALSE;
1008 #if defined(__APPLE__)
1009 /*OSX requires stack frame code to have the correct alignment. */
1013 if (cfg->arch.need_stack_frame_inited)
1014 return cfg->arch.need_stack_frame;
1016 header = cfg->header;
1017 sig = mono_method_signature (cfg->method);
1019 if (cfg->disable_omit_fp)
1021 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1023 else if (cfg->method->save_lmf)
1025 else if (cfg->stack_offset)
1027 else if (cfg->param_area)
1029 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1031 else if (header->num_clauses)
1033 else if (sig->param_count + sig->hasthis)
1035 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1037 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1038 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1041 set_needs_stack_frame (cfg, result);
1043 return cfg->arch.need_stack_frame;
1047 * Set var information according to the calling convention. X86 version.
1048 * The locals var stuff should most likely be split in another method.
1051 mono_arch_allocate_vars (MonoCompile *cfg)
1053 MonoMethodSignature *sig;
1054 MonoMethodHeader *header;
1056 guint32 locals_stack_size, locals_stack_align;
1061 header = cfg->header;
1062 sig = mono_method_signature (cfg->method);
1064 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1066 cfg->frame_reg = X86_EBP;
1069 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1070 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1071 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1074 /* Reserve space to save LMF and caller saved registers */
1076 if (cfg->method->save_lmf) {
1077 /* The LMF var is allocated normally */
1079 if (cfg->used_int_regs & (1 << X86_EBX)) {
1083 if (cfg->used_int_regs & (1 << X86_EDI)) {
1087 if (cfg->used_int_regs & (1 << X86_ESI)) {
1092 switch (cinfo->ret.storage) {
1093 case ArgValuetypeInReg:
1094 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1096 cfg->ret->opcode = OP_REGOFFSET;
1097 cfg->ret->inst_basereg = X86_EBP;
1098 cfg->ret->inst_offset = - offset;
1104 /* Allocate locals */
1105 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1106 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1107 char *mname = mono_method_full_name (cfg->method, TRUE);
1108 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1109 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1113 if (locals_stack_align) {
1114 int prev_offset = offset;
1116 offset += (locals_stack_align - 1);
1117 offset &= ~(locals_stack_align - 1);
1119 while (prev_offset < offset) {
1121 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1124 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1125 cfg->locals_max_stack_offset = - offset;
1127 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1128 * have locals larger than 8 bytes we need to make sure that
1129 * they have the appropriate offset.
1131 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1132 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1133 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1134 if (offsets [i] != -1) {
1135 MonoInst *inst = cfg->varinfo [i];
1136 inst->opcode = OP_REGOFFSET;
1137 inst->inst_basereg = X86_EBP;
1138 inst->inst_offset = - (offset + offsets [i]);
1139 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1142 offset += locals_stack_size;
1146 * Allocate arguments+return value
1149 switch (cinfo->ret.storage) {
1151 if (cfg->vret_addr) {
1153 * In the new IR, the cfg->vret_addr variable represents the
1154 * vtype return value.
1156 cfg->vret_addr->opcode = OP_REGOFFSET;
1157 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1158 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1159 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1160 printf ("vret_addr =");
1161 mono_print_ins (cfg->vret_addr);
1164 cfg->ret->opcode = OP_REGOFFSET;
1165 cfg->ret->inst_basereg = X86_EBP;
1166 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1169 case ArgValuetypeInReg:
1172 cfg->ret->opcode = OP_REGVAR;
1173 cfg->ret->inst_c0 = cinfo->ret.reg;
1174 cfg->ret->dreg = cinfo->ret.reg;
1177 case ArgOnFloatFpStack:
1178 case ArgOnDoubleFpStack:
1181 g_assert_not_reached ();
1184 if (sig->call_convention == MONO_CALL_VARARG) {
1185 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1186 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1189 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1190 ArgInfo *ainfo = &cinfo->args [i];
1191 inst = cfg->args [i];
1192 if (inst->opcode != OP_REGVAR) {
1193 inst->opcode = OP_REGOFFSET;
1194 inst->inst_basereg = X86_EBP;
1196 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1199 cfg->stack_offset = offset;
1203 mono_arch_create_vars (MonoCompile *cfg)
1206 MonoMethodSignature *sig;
1209 sig = mono_method_signature (cfg->method);
1211 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1212 sig_ret = mini_replace_type (sig->ret);
1214 if (cinfo->ret.storage == ArgValuetypeInReg)
1215 cfg->ret_var_is_local = TRUE;
1216 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (cfg, sig_ret))) {
1217 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1220 #ifdef MONO_X86_NO_PUSHES
1221 cfg->arch.no_pushes = TRUE;
1224 if (cfg->method->save_lmf) {
1225 cfg->create_lmf_var = TRUE;
1228 cfg->lmf_ir_mono_lmf = TRUE;
1232 cfg->arch_eh_jit_info = 1;
1236 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1237 * so we try to do it just once when we have multiple fp arguments in a row.
1238 * We don't use this mechanism generally because for int arguments the generated code
1239 * is slightly bigger and new generation cpus optimize away the dependency chains
1240 * created by push instructions on the esp value.
1241 * fp_arg_setup is the first argument in the execution sequence where the esp register
1244 static G_GNUC_UNUSED int
1245 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1250 for (; start_arg < sig->param_count; ++start_arg) {
1251 t = mini_replace_type (sig->params [start_arg]);
1252 if (!t->byref && t->type == MONO_TYPE_R8) {
1253 fp_space += sizeof (double);
1254 *fp_arg_setup = start_arg;
1263 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1265 MonoMethodSignature *tmp_sig;
1269 * mono_ArgIterator_Setup assumes the signature cookie is
1270 * passed first and all the arguments which were before it are
1271 * passed on the stack after the signature. So compensate by
1272 * passing a different signature.
1274 tmp_sig = mono_metadata_signature_dup (call->signature);
1275 tmp_sig->param_count -= call->signature->sentinelpos;
1276 tmp_sig->sentinelpos = 0;
1277 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1279 if (cfg->compile_aot) {
1280 sig_reg = mono_alloc_ireg (cfg);
1281 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1282 if (cfg->arch.no_pushes) {
1283 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1285 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, sig_reg);
1288 if (cfg->arch.no_pushes) {
1289 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1291 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1298 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1303 LLVMCallInfo *linfo;
1304 MonoType *t, *sig_ret;
1306 n = sig->param_count + sig->hasthis;
1308 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1311 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1314 * LLVM always uses the native ABI while we use our own ABI, the
1315 * only difference is the handling of vtypes:
1316 * - we only pass/receive them in registers in some cases, and only
1317 * in 1 or 2 integer registers.
1319 if (cinfo->ret.storage == ArgValuetypeInReg) {
1321 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1322 cfg->disable_llvm = TRUE;
1326 cfg->exception_message = g_strdup ("vtype ret in call");
1327 cfg->disable_llvm = TRUE;
1329 linfo->ret.storage = LLVMArgVtypeInReg;
1330 for (j = 0; j < 2; ++j)
1331 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1335 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage == ArgInIReg) {
1336 /* Vtype returned using a hidden argument */
1337 linfo->ret.storage = LLVMArgVtypeRetAddr;
1338 linfo->vret_arg_index = cinfo->vret_arg_index;
1341 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage != ArgInIReg) {
1343 cfg->exception_message = g_strdup ("vtype ret in call");
1344 cfg->disable_llvm = TRUE;
1347 for (i = 0; i < n; ++i) {
1348 ainfo = cinfo->args + i;
1350 if (i >= sig->hasthis)
1351 t = sig->params [i - sig->hasthis];
1353 t = &mono_defaults.int_class->byval_arg;
1355 linfo->args [i].storage = LLVMArgNone;
1357 switch (ainfo->storage) {
1359 linfo->args [i].storage = LLVMArgInIReg;
1361 case ArgInDoubleSSEReg:
1362 case ArgInFloatSSEReg:
1363 linfo->args [i].storage = LLVMArgInFPReg;
1366 if (mini_type_is_vtype (cfg, t)) {
1367 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1368 /* LLVM seems to allocate argument space for empty structures too */
1369 linfo->args [i].storage = LLVMArgNone;
1371 linfo->args [i].storage = LLVMArgVtypeByVal;
1373 linfo->args [i].storage = LLVMArgInIReg;
1375 if (t->type == MONO_TYPE_R4)
1376 linfo->args [i].storage = LLVMArgInFPReg;
1377 else if (t->type == MONO_TYPE_R8)
1378 linfo->args [i].storage = LLVMArgInFPReg;
1382 case ArgValuetypeInReg:
1384 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1385 cfg->disable_llvm = TRUE;
1389 cfg->exception_message = g_strdup ("vtype arg");
1390 cfg->disable_llvm = TRUE;
1392 linfo->args [i].storage = LLVMArgVtypeInReg;
1393 for (j = 0; j < 2; ++j)
1394 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1398 linfo->args [i].storage = LLVMArgGSharedVt;
1401 cfg->exception_message = g_strdup ("ainfo->storage");
1402 cfg->disable_llvm = TRUE;
1412 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1414 if (cfg->compute_gc_maps) {
1417 /* Needs checking if the feature will be enabled again */
1418 g_assert (!cfg->arch.no_pushes);
1420 /* On x86, the offsets are from the sp value before the start of the call sequence */
1422 t = &mono_defaults.int_class->byval_arg;
1423 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1428 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1432 MonoMethodSignature *sig;
1435 int sentinelpos = 0, sp_offset = 0;
1437 sig = call->signature;
1438 n = sig->param_count + sig->hasthis;
1439 sig_ret = mini_replace_type (sig->ret);
1441 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1442 call->call_info = cinfo;
1444 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1445 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1447 if (cinfo->need_stack_align && !cfg->arch.no_pushes) {
1448 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1449 arg->dreg = X86_ESP;
1450 arg->sreg1 = X86_ESP;
1451 arg->inst_imm = cinfo->stack_align_amount;
1452 MONO_ADD_INS (cfg->cbb, arg);
1453 for (i = 0; i < cinfo->stack_align_amount; i += sizeof (mgreg_t)) {
1456 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1460 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1461 if (cinfo->ret.storage == ArgValuetypeInReg) {
1463 * Tell the JIT to use a more efficient calling convention: call using
1464 * OP_CALL, compute the result location after the call, and save the
1467 call->vret_in_reg = TRUE;
1469 NULLIFY_INS (call->vret_var);
1473 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1475 /* Handle the case where there are no implicit arguments */
1476 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1477 emit_sig_cookie (cfg, call, cinfo);
1478 sp_offset = (cfg->arch.no_pushes) ? cinfo->sig_cookie.offset : (sp_offset + 4);
1479 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1482 /* Arguments are pushed in the reverse order */
1483 for (i = n - 1; i >= 0; i --) {
1484 ArgInfo *ainfo = cinfo->args + i;
1485 MonoType *orig_type, *t;
1488 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1490 /* Push the vret arg before the first argument */
1491 if (cfg->arch.no_pushes) {
1492 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1493 vtarg->type = STACK_MP;
1494 vtarg->inst_destbasereg = X86_ESP;
1495 vtarg->sreg1 = call->vret_var->dreg;
1496 vtarg->inst_offset = cinfo->ret.offset;
1497 MONO_ADD_INS (cfg->cbb, vtarg);
1498 sp_offset = cinfo->ret.offset;
1500 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1501 vtarg->type = STACK_MP;
1502 vtarg->sreg1 = call->vret_var->dreg;
1503 MONO_ADD_INS (cfg->cbb, vtarg);
1506 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1509 if (i >= sig->hasthis)
1510 t = sig->params [i - sig->hasthis];
1512 t = &mono_defaults.int_class->byval_arg;
1514 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1516 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1518 in = call->args [i];
1519 arg->cil_code = in->cil_code;
1520 arg->sreg1 = in->dreg;
1521 arg->type = in->type;
1523 g_assert (in->dreg != -1);
1525 if (ainfo->storage == ArgGSharedVt) {
1526 arg->opcode = OP_OUTARG_VT;
1527 arg->sreg1 = in->dreg;
1528 arg->klass = in->klass;
1529 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1530 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1532 MONO_ADD_INS (cfg->cbb, arg);
1533 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1537 g_assert (in->klass);
1539 if (t->type == MONO_TYPE_TYPEDBYREF) {
1540 size = sizeof (MonoTypedRef);
1541 align = sizeof (gpointer);
1544 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1548 arg->opcode = OP_OUTARG_VT;
1549 arg->sreg1 = in->dreg;
1550 arg->klass = in->klass;
1551 arg->backend.size = size;
1552 arg->inst_p0 = call;
1553 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1554 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1556 MONO_ADD_INS (cfg->cbb, arg);
1557 if (ainfo->storage != ArgValuetypeInReg) {
1558 sp_offset = (cfg->arch.no_pushes) ? ainfo->offset : (sp_offset + size);
1559 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1563 switch (ainfo->storage) {
1566 if (t->type == MONO_TYPE_R4) {
1567 if (cfg->arch.no_pushes) {
1568 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1570 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1571 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, 0, in->dreg);
1574 } else if (t->type == MONO_TYPE_R8) {
1575 if (cfg->arch.no_pushes) {
1576 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1578 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1579 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, 0, in->dreg);
1582 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1583 if (cfg->arch.no_pushes) {
1584 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, in->dreg + 2);
1585 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg + 1);
1587 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1588 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 1);
1593 if (cfg->arch.no_pushes) {
1594 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1596 arg->opcode = OP_X86_PUSH;
1597 MONO_ADD_INS (cfg->cbb, arg);
1602 if (cfg->arch.no_pushes) {
1603 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1605 arg->opcode = OP_X86_PUSH;
1606 MONO_ADD_INS (cfg->cbb, arg);
1612 arg->opcode = OP_MOVE;
1613 arg->dreg = ainfo->reg;
1614 MONO_ADD_INS (cfg->cbb, arg);
1618 g_assert_not_reached ();
1621 sp_offset = (cfg->arch.no_pushes) ? ainfo->offset : (sp_offset + argsize);
1623 if (cfg->compute_gc_maps) {
1625 /* FIXME: The == STACK_OBJ check might be fragile ? */
1626 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1628 if (call->need_unbox_trampoline)
1629 /* The unbox trampoline transforms this into a managed pointer */
1630 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.int_class->this_arg);
1632 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.object_class->byval_arg);
1634 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1638 for (j = 0; j < argsize; j += 4) {
1639 if (cfg->arch.no_pushes)
1640 emit_gc_param_slot_def (cfg, sp_offset + j, NULL);
1642 emit_gc_param_slot_def (cfg, sp_offset - j, NULL);
1648 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1649 /* Emit the signature cookie just before the implicit arguments */
1650 emit_sig_cookie (cfg, call, cinfo);
1651 sp_offset = (cfg->arch.no_pushes) ? cinfo->sig_cookie.offset : (sp_offset + 4);
1652 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1656 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1659 if (cinfo->ret.storage == ArgValuetypeInReg) {
1662 else if (cinfo->ret.storage == ArgInIReg) {
1664 /* The return address is passed in a register */
1665 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1666 vtarg->sreg1 = call->inst.dreg;
1667 vtarg->dreg = mono_alloc_ireg (cfg);
1668 MONO_ADD_INS (cfg->cbb, vtarg);
1670 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1671 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1672 if (cfg->arch.no_pushes) {
1673 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1674 sp_offset = cinfo->ret.offset;
1677 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1678 vtarg->type = STACK_MP;
1679 vtarg->sreg1 = call->vret_var->dreg;
1680 MONO_ADD_INS (cfg->cbb, vtarg);
1683 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1686 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1687 if (!cfg->arch.no_pushes)
1688 cinfo->stack_usage -= cinfo->callee_stack_pop;
1691 call->stack_usage = cinfo->stack_usage;
1692 call->stack_align_amount = cinfo->stack_align_amount;
1693 if (!cfg->arch.no_pushes)
1694 cfg->arch.param_area_size = MAX (cfg->arch.param_area_size, sp_offset);
1698 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1700 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1701 ArgInfo *ainfo = ins->inst_p1;
1703 int size = ins->backend.size;
1705 if (ainfo->storage == ArgValuetypeInReg) {
1706 int dreg = mono_alloc_ireg (cfg);
1709 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1712 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1715 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1719 g_assert_not_reached ();
1721 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1724 if (cfg->gsharedvt && mini_is_gsharedvt_klass (cfg, ins->klass)) {
1726 if (cfg->arch.no_pushes) {
1727 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1729 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1730 arg->sreg1 = src->dreg;
1731 MONO_ADD_INS (cfg->cbb, arg);
1733 } else if (size <= 4) {
1734 if (cfg->arch.no_pushes) {
1735 int dreg = mono_alloc_ireg (cfg);
1736 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1737 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1739 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1740 arg->sreg1 = src->dreg;
1741 MONO_ADD_INS (cfg->cbb, arg);
1743 } else if (size <= 20) {
1744 if (cfg->arch.no_pushes) {
1745 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1747 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1748 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1751 if (cfg->arch.no_pushes) {
1752 // FIXME: Code growth
1753 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1755 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1756 arg->inst_basereg = src->dreg;
1757 arg->inst_offset = 0;
1758 arg->inst_imm = size;
1760 MONO_ADD_INS (cfg->cbb, arg);
1767 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1769 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1772 if (ret->type == MONO_TYPE_R4) {
1773 if (COMPILE_LLVM (cfg))
1774 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1777 } else if (ret->type == MONO_TYPE_R8) {
1778 if (COMPILE_LLVM (cfg))
1779 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1782 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1783 if (COMPILE_LLVM (cfg))
1784 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1786 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1787 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1793 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1797 * Allow tracing to work with this interface (with an optional argument)
1800 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1804 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1805 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1807 /* if some args are passed in registers, we need to save them here */
1808 x86_push_reg (code, X86_EBP);
1810 if (cfg->compile_aot) {
1811 x86_push_imm (code, cfg->method);
1812 x86_mov_reg_imm (code, X86_EAX, func);
1813 x86_call_reg (code, X86_EAX);
1815 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1816 x86_push_imm (code, cfg->method);
1817 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1818 x86_call_code (code, 0);
1820 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1834 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1837 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1838 MonoMethod *method = cfg->method;
1839 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1841 switch (ret_type->type) {
1842 case MONO_TYPE_VOID:
1843 /* special case string .ctor icall */
1844 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1845 save_mode = SAVE_EAX;
1846 stack_usage = enable_arguments ? 8 : 4;
1848 save_mode = SAVE_NONE;
1852 save_mode = SAVE_EAX_EDX;
1853 stack_usage = enable_arguments ? 16 : 8;
1857 save_mode = SAVE_FP;
1858 stack_usage = enable_arguments ? 16 : 8;
1860 case MONO_TYPE_GENERICINST:
1861 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1862 save_mode = SAVE_EAX;
1863 stack_usage = enable_arguments ? 8 : 4;
1867 case MONO_TYPE_VALUETYPE:
1868 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1869 save_mode = SAVE_STRUCT;
1870 stack_usage = enable_arguments ? 4 : 0;
1873 save_mode = SAVE_EAX;
1874 stack_usage = enable_arguments ? 8 : 4;
1878 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1880 switch (save_mode) {
1882 x86_push_reg (code, X86_EDX);
1883 x86_push_reg (code, X86_EAX);
1884 if (enable_arguments) {
1885 x86_push_reg (code, X86_EDX);
1886 x86_push_reg (code, X86_EAX);
1891 x86_push_reg (code, X86_EAX);
1892 if (enable_arguments) {
1893 x86_push_reg (code, X86_EAX);
1898 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1899 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1900 if (enable_arguments) {
1901 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1902 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1907 if (enable_arguments) {
1908 x86_push_membase (code, X86_EBP, 8);
1917 if (cfg->compile_aot) {
1918 x86_push_imm (code, method);
1919 x86_mov_reg_imm (code, X86_EAX, func);
1920 x86_call_reg (code, X86_EAX);
1922 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1923 x86_push_imm (code, method);
1924 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1925 x86_call_code (code, 0);
1928 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1930 switch (save_mode) {
1932 x86_pop_reg (code, X86_EAX);
1933 x86_pop_reg (code, X86_EDX);
1936 x86_pop_reg (code, X86_EAX);
1939 x86_fld_membase (code, X86_ESP, 0, TRUE);
1940 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1947 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1952 #define EMIT_COND_BRANCH(ins,cond,sign) \
1953 if (ins->inst_true_bb->native_offset) { \
1954 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1956 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1957 if ((cfg->opt & MONO_OPT_BRANCH) && \
1958 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1959 x86_branch8 (code, cond, 0, sign); \
1961 x86_branch32 (code, cond, 0, sign); \
1965 * Emit an exception if condition is fail and
1966 * if possible do a directly branch to target
1968 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1970 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1971 if (tins == NULL) { \
1972 mono_add_patch_info (cfg, code - cfg->native_code, \
1973 MONO_PATCH_INFO_EXC, exc_name); \
1974 x86_branch32 (code, cond, 0, signed); \
1976 EMIT_COND_BRANCH (tins, cond, signed); \
1980 #define EMIT_FPCOMPARE(code) do { \
1981 x86_fcompp (code); \
1982 x86_fnstsw (code); \
1987 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1989 gboolean needs_paddings = TRUE;
1991 MonoJumpInfo *jinfo = NULL;
1993 if (cfg->abs_patches) {
1994 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1995 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1996 needs_paddings = FALSE;
1999 if (cfg->compile_aot)
2000 needs_paddings = FALSE;
2001 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
2002 This is required for code patching to be safe on SMP machines.
2004 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
2005 #ifndef __native_client_codegen__
2006 if (needs_paddings && pad_size)
2007 x86_padding (code, 4 - pad_size);
2010 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2011 x86_call_code (code, 0);
2016 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
2019 * mono_peephole_pass_1:
2021 * Perform peephole opts which should/can be performed before local regalloc
2024 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2028 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2029 MonoInst *last_ins = ins->prev;
2031 switch (ins->opcode) {
2034 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
2036 * X86_LEA is like ADD, but doesn't have the
2037 * sreg1==dreg restriction.
2039 ins->opcode = OP_X86_LEA_MEMBASE;
2040 ins->inst_basereg = ins->sreg1;
2041 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2042 ins->opcode = OP_X86_INC_REG;
2046 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
2047 ins->opcode = OP_X86_LEA_MEMBASE;
2048 ins->inst_basereg = ins->sreg1;
2049 ins->inst_imm = -ins->inst_imm;
2050 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2051 ins->opcode = OP_X86_DEC_REG;
2053 case OP_COMPARE_IMM:
2054 case OP_ICOMPARE_IMM:
2055 /* OP_COMPARE_IMM (reg, 0)
2057 * OP_X86_TEST_NULL (reg)
2060 ins->opcode = OP_X86_TEST_NULL;
2062 case OP_X86_COMPARE_MEMBASE_IMM:
2064 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2065 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2067 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2068 * OP_COMPARE_IMM reg, imm
2070 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2072 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2073 ins->inst_basereg == last_ins->inst_destbasereg &&
2074 ins->inst_offset == last_ins->inst_offset) {
2075 ins->opcode = OP_COMPARE_IMM;
2076 ins->sreg1 = last_ins->sreg1;
2078 /* check if we can remove cmp reg,0 with test null */
2080 ins->opcode = OP_X86_TEST_NULL;
2084 case OP_X86_PUSH_MEMBASE:
2085 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
2086 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2087 ins->inst_basereg == last_ins->inst_destbasereg &&
2088 ins->inst_offset == last_ins->inst_offset) {
2089 ins->opcode = OP_X86_PUSH;
2090 ins->sreg1 = last_ins->sreg1;
2095 mono_peephole_ins (bb, ins);
2100 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2104 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2105 switch (ins->opcode) {
2107 /* reg = 0 -> XOR (reg, reg) */
2108 /* XOR sets cflags on x86, so we cant do it always */
2109 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2112 ins->opcode = OP_IXOR;
2113 ins->sreg1 = ins->dreg;
2114 ins->sreg2 = ins->dreg;
2117 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2118 * since it takes 3 bytes instead of 7.
2120 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2121 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2122 ins2->opcode = OP_STORE_MEMBASE_REG;
2123 ins2->sreg1 = ins->dreg;
2125 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2126 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2127 ins2->sreg1 = ins->dreg;
2129 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2130 /* Continue iteration */
2139 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2140 ins->opcode = OP_X86_INC_REG;
2144 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2145 ins->opcode = OP_X86_DEC_REG;
2149 mono_peephole_ins (bb, ins);
2154 * mono_arch_lowering_pass:
2156 * Converts complex opcodes into simpler ones so that each IR instruction
2157 * corresponds to one machine instruction.
2160 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2162 MonoInst *ins, *next;
2165 * FIXME: Need to add more instructions, but the current machine
2166 * description can't model some parts of the composite instructions like
2169 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2170 switch (ins->opcode) {
2173 case OP_IDIV_UN_IMM:
2174 case OP_IREM_UN_IMM:
2176 * Keep the cases where we could generated optimized code, otherwise convert
2177 * to the non-imm variant.
2179 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2181 mono_decompose_op_imm (cfg, bb, ins);
2188 bb->max_vreg = cfg->next_vreg;
2192 branch_cc_table [] = {
2193 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2194 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2195 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2198 /* Maps CMP_... constants to X86_CC_... constants */
2201 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2202 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2206 cc_signed_table [] = {
2207 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2208 FALSE, FALSE, FALSE, FALSE
2211 static unsigned char*
2212 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2214 #define XMM_TEMP_REG 0
2215 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2216 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2217 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2218 /* optimize by assigning a local var for this use so we avoid
2219 * the stack manipulations */
2220 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2221 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2222 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2223 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2224 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2226 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2228 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2231 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2232 x86_fnstcw_membase(code, X86_ESP, 0);
2233 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2234 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2235 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2236 x86_fldcw_membase (code, X86_ESP, 2);
2238 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2239 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2240 x86_pop_reg (code, dreg);
2241 /* FIXME: need the high register
2242 * x86_pop_reg (code, dreg_high);
2245 x86_push_reg (code, X86_EAX); // SP = SP - 4
2246 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2247 x86_pop_reg (code, dreg);
2249 x86_fldcw_membase (code, X86_ESP, 0);
2250 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2253 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2255 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2259 static unsigned char*
2260 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2262 int sreg = tree->sreg1;
2263 int need_touch = FALSE;
2265 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2274 * If requested stack size is larger than one page,
2275 * perform stack-touch operation
2278 * Generate stack probe code.
2279 * Under Windows, it is necessary to allocate one page at a time,
2280 * "touching" stack after each successful sub-allocation. This is
2281 * because of the way stack growth is implemented - there is a
2282 * guard page before the lowest stack page that is currently commited.
2283 * Stack normally grows sequentially so OS traps access to the
2284 * guard page and commits more pages when needed.
2286 x86_test_reg_imm (code, sreg, ~0xFFF);
2287 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2289 br[2] = code; /* loop */
2290 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2291 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2294 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2295 * that follows only initializes the last part of the area.
2297 /* Same as the init code below with size==0x1000 */
2298 if (tree->flags & MONO_INST_INIT) {
2299 x86_push_reg (code, X86_EAX);
2300 x86_push_reg (code, X86_ECX);
2301 x86_push_reg (code, X86_EDI);
2302 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2303 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2304 if (cfg->param_area && cfg->arch.no_pushes)
2305 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2307 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2309 x86_prefix (code, X86_REP_PREFIX);
2311 x86_pop_reg (code, X86_EDI);
2312 x86_pop_reg (code, X86_ECX);
2313 x86_pop_reg (code, X86_EAX);
2316 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2317 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2318 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2319 x86_patch (br[3], br[2]);
2320 x86_test_reg_reg (code, sreg, sreg);
2321 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2322 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2324 br[1] = code; x86_jump8 (code, 0);
2326 x86_patch (br[0], code);
2327 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2328 x86_patch (br[1], code);
2329 x86_patch (br[4], code);
2332 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2334 if (tree->flags & MONO_INST_INIT) {
2336 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2337 x86_push_reg (code, X86_EAX);
2340 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2341 x86_push_reg (code, X86_ECX);
2344 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2345 x86_push_reg (code, X86_EDI);
2349 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2350 if (sreg != X86_ECX)
2351 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2352 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2354 if (cfg->param_area && cfg->arch.no_pushes)
2355 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2357 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2359 x86_prefix (code, X86_REP_PREFIX);
2362 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2363 x86_pop_reg (code, X86_EDI);
2364 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2365 x86_pop_reg (code, X86_ECX);
2366 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2367 x86_pop_reg (code, X86_EAX);
2374 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2376 /* Move return value to the target register */
2377 switch (ins->opcode) {
2380 case OP_CALL_MEMBASE:
2381 if (ins->dreg != X86_EAX)
2382 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2392 static int tls_gs_offset;
2396 mono_x86_have_tls_get (void)
2399 static gboolean have_tls_get = FALSE;
2400 static gboolean inited = FALSE;
2404 return have_tls_get;
2406 ins = (guint32*)pthread_getspecific;
2408 * We're looking for these two instructions:
2410 * mov 0x4(%esp),%eax
2411 * mov %gs:[offset](,%eax,4),%eax
2413 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2414 tls_gs_offset = ins [2];
2418 return have_tls_get;
2419 #elif defined(TARGET_ANDROID)
2427 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2429 #if defined(__APPLE__)
2430 x86_prefix (code, X86_GS_PREFIX);
2431 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2432 #elif defined(TARGET_WIN32)
2433 g_assert_not_reached ();
2435 x86_prefix (code, X86_GS_PREFIX);
2436 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2442 * mono_x86_emit_tls_get:
2443 * @code: buffer to store code to
2444 * @dreg: hard register where to place the result
2445 * @tls_offset: offset info
2447 * mono_x86_emit_tls_get emits in @code the native code that puts in
2448 * the dreg register the item in the thread local storage identified
2451 * Returns: a pointer to the end of the stored code
2454 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2456 #if defined(__APPLE__)
2457 x86_prefix (code, X86_GS_PREFIX);
2458 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2459 #elif defined(TARGET_WIN32)
2461 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2462 * Journal and/or a disassembly of the TlsGet () function.
2464 g_assert (tls_offset < 64);
2465 x86_prefix (code, X86_FS_PREFIX);
2466 x86_mov_reg_mem (code, dreg, 0x18, 4);
2467 /* Dunno what this does but TlsGetValue () contains it */
2468 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2469 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2471 if (optimize_for_xen) {
2472 x86_prefix (code, X86_GS_PREFIX);
2473 x86_mov_reg_mem (code, dreg, 0, 4);
2474 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2476 x86_prefix (code, X86_GS_PREFIX);
2477 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2484 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2486 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2487 #if defined(__APPLE__) || defined(__linux__)
2488 if (dreg != offset_reg)
2489 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2490 x86_prefix (code, X86_GS_PREFIX);
2491 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2493 g_assert_not_reached ();
2499 mono_x86_emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2501 return emit_tls_get_reg (code, dreg, offset_reg);
2505 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2507 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2509 g_assert_not_reached ();
2510 #elif defined(__APPLE__) || defined(__linux__)
2511 x86_prefix (code, X86_GS_PREFIX);
2512 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2514 g_assert_not_reached ();
2520 * mono_arch_translate_tls_offset:
2522 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2525 mono_arch_translate_tls_offset (int offset)
2528 return tls_gs_offset + (offset * 4);
2537 * Emit code to initialize an LMF structure at LMF_OFFSET.
2540 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2542 /* save all caller saved regs */
2543 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2544 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2545 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2546 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2547 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2548 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2549 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2551 /* save the current IP */
2552 if (cfg->compile_aot) {
2553 /* This pushes the current ip */
2554 x86_call_imm (code, 0);
2555 x86_pop_reg (code, X86_EAX);
2557 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2558 x86_mov_reg_imm (code, X86_EAX, 0);
2560 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2562 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2563 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2564 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2565 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2566 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2567 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2568 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2569 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2570 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2575 #define REAL_PRINT_REG(text,reg) \
2576 mono_assert (reg >= 0); \
2577 x86_push_reg (code, X86_EAX); \
2578 x86_push_reg (code, X86_EDX); \
2579 x86_push_reg (code, X86_ECX); \
2580 x86_push_reg (code, reg); \
2581 x86_push_imm (code, reg); \
2582 x86_push_imm (code, text " %d %p\n"); \
2583 x86_mov_reg_imm (code, X86_EAX, printf); \
2584 x86_call_reg (code, X86_EAX); \
2585 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2586 x86_pop_reg (code, X86_ECX); \
2587 x86_pop_reg (code, X86_EDX); \
2588 x86_pop_reg (code, X86_EAX);
2590 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2591 #ifdef __native__client_codegen__
2592 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2595 /* benchmark and set based on cpu */
2596 #define LOOP_ALIGNMENT 8
2597 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2601 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2606 guint8 *code = cfg->native_code + cfg->code_len;
2609 if (cfg->opt & MONO_OPT_LOOP) {
2610 int pad, align = LOOP_ALIGNMENT;
2611 /* set alignment depending on cpu */
2612 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2614 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2615 x86_padding (code, pad);
2616 cfg->code_len += pad;
2617 bb->native_offset = cfg->code_len;
2620 #ifdef __native_client_codegen__
2622 /* For Native Client, all indirect call/jump targets must be */
2623 /* 32-byte aligned. Exception handler blocks are jumped to */
2624 /* indirectly as well. */
2625 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2626 (bb->flags & BB_EXCEPTION_HANDLER);
2628 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2629 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2630 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2631 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2632 cfg->code_len += pad;
2633 bb->native_offset = cfg->code_len;
2636 #endif /* __native_client_codegen__ */
2637 if (cfg->verbose_level > 2)
2638 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2640 cpos = bb->max_offset;
2642 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2643 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2644 g_assert (!cfg->compile_aot);
2647 cov->data [bb->dfn].cil_code = bb->cil_code;
2648 /* this is not thread save, but good enough */
2649 x86_inc_mem (code, &cov->data [bb->dfn].count);
2652 offset = code - cfg->native_code;
2654 mono_debug_open_block (cfg, bb, offset);
2656 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2657 x86_breakpoint (code);
2659 MONO_BB_FOR_EACH_INS (bb, ins) {
2660 offset = code - cfg->native_code;
2662 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2664 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2666 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2667 cfg->code_size *= 2;
2668 cfg->native_code = mono_realloc_native_code(cfg);
2669 code = cfg->native_code + offset;
2670 cfg->stat_code_reallocs++;
2673 if (cfg->debug_info)
2674 mono_debug_record_line_number (cfg, ins, offset);
2676 switch (ins->opcode) {
2678 x86_mul_reg (code, ins->sreg2, TRUE);
2681 x86_mul_reg (code, ins->sreg2, FALSE);
2683 case OP_X86_SETEQ_MEMBASE:
2684 case OP_X86_SETNE_MEMBASE:
2685 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2686 ins->inst_basereg, ins->inst_offset, TRUE);
2688 case OP_STOREI1_MEMBASE_IMM:
2689 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2691 case OP_STOREI2_MEMBASE_IMM:
2692 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2694 case OP_STORE_MEMBASE_IMM:
2695 case OP_STOREI4_MEMBASE_IMM:
2696 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2698 case OP_STOREI1_MEMBASE_REG:
2699 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2701 case OP_STOREI2_MEMBASE_REG:
2702 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2704 case OP_STORE_MEMBASE_REG:
2705 case OP_STOREI4_MEMBASE_REG:
2706 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2708 case OP_STORE_MEM_IMM:
2709 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2712 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2716 /* These are created by the cprop pass so they use inst_imm as the source */
2717 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2720 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2723 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2725 case OP_LOAD_MEMBASE:
2726 case OP_LOADI4_MEMBASE:
2727 case OP_LOADU4_MEMBASE:
2728 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2730 case OP_LOADU1_MEMBASE:
2731 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2733 case OP_LOADI1_MEMBASE:
2734 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2736 case OP_LOADU2_MEMBASE:
2737 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2739 case OP_LOADI2_MEMBASE:
2740 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2742 case OP_ICONV_TO_I1:
2744 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2746 case OP_ICONV_TO_I2:
2748 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2750 case OP_ICONV_TO_U1:
2751 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2753 case OP_ICONV_TO_U2:
2754 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2758 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2760 case OP_COMPARE_IMM:
2761 case OP_ICOMPARE_IMM:
2762 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2764 case OP_X86_COMPARE_MEMBASE_REG:
2765 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2767 case OP_X86_COMPARE_MEMBASE_IMM:
2768 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2770 case OP_X86_COMPARE_MEMBASE8_IMM:
2771 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2773 case OP_X86_COMPARE_REG_MEMBASE:
2774 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2776 case OP_X86_COMPARE_MEM_IMM:
2777 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2779 case OP_X86_TEST_NULL:
2780 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2782 case OP_X86_ADD_MEMBASE_IMM:
2783 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2785 case OP_X86_ADD_REG_MEMBASE:
2786 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2788 case OP_X86_SUB_MEMBASE_IMM:
2789 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2791 case OP_X86_SUB_REG_MEMBASE:
2792 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2794 case OP_X86_AND_MEMBASE_IMM:
2795 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2797 case OP_X86_OR_MEMBASE_IMM:
2798 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2800 case OP_X86_XOR_MEMBASE_IMM:
2801 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2803 case OP_X86_ADD_MEMBASE_REG:
2804 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2806 case OP_X86_SUB_MEMBASE_REG:
2807 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2809 case OP_X86_AND_MEMBASE_REG:
2810 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2812 case OP_X86_OR_MEMBASE_REG:
2813 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2815 case OP_X86_XOR_MEMBASE_REG:
2816 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2818 case OP_X86_INC_MEMBASE:
2819 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2821 case OP_X86_INC_REG:
2822 x86_inc_reg (code, ins->dreg);
2824 case OP_X86_DEC_MEMBASE:
2825 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2827 case OP_X86_DEC_REG:
2828 x86_dec_reg (code, ins->dreg);
2830 case OP_X86_MUL_REG_MEMBASE:
2831 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2833 case OP_X86_AND_REG_MEMBASE:
2834 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2836 case OP_X86_OR_REG_MEMBASE:
2837 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2839 case OP_X86_XOR_REG_MEMBASE:
2840 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2843 x86_breakpoint (code);
2845 case OP_RELAXED_NOP:
2846 x86_prefix (code, X86_REP_PREFIX);
2854 case OP_DUMMY_STORE:
2855 case OP_DUMMY_ICONST:
2856 case OP_DUMMY_R8CONST:
2857 case OP_NOT_REACHED:
2860 case OP_SEQ_POINT: {
2863 if (cfg->compile_aot)
2867 * Read from the single stepping trigger page. This will cause a
2868 * SIGSEGV when single stepping is enabled.
2869 * We do this _before_ the breakpoint, so single stepping after
2870 * a breakpoint is hit will step to the next IL offset.
2872 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2873 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2875 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2878 * A placeholder for a possible breakpoint inserted by
2879 * mono_arch_set_breakpoint ().
2881 for (i = 0; i < 6; ++i)
2884 * Add an additional nop so skipping the bp doesn't cause the ip to point
2885 * to another IL offset.
2893 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2897 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2902 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2906 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2911 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2915 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2920 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2924 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2927 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2931 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2935 #if defined( __native_client_codegen__ )
2936 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2937 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2940 * The code is the same for div/rem, the allocator will allocate dreg
2941 * to RAX/RDX as appropriate.
2943 if (ins->sreg2 == X86_EDX) {
2944 /* cdq clobbers this */
2945 x86_push_reg (code, ins->sreg2);
2947 x86_div_membase (code, X86_ESP, 0, TRUE);
2948 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2951 x86_div_reg (code, ins->sreg2, TRUE);
2956 #if defined( __native_client_codegen__ )
2957 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2958 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2960 if (ins->sreg2 == X86_EDX) {
2961 x86_push_reg (code, ins->sreg2);
2962 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2963 x86_div_membase (code, X86_ESP, 0, FALSE);
2964 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2966 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2967 x86_div_reg (code, ins->sreg2, FALSE);
2971 #if defined( __native_client_codegen__ )
2972 if (ins->inst_imm == 0) {
2973 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2974 x86_jump32 (code, 0);
2978 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2980 x86_div_reg (code, ins->sreg2, TRUE);
2983 int power = mono_is_power_of_two (ins->inst_imm);
2985 g_assert (ins->sreg1 == X86_EAX);
2986 g_assert (ins->dreg == X86_EAX);
2987 g_assert (power >= 0);
2990 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2992 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2994 * If the divident is >= 0, this does not nothing. If it is positive, it
2995 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2997 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2998 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2999 } else if (power == 0) {
3000 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3002 /* Based on gcc code */
3004 /* Add compensation for negative dividents */
3006 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
3007 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
3008 /* Compute remainder */
3009 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
3010 /* Remove compensation */
3011 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
3016 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3020 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3023 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3027 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3030 g_assert (ins->sreg2 == X86_ECX);
3031 x86_shift_reg (code, X86_SHL, ins->dreg);
3034 g_assert (ins->sreg2 == X86_ECX);
3035 x86_shift_reg (code, X86_SAR, ins->dreg);
3039 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3042 case OP_ISHR_UN_IMM:
3043 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3046 g_assert (ins->sreg2 == X86_ECX);
3047 x86_shift_reg (code, X86_SHR, ins->dreg);
3051 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3054 guint8 *jump_to_end;
3056 /* handle shifts below 32 bits */
3057 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
3058 x86_shift_reg (code, X86_SHL, ins->sreg1);
3060 x86_test_reg_imm (code, X86_ECX, 32);
3061 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3063 /* handle shift over 32 bit */
3064 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3065 x86_clear_reg (code, ins->sreg1);
3067 x86_patch (jump_to_end, code);
3071 guint8 *jump_to_end;
3073 /* handle shifts below 32 bits */
3074 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3075 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
3077 x86_test_reg_imm (code, X86_ECX, 32);
3078 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3080 /* handle shifts over 31 bits */
3081 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3082 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
3084 x86_patch (jump_to_end, code);
3088 guint8 *jump_to_end;
3090 /* handle shifts below 32 bits */
3091 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3092 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
3094 x86_test_reg_imm (code, X86_ECX, 32);
3095 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3097 /* handle shifts over 31 bits */
3098 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3099 x86_clear_reg (code, ins->backend.reg3);
3101 x86_patch (jump_to_end, code);
3105 if (ins->inst_imm >= 32) {
3106 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3107 x86_clear_reg (code, ins->sreg1);
3108 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
3110 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
3111 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
3115 if (ins->inst_imm >= 32) {
3116 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3117 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
3118 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
3120 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3121 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3124 case OP_LSHR_UN_IMM:
3125 if (ins->inst_imm >= 32) {
3126 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3127 x86_clear_reg (code, ins->backend.reg3);
3128 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3130 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3131 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3135 x86_not_reg (code, ins->sreg1);
3138 x86_neg_reg (code, ins->sreg1);
3142 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3146 switch (ins->inst_imm) {
3150 if (ins->dreg != ins->sreg1)
3151 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3152 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3155 /* LEA r1, [r2 + r2*2] */
3156 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3159 /* LEA r1, [r2 + r2*4] */
3160 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3163 /* LEA r1, [r2 + r2*2] */
3165 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3166 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3169 /* LEA r1, [r2 + r2*8] */
3170 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3173 /* LEA r1, [r2 + r2*4] */
3175 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3176 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3179 /* LEA r1, [r2 + r2*2] */
3181 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3182 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3185 /* LEA r1, [r2 + r2*4] */
3186 /* LEA r1, [r1 + r1*4] */
3187 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3188 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3191 /* LEA r1, [r2 + r2*4] */
3193 /* LEA r1, [r1 + r1*4] */
3194 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3195 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3196 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3199 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3204 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3205 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3207 case OP_IMUL_OVF_UN: {
3208 /* the mul operation and the exception check should most likely be split */
3209 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3210 /*g_assert (ins->sreg2 == X86_EAX);
3211 g_assert (ins->dreg == X86_EAX);*/
3212 if (ins->sreg2 == X86_EAX) {
3213 non_eax_reg = ins->sreg1;
3214 } else if (ins->sreg1 == X86_EAX) {
3215 non_eax_reg = ins->sreg2;
3217 /* no need to save since we're going to store to it anyway */
3218 if (ins->dreg != X86_EAX) {
3220 x86_push_reg (code, X86_EAX);
3222 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3223 non_eax_reg = ins->sreg2;
3225 if (ins->dreg == X86_EDX) {
3228 x86_push_reg (code, X86_EAX);
3230 } else if (ins->dreg != X86_EAX) {
3232 x86_push_reg (code, X86_EDX);
3234 x86_mul_reg (code, non_eax_reg, FALSE);
3235 /* save before the check since pop and mov don't change the flags */
3236 if (ins->dreg != X86_EAX)
3237 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3239 x86_pop_reg (code, X86_EDX);
3241 x86_pop_reg (code, X86_EAX);
3242 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3246 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3249 g_assert_not_reached ();
3250 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3251 x86_mov_reg_imm (code, ins->dreg, 0);
3254 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3255 x86_mov_reg_imm (code, ins->dreg, 0);
3257 case OP_LOAD_GOTADDR:
3258 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3259 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3262 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3263 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3265 case OP_X86_PUSH_GOT_ENTRY:
3266 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3267 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3270 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3273 MonoCallInst *call = (MonoCallInst*)ins;
3276 ins->flags |= MONO_INST_GC_CALLSITE;
3277 ins->backend.pc_offset = code - cfg->native_code;
3279 /* reset offset to make max_len work */
3280 offset = code - cfg->native_code;
3282 g_assert (!cfg->method->save_lmf);
3284 /* restore callee saved registers */
3285 for (i = 0; i < X86_NREG; ++i)
3286 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3288 if (cfg->used_int_regs & (1 << X86_ESI)) {
3289 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3292 if (cfg->used_int_regs & (1 << X86_EDI)) {
3293 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3296 if (cfg->used_int_regs & (1 << X86_EBX)) {
3297 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3301 /* Copy arguments on the stack to our argument area */
3302 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3303 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3304 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3307 /* restore ESP/EBP */
3309 offset = code - cfg->native_code;
3310 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3311 x86_jump32 (code, 0);
3313 ins->flags |= MONO_INST_GC_CALLSITE;
3314 cfg->disable_aot = TRUE;
3318 /* ensure ins->sreg1 is not NULL
3319 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3320 * cmp DWORD PTR [eax], 0
3322 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3325 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3326 x86_push_reg (code, hreg);
3327 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3328 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3329 x86_pop_reg (code, hreg);
3342 case OP_VOIDCALL_REG:
3344 case OP_FCALL_MEMBASE:
3345 case OP_LCALL_MEMBASE:
3346 case OP_VCALL_MEMBASE:
3347 case OP_VCALL2_MEMBASE:
3348 case OP_VOIDCALL_MEMBASE:
3349 case OP_CALL_MEMBASE: {
3352 call = (MonoCallInst*)ins;
3353 cinfo = (CallInfo*)call->call_info;
3355 switch (ins->opcode) {
3362 if (ins->flags & MONO_INST_HAS_METHOD)
3363 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3365 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3371 case OP_VOIDCALL_REG:
3373 x86_call_reg (code, ins->sreg1);
3375 case OP_FCALL_MEMBASE:
3376 case OP_LCALL_MEMBASE:
3377 case OP_VCALL_MEMBASE:
3378 case OP_VCALL2_MEMBASE:
3379 case OP_VOIDCALL_MEMBASE:
3380 case OP_CALL_MEMBASE:
3381 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3384 g_assert_not_reached ();
3387 ins->flags |= MONO_INST_GC_CALLSITE;
3388 ins->backend.pc_offset = code - cfg->native_code;
3389 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature) && !cfg->arch.no_pushes) {
3390 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
3391 * bytes to pop, we want to use pops. GCC does this (note it won't happen
3392 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
3393 * smart enough to do that optimization yet
3395 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
3396 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
3397 * (most likely from locality benefits). People with other processors should
3398 * check on theirs to see what happens.
3400 if (call->stack_usage == 4) {
3401 /* we want to use registers that won't get used soon, so use
3402 * ecx, as eax will get allocated first. edx is used by long calls,
3403 * so we can't use that.
3406 x86_pop_reg (code, X86_ECX);
3408 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3410 } else if (cinfo->callee_stack_pop && cfg->arch.no_pushes) {
3411 /* Have to compensate for the stack space popped by the callee */
3412 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3414 code = emit_move_return_value (cfg, ins, code);
3418 g_assert (!cfg->arch.no_pushes);
3419 x86_push_reg (code, ins->sreg1);
3421 case OP_X86_PUSH_IMM:
3422 g_assert (!cfg->arch.no_pushes);
3423 x86_push_imm (code, ins->inst_imm);
3425 case OP_X86_PUSH_MEMBASE:
3426 g_assert (!cfg->arch.no_pushes);
3427 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
3429 case OP_X86_PUSH_OBJ:
3430 g_assert (!cfg->arch.no_pushes);
3431 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
3432 x86_push_reg (code, X86_EDI);
3433 x86_push_reg (code, X86_ESI);
3434 x86_push_reg (code, X86_ECX);
3435 if (ins->inst_offset)
3436 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
3438 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
3439 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
3440 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
3442 x86_prefix (code, X86_REP_PREFIX);
3444 x86_pop_reg (code, X86_ECX);
3445 x86_pop_reg (code, X86_ESI);
3446 x86_pop_reg (code, X86_EDI);
3449 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3451 case OP_X86_LEA_MEMBASE:
3452 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3455 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3458 /* keep alignment */
3459 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3460 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3461 code = mono_emit_stack_alloc (cfg, code, ins);
3462 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3463 if (cfg->param_area && cfg->arch.no_pushes)
3464 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3466 case OP_LOCALLOC_IMM: {
3467 guint32 size = ins->inst_imm;
3468 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3470 if (ins->flags & MONO_INST_INIT) {
3471 /* FIXME: Optimize this */
3472 x86_mov_reg_imm (code, ins->dreg, size);
3473 ins->sreg1 = ins->dreg;
3475 code = mono_emit_stack_alloc (cfg, code, ins);
3476 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3478 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3479 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3481 if (cfg->param_area && cfg->arch.no_pushes)
3482 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3486 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3487 x86_push_reg (code, ins->sreg1);
3488 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3489 (gpointer)"mono_arch_throw_exception");
3490 ins->flags |= MONO_INST_GC_CALLSITE;
3491 ins->backend.pc_offset = code - cfg->native_code;
3495 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3496 x86_push_reg (code, ins->sreg1);
3497 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3498 (gpointer)"mono_arch_rethrow_exception");
3499 ins->flags |= MONO_INST_GC_CALLSITE;
3500 ins->backend.pc_offset = code - cfg->native_code;
3503 case OP_CALL_HANDLER:
3504 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3505 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3506 x86_call_imm (code, 0);
3507 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3508 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3510 case OP_START_HANDLER: {
3511 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3512 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3513 if (cfg->param_area && cfg->arch.no_pushes) {
3514 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3518 case OP_ENDFINALLY: {
3519 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3520 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3524 case OP_ENDFILTER: {
3525 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3526 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3527 /* The local allocator will put the result into EAX */
3533 ins->inst_c0 = code - cfg->native_code;
3536 if (ins->inst_target_bb->native_offset) {
3537 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3539 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3540 if ((cfg->opt & MONO_OPT_BRANCH) &&
3541 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3542 x86_jump8 (code, 0);
3544 x86_jump32 (code, 0);
3548 x86_jump_reg (code, ins->sreg1);
3567 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3568 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3570 case OP_COND_EXC_EQ:
3571 case OP_COND_EXC_NE_UN:
3572 case OP_COND_EXC_LT:
3573 case OP_COND_EXC_LT_UN:
3574 case OP_COND_EXC_GT:
3575 case OP_COND_EXC_GT_UN:
3576 case OP_COND_EXC_GE:
3577 case OP_COND_EXC_GE_UN:
3578 case OP_COND_EXC_LE:
3579 case OP_COND_EXC_LE_UN:
3580 case OP_COND_EXC_IEQ:
3581 case OP_COND_EXC_INE_UN:
3582 case OP_COND_EXC_ILT:
3583 case OP_COND_EXC_ILT_UN:
3584 case OP_COND_EXC_IGT:
3585 case OP_COND_EXC_IGT_UN:
3586 case OP_COND_EXC_IGE:
3587 case OP_COND_EXC_IGE_UN:
3588 case OP_COND_EXC_ILE:
3589 case OP_COND_EXC_ILE_UN:
3590 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3592 case OP_COND_EXC_OV:
3593 case OP_COND_EXC_NO:
3595 case OP_COND_EXC_NC:
3596 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3598 case OP_COND_EXC_IOV:
3599 case OP_COND_EXC_INO:
3600 case OP_COND_EXC_IC:
3601 case OP_COND_EXC_INC:
3602 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3614 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3622 case OP_CMOV_INE_UN:
3623 case OP_CMOV_IGE_UN:
3624 case OP_CMOV_IGT_UN:
3625 case OP_CMOV_ILE_UN:
3626 case OP_CMOV_ILT_UN:
3627 g_assert (ins->dreg == ins->sreg1);
3628 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3631 /* floating point opcodes */
3633 double d = *(double *)ins->inst_p0;
3635 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3637 } else if (d == 1.0) {
3640 if (cfg->compile_aot) {
3641 guint32 *val = (guint32*)&d;
3642 x86_push_imm (code, val [1]);
3643 x86_push_imm (code, val [0]);
3644 x86_fld_membase (code, X86_ESP, 0, TRUE);
3645 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3648 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3649 x86_fld (code, NULL, TRUE);
3655 float f = *(float *)ins->inst_p0;
3657 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3659 } else if (f == 1.0) {
3662 if (cfg->compile_aot) {
3663 guint32 val = *(guint32*)&f;
3664 x86_push_imm (code, val);
3665 x86_fld_membase (code, X86_ESP, 0, FALSE);
3666 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3669 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3670 x86_fld (code, NULL, FALSE);
3675 case OP_STORER8_MEMBASE_REG:
3676 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3678 case OP_LOADR8_MEMBASE:
3679 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3681 case OP_STORER4_MEMBASE_REG:
3682 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3684 case OP_LOADR4_MEMBASE:
3685 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3687 case OP_ICONV_TO_R4:
3688 x86_push_reg (code, ins->sreg1);
3689 x86_fild_membase (code, X86_ESP, 0, FALSE);
3690 /* Change precision */
3691 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3692 x86_fld_membase (code, X86_ESP, 0, FALSE);
3693 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3695 case OP_ICONV_TO_R8:
3696 x86_push_reg (code, ins->sreg1);
3697 x86_fild_membase (code, X86_ESP, 0, FALSE);
3698 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3700 case OP_ICONV_TO_R_UN:
3701 x86_push_imm (code, 0);
3702 x86_push_reg (code, ins->sreg1);
3703 x86_fild_membase (code, X86_ESP, 0, TRUE);
3704 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3706 case OP_X86_FP_LOAD_I8:
3707 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3709 case OP_X86_FP_LOAD_I4:
3710 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3712 case OP_FCONV_TO_R4:
3713 /* Change precision */
3714 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3715 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3716 x86_fld_membase (code, X86_ESP, 0, FALSE);
3717 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3719 case OP_FCONV_TO_I1:
3720 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3722 case OP_FCONV_TO_U1:
3723 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3725 case OP_FCONV_TO_I2:
3726 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3728 case OP_FCONV_TO_U2:
3729 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3731 case OP_FCONV_TO_I4:
3733 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3735 case OP_FCONV_TO_I8:
3736 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3737 x86_fnstcw_membase(code, X86_ESP, 0);
3738 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3739 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3740 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3741 x86_fldcw_membase (code, X86_ESP, 2);
3742 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3743 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3744 x86_pop_reg (code, ins->dreg);
3745 x86_pop_reg (code, ins->backend.reg3);
3746 x86_fldcw_membase (code, X86_ESP, 0);
3747 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3749 case OP_LCONV_TO_R8_2:
3750 x86_push_reg (code, ins->sreg2);
3751 x86_push_reg (code, ins->sreg1);
3752 x86_fild_membase (code, X86_ESP, 0, TRUE);
3753 /* Change precision */
3754 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3755 x86_fld_membase (code, X86_ESP, 0, TRUE);
3756 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3758 case OP_LCONV_TO_R4_2:
3759 x86_push_reg (code, ins->sreg2);
3760 x86_push_reg (code, ins->sreg1);
3761 x86_fild_membase (code, X86_ESP, 0, TRUE);
3762 /* Change precision */
3763 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3764 x86_fld_membase (code, X86_ESP, 0, FALSE);
3765 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3767 case OP_LCONV_TO_R_UN_2: {
3768 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3771 /* load 64bit integer to FP stack */
3772 x86_push_reg (code, ins->sreg2);
3773 x86_push_reg (code, ins->sreg1);
3774 x86_fild_membase (code, X86_ESP, 0, TRUE);
3776 /* test if lreg is negative */
3777 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3778 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3780 /* add correction constant mn */
3781 if (cfg->compile_aot) {
3782 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3783 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3784 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3785 x86_fld80_membase (code, X86_ESP, 2);
3786 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3788 x86_fld80_mem (code, mn);
3790 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3792 x86_patch (br, code);
3794 /* Change precision */
3795 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3796 x86_fld_membase (code, X86_ESP, 0, TRUE);
3798 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3802 case OP_LCONV_TO_OVF_I:
3803 case OP_LCONV_TO_OVF_I4_2: {
3804 guint8 *br [3], *label [1];
3808 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3810 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3812 /* If the low word top bit is set, see if we are negative */
3813 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3814 /* We are not negative (no top bit set, check for our top word to be zero */
3815 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3816 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3819 /* throw exception */
3820 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3822 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3823 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3824 x86_jump8 (code, 0);
3826 x86_jump32 (code, 0);
3828 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3829 x86_jump32 (code, 0);
3833 x86_patch (br [0], code);
3834 /* our top bit is set, check that top word is 0xfffffff */
3835 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3837 x86_patch (br [1], code);
3838 /* nope, emit exception */
3839 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3840 x86_patch (br [2], label [0]);
3842 if (ins->dreg != ins->sreg1)
3843 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3847 /* Not needed on the fp stack */
3850 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3853 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3856 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3859 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3867 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3872 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3879 * it really doesn't make sense to inline all this code,
3880 * it's here just to show that things may not be as simple
3883 guchar *check_pos, *end_tan, *pop_jump;
3884 x86_push_reg (code, X86_EAX);
3887 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3889 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3890 x86_fstp (code, 0); /* pop the 1.0 */
3892 x86_jump8 (code, 0);
3894 x86_fp_op (code, X86_FADD, 0);
3898 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3900 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3903 x86_patch (pop_jump, code);
3904 x86_fstp (code, 0); /* pop the 1.0 */
3905 x86_patch (check_pos, code);
3906 x86_patch (end_tan, code);
3908 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3909 x86_pop_reg (code, X86_EAX);
3916 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3925 g_assert (cfg->opt & MONO_OPT_CMOV);
3926 g_assert (ins->dreg == ins->sreg1);
3927 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3928 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3931 g_assert (cfg->opt & MONO_OPT_CMOV);
3932 g_assert (ins->dreg == ins->sreg1);
3933 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3934 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3937 g_assert (cfg->opt & MONO_OPT_CMOV);
3938 g_assert (ins->dreg == ins->sreg1);
3939 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3940 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3943 g_assert (cfg->opt & MONO_OPT_CMOV);
3944 g_assert (ins->dreg == ins->sreg1);
3945 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3946 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3952 x86_fxch (code, ins->inst_imm);
3957 x86_push_reg (code, X86_EAX);
3958 /* we need to exchange ST(0) with ST(1) */
3961 /* this requires a loop, because fprem somtimes
3962 * returns a partial remainder */
3964 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3965 /* x86_fprem1 (code); */
3968 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3970 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3976 x86_pop_reg (code, X86_EAX);
3980 if (cfg->opt & MONO_OPT_FCMOV) {
3981 x86_fcomip (code, 1);
3985 /* this overwrites EAX */
3986 EMIT_FPCOMPARE(code);
3987 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3991 if (cfg->opt & MONO_OPT_FCMOV) {
3992 /* zeroing the register at the start results in
3993 * shorter and faster code (we can also remove the widening op)
3995 guchar *unordered_check;
3996 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3997 x86_fcomip (code, 1);
3999 unordered_check = code;
4000 x86_branch8 (code, X86_CC_P, 0, FALSE);
4001 if (ins->opcode == OP_FCEQ) {
4002 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4003 x86_patch (unordered_check, code);
4005 guchar *jump_to_end;
4006 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
4008 x86_jump8 (code, 0);
4009 x86_patch (unordered_check, code);
4010 x86_inc_reg (code, ins->dreg);
4011 x86_patch (jump_to_end, code);
4016 if (ins->dreg != X86_EAX)
4017 x86_push_reg (code, X86_EAX);
4019 EMIT_FPCOMPARE(code);
4020 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4021 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4022 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
4023 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4025 if (ins->dreg != X86_EAX)
4026 x86_pop_reg (code, X86_EAX);
4030 if (cfg->opt & MONO_OPT_FCMOV) {
4031 /* zeroing the register at the start results in
4032 * shorter and faster code (we can also remove the widening op)
4034 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4035 x86_fcomip (code, 1);
4037 if (ins->opcode == OP_FCLT_UN) {
4038 guchar *unordered_check = code;
4039 guchar *jump_to_end;
4040 x86_branch8 (code, X86_CC_P, 0, FALSE);
4041 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4043 x86_jump8 (code, 0);
4044 x86_patch (unordered_check, code);
4045 x86_inc_reg (code, ins->dreg);
4046 x86_patch (jump_to_end, code);
4048 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4052 if (ins->dreg != X86_EAX)
4053 x86_push_reg (code, X86_EAX);
4055 EMIT_FPCOMPARE(code);
4056 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4057 if (ins->opcode == OP_FCLT_UN) {
4058 guchar *is_not_zero_check, *end_jump;
4059 is_not_zero_check = code;
4060 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4062 x86_jump8 (code, 0);
4063 x86_patch (is_not_zero_check, code);
4064 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4066 x86_patch (end_jump, code);
4068 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4069 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4071 if (ins->dreg != X86_EAX)
4072 x86_pop_reg (code, X86_EAX);
4075 guchar *unordered_check;
4076 guchar *jump_to_end;
4077 if (cfg->opt & MONO_OPT_FCMOV) {
4078 /* zeroing the register at the start results in
4079 * shorter and faster code (we can also remove the widening op)
4081 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4082 x86_fcomip (code, 1);
4084 unordered_check = code;
4085 x86_branch8 (code, X86_CC_P, 0, FALSE);
4086 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
4087 x86_patch (unordered_check, code);
4090 if (ins->dreg != X86_EAX)
4091 x86_push_reg (code, X86_EAX);
4093 EMIT_FPCOMPARE(code);
4094 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4095 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4096 unordered_check = code;
4097 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4099 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4100 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
4101 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4103 x86_jump8 (code, 0);
4104 x86_patch (unordered_check, code);
4105 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4106 x86_patch (jump_to_end, code);
4108 if (ins->dreg != X86_EAX)
4109 x86_pop_reg (code, X86_EAX);
4114 if (cfg->opt & MONO_OPT_FCMOV) {
4115 /* zeroing the register at the start results in
4116 * shorter and faster code (we can also remove the widening op)
4118 guchar *unordered_check;
4119 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4120 x86_fcomip (code, 1);
4122 if (ins->opcode == OP_FCGT) {
4123 unordered_check = code;
4124 x86_branch8 (code, X86_CC_P, 0, FALSE);
4125 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4126 x86_patch (unordered_check, code);
4128 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4132 if (ins->dreg != X86_EAX)
4133 x86_push_reg (code, X86_EAX);
4135 EMIT_FPCOMPARE(code);
4136 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4137 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4138 if (ins->opcode == OP_FCGT_UN) {
4139 guchar *is_not_zero_check, *end_jump;
4140 is_not_zero_check = code;
4141 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4143 x86_jump8 (code, 0);
4144 x86_patch (is_not_zero_check, code);
4145 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4147 x86_patch (end_jump, code);
4149 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4150 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4152 if (ins->dreg != X86_EAX)
4153 x86_pop_reg (code, X86_EAX);
4156 guchar *unordered_check;
4157 guchar *jump_to_end;
4158 if (cfg->opt & MONO_OPT_FCMOV) {
4159 /* zeroing the register at the start results in
4160 * shorter and faster code (we can also remove the widening op)
4162 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4163 x86_fcomip (code, 1);
4165 unordered_check = code;
4166 x86_branch8 (code, X86_CC_P, 0, FALSE);
4167 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4168 x86_patch (unordered_check, code);
4171 if (ins->dreg != X86_EAX)
4172 x86_push_reg (code, X86_EAX);
4174 EMIT_FPCOMPARE(code);
4175 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4176 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4177 unordered_check = code;
4178 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4180 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4181 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4182 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4184 x86_jump8 (code, 0);
4185 x86_patch (unordered_check, code);
4186 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4187 x86_patch (jump_to_end, code);
4189 if (ins->dreg != X86_EAX)
4190 x86_pop_reg (code, X86_EAX);
4194 if (cfg->opt & MONO_OPT_FCMOV) {
4195 guchar *jump = code;
4196 x86_branch8 (code, X86_CC_P, 0, TRUE);
4197 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4198 x86_patch (jump, code);
4201 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4202 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4205 /* Branch if C013 != 100 */
4206 if (cfg->opt & MONO_OPT_FCMOV) {
4207 /* branch if !ZF or (PF|CF) */
4208 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4209 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4210 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4213 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4214 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4217 if (cfg->opt & MONO_OPT_FCMOV) {
4218 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4221 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4224 if (cfg->opt & MONO_OPT_FCMOV) {
4225 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4226 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4229 if (ins->opcode == OP_FBLT_UN) {
4230 guchar *is_not_zero_check, *end_jump;
4231 is_not_zero_check = code;
4232 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4234 x86_jump8 (code, 0);
4235 x86_patch (is_not_zero_check, code);
4236 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4238 x86_patch (end_jump, code);
4240 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4244 if (cfg->opt & MONO_OPT_FCMOV) {
4245 if (ins->opcode == OP_FBGT) {
4248 /* skip branch if C1=1 */
4250 x86_branch8 (code, X86_CC_P, 0, FALSE);
4251 /* branch if (C0 | C3) = 1 */
4252 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4253 x86_patch (br1, code);
4255 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4259 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4260 if (ins->opcode == OP_FBGT_UN) {
4261 guchar *is_not_zero_check, *end_jump;
4262 is_not_zero_check = code;
4263 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4265 x86_jump8 (code, 0);
4266 x86_patch (is_not_zero_check, code);
4267 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4269 x86_patch (end_jump, code);
4271 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4274 /* Branch if C013 == 100 or 001 */
4275 if (cfg->opt & MONO_OPT_FCMOV) {
4278 /* skip branch if C1=1 */
4280 x86_branch8 (code, X86_CC_P, 0, FALSE);
4281 /* branch if (C0 | C3) = 1 */
4282 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4283 x86_patch (br1, code);
4286 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4287 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4288 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4289 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4292 /* Branch if C013 == 000 */
4293 if (cfg->opt & MONO_OPT_FCMOV) {
4294 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4297 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4300 /* Branch if C013=000 or 100 */
4301 if (cfg->opt & MONO_OPT_FCMOV) {
4304 /* skip branch if C1=1 */
4306 x86_branch8 (code, X86_CC_P, 0, FALSE);
4307 /* branch if C0=0 */
4308 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4309 x86_patch (br1, code);
4312 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4313 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4314 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4317 /* Branch if C013 != 001 */
4318 if (cfg->opt & MONO_OPT_FCMOV) {
4319 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4320 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4323 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4324 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4328 x86_push_reg (code, X86_EAX);
4331 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4332 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4333 x86_pop_reg (code, X86_EAX);
4335 /* Have to clean up the fp stack before throwing the exception */
4337 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4340 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4342 x86_patch (br1, code);
4346 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4349 case OP_TLS_GET_REG: {
4350 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4354 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4357 case OP_TLS_SET_REG: {
4358 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4361 case OP_MEMORY_BARRIER: {
4362 /* x86 only needs barrier for StoreLoad and FullBarrier */
4363 switch (ins->backend.memory_barrier_kind) {
4364 case StoreLoadBarrier:
4366 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4367 x86_prefix (code, X86_LOCK_PREFIX);
4368 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4373 case OP_ATOMIC_ADD_I4: {
4374 int dreg = ins->dreg;
4376 g_assert (cfg->has_atomic_add_i4);
4378 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4379 if (ins->sreg2 == dreg) {
4380 if (dreg == X86_EBX) {
4382 if (ins->inst_basereg == X86_EDI)
4386 if (ins->inst_basereg == X86_EBX)
4389 } else if (ins->inst_basereg == dreg) {
4390 if (dreg == X86_EBX) {
4392 if (ins->sreg2 == X86_EDI)
4396 if (ins->sreg2 == X86_EBX)
4401 if (dreg != ins->dreg) {
4402 x86_push_reg (code, dreg);
4405 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4406 x86_prefix (code, X86_LOCK_PREFIX);
4407 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4408 /* dreg contains the old value, add with sreg2 value */
4409 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4411 if (ins->dreg != dreg) {
4412 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4413 x86_pop_reg (code, dreg);
4418 case OP_ATOMIC_EXCHANGE_I4: {
4420 int sreg2 = ins->sreg2;
4421 int breg = ins->inst_basereg;
4423 g_assert (cfg->has_atomic_exchange_i4);
4425 /* cmpxchg uses eax as comperand, need to make sure we can use it
4426 * hack to overcome limits in x86 reg allocator
4427 * (req: dreg == eax and sreg2 != eax and breg != eax)
4429 g_assert (ins->dreg == X86_EAX);
4431 /* We need the EAX reg for the cmpxchg */
4432 if (ins->sreg2 == X86_EAX) {
4433 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4434 x86_push_reg (code, sreg2);
4435 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4438 if (breg == X86_EAX) {
4439 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4440 x86_push_reg (code, breg);
4441 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4444 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4446 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4447 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4448 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4449 x86_patch (br [1], br [0]);
4451 if (breg != ins->inst_basereg)
4452 x86_pop_reg (code, breg);
4454 if (ins->sreg2 != sreg2)
4455 x86_pop_reg (code, sreg2);
4459 case OP_ATOMIC_CAS_I4: {
4460 g_assert (ins->dreg == X86_EAX);
4461 g_assert (ins->sreg3 == X86_EAX);
4462 g_assert (ins->sreg1 != X86_EAX);
4463 g_assert (ins->sreg1 != ins->sreg2);
4465 x86_prefix (code, X86_LOCK_PREFIX);
4466 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4469 case OP_CARD_TABLE_WBARRIER: {
4470 int ptr = ins->sreg1;
4471 int value = ins->sreg2;
4473 int nursery_shift, card_table_shift;
4474 gpointer card_table_mask;
4475 size_t nursery_size;
4476 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4477 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4478 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4481 * We need one register we can clobber, we choose EDX and make sreg1
4482 * fixed EAX to work around limitations in the local register allocator.
4483 * sreg2 might get allocated to EDX, but that is not a problem since
4484 * we use it before clobbering EDX.
4486 g_assert (ins->sreg1 == X86_EAX);
4489 * This is the code we produce:
4492 * edx >>= nursery_shift
4493 * cmp edx, (nursery_start >> nursery_shift)
4496 * edx >>= card_table_shift
4497 * card_table[edx] = 1
4501 if (card_table_nursery_check) {
4502 if (value != X86_EDX)
4503 x86_mov_reg_reg (code, X86_EDX, value, 4);
4504 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4505 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4506 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4508 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4509 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4510 if (card_table_mask)
4511 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4512 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4513 if (card_table_nursery_check)
4514 x86_patch (br, code);
4517 #ifdef MONO_ARCH_SIMD_INTRINSICS
4519 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4522 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4525 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4528 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4531 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4534 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4537 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4538 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4541 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4544 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4547 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4550 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4553 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4556 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4559 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4562 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4565 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4568 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4571 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4574 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4577 case OP_PSHUFLEW_HIGH:
4578 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4579 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4581 case OP_PSHUFLEW_LOW:
4582 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4583 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4586 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4587 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4590 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4591 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4594 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4595 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4599 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4602 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4605 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4608 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4611 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4614 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4617 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4618 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4621 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4624 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4627 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4630 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4633 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4636 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4639 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4642 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4645 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4648 case OP_EXTRACT_MASK:
4649 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4653 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4656 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4659 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4663 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4666 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4669 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4672 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4676 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4679 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4682 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4685 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4689 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4692 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4695 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4699 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4702 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4705 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4709 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4712 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4716 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4719 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4722 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4726 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4729 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4732 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4736 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4739 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4742 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4745 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4749 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4752 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4755 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4758 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4761 case OP_PSUM_ABS_DIFF:
4762 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4765 case OP_UNPACK_LOWB:
4766 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4768 case OP_UNPACK_LOWW:
4769 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4771 case OP_UNPACK_LOWD:
4772 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4774 case OP_UNPACK_LOWQ:
4775 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4777 case OP_UNPACK_LOWPS:
4778 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4780 case OP_UNPACK_LOWPD:
4781 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4784 case OP_UNPACK_HIGHB:
4785 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4787 case OP_UNPACK_HIGHW:
4788 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4790 case OP_UNPACK_HIGHD:
4791 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4793 case OP_UNPACK_HIGHQ:
4794 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4796 case OP_UNPACK_HIGHPS:
4797 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4799 case OP_UNPACK_HIGHPD:
4800 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4804 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4807 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4810 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4813 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4816 case OP_PADDB_SAT_UN:
4817 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4819 case OP_PSUBB_SAT_UN:
4820 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4822 case OP_PADDW_SAT_UN:
4823 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4825 case OP_PSUBW_SAT_UN:
4826 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4830 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4833 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4836 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4839 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4843 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4846 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4849 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4851 case OP_PMULW_HIGH_UN:
4852 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4855 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4859 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4862 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4866 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4869 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4873 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4876 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4880 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4883 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4887 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4890 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4894 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4897 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4901 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4904 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4908 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4911 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4915 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4918 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4922 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4924 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4925 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4929 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4931 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4932 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4936 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4938 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4939 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4943 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4945 case OP_EXTRACTX_U2:
4946 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4948 case OP_INSERTX_U1_SLOW:
4949 /*sreg1 is the extracted ireg (scratch)
4950 /sreg2 is the to be inserted ireg (scratch)
4951 /dreg is the xreg to receive the value*/
4953 /*clear the bits from the extracted word*/
4954 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4955 /*shift the value to insert if needed*/
4956 if (ins->inst_c0 & 1)
4957 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4958 /*join them together*/
4959 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4960 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4962 case OP_INSERTX_I4_SLOW:
4963 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4964 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4965 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4968 case OP_INSERTX_R4_SLOW:
4969 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4970 /*TODO if inst_c0 == 0 use movss*/
4971 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4972 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4974 case OP_INSERTX_R8_SLOW:
4975 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4976 if (cfg->verbose_level)
4977 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4979 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4981 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4984 case OP_STOREX_MEMBASE_REG:
4985 case OP_STOREX_MEMBASE:
4986 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4988 case OP_LOADX_MEMBASE:
4989 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4991 case OP_LOADX_ALIGNED_MEMBASE:
4992 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4994 case OP_STOREX_ALIGNED_MEMBASE_REG:
4995 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4997 case OP_STOREX_NTA_MEMBASE_REG:
4998 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
5000 case OP_PREFETCH_MEMBASE:
5001 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5005 /*FIXME the peephole pass should have killed this*/
5006 if (ins->dreg != ins->sreg1)
5007 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5010 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
5012 case OP_ICONV_TO_R8_RAW:
5013 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
5014 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
5017 case OP_FCONV_TO_R8_X:
5018 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
5019 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5022 case OP_XCONV_R8_TO_I4:
5023 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
5024 switch (ins->backend.source_opcode) {
5025 case OP_FCONV_TO_I1:
5026 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5028 case OP_FCONV_TO_U1:
5029 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5031 case OP_FCONV_TO_I2:
5032 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5034 case OP_FCONV_TO_U2:
5035 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5041 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
5042 /*The +4 is to get a mov ?h, ?l over the same reg.*/
5043 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
5044 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
5045 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
5046 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5049 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
5050 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
5051 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5054 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
5055 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5058 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
5059 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5060 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5063 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
5064 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5065 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
5069 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
5072 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
5075 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
5078 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
5081 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
5084 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
5087 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
5090 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
5094 case OP_LIVERANGE_START: {
5095 if (cfg->verbose_level > 1)
5096 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5097 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5100 case OP_LIVERANGE_END: {
5101 if (cfg->verbose_level > 1)
5102 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5103 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5106 case OP_NACL_GC_SAFE_POINT: {
5107 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
5108 if (cfg->compile_aot)
5109 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5113 x86_test_mem_imm8 (code, (gpointer)&__nacl_thread_suspension_needed, 0xFFFFFFFF);
5114 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
5115 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5116 x86_patch (br[0], code);
5121 case OP_GC_LIVENESS_DEF:
5122 case OP_GC_LIVENESS_USE:
5123 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5124 ins->backend.pc_offset = code - cfg->native_code;
5126 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5127 ins->backend.pc_offset = code - cfg->native_code;
5128 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5131 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
5134 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
5137 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
5138 g_assert_not_reached ();
5141 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
5142 #ifndef __native_client_codegen__
5143 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5144 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5145 g_assert_not_reached ();
5146 #endif /* __native_client_codegen__ */
5152 cfg->code_len = code - cfg->native_code;
5155 #endif /* DISABLE_JIT */
5158 mono_arch_register_lowlevel_calls (void)
5163 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
5165 MonoJumpInfo *patch_info;
5166 gboolean compile_aot = !run_cctors;
5168 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5169 unsigned char *ip = patch_info->ip.i + code;
5170 const unsigned char *target;
5173 switch (patch_info->type) {
5174 case MONO_PATCH_INFO_BB:
5175 case MONO_PATCH_INFO_LABEL:
5178 /* No need to patch these */
5183 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5185 switch (patch_info->type) {
5186 case MONO_PATCH_INFO_IP:
5187 *((gconstpointer *)(ip)) = target;
5189 case MONO_PATCH_INFO_CLASS_INIT: {
5191 /* Might already been changed to a nop */
5192 x86_call_code (code, 0);
5193 x86_patch (ip, target);
5196 case MONO_PATCH_INFO_ABS:
5197 case MONO_PATCH_INFO_METHOD:
5198 case MONO_PATCH_INFO_METHOD_JUMP:
5199 case MONO_PATCH_INFO_INTERNAL_METHOD:
5200 case MONO_PATCH_INFO_BB:
5201 case MONO_PATCH_INFO_LABEL:
5202 case MONO_PATCH_INFO_RGCTX_FETCH:
5203 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
5204 case MONO_PATCH_INFO_MONITOR_ENTER:
5205 case MONO_PATCH_INFO_MONITOR_EXIT:
5206 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5207 #if defined(__native_client_codegen__) && defined(__native_client__)
5208 if (nacl_is_code_address (code)) {
5209 /* For tail calls, code is patched after being installed */
5210 /* but not through the normal "patch callsite" method. */
5211 unsigned char buf[kNaClAlignment];
5212 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5213 unsigned char *_target = target;
5215 /* All patch targets modified in x86_patch */
5216 /* are IP relative. */
5217 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5218 memcpy (buf, aligned_code, kNaClAlignment);
5219 /* Patch a temp buffer of bundle size, */
5220 /* then install to actual location. */
5221 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5222 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5223 g_assert (ret == 0);
5226 x86_patch (ip, target);
5229 x86_patch (ip, target);
5232 case MONO_PATCH_INFO_NONE:
5234 case MONO_PATCH_INFO_R4:
5235 case MONO_PATCH_INFO_R8: {
5236 guint32 offset = mono_arch_get_patch_offset (ip);
5237 *((gconstpointer *)(ip + offset)) = target;
5241 guint32 offset = mono_arch_get_patch_offset (ip);
5242 #if !defined(__native_client__)
5243 *((gconstpointer *)(ip + offset)) = target;
5245 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5253 static G_GNUC_UNUSED void
5254 stack_unaligned (MonoMethod *m, gpointer caller)
5256 printf ("%s\n", mono_method_full_name (m, TRUE));
5257 g_assert_not_reached ();
5261 mono_arch_emit_prolog (MonoCompile *cfg)
5263 MonoMethod *method = cfg->method;
5265 MonoMethodSignature *sig;
5267 int alloc_size, pos, max_offset, i, cfa_offset;
5269 gboolean need_stack_frame;
5270 #ifdef __native_client_codegen__
5271 guint alignment_check;
5274 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5276 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5277 cfg->code_size += 512;
5279 #if defined(__default_codegen__)
5280 code = cfg->native_code = g_malloc (cfg->code_size);
5281 #elif defined(__native_client_codegen__)
5282 /* native_code_alloc is not 32-byte aligned, native_code is. */
5283 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5284 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5286 /* Align native_code to next nearest kNaclAlignment byte. */
5287 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5288 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5290 code = cfg->native_code;
5292 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5293 g_assert(alignment_check == 0);
5300 /* Check that the stack is aligned on osx */
5301 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5302 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5303 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5305 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5306 x86_push_membase (code, X86_ESP, 0);
5307 x86_push_imm (code, cfg->method);
5308 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5309 x86_call_reg (code, X86_EAX);
5310 x86_patch (br [0], code);
5314 /* Offset between RSP and the CFA */
5318 cfa_offset = sizeof (gpointer);
5319 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5320 // IP saved at CFA - 4
5321 /* There is no IP reg on x86 */
5322 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5323 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5325 need_stack_frame = needs_stack_frame (cfg);
5327 if (need_stack_frame) {
5328 x86_push_reg (code, X86_EBP);
5329 cfa_offset += sizeof (gpointer);
5330 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5331 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5332 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5333 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5334 /* These are handled automatically by the stack marking code */
5335 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5337 cfg->frame_reg = X86_ESP;
5340 if (cfg->arch.no_pushes) {
5341 cfg->stack_offset += cfg->param_area;
5342 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5345 alloc_size = cfg->stack_offset;
5348 if (!method->save_lmf) {
5349 if (cfg->used_int_regs & (1 << X86_EBX)) {
5350 x86_push_reg (code, X86_EBX);
5352 cfa_offset += sizeof (gpointer);
5353 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5354 /* These are handled automatically by the stack marking code */
5355 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5358 if (cfg->used_int_regs & (1 << X86_EDI)) {
5359 x86_push_reg (code, X86_EDI);
5361 cfa_offset += sizeof (gpointer);
5362 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5363 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5366 if (cfg->used_int_regs & (1 << X86_ESI)) {
5367 x86_push_reg (code, X86_ESI);
5369 cfa_offset += sizeof (gpointer);
5370 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5371 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5377 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5378 if (mono_do_x86_stack_align && need_stack_frame) {
5379 int tot = alloc_size + pos + 4; /* ret ip */
5380 if (need_stack_frame)
5382 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5384 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5385 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5386 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5390 cfg->arch.sp_fp_offset = alloc_size + pos;
5393 /* See mono_emit_stack_alloc */
5394 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5395 guint32 remaining_size = alloc_size;
5396 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5397 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5398 guint32 offset = code - cfg->native_code;
5399 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5400 while (required_code_size >= (cfg->code_size - offset))
5401 cfg->code_size *= 2;
5402 cfg->native_code = mono_realloc_native_code(cfg);
5403 code = cfg->native_code + offset;
5404 cfg->stat_code_reallocs++;
5406 while (remaining_size >= 0x1000) {
5407 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5408 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5409 remaining_size -= 0x1000;
5412 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5414 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5417 g_assert (need_stack_frame);
5420 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5421 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5422 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5425 #if DEBUG_STACK_ALIGNMENT
5426 /* check the stack is aligned */
5427 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5428 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5429 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5430 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5431 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5432 x86_breakpoint (code);
5436 /* compute max_offset in order to use short forward jumps */
5438 if (cfg->opt & MONO_OPT_BRANCH) {
5439 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5441 bb->max_offset = max_offset;
5443 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5445 /* max alignment for loops */
5446 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5447 max_offset += LOOP_ALIGNMENT;
5448 #ifdef __native_client_codegen__
5449 /* max alignment for native client */
5450 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5451 max_offset += kNaClAlignment;
5453 MONO_BB_FOR_EACH_INS (bb, ins) {
5454 if (ins->opcode == OP_LABEL)
5455 ins->inst_c1 = max_offset;
5456 #ifdef __native_client_codegen__
5457 switch (ins->opcode)
5469 case OP_VOIDCALL_REG:
5471 case OP_FCALL_MEMBASE:
5472 case OP_LCALL_MEMBASE:
5473 case OP_VCALL_MEMBASE:
5474 case OP_VCALL2_MEMBASE:
5475 case OP_VOIDCALL_MEMBASE:
5476 case OP_CALL_MEMBASE:
5477 max_offset += kNaClAlignment;
5480 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5483 #endif /* __native_client_codegen__ */
5484 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5489 /* store runtime generic context */
5490 if (cfg->rgctx_var) {
5491 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5493 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5496 if (method->save_lmf)
5497 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5499 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5500 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5502 /* load arguments allocated to register from the stack */
5503 sig = mono_method_signature (method);
5506 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5507 inst = cfg->args [pos];
5508 if (inst->opcode == OP_REGVAR) {
5509 g_assert (need_stack_frame);
5510 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5511 if (cfg->verbose_level > 2)
5512 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5517 cfg->code_len = code - cfg->native_code;
5519 g_assert (cfg->code_len < cfg->code_size);
5525 mono_arch_emit_epilog (MonoCompile *cfg)
5527 MonoMethod *method = cfg->method;
5528 MonoMethodSignature *sig = mono_method_signature (method);
5530 guint32 stack_to_pop;
5532 int max_epilog_size = 16;
5534 gboolean need_stack_frame = needs_stack_frame (cfg);
5536 if (cfg->method->save_lmf)
5537 max_epilog_size += 128;
5539 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5540 cfg->code_size *= 2;
5541 cfg->native_code = mono_realloc_native_code(cfg);
5542 cfg->stat_code_reallocs++;
5545 code = cfg->native_code + cfg->code_len;
5547 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5548 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5550 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5553 if (method->save_lmf) {
5554 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5556 gboolean supported = FALSE;
5558 if (cfg->compile_aot) {
5559 #if defined(__APPLE__) || defined(__linux__)
5562 } else if (mono_get_jit_tls_offset () != -1) {
5566 /* check if we need to restore protection of the stack after a stack overflow */
5568 if (cfg->compile_aot) {
5569 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5571 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5573 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5576 /* we load the value in a separate instruction: this mechanism may be
5577 * used later as a safer way to do thread interruption
5579 x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5580 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5582 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5583 /* note that the call trampoline will preserve eax/edx */
5584 x86_call_reg (code, X86_ECX);
5585 x86_patch (patch, code);
5587 /* FIXME: maybe save the jit tls in the prolog */
5590 /* restore caller saved regs */
5591 if (cfg->used_int_regs & (1 << X86_EBX)) {
5592 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5595 if (cfg->used_int_regs & (1 << X86_EDI)) {
5596 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5598 if (cfg->used_int_regs & (1 << X86_ESI)) {
5599 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5602 /* EBP is restored by LEAVE */
5604 for (i = 0; i < X86_NREG; ++i) {
5605 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5611 g_assert (need_stack_frame);
5612 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5616 g_assert (need_stack_frame);
5617 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5620 if (cfg->used_int_regs & (1 << X86_ESI)) {
5621 x86_pop_reg (code, X86_ESI);
5623 if (cfg->used_int_regs & (1 << X86_EDI)) {
5624 x86_pop_reg (code, X86_EDI);
5626 if (cfg->used_int_regs & (1 << X86_EBX)) {
5627 x86_pop_reg (code, X86_EBX);
5631 /* Load returned vtypes into registers if needed */
5632 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5633 if (cinfo->ret.storage == ArgValuetypeInReg) {
5634 for (quad = 0; quad < 2; quad ++) {
5635 switch (cinfo->ret.pair_storage [quad]) {
5637 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5639 case ArgOnFloatFpStack:
5640 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5642 case ArgOnDoubleFpStack:
5643 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5648 g_assert_not_reached ();
5653 if (need_stack_frame)
5656 if (CALLCONV_IS_STDCALL (sig)) {
5657 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5659 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5660 } else if (cinfo->callee_stack_pop)
5661 stack_to_pop = cinfo->callee_stack_pop;
5666 g_assert (need_stack_frame);
5667 x86_ret_imm (code, stack_to_pop);
5672 cfg->code_len = code - cfg->native_code;
5674 g_assert (cfg->code_len < cfg->code_size);
5678 mono_arch_emit_exceptions (MonoCompile *cfg)
5680 MonoJumpInfo *patch_info;
5683 MonoClass *exc_classes [16];
5684 guint8 *exc_throw_start [16], *exc_throw_end [16];
5688 /* Compute needed space */
5689 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5690 if (patch_info->type == MONO_PATCH_INFO_EXC)
5695 * make sure we have enough space for exceptions
5696 * 16 is the size of two push_imm instructions and a call
5698 if (cfg->compile_aot)
5699 code_size = exc_count * 32;
5701 code_size = exc_count * 16;
5703 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5704 cfg->code_size *= 2;
5705 cfg->native_code = mono_realloc_native_code(cfg);
5706 cfg->stat_code_reallocs++;
5709 code = cfg->native_code + cfg->code_len;
5712 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5713 switch (patch_info->type) {
5714 case MONO_PATCH_INFO_EXC: {
5715 MonoClass *exc_class;
5719 x86_patch (patch_info->ip.i + cfg->native_code, code);
5721 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5722 g_assert (exc_class);
5723 throw_ip = patch_info->ip.i;
5725 /* Find a throw sequence for the same exception class */
5726 for (i = 0; i < nthrows; ++i)
5727 if (exc_classes [i] == exc_class)
5730 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5731 x86_jump_code (code, exc_throw_start [i]);
5732 patch_info->type = MONO_PATCH_INFO_NONE;
5737 /* Compute size of code following the push <OFFSET> */
5738 #if defined(__default_codegen__)
5740 #elif defined(__native_client_codegen__)
5741 code = mono_nacl_align (code);
5742 size = kNaClAlignment;
5744 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5746 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5747 /* Use the shorter form */
5749 x86_push_imm (code, 0);
5753 x86_push_imm (code, 0xf0f0f0f0);
5758 exc_classes [nthrows] = exc_class;
5759 exc_throw_start [nthrows] = code;
5762 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5763 patch_info->data.name = "mono_arch_throw_corlib_exception";
5764 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5765 patch_info->ip.i = code - cfg->native_code;
5766 x86_call_code (code, 0);
5767 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5772 exc_throw_end [nthrows] = code;
5784 cfg->code_len = code - cfg->native_code;
5786 g_assert (cfg->code_len < cfg->code_size);
5790 mono_arch_flush_icache (guint8 *code, gint size)
5796 mono_arch_flush_register_windows (void)
5801 mono_arch_is_inst_imm (gint64 imm)
5807 mono_arch_finish_init (void)
5809 if (!g_getenv ("MONO_NO_TLS")) {
5810 #ifndef TARGET_WIN32
5812 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5819 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5823 #ifdef MONO_ARCH_HAVE_IMT
5825 // Linear handler, the bsearch head compare is shorter
5826 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5827 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5828 // x86_patch(ins,target)
5829 //[1 + 5] x86_jump_mem(inst,mem)
5832 #if defined(__default_codegen__)
5833 #define BR_SMALL_SIZE 2
5834 #define BR_LARGE_SIZE 5
5835 #elif defined(__native_client_codegen__)
5836 /* I suspect the size calculation below is actually incorrect. */
5837 /* TODO: fix the calculation that uses these sizes. */
5838 #define BR_SMALL_SIZE 16
5839 #define BR_LARGE_SIZE 12
5840 #endif /*__native_client_codegen__*/
5841 #define JUMP_IMM_SIZE 6
5842 #define ENABLE_WRONG_METHOD_CHECK 0
5846 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5848 int i, distance = 0;
5849 for (i = start; i < target; ++i)
5850 distance += imt_entries [i]->chunk_size;
5855 * LOCKING: called with the domain lock held
5858 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5859 gpointer fail_tramp)
5863 guint8 *code, *start;
5865 for (i = 0; i < count; ++i) {
5866 MonoIMTCheckItem *item = imt_entries [i];
5867 if (item->is_equals) {
5868 if (item->check_target_idx) {
5869 if (!item->compare_done)
5870 item->chunk_size += CMP_SIZE;
5871 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5874 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5876 item->chunk_size += JUMP_IMM_SIZE;
5877 #if ENABLE_WRONG_METHOD_CHECK
5878 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5883 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5884 imt_entries [item->check_target_idx]->compare_done = TRUE;
5886 size += item->chunk_size;
5888 #if defined(__native_client__) && defined(__native_client_codegen__)
5889 /* In Native Client, we don't re-use thunks, allocate from the */
5890 /* normal code manager paths. */
5891 size = NACL_BUNDLE_ALIGN_UP (size);
5892 code = mono_domain_code_reserve (domain, size);
5895 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5897 code = mono_domain_code_reserve (domain, size);
5900 for (i = 0; i < count; ++i) {
5901 MonoIMTCheckItem *item = imt_entries [i];
5902 item->code_target = code;
5903 if (item->is_equals) {
5904 if (item->check_target_idx) {
5905 if (!item->compare_done)
5906 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5907 item->jmp_code = code;
5908 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5909 if (item->has_target_code)
5910 x86_jump_code (code, item->value.target_code);
5912 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5915 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5916 item->jmp_code = code;
5917 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5918 if (item->has_target_code)
5919 x86_jump_code (code, item->value.target_code);
5921 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5922 x86_patch (item->jmp_code, code);
5923 x86_jump_code (code, fail_tramp);
5924 item->jmp_code = NULL;
5926 /* enable the commented code to assert on wrong method */
5927 #if ENABLE_WRONG_METHOD_CHECK
5928 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5929 item->jmp_code = code;
5930 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5932 if (item->has_target_code)
5933 x86_jump_code (code, item->value.target_code);
5935 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5936 #if ENABLE_WRONG_METHOD_CHECK
5937 x86_patch (item->jmp_code, code);
5938 x86_breakpoint (code);
5939 item->jmp_code = NULL;
5944 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5945 item->jmp_code = code;
5946 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5947 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5949 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5952 /* patch the branches to get to the target items */
5953 for (i = 0; i < count; ++i) {
5954 MonoIMTCheckItem *item = imt_entries [i];
5955 if (item->jmp_code) {
5956 if (item->check_target_idx) {
5957 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5963 mono_stats.imt_thunks_size += code - start;
5964 g_assert (code - start <= size);
5968 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5969 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5973 if (mono_jit_map_is_enabled ()) {
5976 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5978 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5979 mono_emit_jit_tramp (start, code - start, buff);
5983 nacl_domain_code_validate (domain, &start, size, &code);
5989 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5991 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5996 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5998 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6002 mono_arch_get_cie_program (void)
6006 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
6007 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
6013 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6015 MonoInst *ins = NULL;
6018 if (cmethod->klass == mono_defaults.math_class) {
6019 if (strcmp (cmethod->name, "Sin") == 0) {
6021 } else if (strcmp (cmethod->name, "Cos") == 0) {
6023 } else if (strcmp (cmethod->name, "Tan") == 0) {
6025 } else if (strcmp (cmethod->name, "Atan") == 0) {
6027 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6029 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6031 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
6036 MONO_INST_NEW (cfg, ins, opcode);
6037 ins->type = STACK_R8;
6038 ins->dreg = mono_alloc_freg (cfg);
6039 ins->sreg1 = args [0]->dreg;
6040 MONO_ADD_INS (cfg->cbb, ins);
6043 if (cfg->opt & MONO_OPT_CMOV) {
6046 if (strcmp (cmethod->name, "Min") == 0) {
6047 if (fsig->params [0]->type == MONO_TYPE_I4)
6049 } else if (strcmp (cmethod->name, "Max") == 0) {
6050 if (fsig->params [0]->type == MONO_TYPE_I4)
6055 MONO_INST_NEW (cfg, ins, opcode);
6056 ins->type = STACK_I4;
6057 ins->dreg = mono_alloc_ireg (cfg);
6058 ins->sreg1 = args [0]->dreg;
6059 ins->sreg2 = args [1]->dreg;
6060 MONO_ADD_INS (cfg->cbb, ins);
6065 /* OP_FREM is not IEEE compatible */
6066 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6067 MONO_INST_NEW (cfg, ins, OP_FREM);
6068 ins->inst_i0 = args [0];
6069 ins->inst_i1 = args [1];
6078 mono_arch_print_tree (MonoInst *tree, int arity)
6084 mono_arch_get_patch_offset (guint8 *code)
6086 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
6088 else if (code [0] == 0xba)
6090 else if (code [0] == 0x68)
6093 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
6094 /* push <OFFSET>(<REG>) */
6096 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
6097 /* call *<OFFSET>(<REG>) */
6099 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
6102 else if ((code [0] == 0x58) && (code [1] == 0x05))
6103 /* pop %eax; add <OFFSET>, %eax */
6105 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6106 /* pop <REG>; add <OFFSET>, <REG> */
6108 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6109 /* mov <REG>, imm */
6112 g_assert_not_reached ();
6118 * mono_breakpoint_clean_code:
6120 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6121 * breakpoints in the original code, they are removed in the copy.
6123 * Returns TRUE if no sw breakpoint was present.
6126 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6129 gboolean can_write = TRUE;
6131 * If method_start is non-NULL we need to perform bound checks, since we access memory
6132 * at code - offset we could go before the start of the method and end up in a different
6133 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6136 if (!method_start || code - offset >= method_start) {
6137 memcpy (buf, code - offset, size);
6139 int diff = code - method_start;
6140 memset (buf, 0, size);
6141 memcpy (buf + offset - diff, method_start, diff + size - offset);
6144 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6145 int idx = mono_breakpoint_info_index [i];
6149 ptr = mono_breakpoint_info [idx].address;
6150 if (ptr >= code && ptr < code + size) {
6151 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6153 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6154 buf [ptr - code] = saved_byte;
6161 * mono_x86_get_this_arg_offset:
6163 * Return the offset of the stack location where this is passed during a virtual
6167 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6173 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6175 guint32 esp = regs [X86_ESP];
6176 CallInfo *cinfo = NULL;
6183 * The stack looks like:
6187 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
6189 res = (((MonoObject**)esp) [5 + (offset / 4)]);
6195 #define MAX_ARCH_DELEGATE_PARAMS 10
6198 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6200 guint8 *code, *start;
6201 int code_reserve = 64;
6204 * The stack contains:
6210 start = code = mono_global_codeman_reserve (code_reserve);
6212 /* Replace the this argument with the target */
6213 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6214 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6215 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6216 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6218 g_assert ((code - start) < code_reserve);
6221 /* 8 for mov_reg and jump, plus 8 for each parameter */
6222 #ifdef __native_client_codegen__
6223 /* TODO: calculate this size correctly */
6224 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6226 code_reserve = 8 + (param_count * 8);
6227 #endif /* __native_client_codegen__ */
6229 * The stack contains:
6230 * <args in reverse order>
6235 * <args in reverse order>
6238 * without unbalancing the stack.
6239 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6240 * and leaving original spot of first arg as placeholder in stack so
6241 * when callee pops stack everything works.
6244 start = code = mono_global_codeman_reserve (code_reserve);
6246 /* store delegate for access to method_ptr */
6247 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6250 for (i = 0; i < param_count; ++i) {
6251 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6252 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6255 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6257 g_assert ((code - start) < code_reserve);
6260 nacl_global_codeman_validate(&start, code_reserve, &code);
6261 mono_debug_add_delegate_trampoline (start, code - start);
6264 *code_len = code - start;
6266 if (mono_jit_map_is_enabled ()) {
6269 buff = (char*)"delegate_invoke_has_target";
6271 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6272 mono_emit_jit_tramp (start, code - start, buff);
6281 mono_arch_get_delegate_invoke_impls (void)
6289 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6290 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
6292 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6293 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6294 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
6295 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
6296 g_free (tramp_name);
6303 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6305 guint8 *code, *start;
6307 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6310 /* FIXME: Support more cases */
6311 if (MONO_TYPE_ISSTRUCT (sig->ret))
6315 * The stack contains:
6321 static guint8* cached = NULL;
6326 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6328 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6330 mono_memory_barrier ();
6334 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6337 for (i = 0; i < sig->param_count; ++i)
6338 if (!mono_is_regsize_var (sig->params [i]))
6341 code = cache [sig->param_count];
6345 if (mono_aot_only) {
6346 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6347 start = mono_aot_get_trampoline (name);
6350 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6353 mono_memory_barrier ();
6355 cache [sig->param_count] = start;
6362 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6365 case X86_EAX: return ctx->eax;
6366 case X86_EBX: return ctx->ebx;
6367 case X86_ECX: return ctx->ecx;
6368 case X86_EDX: return ctx->edx;
6369 case X86_ESP: return ctx->esp;
6370 case X86_EBP: return ctx->ebp;
6371 case X86_ESI: return ctx->esi;
6372 case X86_EDI: return ctx->edi;
6374 g_assert_not_reached ();
6380 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6408 g_assert_not_reached ();
6412 #ifdef MONO_ARCH_SIMD_INTRINSICS
6415 get_float_to_x_spill_area (MonoCompile *cfg)
6417 if (!cfg->fconv_to_r8_x_var) {
6418 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6419 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6421 return cfg->fconv_to_r8_x_var;
6425 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6428 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6431 int dreg, src_opcode;
6433 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6436 switch (src_opcode = ins->opcode) {
6437 case OP_FCONV_TO_I1:
6438 case OP_FCONV_TO_U1:
6439 case OP_FCONV_TO_I2:
6440 case OP_FCONV_TO_U2:
6441 case OP_FCONV_TO_I4:
6448 /* dreg is the IREG and sreg1 is the FREG */
6449 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6450 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6451 fconv->sreg1 = ins->sreg1;
6452 fconv->dreg = mono_alloc_ireg (cfg);
6453 fconv->type = STACK_VTYPE;
6454 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6456 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6460 ins->opcode = OP_XCONV_R8_TO_I4;
6462 ins->klass = mono_defaults.int32_class;
6463 ins->sreg1 = fconv->dreg;
6465 ins->type = STACK_I4;
6466 ins->backend.source_opcode = src_opcode;
6469 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6472 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6477 if (long_ins->opcode == OP_LNEG) {
6479 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6480 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6481 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6486 #ifdef MONO_ARCH_SIMD_INTRINSICS
6488 if (!(cfg->opt & MONO_OPT_SIMD))
6491 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6492 switch (long_ins->opcode) {
6494 vreg = long_ins->sreg1;
6496 if (long_ins->inst_c0) {
6497 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6498 ins->klass = long_ins->klass;
6499 ins->sreg1 = long_ins->sreg1;
6501 ins->type = STACK_VTYPE;
6502 ins->dreg = vreg = alloc_ireg (cfg);
6503 MONO_ADD_INS (cfg->cbb, ins);
6506 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6507 ins->klass = mono_defaults.int32_class;
6509 ins->type = STACK_I4;
6510 ins->dreg = long_ins->dreg + 1;
6511 MONO_ADD_INS (cfg->cbb, ins);
6513 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6514 ins->klass = long_ins->klass;
6515 ins->sreg1 = long_ins->sreg1;
6516 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6517 ins->type = STACK_VTYPE;
6518 ins->dreg = vreg = alloc_ireg (cfg);
6519 MONO_ADD_INS (cfg->cbb, ins);
6521 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6522 ins->klass = mono_defaults.int32_class;
6524 ins->type = STACK_I4;
6525 ins->dreg = long_ins->dreg + 2;
6526 MONO_ADD_INS (cfg->cbb, ins);
6528 long_ins->opcode = OP_NOP;
6530 case OP_INSERTX_I8_SLOW:
6531 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6532 ins->dreg = long_ins->dreg;
6533 ins->sreg1 = long_ins->dreg;
6534 ins->sreg2 = long_ins->sreg2 + 1;
6535 ins->inst_c0 = long_ins->inst_c0 * 2;
6536 MONO_ADD_INS (cfg->cbb, ins);
6538 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6539 ins->dreg = long_ins->dreg;
6540 ins->sreg1 = long_ins->dreg;
6541 ins->sreg2 = long_ins->sreg2 + 2;
6542 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6543 MONO_ADD_INS (cfg->cbb, ins);
6545 long_ins->opcode = OP_NOP;
6548 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6549 ins->dreg = long_ins->dreg;
6550 ins->sreg1 = long_ins->sreg1 + 1;
6551 ins->klass = long_ins->klass;
6552 ins->type = STACK_VTYPE;
6553 MONO_ADD_INS (cfg->cbb, ins);
6555 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6556 ins->dreg = long_ins->dreg;
6557 ins->sreg1 = long_ins->dreg;
6558 ins->sreg2 = long_ins->sreg1 + 2;
6560 ins->klass = long_ins->klass;
6561 ins->type = STACK_VTYPE;
6562 MONO_ADD_INS (cfg->cbb, ins);
6564 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6565 ins->dreg = long_ins->dreg;
6566 ins->sreg1 = long_ins->dreg;;
6567 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6568 ins->klass = long_ins->klass;
6569 ins->type = STACK_VTYPE;
6570 MONO_ADD_INS (cfg->cbb, ins);
6572 long_ins->opcode = OP_NOP;
6575 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6578 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6580 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6583 gpointer *sp, old_value;
6586 offset = clause->exvar_offset;
6589 bp = MONO_CONTEXT_GET_BP (ctx);
6590 sp = *(gpointer*)(bp + offset);
6593 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6602 * mono_aot_emit_load_got_addr:
6604 * Emit code to load the got address.
6605 * On x86, the result is placed into EBX.
6608 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6610 x86_call_imm (code, 0);
6612 * The patch needs to point to the pop, since the GOT offset needs
6613 * to be added to that address.
6616 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6618 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6619 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6620 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6626 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6629 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6631 g_assert_not_reached ();
6632 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6637 * mono_arch_emit_load_aotconst:
6639 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6640 * TARGET from the mscorlib GOT in full-aot code.
6641 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6645 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6647 /* Load the mscorlib got address */
6648 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6649 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6650 /* arch_emit_got_access () patches this */
6651 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6656 /* Can't put this into mini-x86.h */
6658 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6661 mono_arch_get_trampolines (gboolean aot)
6663 MonoTrampInfo *info;
6664 GSList *tramps = NULL;
6666 mono_x86_get_signal_exception_trampoline (&info, aot);
6668 tramps = g_slist_append (tramps, info);
6675 #define DBG_SIGNAL SIGBUS
6677 #define DBG_SIGNAL SIGSEGV
6680 /* Soft Debug support */
6681 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6684 * mono_arch_set_breakpoint:
6686 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6687 * The location should contain code emitted by OP_SEQ_POINT.
6690 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6695 * In production, we will use int3 (has to fix the size in the md
6696 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6699 g_assert (code [0] == 0x90);
6700 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6704 * mono_arch_clear_breakpoint:
6706 * Clear the breakpoint at IP.
6709 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6714 for (i = 0; i < 6; ++i)
6719 * mono_arch_start_single_stepping:
6721 * Start single stepping.
6724 mono_arch_start_single_stepping (void)
6726 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6730 * mono_arch_stop_single_stepping:
6732 * Stop single stepping.
6735 mono_arch_stop_single_stepping (void)
6737 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6741 * mono_arch_is_single_step_event:
6743 * Return whenever the machine state in SIGCTX corresponds to a single
6747 mono_arch_is_single_step_event (void *info, void *sigctx)
6750 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6752 if (((gpointer)einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6757 siginfo_t* sinfo = (siginfo_t*) info;
6758 /* Sometimes the address is off by 4 */
6759 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6767 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6770 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6771 if (((gpointer)einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6776 siginfo_t* sinfo = (siginfo_t*)info;
6777 /* Sometimes the address is off by 4 */
6778 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6785 #define BREAKPOINT_SIZE 6
6788 * mono_arch_skip_breakpoint:
6790 * See mini-amd64.c for docs.
6793 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6795 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6799 * mono_arch_skip_single_step:
6801 * See mini-amd64.c for docs.
6804 mono_arch_skip_single_step (MonoContext *ctx)
6806 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6810 * mono_arch_get_seq_point_info:
6812 * See mini-amd64.c for docs.
6815 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6822 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6824 ext->lmf.previous_lmf = (gsize)prev_lmf;
6825 /* Mark that this is a MonoLMFExt */
6826 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6827 ext->lmf.ebp = (gssize)ext;
6833 mono_arch_opcode_supported (int opcode)
6836 case OP_ATOMIC_ADD_I4:
6837 case OP_ATOMIC_EXCHANGE_I4:
6838 case OP_ATOMIC_CAS_I4:
6845 #if defined(ENABLE_GSHAREDVT)
6847 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6849 #endif /* !MONOTOUCH */