2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/appdomain.h>
21 #include <mono/metadata/debug-helpers.h>
22 #include <mono/metadata/threads.h>
23 #include <mono/metadata/profiler-private.h>
24 #include <mono/metadata/mono-debug.h>
25 #include <mono/metadata/gc-internal.h>
26 #include <mono/utils/mono-math.h>
27 #include <mono/utils/mono-counters.h>
28 #include <mono/utils/mono-mmap.h>
29 #include <mono/utils/mono-memory-model.h>
30 #include <mono/utils/mono-hwcap-x86.h>
40 static gboolean optimize_for_xen = TRUE;
42 #define optimize_for_xen 0
46 /* This mutex protects architecture specific caches */
47 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
48 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
49 static CRITICAL_SECTION mini_arch_mutex;
51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
56 /* Under windows, the default pinvoke calling convention is stdcall */
57 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
59 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
62 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
65 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
68 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
70 #ifdef __native_client_codegen__
72 /* Default alignment for Native Client is 32-byte. */
73 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
75 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
76 /* Check that alignment doesn't cross an alignment boundary. */
78 mono_arch_nacl_pad (guint8 *code, int pad)
80 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
82 if (pad == 0) return code;
83 /* assertion: alignment cannot cross a block boundary */
84 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
85 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
86 while (pad >= kMaxPadding) {
87 x86_padding (code, kMaxPadding);
90 if (pad != 0) x86_padding (code, pad);
95 mono_arch_nacl_skip_nops (guint8 *code)
101 #endif /* __native_client_codegen__ */
104 * The code generated for sequence points reads from this location, which is
105 * made read-only when single stepping is enabled.
107 static gpointer ss_trigger_page;
109 /* Enabled breakpoints read from this trigger page */
110 static gpointer bp_trigger_page;
113 mono_arch_regname (int reg)
116 case X86_EAX: return "%eax";
117 case X86_EBX: return "%ebx";
118 case X86_ECX: return "%ecx";
119 case X86_EDX: return "%edx";
120 case X86_ESP: return "%esp";
121 case X86_EBP: return "%ebp";
122 case X86_EDI: return "%edi";
123 case X86_ESI: return "%esi";
129 mono_arch_fregname (int reg)
154 mono_arch_xregname (int reg)
179 mono_x86_patch (unsigned char* code, gpointer target)
181 x86_patch (code, (unsigned char*)target);
192 /* gsharedvt argument passed by addr */
204 /* Only if storage == ArgValuetypeInReg */
205 ArgStorage pair_storage [2];
214 gboolean need_stack_align;
215 guint32 stack_align_amount;
216 gboolean vtype_retaddr;
217 /* The index of the vret arg in the argument list */
225 #define FLOAT_PARAM_REGS 0
227 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
229 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
234 switch (sig->call_convention) {
235 case MONO_CALL_THISCALL:
236 return thiscall_param_regs;
242 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
243 #define SMALL_STRUCTS_IN_REGS
244 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
248 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
250 ainfo->offset = *stack_size;
252 if (!param_regs || param_regs [*gr] == X86_NREG) {
253 ainfo->storage = ArgOnStack;
255 (*stack_size) += sizeof (gpointer);
258 ainfo->storage = ArgInIReg;
259 ainfo->reg = param_regs [*gr];
265 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
267 ainfo->offset = *stack_size;
269 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
271 ainfo->storage = ArgOnStack;
272 (*stack_size) += sizeof (gpointer) * 2;
277 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
279 ainfo->offset = *stack_size;
281 if (*gr >= FLOAT_PARAM_REGS) {
282 ainfo->storage = ArgOnStack;
283 (*stack_size) += is_double ? 8 : 4;
284 ainfo->nslots = is_double ? 2 : 1;
287 /* A double register */
289 ainfo->storage = ArgInDoubleSSEReg;
291 ainfo->storage = ArgInFloatSSEReg;
299 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
301 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
306 klass = mono_class_from_mono_type (type);
307 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
309 #ifdef SMALL_STRUCTS_IN_REGS
310 if (sig->pinvoke && is_return) {
311 MonoMarshalType *info;
314 * the exact rules are not very well documented, the code below seems to work with the
315 * code generated by gcc 3.3.3 -mno-cygwin.
317 info = mono_marshal_load_type_info (klass);
320 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
322 /* Special case structs with only a float member */
323 if (info->num_fields == 1) {
324 int ftype = mini_replace_type (info->fields [0].field->type)->type;
325 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
326 ainfo->storage = ArgValuetypeInReg;
327 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
330 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
331 ainfo->storage = ArgValuetypeInReg;
332 ainfo->pair_storage [0] = ArgOnFloatFpStack;
336 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
337 ainfo->storage = ArgValuetypeInReg;
338 ainfo->pair_storage [0] = ArgInIReg;
339 ainfo->pair_regs [0] = return_regs [0];
340 if (info->native_size > 4) {
341 ainfo->pair_storage [1] = ArgInIReg;
342 ainfo->pair_regs [1] = return_regs [1];
349 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
350 g_assert (size <= 4);
351 ainfo->storage = ArgValuetypeInReg;
352 ainfo->reg = param_regs [*gr];
357 ainfo->offset = *stack_size;
358 ainfo->storage = ArgOnStack;
359 *stack_size += ALIGN_TO (size, sizeof (gpointer));
360 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
366 * Obtain information about a call according to the calling convention.
367 * For x86 ELF, see the "System V Application Binary Interface Intel386
368 * Architecture Processor Supplment, Fourth Edition" document for more
370 * For x86 win32, see ???.
373 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
375 guint32 i, gr, fr, pstart;
376 const guint32 *param_regs;
378 int n = sig->hasthis + sig->param_count;
379 guint32 stack_size = 0;
380 gboolean is_pinvoke = sig->pinvoke;
386 param_regs = callconv_param_regs(sig);
390 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
391 switch (ret_type->type) {
392 case MONO_TYPE_BOOLEAN:
403 case MONO_TYPE_FNPTR:
404 case MONO_TYPE_CLASS:
405 case MONO_TYPE_OBJECT:
406 case MONO_TYPE_SZARRAY:
407 case MONO_TYPE_ARRAY:
408 case MONO_TYPE_STRING:
409 cinfo->ret.storage = ArgInIReg;
410 cinfo->ret.reg = X86_EAX;
414 cinfo->ret.storage = ArgInIReg;
415 cinfo->ret.reg = X86_EAX;
416 cinfo->ret.is_pair = TRUE;
419 cinfo->ret.storage = ArgOnFloatFpStack;
422 cinfo->ret.storage = ArgOnDoubleFpStack;
424 case MONO_TYPE_GENERICINST:
425 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
426 cinfo->ret.storage = ArgInIReg;
427 cinfo->ret.reg = X86_EAX;
430 if (mini_is_gsharedvt_type_gsctx (gsctx, ret_type)) {
431 cinfo->ret.storage = ArgOnStack;
432 cinfo->vtype_retaddr = TRUE;
436 case MONO_TYPE_VALUETYPE:
437 case MONO_TYPE_TYPEDBYREF: {
438 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
440 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
441 if (cinfo->ret.storage == ArgOnStack) {
442 cinfo->vtype_retaddr = TRUE;
443 /* The caller passes the address where the value is stored */
449 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ret_type));
450 cinfo->ret.storage = ArgOnStack;
451 cinfo->vtype_retaddr = TRUE;
454 cinfo->ret.storage = ArgNone;
457 g_error ("Can't handle as return value 0x%x", ret_type->type);
463 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
464 * the first argument, allowing 'this' to be always passed in the first arg reg.
465 * Also do this if the first argument is a reference type, since virtual calls
466 * are sometimes made using calli without sig->hasthis set, like in the delegate
469 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
471 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
473 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
476 cinfo->vret_arg_offset = stack_size;
477 add_general (&gr, NULL, &stack_size, &cinfo->ret);
478 cinfo->vret_arg_index = 1;
482 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
484 if (cinfo->vtype_retaddr)
485 add_general (&gr, NULL, &stack_size, &cinfo->ret);
488 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
489 fr = FLOAT_PARAM_REGS;
491 /* Emit the signature cookie just before the implicit arguments */
492 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
495 for (i = pstart; i < sig->param_count; ++i) {
496 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
499 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
500 /* We allways pass the sig cookie on the stack for simplicity */
502 * Prevent implicit arguments + the sig cookie from being passed
505 fr = FLOAT_PARAM_REGS;
507 /* Emit the signature cookie just before the implicit arguments */
508 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
511 if (sig->params [i]->byref) {
512 add_general (&gr, param_regs, &stack_size, ainfo);
515 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
516 switch (ptype->type) {
517 case MONO_TYPE_BOOLEAN:
520 add_general (&gr, param_regs, &stack_size, ainfo);
525 add_general (&gr, param_regs, &stack_size, ainfo);
529 add_general (&gr, param_regs, &stack_size, ainfo);
534 case MONO_TYPE_FNPTR:
535 case MONO_TYPE_CLASS:
536 case MONO_TYPE_OBJECT:
537 case MONO_TYPE_STRING:
538 case MONO_TYPE_SZARRAY:
539 case MONO_TYPE_ARRAY:
540 add_general (&gr, param_regs, &stack_size, ainfo);
542 case MONO_TYPE_GENERICINST:
543 if (!mono_type_generic_inst_is_valuetype (ptype)) {
544 add_general (&gr, param_regs, &stack_size, ainfo);
547 if (mini_is_gsharedvt_type_gsctx (gsctx, ptype)) {
548 /* gsharedvt arguments are passed by ref */
549 add_general (&gr, param_regs, &stack_size, ainfo);
550 g_assert (ainfo->storage == ArgOnStack);
551 ainfo->storage = ArgGSharedVt;
555 case MONO_TYPE_VALUETYPE:
556 case MONO_TYPE_TYPEDBYREF:
557 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
561 add_general_pair (&gr, param_regs, &stack_size, ainfo);
564 add_float (&fr, &stack_size, ainfo, FALSE);
567 add_float (&fr, &stack_size, ainfo, TRUE);
571 /* gsharedvt arguments are passed by ref */
572 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ptype));
573 add_general (&gr, param_regs, &stack_size, ainfo);
574 g_assert (ainfo->storage == ArgOnStack);
575 ainfo->storage = ArgGSharedVt;
578 g_error ("unexpected type 0x%x", ptype->type);
579 g_assert_not_reached ();
583 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
584 fr = FLOAT_PARAM_REGS;
586 /* Emit the signature cookie just before the implicit arguments */
587 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
590 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
591 cinfo->need_stack_align = TRUE;
592 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
593 stack_size += cinfo->stack_align_amount;
596 cinfo->stack_usage = stack_size;
597 cinfo->reg_usage = gr;
598 cinfo->freg_usage = fr;
603 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
605 int n = sig->hasthis + sig->param_count;
609 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
611 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
613 return get_call_info_internal (gsctx, cinfo, sig);
617 * mono_arch_get_argument_info:
618 * @csig: a method signature
619 * @param_count: the number of parameters to consider
620 * @arg_info: an array to store the result infos
622 * Gathers information on parameters such as size, alignment and
623 * padding. arg_info should be large enought to hold param_count + 1 entries.
625 * Returns the size of the argument area on the stack.
626 * This should be signal safe, since it is called from
627 * mono_arch_find_jit_info ().
628 * FIXME: The metadata calls might not be signal safe.
631 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
633 int len, k, args_size = 0;
639 /* Avoid g_malloc as it is not signal safe */
640 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
641 cinfo = (CallInfo*)g_newa (guint8*, len);
642 memset (cinfo, 0, len);
644 cinfo = get_call_info_internal (gsctx, cinfo, csig);
646 arg_info [0].offset = offset;
648 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
649 args_size += sizeof (gpointer);
654 args_size += sizeof (gpointer);
658 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
659 /* Emitted after this */
660 args_size += sizeof (gpointer);
664 arg_info [0].size = args_size;
666 for (k = 0; k < param_count; k++) {
667 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
669 /* ignore alignment for now */
672 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
673 arg_info [k].pad = pad;
675 arg_info [k + 1].pad = 0;
676 arg_info [k + 1].size = size;
678 arg_info [k + 1].offset = offset;
681 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
682 /* Emitted after the first arg */
683 args_size += sizeof (gpointer);
688 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
689 align = MONO_ARCH_FRAME_ALIGNMENT;
692 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
693 arg_info [k].pad = pad;
699 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
701 MonoType *callee_ret;
705 if (cfg->compile_aot && !cfg->full_aot)
706 /* OP_TAILCALL doesn't work with AOT */
709 c1 = get_call_info (NULL, NULL, caller_sig);
710 c2 = get_call_info (NULL, NULL, callee_sig);
712 * Tail calls with more callee stack usage than the caller cannot be supported, since
713 * the extra stack space would be left on the stack after the tail call.
715 res = c1->stack_usage >= c2->stack_usage;
716 callee_ret = mini_replace_type (callee_sig->ret);
717 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
718 /* An address on the callee's stack is passed as the first argument */
728 * Initialize the cpu to execute managed code.
731 mono_arch_cpu_init (void)
733 /* spec compliance requires running with double precision */
737 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
738 fpcw &= ~X86_FPCW_PRECC_MASK;
739 fpcw |= X86_FPCW_PREC_DOUBLE;
740 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
741 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
743 _control87 (_PC_53, MCW_PC);
748 * Initialize architecture specific code.
751 mono_arch_init (void)
753 InitializeCriticalSection (&mini_arch_mutex);
755 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
756 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
757 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
759 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
760 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
761 #if defined(ENABLE_GSHAREDVT)
762 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
767 * Cleanup architecture specific code.
770 mono_arch_cleanup (void)
773 mono_vfree (ss_trigger_page, mono_pagesize ());
775 mono_vfree (bp_trigger_page, mono_pagesize ());
776 DeleteCriticalSection (&mini_arch_mutex);
780 * This function returns the optimizations supported on this cpu.
783 mono_arch_cpu_optimizations (guint32 *exclude_mask)
785 #if !defined(__native_client__)
790 if (mono_hwcap_x86_has_cmov) {
791 opts |= MONO_OPT_CMOV;
793 if (mono_hwcap_x86_has_fcmov)
794 opts |= MONO_OPT_FCMOV;
796 *exclude_mask |= MONO_OPT_FCMOV;
798 *exclude_mask |= MONO_OPT_CMOV;
801 if (mono_hwcap_x86_has_sse2)
802 opts |= MONO_OPT_SSE2;
804 *exclude_mask |= MONO_OPT_SSE2;
806 #ifdef MONO_ARCH_SIMD_INTRINSICS
807 /*SIMD intrinsics require at least SSE2.*/
808 if (!mono_hwcap_x86_has_sse2)
809 *exclude_mask |= MONO_OPT_SIMD;
814 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
819 * This function test for all SSE functions supported.
821 * Returns a bitmask corresponding to all supported versions.
825 mono_arch_cpu_enumerate_simd_versions (void)
827 guint32 sse_opts = 0;
829 if (mono_hwcap_x86_has_sse1)
830 sse_opts |= SIMD_VERSION_SSE1;
832 if (mono_hwcap_x86_has_sse2)
833 sse_opts |= SIMD_VERSION_SSE2;
835 if (mono_hwcap_x86_has_sse3)
836 sse_opts |= SIMD_VERSION_SSE3;
838 if (mono_hwcap_x86_has_ssse3)
839 sse_opts |= SIMD_VERSION_SSSE3;
841 if (mono_hwcap_x86_has_sse41)
842 sse_opts |= SIMD_VERSION_SSE41;
844 if (mono_hwcap_x86_has_sse42)
845 sse_opts |= SIMD_VERSION_SSE42;
847 if (mono_hwcap_x86_has_sse4a)
848 sse_opts |= SIMD_VERSION_SSE4a;
854 * Determine whenever the trap whose info is in SIGINFO is caused by
858 mono_arch_is_int_overflow (void *sigctx, void *info)
863 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
865 ip = (guint8*)ctx.eip;
867 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
871 switch (x86_modrm_rm (ip [1])) {
891 g_assert_not_reached ();
903 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
908 for (i = 0; i < cfg->num_varinfo; i++) {
909 MonoInst *ins = cfg->varinfo [i];
910 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
913 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
916 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
917 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
920 /* we dont allocate I1 to registers because there is no simply way to sign extend
921 * 8bit quantities in caller saved registers on x86 */
922 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
923 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
924 g_assert (i == vmv->idx);
925 vars = g_list_prepend (vars, vmv);
929 vars = mono_varlist_sort (cfg, vars, 0);
935 mono_arch_get_global_int_regs (MonoCompile *cfg)
939 /* we can use 3 registers for global allocation */
940 regs = g_list_prepend (regs, (gpointer)X86_EBX);
941 regs = g_list_prepend (regs, (gpointer)X86_ESI);
942 regs = g_list_prepend (regs, (gpointer)X86_EDI);
948 * mono_arch_regalloc_cost:
950 * Return the cost, in number of memory references, of the action of
951 * allocating the variable VMV into a register during global register
955 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
957 MonoInst *ins = cfg->varinfo [vmv->idx];
959 if (cfg->method->save_lmf)
960 /* The register is already saved */
961 return (ins->opcode == OP_ARG) ? 1 : 0;
963 /* push+pop+possible load if it is an argument */
964 return (ins->opcode == OP_ARG) ? 3 : 2;
968 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
970 static int inited = FALSE;
971 static int count = 0;
973 if (cfg->arch.need_stack_frame_inited) {
974 g_assert (cfg->arch.need_stack_frame == flag);
978 cfg->arch.need_stack_frame = flag;
979 cfg->arch.need_stack_frame_inited = TRUE;
985 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
990 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
994 needs_stack_frame (MonoCompile *cfg)
996 MonoMethodSignature *sig;
997 MonoMethodHeader *header;
998 gboolean result = FALSE;
1000 #if defined(__APPLE__)
1001 /*OSX requires stack frame code to have the correct alignment. */
1005 if (cfg->arch.need_stack_frame_inited)
1006 return cfg->arch.need_stack_frame;
1008 header = cfg->header;
1009 sig = mono_method_signature (cfg->method);
1011 if (cfg->disable_omit_fp)
1013 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1015 else if (cfg->method->save_lmf)
1017 else if (cfg->stack_offset)
1019 else if (cfg->param_area)
1021 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1023 else if (header->num_clauses)
1025 else if (sig->param_count + sig->hasthis)
1027 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1029 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1030 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1033 set_needs_stack_frame (cfg, result);
1035 return cfg->arch.need_stack_frame;
1039 * Set var information according to the calling convention. X86 version.
1040 * The locals var stuff should most likely be split in another method.
1043 mono_arch_allocate_vars (MonoCompile *cfg)
1045 MonoMethodSignature *sig;
1046 MonoMethodHeader *header;
1048 guint32 locals_stack_size, locals_stack_align;
1053 header = cfg->header;
1054 sig = mono_method_signature (cfg->method);
1056 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1058 cfg->frame_reg = X86_EBP;
1061 if (cfg->has_atomic_add_new_i4 || cfg->has_atomic_exchange_i4) {
1062 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1063 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1066 /* Reserve space to save LMF and caller saved registers */
1068 if (cfg->method->save_lmf) {
1069 /* The LMF var is allocated normally */
1071 if (cfg->used_int_regs & (1 << X86_EBX)) {
1075 if (cfg->used_int_regs & (1 << X86_EDI)) {
1079 if (cfg->used_int_regs & (1 << X86_ESI)) {
1084 switch (cinfo->ret.storage) {
1085 case ArgValuetypeInReg:
1086 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1088 cfg->ret->opcode = OP_REGOFFSET;
1089 cfg->ret->inst_basereg = X86_EBP;
1090 cfg->ret->inst_offset = - offset;
1096 /* Allocate locals */
1097 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1098 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1099 char *mname = mono_method_full_name (cfg->method, TRUE);
1100 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1101 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1105 if (locals_stack_align) {
1106 int prev_offset = offset;
1108 offset += (locals_stack_align - 1);
1109 offset &= ~(locals_stack_align - 1);
1111 while (prev_offset < offset) {
1113 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1116 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1117 cfg->locals_max_stack_offset = - offset;
1119 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1120 * have locals larger than 8 bytes we need to make sure that
1121 * they have the appropriate offset.
1123 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1124 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1125 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1126 if (offsets [i] != -1) {
1127 MonoInst *inst = cfg->varinfo [i];
1128 inst->opcode = OP_REGOFFSET;
1129 inst->inst_basereg = X86_EBP;
1130 inst->inst_offset = - (offset + offsets [i]);
1131 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1134 offset += locals_stack_size;
1138 * Allocate arguments+return value
1141 switch (cinfo->ret.storage) {
1143 if (cfg->vret_addr) {
1145 * In the new IR, the cfg->vret_addr variable represents the
1146 * vtype return value.
1148 cfg->vret_addr->opcode = OP_REGOFFSET;
1149 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1150 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1151 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1152 printf ("vret_addr =");
1153 mono_print_ins (cfg->vret_addr);
1156 cfg->ret->opcode = OP_REGOFFSET;
1157 cfg->ret->inst_basereg = X86_EBP;
1158 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1161 case ArgValuetypeInReg:
1164 cfg->ret->opcode = OP_REGVAR;
1165 cfg->ret->inst_c0 = cinfo->ret.reg;
1166 cfg->ret->dreg = cinfo->ret.reg;
1169 case ArgOnFloatFpStack:
1170 case ArgOnDoubleFpStack:
1173 g_assert_not_reached ();
1176 if (sig->call_convention == MONO_CALL_VARARG) {
1177 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1178 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1181 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1182 ArgInfo *ainfo = &cinfo->args [i];
1183 inst = cfg->args [i];
1184 if (inst->opcode != OP_REGVAR) {
1185 inst->opcode = OP_REGOFFSET;
1186 inst->inst_basereg = X86_EBP;
1188 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1191 cfg->stack_offset = offset;
1195 mono_arch_create_vars (MonoCompile *cfg)
1198 MonoMethodSignature *sig;
1201 sig = mono_method_signature (cfg->method);
1203 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1204 sig_ret = mini_replace_type (sig->ret);
1206 if (cinfo->ret.storage == ArgValuetypeInReg)
1207 cfg->ret_var_is_local = TRUE;
1208 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (cfg, sig_ret))) {
1209 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1212 #ifdef MONO_X86_NO_PUSHES
1213 cfg->arch.no_pushes = TRUE;
1216 if (cfg->method->save_lmf) {
1217 cfg->create_lmf_var = TRUE;
1220 cfg->lmf_ir_mono_lmf = TRUE;
1224 cfg->arch_eh_jit_info = 1;
1228 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1229 * so we try to do it just once when we have multiple fp arguments in a row.
1230 * We don't use this mechanism generally because for int arguments the generated code
1231 * is slightly bigger and new generation cpus optimize away the dependency chains
1232 * created by push instructions on the esp value.
1233 * fp_arg_setup is the first argument in the execution sequence where the esp register
1236 static G_GNUC_UNUSED int
1237 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1242 for (; start_arg < sig->param_count; ++start_arg) {
1243 t = mini_replace_type (sig->params [start_arg]);
1244 if (!t->byref && t->type == MONO_TYPE_R8) {
1245 fp_space += sizeof (double);
1246 *fp_arg_setup = start_arg;
1255 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1257 MonoMethodSignature *tmp_sig;
1261 * mono_ArgIterator_Setup assumes the signature cookie is
1262 * passed first and all the arguments which were before it are
1263 * passed on the stack after the signature. So compensate by
1264 * passing a different signature.
1266 tmp_sig = mono_metadata_signature_dup (call->signature);
1267 tmp_sig->param_count -= call->signature->sentinelpos;
1268 tmp_sig->sentinelpos = 0;
1269 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1271 if (cfg->compile_aot) {
1272 sig_reg = mono_alloc_ireg (cfg);
1273 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1274 if (cfg->arch.no_pushes) {
1275 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1277 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, sig_reg);
1280 if (cfg->arch.no_pushes) {
1281 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1283 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1290 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1295 LLVMCallInfo *linfo;
1296 MonoType *t, *sig_ret;
1298 n = sig->param_count + sig->hasthis;
1300 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1303 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1306 * LLVM always uses the native ABI while we use our own ABI, the
1307 * only difference is the handling of vtypes:
1308 * - we only pass/receive them in registers in some cases, and only
1309 * in 1 or 2 integer registers.
1311 if (cinfo->ret.storage == ArgValuetypeInReg) {
1313 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1314 cfg->disable_llvm = TRUE;
1318 cfg->exception_message = g_strdup ("vtype ret in call");
1319 cfg->disable_llvm = TRUE;
1321 linfo->ret.storage = LLVMArgVtypeInReg;
1322 for (j = 0; j < 2; ++j)
1323 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1327 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage == ArgInIReg) {
1328 /* Vtype returned using a hidden argument */
1329 linfo->ret.storage = LLVMArgVtypeRetAddr;
1330 linfo->vret_arg_index = cinfo->vret_arg_index;
1333 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage != ArgInIReg) {
1335 cfg->exception_message = g_strdup ("vtype ret in call");
1336 cfg->disable_llvm = TRUE;
1339 for (i = 0; i < n; ++i) {
1340 ainfo = cinfo->args + i;
1342 if (i >= sig->hasthis)
1343 t = sig->params [i - sig->hasthis];
1345 t = &mono_defaults.int_class->byval_arg;
1347 linfo->args [i].storage = LLVMArgNone;
1349 switch (ainfo->storage) {
1351 linfo->args [i].storage = LLVMArgInIReg;
1353 case ArgInDoubleSSEReg:
1354 case ArgInFloatSSEReg:
1355 linfo->args [i].storage = LLVMArgInFPReg;
1358 if (mini_type_is_vtype (cfg, t)) {
1359 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1360 /* LLVM seems to allocate argument space for empty structures too */
1361 linfo->args [i].storage = LLVMArgNone;
1363 linfo->args [i].storage = LLVMArgVtypeByVal;
1365 linfo->args [i].storage = LLVMArgInIReg;
1367 if (t->type == MONO_TYPE_R4)
1368 linfo->args [i].storage = LLVMArgInFPReg;
1369 else if (t->type == MONO_TYPE_R8)
1370 linfo->args [i].storage = LLVMArgInFPReg;
1374 case ArgValuetypeInReg:
1376 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1377 cfg->disable_llvm = TRUE;
1381 cfg->exception_message = g_strdup ("vtype arg");
1382 cfg->disable_llvm = TRUE;
1384 linfo->args [i].storage = LLVMArgVtypeInReg;
1385 for (j = 0; j < 2; ++j)
1386 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1390 linfo->args [i].storage = LLVMArgGSharedVt;
1393 cfg->exception_message = g_strdup ("ainfo->storage");
1394 cfg->disable_llvm = TRUE;
1404 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1406 if (cfg->compute_gc_maps) {
1409 /* Needs checking if the feature will be enabled again */
1410 g_assert (!cfg->arch.no_pushes);
1412 /* On x86, the offsets are from the sp value before the start of the call sequence */
1414 t = &mono_defaults.int_class->byval_arg;
1415 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1420 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1424 MonoMethodSignature *sig;
1427 int sentinelpos = 0, sp_offset = 0;
1429 sig = call->signature;
1430 n = sig->param_count + sig->hasthis;
1431 sig_ret = mini_replace_type (sig->ret);
1433 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1435 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1436 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1438 if (cinfo->need_stack_align && !cfg->arch.no_pushes) {
1439 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1440 arg->dreg = X86_ESP;
1441 arg->sreg1 = X86_ESP;
1442 arg->inst_imm = cinfo->stack_align_amount;
1443 MONO_ADD_INS (cfg->cbb, arg);
1444 for (i = 0; i < cinfo->stack_align_amount; i += sizeof (mgreg_t)) {
1447 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1451 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1452 if (cinfo->ret.storage == ArgValuetypeInReg) {
1454 * Tell the JIT to use a more efficient calling convention: call using
1455 * OP_CALL, compute the result location after the call, and save the
1458 call->vret_in_reg = TRUE;
1460 NULLIFY_INS (call->vret_var);
1464 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1466 /* Handle the case where there are no implicit arguments */
1467 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1468 emit_sig_cookie (cfg, call, cinfo);
1469 sp_offset = (cfg->arch.no_pushes) ? cinfo->sig_cookie.offset : (sp_offset + 4);
1470 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1473 /* Arguments are pushed in the reverse order */
1474 for (i = n - 1; i >= 0; i --) {
1475 ArgInfo *ainfo = cinfo->args + i;
1476 MonoType *orig_type, *t;
1479 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1481 /* Push the vret arg before the first argument */
1482 if (cfg->arch.no_pushes) {
1483 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1484 vtarg->type = STACK_MP;
1485 vtarg->inst_destbasereg = X86_ESP;
1486 vtarg->sreg1 = call->vret_var->dreg;
1487 vtarg->inst_offset = cinfo->ret.offset;
1488 MONO_ADD_INS (cfg->cbb, vtarg);
1489 sp_offset = cinfo->ret.offset;
1491 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1492 vtarg->type = STACK_MP;
1493 vtarg->sreg1 = call->vret_var->dreg;
1494 MONO_ADD_INS (cfg->cbb, vtarg);
1497 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1500 if (i >= sig->hasthis)
1501 t = sig->params [i - sig->hasthis];
1503 t = &mono_defaults.int_class->byval_arg;
1505 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1507 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1509 in = call->args [i];
1510 arg->cil_code = in->cil_code;
1511 arg->sreg1 = in->dreg;
1512 arg->type = in->type;
1514 g_assert (in->dreg != -1);
1516 if (ainfo->storage == ArgGSharedVt) {
1517 arg->opcode = OP_OUTARG_VT;
1518 arg->sreg1 = in->dreg;
1519 arg->klass = in->klass;
1520 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1521 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1523 MONO_ADD_INS (cfg->cbb, arg);
1524 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1528 g_assert (in->klass);
1530 if (t->type == MONO_TYPE_TYPEDBYREF) {
1531 size = sizeof (MonoTypedRef);
1532 align = sizeof (gpointer);
1535 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1539 arg->opcode = OP_OUTARG_VT;
1540 arg->sreg1 = in->dreg;
1541 arg->klass = in->klass;
1542 arg->backend.size = size;
1543 arg->inst_p0 = call;
1544 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1545 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1547 MONO_ADD_INS (cfg->cbb, arg);
1548 if (ainfo->storage != ArgValuetypeInReg) {
1549 sp_offset = (cfg->arch.no_pushes) ? ainfo->offset : (sp_offset + size);
1550 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1554 switch (ainfo->storage) {
1557 if (t->type == MONO_TYPE_R4) {
1558 if (cfg->arch.no_pushes) {
1559 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1561 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1562 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, 0, in->dreg);
1565 } else if (t->type == MONO_TYPE_R8) {
1566 if (cfg->arch.no_pushes) {
1567 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1569 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1570 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, 0, in->dreg);
1573 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1574 if (cfg->arch.no_pushes) {
1575 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, in->dreg + 2);
1576 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg + 1);
1578 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1579 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 1);
1584 if (cfg->arch.no_pushes) {
1585 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1587 arg->opcode = OP_X86_PUSH;
1588 MONO_ADD_INS (cfg->cbb, arg);
1593 if (cfg->arch.no_pushes) {
1594 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1596 arg->opcode = OP_X86_PUSH;
1597 MONO_ADD_INS (cfg->cbb, arg);
1603 arg->opcode = OP_MOVE;
1604 arg->dreg = ainfo->reg;
1605 MONO_ADD_INS (cfg->cbb, arg);
1609 g_assert_not_reached ();
1612 sp_offset = (cfg->arch.no_pushes) ? ainfo->offset : (sp_offset + argsize);
1614 if (cfg->compute_gc_maps) {
1616 /* FIXME: The == STACK_OBJ check might be fragile ? */
1617 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1619 if (call->need_unbox_trampoline)
1620 /* The unbox trampoline transforms this into a managed pointer */
1621 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.int_class->this_arg);
1623 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.object_class->byval_arg);
1625 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1629 for (j = 0; j < argsize; j += 4) {
1630 if (cfg->arch.no_pushes)
1631 emit_gc_param_slot_def (cfg, sp_offset + j, NULL);
1633 emit_gc_param_slot_def (cfg, sp_offset - j, NULL);
1639 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1640 /* Emit the signature cookie just before the implicit arguments */
1641 emit_sig_cookie (cfg, call, cinfo);
1642 sp_offset = (cfg->arch.no_pushes) ? cinfo->sig_cookie.offset : (sp_offset + 4);
1643 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1647 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1650 if (cinfo->ret.storage == ArgValuetypeInReg) {
1653 else if (cinfo->ret.storage == ArgInIReg) {
1655 /* The return address is passed in a register */
1656 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1657 vtarg->sreg1 = call->inst.dreg;
1658 vtarg->dreg = mono_alloc_ireg (cfg);
1659 MONO_ADD_INS (cfg->cbb, vtarg);
1661 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1662 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1663 if (cfg->arch.no_pushes) {
1664 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1665 sp_offset = cinfo->ret.offset;
1668 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1669 vtarg->type = STACK_MP;
1670 vtarg->sreg1 = call->vret_var->dreg;
1671 MONO_ADD_INS (cfg->cbb, vtarg);
1674 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1677 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1678 if (cinfo->ret.storage != ArgValuetypeInReg)
1679 cinfo->stack_usage -= 4;
1682 call->stack_usage = cinfo->stack_usage;
1683 call->stack_align_amount = cinfo->stack_align_amount;
1684 if (!cfg->arch.no_pushes)
1685 cfg->arch.param_area_size = MAX (cfg->arch.param_area_size, sp_offset);
1689 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1691 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1692 ArgInfo *ainfo = ins->inst_p1;
1694 int size = ins->backend.size;
1696 if (ainfo->storage == ArgValuetypeInReg) {
1697 int dreg = mono_alloc_ireg (cfg);
1700 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1703 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1706 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1710 g_assert_not_reached ();
1712 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1715 if (cfg->gsharedvt && mini_is_gsharedvt_klass (cfg, ins->klass)) {
1717 if (cfg->arch.no_pushes) {
1718 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1720 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1721 arg->sreg1 = src->dreg;
1722 MONO_ADD_INS (cfg->cbb, arg);
1724 } else if (size <= 4) {
1725 if (cfg->arch.no_pushes) {
1726 int dreg = mono_alloc_ireg (cfg);
1727 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1728 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1730 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1731 arg->sreg1 = src->dreg;
1732 MONO_ADD_INS (cfg->cbb, arg);
1734 } else if (size <= 20) {
1735 if (cfg->arch.no_pushes) {
1736 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1738 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1739 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1742 if (cfg->arch.no_pushes) {
1743 // FIXME: Code growth
1744 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1746 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1747 arg->inst_basereg = src->dreg;
1748 arg->inst_offset = 0;
1749 arg->inst_imm = size;
1751 MONO_ADD_INS (cfg->cbb, arg);
1758 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1760 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1763 if (ret->type == MONO_TYPE_R4) {
1764 if (COMPILE_LLVM (cfg))
1765 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1768 } else if (ret->type == MONO_TYPE_R8) {
1769 if (COMPILE_LLVM (cfg))
1770 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1773 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1774 if (COMPILE_LLVM (cfg))
1775 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1777 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1778 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1784 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1788 * Allow tracing to work with this interface (with an optional argument)
1791 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1795 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1796 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1798 /* if some args are passed in registers, we need to save them here */
1799 x86_push_reg (code, X86_EBP);
1801 if (cfg->compile_aot) {
1802 x86_push_imm (code, cfg->method);
1803 x86_mov_reg_imm (code, X86_EAX, func);
1804 x86_call_reg (code, X86_EAX);
1806 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1807 x86_push_imm (code, cfg->method);
1808 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1809 x86_call_code (code, 0);
1811 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1825 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1828 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1829 MonoMethod *method = cfg->method;
1830 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1832 switch (ret_type->type) {
1833 case MONO_TYPE_VOID:
1834 /* special case string .ctor icall */
1835 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1836 save_mode = SAVE_EAX;
1837 stack_usage = enable_arguments ? 8 : 4;
1839 save_mode = SAVE_NONE;
1843 save_mode = SAVE_EAX_EDX;
1844 stack_usage = enable_arguments ? 16 : 8;
1848 save_mode = SAVE_FP;
1849 stack_usage = enable_arguments ? 16 : 8;
1851 case MONO_TYPE_GENERICINST:
1852 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1853 save_mode = SAVE_EAX;
1854 stack_usage = enable_arguments ? 8 : 4;
1858 case MONO_TYPE_VALUETYPE:
1859 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1860 save_mode = SAVE_STRUCT;
1861 stack_usage = enable_arguments ? 4 : 0;
1864 save_mode = SAVE_EAX;
1865 stack_usage = enable_arguments ? 8 : 4;
1869 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1871 switch (save_mode) {
1873 x86_push_reg (code, X86_EDX);
1874 x86_push_reg (code, X86_EAX);
1875 if (enable_arguments) {
1876 x86_push_reg (code, X86_EDX);
1877 x86_push_reg (code, X86_EAX);
1882 x86_push_reg (code, X86_EAX);
1883 if (enable_arguments) {
1884 x86_push_reg (code, X86_EAX);
1889 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1890 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1891 if (enable_arguments) {
1892 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1893 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1898 if (enable_arguments) {
1899 x86_push_membase (code, X86_EBP, 8);
1908 if (cfg->compile_aot) {
1909 x86_push_imm (code, method);
1910 x86_mov_reg_imm (code, X86_EAX, func);
1911 x86_call_reg (code, X86_EAX);
1913 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1914 x86_push_imm (code, method);
1915 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1916 x86_call_code (code, 0);
1919 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1921 switch (save_mode) {
1923 x86_pop_reg (code, X86_EAX);
1924 x86_pop_reg (code, X86_EDX);
1927 x86_pop_reg (code, X86_EAX);
1930 x86_fld_membase (code, X86_ESP, 0, TRUE);
1931 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1938 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1943 #define EMIT_COND_BRANCH(ins,cond,sign) \
1944 if (ins->inst_true_bb->native_offset) { \
1945 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1947 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1948 if ((cfg->opt & MONO_OPT_BRANCH) && \
1949 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1950 x86_branch8 (code, cond, 0, sign); \
1952 x86_branch32 (code, cond, 0, sign); \
1956 * Emit an exception if condition is fail and
1957 * if possible do a directly branch to target
1959 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1961 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1962 if (tins == NULL) { \
1963 mono_add_patch_info (cfg, code - cfg->native_code, \
1964 MONO_PATCH_INFO_EXC, exc_name); \
1965 x86_branch32 (code, cond, 0, signed); \
1967 EMIT_COND_BRANCH (tins, cond, signed); \
1971 #define EMIT_FPCOMPARE(code) do { \
1972 x86_fcompp (code); \
1973 x86_fnstsw (code); \
1978 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1980 gboolean needs_paddings = TRUE;
1982 MonoJumpInfo *jinfo = NULL;
1984 if (cfg->abs_patches) {
1985 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1986 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1987 needs_paddings = FALSE;
1990 if (cfg->compile_aot)
1991 needs_paddings = FALSE;
1992 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1993 This is required for code patching to be safe on SMP machines.
1995 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1996 #ifndef __native_client_codegen__
1997 if (needs_paddings && pad_size)
1998 x86_padding (code, 4 - pad_size);
2001 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2002 x86_call_code (code, 0);
2007 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
2010 * mono_peephole_pass_1:
2012 * Perform peephole opts which should/can be performed before local regalloc
2015 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2019 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2020 MonoInst *last_ins = ins->prev;
2022 switch (ins->opcode) {
2025 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
2027 * X86_LEA is like ADD, but doesn't have the
2028 * sreg1==dreg restriction.
2030 ins->opcode = OP_X86_LEA_MEMBASE;
2031 ins->inst_basereg = ins->sreg1;
2032 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2033 ins->opcode = OP_X86_INC_REG;
2037 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
2038 ins->opcode = OP_X86_LEA_MEMBASE;
2039 ins->inst_basereg = ins->sreg1;
2040 ins->inst_imm = -ins->inst_imm;
2041 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2042 ins->opcode = OP_X86_DEC_REG;
2044 case OP_COMPARE_IMM:
2045 case OP_ICOMPARE_IMM:
2046 /* OP_COMPARE_IMM (reg, 0)
2048 * OP_X86_TEST_NULL (reg)
2051 ins->opcode = OP_X86_TEST_NULL;
2053 case OP_X86_COMPARE_MEMBASE_IMM:
2055 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2056 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2058 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2059 * OP_COMPARE_IMM reg, imm
2061 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2063 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2064 ins->inst_basereg == last_ins->inst_destbasereg &&
2065 ins->inst_offset == last_ins->inst_offset) {
2066 ins->opcode = OP_COMPARE_IMM;
2067 ins->sreg1 = last_ins->sreg1;
2069 /* check if we can remove cmp reg,0 with test null */
2071 ins->opcode = OP_X86_TEST_NULL;
2075 case OP_X86_PUSH_MEMBASE:
2076 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
2077 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2078 ins->inst_basereg == last_ins->inst_destbasereg &&
2079 ins->inst_offset == last_ins->inst_offset) {
2080 ins->opcode = OP_X86_PUSH;
2081 ins->sreg1 = last_ins->sreg1;
2086 mono_peephole_ins (bb, ins);
2091 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2095 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2096 switch (ins->opcode) {
2098 /* reg = 0 -> XOR (reg, reg) */
2099 /* XOR sets cflags on x86, so we cant do it always */
2100 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2103 ins->opcode = OP_IXOR;
2104 ins->sreg1 = ins->dreg;
2105 ins->sreg2 = ins->dreg;
2108 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2109 * since it takes 3 bytes instead of 7.
2111 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2112 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2113 ins2->opcode = OP_STORE_MEMBASE_REG;
2114 ins2->sreg1 = ins->dreg;
2116 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2117 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2118 ins2->sreg1 = ins->dreg;
2120 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2121 /* Continue iteration */
2130 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2131 ins->opcode = OP_X86_INC_REG;
2135 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2136 ins->opcode = OP_X86_DEC_REG;
2140 mono_peephole_ins (bb, ins);
2145 * mono_arch_lowering_pass:
2147 * Converts complex opcodes into simpler ones so that each IR instruction
2148 * corresponds to one machine instruction.
2151 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2153 MonoInst *ins, *next;
2156 * FIXME: Need to add more instructions, but the current machine
2157 * description can't model some parts of the composite instructions like
2160 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2161 switch (ins->opcode) {
2164 case OP_IDIV_UN_IMM:
2165 case OP_IREM_UN_IMM:
2167 * Keep the cases where we could generated optimized code, otherwise convert
2168 * to the non-imm variant.
2170 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2172 mono_decompose_op_imm (cfg, bb, ins);
2179 bb->max_vreg = cfg->next_vreg;
2183 branch_cc_table [] = {
2184 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2185 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2186 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2189 /* Maps CMP_... constants to X86_CC_... constants */
2192 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2193 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2197 cc_signed_table [] = {
2198 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2199 FALSE, FALSE, FALSE, FALSE
2202 static unsigned char*
2203 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2205 #define XMM_TEMP_REG 0
2206 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2207 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2208 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2209 /* optimize by assigning a local var for this use so we avoid
2210 * the stack manipulations */
2211 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2212 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2213 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2214 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2215 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2217 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2219 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2222 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2223 x86_fnstcw_membase(code, X86_ESP, 0);
2224 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2225 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2226 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2227 x86_fldcw_membase (code, X86_ESP, 2);
2229 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2230 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2231 x86_pop_reg (code, dreg);
2232 /* FIXME: need the high register
2233 * x86_pop_reg (code, dreg_high);
2236 x86_push_reg (code, X86_EAX); // SP = SP - 4
2237 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2238 x86_pop_reg (code, dreg);
2240 x86_fldcw_membase (code, X86_ESP, 0);
2241 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2244 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2246 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2250 static unsigned char*
2251 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2253 int sreg = tree->sreg1;
2254 int need_touch = FALSE;
2256 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2265 * If requested stack size is larger than one page,
2266 * perform stack-touch operation
2269 * Generate stack probe code.
2270 * Under Windows, it is necessary to allocate one page at a time,
2271 * "touching" stack after each successful sub-allocation. This is
2272 * because of the way stack growth is implemented - there is a
2273 * guard page before the lowest stack page that is currently commited.
2274 * Stack normally grows sequentially so OS traps access to the
2275 * guard page and commits more pages when needed.
2277 x86_test_reg_imm (code, sreg, ~0xFFF);
2278 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2280 br[2] = code; /* loop */
2281 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2282 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2285 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2286 * that follows only initializes the last part of the area.
2288 /* Same as the init code below with size==0x1000 */
2289 if (tree->flags & MONO_INST_INIT) {
2290 x86_push_reg (code, X86_EAX);
2291 x86_push_reg (code, X86_ECX);
2292 x86_push_reg (code, X86_EDI);
2293 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2294 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2295 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2296 if (cfg->param_area && cfg->arch.no_pushes)
2297 x86_alu_reg_imm (code, X86_ADD, X86_EDI, cfg->param_area);
2299 x86_prefix (code, X86_REP_PREFIX);
2301 x86_pop_reg (code, X86_EDI);
2302 x86_pop_reg (code, X86_ECX);
2303 x86_pop_reg (code, X86_EAX);
2306 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2307 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2308 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2309 x86_patch (br[3], br[2]);
2310 x86_test_reg_reg (code, sreg, sreg);
2311 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2312 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2314 br[1] = code; x86_jump8 (code, 0);
2316 x86_patch (br[0], code);
2317 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2318 x86_patch (br[1], code);
2319 x86_patch (br[4], code);
2322 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2324 if (tree->flags & MONO_INST_INIT) {
2326 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2327 x86_push_reg (code, X86_EAX);
2330 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2331 x86_push_reg (code, X86_ECX);
2334 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2335 x86_push_reg (code, X86_EDI);
2339 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2340 if (sreg != X86_ECX)
2341 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2342 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2344 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2346 x86_prefix (code, X86_REP_PREFIX);
2349 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2350 x86_pop_reg (code, X86_EDI);
2351 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2352 x86_pop_reg (code, X86_ECX);
2353 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2354 x86_pop_reg (code, X86_EAX);
2361 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2363 /* Move return value to the target register */
2364 switch (ins->opcode) {
2367 case OP_CALL_MEMBASE:
2368 if (ins->dreg != X86_EAX)
2369 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2379 static int tls_gs_offset;
2383 mono_x86_have_tls_get (void)
2386 static gboolean have_tls_get = FALSE;
2387 static gboolean inited = FALSE;
2391 return have_tls_get;
2393 ins = (guint32*)pthread_getspecific;
2395 * We're looking for these two instructions:
2397 * mov 0x4(%esp),%eax
2398 * mov %gs:[offset](,%eax,4),%eax
2400 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2401 tls_gs_offset = ins [2];
2405 return have_tls_get;
2406 #elif defined(TARGET_ANDROID)
2414 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2416 #if defined(__APPLE__)
2417 x86_prefix (code, X86_GS_PREFIX);
2418 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2419 #elif defined(TARGET_WIN32)
2420 g_assert_not_reached ();
2422 x86_prefix (code, X86_GS_PREFIX);
2423 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2429 * mono_x86_emit_tls_get:
2430 * @code: buffer to store code to
2431 * @dreg: hard register where to place the result
2432 * @tls_offset: offset info
2434 * mono_x86_emit_tls_get emits in @code the native code that puts in
2435 * the dreg register the item in the thread local storage identified
2438 * Returns: a pointer to the end of the stored code
2441 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2443 #if defined(__APPLE__)
2444 x86_prefix (code, X86_GS_PREFIX);
2445 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2446 #elif defined(TARGET_WIN32)
2448 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2449 * Journal and/or a disassembly of the TlsGet () function.
2451 g_assert (tls_offset < 64);
2452 x86_prefix (code, X86_FS_PREFIX);
2453 x86_mov_reg_mem (code, dreg, 0x18, 4);
2454 /* Dunno what this does but TlsGetValue () contains it */
2455 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2456 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2458 if (optimize_for_xen) {
2459 x86_prefix (code, X86_GS_PREFIX);
2460 x86_mov_reg_mem (code, dreg, 0, 4);
2461 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2463 x86_prefix (code, X86_GS_PREFIX);
2464 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2471 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2473 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2474 #if defined(__APPLE__) || defined(__linux__)
2475 if (dreg != offset_reg)
2476 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2477 x86_prefix (code, X86_GS_PREFIX);
2478 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2480 g_assert_not_reached ();
2486 mono_x86_emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2488 return emit_tls_get_reg (code, dreg, offset_reg);
2492 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2494 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2496 g_assert_not_reached ();
2497 #elif defined(__APPLE__) || defined(__linux__)
2498 x86_prefix (code, X86_GS_PREFIX);
2499 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2501 g_assert_not_reached ();
2507 * mono_arch_translate_tls_offset:
2509 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2512 mono_arch_translate_tls_offset (int offset)
2515 return tls_gs_offset + (offset * 4);
2524 * Emit code to initialize an LMF structure at LMF_OFFSET.
2527 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2529 /* save all caller saved regs */
2530 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2531 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx));
2532 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2533 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi));
2534 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2535 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi));
2536 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2538 /* save the current IP */
2539 if (cfg->compile_aot) {
2540 /* This pushes the current ip */
2541 x86_call_imm (code, 0);
2542 x86_pop_reg (code, X86_EAX);
2544 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2545 x86_mov_reg_imm (code, X86_EAX, 0);
2547 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2549 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2550 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2551 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2552 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2553 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2554 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2555 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2556 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2557 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2562 #define REAL_PRINT_REG(text,reg) \
2563 mono_assert (reg >= 0); \
2564 x86_push_reg (code, X86_EAX); \
2565 x86_push_reg (code, X86_EDX); \
2566 x86_push_reg (code, X86_ECX); \
2567 x86_push_reg (code, reg); \
2568 x86_push_imm (code, reg); \
2569 x86_push_imm (code, text " %d %p\n"); \
2570 x86_mov_reg_imm (code, X86_EAX, printf); \
2571 x86_call_reg (code, X86_EAX); \
2572 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2573 x86_pop_reg (code, X86_ECX); \
2574 x86_pop_reg (code, X86_EDX); \
2575 x86_pop_reg (code, X86_EAX);
2577 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2578 #ifdef __native__client_codegen__
2579 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2582 /* benchmark and set based on cpu */
2583 #define LOOP_ALIGNMENT 8
2584 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2588 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2593 guint8 *code = cfg->native_code + cfg->code_len;
2596 if (cfg->opt & MONO_OPT_LOOP) {
2597 int pad, align = LOOP_ALIGNMENT;
2598 /* set alignment depending on cpu */
2599 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2601 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2602 x86_padding (code, pad);
2603 cfg->code_len += pad;
2604 bb->native_offset = cfg->code_len;
2607 #ifdef __native_client_codegen__
2609 /* For Native Client, all indirect call/jump targets must be */
2610 /* 32-byte aligned. Exception handler blocks are jumped to */
2611 /* indirectly as well. */
2612 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2613 (bb->flags & BB_EXCEPTION_HANDLER);
2615 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2616 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2617 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2618 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2619 cfg->code_len += pad;
2620 bb->native_offset = cfg->code_len;
2623 #endif /* __native_client_codegen__ */
2624 if (cfg->verbose_level > 2)
2625 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2627 cpos = bb->max_offset;
2629 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2630 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2631 g_assert (!cfg->compile_aot);
2634 cov->data [bb->dfn].cil_code = bb->cil_code;
2635 /* this is not thread save, but good enough */
2636 x86_inc_mem (code, &cov->data [bb->dfn].count);
2639 offset = code - cfg->native_code;
2641 mono_debug_open_block (cfg, bb, offset);
2643 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2644 x86_breakpoint (code);
2646 MONO_BB_FOR_EACH_INS (bb, ins) {
2647 offset = code - cfg->native_code;
2649 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2651 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2653 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2654 cfg->code_size *= 2;
2655 cfg->native_code = mono_realloc_native_code(cfg);
2656 code = cfg->native_code + offset;
2657 cfg->stat_code_reallocs++;
2660 if (cfg->debug_info)
2661 mono_debug_record_line_number (cfg, ins, offset);
2663 switch (ins->opcode) {
2665 x86_mul_reg (code, ins->sreg2, TRUE);
2668 x86_mul_reg (code, ins->sreg2, FALSE);
2670 case OP_X86_SETEQ_MEMBASE:
2671 case OP_X86_SETNE_MEMBASE:
2672 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2673 ins->inst_basereg, ins->inst_offset, TRUE);
2675 case OP_STOREI1_MEMBASE_IMM:
2676 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2678 case OP_STOREI2_MEMBASE_IMM:
2679 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2681 case OP_STORE_MEMBASE_IMM:
2682 case OP_STOREI4_MEMBASE_IMM:
2683 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2685 case OP_STOREI1_MEMBASE_REG:
2686 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2688 case OP_STOREI2_MEMBASE_REG:
2689 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2691 case OP_STORE_MEMBASE_REG:
2692 case OP_STOREI4_MEMBASE_REG:
2693 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2695 case OP_STORE_MEM_IMM:
2696 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2699 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2703 /* These are created by the cprop pass so they use inst_imm as the source */
2704 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2707 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2710 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2712 case OP_LOAD_MEMBASE:
2713 case OP_LOADI4_MEMBASE:
2714 case OP_LOADU4_MEMBASE:
2715 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2717 case OP_LOADU1_MEMBASE:
2718 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2720 case OP_LOADI1_MEMBASE:
2721 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2723 case OP_LOADU2_MEMBASE:
2724 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2726 case OP_LOADI2_MEMBASE:
2727 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2729 case OP_ICONV_TO_I1:
2731 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2733 case OP_ICONV_TO_I2:
2735 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2737 case OP_ICONV_TO_U1:
2738 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2740 case OP_ICONV_TO_U2:
2741 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2745 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2747 case OP_COMPARE_IMM:
2748 case OP_ICOMPARE_IMM:
2749 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2751 case OP_X86_COMPARE_MEMBASE_REG:
2752 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2754 case OP_X86_COMPARE_MEMBASE_IMM:
2755 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2757 case OP_X86_COMPARE_MEMBASE8_IMM:
2758 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2760 case OP_X86_COMPARE_REG_MEMBASE:
2761 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2763 case OP_X86_COMPARE_MEM_IMM:
2764 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2766 case OP_X86_TEST_NULL:
2767 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2769 case OP_X86_ADD_MEMBASE_IMM:
2770 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2772 case OP_X86_ADD_REG_MEMBASE:
2773 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2775 case OP_X86_SUB_MEMBASE_IMM:
2776 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2778 case OP_X86_SUB_REG_MEMBASE:
2779 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2781 case OP_X86_AND_MEMBASE_IMM:
2782 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2784 case OP_X86_OR_MEMBASE_IMM:
2785 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2787 case OP_X86_XOR_MEMBASE_IMM:
2788 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2790 case OP_X86_ADD_MEMBASE_REG:
2791 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2793 case OP_X86_SUB_MEMBASE_REG:
2794 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2796 case OP_X86_AND_MEMBASE_REG:
2797 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2799 case OP_X86_OR_MEMBASE_REG:
2800 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2802 case OP_X86_XOR_MEMBASE_REG:
2803 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2805 case OP_X86_INC_MEMBASE:
2806 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2808 case OP_X86_INC_REG:
2809 x86_inc_reg (code, ins->dreg);
2811 case OP_X86_DEC_MEMBASE:
2812 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2814 case OP_X86_DEC_REG:
2815 x86_dec_reg (code, ins->dreg);
2817 case OP_X86_MUL_REG_MEMBASE:
2818 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2820 case OP_X86_AND_REG_MEMBASE:
2821 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2823 case OP_X86_OR_REG_MEMBASE:
2824 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2826 case OP_X86_XOR_REG_MEMBASE:
2827 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2830 x86_breakpoint (code);
2832 case OP_RELAXED_NOP:
2833 x86_prefix (code, X86_REP_PREFIX);
2841 case OP_DUMMY_STORE:
2842 case OP_DUMMY_ICONST:
2843 case OP_DUMMY_R8CONST:
2844 case OP_NOT_REACHED:
2847 case OP_SEQ_POINT: {
2850 if (cfg->compile_aot)
2854 * Read from the single stepping trigger page. This will cause a
2855 * SIGSEGV when single stepping is enabled.
2856 * We do this _before_ the breakpoint, so single stepping after
2857 * a breakpoint is hit will step to the next IL offset.
2859 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2860 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2862 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2865 * A placeholder for a possible breakpoint inserted by
2866 * mono_arch_set_breakpoint ().
2868 for (i = 0; i < 6; ++i)
2871 * Add an additional nop so skipping the bp doesn't cause the ip to point
2872 * to another IL offset.
2880 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2884 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2889 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2893 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2898 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2902 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2907 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2911 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2914 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2918 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2922 #if defined( __native_client_codegen__ )
2923 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2924 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2927 * The code is the same for div/rem, the allocator will allocate dreg
2928 * to RAX/RDX as appropriate.
2930 if (ins->sreg2 == X86_EDX) {
2931 /* cdq clobbers this */
2932 x86_push_reg (code, ins->sreg2);
2934 x86_div_membase (code, X86_ESP, 0, TRUE);
2935 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2938 x86_div_reg (code, ins->sreg2, TRUE);
2943 #if defined( __native_client_codegen__ )
2944 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2945 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2947 if (ins->sreg2 == X86_EDX) {
2948 x86_push_reg (code, ins->sreg2);
2949 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2950 x86_div_membase (code, X86_ESP, 0, FALSE);
2951 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2953 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2954 x86_div_reg (code, ins->sreg2, FALSE);
2958 #if defined( __native_client_codegen__ )
2959 if (ins->inst_imm == 0) {
2960 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2961 x86_jump32 (code, 0);
2965 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2967 x86_div_reg (code, ins->sreg2, TRUE);
2970 int power = mono_is_power_of_two (ins->inst_imm);
2972 g_assert (ins->sreg1 == X86_EAX);
2973 g_assert (ins->dreg == X86_EAX);
2974 g_assert (power >= 0);
2977 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2979 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2981 * If the divident is >= 0, this does not nothing. If it is positive, it
2982 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2984 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2985 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2986 } else if (power == 0) {
2987 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2989 /* Based on gcc code */
2991 /* Add compensation for negative dividents */
2993 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2994 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2995 /* Compute remainder */
2996 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2997 /* Remove compensation */
2998 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
3003 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3007 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3010 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3014 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3017 g_assert (ins->sreg2 == X86_ECX);
3018 x86_shift_reg (code, X86_SHL, ins->dreg);
3021 g_assert (ins->sreg2 == X86_ECX);
3022 x86_shift_reg (code, X86_SAR, ins->dreg);
3026 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3029 case OP_ISHR_UN_IMM:
3030 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3033 g_assert (ins->sreg2 == X86_ECX);
3034 x86_shift_reg (code, X86_SHR, ins->dreg);
3038 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3041 guint8 *jump_to_end;
3043 /* handle shifts below 32 bits */
3044 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
3045 x86_shift_reg (code, X86_SHL, ins->sreg1);
3047 x86_test_reg_imm (code, X86_ECX, 32);
3048 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3050 /* handle shift over 32 bit */
3051 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3052 x86_clear_reg (code, ins->sreg1);
3054 x86_patch (jump_to_end, code);
3058 guint8 *jump_to_end;
3060 /* handle shifts below 32 bits */
3061 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3062 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
3064 x86_test_reg_imm (code, X86_ECX, 32);
3065 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3067 /* handle shifts over 31 bits */
3068 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3069 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
3071 x86_patch (jump_to_end, code);
3075 guint8 *jump_to_end;
3077 /* handle shifts below 32 bits */
3078 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3079 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
3081 x86_test_reg_imm (code, X86_ECX, 32);
3082 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3084 /* handle shifts over 31 bits */
3085 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3086 x86_clear_reg (code, ins->backend.reg3);
3088 x86_patch (jump_to_end, code);
3092 if (ins->inst_imm >= 32) {
3093 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3094 x86_clear_reg (code, ins->sreg1);
3095 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
3097 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
3098 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
3102 if (ins->inst_imm >= 32) {
3103 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3104 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
3105 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
3107 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3108 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3111 case OP_LSHR_UN_IMM:
3112 if (ins->inst_imm >= 32) {
3113 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3114 x86_clear_reg (code, ins->backend.reg3);
3115 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3117 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3118 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3122 x86_not_reg (code, ins->sreg1);
3125 x86_neg_reg (code, ins->sreg1);
3129 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3133 switch (ins->inst_imm) {
3137 if (ins->dreg != ins->sreg1)
3138 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3139 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3142 /* LEA r1, [r2 + r2*2] */
3143 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3146 /* LEA r1, [r2 + r2*4] */
3147 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3150 /* LEA r1, [r2 + r2*2] */
3152 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3153 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3156 /* LEA r1, [r2 + r2*8] */
3157 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3160 /* LEA r1, [r2 + r2*4] */
3162 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3163 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3166 /* LEA r1, [r2 + r2*2] */
3168 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3169 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3172 /* LEA r1, [r2 + r2*4] */
3173 /* LEA r1, [r1 + r1*4] */
3174 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3175 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3178 /* LEA r1, [r2 + r2*4] */
3180 /* LEA r1, [r1 + r1*4] */
3181 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3182 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3183 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3186 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3191 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3192 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3194 case OP_IMUL_OVF_UN: {
3195 /* the mul operation and the exception check should most likely be split */
3196 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3197 /*g_assert (ins->sreg2 == X86_EAX);
3198 g_assert (ins->dreg == X86_EAX);*/
3199 if (ins->sreg2 == X86_EAX) {
3200 non_eax_reg = ins->sreg1;
3201 } else if (ins->sreg1 == X86_EAX) {
3202 non_eax_reg = ins->sreg2;
3204 /* no need to save since we're going to store to it anyway */
3205 if (ins->dreg != X86_EAX) {
3207 x86_push_reg (code, X86_EAX);
3209 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3210 non_eax_reg = ins->sreg2;
3212 if (ins->dreg == X86_EDX) {
3215 x86_push_reg (code, X86_EAX);
3217 } else if (ins->dreg != X86_EAX) {
3219 x86_push_reg (code, X86_EDX);
3221 x86_mul_reg (code, non_eax_reg, FALSE);
3222 /* save before the check since pop and mov don't change the flags */
3223 if (ins->dreg != X86_EAX)
3224 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3226 x86_pop_reg (code, X86_EDX);
3228 x86_pop_reg (code, X86_EAX);
3229 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3233 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3236 g_assert_not_reached ();
3237 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3238 x86_mov_reg_imm (code, ins->dreg, 0);
3241 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3242 x86_mov_reg_imm (code, ins->dreg, 0);
3244 case OP_LOAD_GOTADDR:
3245 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3246 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3249 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3250 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3252 case OP_X86_PUSH_GOT_ENTRY:
3253 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3254 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3257 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3260 MonoCallInst *call = (MonoCallInst*)ins;
3263 ins->flags |= MONO_INST_GC_CALLSITE;
3264 ins->backend.pc_offset = code - cfg->native_code;
3266 /* reset offset to make max_len work */
3267 offset = code - cfg->native_code;
3269 g_assert (!cfg->method->save_lmf);
3271 /* restore callee saved registers */
3272 for (i = 0; i < X86_NREG; ++i)
3273 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3275 if (cfg->used_int_regs & (1 << X86_ESI)) {
3276 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3279 if (cfg->used_int_regs & (1 << X86_EDI)) {
3280 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3283 if (cfg->used_int_regs & (1 << X86_EBX)) {
3284 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3288 /* Copy arguments on the stack to our argument area */
3289 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3290 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3291 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3294 /* restore ESP/EBP */
3296 offset = code - cfg->native_code;
3297 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3298 x86_jump32 (code, 0);
3300 ins->flags |= MONO_INST_GC_CALLSITE;
3301 cfg->disable_aot = TRUE;
3305 /* ensure ins->sreg1 is not NULL
3306 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3307 * cmp DWORD PTR [eax], 0
3309 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3312 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3313 x86_push_reg (code, hreg);
3314 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3315 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3316 x86_pop_reg (code, hreg);
3325 call = (MonoCallInst*)ins;
3326 if (ins->flags & MONO_INST_HAS_METHOD)
3327 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3329 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3330 ins->flags |= MONO_INST_GC_CALLSITE;
3331 ins->backend.pc_offset = code - cfg->native_code;
3332 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature) && !cfg->arch.no_pushes) {
3333 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
3334 * bytes to pop, we want to use pops. GCC does this (note it won't happen
3335 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
3336 * smart enough to do that optimization yet
3338 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
3339 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
3340 * (most likely from locality benefits). People with other processors should
3341 * check on theirs to see what happens.
3343 if (call->stack_usage == 4) {
3344 /* we want to use registers that won't get used soon, so use
3345 * ecx, as eax will get allocated first. edx is used by long calls,
3346 * so we can't use that.
3349 x86_pop_reg (code, X86_ECX);
3351 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3354 code = emit_move_return_value (cfg, ins, code);
3360 case OP_VOIDCALL_REG:
3362 call = (MonoCallInst*)ins;
3363 x86_call_reg (code, ins->sreg1);
3364 ins->flags |= MONO_INST_GC_CALLSITE;
3365 ins->backend.pc_offset = code - cfg->native_code;
3366 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature) && !cfg->arch.no_pushes) {
3367 if (call->stack_usage == 4)
3368 x86_pop_reg (code, X86_ECX);
3370 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3372 code = emit_move_return_value (cfg, ins, code);
3374 case OP_FCALL_MEMBASE:
3375 case OP_LCALL_MEMBASE:
3376 case OP_VCALL_MEMBASE:
3377 case OP_VCALL2_MEMBASE:
3378 case OP_VOIDCALL_MEMBASE:
3379 case OP_CALL_MEMBASE:
3380 call = (MonoCallInst*)ins;
3382 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3383 ins->flags |= MONO_INST_GC_CALLSITE;
3384 ins->backend.pc_offset = code - cfg->native_code;
3385 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature) && !cfg->arch.no_pushes) {
3386 if (call->stack_usage == 4)
3387 x86_pop_reg (code, X86_ECX);
3389 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3391 code = emit_move_return_value (cfg, ins, code);
3394 g_assert (!cfg->arch.no_pushes);
3395 x86_push_reg (code, ins->sreg1);
3397 case OP_X86_PUSH_IMM:
3398 g_assert (!cfg->arch.no_pushes);
3399 x86_push_imm (code, ins->inst_imm);
3401 case OP_X86_PUSH_MEMBASE:
3402 g_assert (!cfg->arch.no_pushes);
3403 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
3405 case OP_X86_PUSH_OBJ:
3406 g_assert (!cfg->arch.no_pushes);
3407 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
3408 x86_push_reg (code, X86_EDI);
3409 x86_push_reg (code, X86_ESI);
3410 x86_push_reg (code, X86_ECX);
3411 if (ins->inst_offset)
3412 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
3414 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
3415 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
3416 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
3418 x86_prefix (code, X86_REP_PREFIX);
3420 x86_pop_reg (code, X86_ECX);
3421 x86_pop_reg (code, X86_ESI);
3422 x86_pop_reg (code, X86_EDI);
3425 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3427 case OP_X86_LEA_MEMBASE:
3428 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3431 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3434 /* keep alignment */
3435 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3436 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3437 code = mono_emit_stack_alloc (cfg, code, ins);
3438 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3439 if (cfg->param_area && cfg->arch.no_pushes)
3440 x86_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
3442 case OP_LOCALLOC_IMM: {
3443 guint32 size = ins->inst_imm;
3444 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3446 if (ins->flags & MONO_INST_INIT) {
3447 /* FIXME: Optimize this */
3448 x86_mov_reg_imm (code, ins->dreg, size);
3449 ins->sreg1 = ins->dreg;
3451 code = mono_emit_stack_alloc (cfg, code, ins);
3452 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3454 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3455 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3457 if (cfg->param_area && cfg->arch.no_pushes)
3458 x86_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
3462 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3463 x86_push_reg (code, ins->sreg1);
3464 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3465 (gpointer)"mono_arch_throw_exception");
3466 ins->flags |= MONO_INST_GC_CALLSITE;
3467 ins->backend.pc_offset = code - cfg->native_code;
3471 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3472 x86_push_reg (code, ins->sreg1);
3473 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3474 (gpointer)"mono_arch_rethrow_exception");
3475 ins->flags |= MONO_INST_GC_CALLSITE;
3476 ins->backend.pc_offset = code - cfg->native_code;
3479 case OP_CALL_HANDLER:
3480 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3481 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3482 x86_call_imm (code, 0);
3483 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3484 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3486 case OP_START_HANDLER: {
3487 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3488 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3489 if (cfg->param_area && cfg->arch.no_pushes) {
3490 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3494 case OP_ENDFINALLY: {
3495 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3496 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3500 case OP_ENDFILTER: {
3501 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3502 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3503 /* The local allocator will put the result into EAX */
3509 ins->inst_c0 = code - cfg->native_code;
3512 if (ins->inst_target_bb->native_offset) {
3513 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3515 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3516 if ((cfg->opt & MONO_OPT_BRANCH) &&
3517 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3518 x86_jump8 (code, 0);
3520 x86_jump32 (code, 0);
3524 x86_jump_reg (code, ins->sreg1);
3543 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3544 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3546 case OP_COND_EXC_EQ:
3547 case OP_COND_EXC_NE_UN:
3548 case OP_COND_EXC_LT:
3549 case OP_COND_EXC_LT_UN:
3550 case OP_COND_EXC_GT:
3551 case OP_COND_EXC_GT_UN:
3552 case OP_COND_EXC_GE:
3553 case OP_COND_EXC_GE_UN:
3554 case OP_COND_EXC_LE:
3555 case OP_COND_EXC_LE_UN:
3556 case OP_COND_EXC_IEQ:
3557 case OP_COND_EXC_INE_UN:
3558 case OP_COND_EXC_ILT:
3559 case OP_COND_EXC_ILT_UN:
3560 case OP_COND_EXC_IGT:
3561 case OP_COND_EXC_IGT_UN:
3562 case OP_COND_EXC_IGE:
3563 case OP_COND_EXC_IGE_UN:
3564 case OP_COND_EXC_ILE:
3565 case OP_COND_EXC_ILE_UN:
3566 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3568 case OP_COND_EXC_OV:
3569 case OP_COND_EXC_NO:
3571 case OP_COND_EXC_NC:
3572 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3574 case OP_COND_EXC_IOV:
3575 case OP_COND_EXC_INO:
3576 case OP_COND_EXC_IC:
3577 case OP_COND_EXC_INC:
3578 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3590 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3598 case OP_CMOV_INE_UN:
3599 case OP_CMOV_IGE_UN:
3600 case OP_CMOV_IGT_UN:
3601 case OP_CMOV_ILE_UN:
3602 case OP_CMOV_ILT_UN:
3603 g_assert (ins->dreg == ins->sreg1);
3604 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3607 /* floating point opcodes */
3609 double d = *(double *)ins->inst_p0;
3611 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3613 } else if (d == 1.0) {
3616 if (cfg->compile_aot) {
3617 guint32 *val = (guint32*)&d;
3618 x86_push_imm (code, val [1]);
3619 x86_push_imm (code, val [0]);
3620 x86_fld_membase (code, X86_ESP, 0, TRUE);
3621 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3624 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3625 x86_fld (code, NULL, TRUE);
3631 float f = *(float *)ins->inst_p0;
3633 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3635 } else if (f == 1.0) {
3638 if (cfg->compile_aot) {
3639 guint32 val = *(guint32*)&f;
3640 x86_push_imm (code, val);
3641 x86_fld_membase (code, X86_ESP, 0, FALSE);
3642 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3645 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3646 x86_fld (code, NULL, FALSE);
3651 case OP_STORER8_MEMBASE_REG:
3652 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3654 case OP_LOADR8_MEMBASE:
3655 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3657 case OP_STORER4_MEMBASE_REG:
3658 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3660 case OP_LOADR4_MEMBASE:
3661 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3663 case OP_ICONV_TO_R4:
3664 x86_push_reg (code, ins->sreg1);
3665 x86_fild_membase (code, X86_ESP, 0, FALSE);
3666 /* Change precision */
3667 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3668 x86_fld_membase (code, X86_ESP, 0, FALSE);
3669 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3671 case OP_ICONV_TO_R8:
3672 x86_push_reg (code, ins->sreg1);
3673 x86_fild_membase (code, X86_ESP, 0, FALSE);
3674 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3676 case OP_ICONV_TO_R_UN:
3677 x86_push_imm (code, 0);
3678 x86_push_reg (code, ins->sreg1);
3679 x86_fild_membase (code, X86_ESP, 0, TRUE);
3680 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3682 case OP_X86_FP_LOAD_I8:
3683 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3685 case OP_X86_FP_LOAD_I4:
3686 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3688 case OP_FCONV_TO_R4:
3689 /* Change precision */
3690 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3691 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3692 x86_fld_membase (code, X86_ESP, 0, FALSE);
3693 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3695 case OP_FCONV_TO_I1:
3696 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3698 case OP_FCONV_TO_U1:
3699 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3701 case OP_FCONV_TO_I2:
3702 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3704 case OP_FCONV_TO_U2:
3705 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3707 case OP_FCONV_TO_I4:
3709 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3711 case OP_FCONV_TO_I8:
3712 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3713 x86_fnstcw_membase(code, X86_ESP, 0);
3714 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3715 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3716 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3717 x86_fldcw_membase (code, X86_ESP, 2);
3718 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3719 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3720 x86_pop_reg (code, ins->dreg);
3721 x86_pop_reg (code, ins->backend.reg3);
3722 x86_fldcw_membase (code, X86_ESP, 0);
3723 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3725 case OP_LCONV_TO_R8_2:
3726 x86_push_reg (code, ins->sreg2);
3727 x86_push_reg (code, ins->sreg1);
3728 x86_fild_membase (code, X86_ESP, 0, TRUE);
3729 /* Change precision */
3730 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3731 x86_fld_membase (code, X86_ESP, 0, TRUE);
3732 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3734 case OP_LCONV_TO_R4_2:
3735 x86_push_reg (code, ins->sreg2);
3736 x86_push_reg (code, ins->sreg1);
3737 x86_fild_membase (code, X86_ESP, 0, TRUE);
3738 /* Change precision */
3739 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3740 x86_fld_membase (code, X86_ESP, 0, FALSE);
3741 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3743 case OP_LCONV_TO_R_UN_2: {
3744 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3747 /* load 64bit integer to FP stack */
3748 x86_push_reg (code, ins->sreg2);
3749 x86_push_reg (code, ins->sreg1);
3750 x86_fild_membase (code, X86_ESP, 0, TRUE);
3752 /* test if lreg is negative */
3753 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3754 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3756 /* add correction constant mn */
3757 if (cfg->compile_aot) {
3758 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3759 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3760 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3761 x86_fld80_membase (code, X86_ESP, 2);
3762 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3764 x86_fld80_mem (code, mn);
3766 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3768 x86_patch (br, code);
3770 /* Change precision */
3771 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3772 x86_fld_membase (code, X86_ESP, 0, TRUE);
3774 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3778 case OP_LCONV_TO_OVF_I:
3779 case OP_LCONV_TO_OVF_I4_2: {
3780 guint8 *br [3], *label [1];
3784 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3786 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3788 /* If the low word top bit is set, see if we are negative */
3789 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3790 /* We are not negative (no top bit set, check for our top word to be zero */
3791 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3792 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3795 /* throw exception */
3796 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3798 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3799 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3800 x86_jump8 (code, 0);
3802 x86_jump32 (code, 0);
3804 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3805 x86_jump32 (code, 0);
3809 x86_patch (br [0], code);
3810 /* our top bit is set, check that top word is 0xfffffff */
3811 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3813 x86_patch (br [1], code);
3814 /* nope, emit exception */
3815 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3816 x86_patch (br [2], label [0]);
3818 if (ins->dreg != ins->sreg1)
3819 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3823 /* Not needed on the fp stack */
3826 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3829 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3832 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3835 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3843 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3848 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3855 * it really doesn't make sense to inline all this code,
3856 * it's here just to show that things may not be as simple
3859 guchar *check_pos, *end_tan, *pop_jump;
3860 x86_push_reg (code, X86_EAX);
3863 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3865 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3866 x86_fstp (code, 0); /* pop the 1.0 */
3868 x86_jump8 (code, 0);
3870 x86_fp_op (code, X86_FADD, 0);
3874 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3876 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3879 x86_patch (pop_jump, code);
3880 x86_fstp (code, 0); /* pop the 1.0 */
3881 x86_patch (check_pos, code);
3882 x86_patch (end_tan, code);
3884 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3885 x86_pop_reg (code, X86_EAX);
3892 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3901 g_assert (cfg->opt & MONO_OPT_CMOV);
3902 g_assert (ins->dreg == ins->sreg1);
3903 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3904 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3907 g_assert (cfg->opt & MONO_OPT_CMOV);
3908 g_assert (ins->dreg == ins->sreg1);
3909 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3910 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3913 g_assert (cfg->opt & MONO_OPT_CMOV);
3914 g_assert (ins->dreg == ins->sreg1);
3915 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3916 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3919 g_assert (cfg->opt & MONO_OPT_CMOV);
3920 g_assert (ins->dreg == ins->sreg1);
3921 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3922 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3928 x86_fxch (code, ins->inst_imm);
3933 x86_push_reg (code, X86_EAX);
3934 /* we need to exchange ST(0) with ST(1) */
3937 /* this requires a loop, because fprem somtimes
3938 * returns a partial remainder */
3940 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3941 /* x86_fprem1 (code); */
3944 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3946 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3952 x86_pop_reg (code, X86_EAX);
3956 if (cfg->opt & MONO_OPT_FCMOV) {
3957 x86_fcomip (code, 1);
3961 /* this overwrites EAX */
3962 EMIT_FPCOMPARE(code);
3963 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3967 if (cfg->opt & MONO_OPT_FCMOV) {
3968 /* zeroing the register at the start results in
3969 * shorter and faster code (we can also remove the widening op)
3971 guchar *unordered_check;
3972 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3973 x86_fcomip (code, 1);
3975 unordered_check = code;
3976 x86_branch8 (code, X86_CC_P, 0, FALSE);
3977 if (ins->opcode == OP_FCEQ) {
3978 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3979 x86_patch (unordered_check, code);
3981 guchar *jump_to_end;
3982 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3984 x86_jump8 (code, 0);
3985 x86_patch (unordered_check, code);
3986 x86_inc_reg (code, ins->dreg);
3987 x86_patch (jump_to_end, code);
3992 if (ins->dreg != X86_EAX)
3993 x86_push_reg (code, X86_EAX);
3995 EMIT_FPCOMPARE(code);
3996 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3997 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3998 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3999 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4001 if (ins->dreg != X86_EAX)
4002 x86_pop_reg (code, X86_EAX);
4006 if (cfg->opt & MONO_OPT_FCMOV) {
4007 /* zeroing the register at the start results in
4008 * shorter and faster code (we can also remove the widening op)
4010 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4011 x86_fcomip (code, 1);
4013 if (ins->opcode == OP_FCLT_UN) {
4014 guchar *unordered_check = code;
4015 guchar *jump_to_end;
4016 x86_branch8 (code, X86_CC_P, 0, FALSE);
4017 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4019 x86_jump8 (code, 0);
4020 x86_patch (unordered_check, code);
4021 x86_inc_reg (code, ins->dreg);
4022 x86_patch (jump_to_end, code);
4024 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4028 if (ins->dreg != X86_EAX)
4029 x86_push_reg (code, X86_EAX);
4031 EMIT_FPCOMPARE(code);
4032 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4033 if (ins->opcode == OP_FCLT_UN) {
4034 guchar *is_not_zero_check, *end_jump;
4035 is_not_zero_check = code;
4036 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4038 x86_jump8 (code, 0);
4039 x86_patch (is_not_zero_check, code);
4040 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4042 x86_patch (end_jump, code);
4044 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4045 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4047 if (ins->dreg != X86_EAX)
4048 x86_pop_reg (code, X86_EAX);
4051 guchar *unordered_check;
4052 guchar *jump_to_end;
4053 if (cfg->opt & MONO_OPT_FCMOV) {
4054 /* zeroing the register at the start results in
4055 * shorter and faster code (we can also remove the widening op)
4057 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4058 x86_fcomip (code, 1);
4060 unordered_check = code;
4061 x86_branch8 (code, X86_CC_P, 0, FALSE);
4062 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
4063 x86_patch (unordered_check, code);
4066 if (ins->dreg != X86_EAX)
4067 x86_push_reg (code, X86_EAX);
4069 EMIT_FPCOMPARE(code);
4070 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4071 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4072 unordered_check = code;
4073 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4075 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4076 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
4077 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4079 x86_jump8 (code, 0);
4080 x86_patch (unordered_check, code);
4081 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4082 x86_patch (jump_to_end, code);
4084 if (ins->dreg != X86_EAX)
4085 x86_pop_reg (code, X86_EAX);
4090 if (cfg->opt & MONO_OPT_FCMOV) {
4091 /* zeroing the register at the start results in
4092 * shorter and faster code (we can also remove the widening op)
4094 guchar *unordered_check;
4095 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4096 x86_fcomip (code, 1);
4098 if (ins->opcode == OP_FCGT) {
4099 unordered_check = code;
4100 x86_branch8 (code, X86_CC_P, 0, FALSE);
4101 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4102 x86_patch (unordered_check, code);
4104 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4108 if (ins->dreg != X86_EAX)
4109 x86_push_reg (code, X86_EAX);
4111 EMIT_FPCOMPARE(code);
4112 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4113 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4114 if (ins->opcode == OP_FCGT_UN) {
4115 guchar *is_not_zero_check, *end_jump;
4116 is_not_zero_check = code;
4117 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4119 x86_jump8 (code, 0);
4120 x86_patch (is_not_zero_check, code);
4121 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4123 x86_patch (end_jump, code);
4125 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4126 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4128 if (ins->dreg != X86_EAX)
4129 x86_pop_reg (code, X86_EAX);
4132 guchar *unordered_check;
4133 guchar *jump_to_end;
4134 if (cfg->opt & MONO_OPT_FCMOV) {
4135 /* zeroing the register at the start results in
4136 * shorter and faster code (we can also remove the widening op)
4138 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4139 x86_fcomip (code, 1);
4141 unordered_check = code;
4142 x86_branch8 (code, X86_CC_P, 0, FALSE);
4143 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4144 x86_patch (unordered_check, code);
4147 if (ins->dreg != X86_EAX)
4148 x86_push_reg (code, X86_EAX);
4150 EMIT_FPCOMPARE(code);
4151 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4152 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4153 unordered_check = code;
4154 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4156 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4157 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4158 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4160 x86_jump8 (code, 0);
4161 x86_patch (unordered_check, code);
4162 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4163 x86_patch (jump_to_end, code);
4165 if (ins->dreg != X86_EAX)
4166 x86_pop_reg (code, X86_EAX);
4170 if (cfg->opt & MONO_OPT_FCMOV) {
4171 guchar *jump = code;
4172 x86_branch8 (code, X86_CC_P, 0, TRUE);
4173 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4174 x86_patch (jump, code);
4177 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4178 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4181 /* Branch if C013 != 100 */
4182 if (cfg->opt & MONO_OPT_FCMOV) {
4183 /* branch if !ZF or (PF|CF) */
4184 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4185 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4186 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4189 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4190 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4193 if (cfg->opt & MONO_OPT_FCMOV) {
4194 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4197 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4200 if (cfg->opt & MONO_OPT_FCMOV) {
4201 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4202 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4205 if (ins->opcode == OP_FBLT_UN) {
4206 guchar *is_not_zero_check, *end_jump;
4207 is_not_zero_check = code;
4208 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4210 x86_jump8 (code, 0);
4211 x86_patch (is_not_zero_check, code);
4212 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4214 x86_patch (end_jump, code);
4216 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4220 if (cfg->opt & MONO_OPT_FCMOV) {
4221 if (ins->opcode == OP_FBGT) {
4224 /* skip branch if C1=1 */
4226 x86_branch8 (code, X86_CC_P, 0, FALSE);
4227 /* branch if (C0 | C3) = 1 */
4228 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4229 x86_patch (br1, code);
4231 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4235 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4236 if (ins->opcode == OP_FBGT_UN) {
4237 guchar *is_not_zero_check, *end_jump;
4238 is_not_zero_check = code;
4239 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4241 x86_jump8 (code, 0);
4242 x86_patch (is_not_zero_check, code);
4243 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4245 x86_patch (end_jump, code);
4247 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4250 /* Branch if C013 == 100 or 001 */
4251 if (cfg->opt & MONO_OPT_FCMOV) {
4254 /* skip branch if C1=1 */
4256 x86_branch8 (code, X86_CC_P, 0, FALSE);
4257 /* branch if (C0 | C3) = 1 */
4258 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4259 x86_patch (br1, code);
4262 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4263 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4264 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4265 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4268 /* Branch if C013 == 000 */
4269 if (cfg->opt & MONO_OPT_FCMOV) {
4270 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4273 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4276 /* Branch if C013=000 or 100 */
4277 if (cfg->opt & MONO_OPT_FCMOV) {
4280 /* skip branch if C1=1 */
4282 x86_branch8 (code, X86_CC_P, 0, FALSE);
4283 /* branch if C0=0 */
4284 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4285 x86_patch (br1, code);
4288 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4289 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4290 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4293 /* Branch if C013 != 001 */
4294 if (cfg->opt & MONO_OPT_FCMOV) {
4295 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4296 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4299 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4300 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4304 x86_push_reg (code, X86_EAX);
4307 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4308 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4309 x86_pop_reg (code, X86_EAX);
4311 /* Have to clean up the fp stack before throwing the exception */
4313 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4316 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4318 x86_patch (br1, code);
4322 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4325 case OP_TLS_GET_REG: {
4326 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4330 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4333 case OP_TLS_SET_REG: {
4334 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4337 case OP_MEMORY_BARRIER: {
4338 /* x86 only needs barrier for StoreLoad and FullBarrier */
4339 switch (ins->backend.memory_barrier_kind) {
4340 case StoreLoadBarrier:
4342 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4343 x86_prefix (code, X86_LOCK_PREFIX);
4344 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4349 case OP_ATOMIC_ADD_I4: {
4350 int dreg = ins->dreg;
4352 if (dreg == ins->inst_basereg) {
4353 x86_push_reg (code, ins->sreg2);
4357 if (dreg != ins->sreg2)
4358 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
4360 x86_prefix (code, X86_LOCK_PREFIX);
4361 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4363 if (dreg != ins->dreg) {
4364 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4365 x86_pop_reg (code, dreg);
4370 case OP_ATOMIC_ADD_NEW_I4: {
4371 int dreg = ins->dreg;
4373 g_assert (cfg->has_atomic_add_new_i4);
4375 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4376 if (ins->sreg2 == dreg) {
4377 if (dreg == X86_EBX) {
4379 if (ins->inst_basereg == X86_EDI)
4383 if (ins->inst_basereg == X86_EBX)
4386 } else if (ins->inst_basereg == dreg) {
4387 if (dreg == X86_EBX) {
4389 if (ins->sreg2 == X86_EDI)
4393 if (ins->sreg2 == X86_EBX)
4398 if (dreg != ins->dreg) {
4399 x86_push_reg (code, dreg);
4402 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4403 x86_prefix (code, X86_LOCK_PREFIX);
4404 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4405 /* dreg contains the old value, add with sreg2 value */
4406 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4408 if (ins->dreg != dreg) {
4409 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4410 x86_pop_reg (code, dreg);
4415 case OP_ATOMIC_EXCHANGE_I4: {
4417 int sreg2 = ins->sreg2;
4418 int breg = ins->inst_basereg;
4420 g_assert (cfg->has_atomic_exchange_i4);
4422 /* cmpxchg uses eax as comperand, need to make sure we can use it
4423 * hack to overcome limits in x86 reg allocator
4424 * (req: dreg == eax and sreg2 != eax and breg != eax)
4426 g_assert (ins->dreg == X86_EAX);
4428 /* We need the EAX reg for the cmpxchg */
4429 if (ins->sreg2 == X86_EAX) {
4430 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4431 x86_push_reg (code, sreg2);
4432 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4435 if (breg == X86_EAX) {
4436 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4437 x86_push_reg (code, breg);
4438 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4441 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4443 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4444 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4445 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4446 x86_patch (br [1], br [0]);
4448 if (breg != ins->inst_basereg)
4449 x86_pop_reg (code, breg);
4451 if (ins->sreg2 != sreg2)
4452 x86_pop_reg (code, sreg2);
4456 case OP_ATOMIC_CAS_I4: {
4457 g_assert (ins->dreg == X86_EAX);
4458 g_assert (ins->sreg3 == X86_EAX);
4459 g_assert (ins->sreg1 != X86_EAX);
4460 g_assert (ins->sreg1 != ins->sreg2);
4462 x86_prefix (code, X86_LOCK_PREFIX);
4463 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4466 case OP_CARD_TABLE_WBARRIER: {
4467 int ptr = ins->sreg1;
4468 int value = ins->sreg2;
4470 int nursery_shift, card_table_shift;
4471 gpointer card_table_mask;
4472 size_t nursery_size;
4473 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4474 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4475 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4478 * We need one register we can clobber, we choose EDX and make sreg1
4479 * fixed EAX to work around limitations in the local register allocator.
4480 * sreg2 might get allocated to EDX, but that is not a problem since
4481 * we use it before clobbering EDX.
4483 g_assert (ins->sreg1 == X86_EAX);
4486 * This is the code we produce:
4489 * edx >>= nursery_shift
4490 * cmp edx, (nursery_start >> nursery_shift)
4493 * edx >>= card_table_shift
4494 * card_table[edx] = 1
4498 if (card_table_nursery_check) {
4499 if (value != X86_EDX)
4500 x86_mov_reg_reg (code, X86_EDX, value, 4);
4501 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4502 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4503 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4505 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4506 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4507 if (card_table_mask)
4508 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4509 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4510 if (card_table_nursery_check)
4511 x86_patch (br, code);
4514 #ifdef MONO_ARCH_SIMD_INTRINSICS
4516 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4519 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4522 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4525 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4528 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4531 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4534 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4535 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4538 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4541 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4544 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4547 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4550 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4553 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4556 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4559 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4562 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4565 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4568 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4571 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4574 case OP_PSHUFLEW_HIGH:
4575 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4576 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4578 case OP_PSHUFLEW_LOW:
4579 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4580 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4583 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4584 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4587 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4588 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4591 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4592 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4596 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4599 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4602 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4605 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4608 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4611 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4614 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4615 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4618 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4621 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4624 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4627 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4630 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4633 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4636 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4639 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4642 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4645 case OP_EXTRACT_MASK:
4646 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4650 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4653 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4656 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4660 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4663 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4666 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4669 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4673 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4676 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4679 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4682 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4686 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4689 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4692 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4696 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4699 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4702 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4706 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4709 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4713 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4716 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4719 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4723 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4726 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4729 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4733 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4736 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4739 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4742 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4746 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4749 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4752 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4755 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4758 case OP_PSUM_ABS_DIFF:
4759 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4762 case OP_UNPACK_LOWB:
4763 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4765 case OP_UNPACK_LOWW:
4766 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4768 case OP_UNPACK_LOWD:
4769 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4771 case OP_UNPACK_LOWQ:
4772 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4774 case OP_UNPACK_LOWPS:
4775 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4777 case OP_UNPACK_LOWPD:
4778 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4781 case OP_UNPACK_HIGHB:
4782 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4784 case OP_UNPACK_HIGHW:
4785 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4787 case OP_UNPACK_HIGHD:
4788 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4790 case OP_UNPACK_HIGHQ:
4791 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4793 case OP_UNPACK_HIGHPS:
4794 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4796 case OP_UNPACK_HIGHPD:
4797 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4801 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4804 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4807 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4810 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4813 case OP_PADDB_SAT_UN:
4814 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4816 case OP_PSUBB_SAT_UN:
4817 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4819 case OP_PADDW_SAT_UN:
4820 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4822 case OP_PSUBW_SAT_UN:
4823 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4827 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4830 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4833 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4836 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4840 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4843 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4846 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4848 case OP_PMULW_HIGH_UN:
4849 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4852 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4856 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4859 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4863 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4866 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4870 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4873 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4877 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4880 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4884 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4887 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4891 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4894 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4898 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4901 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4905 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4908 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4912 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4915 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4919 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4921 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4922 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4926 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4928 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4929 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4933 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4935 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4936 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4940 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4942 case OP_EXTRACTX_U2:
4943 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4945 case OP_INSERTX_U1_SLOW:
4946 /*sreg1 is the extracted ireg (scratch)
4947 /sreg2 is the to be inserted ireg (scratch)
4948 /dreg is the xreg to receive the value*/
4950 /*clear the bits from the extracted word*/
4951 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4952 /*shift the value to insert if needed*/
4953 if (ins->inst_c0 & 1)
4954 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4955 /*join them together*/
4956 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4957 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4959 case OP_INSERTX_I4_SLOW:
4960 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4961 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4962 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4965 case OP_INSERTX_R4_SLOW:
4966 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4967 /*TODO if inst_c0 == 0 use movss*/
4968 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4969 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4971 case OP_INSERTX_R8_SLOW:
4972 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4973 if (cfg->verbose_level)
4974 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4976 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4978 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4981 case OP_STOREX_MEMBASE_REG:
4982 case OP_STOREX_MEMBASE:
4983 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4985 case OP_LOADX_MEMBASE:
4986 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4988 case OP_LOADX_ALIGNED_MEMBASE:
4989 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4991 case OP_STOREX_ALIGNED_MEMBASE_REG:
4992 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4994 case OP_STOREX_NTA_MEMBASE_REG:
4995 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4997 case OP_PREFETCH_MEMBASE:
4998 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5002 /*FIXME the peephole pass should have killed this*/
5003 if (ins->dreg != ins->sreg1)
5004 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5007 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
5009 case OP_ICONV_TO_R8_RAW:
5010 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
5011 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
5014 case OP_FCONV_TO_R8_X:
5015 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
5016 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5019 case OP_XCONV_R8_TO_I4:
5020 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
5021 switch (ins->backend.source_opcode) {
5022 case OP_FCONV_TO_I1:
5023 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5025 case OP_FCONV_TO_U1:
5026 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5028 case OP_FCONV_TO_I2:
5029 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5031 case OP_FCONV_TO_U2:
5032 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5038 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
5039 /*The +4 is to get a mov ?h, ?l over the same reg.*/
5040 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
5041 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
5042 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
5043 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5046 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
5047 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
5048 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5051 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
5052 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5055 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
5056 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5057 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5060 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
5061 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5062 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
5066 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
5069 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
5072 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
5075 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
5078 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
5081 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
5084 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
5087 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
5091 case OP_LIVERANGE_START: {
5092 if (cfg->verbose_level > 1)
5093 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5094 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5097 case OP_LIVERANGE_END: {
5098 if (cfg->verbose_level > 1)
5099 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5100 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5103 case OP_NACL_GC_SAFE_POINT: {
5104 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
5105 if (cfg->compile_aot)
5106 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5110 x86_test_mem_imm8 (code, (gpointer)&__nacl_thread_suspension_needed, 0xFFFFFFFF);
5111 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
5112 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5113 x86_patch (br[0], code);
5118 case OP_GC_LIVENESS_DEF:
5119 case OP_GC_LIVENESS_USE:
5120 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5121 ins->backend.pc_offset = code - cfg->native_code;
5123 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5124 ins->backend.pc_offset = code - cfg->native_code;
5125 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5128 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
5131 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
5134 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
5135 g_assert_not_reached ();
5138 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
5139 #ifndef __native_client_codegen__
5140 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5141 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5142 g_assert_not_reached ();
5143 #endif /* __native_client_codegen__ */
5149 cfg->code_len = code - cfg->native_code;
5152 #endif /* DISABLE_JIT */
5155 mono_arch_register_lowlevel_calls (void)
5160 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
5162 MonoJumpInfo *patch_info;
5163 gboolean compile_aot = !run_cctors;
5165 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5166 unsigned char *ip = patch_info->ip.i + code;
5167 const unsigned char *target;
5170 switch (patch_info->type) {
5171 case MONO_PATCH_INFO_BB:
5172 case MONO_PATCH_INFO_LABEL:
5175 /* No need to patch these */
5180 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5182 switch (patch_info->type) {
5183 case MONO_PATCH_INFO_IP:
5184 *((gconstpointer *)(ip)) = target;
5186 case MONO_PATCH_INFO_CLASS_INIT: {
5188 /* Might already been changed to a nop */
5189 x86_call_code (code, 0);
5190 x86_patch (ip, target);
5193 case MONO_PATCH_INFO_ABS:
5194 case MONO_PATCH_INFO_METHOD:
5195 case MONO_PATCH_INFO_METHOD_JUMP:
5196 case MONO_PATCH_INFO_INTERNAL_METHOD:
5197 case MONO_PATCH_INFO_BB:
5198 case MONO_PATCH_INFO_LABEL:
5199 case MONO_PATCH_INFO_RGCTX_FETCH:
5200 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
5201 case MONO_PATCH_INFO_MONITOR_ENTER:
5202 case MONO_PATCH_INFO_MONITOR_EXIT:
5203 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5204 #if defined(__native_client_codegen__) && defined(__native_client__)
5205 if (nacl_is_code_address (code)) {
5206 /* For tail calls, code is patched after being installed */
5207 /* but not through the normal "patch callsite" method. */
5208 unsigned char buf[kNaClAlignment];
5209 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5210 unsigned char *_target = target;
5212 /* All patch targets modified in x86_patch */
5213 /* are IP relative. */
5214 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5215 memcpy (buf, aligned_code, kNaClAlignment);
5216 /* Patch a temp buffer of bundle size, */
5217 /* then install to actual location. */
5218 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5219 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5220 g_assert (ret == 0);
5223 x86_patch (ip, target);
5226 x86_patch (ip, target);
5229 case MONO_PATCH_INFO_NONE:
5231 case MONO_PATCH_INFO_R4:
5232 case MONO_PATCH_INFO_R8: {
5233 guint32 offset = mono_arch_get_patch_offset (ip);
5234 *((gconstpointer *)(ip + offset)) = target;
5238 guint32 offset = mono_arch_get_patch_offset (ip);
5239 #if !defined(__native_client__)
5240 *((gconstpointer *)(ip + offset)) = target;
5242 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5250 static G_GNUC_UNUSED void
5251 stack_unaligned (MonoMethod *m, gpointer caller)
5253 printf ("%s\n", mono_method_full_name (m, TRUE));
5254 g_assert_not_reached ();
5258 mono_arch_emit_prolog (MonoCompile *cfg)
5260 MonoMethod *method = cfg->method;
5262 MonoMethodSignature *sig;
5264 int alloc_size, pos, max_offset, i, cfa_offset;
5266 gboolean need_stack_frame;
5267 #ifdef __native_client_codegen__
5268 guint alignment_check;
5271 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5273 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5274 cfg->code_size += 512;
5276 #if defined(__default_codegen__)
5277 code = cfg->native_code = g_malloc (cfg->code_size);
5278 #elif defined(__native_client_codegen__)
5279 /* native_code_alloc is not 32-byte aligned, native_code is. */
5280 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5281 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5283 /* Align native_code to next nearest kNaclAlignment byte. */
5284 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5285 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5287 code = cfg->native_code;
5289 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5290 g_assert(alignment_check == 0);
5297 /* Check that the stack is aligned on osx */
5298 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5299 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5300 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5302 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5303 x86_push_membase (code, X86_ESP, 0);
5304 x86_push_imm (code, cfg->method);
5305 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5306 x86_call_reg (code, X86_EAX);
5307 x86_patch (br [0], code);
5311 /* Offset between RSP and the CFA */
5315 cfa_offset = sizeof (gpointer);
5316 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5317 // IP saved at CFA - 4
5318 /* There is no IP reg on x86 */
5319 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5320 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5322 need_stack_frame = needs_stack_frame (cfg);
5324 if (need_stack_frame) {
5325 x86_push_reg (code, X86_EBP);
5326 cfa_offset += sizeof (gpointer);
5327 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5328 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5329 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5330 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5331 /* These are handled automatically by the stack marking code */
5332 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5334 cfg->frame_reg = X86_ESP;
5337 if (cfg->arch.no_pushes) {
5338 cfg->stack_offset += cfg->param_area;
5339 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5342 alloc_size = cfg->stack_offset;
5345 if (!method->save_lmf) {
5346 if (cfg->used_int_regs & (1 << X86_EBX)) {
5347 x86_push_reg (code, X86_EBX);
5349 cfa_offset += sizeof (gpointer);
5350 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5351 /* These are handled automatically by the stack marking code */
5352 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5355 if (cfg->used_int_regs & (1 << X86_EDI)) {
5356 x86_push_reg (code, X86_EDI);
5358 cfa_offset += sizeof (gpointer);
5359 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5360 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5363 if (cfg->used_int_regs & (1 << X86_ESI)) {
5364 x86_push_reg (code, X86_ESI);
5366 cfa_offset += sizeof (gpointer);
5367 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5368 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5374 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5375 if (mono_do_x86_stack_align && need_stack_frame) {
5376 int tot = alloc_size + pos + 4; /* ret ip */
5377 if (need_stack_frame)
5379 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5381 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5382 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5383 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5387 cfg->arch.sp_fp_offset = alloc_size + pos;
5390 /* See mono_emit_stack_alloc */
5391 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5392 guint32 remaining_size = alloc_size;
5393 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5394 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5395 guint32 offset = code - cfg->native_code;
5396 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5397 while (required_code_size >= (cfg->code_size - offset))
5398 cfg->code_size *= 2;
5399 cfg->native_code = mono_realloc_native_code(cfg);
5400 code = cfg->native_code + offset;
5401 cfg->stat_code_reallocs++;
5403 while (remaining_size >= 0x1000) {
5404 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5405 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5406 remaining_size -= 0x1000;
5409 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5411 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5414 g_assert (need_stack_frame);
5417 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5418 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5419 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5422 #if DEBUG_STACK_ALIGNMENT
5423 /* check the stack is aligned */
5424 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5425 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5426 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5427 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5428 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5429 x86_breakpoint (code);
5433 /* compute max_offset in order to use short forward jumps */
5435 if (cfg->opt & MONO_OPT_BRANCH) {
5436 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5438 bb->max_offset = max_offset;
5440 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5442 /* max alignment for loops */
5443 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5444 max_offset += LOOP_ALIGNMENT;
5445 #ifdef __native_client_codegen__
5446 /* max alignment for native client */
5447 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5448 max_offset += kNaClAlignment;
5450 MONO_BB_FOR_EACH_INS (bb, ins) {
5451 if (ins->opcode == OP_LABEL)
5452 ins->inst_c1 = max_offset;
5453 #ifdef __native_client_codegen__
5454 switch (ins->opcode)
5466 case OP_VOIDCALL_REG:
5468 case OP_FCALL_MEMBASE:
5469 case OP_LCALL_MEMBASE:
5470 case OP_VCALL_MEMBASE:
5471 case OP_VCALL2_MEMBASE:
5472 case OP_VOIDCALL_MEMBASE:
5473 case OP_CALL_MEMBASE:
5474 max_offset += kNaClAlignment;
5477 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5480 #endif /* __native_client_codegen__ */
5481 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5486 /* store runtime generic context */
5487 if (cfg->rgctx_var) {
5488 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5490 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5493 if (method->save_lmf)
5494 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5496 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5497 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5499 /* load arguments allocated to register from the stack */
5500 sig = mono_method_signature (method);
5503 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5504 inst = cfg->args [pos];
5505 if (inst->opcode == OP_REGVAR) {
5506 g_assert (need_stack_frame);
5507 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5508 if (cfg->verbose_level > 2)
5509 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5514 cfg->code_len = code - cfg->native_code;
5516 g_assert (cfg->code_len < cfg->code_size);
5522 mono_arch_emit_epilog (MonoCompile *cfg)
5524 MonoMethod *method = cfg->method;
5525 MonoMethodSignature *sig = mono_method_signature (method);
5527 guint32 stack_to_pop;
5529 int max_epilog_size = 16;
5531 gboolean need_stack_frame = needs_stack_frame (cfg);
5533 if (cfg->method->save_lmf)
5534 max_epilog_size += 128;
5536 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5537 cfg->code_size *= 2;
5538 cfg->native_code = mono_realloc_native_code(cfg);
5539 cfg->stat_code_reallocs++;
5542 code = cfg->native_code + cfg->code_len;
5544 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5545 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5547 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5550 if (method->save_lmf) {
5551 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5553 gboolean supported = FALSE;
5555 if (cfg->compile_aot) {
5556 #if defined(__APPLE__) || defined(__linux__)
5559 } else if (mono_get_jit_tls_offset () != -1) {
5563 /* check if we need to restore protection of the stack after a stack overflow */
5565 if (cfg->compile_aot) {
5566 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5568 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5570 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5573 /* we load the value in a separate instruction: this mechanism may be
5574 * used later as a safer way to do thread interruption
5576 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5577 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5579 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5580 /* note that the call trampoline will preserve eax/edx */
5581 x86_call_reg (code, X86_ECX);
5582 x86_patch (patch, code);
5584 /* FIXME: maybe save the jit tls in the prolog */
5587 /* restore caller saved regs */
5588 if (cfg->used_int_regs & (1 << X86_EBX)) {
5589 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
5592 if (cfg->used_int_regs & (1 << X86_EDI)) {
5593 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
5595 if (cfg->used_int_regs & (1 << X86_ESI)) {
5596 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
5599 /* EBP is restored by LEAVE */
5601 for (i = 0; i < X86_NREG; ++i) {
5602 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5608 g_assert (need_stack_frame);
5609 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5613 g_assert (need_stack_frame);
5614 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5617 if (cfg->used_int_regs & (1 << X86_ESI)) {
5618 x86_pop_reg (code, X86_ESI);
5620 if (cfg->used_int_regs & (1 << X86_EDI)) {
5621 x86_pop_reg (code, X86_EDI);
5623 if (cfg->used_int_regs & (1 << X86_EBX)) {
5624 x86_pop_reg (code, X86_EBX);
5628 /* Load returned vtypes into registers if needed */
5629 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5630 if (cinfo->ret.storage == ArgValuetypeInReg) {
5631 for (quad = 0; quad < 2; quad ++) {
5632 switch (cinfo->ret.pair_storage [quad]) {
5634 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5636 case ArgOnFloatFpStack:
5637 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5639 case ArgOnDoubleFpStack:
5640 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5645 g_assert_not_reached ();
5650 if (need_stack_frame)
5653 if (CALLCONV_IS_STDCALL (sig)) {
5654 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5656 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5657 } else if (cinfo->vtype_retaddr && !cfg->arch.no_pushes)
5663 g_assert (need_stack_frame);
5664 x86_ret_imm (code, stack_to_pop);
5669 cfg->code_len = code - cfg->native_code;
5671 g_assert (cfg->code_len < cfg->code_size);
5675 mono_arch_emit_exceptions (MonoCompile *cfg)
5677 MonoJumpInfo *patch_info;
5680 MonoClass *exc_classes [16];
5681 guint8 *exc_throw_start [16], *exc_throw_end [16];
5685 /* Compute needed space */
5686 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5687 if (patch_info->type == MONO_PATCH_INFO_EXC)
5692 * make sure we have enough space for exceptions
5693 * 16 is the size of two push_imm instructions and a call
5695 if (cfg->compile_aot)
5696 code_size = exc_count * 32;
5698 code_size = exc_count * 16;
5700 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5701 cfg->code_size *= 2;
5702 cfg->native_code = mono_realloc_native_code(cfg);
5703 cfg->stat_code_reallocs++;
5706 code = cfg->native_code + cfg->code_len;
5709 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5710 switch (patch_info->type) {
5711 case MONO_PATCH_INFO_EXC: {
5712 MonoClass *exc_class;
5716 x86_patch (patch_info->ip.i + cfg->native_code, code);
5718 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5719 g_assert (exc_class);
5720 throw_ip = patch_info->ip.i;
5722 /* Find a throw sequence for the same exception class */
5723 for (i = 0; i < nthrows; ++i)
5724 if (exc_classes [i] == exc_class)
5727 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5728 x86_jump_code (code, exc_throw_start [i]);
5729 patch_info->type = MONO_PATCH_INFO_NONE;
5734 /* Compute size of code following the push <OFFSET> */
5735 #if defined(__default_codegen__)
5737 #elif defined(__native_client_codegen__)
5738 code = mono_nacl_align (code);
5739 size = kNaClAlignment;
5741 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5743 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5744 /* Use the shorter form */
5746 x86_push_imm (code, 0);
5750 x86_push_imm (code, 0xf0f0f0f0);
5755 exc_classes [nthrows] = exc_class;
5756 exc_throw_start [nthrows] = code;
5759 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5760 patch_info->data.name = "mono_arch_throw_corlib_exception";
5761 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5762 patch_info->ip.i = code - cfg->native_code;
5763 x86_call_code (code, 0);
5764 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5769 exc_throw_end [nthrows] = code;
5781 cfg->code_len = code - cfg->native_code;
5783 g_assert (cfg->code_len < cfg->code_size);
5787 mono_arch_flush_icache (guint8 *code, gint size)
5793 mono_arch_flush_register_windows (void)
5798 mono_arch_is_inst_imm (gint64 imm)
5804 mono_arch_finish_init (void)
5806 if (!g_getenv ("MONO_NO_TLS")) {
5807 #ifndef TARGET_WIN32
5809 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5816 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5820 #ifdef MONO_ARCH_HAVE_IMT
5822 // Linear handler, the bsearch head compare is shorter
5823 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5824 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5825 // x86_patch(ins,target)
5826 //[1 + 5] x86_jump_mem(inst,mem)
5829 #if defined(__default_codegen__)
5830 #define BR_SMALL_SIZE 2
5831 #define BR_LARGE_SIZE 5
5832 #elif defined(__native_client_codegen__)
5833 /* I suspect the size calculation below is actually incorrect. */
5834 /* TODO: fix the calculation that uses these sizes. */
5835 #define BR_SMALL_SIZE 16
5836 #define BR_LARGE_SIZE 12
5837 #endif /*__native_client_codegen__*/
5838 #define JUMP_IMM_SIZE 6
5839 #define ENABLE_WRONG_METHOD_CHECK 0
5843 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5845 int i, distance = 0;
5846 for (i = start; i < target; ++i)
5847 distance += imt_entries [i]->chunk_size;
5852 * LOCKING: called with the domain lock held
5855 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5856 gpointer fail_tramp)
5860 guint8 *code, *start;
5862 for (i = 0; i < count; ++i) {
5863 MonoIMTCheckItem *item = imt_entries [i];
5864 if (item->is_equals) {
5865 if (item->check_target_idx) {
5866 if (!item->compare_done)
5867 item->chunk_size += CMP_SIZE;
5868 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5871 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5873 item->chunk_size += JUMP_IMM_SIZE;
5874 #if ENABLE_WRONG_METHOD_CHECK
5875 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5880 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5881 imt_entries [item->check_target_idx]->compare_done = TRUE;
5883 size += item->chunk_size;
5885 #if defined(__native_client__) && defined(__native_client_codegen__)
5886 /* In Native Client, we don't re-use thunks, allocate from the */
5887 /* normal code manager paths. */
5888 size = NACL_BUNDLE_ALIGN_UP (size);
5889 code = mono_domain_code_reserve (domain, size);
5892 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5894 code = mono_domain_code_reserve (domain, size);
5897 for (i = 0; i < count; ++i) {
5898 MonoIMTCheckItem *item = imt_entries [i];
5899 item->code_target = code;
5900 if (item->is_equals) {
5901 if (item->check_target_idx) {
5902 if (!item->compare_done)
5903 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5904 item->jmp_code = code;
5905 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5906 if (item->has_target_code)
5907 x86_jump_code (code, item->value.target_code);
5909 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5912 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5913 item->jmp_code = code;
5914 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5915 if (item->has_target_code)
5916 x86_jump_code (code, item->value.target_code);
5918 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5919 x86_patch (item->jmp_code, code);
5920 x86_jump_code (code, fail_tramp);
5921 item->jmp_code = NULL;
5923 /* enable the commented code to assert on wrong method */
5924 #if ENABLE_WRONG_METHOD_CHECK
5925 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5926 item->jmp_code = code;
5927 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5929 if (item->has_target_code)
5930 x86_jump_code (code, item->value.target_code);
5932 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5933 #if ENABLE_WRONG_METHOD_CHECK
5934 x86_patch (item->jmp_code, code);
5935 x86_breakpoint (code);
5936 item->jmp_code = NULL;
5941 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5942 item->jmp_code = code;
5943 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5944 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5946 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5949 /* patch the branches to get to the target items */
5950 for (i = 0; i < count; ++i) {
5951 MonoIMTCheckItem *item = imt_entries [i];
5952 if (item->jmp_code) {
5953 if (item->check_target_idx) {
5954 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5960 mono_stats.imt_thunks_size += code - start;
5961 g_assert (code - start <= size);
5965 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5966 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5970 if (mono_jit_map_is_enabled ()) {
5973 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5975 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5976 mono_emit_jit_tramp (start, code - start, buff);
5980 nacl_domain_code_validate (domain, &start, size, &code);
5986 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5988 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5993 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5995 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5999 mono_arch_get_cie_program (void)
6003 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
6004 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
6010 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6012 MonoInst *ins = NULL;
6015 if (cmethod->klass == mono_defaults.math_class) {
6016 if (strcmp (cmethod->name, "Sin") == 0) {
6018 } else if (strcmp (cmethod->name, "Cos") == 0) {
6020 } else if (strcmp (cmethod->name, "Tan") == 0) {
6022 } else if (strcmp (cmethod->name, "Atan") == 0) {
6024 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6026 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6028 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
6033 MONO_INST_NEW (cfg, ins, opcode);
6034 ins->type = STACK_R8;
6035 ins->dreg = mono_alloc_freg (cfg);
6036 ins->sreg1 = args [0]->dreg;
6037 MONO_ADD_INS (cfg->cbb, ins);
6040 if (cfg->opt & MONO_OPT_CMOV) {
6043 if (strcmp (cmethod->name, "Min") == 0) {
6044 if (fsig->params [0]->type == MONO_TYPE_I4)
6046 } else if (strcmp (cmethod->name, "Max") == 0) {
6047 if (fsig->params [0]->type == MONO_TYPE_I4)
6052 MONO_INST_NEW (cfg, ins, opcode);
6053 ins->type = STACK_I4;
6054 ins->dreg = mono_alloc_ireg (cfg);
6055 ins->sreg1 = args [0]->dreg;
6056 ins->sreg2 = args [1]->dreg;
6057 MONO_ADD_INS (cfg->cbb, ins);
6062 /* OP_FREM is not IEEE compatible */
6063 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6064 MONO_INST_NEW (cfg, ins, OP_FREM);
6065 ins->inst_i0 = args [0];
6066 ins->inst_i1 = args [1];
6075 mono_arch_print_tree (MonoInst *tree, int arity)
6081 mono_arch_get_patch_offset (guint8 *code)
6083 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
6085 else if (code [0] == 0xba)
6087 else if (code [0] == 0x68)
6090 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
6091 /* push <OFFSET>(<REG>) */
6093 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
6094 /* call *<OFFSET>(<REG>) */
6096 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
6099 else if ((code [0] == 0x58) && (code [1] == 0x05))
6100 /* pop %eax; add <OFFSET>, %eax */
6102 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6103 /* pop <REG>; add <OFFSET>, <REG> */
6105 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6106 /* mov <REG>, imm */
6109 g_assert_not_reached ();
6115 * mono_breakpoint_clean_code:
6117 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6118 * breakpoints in the original code, they are removed in the copy.
6120 * Returns TRUE if no sw breakpoint was present.
6123 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6126 gboolean can_write = TRUE;
6128 * If method_start is non-NULL we need to perform bound checks, since we access memory
6129 * at code - offset we could go before the start of the method and end up in a different
6130 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6133 if (!method_start || code - offset >= method_start) {
6134 memcpy (buf, code - offset, size);
6136 int diff = code - method_start;
6137 memset (buf, 0, size);
6138 memcpy (buf + offset - diff, method_start, diff + size - offset);
6141 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6142 int idx = mono_breakpoint_info_index [i];
6146 ptr = mono_breakpoint_info [idx].address;
6147 if (ptr >= code && ptr < code + size) {
6148 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6150 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6151 buf [ptr - code] = saved_byte;
6158 * mono_x86_get_this_arg_offset:
6160 * Return the offset of the stack location where this is passed during a virtual
6164 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6170 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6172 guint32 esp = regs [X86_ESP];
6173 CallInfo *cinfo = NULL;
6180 * The stack looks like:
6184 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
6186 res = (((MonoObject**)esp) [5 + (offset / 4)]);
6192 #define MAX_ARCH_DELEGATE_PARAMS 10
6195 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6197 guint8 *code, *start;
6198 int code_reserve = 64;
6201 * The stack contains:
6207 start = code = mono_global_codeman_reserve (code_reserve);
6209 /* Replace the this argument with the target */
6210 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6211 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
6212 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6213 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6215 g_assert ((code - start) < code_reserve);
6218 /* 8 for mov_reg and jump, plus 8 for each parameter */
6219 #ifdef __native_client_codegen__
6220 /* TODO: calculate this size correctly */
6221 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6223 code_reserve = 8 + (param_count * 8);
6224 #endif /* __native_client_codegen__ */
6226 * The stack contains:
6227 * <args in reverse order>
6232 * <args in reverse order>
6235 * without unbalancing the stack.
6236 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6237 * and leaving original spot of first arg as placeholder in stack so
6238 * when callee pops stack everything works.
6241 start = code = mono_global_codeman_reserve (code_reserve);
6243 /* store delegate for access to method_ptr */
6244 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6247 for (i = 0; i < param_count; ++i) {
6248 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6249 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6252 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6254 g_assert ((code - start) < code_reserve);
6257 nacl_global_codeman_validate(&start, code_reserve, &code);
6258 mono_debug_add_delegate_trampoline (start, code - start);
6261 *code_len = code - start;
6263 if (mono_jit_map_is_enabled ()) {
6266 buff = (char*)"delegate_invoke_has_target";
6268 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6269 mono_emit_jit_tramp (start, code - start, buff);
6278 mono_arch_get_delegate_invoke_impls (void)
6286 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6287 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
6289 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6290 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6291 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
6292 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
6293 g_free (tramp_name);
6300 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6302 guint8 *code, *start;
6304 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6307 /* FIXME: Support more cases */
6308 if (MONO_TYPE_ISSTRUCT (sig->ret))
6312 * The stack contains:
6318 static guint8* cached = NULL;
6323 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6325 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6327 mono_memory_barrier ();
6331 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6334 for (i = 0; i < sig->param_count; ++i)
6335 if (!mono_is_regsize_var (sig->params [i]))
6338 code = cache [sig->param_count];
6342 if (mono_aot_only) {
6343 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6344 start = mono_aot_get_trampoline (name);
6347 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6350 mono_memory_barrier ();
6352 cache [sig->param_count] = start;
6359 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6362 case X86_EAX: return ctx->eax;
6363 case X86_EBX: return ctx->ebx;
6364 case X86_ECX: return ctx->ecx;
6365 case X86_EDX: return ctx->edx;
6366 case X86_ESP: return ctx->esp;
6367 case X86_EBP: return ctx->ebp;
6368 case X86_ESI: return ctx->esi;
6369 case X86_EDI: return ctx->edi;
6371 g_assert_not_reached ();
6377 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6405 g_assert_not_reached ();
6409 #ifdef MONO_ARCH_SIMD_INTRINSICS
6412 get_float_to_x_spill_area (MonoCompile *cfg)
6414 if (!cfg->fconv_to_r8_x_var) {
6415 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6416 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6418 return cfg->fconv_to_r8_x_var;
6422 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6425 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6428 int dreg, src_opcode;
6430 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6433 switch (src_opcode = ins->opcode) {
6434 case OP_FCONV_TO_I1:
6435 case OP_FCONV_TO_U1:
6436 case OP_FCONV_TO_I2:
6437 case OP_FCONV_TO_U2:
6438 case OP_FCONV_TO_I4:
6445 /* dreg is the IREG and sreg1 is the FREG */
6446 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6447 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6448 fconv->sreg1 = ins->sreg1;
6449 fconv->dreg = mono_alloc_ireg (cfg);
6450 fconv->type = STACK_VTYPE;
6451 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6453 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6457 ins->opcode = OP_XCONV_R8_TO_I4;
6459 ins->klass = mono_defaults.int32_class;
6460 ins->sreg1 = fconv->dreg;
6462 ins->type = STACK_I4;
6463 ins->backend.source_opcode = src_opcode;
6466 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6469 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6474 if (long_ins->opcode == OP_LNEG) {
6476 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6477 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6478 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6483 #ifdef MONO_ARCH_SIMD_INTRINSICS
6485 if (!(cfg->opt & MONO_OPT_SIMD))
6488 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6489 switch (long_ins->opcode) {
6491 vreg = long_ins->sreg1;
6493 if (long_ins->inst_c0) {
6494 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6495 ins->klass = long_ins->klass;
6496 ins->sreg1 = long_ins->sreg1;
6498 ins->type = STACK_VTYPE;
6499 ins->dreg = vreg = alloc_ireg (cfg);
6500 MONO_ADD_INS (cfg->cbb, ins);
6503 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6504 ins->klass = mono_defaults.int32_class;
6506 ins->type = STACK_I4;
6507 ins->dreg = long_ins->dreg + 1;
6508 MONO_ADD_INS (cfg->cbb, ins);
6510 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6511 ins->klass = long_ins->klass;
6512 ins->sreg1 = long_ins->sreg1;
6513 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6514 ins->type = STACK_VTYPE;
6515 ins->dreg = vreg = alloc_ireg (cfg);
6516 MONO_ADD_INS (cfg->cbb, ins);
6518 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6519 ins->klass = mono_defaults.int32_class;
6521 ins->type = STACK_I4;
6522 ins->dreg = long_ins->dreg + 2;
6523 MONO_ADD_INS (cfg->cbb, ins);
6525 long_ins->opcode = OP_NOP;
6527 case OP_INSERTX_I8_SLOW:
6528 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6529 ins->dreg = long_ins->dreg;
6530 ins->sreg1 = long_ins->dreg;
6531 ins->sreg2 = long_ins->sreg2 + 1;
6532 ins->inst_c0 = long_ins->inst_c0 * 2;
6533 MONO_ADD_INS (cfg->cbb, ins);
6535 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6536 ins->dreg = long_ins->dreg;
6537 ins->sreg1 = long_ins->dreg;
6538 ins->sreg2 = long_ins->sreg2 + 2;
6539 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6540 MONO_ADD_INS (cfg->cbb, ins);
6542 long_ins->opcode = OP_NOP;
6545 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6546 ins->dreg = long_ins->dreg;
6547 ins->sreg1 = long_ins->sreg1 + 1;
6548 ins->klass = long_ins->klass;
6549 ins->type = STACK_VTYPE;
6550 MONO_ADD_INS (cfg->cbb, ins);
6552 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6553 ins->dreg = long_ins->dreg;
6554 ins->sreg1 = long_ins->dreg;
6555 ins->sreg2 = long_ins->sreg1 + 2;
6557 ins->klass = long_ins->klass;
6558 ins->type = STACK_VTYPE;
6559 MONO_ADD_INS (cfg->cbb, ins);
6561 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6562 ins->dreg = long_ins->dreg;
6563 ins->sreg1 = long_ins->dreg;;
6564 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6565 ins->klass = long_ins->klass;
6566 ins->type = STACK_VTYPE;
6567 MONO_ADD_INS (cfg->cbb, ins);
6569 long_ins->opcode = OP_NOP;
6572 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6575 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6577 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6580 gpointer *sp, old_value;
6583 offset = clause->exvar_offset;
6586 bp = MONO_CONTEXT_GET_BP (ctx);
6587 sp = *(gpointer*)(bp + offset);
6590 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6599 * mono_aot_emit_load_got_addr:
6601 * Emit code to load the got address.
6602 * On x86, the result is placed into EBX.
6605 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6607 x86_call_imm (code, 0);
6609 * The patch needs to point to the pop, since the GOT offset needs
6610 * to be added to that address.
6613 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6615 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6616 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6617 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6623 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6626 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6628 g_assert_not_reached ();
6629 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6634 * mono_arch_emit_load_aotconst:
6636 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6637 * TARGET from the mscorlib GOT in full-aot code.
6638 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6642 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6644 /* Load the mscorlib got address */
6645 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6646 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6647 /* arch_emit_got_access () patches this */
6648 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6653 /* Can't put this into mini-x86.h */
6655 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6658 mono_arch_get_trampolines (gboolean aot)
6660 MonoTrampInfo *info;
6661 GSList *tramps = NULL;
6663 mono_x86_get_signal_exception_trampoline (&info, aot);
6665 tramps = g_slist_append (tramps, info);
6672 #define DBG_SIGNAL SIGBUS
6674 #define DBG_SIGNAL SIGSEGV
6677 /* Soft Debug support */
6678 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6681 * mono_arch_set_breakpoint:
6683 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6684 * The location should contain code emitted by OP_SEQ_POINT.
6687 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6692 * In production, we will use int3 (has to fix the size in the md
6693 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6696 g_assert (code [0] == 0x90);
6697 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6701 * mono_arch_clear_breakpoint:
6703 * Clear the breakpoint at IP.
6706 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6711 for (i = 0; i < 6; ++i)
6716 * mono_arch_start_single_stepping:
6718 * Start single stepping.
6721 mono_arch_start_single_stepping (void)
6723 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6727 * mono_arch_stop_single_stepping:
6729 * Stop single stepping.
6732 mono_arch_stop_single_stepping (void)
6734 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6738 * mono_arch_is_single_step_event:
6740 * Return whenever the machine state in SIGCTX corresponds to a single
6744 mono_arch_is_single_step_event (void *info, void *sigctx)
6747 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6749 if (((gpointer)einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6754 siginfo_t* sinfo = (siginfo_t*) info;
6755 /* Sometimes the address is off by 4 */
6756 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6764 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6767 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6768 if (((gpointer)einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6773 siginfo_t* sinfo = (siginfo_t*)info;
6774 /* Sometimes the address is off by 4 */
6775 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6782 #define BREAKPOINT_SIZE 6
6785 * mono_arch_skip_breakpoint:
6787 * See mini-amd64.c for docs.
6790 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6792 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6796 * mono_arch_skip_single_step:
6798 * See mini-amd64.c for docs.
6801 mono_arch_skip_single_step (MonoContext *ctx)
6803 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6807 * mono_arch_get_seq_point_info:
6809 * See mini-amd64.c for docs.
6812 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6819 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6821 ext->lmf.previous_lmf = (gsize)prev_lmf;
6822 /* Mark that this is a MonoLMFExt */
6823 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6824 ext->lmf.ebp = (gssize)ext;
6829 #if defined(ENABLE_GSHAREDVT)
6831 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6833 #endif /* !MONOTOUCH */