2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/appdomain.h>
21 #include <mono/metadata/debug-helpers.h>
22 #include <mono/metadata/threads.h>
23 #include <mono/metadata/profiler-private.h>
24 #include <mono/metadata/mono-debug.h>
25 #include <mono/metadata/gc-internal.h>
26 #include <mono/utils/mono-math.h>
27 #include <mono/utils/mono-counters.h>
28 #include <mono/utils/mono-mmap.h>
29 #include <mono/utils/mono-memory-model.h>
30 #include <mono/utils/mono-hwcap-x86.h>
40 static gboolean optimize_for_xen = TRUE;
42 #define optimize_for_xen 0
46 /* This mutex protects architecture specific caches */
47 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
48 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
49 static CRITICAL_SECTION mini_arch_mutex;
51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
56 /* Under windows, the default pinvoke calling convention is stdcall */
57 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
59 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
62 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
65 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
68 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
70 #ifdef __native_client_codegen__
72 /* Default alignment for Native Client is 32-byte. */
73 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
75 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
76 /* Check that alignment doesn't cross an alignment boundary. */
78 mono_arch_nacl_pad (guint8 *code, int pad)
80 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
82 if (pad == 0) return code;
83 /* assertion: alignment cannot cross a block boundary */
84 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
85 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
86 while (pad >= kMaxPadding) {
87 x86_padding (code, kMaxPadding);
90 if (pad != 0) x86_padding (code, pad);
95 mono_arch_nacl_skip_nops (guint8 *code)
101 #endif /* __native_client_codegen__ */
104 * The code generated for sequence points reads from this location, which is
105 * made read-only when single stepping is enabled.
107 static gpointer ss_trigger_page;
109 /* Enabled breakpoints read from this trigger page */
110 static gpointer bp_trigger_page;
113 mono_arch_regname (int reg)
116 case X86_EAX: return "%eax";
117 case X86_EBX: return "%ebx";
118 case X86_ECX: return "%ecx";
119 case X86_EDX: return "%edx";
120 case X86_ESP: return "%esp";
121 case X86_EBP: return "%ebp";
122 case X86_EDI: return "%edi";
123 case X86_ESI: return "%esi";
129 mono_arch_fregname (int reg)
154 mono_arch_xregname (int reg)
179 mono_x86_patch (unsigned char* code, gpointer target)
181 x86_patch (code, (unsigned char*)target);
192 /* gsharedvt argument passed by addr */
204 /* Only if storage == ArgValuetypeInReg */
205 ArgStorage pair_storage [2];
214 gboolean need_stack_align;
215 guint32 stack_align_amount;
216 gboolean vtype_retaddr;
217 /* The index of the vret arg in the argument list */
225 #define FLOAT_PARAM_REGS 0
227 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
229 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
234 switch (sig->call_convention) {
235 case MONO_CALL_THISCALL:
236 return thiscall_param_regs;
242 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
243 #define SMALL_STRUCTS_IN_REGS
244 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
248 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
250 ainfo->offset = *stack_size;
252 if (!param_regs || param_regs [*gr] == X86_NREG) {
253 ainfo->storage = ArgOnStack;
255 (*stack_size) += sizeof (gpointer);
258 ainfo->storage = ArgInIReg;
259 ainfo->reg = param_regs [*gr];
265 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
267 ainfo->offset = *stack_size;
269 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
271 ainfo->storage = ArgOnStack;
272 (*stack_size) += sizeof (gpointer) * 2;
277 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
279 ainfo->offset = *stack_size;
281 if (*gr >= FLOAT_PARAM_REGS) {
282 ainfo->storage = ArgOnStack;
283 (*stack_size) += is_double ? 8 : 4;
284 ainfo->nslots = is_double ? 2 : 1;
287 /* A double register */
289 ainfo->storage = ArgInDoubleSSEReg;
291 ainfo->storage = ArgInFloatSSEReg;
299 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
301 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
306 klass = mono_class_from_mono_type (type);
307 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
309 #ifdef SMALL_STRUCTS_IN_REGS
310 if (sig->pinvoke && is_return) {
311 MonoMarshalType *info;
314 * the exact rules are not very well documented, the code below seems to work with the
315 * code generated by gcc 3.3.3 -mno-cygwin.
317 info = mono_marshal_load_type_info (klass);
320 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
322 /* Special case structs with only a float member */
323 if (info->num_fields == 1) {
324 int ftype = mini_replace_type (info->fields [0].field->type)->type;
325 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
326 ainfo->storage = ArgValuetypeInReg;
327 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
330 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
331 ainfo->storage = ArgValuetypeInReg;
332 ainfo->pair_storage [0] = ArgOnFloatFpStack;
336 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
337 ainfo->storage = ArgValuetypeInReg;
338 ainfo->pair_storage [0] = ArgInIReg;
339 ainfo->pair_regs [0] = return_regs [0];
340 if (info->native_size > 4) {
341 ainfo->pair_storage [1] = ArgInIReg;
342 ainfo->pair_regs [1] = return_regs [1];
349 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
350 g_assert (size <= 4);
351 ainfo->storage = ArgValuetypeInReg;
352 ainfo->reg = param_regs [*gr];
357 ainfo->offset = *stack_size;
358 ainfo->storage = ArgOnStack;
359 *stack_size += ALIGN_TO (size, sizeof (gpointer));
360 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
366 * Obtain information about a call according to the calling convention.
367 * For x86 ELF, see the "System V Application Binary Interface Intel386
368 * Architecture Processor Supplment, Fourth Edition" document for more
370 * For x86 win32, see ???.
373 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
375 guint32 i, gr, fr, pstart;
376 const guint32 *param_regs;
378 int n = sig->hasthis + sig->param_count;
379 guint32 stack_size = 0;
380 gboolean is_pinvoke = sig->pinvoke;
386 param_regs = callconv_param_regs(sig);
390 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
391 switch (ret_type->type) {
392 case MONO_TYPE_BOOLEAN:
403 case MONO_TYPE_FNPTR:
404 case MONO_TYPE_CLASS:
405 case MONO_TYPE_OBJECT:
406 case MONO_TYPE_SZARRAY:
407 case MONO_TYPE_ARRAY:
408 case MONO_TYPE_STRING:
409 cinfo->ret.storage = ArgInIReg;
410 cinfo->ret.reg = X86_EAX;
414 cinfo->ret.storage = ArgInIReg;
415 cinfo->ret.reg = X86_EAX;
416 cinfo->ret.is_pair = TRUE;
419 cinfo->ret.storage = ArgOnFloatFpStack;
422 cinfo->ret.storage = ArgOnDoubleFpStack;
424 case MONO_TYPE_GENERICINST:
425 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
426 cinfo->ret.storage = ArgInIReg;
427 cinfo->ret.reg = X86_EAX;
430 if (mini_is_gsharedvt_type_gsctx (gsctx, ret_type)) {
431 cinfo->ret.storage = ArgOnStack;
432 cinfo->vtype_retaddr = TRUE;
436 case MONO_TYPE_VALUETYPE:
437 case MONO_TYPE_TYPEDBYREF: {
438 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
440 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
441 if (cinfo->ret.storage == ArgOnStack) {
442 cinfo->vtype_retaddr = TRUE;
443 /* The caller passes the address where the value is stored */
449 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ret_type));
450 cinfo->ret.storage = ArgOnStack;
451 cinfo->vtype_retaddr = TRUE;
454 cinfo->ret.storage = ArgNone;
457 g_error ("Can't handle as return value 0x%x", ret_type->type);
463 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
464 * the first argument, allowing 'this' to be always passed in the first arg reg.
465 * Also do this if the first argument is a reference type, since virtual calls
466 * are sometimes made using calli without sig->hasthis set, like in the delegate
469 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
471 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
473 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
476 cinfo->vret_arg_offset = stack_size;
477 add_general (&gr, NULL, &stack_size, &cinfo->ret);
478 cinfo->vret_arg_index = 1;
482 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
484 if (cinfo->vtype_retaddr)
485 add_general (&gr, NULL, &stack_size, &cinfo->ret);
488 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
489 fr = FLOAT_PARAM_REGS;
491 /* Emit the signature cookie just before the implicit arguments */
492 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
495 for (i = pstart; i < sig->param_count; ++i) {
496 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
499 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
500 /* We allways pass the sig cookie on the stack for simplicity */
502 * Prevent implicit arguments + the sig cookie from being passed
505 fr = FLOAT_PARAM_REGS;
507 /* Emit the signature cookie just before the implicit arguments */
508 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
511 if (sig->params [i]->byref) {
512 add_general (&gr, param_regs, &stack_size, ainfo);
515 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
516 switch (ptype->type) {
517 case MONO_TYPE_BOOLEAN:
520 add_general (&gr, param_regs, &stack_size, ainfo);
525 add_general (&gr, param_regs, &stack_size, ainfo);
529 add_general (&gr, param_regs, &stack_size, ainfo);
534 case MONO_TYPE_FNPTR:
535 case MONO_TYPE_CLASS:
536 case MONO_TYPE_OBJECT:
537 case MONO_TYPE_STRING:
538 case MONO_TYPE_SZARRAY:
539 case MONO_TYPE_ARRAY:
540 add_general (&gr, param_regs, &stack_size, ainfo);
542 case MONO_TYPE_GENERICINST:
543 if (!mono_type_generic_inst_is_valuetype (ptype)) {
544 add_general (&gr, param_regs, &stack_size, ainfo);
547 if (mini_is_gsharedvt_type_gsctx (gsctx, ptype)) {
548 /* gsharedvt arguments are passed by ref */
549 add_general (&gr, param_regs, &stack_size, ainfo);
550 g_assert (ainfo->storage == ArgOnStack);
551 ainfo->storage = ArgGSharedVt;
555 case MONO_TYPE_VALUETYPE:
556 case MONO_TYPE_TYPEDBYREF:
557 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
561 add_general_pair (&gr, param_regs, &stack_size, ainfo);
564 add_float (&fr, &stack_size, ainfo, FALSE);
567 add_float (&fr, &stack_size, ainfo, TRUE);
571 /* gsharedvt arguments are passed by ref */
572 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ptype));
573 add_general (&gr, param_regs, &stack_size, ainfo);
574 g_assert (ainfo->storage == ArgOnStack);
575 ainfo->storage = ArgGSharedVt;
578 g_error ("unexpected type 0x%x", ptype->type);
579 g_assert_not_reached ();
583 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
584 fr = FLOAT_PARAM_REGS;
586 /* Emit the signature cookie just before the implicit arguments */
587 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
590 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
591 cinfo->need_stack_align = TRUE;
592 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
593 stack_size += cinfo->stack_align_amount;
596 cinfo->stack_usage = stack_size;
597 cinfo->reg_usage = gr;
598 cinfo->freg_usage = fr;
603 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
605 int n = sig->hasthis + sig->param_count;
609 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
611 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
613 return get_call_info_internal (gsctx, cinfo, sig);
617 * mono_arch_get_argument_info:
618 * @csig: a method signature
619 * @param_count: the number of parameters to consider
620 * @arg_info: an array to store the result infos
622 * Gathers information on parameters such as size, alignment and
623 * padding. arg_info should be large enought to hold param_count + 1 entries.
625 * Returns the size of the argument area on the stack.
626 * This should be signal safe, since it is called from
627 * mono_arch_find_jit_info ().
628 * FIXME: The metadata calls might not be signal safe.
631 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
633 int len, k, args_size = 0;
639 /* Avoid g_malloc as it is not signal safe */
640 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
641 cinfo = (CallInfo*)g_newa (guint8*, len);
642 memset (cinfo, 0, len);
644 cinfo = get_call_info_internal (gsctx, cinfo, csig);
646 arg_info [0].offset = offset;
648 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
649 args_size += sizeof (gpointer);
654 args_size += sizeof (gpointer);
658 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
659 /* Emitted after this */
660 args_size += sizeof (gpointer);
664 arg_info [0].size = args_size;
666 for (k = 0; k < param_count; k++) {
667 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
669 /* ignore alignment for now */
672 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
673 arg_info [k].pad = pad;
675 arg_info [k + 1].pad = 0;
676 arg_info [k + 1].size = size;
678 arg_info [k + 1].offset = offset;
681 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
682 /* Emitted after the first arg */
683 args_size += sizeof (gpointer);
688 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
689 align = MONO_ARCH_FRAME_ALIGNMENT;
692 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
693 arg_info [k].pad = pad;
699 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
701 MonoType *callee_ret;
705 if (cfg->compile_aot && !cfg->full_aot)
706 /* OP_TAILCALL doesn't work with AOT */
709 c1 = get_call_info (NULL, NULL, caller_sig);
710 c2 = get_call_info (NULL, NULL, callee_sig);
712 * Tail calls with more callee stack usage than the caller cannot be supported, since
713 * the extra stack space would be left on the stack after the tail call.
715 res = c1->stack_usage >= c2->stack_usage;
716 callee_ret = mini_replace_type (callee_sig->ret);
717 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
718 /* An address on the callee's stack is passed as the first argument */
728 * Initialize the cpu to execute managed code.
731 mono_arch_cpu_init (void)
733 /* spec compliance requires running with double precision */
737 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
738 fpcw &= ~X86_FPCW_PRECC_MASK;
739 fpcw |= X86_FPCW_PREC_DOUBLE;
740 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
741 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
743 _control87 (_PC_53, MCW_PC);
748 * Initialize architecture specific code.
751 mono_arch_init (void)
753 InitializeCriticalSection (&mini_arch_mutex);
755 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
756 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
757 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
759 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
760 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
761 #if defined(ENABLE_GSHAREDVT)
762 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
767 * Cleanup architecture specific code.
770 mono_arch_cleanup (void)
773 mono_vfree (ss_trigger_page, mono_pagesize ());
775 mono_vfree (bp_trigger_page, mono_pagesize ());
776 DeleteCriticalSection (&mini_arch_mutex);
780 * This function returns the optimizations supported on this cpu.
783 mono_arch_cpu_optimizations (guint32 *exclude_mask)
785 #if !defined(__native_client__)
790 if (mono_hwcap_x86_has_cmov) {
791 opts |= MONO_OPT_CMOV;
793 if (mono_hwcap_x86_has_fcmov)
794 opts |= MONO_OPT_FCMOV;
796 *exclude_mask |= MONO_OPT_FCMOV;
798 *exclude_mask |= MONO_OPT_CMOV;
801 if (mono_hwcap_x86_has_sse2)
802 opts |= MONO_OPT_SSE2;
804 *exclude_mask |= MONO_OPT_SSE2;
806 #ifdef MONO_ARCH_SIMD_INTRINSICS
807 /*SIMD intrinsics require at least SSE2.*/
808 if (!mono_hwcap_x86_has_sse2)
809 *exclude_mask |= MONO_OPT_SIMD;
814 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
819 * This function test for all SSE functions supported.
821 * Returns a bitmask corresponding to all supported versions.
825 mono_arch_cpu_enumerate_simd_versions (void)
827 guint32 sse_opts = 0;
829 if (mono_hwcap_x86_has_sse1)
830 sse_opts |= SIMD_VERSION_SSE1;
832 if (mono_hwcap_x86_has_sse2)
833 sse_opts |= SIMD_VERSION_SSE2;
835 if (mono_hwcap_x86_has_sse3)
836 sse_opts |= SIMD_VERSION_SSE3;
838 if (mono_hwcap_x86_has_ssse3)
839 sse_opts |= SIMD_VERSION_SSSE3;
841 if (mono_hwcap_x86_has_sse41)
842 sse_opts |= SIMD_VERSION_SSE41;
844 if (mono_hwcap_x86_has_sse42)
845 sse_opts |= SIMD_VERSION_SSE42;
847 if (mono_hwcap_x86_has_sse4a)
848 sse_opts |= SIMD_VERSION_SSE4a;
854 * Determine whenever the trap whose info is in SIGINFO is caused by
858 mono_arch_is_int_overflow (void *sigctx, void *info)
863 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
865 ip = (guint8*)ctx.eip;
867 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
871 switch (x86_modrm_rm (ip [1])) {
891 g_assert_not_reached ();
903 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
908 for (i = 0; i < cfg->num_varinfo; i++) {
909 MonoInst *ins = cfg->varinfo [i];
910 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
913 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
916 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
917 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
920 /* we dont allocate I1 to registers because there is no simply way to sign extend
921 * 8bit quantities in caller saved registers on x86 */
922 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
923 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
924 g_assert (i == vmv->idx);
925 vars = g_list_prepend (vars, vmv);
929 vars = mono_varlist_sort (cfg, vars, 0);
935 mono_arch_get_global_int_regs (MonoCompile *cfg)
939 /* we can use 3 registers for global allocation */
940 regs = g_list_prepend (regs, (gpointer)X86_EBX);
941 regs = g_list_prepend (regs, (gpointer)X86_ESI);
942 regs = g_list_prepend (regs, (gpointer)X86_EDI);
948 * mono_arch_regalloc_cost:
950 * Return the cost, in number of memory references, of the action of
951 * allocating the variable VMV into a register during global register
955 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
957 MonoInst *ins = cfg->varinfo [vmv->idx];
959 if (cfg->method->save_lmf)
960 /* The register is already saved */
961 return (ins->opcode == OP_ARG) ? 1 : 0;
963 /* push+pop+possible load if it is an argument */
964 return (ins->opcode == OP_ARG) ? 3 : 2;
968 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
970 static int inited = FALSE;
971 static int count = 0;
973 if (cfg->arch.need_stack_frame_inited) {
974 g_assert (cfg->arch.need_stack_frame == flag);
978 cfg->arch.need_stack_frame = flag;
979 cfg->arch.need_stack_frame_inited = TRUE;
985 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
990 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
994 needs_stack_frame (MonoCompile *cfg)
996 MonoMethodSignature *sig;
997 MonoMethodHeader *header;
998 gboolean result = FALSE;
1000 #if defined(__APPLE__)
1001 /*OSX requires stack frame code to have the correct alignment. */
1005 if (cfg->arch.need_stack_frame_inited)
1006 return cfg->arch.need_stack_frame;
1008 header = cfg->header;
1009 sig = mono_method_signature (cfg->method);
1011 if (cfg->disable_omit_fp)
1013 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1015 else if (cfg->method->save_lmf)
1017 else if (cfg->stack_offset)
1019 else if (cfg->param_area)
1021 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1023 else if (header->num_clauses)
1025 else if (sig->param_count + sig->hasthis)
1027 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1029 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1030 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1033 set_needs_stack_frame (cfg, result);
1035 return cfg->arch.need_stack_frame;
1039 * Set var information according to the calling convention. X86 version.
1040 * The locals var stuff should most likely be split in another method.
1043 mono_arch_allocate_vars (MonoCompile *cfg)
1045 MonoMethodSignature *sig;
1046 MonoMethodHeader *header;
1048 guint32 locals_stack_size, locals_stack_align;
1053 header = cfg->header;
1054 sig = mono_method_signature (cfg->method);
1056 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1058 cfg->frame_reg = X86_EBP;
1061 if (cfg->has_atomic_add_new_i4 || cfg->has_atomic_exchange_i4) {
1062 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1063 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1066 /* Reserve space to save LMF and caller saved registers */
1068 if (cfg->method->save_lmf) {
1069 /* The LMF var is allocated normally */
1071 if (cfg->used_int_regs & (1 << X86_EBX)) {
1075 if (cfg->used_int_regs & (1 << X86_EDI)) {
1079 if (cfg->used_int_regs & (1 << X86_ESI)) {
1084 switch (cinfo->ret.storage) {
1085 case ArgValuetypeInReg:
1086 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1088 cfg->ret->opcode = OP_REGOFFSET;
1089 cfg->ret->inst_basereg = X86_EBP;
1090 cfg->ret->inst_offset = - offset;
1096 /* Allocate locals */
1097 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1098 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1099 char *mname = mono_method_full_name (cfg->method, TRUE);
1100 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1101 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1105 if (locals_stack_align) {
1106 int prev_offset = offset;
1108 offset += (locals_stack_align - 1);
1109 offset &= ~(locals_stack_align - 1);
1111 while (prev_offset < offset) {
1113 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1116 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1117 cfg->locals_max_stack_offset = - offset;
1119 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1120 * have locals larger than 8 bytes we need to make sure that
1121 * they have the appropriate offset.
1123 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1124 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1125 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1126 if (offsets [i] != -1) {
1127 MonoInst *inst = cfg->varinfo [i];
1128 inst->opcode = OP_REGOFFSET;
1129 inst->inst_basereg = X86_EBP;
1130 inst->inst_offset = - (offset + offsets [i]);
1131 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1134 offset += locals_stack_size;
1138 * Allocate arguments+return value
1141 switch (cinfo->ret.storage) {
1143 if (cfg->vret_addr) {
1145 * In the new IR, the cfg->vret_addr variable represents the
1146 * vtype return value.
1148 cfg->vret_addr->opcode = OP_REGOFFSET;
1149 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1150 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1151 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1152 printf ("vret_addr =");
1153 mono_print_ins (cfg->vret_addr);
1156 cfg->ret->opcode = OP_REGOFFSET;
1157 cfg->ret->inst_basereg = X86_EBP;
1158 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1161 case ArgValuetypeInReg:
1164 cfg->ret->opcode = OP_REGVAR;
1165 cfg->ret->inst_c0 = cinfo->ret.reg;
1166 cfg->ret->dreg = cinfo->ret.reg;
1169 case ArgOnFloatFpStack:
1170 case ArgOnDoubleFpStack:
1173 g_assert_not_reached ();
1176 if (sig->call_convention == MONO_CALL_VARARG) {
1177 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1178 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1181 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1182 ArgInfo *ainfo = &cinfo->args [i];
1183 inst = cfg->args [i];
1184 if (inst->opcode != OP_REGVAR) {
1185 inst->opcode = OP_REGOFFSET;
1186 inst->inst_basereg = X86_EBP;
1188 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1191 cfg->stack_offset = offset;
1195 mono_arch_create_vars (MonoCompile *cfg)
1198 MonoMethodSignature *sig;
1201 sig = mono_method_signature (cfg->method);
1203 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1204 sig_ret = mini_replace_type (sig->ret);
1206 if (cinfo->ret.storage == ArgValuetypeInReg)
1207 cfg->ret_var_is_local = TRUE;
1208 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (cfg, sig_ret))) {
1209 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1212 if (cfg->method->save_lmf) {
1213 cfg->create_lmf_var = TRUE;
1216 cfg->lmf_ir_mono_lmf = TRUE;
1220 cfg->arch_eh_jit_info = 1;
1224 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1225 * so we try to do it just once when we have multiple fp arguments in a row.
1226 * We don't use this mechanism generally because for int arguments the generated code
1227 * is slightly bigger and new generation cpus optimize away the dependency chains
1228 * created by push instructions on the esp value.
1229 * fp_arg_setup is the first argument in the execution sequence where the esp register
1232 static G_GNUC_UNUSED int
1233 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1238 for (; start_arg < sig->param_count; ++start_arg) {
1239 t = mini_replace_type (sig->params [start_arg]);
1240 if (!t->byref && t->type == MONO_TYPE_R8) {
1241 fp_space += sizeof (double);
1242 *fp_arg_setup = start_arg;
1251 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1253 MonoMethodSignature *tmp_sig;
1257 * mono_ArgIterator_Setup assumes the signature cookie is
1258 * passed first and all the arguments which were before it are
1259 * passed on the stack after the signature. So compensate by
1260 * passing a different signature.
1262 tmp_sig = mono_metadata_signature_dup (call->signature);
1263 tmp_sig->param_count -= call->signature->sentinelpos;
1264 tmp_sig->sentinelpos = 0;
1265 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1267 if (cfg->compile_aot) {
1268 sig_reg = mono_alloc_ireg (cfg);
1269 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1270 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, sig_reg);
1272 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1278 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1283 LLVMCallInfo *linfo;
1284 MonoType *t, *sig_ret;
1286 n = sig->param_count + sig->hasthis;
1288 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1291 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1294 * LLVM always uses the native ABI while we use our own ABI, the
1295 * only difference is the handling of vtypes:
1296 * - we only pass/receive them in registers in some cases, and only
1297 * in 1 or 2 integer registers.
1299 if (cinfo->ret.storage == ArgValuetypeInReg) {
1301 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1302 cfg->disable_llvm = TRUE;
1306 cfg->exception_message = g_strdup ("vtype ret in call");
1307 cfg->disable_llvm = TRUE;
1309 linfo->ret.storage = LLVMArgVtypeInReg;
1310 for (j = 0; j < 2; ++j)
1311 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1315 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage == ArgInIReg) {
1316 /* Vtype returned using a hidden argument */
1317 linfo->ret.storage = LLVMArgVtypeRetAddr;
1318 linfo->vret_arg_index = cinfo->vret_arg_index;
1321 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage != ArgInIReg) {
1323 cfg->exception_message = g_strdup ("vtype ret in call");
1324 cfg->disable_llvm = TRUE;
1327 for (i = 0; i < n; ++i) {
1328 ainfo = cinfo->args + i;
1330 if (i >= sig->hasthis)
1331 t = sig->params [i - sig->hasthis];
1333 t = &mono_defaults.int_class->byval_arg;
1335 linfo->args [i].storage = LLVMArgNone;
1337 switch (ainfo->storage) {
1339 linfo->args [i].storage = LLVMArgInIReg;
1341 case ArgInDoubleSSEReg:
1342 case ArgInFloatSSEReg:
1343 linfo->args [i].storage = LLVMArgInFPReg;
1346 if (mini_type_is_vtype (cfg, t)) {
1347 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1348 /* LLVM seems to allocate argument space for empty structures too */
1349 linfo->args [i].storage = LLVMArgNone;
1351 linfo->args [i].storage = LLVMArgVtypeByVal;
1353 linfo->args [i].storage = LLVMArgInIReg;
1355 if (t->type == MONO_TYPE_R4)
1356 linfo->args [i].storage = LLVMArgInFPReg;
1357 else if (t->type == MONO_TYPE_R8)
1358 linfo->args [i].storage = LLVMArgInFPReg;
1362 case ArgValuetypeInReg:
1364 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1365 cfg->disable_llvm = TRUE;
1369 cfg->exception_message = g_strdup ("vtype arg");
1370 cfg->disable_llvm = TRUE;
1372 linfo->args [i].storage = LLVMArgVtypeInReg;
1373 for (j = 0; j < 2; ++j)
1374 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1378 linfo->args [i].storage = LLVMArgGSharedVt;
1381 cfg->exception_message = g_strdup ("ainfo->storage");
1382 cfg->disable_llvm = TRUE;
1392 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1394 if (cfg->compute_gc_maps) {
1397 /* On x86, the offsets are from the sp value before the start of the call sequence */
1399 t = &mono_defaults.int_class->byval_arg;
1400 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1405 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1409 MonoMethodSignature *sig;
1412 int sentinelpos = 0, sp_offset = 0;
1414 sig = call->signature;
1415 n = sig->param_count + sig->hasthis;
1416 sig_ret = mini_replace_type (sig->ret);
1418 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1420 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1421 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1423 if (cinfo->need_stack_align) {
1424 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1425 arg->dreg = X86_ESP;
1426 arg->sreg1 = X86_ESP;
1427 arg->inst_imm = cinfo->stack_align_amount;
1428 MONO_ADD_INS (cfg->cbb, arg);
1429 for (i = 0; i < cinfo->stack_align_amount; i += sizeof (mgreg_t)) {
1432 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1436 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1437 if (cinfo->ret.storage == ArgValuetypeInReg) {
1439 * Tell the JIT to use a more efficient calling convention: call using
1440 * OP_CALL, compute the result location after the call, and save the
1443 call->vret_in_reg = TRUE;
1445 NULLIFY_INS (call->vret_var);
1449 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1451 /* Handle the case where there are no implicit arguments */
1452 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1453 emit_sig_cookie (cfg, call, cinfo);
1455 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1458 /* Arguments are pushed in the reverse order */
1459 for (i = n - 1; i >= 0; i --) {
1460 ArgInfo *ainfo = cinfo->args + i;
1461 MonoType *orig_type, *t;
1464 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1465 /* Push the vret arg before the first argument */
1467 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1468 vtarg->type = STACK_MP;
1469 vtarg->sreg1 = call->vret_var->dreg;
1470 MONO_ADD_INS (cfg->cbb, vtarg);
1472 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1475 if (i >= sig->hasthis)
1476 t = sig->params [i - sig->hasthis];
1478 t = &mono_defaults.int_class->byval_arg;
1480 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1482 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1484 in = call->args [i];
1485 arg->cil_code = in->cil_code;
1486 arg->sreg1 = in->dreg;
1487 arg->type = in->type;
1489 g_assert (in->dreg != -1);
1491 if (ainfo->storage == ArgGSharedVt) {
1492 arg->opcode = OP_OUTARG_VT;
1493 arg->sreg1 = in->dreg;
1494 arg->klass = in->klass;
1495 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1496 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1498 MONO_ADD_INS (cfg->cbb, arg);
1499 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1503 g_assert (in->klass);
1505 if (t->type == MONO_TYPE_TYPEDBYREF) {
1506 size = sizeof (MonoTypedRef);
1507 align = sizeof (gpointer);
1510 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1514 arg->opcode = OP_OUTARG_VT;
1515 arg->sreg1 = in->dreg;
1516 arg->klass = in->klass;
1517 arg->backend.size = size;
1518 arg->inst_p0 = call;
1519 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1520 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1522 MONO_ADD_INS (cfg->cbb, arg);
1523 if (ainfo->storage != ArgValuetypeInReg) {
1525 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1531 switch (ainfo->storage) {
1533 arg->opcode = OP_X86_PUSH;
1535 if (t->type == MONO_TYPE_R4) {
1536 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1537 arg->opcode = OP_STORER4_MEMBASE_REG;
1538 arg->inst_destbasereg = X86_ESP;
1539 arg->inst_offset = 0;
1541 } else if (t->type == MONO_TYPE_R8) {
1542 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1543 arg->opcode = OP_STORER8_MEMBASE_REG;
1544 arg->inst_destbasereg = X86_ESP;
1545 arg->inst_offset = 0;
1547 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1549 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1555 arg->opcode = OP_MOVE;
1556 arg->dreg = ainfo->reg;
1560 g_assert_not_reached ();
1563 MONO_ADD_INS (cfg->cbb, arg);
1565 sp_offset += argsize;
1567 if (cfg->compute_gc_maps) {
1569 /* FIXME: The == STACK_OBJ check might be fragile ? */
1570 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1572 if (call->need_unbox_trampoline)
1573 /* The unbox trampoline transforms this into a managed pointer */
1574 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.int_class->this_arg);
1576 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.object_class->byval_arg);
1578 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1582 for (j = 0; j < argsize; j += 4)
1583 emit_gc_param_slot_def (cfg, sp_offset - j, NULL);
1588 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1589 /* Emit the signature cookie just before the implicit arguments */
1590 emit_sig_cookie (cfg, call, cinfo);
1592 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1596 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1599 if (cinfo->ret.storage == ArgValuetypeInReg) {
1602 else if (cinfo->ret.storage == ArgInIReg) {
1604 /* The return address is passed in a register */
1605 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1606 vtarg->sreg1 = call->inst.dreg;
1607 vtarg->dreg = mono_alloc_ireg (cfg);
1608 MONO_ADD_INS (cfg->cbb, vtarg);
1610 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1611 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1613 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1614 vtarg->type = STACK_MP;
1615 vtarg->sreg1 = call->vret_var->dreg;
1616 MONO_ADD_INS (cfg->cbb, vtarg);
1618 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1621 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1622 if (cinfo->ret.storage != ArgValuetypeInReg)
1623 cinfo->stack_usage -= 4;
1626 call->stack_usage = cinfo->stack_usage;
1627 call->stack_align_amount = cinfo->stack_align_amount;
1628 cfg->arch.param_area_size = MAX (cfg->arch.param_area_size, sp_offset);
1632 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1634 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1635 ArgInfo *ainfo = ins->inst_p1;
1637 int size = ins->backend.size;
1639 if (ainfo->storage == ArgValuetypeInReg) {
1640 int dreg = mono_alloc_ireg (cfg);
1643 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1646 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1649 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1653 g_assert_not_reached ();
1655 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1658 if (cfg->gsharedvt && mini_is_gsharedvt_klass (cfg, ins->klass)) {
1660 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1661 arg->sreg1 = src->dreg;
1662 MONO_ADD_INS (cfg->cbb, arg);
1663 } else if (size <= 4) {
1664 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1665 arg->sreg1 = src->dreg;
1667 MONO_ADD_INS (cfg->cbb, arg);
1668 } else if (size <= 20) {
1669 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1670 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1672 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1673 arg->inst_basereg = src->dreg;
1674 arg->inst_offset = 0;
1675 arg->inst_imm = size;
1677 MONO_ADD_INS (cfg->cbb, arg);
1683 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1685 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1688 if (ret->type == MONO_TYPE_R4) {
1689 if (COMPILE_LLVM (cfg))
1690 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1693 } else if (ret->type == MONO_TYPE_R8) {
1694 if (COMPILE_LLVM (cfg))
1695 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1698 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1699 if (COMPILE_LLVM (cfg))
1700 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1702 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1703 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1709 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1713 * Allow tracing to work with this interface (with an optional argument)
1716 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1720 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1721 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1723 /* if some args are passed in registers, we need to save them here */
1724 x86_push_reg (code, X86_EBP);
1726 if (cfg->compile_aot) {
1727 x86_push_imm (code, cfg->method);
1728 x86_mov_reg_imm (code, X86_EAX, func);
1729 x86_call_reg (code, X86_EAX);
1731 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1732 x86_push_imm (code, cfg->method);
1733 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1734 x86_call_code (code, 0);
1736 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1750 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1753 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1754 MonoMethod *method = cfg->method;
1755 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1757 switch (ret_type->type) {
1758 case MONO_TYPE_VOID:
1759 /* special case string .ctor icall */
1760 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1761 save_mode = SAVE_EAX;
1762 stack_usage = enable_arguments ? 8 : 4;
1764 save_mode = SAVE_NONE;
1768 save_mode = SAVE_EAX_EDX;
1769 stack_usage = enable_arguments ? 16 : 8;
1773 save_mode = SAVE_FP;
1774 stack_usage = enable_arguments ? 16 : 8;
1776 case MONO_TYPE_GENERICINST:
1777 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1778 save_mode = SAVE_EAX;
1779 stack_usage = enable_arguments ? 8 : 4;
1783 case MONO_TYPE_VALUETYPE:
1784 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1785 save_mode = SAVE_STRUCT;
1786 stack_usage = enable_arguments ? 4 : 0;
1789 save_mode = SAVE_EAX;
1790 stack_usage = enable_arguments ? 8 : 4;
1794 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1796 switch (save_mode) {
1798 x86_push_reg (code, X86_EDX);
1799 x86_push_reg (code, X86_EAX);
1800 if (enable_arguments) {
1801 x86_push_reg (code, X86_EDX);
1802 x86_push_reg (code, X86_EAX);
1807 x86_push_reg (code, X86_EAX);
1808 if (enable_arguments) {
1809 x86_push_reg (code, X86_EAX);
1814 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1815 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1816 if (enable_arguments) {
1817 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1818 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1823 if (enable_arguments) {
1824 x86_push_membase (code, X86_EBP, 8);
1833 if (cfg->compile_aot) {
1834 x86_push_imm (code, method);
1835 x86_mov_reg_imm (code, X86_EAX, func);
1836 x86_call_reg (code, X86_EAX);
1838 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1839 x86_push_imm (code, method);
1840 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1841 x86_call_code (code, 0);
1844 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1846 switch (save_mode) {
1848 x86_pop_reg (code, X86_EAX);
1849 x86_pop_reg (code, X86_EDX);
1852 x86_pop_reg (code, X86_EAX);
1855 x86_fld_membase (code, X86_ESP, 0, TRUE);
1856 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1863 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1868 #define EMIT_COND_BRANCH(ins,cond,sign) \
1869 if (ins->inst_true_bb->native_offset) { \
1870 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1872 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1873 if ((cfg->opt & MONO_OPT_BRANCH) && \
1874 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1875 x86_branch8 (code, cond, 0, sign); \
1877 x86_branch32 (code, cond, 0, sign); \
1881 * Emit an exception if condition is fail and
1882 * if possible do a directly branch to target
1884 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1886 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1887 if (tins == NULL) { \
1888 mono_add_patch_info (cfg, code - cfg->native_code, \
1889 MONO_PATCH_INFO_EXC, exc_name); \
1890 x86_branch32 (code, cond, 0, signed); \
1892 EMIT_COND_BRANCH (tins, cond, signed); \
1896 #define EMIT_FPCOMPARE(code) do { \
1897 x86_fcompp (code); \
1898 x86_fnstsw (code); \
1903 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1905 gboolean needs_paddings = TRUE;
1907 MonoJumpInfo *jinfo = NULL;
1909 if (cfg->abs_patches) {
1910 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1911 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1912 needs_paddings = FALSE;
1915 if (cfg->compile_aot)
1916 needs_paddings = FALSE;
1917 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1918 This is required for code patching to be safe on SMP machines.
1920 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1921 #ifndef __native_client_codegen__
1922 if (needs_paddings && pad_size)
1923 x86_padding (code, 4 - pad_size);
1926 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1927 x86_call_code (code, 0);
1932 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1935 * mono_peephole_pass_1:
1937 * Perform peephole opts which should/can be performed before local regalloc
1940 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1944 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1945 MonoInst *last_ins = ins->prev;
1947 switch (ins->opcode) {
1950 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1952 * X86_LEA is like ADD, but doesn't have the
1953 * sreg1==dreg restriction.
1955 ins->opcode = OP_X86_LEA_MEMBASE;
1956 ins->inst_basereg = ins->sreg1;
1957 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1958 ins->opcode = OP_X86_INC_REG;
1962 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1963 ins->opcode = OP_X86_LEA_MEMBASE;
1964 ins->inst_basereg = ins->sreg1;
1965 ins->inst_imm = -ins->inst_imm;
1966 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1967 ins->opcode = OP_X86_DEC_REG;
1969 case OP_COMPARE_IMM:
1970 case OP_ICOMPARE_IMM:
1971 /* OP_COMPARE_IMM (reg, 0)
1973 * OP_X86_TEST_NULL (reg)
1976 ins->opcode = OP_X86_TEST_NULL;
1978 case OP_X86_COMPARE_MEMBASE_IMM:
1980 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1981 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1983 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1984 * OP_COMPARE_IMM reg, imm
1986 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1988 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1989 ins->inst_basereg == last_ins->inst_destbasereg &&
1990 ins->inst_offset == last_ins->inst_offset) {
1991 ins->opcode = OP_COMPARE_IMM;
1992 ins->sreg1 = last_ins->sreg1;
1994 /* check if we can remove cmp reg,0 with test null */
1996 ins->opcode = OP_X86_TEST_NULL;
2000 case OP_X86_PUSH_MEMBASE:
2001 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
2002 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2003 ins->inst_basereg == last_ins->inst_destbasereg &&
2004 ins->inst_offset == last_ins->inst_offset) {
2005 ins->opcode = OP_X86_PUSH;
2006 ins->sreg1 = last_ins->sreg1;
2011 mono_peephole_ins (bb, ins);
2016 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2020 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2021 switch (ins->opcode) {
2023 /* reg = 0 -> XOR (reg, reg) */
2024 /* XOR sets cflags on x86, so we cant do it always */
2025 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2028 ins->opcode = OP_IXOR;
2029 ins->sreg1 = ins->dreg;
2030 ins->sreg2 = ins->dreg;
2033 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2034 * since it takes 3 bytes instead of 7.
2036 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2037 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2038 ins2->opcode = OP_STORE_MEMBASE_REG;
2039 ins2->sreg1 = ins->dreg;
2041 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2042 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2043 ins2->sreg1 = ins->dreg;
2045 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2046 /* Continue iteration */
2055 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2056 ins->opcode = OP_X86_INC_REG;
2060 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2061 ins->opcode = OP_X86_DEC_REG;
2065 mono_peephole_ins (bb, ins);
2070 * mono_arch_lowering_pass:
2072 * Converts complex opcodes into simpler ones so that each IR instruction
2073 * corresponds to one machine instruction.
2076 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2078 MonoInst *ins, *next;
2081 * FIXME: Need to add more instructions, but the current machine
2082 * description can't model some parts of the composite instructions like
2085 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2086 switch (ins->opcode) {
2089 case OP_IDIV_UN_IMM:
2090 case OP_IREM_UN_IMM:
2092 * Keep the cases where we could generated optimized code, otherwise convert
2093 * to the non-imm variant.
2095 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2097 mono_decompose_op_imm (cfg, bb, ins);
2104 bb->max_vreg = cfg->next_vreg;
2108 branch_cc_table [] = {
2109 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2110 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2111 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2114 /* Maps CMP_... constants to X86_CC_... constants */
2117 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2118 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2122 cc_signed_table [] = {
2123 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2124 FALSE, FALSE, FALSE, FALSE
2127 static unsigned char*
2128 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2130 #define XMM_TEMP_REG 0
2131 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2132 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2133 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2134 /* optimize by assigning a local var for this use so we avoid
2135 * the stack manipulations */
2136 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2137 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2138 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2139 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2140 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2142 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2144 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2147 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2148 x86_fnstcw_membase(code, X86_ESP, 0);
2149 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2150 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2151 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2152 x86_fldcw_membase (code, X86_ESP, 2);
2154 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2155 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2156 x86_pop_reg (code, dreg);
2157 /* FIXME: need the high register
2158 * x86_pop_reg (code, dreg_high);
2161 x86_push_reg (code, X86_EAX); // SP = SP - 4
2162 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2163 x86_pop_reg (code, dreg);
2165 x86_fldcw_membase (code, X86_ESP, 0);
2166 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2169 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2171 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2175 static unsigned char*
2176 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2178 int sreg = tree->sreg1;
2179 int need_touch = FALSE;
2181 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2190 * If requested stack size is larger than one page,
2191 * perform stack-touch operation
2194 * Generate stack probe code.
2195 * Under Windows, it is necessary to allocate one page at a time,
2196 * "touching" stack after each successful sub-allocation. This is
2197 * because of the way stack growth is implemented - there is a
2198 * guard page before the lowest stack page that is currently commited.
2199 * Stack normally grows sequentially so OS traps access to the
2200 * guard page and commits more pages when needed.
2202 x86_test_reg_imm (code, sreg, ~0xFFF);
2203 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2205 br[2] = code; /* loop */
2206 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2207 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2210 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2211 * that follows only initializes the last part of the area.
2213 /* Same as the init code below with size==0x1000 */
2214 if (tree->flags & MONO_INST_INIT) {
2215 x86_push_reg (code, X86_EAX);
2216 x86_push_reg (code, X86_ECX);
2217 x86_push_reg (code, X86_EDI);
2218 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2219 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2220 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2222 x86_prefix (code, X86_REP_PREFIX);
2224 x86_pop_reg (code, X86_EDI);
2225 x86_pop_reg (code, X86_ECX);
2226 x86_pop_reg (code, X86_EAX);
2229 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2230 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2231 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2232 x86_patch (br[3], br[2]);
2233 x86_test_reg_reg (code, sreg, sreg);
2234 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2235 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2237 br[1] = code; x86_jump8 (code, 0);
2239 x86_patch (br[0], code);
2240 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2241 x86_patch (br[1], code);
2242 x86_patch (br[4], code);
2245 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2247 if (tree->flags & MONO_INST_INIT) {
2249 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2250 x86_push_reg (code, X86_EAX);
2253 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2254 x86_push_reg (code, X86_ECX);
2257 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2258 x86_push_reg (code, X86_EDI);
2262 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2263 if (sreg != X86_ECX)
2264 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2265 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2267 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2269 x86_prefix (code, X86_REP_PREFIX);
2272 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2273 x86_pop_reg (code, X86_EDI);
2274 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2275 x86_pop_reg (code, X86_ECX);
2276 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2277 x86_pop_reg (code, X86_EAX);
2284 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2286 /* Move return value to the target register */
2287 switch (ins->opcode) {
2290 case OP_CALL_MEMBASE:
2291 if (ins->dreg != X86_EAX)
2292 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2302 static int tls_gs_offset;
2306 mono_x86_have_tls_get (void)
2309 static gboolean have_tls_get = FALSE;
2310 static gboolean inited = FALSE;
2314 return have_tls_get;
2316 ins = (guint32*)pthread_getspecific;
2318 * We're looking for these two instructions:
2320 * mov 0x4(%esp),%eax
2321 * mov %gs:[offset](,%eax,4),%eax
2323 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2324 tls_gs_offset = ins [2];
2328 return have_tls_get;
2329 #elif defined(TARGET_ANDROID)
2337 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2339 #if defined(__APPLE__)
2340 x86_prefix (code, X86_GS_PREFIX);
2341 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2342 #elif defined(TARGET_WIN32)
2343 g_assert_not_reached ();
2345 x86_prefix (code, X86_GS_PREFIX);
2346 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2352 * mono_x86_emit_tls_get:
2353 * @code: buffer to store code to
2354 * @dreg: hard register where to place the result
2355 * @tls_offset: offset info
2357 * mono_x86_emit_tls_get emits in @code the native code that puts in
2358 * the dreg register the item in the thread local storage identified
2361 * Returns: a pointer to the end of the stored code
2364 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2366 #if defined(__APPLE__)
2367 x86_prefix (code, X86_GS_PREFIX);
2368 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2369 #elif defined(TARGET_WIN32)
2371 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2372 * Journal and/or a disassembly of the TlsGet () function.
2374 g_assert (tls_offset < 64);
2375 x86_prefix (code, X86_FS_PREFIX);
2376 x86_mov_reg_mem (code, dreg, 0x18, 4);
2377 /* Dunno what this does but TlsGetValue () contains it */
2378 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2379 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2381 if (optimize_for_xen) {
2382 x86_prefix (code, X86_GS_PREFIX);
2383 x86_mov_reg_mem (code, dreg, 0, 4);
2384 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2386 x86_prefix (code, X86_GS_PREFIX);
2387 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2394 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2396 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2397 #if defined(__APPLE__) || defined(__linux__)
2398 if (dreg != offset_reg)
2399 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2400 x86_prefix (code, X86_GS_PREFIX);
2401 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2403 g_assert_not_reached ();
2409 mono_x86_emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2411 return emit_tls_get_reg (code, dreg, offset_reg);
2415 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2417 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2419 g_assert_not_reached ();
2420 #elif defined(__APPLE__) || defined(__linux__)
2421 x86_prefix (code, X86_GS_PREFIX);
2422 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2424 g_assert_not_reached ();
2430 * mono_arch_translate_tls_offset:
2432 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2435 mono_arch_translate_tls_offset (int offset)
2438 return tls_gs_offset + (offset * 4);
2447 * Emit code to initialize an LMF structure at LMF_OFFSET.
2450 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2452 /* save all caller saved regs */
2453 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2454 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx));
2455 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2456 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi));
2457 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2458 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi));
2459 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2461 /* save the current IP */
2462 if (cfg->compile_aot) {
2463 /* This pushes the current ip */
2464 x86_call_imm (code, 0);
2465 x86_pop_reg (code, X86_EAX);
2467 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2468 x86_mov_reg_imm (code, X86_EAX, 0);
2470 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2472 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2473 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2474 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2475 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2476 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2477 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2478 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2479 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2480 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2485 #define REAL_PRINT_REG(text,reg) \
2486 mono_assert (reg >= 0); \
2487 x86_push_reg (code, X86_EAX); \
2488 x86_push_reg (code, X86_EDX); \
2489 x86_push_reg (code, X86_ECX); \
2490 x86_push_reg (code, reg); \
2491 x86_push_imm (code, reg); \
2492 x86_push_imm (code, text " %d %p\n"); \
2493 x86_mov_reg_imm (code, X86_EAX, printf); \
2494 x86_call_reg (code, X86_EAX); \
2495 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2496 x86_pop_reg (code, X86_ECX); \
2497 x86_pop_reg (code, X86_EDX); \
2498 x86_pop_reg (code, X86_EAX);
2500 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2501 #ifdef __native__client_codegen__
2502 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2505 /* benchmark and set based on cpu */
2506 #define LOOP_ALIGNMENT 8
2507 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2511 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2516 guint8 *code = cfg->native_code + cfg->code_len;
2519 if (cfg->opt & MONO_OPT_LOOP) {
2520 int pad, align = LOOP_ALIGNMENT;
2521 /* set alignment depending on cpu */
2522 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2524 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2525 x86_padding (code, pad);
2526 cfg->code_len += pad;
2527 bb->native_offset = cfg->code_len;
2530 #ifdef __native_client_codegen__
2532 /* For Native Client, all indirect call/jump targets must be */
2533 /* 32-byte aligned. Exception handler blocks are jumped to */
2534 /* indirectly as well. */
2535 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2536 (bb->flags & BB_EXCEPTION_HANDLER);
2538 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2539 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2540 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2541 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2542 cfg->code_len += pad;
2543 bb->native_offset = cfg->code_len;
2546 #endif /* __native_client_codegen__ */
2547 if (cfg->verbose_level > 2)
2548 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2550 cpos = bb->max_offset;
2552 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2553 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2554 g_assert (!cfg->compile_aot);
2557 cov->data [bb->dfn].cil_code = bb->cil_code;
2558 /* this is not thread save, but good enough */
2559 x86_inc_mem (code, &cov->data [bb->dfn].count);
2562 offset = code - cfg->native_code;
2564 mono_debug_open_block (cfg, bb, offset);
2566 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2567 x86_breakpoint (code);
2569 MONO_BB_FOR_EACH_INS (bb, ins) {
2570 offset = code - cfg->native_code;
2572 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2574 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2576 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2577 cfg->code_size *= 2;
2578 cfg->native_code = mono_realloc_native_code(cfg);
2579 code = cfg->native_code + offset;
2580 cfg->stat_code_reallocs++;
2583 if (cfg->debug_info)
2584 mono_debug_record_line_number (cfg, ins, offset);
2586 switch (ins->opcode) {
2588 x86_mul_reg (code, ins->sreg2, TRUE);
2591 x86_mul_reg (code, ins->sreg2, FALSE);
2593 case OP_X86_SETEQ_MEMBASE:
2594 case OP_X86_SETNE_MEMBASE:
2595 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2596 ins->inst_basereg, ins->inst_offset, TRUE);
2598 case OP_STOREI1_MEMBASE_IMM:
2599 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2601 case OP_STOREI2_MEMBASE_IMM:
2602 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2604 case OP_STORE_MEMBASE_IMM:
2605 case OP_STOREI4_MEMBASE_IMM:
2606 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2608 case OP_STOREI1_MEMBASE_REG:
2609 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2611 case OP_STOREI2_MEMBASE_REG:
2612 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2614 case OP_STORE_MEMBASE_REG:
2615 case OP_STOREI4_MEMBASE_REG:
2616 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2618 case OP_STORE_MEM_IMM:
2619 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2622 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2626 /* These are created by the cprop pass so they use inst_imm as the source */
2627 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2630 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2633 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2635 case OP_LOAD_MEMBASE:
2636 case OP_LOADI4_MEMBASE:
2637 case OP_LOADU4_MEMBASE:
2638 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2640 case OP_LOADU1_MEMBASE:
2641 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2643 case OP_LOADI1_MEMBASE:
2644 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2646 case OP_LOADU2_MEMBASE:
2647 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2649 case OP_LOADI2_MEMBASE:
2650 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2652 case OP_ICONV_TO_I1:
2654 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2656 case OP_ICONV_TO_I2:
2658 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2660 case OP_ICONV_TO_U1:
2661 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2663 case OP_ICONV_TO_U2:
2664 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2668 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2670 case OP_COMPARE_IMM:
2671 case OP_ICOMPARE_IMM:
2672 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2674 case OP_X86_COMPARE_MEMBASE_REG:
2675 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2677 case OP_X86_COMPARE_MEMBASE_IMM:
2678 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2680 case OP_X86_COMPARE_MEMBASE8_IMM:
2681 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2683 case OP_X86_COMPARE_REG_MEMBASE:
2684 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2686 case OP_X86_COMPARE_MEM_IMM:
2687 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2689 case OP_X86_TEST_NULL:
2690 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2692 case OP_X86_ADD_MEMBASE_IMM:
2693 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2695 case OP_X86_ADD_REG_MEMBASE:
2696 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2698 case OP_X86_SUB_MEMBASE_IMM:
2699 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2701 case OP_X86_SUB_REG_MEMBASE:
2702 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2704 case OP_X86_AND_MEMBASE_IMM:
2705 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2707 case OP_X86_OR_MEMBASE_IMM:
2708 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2710 case OP_X86_XOR_MEMBASE_IMM:
2711 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2713 case OP_X86_ADD_MEMBASE_REG:
2714 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2716 case OP_X86_SUB_MEMBASE_REG:
2717 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2719 case OP_X86_AND_MEMBASE_REG:
2720 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2722 case OP_X86_OR_MEMBASE_REG:
2723 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2725 case OP_X86_XOR_MEMBASE_REG:
2726 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2728 case OP_X86_INC_MEMBASE:
2729 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2731 case OP_X86_INC_REG:
2732 x86_inc_reg (code, ins->dreg);
2734 case OP_X86_DEC_MEMBASE:
2735 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2737 case OP_X86_DEC_REG:
2738 x86_dec_reg (code, ins->dreg);
2740 case OP_X86_MUL_REG_MEMBASE:
2741 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2743 case OP_X86_AND_REG_MEMBASE:
2744 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2746 case OP_X86_OR_REG_MEMBASE:
2747 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2749 case OP_X86_XOR_REG_MEMBASE:
2750 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2753 x86_breakpoint (code);
2755 case OP_RELAXED_NOP:
2756 x86_prefix (code, X86_REP_PREFIX);
2764 case OP_DUMMY_STORE:
2765 case OP_DUMMY_ICONST:
2766 case OP_DUMMY_R8CONST:
2767 case OP_NOT_REACHED:
2770 case OP_SEQ_POINT: {
2773 if (cfg->compile_aot)
2777 * Read from the single stepping trigger page. This will cause a
2778 * SIGSEGV when single stepping is enabled.
2779 * We do this _before_ the breakpoint, so single stepping after
2780 * a breakpoint is hit will step to the next IL offset.
2782 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2783 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2785 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2788 * A placeholder for a possible breakpoint inserted by
2789 * mono_arch_set_breakpoint ().
2791 for (i = 0; i < 6; ++i)
2794 * Add an additional nop so skipping the bp doesn't cause the ip to point
2795 * to another IL offset.
2803 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2807 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2812 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2816 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2821 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2825 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2830 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2834 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2837 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2841 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2845 #if defined( __native_client_codegen__ )
2846 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2847 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2850 * The code is the same for div/rem, the allocator will allocate dreg
2851 * to RAX/RDX as appropriate.
2853 if (ins->sreg2 == X86_EDX) {
2854 /* cdq clobbers this */
2855 x86_push_reg (code, ins->sreg2);
2857 x86_div_membase (code, X86_ESP, 0, TRUE);
2858 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2861 x86_div_reg (code, ins->sreg2, TRUE);
2866 #if defined( __native_client_codegen__ )
2867 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2868 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2870 if (ins->sreg2 == X86_EDX) {
2871 x86_push_reg (code, ins->sreg2);
2872 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2873 x86_div_membase (code, X86_ESP, 0, FALSE);
2874 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2876 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2877 x86_div_reg (code, ins->sreg2, FALSE);
2881 #if defined( __native_client_codegen__ )
2882 if (ins->inst_imm == 0) {
2883 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2884 x86_jump32 (code, 0);
2888 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2890 x86_div_reg (code, ins->sreg2, TRUE);
2893 int power = mono_is_power_of_two (ins->inst_imm);
2895 g_assert (ins->sreg1 == X86_EAX);
2896 g_assert (ins->dreg == X86_EAX);
2897 g_assert (power >= 0);
2900 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2902 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2904 * If the divident is >= 0, this does not nothing. If it is positive, it
2905 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2907 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2908 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2909 } else if (power == 0) {
2910 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2912 /* Based on gcc code */
2914 /* Add compensation for negative dividents */
2916 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2917 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2918 /* Compute remainder */
2919 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2920 /* Remove compensation */
2921 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2926 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2930 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2933 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2937 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2940 g_assert (ins->sreg2 == X86_ECX);
2941 x86_shift_reg (code, X86_SHL, ins->dreg);
2944 g_assert (ins->sreg2 == X86_ECX);
2945 x86_shift_reg (code, X86_SAR, ins->dreg);
2949 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2952 case OP_ISHR_UN_IMM:
2953 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2956 g_assert (ins->sreg2 == X86_ECX);
2957 x86_shift_reg (code, X86_SHR, ins->dreg);
2961 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2964 guint8 *jump_to_end;
2966 /* handle shifts below 32 bits */
2967 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2968 x86_shift_reg (code, X86_SHL, ins->sreg1);
2970 x86_test_reg_imm (code, X86_ECX, 32);
2971 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2973 /* handle shift over 32 bit */
2974 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2975 x86_clear_reg (code, ins->sreg1);
2977 x86_patch (jump_to_end, code);
2981 guint8 *jump_to_end;
2983 /* handle shifts below 32 bits */
2984 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2985 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2987 x86_test_reg_imm (code, X86_ECX, 32);
2988 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2990 /* handle shifts over 31 bits */
2991 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2992 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2994 x86_patch (jump_to_end, code);
2998 guint8 *jump_to_end;
3000 /* handle shifts below 32 bits */
3001 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3002 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
3004 x86_test_reg_imm (code, X86_ECX, 32);
3005 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3007 /* handle shifts over 31 bits */
3008 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3009 x86_clear_reg (code, ins->backend.reg3);
3011 x86_patch (jump_to_end, code);
3015 if (ins->inst_imm >= 32) {
3016 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3017 x86_clear_reg (code, ins->sreg1);
3018 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
3020 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
3021 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
3025 if (ins->inst_imm >= 32) {
3026 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3027 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
3028 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
3030 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3031 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3034 case OP_LSHR_UN_IMM:
3035 if (ins->inst_imm >= 32) {
3036 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3037 x86_clear_reg (code, ins->backend.reg3);
3038 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3040 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3041 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3045 x86_not_reg (code, ins->sreg1);
3048 x86_neg_reg (code, ins->sreg1);
3052 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3056 switch (ins->inst_imm) {
3060 if (ins->dreg != ins->sreg1)
3061 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3062 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3065 /* LEA r1, [r2 + r2*2] */
3066 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3069 /* LEA r1, [r2 + r2*4] */
3070 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3073 /* LEA r1, [r2 + r2*2] */
3075 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3076 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3079 /* LEA r1, [r2 + r2*8] */
3080 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3083 /* LEA r1, [r2 + r2*4] */
3085 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3086 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3089 /* LEA r1, [r2 + r2*2] */
3091 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3092 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3095 /* LEA r1, [r2 + r2*4] */
3096 /* LEA r1, [r1 + r1*4] */
3097 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3098 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3101 /* LEA r1, [r2 + r2*4] */
3103 /* LEA r1, [r1 + r1*4] */
3104 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3105 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3106 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3109 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3114 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3115 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3117 case OP_IMUL_OVF_UN: {
3118 /* the mul operation and the exception check should most likely be split */
3119 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3120 /*g_assert (ins->sreg2 == X86_EAX);
3121 g_assert (ins->dreg == X86_EAX);*/
3122 if (ins->sreg2 == X86_EAX) {
3123 non_eax_reg = ins->sreg1;
3124 } else if (ins->sreg1 == X86_EAX) {
3125 non_eax_reg = ins->sreg2;
3127 /* no need to save since we're going to store to it anyway */
3128 if (ins->dreg != X86_EAX) {
3130 x86_push_reg (code, X86_EAX);
3132 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3133 non_eax_reg = ins->sreg2;
3135 if (ins->dreg == X86_EDX) {
3138 x86_push_reg (code, X86_EAX);
3140 } else if (ins->dreg != X86_EAX) {
3142 x86_push_reg (code, X86_EDX);
3144 x86_mul_reg (code, non_eax_reg, FALSE);
3145 /* save before the check since pop and mov don't change the flags */
3146 if (ins->dreg != X86_EAX)
3147 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3149 x86_pop_reg (code, X86_EDX);
3151 x86_pop_reg (code, X86_EAX);
3152 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3156 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3159 g_assert_not_reached ();
3160 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3161 x86_mov_reg_imm (code, ins->dreg, 0);
3164 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3165 x86_mov_reg_imm (code, ins->dreg, 0);
3167 case OP_LOAD_GOTADDR:
3168 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3169 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3172 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3173 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3175 case OP_X86_PUSH_GOT_ENTRY:
3176 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3177 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3180 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3183 MonoCallInst *call = (MonoCallInst*)ins;
3186 ins->flags |= MONO_INST_GC_CALLSITE;
3187 ins->backend.pc_offset = code - cfg->native_code;
3189 /* reset offset to make max_len work */
3190 offset = code - cfg->native_code;
3192 g_assert (!cfg->method->save_lmf);
3194 /* restore callee saved registers */
3195 for (i = 0; i < X86_NREG; ++i)
3196 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3198 if (cfg->used_int_regs & (1 << X86_ESI)) {
3199 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3202 if (cfg->used_int_regs & (1 << X86_EDI)) {
3203 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3206 if (cfg->used_int_regs & (1 << X86_EBX)) {
3207 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3211 /* Copy arguments on the stack to our argument area */
3212 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3213 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3214 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3217 /* restore ESP/EBP */
3219 offset = code - cfg->native_code;
3220 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3221 x86_jump32 (code, 0);
3223 ins->flags |= MONO_INST_GC_CALLSITE;
3224 cfg->disable_aot = TRUE;
3228 /* ensure ins->sreg1 is not NULL
3229 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3230 * cmp DWORD PTR [eax], 0
3232 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3235 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3236 x86_push_reg (code, hreg);
3237 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3238 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3239 x86_pop_reg (code, hreg);
3248 call = (MonoCallInst*)ins;
3249 if (ins->flags & MONO_INST_HAS_METHOD)
3250 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3252 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3253 ins->flags |= MONO_INST_GC_CALLSITE;
3254 ins->backend.pc_offset = code - cfg->native_code;
3255 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3256 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
3257 * bytes to pop, we want to use pops. GCC does this (note it won't happen
3258 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
3259 * smart enough to do that optimization yet
3261 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
3262 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
3263 * (most likely from locality benefits). People with other processors should
3264 * check on theirs to see what happens.
3266 if (call->stack_usage == 4) {
3267 /* we want to use registers that won't get used soon, so use
3268 * ecx, as eax will get allocated first. edx is used by long calls,
3269 * so we can't use that.
3272 x86_pop_reg (code, X86_ECX);
3274 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3277 code = emit_move_return_value (cfg, ins, code);
3283 case OP_VOIDCALL_REG:
3285 call = (MonoCallInst*)ins;
3286 x86_call_reg (code, ins->sreg1);
3287 ins->flags |= MONO_INST_GC_CALLSITE;
3288 ins->backend.pc_offset = code - cfg->native_code;
3289 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3290 if (call->stack_usage == 4)
3291 x86_pop_reg (code, X86_ECX);
3293 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3295 code = emit_move_return_value (cfg, ins, code);
3297 case OP_FCALL_MEMBASE:
3298 case OP_LCALL_MEMBASE:
3299 case OP_VCALL_MEMBASE:
3300 case OP_VCALL2_MEMBASE:
3301 case OP_VOIDCALL_MEMBASE:
3302 case OP_CALL_MEMBASE:
3303 call = (MonoCallInst*)ins;
3305 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3306 ins->flags |= MONO_INST_GC_CALLSITE;
3307 ins->backend.pc_offset = code - cfg->native_code;
3308 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3309 if (call->stack_usage == 4)
3310 x86_pop_reg (code, X86_ECX);
3312 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3314 code = emit_move_return_value (cfg, ins, code);
3317 x86_push_reg (code, ins->sreg1);
3319 case OP_X86_PUSH_IMM:
3320 x86_push_imm (code, ins->inst_imm);
3322 case OP_X86_PUSH_MEMBASE:
3323 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
3325 case OP_X86_PUSH_OBJ:
3326 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
3327 x86_push_reg (code, X86_EDI);
3328 x86_push_reg (code, X86_ESI);
3329 x86_push_reg (code, X86_ECX);
3330 if (ins->inst_offset)
3331 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
3333 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
3334 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
3335 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
3337 x86_prefix (code, X86_REP_PREFIX);
3339 x86_pop_reg (code, X86_ECX);
3340 x86_pop_reg (code, X86_ESI);
3341 x86_pop_reg (code, X86_EDI);
3344 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3346 case OP_X86_LEA_MEMBASE:
3347 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3350 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3353 /* keep alignment */
3354 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3355 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3356 code = mono_emit_stack_alloc (code, ins);
3357 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3359 case OP_LOCALLOC_IMM: {
3360 guint32 size = ins->inst_imm;
3361 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3363 if (ins->flags & MONO_INST_INIT) {
3364 /* FIXME: Optimize this */
3365 x86_mov_reg_imm (code, ins->dreg, size);
3366 ins->sreg1 = ins->dreg;
3368 code = mono_emit_stack_alloc (code, ins);
3369 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3371 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3372 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3377 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3378 x86_push_reg (code, ins->sreg1);
3379 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3380 (gpointer)"mono_arch_throw_exception");
3381 ins->flags |= MONO_INST_GC_CALLSITE;
3382 ins->backend.pc_offset = code - cfg->native_code;
3386 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3387 x86_push_reg (code, ins->sreg1);
3388 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3389 (gpointer)"mono_arch_rethrow_exception");
3390 ins->flags |= MONO_INST_GC_CALLSITE;
3391 ins->backend.pc_offset = code - cfg->native_code;
3394 case OP_CALL_HANDLER:
3395 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3396 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3397 x86_call_imm (code, 0);
3398 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3399 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3401 case OP_START_HANDLER: {
3402 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3403 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3406 case OP_ENDFINALLY: {
3407 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3408 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3412 case OP_ENDFILTER: {
3413 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3414 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3415 /* The local allocator will put the result into EAX */
3421 ins->inst_c0 = code - cfg->native_code;
3424 if (ins->inst_target_bb->native_offset) {
3425 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3427 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3428 if ((cfg->opt & MONO_OPT_BRANCH) &&
3429 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3430 x86_jump8 (code, 0);
3432 x86_jump32 (code, 0);
3436 x86_jump_reg (code, ins->sreg1);
3455 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3456 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3458 case OP_COND_EXC_EQ:
3459 case OP_COND_EXC_NE_UN:
3460 case OP_COND_EXC_LT:
3461 case OP_COND_EXC_LT_UN:
3462 case OP_COND_EXC_GT:
3463 case OP_COND_EXC_GT_UN:
3464 case OP_COND_EXC_GE:
3465 case OP_COND_EXC_GE_UN:
3466 case OP_COND_EXC_LE:
3467 case OP_COND_EXC_LE_UN:
3468 case OP_COND_EXC_IEQ:
3469 case OP_COND_EXC_INE_UN:
3470 case OP_COND_EXC_ILT:
3471 case OP_COND_EXC_ILT_UN:
3472 case OP_COND_EXC_IGT:
3473 case OP_COND_EXC_IGT_UN:
3474 case OP_COND_EXC_IGE:
3475 case OP_COND_EXC_IGE_UN:
3476 case OP_COND_EXC_ILE:
3477 case OP_COND_EXC_ILE_UN:
3478 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3480 case OP_COND_EXC_OV:
3481 case OP_COND_EXC_NO:
3483 case OP_COND_EXC_NC:
3484 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3486 case OP_COND_EXC_IOV:
3487 case OP_COND_EXC_INO:
3488 case OP_COND_EXC_IC:
3489 case OP_COND_EXC_INC:
3490 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3502 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3510 case OP_CMOV_INE_UN:
3511 case OP_CMOV_IGE_UN:
3512 case OP_CMOV_IGT_UN:
3513 case OP_CMOV_ILE_UN:
3514 case OP_CMOV_ILT_UN:
3515 g_assert (ins->dreg == ins->sreg1);
3516 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3519 /* floating point opcodes */
3521 double d = *(double *)ins->inst_p0;
3523 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3525 } else if (d == 1.0) {
3528 if (cfg->compile_aot) {
3529 guint32 *val = (guint32*)&d;
3530 x86_push_imm (code, val [1]);
3531 x86_push_imm (code, val [0]);
3532 x86_fld_membase (code, X86_ESP, 0, TRUE);
3533 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3536 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3537 x86_fld (code, NULL, TRUE);
3543 float f = *(float *)ins->inst_p0;
3545 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3547 } else if (f == 1.0) {
3550 if (cfg->compile_aot) {
3551 guint32 val = *(guint32*)&f;
3552 x86_push_imm (code, val);
3553 x86_fld_membase (code, X86_ESP, 0, FALSE);
3554 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3557 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3558 x86_fld (code, NULL, FALSE);
3563 case OP_STORER8_MEMBASE_REG:
3564 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3566 case OP_LOADR8_MEMBASE:
3567 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3569 case OP_STORER4_MEMBASE_REG:
3570 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3572 case OP_LOADR4_MEMBASE:
3573 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3575 case OP_ICONV_TO_R4:
3576 x86_push_reg (code, ins->sreg1);
3577 x86_fild_membase (code, X86_ESP, 0, FALSE);
3578 /* Change precision */
3579 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3580 x86_fld_membase (code, X86_ESP, 0, FALSE);
3581 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3583 case OP_ICONV_TO_R8:
3584 x86_push_reg (code, ins->sreg1);
3585 x86_fild_membase (code, X86_ESP, 0, FALSE);
3586 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3588 case OP_ICONV_TO_R_UN:
3589 x86_push_imm (code, 0);
3590 x86_push_reg (code, ins->sreg1);
3591 x86_fild_membase (code, X86_ESP, 0, TRUE);
3592 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3594 case OP_X86_FP_LOAD_I8:
3595 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3597 case OP_X86_FP_LOAD_I4:
3598 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3600 case OP_FCONV_TO_R4:
3601 /* Change precision */
3602 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3603 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3604 x86_fld_membase (code, X86_ESP, 0, FALSE);
3605 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3607 case OP_FCONV_TO_I1:
3608 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3610 case OP_FCONV_TO_U1:
3611 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3613 case OP_FCONV_TO_I2:
3614 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3616 case OP_FCONV_TO_U2:
3617 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3619 case OP_FCONV_TO_I4:
3621 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3623 case OP_FCONV_TO_I8:
3624 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3625 x86_fnstcw_membase(code, X86_ESP, 0);
3626 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3627 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3628 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3629 x86_fldcw_membase (code, X86_ESP, 2);
3630 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3631 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3632 x86_pop_reg (code, ins->dreg);
3633 x86_pop_reg (code, ins->backend.reg3);
3634 x86_fldcw_membase (code, X86_ESP, 0);
3635 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3637 case OP_LCONV_TO_R8_2:
3638 x86_push_reg (code, ins->sreg2);
3639 x86_push_reg (code, ins->sreg1);
3640 x86_fild_membase (code, X86_ESP, 0, TRUE);
3641 /* Change precision */
3642 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3643 x86_fld_membase (code, X86_ESP, 0, TRUE);
3644 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3646 case OP_LCONV_TO_R4_2:
3647 x86_push_reg (code, ins->sreg2);
3648 x86_push_reg (code, ins->sreg1);
3649 x86_fild_membase (code, X86_ESP, 0, TRUE);
3650 /* Change precision */
3651 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3652 x86_fld_membase (code, X86_ESP, 0, FALSE);
3653 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3655 case OP_LCONV_TO_R_UN_2: {
3656 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3659 /* load 64bit integer to FP stack */
3660 x86_push_reg (code, ins->sreg2);
3661 x86_push_reg (code, ins->sreg1);
3662 x86_fild_membase (code, X86_ESP, 0, TRUE);
3664 /* test if lreg is negative */
3665 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3666 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3668 /* add correction constant mn */
3669 if (cfg->compile_aot) {
3670 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3671 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3672 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3673 x86_fld80_membase (code, X86_ESP, 2);
3674 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3676 x86_fld80_mem (code, mn);
3678 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3680 x86_patch (br, code);
3682 /* Change precision */
3683 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3684 x86_fld_membase (code, X86_ESP, 0, TRUE);
3686 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3690 case OP_LCONV_TO_OVF_I:
3691 case OP_LCONV_TO_OVF_I4_2: {
3692 guint8 *br [3], *label [1];
3696 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3698 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3700 /* If the low word top bit is set, see if we are negative */
3701 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3702 /* We are not negative (no top bit set, check for our top word to be zero */
3703 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3704 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3707 /* throw exception */
3708 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3710 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3711 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3712 x86_jump8 (code, 0);
3714 x86_jump32 (code, 0);
3716 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3717 x86_jump32 (code, 0);
3721 x86_patch (br [0], code);
3722 /* our top bit is set, check that top word is 0xfffffff */
3723 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3725 x86_patch (br [1], code);
3726 /* nope, emit exception */
3727 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3728 x86_patch (br [2], label [0]);
3730 if (ins->dreg != ins->sreg1)
3731 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3735 /* Not needed on the fp stack */
3738 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3741 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3744 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3747 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3755 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3760 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3767 * it really doesn't make sense to inline all this code,
3768 * it's here just to show that things may not be as simple
3771 guchar *check_pos, *end_tan, *pop_jump;
3772 x86_push_reg (code, X86_EAX);
3775 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3777 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3778 x86_fstp (code, 0); /* pop the 1.0 */
3780 x86_jump8 (code, 0);
3782 x86_fp_op (code, X86_FADD, 0);
3786 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3788 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3791 x86_patch (pop_jump, code);
3792 x86_fstp (code, 0); /* pop the 1.0 */
3793 x86_patch (check_pos, code);
3794 x86_patch (end_tan, code);
3796 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3797 x86_pop_reg (code, X86_EAX);
3804 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3813 g_assert (cfg->opt & MONO_OPT_CMOV);
3814 g_assert (ins->dreg == ins->sreg1);
3815 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3816 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3819 g_assert (cfg->opt & MONO_OPT_CMOV);
3820 g_assert (ins->dreg == ins->sreg1);
3821 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3822 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3825 g_assert (cfg->opt & MONO_OPT_CMOV);
3826 g_assert (ins->dreg == ins->sreg1);
3827 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3828 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3831 g_assert (cfg->opt & MONO_OPT_CMOV);
3832 g_assert (ins->dreg == ins->sreg1);
3833 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3834 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3840 x86_fxch (code, ins->inst_imm);
3845 x86_push_reg (code, X86_EAX);
3846 /* we need to exchange ST(0) with ST(1) */
3849 /* this requires a loop, because fprem somtimes
3850 * returns a partial remainder */
3852 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3853 /* x86_fprem1 (code); */
3856 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3858 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3864 x86_pop_reg (code, X86_EAX);
3868 if (cfg->opt & MONO_OPT_FCMOV) {
3869 x86_fcomip (code, 1);
3873 /* this overwrites EAX */
3874 EMIT_FPCOMPARE(code);
3875 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3879 if (cfg->opt & MONO_OPT_FCMOV) {
3880 /* zeroing the register at the start results in
3881 * shorter and faster code (we can also remove the widening op)
3883 guchar *unordered_check;
3884 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3885 x86_fcomip (code, 1);
3887 unordered_check = code;
3888 x86_branch8 (code, X86_CC_P, 0, FALSE);
3889 if (ins->opcode == OP_FCEQ) {
3890 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3891 x86_patch (unordered_check, code);
3893 guchar *jump_to_end;
3894 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3896 x86_jump8 (code, 0);
3897 x86_patch (unordered_check, code);
3898 x86_inc_reg (code, ins->dreg);
3899 x86_patch (jump_to_end, code);
3904 if (ins->dreg != X86_EAX)
3905 x86_push_reg (code, X86_EAX);
3907 EMIT_FPCOMPARE(code);
3908 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3909 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3910 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3911 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3913 if (ins->dreg != X86_EAX)
3914 x86_pop_reg (code, X86_EAX);
3918 if (cfg->opt & MONO_OPT_FCMOV) {
3919 /* zeroing the register at the start results in
3920 * shorter and faster code (we can also remove the widening op)
3922 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3923 x86_fcomip (code, 1);
3925 if (ins->opcode == OP_FCLT_UN) {
3926 guchar *unordered_check = code;
3927 guchar *jump_to_end;
3928 x86_branch8 (code, X86_CC_P, 0, FALSE);
3929 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3931 x86_jump8 (code, 0);
3932 x86_patch (unordered_check, code);
3933 x86_inc_reg (code, ins->dreg);
3934 x86_patch (jump_to_end, code);
3936 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3940 if (ins->dreg != X86_EAX)
3941 x86_push_reg (code, X86_EAX);
3943 EMIT_FPCOMPARE(code);
3944 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3945 if (ins->opcode == OP_FCLT_UN) {
3946 guchar *is_not_zero_check, *end_jump;
3947 is_not_zero_check = code;
3948 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3950 x86_jump8 (code, 0);
3951 x86_patch (is_not_zero_check, code);
3952 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3954 x86_patch (end_jump, code);
3956 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3957 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3959 if (ins->dreg != X86_EAX)
3960 x86_pop_reg (code, X86_EAX);
3963 guchar *unordered_check;
3964 guchar *jump_to_end;
3965 if (cfg->opt & MONO_OPT_FCMOV) {
3966 /* zeroing the register at the start results in
3967 * shorter and faster code (we can also remove the widening op)
3969 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3970 x86_fcomip (code, 1);
3972 unordered_check = code;
3973 x86_branch8 (code, X86_CC_P, 0, FALSE);
3974 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3975 x86_patch (unordered_check, code);
3978 if (ins->dreg != X86_EAX)
3979 x86_push_reg (code, X86_EAX);
3981 EMIT_FPCOMPARE(code);
3982 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3983 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3984 unordered_check = code;
3985 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3987 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3988 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3989 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3991 x86_jump8 (code, 0);
3992 x86_patch (unordered_check, code);
3993 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3994 x86_patch (jump_to_end, code);
3996 if (ins->dreg != X86_EAX)
3997 x86_pop_reg (code, X86_EAX);
4002 if (cfg->opt & MONO_OPT_FCMOV) {
4003 /* zeroing the register at the start results in
4004 * shorter and faster code (we can also remove the widening op)
4006 guchar *unordered_check;
4007 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4008 x86_fcomip (code, 1);
4010 if (ins->opcode == OP_FCGT) {
4011 unordered_check = code;
4012 x86_branch8 (code, X86_CC_P, 0, FALSE);
4013 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4014 x86_patch (unordered_check, code);
4016 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4020 if (ins->dreg != X86_EAX)
4021 x86_push_reg (code, X86_EAX);
4023 EMIT_FPCOMPARE(code);
4024 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4025 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4026 if (ins->opcode == OP_FCGT_UN) {
4027 guchar *is_not_zero_check, *end_jump;
4028 is_not_zero_check = code;
4029 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4031 x86_jump8 (code, 0);
4032 x86_patch (is_not_zero_check, code);
4033 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4035 x86_patch (end_jump, code);
4037 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4038 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4040 if (ins->dreg != X86_EAX)
4041 x86_pop_reg (code, X86_EAX);
4044 guchar *unordered_check;
4045 guchar *jump_to_end;
4046 if (cfg->opt & MONO_OPT_FCMOV) {
4047 /* zeroing the register at the start results in
4048 * shorter and faster code (we can also remove the widening op)
4050 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4051 x86_fcomip (code, 1);
4053 unordered_check = code;
4054 x86_branch8 (code, X86_CC_P, 0, FALSE);
4055 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4056 x86_patch (unordered_check, code);
4059 if (ins->dreg != X86_EAX)
4060 x86_push_reg (code, X86_EAX);
4062 EMIT_FPCOMPARE(code);
4063 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4064 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4065 unordered_check = code;
4066 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4068 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4069 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4070 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4072 x86_jump8 (code, 0);
4073 x86_patch (unordered_check, code);
4074 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4075 x86_patch (jump_to_end, code);
4077 if (ins->dreg != X86_EAX)
4078 x86_pop_reg (code, X86_EAX);
4082 if (cfg->opt & MONO_OPT_FCMOV) {
4083 guchar *jump = code;
4084 x86_branch8 (code, X86_CC_P, 0, TRUE);
4085 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4086 x86_patch (jump, code);
4089 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4090 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4093 /* Branch if C013 != 100 */
4094 if (cfg->opt & MONO_OPT_FCMOV) {
4095 /* branch if !ZF or (PF|CF) */
4096 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4097 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4098 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4101 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4102 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4105 if (cfg->opt & MONO_OPT_FCMOV) {
4106 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4109 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4112 if (cfg->opt & MONO_OPT_FCMOV) {
4113 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4114 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4117 if (ins->opcode == OP_FBLT_UN) {
4118 guchar *is_not_zero_check, *end_jump;
4119 is_not_zero_check = code;
4120 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4122 x86_jump8 (code, 0);
4123 x86_patch (is_not_zero_check, code);
4124 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4126 x86_patch (end_jump, code);
4128 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4132 if (cfg->opt & MONO_OPT_FCMOV) {
4133 if (ins->opcode == OP_FBGT) {
4136 /* skip branch if C1=1 */
4138 x86_branch8 (code, X86_CC_P, 0, FALSE);
4139 /* branch if (C0 | C3) = 1 */
4140 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4141 x86_patch (br1, code);
4143 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4147 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4148 if (ins->opcode == OP_FBGT_UN) {
4149 guchar *is_not_zero_check, *end_jump;
4150 is_not_zero_check = code;
4151 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4153 x86_jump8 (code, 0);
4154 x86_patch (is_not_zero_check, code);
4155 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4157 x86_patch (end_jump, code);
4159 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4162 /* Branch if C013 == 100 or 001 */
4163 if (cfg->opt & MONO_OPT_FCMOV) {
4166 /* skip branch if C1=1 */
4168 x86_branch8 (code, X86_CC_P, 0, FALSE);
4169 /* branch if (C0 | C3) = 1 */
4170 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4171 x86_patch (br1, code);
4174 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4175 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4176 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4177 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4180 /* Branch if C013 == 000 */
4181 if (cfg->opt & MONO_OPT_FCMOV) {
4182 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4185 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4188 /* Branch if C013=000 or 100 */
4189 if (cfg->opt & MONO_OPT_FCMOV) {
4192 /* skip branch if C1=1 */
4194 x86_branch8 (code, X86_CC_P, 0, FALSE);
4195 /* branch if C0=0 */
4196 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4197 x86_patch (br1, code);
4200 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4201 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4202 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4205 /* Branch if C013 != 001 */
4206 if (cfg->opt & MONO_OPT_FCMOV) {
4207 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4208 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4211 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4212 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4216 x86_push_reg (code, X86_EAX);
4219 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4220 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4221 x86_pop_reg (code, X86_EAX);
4223 /* Have to clean up the fp stack before throwing the exception */
4225 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4228 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4230 x86_patch (br1, code);
4234 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4237 case OP_TLS_GET_REG: {
4238 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4242 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4245 case OP_TLS_SET_REG: {
4246 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4249 case OP_MEMORY_BARRIER: {
4250 /* x86 only needs barrier for StoreLoad and FullBarrier */
4251 switch (ins->backend.memory_barrier_kind) {
4252 case StoreLoadBarrier:
4254 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4255 x86_prefix (code, X86_LOCK_PREFIX);
4256 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4261 case OP_ATOMIC_ADD_I4: {
4262 int dreg = ins->dreg;
4264 if (dreg == ins->inst_basereg) {
4265 x86_push_reg (code, ins->sreg2);
4269 if (dreg != ins->sreg2)
4270 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
4272 x86_prefix (code, X86_LOCK_PREFIX);
4273 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4275 if (dreg != ins->dreg) {
4276 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4277 x86_pop_reg (code, dreg);
4282 case OP_ATOMIC_ADD_NEW_I4: {
4283 int dreg = ins->dreg;
4285 g_assert (cfg->has_atomic_add_new_i4);
4287 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4288 if (ins->sreg2 == dreg) {
4289 if (dreg == X86_EBX) {
4291 if (ins->inst_basereg == X86_EDI)
4295 if (ins->inst_basereg == X86_EBX)
4298 } else if (ins->inst_basereg == dreg) {
4299 if (dreg == X86_EBX) {
4301 if (ins->sreg2 == X86_EDI)
4305 if (ins->sreg2 == X86_EBX)
4310 if (dreg != ins->dreg) {
4311 x86_push_reg (code, dreg);
4314 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4315 x86_prefix (code, X86_LOCK_PREFIX);
4316 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4317 /* dreg contains the old value, add with sreg2 value */
4318 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4320 if (ins->dreg != dreg) {
4321 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4322 x86_pop_reg (code, dreg);
4327 case OP_ATOMIC_EXCHANGE_I4: {
4329 int sreg2 = ins->sreg2;
4330 int breg = ins->inst_basereg;
4332 g_assert (cfg->has_atomic_exchange_i4);
4334 /* cmpxchg uses eax as comperand, need to make sure we can use it
4335 * hack to overcome limits in x86 reg allocator
4336 * (req: dreg == eax and sreg2 != eax and breg != eax)
4338 g_assert (ins->dreg == X86_EAX);
4340 /* We need the EAX reg for the cmpxchg */
4341 if (ins->sreg2 == X86_EAX) {
4342 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4343 x86_push_reg (code, sreg2);
4344 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4347 if (breg == X86_EAX) {
4348 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4349 x86_push_reg (code, breg);
4350 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4353 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4355 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4356 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4357 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4358 x86_patch (br [1], br [0]);
4360 if (breg != ins->inst_basereg)
4361 x86_pop_reg (code, breg);
4363 if (ins->sreg2 != sreg2)
4364 x86_pop_reg (code, sreg2);
4368 case OP_ATOMIC_CAS_I4: {
4369 g_assert (ins->dreg == X86_EAX);
4370 g_assert (ins->sreg3 == X86_EAX);
4371 g_assert (ins->sreg1 != X86_EAX);
4372 g_assert (ins->sreg1 != ins->sreg2);
4374 x86_prefix (code, X86_LOCK_PREFIX);
4375 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4378 case OP_CARD_TABLE_WBARRIER: {
4379 int ptr = ins->sreg1;
4380 int value = ins->sreg2;
4382 int nursery_shift, card_table_shift;
4383 gpointer card_table_mask;
4384 size_t nursery_size;
4385 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4386 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4387 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4390 * We need one register we can clobber, we choose EDX and make sreg1
4391 * fixed EAX to work around limitations in the local register allocator.
4392 * sreg2 might get allocated to EDX, but that is not a problem since
4393 * we use it before clobbering EDX.
4395 g_assert (ins->sreg1 == X86_EAX);
4398 * This is the code we produce:
4401 * edx >>= nursery_shift
4402 * cmp edx, (nursery_start >> nursery_shift)
4405 * edx >>= card_table_shift
4406 * card_table[edx] = 1
4410 if (card_table_nursery_check) {
4411 if (value != X86_EDX)
4412 x86_mov_reg_reg (code, X86_EDX, value, 4);
4413 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4414 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4415 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4417 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4418 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4419 if (card_table_mask)
4420 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4421 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4422 if (card_table_nursery_check)
4423 x86_patch (br, code);
4426 #ifdef MONO_ARCH_SIMD_INTRINSICS
4428 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4431 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4434 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4437 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4440 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4443 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4446 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4447 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4450 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4453 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4456 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4459 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4462 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4465 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4468 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4471 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4474 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4477 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4480 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4483 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4486 case OP_PSHUFLEW_HIGH:
4487 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4488 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4490 case OP_PSHUFLEW_LOW:
4491 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4492 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4495 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4496 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4499 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4500 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4503 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4504 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4508 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4511 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4514 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4517 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4520 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4523 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4526 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4527 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4530 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4533 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4536 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4539 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4542 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4545 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4548 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4551 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4554 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4557 case OP_EXTRACT_MASK:
4558 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4562 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4565 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4568 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4572 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4575 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4578 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4581 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4585 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4588 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4591 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4594 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4598 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4601 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4604 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4608 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4611 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4614 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4618 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4621 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4625 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4628 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4631 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4635 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4638 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4641 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4645 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4648 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4651 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4654 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4658 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4661 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4664 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4667 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4670 case OP_PSUM_ABS_DIFF:
4671 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4674 case OP_UNPACK_LOWB:
4675 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4677 case OP_UNPACK_LOWW:
4678 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4680 case OP_UNPACK_LOWD:
4681 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4683 case OP_UNPACK_LOWQ:
4684 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4686 case OP_UNPACK_LOWPS:
4687 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4689 case OP_UNPACK_LOWPD:
4690 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4693 case OP_UNPACK_HIGHB:
4694 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4696 case OP_UNPACK_HIGHW:
4697 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4699 case OP_UNPACK_HIGHD:
4700 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4702 case OP_UNPACK_HIGHQ:
4703 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4705 case OP_UNPACK_HIGHPS:
4706 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4708 case OP_UNPACK_HIGHPD:
4709 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4713 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4716 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4719 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4722 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4725 case OP_PADDB_SAT_UN:
4726 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4728 case OP_PSUBB_SAT_UN:
4729 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4731 case OP_PADDW_SAT_UN:
4732 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4734 case OP_PSUBW_SAT_UN:
4735 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4739 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4742 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4745 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4748 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4752 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4755 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4758 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4760 case OP_PMULW_HIGH_UN:
4761 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4764 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4768 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4771 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4775 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4778 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4782 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4785 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4789 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4792 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4796 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4799 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4803 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4806 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4810 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4813 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4817 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4820 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4824 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4827 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4831 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4833 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4834 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4838 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4840 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4841 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4845 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4847 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4848 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4852 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4854 case OP_EXTRACTX_U2:
4855 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4857 case OP_INSERTX_U1_SLOW:
4858 /*sreg1 is the extracted ireg (scratch)
4859 /sreg2 is the to be inserted ireg (scratch)
4860 /dreg is the xreg to receive the value*/
4862 /*clear the bits from the extracted word*/
4863 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4864 /*shift the value to insert if needed*/
4865 if (ins->inst_c0 & 1)
4866 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4867 /*join them together*/
4868 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4869 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4871 case OP_INSERTX_I4_SLOW:
4872 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4873 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4874 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4877 case OP_INSERTX_R4_SLOW:
4878 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4879 /*TODO if inst_c0 == 0 use movss*/
4880 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4881 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4883 case OP_INSERTX_R8_SLOW:
4884 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4885 if (cfg->verbose_level)
4886 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4888 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4890 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4893 case OP_STOREX_MEMBASE_REG:
4894 case OP_STOREX_MEMBASE:
4895 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4897 case OP_LOADX_MEMBASE:
4898 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4900 case OP_LOADX_ALIGNED_MEMBASE:
4901 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4903 case OP_STOREX_ALIGNED_MEMBASE_REG:
4904 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4906 case OP_STOREX_NTA_MEMBASE_REG:
4907 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4909 case OP_PREFETCH_MEMBASE:
4910 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4914 /*FIXME the peephole pass should have killed this*/
4915 if (ins->dreg != ins->sreg1)
4916 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4919 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4921 case OP_ICONV_TO_R8_RAW:
4922 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4923 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4926 case OP_FCONV_TO_R8_X:
4927 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4928 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4931 case OP_XCONV_R8_TO_I4:
4932 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4933 switch (ins->backend.source_opcode) {
4934 case OP_FCONV_TO_I1:
4935 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4937 case OP_FCONV_TO_U1:
4938 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4940 case OP_FCONV_TO_I2:
4941 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4943 case OP_FCONV_TO_U2:
4944 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4950 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4951 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4952 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4953 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4954 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4955 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4958 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4959 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4960 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4963 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4964 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4967 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4968 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4969 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4972 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4973 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4974 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4978 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4981 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4984 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4987 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4990 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4993 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4996 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4999 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
5003 case OP_LIVERANGE_START: {
5004 if (cfg->verbose_level > 1)
5005 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5006 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5009 case OP_LIVERANGE_END: {
5010 if (cfg->verbose_level > 1)
5011 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5012 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5015 case OP_NACL_GC_SAFE_POINT: {
5016 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
5017 if (cfg->compile_aot)
5018 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5022 x86_test_mem_imm8 (code, (gpointer)&__nacl_thread_suspension_needed, 0xFFFFFFFF);
5023 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
5024 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5025 x86_patch (br[0], code);
5030 case OP_GC_LIVENESS_DEF:
5031 case OP_GC_LIVENESS_USE:
5032 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5033 ins->backend.pc_offset = code - cfg->native_code;
5035 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5036 ins->backend.pc_offset = code - cfg->native_code;
5037 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5040 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
5043 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
5046 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
5047 g_assert_not_reached ();
5050 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
5051 #ifndef __native_client_codegen__
5052 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5053 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5054 g_assert_not_reached ();
5055 #endif /* __native_client_codegen__ */
5061 cfg->code_len = code - cfg->native_code;
5064 #endif /* DISABLE_JIT */
5067 mono_arch_register_lowlevel_calls (void)
5072 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
5074 MonoJumpInfo *patch_info;
5075 gboolean compile_aot = !run_cctors;
5077 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5078 unsigned char *ip = patch_info->ip.i + code;
5079 const unsigned char *target;
5082 switch (patch_info->type) {
5083 case MONO_PATCH_INFO_BB:
5084 case MONO_PATCH_INFO_LABEL:
5087 /* No need to patch these */
5092 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5094 switch (patch_info->type) {
5095 case MONO_PATCH_INFO_IP:
5096 *((gconstpointer *)(ip)) = target;
5098 case MONO_PATCH_INFO_CLASS_INIT: {
5100 /* Might already been changed to a nop */
5101 x86_call_code (code, 0);
5102 x86_patch (ip, target);
5105 case MONO_PATCH_INFO_ABS:
5106 case MONO_PATCH_INFO_METHOD:
5107 case MONO_PATCH_INFO_METHOD_JUMP:
5108 case MONO_PATCH_INFO_INTERNAL_METHOD:
5109 case MONO_PATCH_INFO_BB:
5110 case MONO_PATCH_INFO_LABEL:
5111 case MONO_PATCH_INFO_RGCTX_FETCH:
5112 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
5113 case MONO_PATCH_INFO_MONITOR_ENTER:
5114 case MONO_PATCH_INFO_MONITOR_EXIT:
5115 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5116 #if defined(__native_client_codegen__) && defined(__native_client__)
5117 if (nacl_is_code_address (code)) {
5118 /* For tail calls, code is patched after being installed */
5119 /* but not through the normal "patch callsite" method. */
5120 unsigned char buf[kNaClAlignment];
5121 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5122 unsigned char *_target = target;
5124 /* All patch targets modified in x86_patch */
5125 /* are IP relative. */
5126 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5127 memcpy (buf, aligned_code, kNaClAlignment);
5128 /* Patch a temp buffer of bundle size, */
5129 /* then install to actual location. */
5130 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5131 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5132 g_assert (ret == 0);
5135 x86_patch (ip, target);
5138 x86_patch (ip, target);
5141 case MONO_PATCH_INFO_NONE:
5143 case MONO_PATCH_INFO_R4:
5144 case MONO_PATCH_INFO_R8: {
5145 guint32 offset = mono_arch_get_patch_offset (ip);
5146 *((gconstpointer *)(ip + offset)) = target;
5150 guint32 offset = mono_arch_get_patch_offset (ip);
5151 #if !defined(__native_client__)
5152 *((gconstpointer *)(ip + offset)) = target;
5154 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5162 static G_GNUC_UNUSED void
5163 stack_unaligned (MonoMethod *m, gpointer caller)
5165 printf ("%s\n", mono_method_full_name (m, TRUE));
5166 g_assert_not_reached ();
5170 mono_arch_emit_prolog (MonoCompile *cfg)
5172 MonoMethod *method = cfg->method;
5174 MonoMethodSignature *sig;
5176 int alloc_size, pos, max_offset, i, cfa_offset;
5178 gboolean need_stack_frame;
5179 #ifdef __native_client_codegen__
5180 guint alignment_check;
5183 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5185 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5186 cfg->code_size += 512;
5188 #if defined(__default_codegen__)
5189 code = cfg->native_code = g_malloc (cfg->code_size);
5190 #elif defined(__native_client_codegen__)
5191 /* native_code_alloc is not 32-byte aligned, native_code is. */
5192 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5193 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5195 /* Align native_code to next nearest kNaclAlignment byte. */
5196 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5197 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5199 code = cfg->native_code;
5201 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5202 g_assert(alignment_check == 0);
5209 /* Check that the stack is aligned on osx */
5210 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5211 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5212 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5214 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5215 x86_push_membase (code, X86_ESP, 0);
5216 x86_push_imm (code, cfg->method);
5217 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5218 x86_call_reg (code, X86_EAX);
5219 x86_patch (br [0], code);
5223 /* Offset between RSP and the CFA */
5227 cfa_offset = sizeof (gpointer);
5228 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5229 // IP saved at CFA - 4
5230 /* There is no IP reg on x86 */
5231 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5232 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5234 need_stack_frame = needs_stack_frame (cfg);
5236 if (need_stack_frame) {
5237 x86_push_reg (code, X86_EBP);
5238 cfa_offset += sizeof (gpointer);
5239 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5240 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5241 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5242 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5243 /* These are handled automatically by the stack marking code */
5244 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5246 cfg->frame_reg = X86_ESP;
5249 alloc_size = cfg->stack_offset;
5252 if (!method->save_lmf) {
5253 if (cfg->used_int_regs & (1 << X86_EBX)) {
5254 x86_push_reg (code, X86_EBX);
5256 cfa_offset += sizeof (gpointer);
5257 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5258 /* These are handled automatically by the stack marking code */
5259 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5262 if (cfg->used_int_regs & (1 << X86_EDI)) {
5263 x86_push_reg (code, X86_EDI);
5265 cfa_offset += sizeof (gpointer);
5266 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5267 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5270 if (cfg->used_int_regs & (1 << X86_ESI)) {
5271 x86_push_reg (code, X86_ESI);
5273 cfa_offset += sizeof (gpointer);
5274 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5275 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5281 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5282 if (mono_do_x86_stack_align && need_stack_frame) {
5283 int tot = alloc_size + pos + 4; /* ret ip */
5284 if (need_stack_frame)
5286 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5288 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5289 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5290 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5294 cfg->arch.sp_fp_offset = alloc_size + pos;
5297 /* See mono_emit_stack_alloc */
5298 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5299 guint32 remaining_size = alloc_size;
5300 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5301 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5302 guint32 offset = code - cfg->native_code;
5303 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5304 while (required_code_size >= (cfg->code_size - offset))
5305 cfg->code_size *= 2;
5306 cfg->native_code = mono_realloc_native_code(cfg);
5307 code = cfg->native_code + offset;
5308 cfg->stat_code_reallocs++;
5310 while (remaining_size >= 0x1000) {
5311 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5312 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5313 remaining_size -= 0x1000;
5316 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5318 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5321 g_assert (need_stack_frame);
5324 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5325 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5326 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5329 #if DEBUG_STACK_ALIGNMENT
5330 /* check the stack is aligned */
5331 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5332 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5333 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5334 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5335 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5336 x86_breakpoint (code);
5340 /* compute max_offset in order to use short forward jumps */
5342 if (cfg->opt & MONO_OPT_BRANCH) {
5343 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5345 bb->max_offset = max_offset;
5347 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5349 /* max alignment for loops */
5350 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5351 max_offset += LOOP_ALIGNMENT;
5352 #ifdef __native_client_codegen__
5353 /* max alignment for native client */
5354 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5355 max_offset += kNaClAlignment;
5357 MONO_BB_FOR_EACH_INS (bb, ins) {
5358 if (ins->opcode == OP_LABEL)
5359 ins->inst_c1 = max_offset;
5360 #ifdef __native_client_codegen__
5361 switch (ins->opcode)
5373 case OP_VOIDCALL_REG:
5375 case OP_FCALL_MEMBASE:
5376 case OP_LCALL_MEMBASE:
5377 case OP_VCALL_MEMBASE:
5378 case OP_VCALL2_MEMBASE:
5379 case OP_VOIDCALL_MEMBASE:
5380 case OP_CALL_MEMBASE:
5381 max_offset += kNaClAlignment;
5384 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5387 #endif /* __native_client_codegen__ */
5388 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5393 /* store runtime generic context */
5394 if (cfg->rgctx_var) {
5395 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5397 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5400 if (method->save_lmf)
5401 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5403 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5404 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5406 /* load arguments allocated to register from the stack */
5407 sig = mono_method_signature (method);
5410 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5411 inst = cfg->args [pos];
5412 if (inst->opcode == OP_REGVAR) {
5413 g_assert (need_stack_frame);
5414 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5415 if (cfg->verbose_level > 2)
5416 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5421 cfg->code_len = code - cfg->native_code;
5423 g_assert (cfg->code_len < cfg->code_size);
5429 mono_arch_emit_epilog (MonoCompile *cfg)
5431 MonoMethod *method = cfg->method;
5432 MonoMethodSignature *sig = mono_method_signature (method);
5434 guint32 stack_to_pop;
5436 int max_epilog_size = 16;
5438 gboolean need_stack_frame = needs_stack_frame (cfg);
5440 if (cfg->method->save_lmf)
5441 max_epilog_size += 128;
5443 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5444 cfg->code_size *= 2;
5445 cfg->native_code = mono_realloc_native_code(cfg);
5446 cfg->stat_code_reallocs++;
5449 code = cfg->native_code + cfg->code_len;
5451 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5452 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5454 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5457 if (method->save_lmf) {
5458 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5460 gboolean supported = FALSE;
5462 if (cfg->compile_aot) {
5463 #if defined(__APPLE__) || defined(__linux__)
5466 } else if (mono_get_jit_tls_offset () != -1) {
5470 /* check if we need to restore protection of the stack after a stack overflow */
5472 if (cfg->compile_aot) {
5473 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5475 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5477 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5480 /* we load the value in a separate instruction: this mechanism may be
5481 * used later as a safer way to do thread interruption
5483 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5484 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5486 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5487 /* note that the call trampoline will preserve eax/edx */
5488 x86_call_reg (code, X86_ECX);
5489 x86_patch (patch, code);
5491 /* FIXME: maybe save the jit tls in the prolog */
5494 /* restore caller saved regs */
5495 if (cfg->used_int_regs & (1 << X86_EBX)) {
5496 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
5499 if (cfg->used_int_regs & (1 << X86_EDI)) {
5500 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
5502 if (cfg->used_int_regs & (1 << X86_ESI)) {
5503 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
5506 /* EBP is restored by LEAVE */
5508 for (i = 0; i < X86_NREG; ++i) {
5509 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5515 g_assert (need_stack_frame);
5516 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5520 g_assert (need_stack_frame);
5521 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5524 if (cfg->used_int_regs & (1 << X86_ESI)) {
5525 x86_pop_reg (code, X86_ESI);
5527 if (cfg->used_int_regs & (1 << X86_EDI)) {
5528 x86_pop_reg (code, X86_EDI);
5530 if (cfg->used_int_regs & (1 << X86_EBX)) {
5531 x86_pop_reg (code, X86_EBX);
5535 /* Load returned vtypes into registers if needed */
5536 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5537 if (cinfo->ret.storage == ArgValuetypeInReg) {
5538 for (quad = 0; quad < 2; quad ++) {
5539 switch (cinfo->ret.pair_storage [quad]) {
5541 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5543 case ArgOnFloatFpStack:
5544 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5546 case ArgOnDoubleFpStack:
5547 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5552 g_assert_not_reached ();
5557 if (need_stack_frame)
5560 if (CALLCONV_IS_STDCALL (sig)) {
5561 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5563 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5564 } else if (cinfo->vtype_retaddr)
5570 g_assert (need_stack_frame);
5571 x86_ret_imm (code, stack_to_pop);
5576 cfg->code_len = code - cfg->native_code;
5578 g_assert (cfg->code_len < cfg->code_size);
5582 mono_arch_emit_exceptions (MonoCompile *cfg)
5584 MonoJumpInfo *patch_info;
5587 MonoClass *exc_classes [16];
5588 guint8 *exc_throw_start [16], *exc_throw_end [16];
5592 /* Compute needed space */
5593 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5594 if (patch_info->type == MONO_PATCH_INFO_EXC)
5599 * make sure we have enough space for exceptions
5600 * 16 is the size of two push_imm instructions and a call
5602 if (cfg->compile_aot)
5603 code_size = exc_count * 32;
5605 code_size = exc_count * 16;
5607 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5608 cfg->code_size *= 2;
5609 cfg->native_code = mono_realloc_native_code(cfg);
5610 cfg->stat_code_reallocs++;
5613 code = cfg->native_code + cfg->code_len;
5616 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5617 switch (patch_info->type) {
5618 case MONO_PATCH_INFO_EXC: {
5619 MonoClass *exc_class;
5623 x86_patch (patch_info->ip.i + cfg->native_code, code);
5625 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5626 g_assert (exc_class);
5627 throw_ip = patch_info->ip.i;
5629 /* Find a throw sequence for the same exception class */
5630 for (i = 0; i < nthrows; ++i)
5631 if (exc_classes [i] == exc_class)
5634 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5635 x86_jump_code (code, exc_throw_start [i]);
5636 patch_info->type = MONO_PATCH_INFO_NONE;
5641 /* Compute size of code following the push <OFFSET> */
5642 #if defined(__default_codegen__)
5644 #elif defined(__native_client_codegen__)
5645 code = mono_nacl_align (code);
5646 size = kNaClAlignment;
5648 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5650 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5651 /* Use the shorter form */
5653 x86_push_imm (code, 0);
5657 x86_push_imm (code, 0xf0f0f0f0);
5662 exc_classes [nthrows] = exc_class;
5663 exc_throw_start [nthrows] = code;
5666 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5667 patch_info->data.name = "mono_arch_throw_corlib_exception";
5668 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5669 patch_info->ip.i = code - cfg->native_code;
5670 x86_call_code (code, 0);
5671 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5676 exc_throw_end [nthrows] = code;
5688 cfg->code_len = code - cfg->native_code;
5690 g_assert (cfg->code_len < cfg->code_size);
5694 mono_arch_flush_icache (guint8 *code, gint size)
5700 mono_arch_flush_register_windows (void)
5705 mono_arch_is_inst_imm (gint64 imm)
5711 mono_arch_finish_init (void)
5713 if (!g_getenv ("MONO_NO_TLS")) {
5714 #ifndef TARGET_WIN32
5716 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5723 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5727 #ifdef MONO_ARCH_HAVE_IMT
5729 // Linear handler, the bsearch head compare is shorter
5730 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5731 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5732 // x86_patch(ins,target)
5733 //[1 + 5] x86_jump_mem(inst,mem)
5736 #if defined(__default_codegen__)
5737 #define BR_SMALL_SIZE 2
5738 #define BR_LARGE_SIZE 5
5739 #elif defined(__native_client_codegen__)
5740 /* I suspect the size calculation below is actually incorrect. */
5741 /* TODO: fix the calculation that uses these sizes. */
5742 #define BR_SMALL_SIZE 16
5743 #define BR_LARGE_SIZE 12
5744 #endif /*__native_client_codegen__*/
5745 #define JUMP_IMM_SIZE 6
5746 #define ENABLE_WRONG_METHOD_CHECK 0
5750 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5752 int i, distance = 0;
5753 for (i = start; i < target; ++i)
5754 distance += imt_entries [i]->chunk_size;
5759 * LOCKING: called with the domain lock held
5762 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5763 gpointer fail_tramp)
5767 guint8 *code, *start;
5769 for (i = 0; i < count; ++i) {
5770 MonoIMTCheckItem *item = imt_entries [i];
5771 if (item->is_equals) {
5772 if (item->check_target_idx) {
5773 if (!item->compare_done)
5774 item->chunk_size += CMP_SIZE;
5775 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5778 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5780 item->chunk_size += JUMP_IMM_SIZE;
5781 #if ENABLE_WRONG_METHOD_CHECK
5782 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5787 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5788 imt_entries [item->check_target_idx]->compare_done = TRUE;
5790 size += item->chunk_size;
5792 #if defined(__native_client__) && defined(__native_client_codegen__)
5793 /* In Native Client, we don't re-use thunks, allocate from the */
5794 /* normal code manager paths. */
5795 size = NACL_BUNDLE_ALIGN_UP (size);
5796 code = mono_domain_code_reserve (domain, size);
5799 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5801 code = mono_domain_code_reserve (domain, size);
5804 for (i = 0; i < count; ++i) {
5805 MonoIMTCheckItem *item = imt_entries [i];
5806 item->code_target = code;
5807 if (item->is_equals) {
5808 if (item->check_target_idx) {
5809 if (!item->compare_done)
5810 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5811 item->jmp_code = code;
5812 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5813 if (item->has_target_code)
5814 x86_jump_code (code, item->value.target_code);
5816 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5819 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5820 item->jmp_code = code;
5821 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5822 if (item->has_target_code)
5823 x86_jump_code (code, item->value.target_code);
5825 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5826 x86_patch (item->jmp_code, code);
5827 x86_jump_code (code, fail_tramp);
5828 item->jmp_code = NULL;
5830 /* enable the commented code to assert on wrong method */
5831 #if ENABLE_WRONG_METHOD_CHECK
5832 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5833 item->jmp_code = code;
5834 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5836 if (item->has_target_code)
5837 x86_jump_code (code, item->value.target_code);
5839 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5840 #if ENABLE_WRONG_METHOD_CHECK
5841 x86_patch (item->jmp_code, code);
5842 x86_breakpoint (code);
5843 item->jmp_code = NULL;
5848 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5849 item->jmp_code = code;
5850 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5851 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5853 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5856 /* patch the branches to get to the target items */
5857 for (i = 0; i < count; ++i) {
5858 MonoIMTCheckItem *item = imt_entries [i];
5859 if (item->jmp_code) {
5860 if (item->check_target_idx) {
5861 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5867 mono_stats.imt_thunks_size += code - start;
5868 g_assert (code - start <= size);
5872 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5873 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5877 if (mono_jit_map_is_enabled ()) {
5880 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5882 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5883 mono_emit_jit_tramp (start, code - start, buff);
5887 nacl_domain_code_validate (domain, &start, size, &code);
5893 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5895 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5900 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5902 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5906 mono_arch_get_cie_program (void)
5910 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5911 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5917 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5919 MonoInst *ins = NULL;
5922 if (cmethod->klass == mono_defaults.math_class) {
5923 if (strcmp (cmethod->name, "Sin") == 0) {
5925 } else if (strcmp (cmethod->name, "Cos") == 0) {
5927 } else if (strcmp (cmethod->name, "Tan") == 0) {
5929 } else if (strcmp (cmethod->name, "Atan") == 0) {
5931 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5933 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5935 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5940 MONO_INST_NEW (cfg, ins, opcode);
5941 ins->type = STACK_R8;
5942 ins->dreg = mono_alloc_freg (cfg);
5943 ins->sreg1 = args [0]->dreg;
5944 MONO_ADD_INS (cfg->cbb, ins);
5947 if (cfg->opt & MONO_OPT_CMOV) {
5950 if (strcmp (cmethod->name, "Min") == 0) {
5951 if (fsig->params [0]->type == MONO_TYPE_I4)
5953 } else if (strcmp (cmethod->name, "Max") == 0) {
5954 if (fsig->params [0]->type == MONO_TYPE_I4)
5959 MONO_INST_NEW (cfg, ins, opcode);
5960 ins->type = STACK_I4;
5961 ins->dreg = mono_alloc_ireg (cfg);
5962 ins->sreg1 = args [0]->dreg;
5963 ins->sreg2 = args [1]->dreg;
5964 MONO_ADD_INS (cfg->cbb, ins);
5969 /* OP_FREM is not IEEE compatible */
5970 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5971 MONO_INST_NEW (cfg, ins, OP_FREM);
5972 ins->inst_i0 = args [0];
5973 ins->inst_i1 = args [1];
5982 mono_arch_print_tree (MonoInst *tree, int arity)
5988 mono_arch_get_patch_offset (guint8 *code)
5990 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5992 else if (code [0] == 0xba)
5994 else if (code [0] == 0x68)
5997 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5998 /* push <OFFSET>(<REG>) */
6000 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
6001 /* call *<OFFSET>(<REG>) */
6003 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
6006 else if ((code [0] == 0x58) && (code [1] == 0x05))
6007 /* pop %eax; add <OFFSET>, %eax */
6009 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6010 /* pop <REG>; add <OFFSET>, <REG> */
6012 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6013 /* mov <REG>, imm */
6016 g_assert_not_reached ();
6022 * mono_breakpoint_clean_code:
6024 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6025 * breakpoints in the original code, they are removed in the copy.
6027 * Returns TRUE if no sw breakpoint was present.
6030 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6033 gboolean can_write = TRUE;
6035 * If method_start is non-NULL we need to perform bound checks, since we access memory
6036 * at code - offset we could go before the start of the method and end up in a different
6037 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6040 if (!method_start || code - offset >= method_start) {
6041 memcpy (buf, code - offset, size);
6043 int diff = code - method_start;
6044 memset (buf, 0, size);
6045 memcpy (buf + offset - diff, method_start, diff + size - offset);
6048 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6049 int idx = mono_breakpoint_info_index [i];
6053 ptr = mono_breakpoint_info [idx].address;
6054 if (ptr >= code && ptr < code + size) {
6055 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6057 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6058 buf [ptr - code] = saved_byte;
6065 * mono_x86_get_this_arg_offset:
6067 * Return the offset of the stack location where this is passed during a virtual
6071 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6077 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6079 guint32 esp = regs [X86_ESP];
6080 CallInfo *cinfo = NULL;
6087 * The stack looks like:
6091 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
6093 res = (((MonoObject**)esp) [5 + (offset / 4)]);
6099 #define MAX_ARCH_DELEGATE_PARAMS 10
6102 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6104 guint8 *code, *start;
6105 int code_reserve = 64;
6108 * The stack contains:
6114 start = code = mono_global_codeman_reserve (code_reserve);
6116 /* Replace the this argument with the target */
6117 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6118 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
6119 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6120 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6122 g_assert ((code - start) < code_reserve);
6125 /* 8 for mov_reg and jump, plus 8 for each parameter */
6126 #ifdef __native_client_codegen__
6127 /* TODO: calculate this size correctly */
6128 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6130 code_reserve = 8 + (param_count * 8);
6131 #endif /* __native_client_codegen__ */
6133 * The stack contains:
6134 * <args in reverse order>
6139 * <args in reverse order>
6142 * without unbalancing the stack.
6143 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6144 * and leaving original spot of first arg as placeholder in stack so
6145 * when callee pops stack everything works.
6148 start = code = mono_global_codeman_reserve (code_reserve);
6150 /* store delegate for access to method_ptr */
6151 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6154 for (i = 0; i < param_count; ++i) {
6155 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6156 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6159 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6161 g_assert ((code - start) < code_reserve);
6164 nacl_global_codeman_validate(&start, code_reserve, &code);
6165 mono_debug_add_delegate_trampoline (start, code - start);
6168 *code_len = code - start;
6170 if (mono_jit_map_is_enabled ()) {
6173 buff = (char*)"delegate_invoke_has_target";
6175 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6176 mono_emit_jit_tramp (start, code - start, buff);
6185 mono_arch_get_delegate_invoke_impls (void)
6193 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6194 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
6196 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6197 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6198 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
6199 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
6200 g_free (tramp_name);
6207 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6209 guint8 *code, *start;
6211 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6214 /* FIXME: Support more cases */
6215 if (MONO_TYPE_ISSTRUCT (sig->ret))
6219 * The stack contains:
6225 static guint8* cached = NULL;
6230 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6232 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6234 mono_memory_barrier ();
6238 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6241 for (i = 0; i < sig->param_count; ++i)
6242 if (!mono_is_regsize_var (sig->params [i]))
6245 code = cache [sig->param_count];
6249 if (mono_aot_only) {
6250 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6251 start = mono_aot_get_trampoline (name);
6254 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6257 mono_memory_barrier ();
6259 cache [sig->param_count] = start;
6266 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6269 case X86_EAX: return ctx->eax;
6270 case X86_EBX: return ctx->ebx;
6271 case X86_ECX: return ctx->ecx;
6272 case X86_EDX: return ctx->edx;
6273 case X86_ESP: return ctx->esp;
6274 case X86_EBP: return ctx->ebp;
6275 case X86_ESI: return ctx->esi;
6276 case X86_EDI: return ctx->edi;
6278 g_assert_not_reached ();
6284 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6312 g_assert_not_reached ();
6316 #ifdef MONO_ARCH_SIMD_INTRINSICS
6319 get_float_to_x_spill_area (MonoCompile *cfg)
6321 if (!cfg->fconv_to_r8_x_var) {
6322 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6323 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6325 return cfg->fconv_to_r8_x_var;
6329 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6332 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6335 int dreg, src_opcode;
6337 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6340 switch (src_opcode = ins->opcode) {
6341 case OP_FCONV_TO_I1:
6342 case OP_FCONV_TO_U1:
6343 case OP_FCONV_TO_I2:
6344 case OP_FCONV_TO_U2:
6345 case OP_FCONV_TO_I4:
6352 /* dreg is the IREG and sreg1 is the FREG */
6353 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6354 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6355 fconv->sreg1 = ins->sreg1;
6356 fconv->dreg = mono_alloc_ireg (cfg);
6357 fconv->type = STACK_VTYPE;
6358 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6360 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6364 ins->opcode = OP_XCONV_R8_TO_I4;
6366 ins->klass = mono_defaults.int32_class;
6367 ins->sreg1 = fconv->dreg;
6369 ins->type = STACK_I4;
6370 ins->backend.source_opcode = src_opcode;
6373 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6376 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6381 if (long_ins->opcode == OP_LNEG) {
6383 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6384 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6385 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6390 #ifdef MONO_ARCH_SIMD_INTRINSICS
6392 if (!(cfg->opt & MONO_OPT_SIMD))
6395 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6396 switch (long_ins->opcode) {
6398 vreg = long_ins->sreg1;
6400 if (long_ins->inst_c0) {
6401 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6402 ins->klass = long_ins->klass;
6403 ins->sreg1 = long_ins->sreg1;
6405 ins->type = STACK_VTYPE;
6406 ins->dreg = vreg = alloc_ireg (cfg);
6407 MONO_ADD_INS (cfg->cbb, ins);
6410 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6411 ins->klass = mono_defaults.int32_class;
6413 ins->type = STACK_I4;
6414 ins->dreg = long_ins->dreg + 1;
6415 MONO_ADD_INS (cfg->cbb, ins);
6417 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6418 ins->klass = long_ins->klass;
6419 ins->sreg1 = long_ins->sreg1;
6420 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6421 ins->type = STACK_VTYPE;
6422 ins->dreg = vreg = alloc_ireg (cfg);
6423 MONO_ADD_INS (cfg->cbb, ins);
6425 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6426 ins->klass = mono_defaults.int32_class;
6428 ins->type = STACK_I4;
6429 ins->dreg = long_ins->dreg + 2;
6430 MONO_ADD_INS (cfg->cbb, ins);
6432 long_ins->opcode = OP_NOP;
6434 case OP_INSERTX_I8_SLOW:
6435 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6436 ins->dreg = long_ins->dreg;
6437 ins->sreg1 = long_ins->dreg;
6438 ins->sreg2 = long_ins->sreg2 + 1;
6439 ins->inst_c0 = long_ins->inst_c0 * 2;
6440 MONO_ADD_INS (cfg->cbb, ins);
6442 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6443 ins->dreg = long_ins->dreg;
6444 ins->sreg1 = long_ins->dreg;
6445 ins->sreg2 = long_ins->sreg2 + 2;
6446 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6447 MONO_ADD_INS (cfg->cbb, ins);
6449 long_ins->opcode = OP_NOP;
6452 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6453 ins->dreg = long_ins->dreg;
6454 ins->sreg1 = long_ins->sreg1 + 1;
6455 ins->klass = long_ins->klass;
6456 ins->type = STACK_VTYPE;
6457 MONO_ADD_INS (cfg->cbb, ins);
6459 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6460 ins->dreg = long_ins->dreg;
6461 ins->sreg1 = long_ins->dreg;
6462 ins->sreg2 = long_ins->sreg1 + 2;
6464 ins->klass = long_ins->klass;
6465 ins->type = STACK_VTYPE;
6466 MONO_ADD_INS (cfg->cbb, ins);
6468 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6469 ins->dreg = long_ins->dreg;
6470 ins->sreg1 = long_ins->dreg;;
6471 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6472 ins->klass = long_ins->klass;
6473 ins->type = STACK_VTYPE;
6474 MONO_ADD_INS (cfg->cbb, ins);
6476 long_ins->opcode = OP_NOP;
6479 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6482 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6484 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6487 gpointer *sp, old_value;
6490 offset = clause->exvar_offset;
6493 bp = MONO_CONTEXT_GET_BP (ctx);
6494 sp = *(gpointer*)(bp + offset);
6497 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6506 * mono_aot_emit_load_got_addr:
6508 * Emit code to load the got address.
6509 * On x86, the result is placed into EBX.
6512 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6514 x86_call_imm (code, 0);
6516 * The patch needs to point to the pop, since the GOT offset needs
6517 * to be added to that address.
6520 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6522 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6523 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6524 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6530 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6533 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6535 g_assert_not_reached ();
6536 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6541 * mono_arch_emit_load_aotconst:
6543 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6544 * TARGET from the mscorlib GOT in full-aot code.
6545 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6549 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6551 /* Load the mscorlib got address */
6552 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6553 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6554 /* arch_emit_got_access () patches this */
6555 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6560 /* Can't put this into mini-x86.h */
6562 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6565 mono_arch_get_trampolines (gboolean aot)
6567 MonoTrampInfo *info;
6568 GSList *tramps = NULL;
6570 mono_x86_get_signal_exception_trampoline (&info, aot);
6572 tramps = g_slist_append (tramps, info);
6579 #define DBG_SIGNAL SIGBUS
6581 #define DBG_SIGNAL SIGSEGV
6584 /* Soft Debug support */
6585 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6588 * mono_arch_set_breakpoint:
6590 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6591 * The location should contain code emitted by OP_SEQ_POINT.
6594 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6599 * In production, we will use int3 (has to fix the size in the md
6600 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6603 g_assert (code [0] == 0x90);
6604 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6608 * mono_arch_clear_breakpoint:
6610 * Clear the breakpoint at IP.
6613 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6618 for (i = 0; i < 6; ++i)
6623 * mono_arch_start_single_stepping:
6625 * Start single stepping.
6628 mono_arch_start_single_stepping (void)
6630 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6634 * mono_arch_stop_single_stepping:
6636 * Stop single stepping.
6639 mono_arch_stop_single_stepping (void)
6641 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6645 * mono_arch_is_single_step_event:
6647 * Return whenever the machine state in SIGCTX corresponds to a single
6651 mono_arch_is_single_step_event (void *info, void *sigctx)
6654 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6656 if (((gpointer)einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6661 siginfo_t* sinfo = (siginfo_t*) info;
6662 /* Sometimes the address is off by 4 */
6663 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6671 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6674 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6675 if (((gpointer)einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6680 siginfo_t* sinfo = (siginfo_t*)info;
6681 /* Sometimes the address is off by 4 */
6682 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6689 #define BREAKPOINT_SIZE 6
6692 * mono_arch_skip_breakpoint:
6694 * See mini-amd64.c for docs.
6697 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6699 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6703 * mono_arch_skip_single_step:
6705 * See mini-amd64.c for docs.
6708 mono_arch_skip_single_step (MonoContext *ctx)
6710 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6714 * mono_arch_get_seq_point_info:
6716 * See mini-amd64.c for docs.
6719 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6726 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6728 ext->lmf.previous_lmf = (gsize)prev_lmf;
6729 /* Mark that this is a MonoLMFExt */
6730 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6731 ext->lmf.ebp = (gssize)ext;
6736 #if defined(ENABLE_GSHAREDVT)
6738 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6740 #endif /* !MONOTOUCH */