2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * (C) 2003 Ximian, Inc.
18 #include <mono/metadata/appdomain.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/metadata/threads.h>
21 #include <mono/metadata/profiler-private.h>
22 #include <mono/metadata/mono-debug.h>
23 #include <mono/utils/mono-math.h>
24 #include <mono/utils/mono-counters.h>
25 #include <mono/utils/mono-mmap.h>
32 /* On windows, these hold the key returned by TlsAlloc () */
33 static gint lmf_tls_offset = -1;
34 static gint lmf_addr_tls_offset = -1;
35 static gint appdomain_tls_offset = -1;
38 static gboolean optimize_for_xen = TRUE;
40 #define optimize_for_xen 0
44 static gboolean is_win32 = TRUE;
46 static gboolean is_win32 = FALSE;
49 /* This mutex protects architecture specific caches */
50 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
51 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
52 static CRITICAL_SECTION mini_arch_mutex;
54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
59 /* Under windows, the default pinvoke calling convention is stdcall */
60 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT))
62 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL)
66 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
69 * The code generated for sequence points reads from this location, which is
70 * made read-only when single stepping is enabled.
72 static gpointer ss_trigger_page;
74 /* Enabled breakpoints read from this trigger page */
75 static gpointer bp_trigger_page;
78 mono_arch_regname (int reg)
81 case X86_EAX: return "%eax";
82 case X86_EBX: return "%ebx";
83 case X86_ECX: return "%ecx";
84 case X86_EDX: return "%edx";
85 case X86_ESP: return "%esp";
86 case X86_EBP: return "%ebp";
87 case X86_EDI: return "%edi";
88 case X86_ESI: return "%esi";
94 mono_arch_fregname (int reg)
119 mono_arch_xregname (int reg)
160 /* Only if storage == ArgValuetypeInReg */
161 ArgStorage pair_storage [2];
170 gboolean need_stack_align;
171 guint32 stack_align_amount;
179 #define FLOAT_PARAM_REGS 0
181 static X86_Reg_No param_regs [] = { 0 };
183 #if defined(PLATFORM_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
184 #define SMALL_STRUCTS_IN_REGS
185 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
189 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
191 ainfo->offset = *stack_size;
193 if (*gr >= PARAM_REGS) {
194 ainfo->storage = ArgOnStack;
195 (*stack_size) += sizeof (gpointer);
198 ainfo->storage = ArgInIReg;
199 ainfo->reg = param_regs [*gr];
205 add_general_pair (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
207 ainfo->offset = *stack_size;
209 g_assert (PARAM_REGS == 0);
211 ainfo->storage = ArgOnStack;
212 (*stack_size) += sizeof (gpointer) * 2;
216 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
218 ainfo->offset = *stack_size;
220 if (*gr >= FLOAT_PARAM_REGS) {
221 ainfo->storage = ArgOnStack;
222 (*stack_size) += is_double ? 8 : 4;
225 /* A double register */
227 ainfo->storage = ArgInDoubleSSEReg;
229 ainfo->storage = ArgInFloatSSEReg;
237 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
239 guint32 *gr, guint32 *fr, guint32 *stack_size)
244 klass = mono_class_from_mono_type (type);
245 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
247 #ifdef SMALL_STRUCTS_IN_REGS
248 if (sig->pinvoke && is_return) {
249 MonoMarshalType *info;
252 * the exact rules are not very well documented, the code below seems to work with the
253 * code generated by gcc 3.3.3 -mno-cygwin.
255 info = mono_marshal_load_type_info (klass);
258 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
260 /* Special case structs with only a float member */
261 if ((info->native_size == 8) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R8)) {
262 ainfo->storage = ArgValuetypeInReg;
263 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
266 if ((info->native_size == 4) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R4)) {
267 ainfo->storage = ArgValuetypeInReg;
268 ainfo->pair_storage [0] = ArgOnFloatFpStack;
271 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
272 ainfo->storage = ArgValuetypeInReg;
273 ainfo->pair_storage [0] = ArgInIReg;
274 ainfo->pair_regs [0] = return_regs [0];
275 if (info->native_size > 4) {
276 ainfo->pair_storage [1] = ArgInIReg;
277 ainfo->pair_regs [1] = return_regs [1];
284 ainfo->offset = *stack_size;
285 ainfo->storage = ArgOnStack;
286 *stack_size += ALIGN_TO (size, sizeof (gpointer));
292 * Obtain information about a call according to the calling convention.
293 * For x86 ELF, see the "System V Application Binary Interface Intel386
294 * Architecture Processor Supplment, Fourth Edition" document for more
296 * For x86 win32, see ???.
299 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
303 int n = sig->hasthis + sig->param_count;
304 guint32 stack_size = 0;
308 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
310 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
317 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
318 switch (ret_type->type) {
319 case MONO_TYPE_BOOLEAN:
330 case MONO_TYPE_FNPTR:
331 case MONO_TYPE_CLASS:
332 case MONO_TYPE_OBJECT:
333 case MONO_TYPE_SZARRAY:
334 case MONO_TYPE_ARRAY:
335 case MONO_TYPE_STRING:
336 cinfo->ret.storage = ArgInIReg;
337 cinfo->ret.reg = X86_EAX;
341 cinfo->ret.storage = ArgInIReg;
342 cinfo->ret.reg = X86_EAX;
345 cinfo->ret.storage = ArgOnFloatFpStack;
348 cinfo->ret.storage = ArgOnDoubleFpStack;
350 case MONO_TYPE_GENERICINST:
351 if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
352 cinfo->ret.storage = ArgInIReg;
353 cinfo->ret.reg = X86_EAX;
357 case MONO_TYPE_VALUETYPE: {
358 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
360 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
361 if (cinfo->ret.storage == ArgOnStack)
362 /* The caller passes the address where the value is stored */
363 add_general (&gr, &stack_size, &cinfo->ret);
366 case MONO_TYPE_TYPEDBYREF:
367 /* Same as a valuetype with size 24 */
368 add_general (&gr, &stack_size, &cinfo->ret);
372 cinfo->ret.storage = ArgNone;
375 g_error ("Can't handle as return value 0x%x", sig->ret->type);
381 add_general (&gr, &stack_size, cinfo->args + 0);
383 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
385 fr = FLOAT_PARAM_REGS;
387 /* Emit the signature cookie just before the implicit arguments */
388 add_general (&gr, &stack_size, &cinfo->sig_cookie);
391 for (i = 0; i < sig->param_count; ++i) {
392 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
395 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
396 /* We allways pass the sig cookie on the stack for simplicity */
398 * Prevent implicit arguments + the sig cookie from being passed
402 fr = FLOAT_PARAM_REGS;
404 /* Emit the signature cookie just before the implicit arguments */
405 add_general (&gr, &stack_size, &cinfo->sig_cookie);
408 if (sig->params [i]->byref) {
409 add_general (&gr, &stack_size, ainfo);
412 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
413 switch (ptype->type) {
414 case MONO_TYPE_BOOLEAN:
417 add_general (&gr, &stack_size, ainfo);
422 add_general (&gr, &stack_size, ainfo);
426 add_general (&gr, &stack_size, ainfo);
431 case MONO_TYPE_FNPTR:
432 case MONO_TYPE_CLASS:
433 case MONO_TYPE_OBJECT:
434 case MONO_TYPE_STRING:
435 case MONO_TYPE_SZARRAY:
436 case MONO_TYPE_ARRAY:
437 add_general (&gr, &stack_size, ainfo);
439 case MONO_TYPE_GENERICINST:
440 if (!mono_type_generic_inst_is_valuetype (sig->params [i])) {
441 add_general (&gr, &stack_size, ainfo);
445 case MONO_TYPE_VALUETYPE:
446 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
448 case MONO_TYPE_TYPEDBYREF:
449 stack_size += sizeof (MonoTypedRef);
450 ainfo->storage = ArgOnStack;
454 add_general_pair (&gr, &stack_size, ainfo);
457 add_float (&fr, &stack_size, ainfo, FALSE);
460 add_float (&fr, &stack_size, ainfo, TRUE);
463 g_error ("unexpected type 0x%x", ptype->type);
464 g_assert_not_reached ();
468 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
470 fr = FLOAT_PARAM_REGS;
472 /* Emit the signature cookie just before the implicit arguments */
473 add_general (&gr, &stack_size, &cinfo->sig_cookie);
476 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
477 cinfo->need_stack_align = TRUE;
478 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
479 stack_size += cinfo->stack_align_amount;
482 cinfo->stack_usage = stack_size;
483 cinfo->reg_usage = gr;
484 cinfo->freg_usage = fr;
489 * mono_arch_get_argument_info:
490 * @csig: a method signature
491 * @param_count: the number of parameters to consider
492 * @arg_info: an array to store the result infos
494 * Gathers information on parameters such as size, alignment and
495 * padding. arg_info should be large enought to hold param_count + 1 entries.
497 * Returns the size of the argument area on the stack.
500 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
502 int k, args_size = 0;
508 cinfo = get_call_info (NULL, NULL, csig, FALSE);
510 if (MONO_TYPE_ISSTRUCT (csig->ret) && (cinfo->ret.storage == ArgOnStack)) {
511 args_size += sizeof (gpointer);
515 arg_info [0].offset = offset;
518 args_size += sizeof (gpointer);
522 arg_info [0].size = args_size;
524 for (k = 0; k < param_count; k++) {
525 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
527 /* ignore alignment for now */
530 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
531 arg_info [k].pad = pad;
533 arg_info [k + 1].pad = 0;
534 arg_info [k + 1].size = size;
536 arg_info [k + 1].offset = offset;
540 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
541 align = MONO_ARCH_FRAME_ALIGNMENT;
544 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
545 arg_info [k].pad = pad;
552 static const guchar cpuid_impl [] = {
553 0x55, /* push %ebp */
554 0x89, 0xe5, /* mov %esp,%ebp */
555 0x53, /* push %ebx */
556 0x8b, 0x45, 0x08, /* mov 0x8(%ebp),%eax */
557 0x0f, 0xa2, /* cpuid */
558 0x50, /* push %eax */
559 0x8b, 0x45, 0x10, /* mov 0x10(%ebp),%eax */
560 0x89, 0x18, /* mov %ebx,(%eax) */
561 0x8b, 0x45, 0x14, /* mov 0x14(%ebp),%eax */
562 0x89, 0x08, /* mov %ecx,(%eax) */
563 0x8b, 0x45, 0x18, /* mov 0x18(%ebp),%eax */
564 0x89, 0x10, /* mov %edx,(%eax) */
566 0x8b, 0x55, 0x0c, /* mov 0xc(%ebp),%edx */
567 0x89, 0x02, /* mov %eax,(%edx) */
573 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
576 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
580 __asm__ __volatile__ (
583 "movl %%eax, %%edx\n"
584 "xorl $0x200000, %%eax\n"
589 "xorl %%edx, %%eax\n"
590 "andl $0x200000, %%eax\n"
612 /* Have to use the code manager to get around WinXP DEP */
613 static CpuidFunc func = NULL;
616 ptr = mono_global_codeman_reserve (sizeof (cpuid_impl));
617 memcpy (ptr, cpuid_impl, sizeof (cpuid_impl));
618 func = (CpuidFunc)ptr;
620 func (id, p_eax, p_ebx, p_ecx, p_edx);
623 * We use this approach because of issues with gcc and pic code, see:
624 * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
625 __asm__ __volatile__ ("cpuid"
626 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
635 * Initialize the cpu to execute managed code.
638 mono_arch_cpu_init (void)
640 /* spec compliance requires running with double precision */
644 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
645 fpcw &= ~X86_FPCW_PRECC_MASK;
646 fpcw |= X86_FPCW_PREC_DOUBLE;
647 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
648 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
650 _control87 (_PC_53, MCW_PC);
655 * Initialize architecture specific code.
658 mono_arch_init (void)
660 InitializeCriticalSection (&mini_arch_mutex);
662 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
663 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
664 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
668 * Cleanup architecture specific code.
671 mono_arch_cleanup (void)
673 DeleteCriticalSection (&mini_arch_mutex);
677 * This function returns the optimizations supported on this cpu.
680 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
682 int eax, ebx, ecx, edx;
686 /* Feature Flags function, flags returned in EDX. */
687 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
688 if (edx & (1 << 15)) {
689 opts |= MONO_OPT_CMOV;
691 opts |= MONO_OPT_FCMOV;
693 *exclude_mask |= MONO_OPT_FCMOV;
695 *exclude_mask |= MONO_OPT_CMOV;
697 opts |= MONO_OPT_SSE2;
699 *exclude_mask |= MONO_OPT_SSE2;
701 #ifdef MONO_ARCH_SIMD_INTRINSICS
702 /*SIMD intrinsics require at least SSE2.*/
703 if (!(opts & MONO_OPT_SSE2))
704 *exclude_mask |= MONO_OPT_SIMD;
711 * This function test for all SSE functions supported.
713 * Returns a bitmask corresponding to all supported versions.
717 mono_arch_cpu_enumerate_simd_versions (void)
719 int eax, ebx, ecx, edx;
720 guint32 sse_opts = 0;
722 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
724 sse_opts |= 1 << SIMD_VERSION_SSE1;
726 sse_opts |= 1 << SIMD_VERSION_SSE2;
728 sse_opts |= 1 << SIMD_VERSION_SSE3;
730 sse_opts |= 1 << SIMD_VERSION_SSSE3;
732 sse_opts |= 1 << SIMD_VERSION_SSE41;
734 sse_opts |= 1 << SIMD_VERSION_SSE42;
737 /* Yes, all this needs to be done to check for sse4a.
738 See: "Amd: CPUID Specification"
740 if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
741 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
742 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
743 cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
745 sse_opts |= 1 << SIMD_VERSION_SSE4a;
754 * Determine whenever the trap whose info is in SIGINFO is caused by
758 mono_arch_is_int_overflow (void *sigctx, void *info)
763 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
765 ip = (guint8*)ctx.eip;
767 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
771 switch (x86_modrm_rm (ip [1])) {
791 g_assert_not_reached ();
803 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
808 for (i = 0; i < cfg->num_varinfo; i++) {
809 MonoInst *ins = cfg->varinfo [i];
810 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
813 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
816 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
817 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
820 /* we dont allocate I1 to registers because there is no simply way to sign extend
821 * 8bit quantities in caller saved registers on x86 */
822 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
823 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
824 g_assert (i == vmv->idx);
825 vars = g_list_prepend (vars, vmv);
829 vars = mono_varlist_sort (cfg, vars, 0);
835 mono_arch_get_global_int_regs (MonoCompile *cfg)
839 /* we can use 3 registers for global allocation */
840 regs = g_list_prepend (regs, (gpointer)X86_EBX);
841 regs = g_list_prepend (regs, (gpointer)X86_ESI);
842 regs = g_list_prepend (regs, (gpointer)X86_EDI);
848 * mono_arch_regalloc_cost:
850 * Return the cost, in number of memory references, of the action of
851 * allocating the variable VMV into a register during global register
855 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
857 MonoInst *ins = cfg->varinfo [vmv->idx];
859 if (cfg->method->save_lmf)
860 /* The register is already saved */
861 return (ins->opcode == OP_ARG) ? 1 : 0;
863 /* push+pop+possible load if it is an argument */
864 return (ins->opcode == OP_ARG) ? 3 : 2;
868 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
870 static int inited = FALSE;
871 static int count = 0;
873 if (cfg->arch.need_stack_frame_inited) {
874 g_assert (cfg->arch.need_stack_frame == flag);
878 cfg->arch.need_stack_frame = flag;
879 cfg->arch.need_stack_frame_inited = TRUE;
885 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
890 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
894 needs_stack_frame (MonoCompile *cfg)
896 MonoMethodSignature *sig;
897 MonoMethodHeader *header;
898 gboolean result = FALSE;
900 #if defined(__APPLE__)
901 /*OSX requires stack frame code to have the correct alignment. */
905 if (cfg->arch.need_stack_frame_inited)
906 return cfg->arch.need_stack_frame;
908 header = mono_method_get_header (cfg->method);
909 sig = mono_method_signature (cfg->method);
911 if (cfg->disable_omit_fp)
913 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
915 else if (cfg->method->save_lmf)
917 else if (cfg->stack_offset)
919 else if (cfg->param_area)
921 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
923 else if (header->num_clauses)
925 else if (sig->param_count + sig->hasthis)
927 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
929 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
930 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
933 set_needs_stack_frame (cfg, result);
935 return cfg->arch.need_stack_frame;
939 * Set var information according to the calling convention. X86 version.
940 * The locals var stuff should most likely be split in another method.
943 mono_arch_allocate_vars (MonoCompile *cfg)
945 MonoMethodSignature *sig;
946 MonoMethodHeader *header;
948 guint32 locals_stack_size, locals_stack_align;
953 header = mono_method_get_header (cfg->method);
954 sig = mono_method_signature (cfg->method);
956 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
958 cfg->frame_reg = X86_EBP;
961 /* Reserve space to save LMF and caller saved registers */
963 if (cfg->method->save_lmf) {
964 offset += sizeof (MonoLMF);
966 if (cfg->used_int_regs & (1 << X86_EBX)) {
970 if (cfg->used_int_regs & (1 << X86_EDI)) {
974 if (cfg->used_int_regs & (1 << X86_ESI)) {
979 switch (cinfo->ret.storage) {
980 case ArgValuetypeInReg:
981 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
983 cfg->ret->opcode = OP_REGOFFSET;
984 cfg->ret->inst_basereg = X86_EBP;
985 cfg->ret->inst_offset = - offset;
991 /* Allocate locals */
992 offsets = mono_allocate_stack_slots (cfg, &locals_stack_size, &locals_stack_align);
993 if (locals_stack_align) {
994 offset += (locals_stack_align - 1);
995 offset &= ~(locals_stack_align - 1);
998 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
999 * have locals larger than 8 bytes we need to make sure that
1000 * they have the appropriate offset.
1002 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1003 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1004 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1005 if (offsets [i] != -1) {
1006 MonoInst *inst = cfg->varinfo [i];
1007 inst->opcode = OP_REGOFFSET;
1008 inst->inst_basereg = X86_EBP;
1009 inst->inst_offset = - (offset + offsets [i]);
1010 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1013 offset += locals_stack_size;
1017 * Allocate arguments+return value
1020 switch (cinfo->ret.storage) {
1022 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1024 * In the new IR, the cfg->vret_addr variable represents the
1025 * vtype return value.
1027 cfg->vret_addr->opcode = OP_REGOFFSET;
1028 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1029 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1030 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1031 printf ("vret_addr =");
1032 mono_print_ins (cfg->vret_addr);
1035 cfg->ret->opcode = OP_REGOFFSET;
1036 cfg->ret->inst_basereg = X86_EBP;
1037 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1040 case ArgValuetypeInReg:
1043 cfg->ret->opcode = OP_REGVAR;
1044 cfg->ret->inst_c0 = cinfo->ret.reg;
1045 cfg->ret->dreg = cinfo->ret.reg;
1048 case ArgOnFloatFpStack:
1049 case ArgOnDoubleFpStack:
1052 g_assert_not_reached ();
1055 if (sig->call_convention == MONO_CALL_VARARG) {
1056 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1057 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1060 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1061 ArgInfo *ainfo = &cinfo->args [i];
1062 inst = cfg->args [i];
1063 if (inst->opcode != OP_REGVAR) {
1064 inst->opcode = OP_REGOFFSET;
1065 inst->inst_basereg = X86_EBP;
1067 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1070 cfg->stack_offset = offset;
1074 mono_arch_create_vars (MonoCompile *cfg)
1076 MonoMethodSignature *sig;
1079 sig = mono_method_signature (cfg->method);
1081 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1083 if (cinfo->ret.storage == ArgValuetypeInReg)
1084 cfg->ret_var_is_local = TRUE;
1085 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1086 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1091 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1092 * so we try to do it just once when we have multiple fp arguments in a row.
1093 * We don't use this mechanism generally because for int arguments the generated code
1094 * is slightly bigger and new generation cpus optimize away the dependency chains
1095 * created by push instructions on the esp value.
1096 * fp_arg_setup is the first argument in the execution sequence where the esp register
1099 static G_GNUC_UNUSED int
1100 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1105 for (; start_arg < sig->param_count; ++start_arg) {
1106 t = mini_type_get_underlying_type (NULL, sig->params [start_arg]);
1107 if (!t->byref && t->type == MONO_TYPE_R8) {
1108 fp_space += sizeof (double);
1109 *fp_arg_setup = start_arg;
1118 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1120 MonoMethodSignature *tmp_sig;
1122 /* FIXME: Add support for signature tokens to AOT */
1123 cfg->disable_aot = TRUE;
1126 * mono_ArgIterator_Setup assumes the signature cookie is
1127 * passed first and all the arguments which were before it are
1128 * passed on the stack after the signature. So compensate by
1129 * passing a different signature.
1131 tmp_sig = mono_metadata_signature_dup (call->signature);
1132 tmp_sig->param_count -= call->signature->sentinelpos;
1133 tmp_sig->sentinelpos = 0;
1134 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1136 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1141 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1147 LLVMCallInfo *linfo;
1149 n = sig->param_count + sig->hasthis;
1151 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1153 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1156 * LLVM always uses the native ABI while we use our own ABI, the
1157 * only difference is the handling of vtypes:
1158 * - we only pass/receive them in registers in some cases, and only
1159 * in 1 or 2 integer registers.
1161 if (cinfo->ret.storage == ArgValuetypeInReg) {
1163 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1164 cfg->disable_llvm = TRUE;
1168 cfg->exception_message = g_strdup ("vtype ret in call");
1169 cfg->disable_llvm = TRUE;
1171 linfo->ret.storage = LLVMArgVtypeInReg;
1172 for (j = 0; j < 2; ++j)
1173 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1177 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1178 /* Vtype returned using a hidden argument */
1179 linfo->ret.storage = LLVMArgVtypeRetAddr;
1182 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != ArgInIReg) {
1184 cfg->exception_message = g_strdup ("vtype ret in call");
1185 cfg->disable_llvm = TRUE;
1188 for (i = 0; i < n; ++i) {
1189 ainfo = cinfo->args + i;
1191 linfo->args [i].storage = LLVMArgNone;
1193 switch (ainfo->storage) {
1195 linfo->args [i].storage = LLVMArgInIReg;
1197 case ArgInDoubleSSEReg:
1198 case ArgInFloatSSEReg:
1199 linfo->args [i].storage = LLVMArgInFPReg;
1202 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1203 linfo->args [i].storage = LLVMArgVtypeByVal;
1205 linfo->args [i].storage = LLVMArgInIReg;
1206 if (!sig->params [i - sig->hasthis]->byref) {
1207 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1208 linfo->args [i].storage = LLVMArgInFPReg;
1209 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1210 linfo->args [i].storage = LLVMArgInFPReg;
1215 case ArgValuetypeInReg:
1217 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1218 cfg->disable_llvm = TRUE;
1222 cfg->exception_message = g_strdup ("vtype arg");
1223 cfg->disable_llvm = TRUE;
1225 linfo->args [i].storage = LLVMArgVtypeInReg;
1226 for (j = 0; j < 2; ++j)
1227 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1231 cfg->exception_message = g_strdup ("ainfo->storage");
1232 cfg->disable_llvm = TRUE;
1242 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1245 MonoMethodSignature *sig;
1248 int sentinelpos = 0;
1250 sig = call->signature;
1251 n = sig->param_count + sig->hasthis;
1253 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1255 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1256 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1258 if (cinfo->need_stack_align) {
1259 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1260 arg->dreg = X86_ESP;
1261 arg->sreg1 = X86_ESP;
1262 arg->inst_imm = cinfo->stack_align_amount;
1263 MONO_ADD_INS (cfg->cbb, arg);
1266 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1267 if (cinfo->ret.storage == ArgValuetypeInReg) {
1269 * Tell the JIT to use a more efficient calling convention: call using
1270 * OP_CALL, compute the result location after the call, and save the
1273 call->vret_in_reg = TRUE;
1275 NULLIFY_INS (call->vret_var);
1279 /* Handle the case where there are no implicit arguments */
1280 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1281 emit_sig_cookie (cfg, call, cinfo);
1284 /* Arguments are pushed in the reverse order */
1285 for (i = n - 1; i >= 0; i --) {
1286 ArgInfo *ainfo = cinfo->args + i;
1289 if (i >= sig->hasthis)
1290 t = sig->params [i - sig->hasthis];
1292 t = &mono_defaults.int_class->byval_arg;
1293 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1295 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1297 in = call->args [i];
1298 arg->cil_code = in->cil_code;
1299 arg->sreg1 = in->dreg;
1300 arg->type = in->type;
1302 g_assert (in->dreg != -1);
1304 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1308 g_assert (in->klass);
1310 if (t->type == MONO_TYPE_TYPEDBYREF) {
1311 size = sizeof (MonoTypedRef);
1312 align = sizeof (gpointer);
1315 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1319 arg->opcode = OP_OUTARG_VT;
1320 arg->sreg1 = in->dreg;
1321 arg->klass = in->klass;
1322 arg->backend.size = size;
1324 MONO_ADD_INS (cfg->cbb, arg);
1328 switch (ainfo->storage) {
1330 arg->opcode = OP_X86_PUSH;
1332 if (t->type == MONO_TYPE_R4) {
1333 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1334 arg->opcode = OP_STORER4_MEMBASE_REG;
1335 arg->inst_destbasereg = X86_ESP;
1336 arg->inst_offset = 0;
1337 } else if (t->type == MONO_TYPE_R8) {
1338 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1339 arg->opcode = OP_STORER8_MEMBASE_REG;
1340 arg->inst_destbasereg = X86_ESP;
1341 arg->inst_offset = 0;
1342 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1344 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1349 g_assert_not_reached ();
1352 MONO_ADD_INS (cfg->cbb, arg);
1355 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1356 /* Emit the signature cookie just before the implicit arguments */
1357 emit_sig_cookie (cfg, call, cinfo);
1361 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1364 if (cinfo->ret.storage == ArgValuetypeInReg) {
1367 else if (cinfo->ret.storage == ArgInIReg) {
1369 /* The return address is passed in a register */
1370 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1371 vtarg->sreg1 = call->inst.dreg;
1372 vtarg->dreg = mono_alloc_ireg (cfg);
1373 MONO_ADD_INS (cfg->cbb, vtarg);
1375 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1378 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1379 vtarg->type = STACK_MP;
1380 vtarg->sreg1 = call->vret_var->dreg;
1381 MONO_ADD_INS (cfg->cbb, vtarg);
1384 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1385 if (cinfo->ret.storage != ArgValuetypeInReg)
1386 cinfo->stack_usage -= 4;
1389 call->stack_usage = cinfo->stack_usage;
1393 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1396 int size = ins->backend.size;
1399 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1400 arg->sreg1 = src->dreg;
1402 MONO_ADD_INS (cfg->cbb, arg);
1403 } else if (size <= 20) {
1404 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1405 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1407 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1408 arg->inst_basereg = src->dreg;
1409 arg->inst_offset = 0;
1410 arg->inst_imm = size;
1412 MONO_ADD_INS (cfg->cbb, arg);
1417 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1419 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1422 if (ret->type == MONO_TYPE_R4) {
1423 if (COMPILE_LLVM (cfg))
1424 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1427 } else if (ret->type == MONO_TYPE_R8) {
1428 if (COMPILE_LLVM (cfg))
1429 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1432 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1433 if (COMPILE_LLVM (cfg))
1434 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1436 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1437 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1443 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1447 * Allow tracing to work with this interface (with an optional argument)
1450 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1454 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1455 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1457 /* if some args are passed in registers, we need to save them here */
1458 x86_push_reg (code, X86_EBP);
1460 if (cfg->compile_aot) {
1461 x86_push_imm (code, cfg->method);
1462 x86_mov_reg_imm (code, X86_EAX, func);
1463 x86_call_reg (code, X86_EAX);
1465 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1466 x86_push_imm (code, cfg->method);
1467 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1468 x86_call_code (code, 0);
1470 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1484 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1487 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1488 MonoMethod *method = cfg->method;
1490 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret)->type) {
1491 case MONO_TYPE_VOID:
1492 /* special case string .ctor icall */
1493 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1494 save_mode = SAVE_EAX;
1495 stack_usage = enable_arguments ? 8 : 4;
1497 save_mode = SAVE_NONE;
1501 save_mode = SAVE_EAX_EDX;
1502 stack_usage = enable_arguments ? 16 : 8;
1506 save_mode = SAVE_FP;
1507 stack_usage = enable_arguments ? 16 : 8;
1509 case MONO_TYPE_GENERICINST:
1510 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
1511 save_mode = SAVE_EAX;
1512 stack_usage = enable_arguments ? 8 : 4;
1516 case MONO_TYPE_VALUETYPE:
1517 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1518 save_mode = SAVE_STRUCT;
1519 stack_usage = enable_arguments ? 4 : 0;
1522 save_mode = SAVE_EAX;
1523 stack_usage = enable_arguments ? 8 : 4;
1527 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1529 switch (save_mode) {
1531 x86_push_reg (code, X86_EDX);
1532 x86_push_reg (code, X86_EAX);
1533 if (enable_arguments) {
1534 x86_push_reg (code, X86_EDX);
1535 x86_push_reg (code, X86_EAX);
1540 x86_push_reg (code, X86_EAX);
1541 if (enable_arguments) {
1542 x86_push_reg (code, X86_EAX);
1547 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1548 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1549 if (enable_arguments) {
1550 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1551 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1556 if (enable_arguments) {
1557 x86_push_membase (code, X86_EBP, 8);
1566 if (cfg->compile_aot) {
1567 x86_push_imm (code, method);
1568 x86_mov_reg_imm (code, X86_EAX, func);
1569 x86_call_reg (code, X86_EAX);
1571 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1572 x86_push_imm (code, method);
1573 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1574 x86_call_code (code, 0);
1577 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1579 switch (save_mode) {
1581 x86_pop_reg (code, X86_EAX);
1582 x86_pop_reg (code, X86_EDX);
1585 x86_pop_reg (code, X86_EAX);
1588 x86_fld_membase (code, X86_ESP, 0, TRUE);
1589 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1596 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1601 #define EMIT_COND_BRANCH(ins,cond,sign) \
1602 if (ins->inst_true_bb->native_offset) { \
1603 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1605 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1606 if ((cfg->opt & MONO_OPT_BRANCH) && \
1607 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1608 x86_branch8 (code, cond, 0, sign); \
1610 x86_branch32 (code, cond, 0, sign); \
1614 * Emit an exception if condition is fail and
1615 * if possible do a directly branch to target
1617 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1619 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1620 if (tins == NULL) { \
1621 mono_add_patch_info (cfg, code - cfg->native_code, \
1622 MONO_PATCH_INFO_EXC, exc_name); \
1623 x86_branch32 (code, cond, 0, signed); \
1625 EMIT_COND_BRANCH (tins, cond, signed); \
1629 #define EMIT_FPCOMPARE(code) do { \
1630 x86_fcompp (code); \
1631 x86_fnstsw (code); \
1636 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1638 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1639 x86_call_code (code, 0);
1644 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1647 * mono_peephole_pass_1:
1649 * Perform peephole opts which should/can be performed before local regalloc
1652 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1656 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1657 MonoInst *last_ins = ins->prev;
1659 switch (ins->opcode) {
1662 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1664 * X86_LEA is like ADD, but doesn't have the
1665 * sreg1==dreg restriction.
1667 ins->opcode = OP_X86_LEA_MEMBASE;
1668 ins->inst_basereg = ins->sreg1;
1669 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1670 ins->opcode = OP_X86_INC_REG;
1674 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1675 ins->opcode = OP_X86_LEA_MEMBASE;
1676 ins->inst_basereg = ins->sreg1;
1677 ins->inst_imm = -ins->inst_imm;
1678 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1679 ins->opcode = OP_X86_DEC_REG;
1681 case OP_COMPARE_IMM:
1682 case OP_ICOMPARE_IMM:
1683 /* OP_COMPARE_IMM (reg, 0)
1685 * OP_X86_TEST_NULL (reg)
1688 ins->opcode = OP_X86_TEST_NULL;
1690 case OP_X86_COMPARE_MEMBASE_IMM:
1692 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1693 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1695 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1696 * OP_COMPARE_IMM reg, imm
1698 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1700 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1701 ins->inst_basereg == last_ins->inst_destbasereg &&
1702 ins->inst_offset == last_ins->inst_offset) {
1703 ins->opcode = OP_COMPARE_IMM;
1704 ins->sreg1 = last_ins->sreg1;
1706 /* check if we can remove cmp reg,0 with test null */
1708 ins->opcode = OP_X86_TEST_NULL;
1712 case OP_X86_PUSH_MEMBASE:
1713 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1714 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1715 ins->inst_basereg == last_ins->inst_destbasereg &&
1716 ins->inst_offset == last_ins->inst_offset) {
1717 ins->opcode = OP_X86_PUSH;
1718 ins->sreg1 = last_ins->sreg1;
1723 mono_peephole_ins (bb, ins);
1728 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1732 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1733 switch (ins->opcode) {
1735 /* reg = 0 -> XOR (reg, reg) */
1736 /* XOR sets cflags on x86, so we cant do it always */
1737 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1740 ins->opcode = OP_IXOR;
1741 ins->sreg1 = ins->dreg;
1742 ins->sreg2 = ins->dreg;
1745 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1746 * since it takes 3 bytes instead of 7.
1748 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
1749 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1750 ins2->opcode = OP_STORE_MEMBASE_REG;
1751 ins2->sreg1 = ins->dreg;
1753 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1754 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1755 ins2->sreg1 = ins->dreg;
1757 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1758 /* Continue iteration */
1767 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1768 ins->opcode = OP_X86_INC_REG;
1772 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1773 ins->opcode = OP_X86_DEC_REG;
1777 mono_peephole_ins (bb, ins);
1782 * mono_arch_lowering_pass:
1784 * Converts complex opcodes into simpler ones so that each IR instruction
1785 * corresponds to one machine instruction.
1788 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1790 MonoInst *ins, *next;
1793 * FIXME: Need to add more instructions, but the current machine
1794 * description can't model some parts of the composite instructions like
1797 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
1798 switch (ins->opcode) {
1801 case OP_IDIV_UN_IMM:
1802 case OP_IREM_UN_IMM:
1804 * Keep the cases where we could generated optimized code, otherwise convert
1805 * to the non-imm variant.
1807 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
1809 mono_decompose_op_imm (cfg, bb, ins);
1816 bb->max_vreg = cfg->next_vreg;
1820 branch_cc_table [] = {
1821 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1822 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1823 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1826 /* Maps CMP_... constants to X86_CC_... constants */
1829 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
1830 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
1834 cc_signed_table [] = {
1835 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
1836 FALSE, FALSE, FALSE, FALSE
1839 static unsigned char*
1840 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
1842 #define XMM_TEMP_REG 0
1843 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
1844 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
1845 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
1846 /* optimize by assigning a local var for this use so we avoid
1847 * the stack manipulations */
1848 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1849 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1850 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
1851 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
1852 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1854 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
1856 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
1859 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
1860 x86_fnstcw_membase(code, X86_ESP, 0);
1861 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
1862 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
1863 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
1864 x86_fldcw_membase (code, X86_ESP, 2);
1866 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1867 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
1868 x86_pop_reg (code, dreg);
1869 /* FIXME: need the high register
1870 * x86_pop_reg (code, dreg_high);
1873 x86_push_reg (code, X86_EAX); // SP = SP - 4
1874 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
1875 x86_pop_reg (code, dreg);
1877 x86_fldcw_membase (code, X86_ESP, 0);
1878 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
1881 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
1883 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
1887 static unsigned char*
1888 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
1890 int sreg = tree->sreg1;
1891 int need_touch = FALSE;
1893 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
1902 * If requested stack size is larger than one page,
1903 * perform stack-touch operation
1906 * Generate stack probe code.
1907 * Under Windows, it is necessary to allocate one page at a time,
1908 * "touching" stack after each successful sub-allocation. This is
1909 * because of the way stack growth is implemented - there is a
1910 * guard page before the lowest stack page that is currently commited.
1911 * Stack normally grows sequentially so OS traps access to the
1912 * guard page and commits more pages when needed.
1914 x86_test_reg_imm (code, sreg, ~0xFFF);
1915 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1917 br[2] = code; /* loop */
1918 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
1919 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
1922 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
1923 * that follows only initializes the last part of the area.
1925 /* Same as the init code below with size==0x1000 */
1926 if (tree->flags & MONO_INST_INIT) {
1927 x86_push_reg (code, X86_EAX);
1928 x86_push_reg (code, X86_ECX);
1929 x86_push_reg (code, X86_EDI);
1930 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
1931 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
1932 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
1934 x86_prefix (code, X86_REP_PREFIX);
1936 x86_pop_reg (code, X86_EDI);
1937 x86_pop_reg (code, X86_ECX);
1938 x86_pop_reg (code, X86_EAX);
1941 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
1942 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
1943 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
1944 x86_patch (br[3], br[2]);
1945 x86_test_reg_reg (code, sreg, sreg);
1946 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1947 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
1949 br[1] = code; x86_jump8 (code, 0);
1951 x86_patch (br[0], code);
1952 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
1953 x86_patch (br[1], code);
1954 x86_patch (br[4], code);
1957 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
1959 if (tree->flags & MONO_INST_INIT) {
1961 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
1962 x86_push_reg (code, X86_EAX);
1965 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
1966 x86_push_reg (code, X86_ECX);
1969 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
1970 x86_push_reg (code, X86_EDI);
1974 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
1975 if (sreg != X86_ECX)
1976 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
1977 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
1979 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
1981 x86_prefix (code, X86_REP_PREFIX);
1984 if (tree->dreg != X86_EDI && sreg != X86_EDI)
1985 x86_pop_reg (code, X86_EDI);
1986 if (tree->dreg != X86_ECX && sreg != X86_ECX)
1987 x86_pop_reg (code, X86_ECX);
1988 if (tree->dreg != X86_EAX && sreg != X86_EAX)
1989 x86_pop_reg (code, X86_EAX);
1996 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
1998 /* Move return value to the target register */
1999 switch (ins->opcode) {
2002 case OP_CALL_MEMBASE:
2003 if (ins->dreg != X86_EAX)
2004 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2014 * mono_x86_emit_tls_get:
2015 * @code: buffer to store code to
2016 * @dreg: hard register where to place the result
2017 * @tls_offset: offset info
2019 * mono_x86_emit_tls_get emits in @code the native code that puts in
2020 * the dreg register the item in the thread local storage identified
2023 * Returns: a pointer to the end of the stored code
2026 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2028 #ifdef PLATFORM_WIN32
2030 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2031 * Journal and/or a disassembly of the TlsGet () function.
2033 g_assert (tls_offset < 64);
2034 x86_prefix (code, X86_FS_PREFIX);
2035 x86_mov_reg_mem (code, dreg, 0x18, 4);
2036 /* Dunno what this does but TlsGetValue () contains it */
2037 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2038 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2040 if (optimize_for_xen) {
2041 x86_prefix (code, X86_GS_PREFIX);
2042 x86_mov_reg_mem (code, dreg, 0, 4);
2043 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2045 x86_prefix (code, X86_GS_PREFIX);
2046 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2053 * emit_load_volatile_arguments:
2055 * Load volatile arguments from the stack to the original input registers.
2056 * Required before a tail call.
2059 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2061 MonoMethod *method = cfg->method;
2062 MonoMethodSignature *sig;
2067 /* FIXME: Generate intermediate code instead */
2069 sig = mono_method_signature (method);
2071 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
2073 /* This is the opposite of the code in emit_prolog */
2075 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2076 ArgInfo *ainfo = cinfo->args + i;
2078 inst = cfg->args [i];
2080 if (sig->hasthis && (i == 0))
2081 arg_type = &mono_defaults.object_class->byval_arg;
2083 arg_type = sig->params [i - sig->hasthis];
2086 * On x86, the arguments are either in their original stack locations, or in
2089 if (inst->opcode == OP_REGVAR) {
2090 g_assert (ainfo->storage == ArgOnStack);
2092 x86_mov_membase_reg (code, X86_EBP, inst->inst_offset, inst->dreg, 4);
2099 #define REAL_PRINT_REG(text,reg) \
2100 mono_assert (reg >= 0); \
2101 x86_push_reg (code, X86_EAX); \
2102 x86_push_reg (code, X86_EDX); \
2103 x86_push_reg (code, X86_ECX); \
2104 x86_push_reg (code, reg); \
2105 x86_push_imm (code, reg); \
2106 x86_push_imm (code, text " %d %p\n"); \
2107 x86_mov_reg_imm (code, X86_EAX, printf); \
2108 x86_call_reg (code, X86_EAX); \
2109 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2110 x86_pop_reg (code, X86_ECX); \
2111 x86_pop_reg (code, X86_EDX); \
2112 x86_pop_reg (code, X86_EAX);
2114 /* benchmark and set based on cpu */
2115 #define LOOP_ALIGNMENT 8
2116 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2121 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2126 guint8 *code = cfg->native_code + cfg->code_len;
2129 if (cfg->opt & MONO_OPT_LOOP) {
2130 int pad, align = LOOP_ALIGNMENT;
2131 /* set alignment depending on cpu */
2132 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2134 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2135 x86_padding (code, pad);
2136 cfg->code_len += pad;
2137 bb->native_offset = cfg->code_len;
2141 if (cfg->verbose_level > 2)
2142 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2144 cpos = bb->max_offset;
2146 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2147 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2148 g_assert (!cfg->compile_aot);
2151 cov->data [bb->dfn].cil_code = bb->cil_code;
2152 /* this is not thread save, but good enough */
2153 x86_inc_mem (code, &cov->data [bb->dfn].count);
2156 offset = code - cfg->native_code;
2158 mono_debug_open_block (cfg, bb, offset);
2160 MONO_BB_FOR_EACH_INS (bb, ins) {
2161 offset = code - cfg->native_code;
2163 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2165 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2166 cfg->code_size *= 2;
2167 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2168 code = cfg->native_code + offset;
2169 mono_jit_stats.code_reallocs++;
2172 if (cfg->debug_info)
2173 mono_debug_record_line_number (cfg, ins, offset);
2175 switch (ins->opcode) {
2177 x86_mul_reg (code, ins->sreg2, TRUE);
2180 x86_mul_reg (code, ins->sreg2, FALSE);
2182 case OP_X86_SETEQ_MEMBASE:
2183 case OP_X86_SETNE_MEMBASE:
2184 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2185 ins->inst_basereg, ins->inst_offset, TRUE);
2187 case OP_STOREI1_MEMBASE_IMM:
2188 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2190 case OP_STOREI2_MEMBASE_IMM:
2191 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2193 case OP_STORE_MEMBASE_IMM:
2194 case OP_STOREI4_MEMBASE_IMM:
2195 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2197 case OP_STOREI1_MEMBASE_REG:
2198 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2200 case OP_STOREI2_MEMBASE_REG:
2201 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2203 case OP_STORE_MEMBASE_REG:
2204 case OP_STOREI4_MEMBASE_REG:
2205 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2207 case OP_STORE_MEM_IMM:
2208 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2211 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2215 /* These are created by the cprop pass so they use inst_imm as the source */
2216 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2219 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2222 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2224 case OP_LOAD_MEMBASE:
2225 case OP_LOADI4_MEMBASE:
2226 case OP_LOADU4_MEMBASE:
2227 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2229 case OP_LOADU1_MEMBASE:
2230 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2232 case OP_LOADI1_MEMBASE:
2233 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2235 case OP_LOADU2_MEMBASE:
2236 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2238 case OP_LOADI2_MEMBASE:
2239 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2241 case OP_ICONV_TO_I1:
2243 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2245 case OP_ICONV_TO_I2:
2247 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2249 case OP_ICONV_TO_U1:
2250 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2252 case OP_ICONV_TO_U2:
2253 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2257 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2259 case OP_COMPARE_IMM:
2260 case OP_ICOMPARE_IMM:
2261 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2263 case OP_X86_COMPARE_MEMBASE_REG:
2264 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2266 case OP_X86_COMPARE_MEMBASE_IMM:
2267 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2269 case OP_X86_COMPARE_MEMBASE8_IMM:
2270 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2272 case OP_X86_COMPARE_REG_MEMBASE:
2273 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2275 case OP_X86_COMPARE_MEM_IMM:
2276 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2278 case OP_X86_TEST_NULL:
2279 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2281 case OP_X86_ADD_MEMBASE_IMM:
2282 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2284 case OP_X86_ADD_REG_MEMBASE:
2285 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2287 case OP_X86_SUB_MEMBASE_IMM:
2288 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2290 case OP_X86_SUB_REG_MEMBASE:
2291 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2293 case OP_X86_AND_MEMBASE_IMM:
2294 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2296 case OP_X86_OR_MEMBASE_IMM:
2297 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2299 case OP_X86_XOR_MEMBASE_IMM:
2300 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2302 case OP_X86_ADD_MEMBASE_REG:
2303 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2305 case OP_X86_SUB_MEMBASE_REG:
2306 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2308 case OP_X86_AND_MEMBASE_REG:
2309 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2311 case OP_X86_OR_MEMBASE_REG:
2312 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2314 case OP_X86_XOR_MEMBASE_REG:
2315 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2317 case OP_X86_INC_MEMBASE:
2318 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2320 case OP_X86_INC_REG:
2321 x86_inc_reg (code, ins->dreg);
2323 case OP_X86_DEC_MEMBASE:
2324 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2326 case OP_X86_DEC_REG:
2327 x86_dec_reg (code, ins->dreg);
2329 case OP_X86_MUL_REG_MEMBASE:
2330 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2332 case OP_X86_AND_REG_MEMBASE:
2333 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2335 case OP_X86_OR_REG_MEMBASE:
2336 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2338 case OP_X86_XOR_REG_MEMBASE:
2339 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2342 x86_breakpoint (code);
2344 case OP_RELAXED_NOP:
2345 x86_prefix (code, X86_REP_PREFIX);
2353 case OP_DUMMY_STORE:
2354 case OP_NOT_REACHED:
2357 case OP_SEQ_POINT: {
2360 if (cfg->compile_aot)
2364 * Read from the single stepping trigger page. This will cause a
2365 * SIGSEGV when single stepping is enabled.
2366 * We do this _before_ the breakpoint, so single stepping after
2367 * a breakpoint is hit will step to the next IL offset.
2369 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2370 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2372 il_offset = ins->inst_imm;
2374 if (!cfg->seq_points)
2375 cfg->seq_points = g_ptr_array_new ();
2376 g_ptr_array_add (cfg->seq_points, GUINT_TO_POINTER (il_offset));
2377 g_ptr_array_add (cfg->seq_points, GUINT_TO_POINTER (code - cfg->native_code));
2379 * A placeholder for a possible breakpoint inserted by
2380 * mono_arch_set_breakpoint ().
2382 for (i = 0; i < 6; ++i)
2389 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2393 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2398 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2402 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2407 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2411 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2416 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2420 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2423 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2427 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2432 * The code is the same for div/rem, the allocator will allocate dreg
2433 * to RAX/RDX as appropriate.
2435 if (ins->sreg2 == X86_EDX) {
2436 /* cdq clobbers this */
2437 x86_push_reg (code, ins->sreg2);
2439 x86_div_membase (code, X86_ESP, 0, TRUE);
2440 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2443 x86_div_reg (code, ins->sreg2, TRUE);
2448 if (ins->sreg2 == X86_EDX) {
2449 x86_push_reg (code, ins->sreg2);
2450 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2451 x86_div_membase (code, X86_ESP, 0, FALSE);
2452 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2454 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2455 x86_div_reg (code, ins->sreg2, FALSE);
2459 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2461 x86_div_reg (code, ins->sreg2, TRUE);
2464 int power = mono_is_power_of_two (ins->inst_imm);
2466 g_assert (ins->sreg1 == X86_EAX);
2467 g_assert (ins->dreg == X86_EAX);
2468 g_assert (power >= 0);
2471 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2473 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2475 * If the divident is >= 0, this does not nothing. If it is positive, it
2476 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2478 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2479 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2480 } else if (power == 0) {
2481 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2483 /* Based on gcc code */
2485 /* Add compensation for negative dividents */
2487 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2488 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2489 /* Compute remainder */
2490 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2491 /* Remove compensation */
2492 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2497 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2501 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2504 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2508 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2511 g_assert (ins->sreg2 == X86_ECX);
2512 x86_shift_reg (code, X86_SHL, ins->dreg);
2515 g_assert (ins->sreg2 == X86_ECX);
2516 x86_shift_reg (code, X86_SAR, ins->dreg);
2520 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2523 case OP_ISHR_UN_IMM:
2524 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2527 g_assert (ins->sreg2 == X86_ECX);
2528 x86_shift_reg (code, X86_SHR, ins->dreg);
2532 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2535 guint8 *jump_to_end;
2537 /* handle shifts below 32 bits */
2538 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2539 x86_shift_reg (code, X86_SHL, ins->sreg1);
2541 x86_test_reg_imm (code, X86_ECX, 32);
2542 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2544 /* handle shift over 32 bit */
2545 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2546 x86_clear_reg (code, ins->sreg1);
2548 x86_patch (jump_to_end, code);
2552 guint8 *jump_to_end;
2554 /* handle shifts below 32 bits */
2555 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2556 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2558 x86_test_reg_imm (code, X86_ECX, 32);
2559 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2561 /* handle shifts over 31 bits */
2562 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2563 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2565 x86_patch (jump_to_end, code);
2569 guint8 *jump_to_end;
2571 /* handle shifts below 32 bits */
2572 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2573 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2575 x86_test_reg_imm (code, X86_ECX, 32);
2576 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2578 /* handle shifts over 31 bits */
2579 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2580 x86_clear_reg (code, ins->backend.reg3);
2582 x86_patch (jump_to_end, code);
2586 if (ins->inst_imm >= 32) {
2587 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2588 x86_clear_reg (code, ins->sreg1);
2589 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2591 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2592 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2596 if (ins->inst_imm >= 32) {
2597 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2598 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2599 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2601 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2602 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2605 case OP_LSHR_UN_IMM:
2606 if (ins->inst_imm >= 32) {
2607 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2608 x86_clear_reg (code, ins->backend.reg3);
2609 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2611 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2612 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2616 x86_not_reg (code, ins->sreg1);
2619 x86_neg_reg (code, ins->sreg1);
2623 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2627 switch (ins->inst_imm) {
2631 if (ins->dreg != ins->sreg1)
2632 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2633 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2636 /* LEA r1, [r2 + r2*2] */
2637 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2640 /* LEA r1, [r2 + r2*4] */
2641 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2644 /* LEA r1, [r2 + r2*2] */
2646 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2647 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2650 /* LEA r1, [r2 + r2*8] */
2651 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2654 /* LEA r1, [r2 + r2*4] */
2656 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2657 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2660 /* LEA r1, [r2 + r2*2] */
2662 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2663 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2666 /* LEA r1, [r2 + r2*4] */
2667 /* LEA r1, [r1 + r1*4] */
2668 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2669 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2672 /* LEA r1, [r2 + r2*4] */
2674 /* LEA r1, [r1 + r1*4] */
2675 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2676 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2677 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2680 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2685 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2686 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2688 case OP_IMUL_OVF_UN: {
2689 /* the mul operation and the exception check should most likely be split */
2690 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2691 /*g_assert (ins->sreg2 == X86_EAX);
2692 g_assert (ins->dreg == X86_EAX);*/
2693 if (ins->sreg2 == X86_EAX) {
2694 non_eax_reg = ins->sreg1;
2695 } else if (ins->sreg1 == X86_EAX) {
2696 non_eax_reg = ins->sreg2;
2698 /* no need to save since we're going to store to it anyway */
2699 if (ins->dreg != X86_EAX) {
2701 x86_push_reg (code, X86_EAX);
2703 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
2704 non_eax_reg = ins->sreg2;
2706 if (ins->dreg == X86_EDX) {
2709 x86_push_reg (code, X86_EAX);
2711 } else if (ins->dreg != X86_EAX) {
2713 x86_push_reg (code, X86_EDX);
2715 x86_mul_reg (code, non_eax_reg, FALSE);
2716 /* save before the check since pop and mov don't change the flags */
2717 if (ins->dreg != X86_EAX)
2718 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2720 x86_pop_reg (code, X86_EDX);
2722 x86_pop_reg (code, X86_EAX);
2723 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2727 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
2730 g_assert_not_reached ();
2731 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2732 x86_mov_reg_imm (code, ins->dreg, 0);
2735 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2736 x86_mov_reg_imm (code, ins->dreg, 0);
2738 case OP_LOAD_GOTADDR:
2739 x86_call_imm (code, 0);
2741 * The patch needs to point to the pop, since the GOT offset needs
2742 * to be added to that address.
2744 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
2745 x86_pop_reg (code, ins->dreg);
2746 x86_alu_reg_imm (code, X86_ADD, ins->dreg, 0xf0f0f0f0);
2749 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2750 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
2752 case OP_X86_PUSH_GOT_ENTRY:
2753 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2754 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
2757 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2761 * Note: this 'frame destruction' logic is useful for tail calls, too.
2762 * Keep in sync with the code in emit_epilog.
2766 /* FIXME: no tracing support... */
2767 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2768 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2769 /* reset offset to make max_len work */
2770 offset = code - cfg->native_code;
2772 g_assert (!cfg->method->save_lmf);
2774 code = emit_load_volatile_arguments (cfg, code);
2776 if (cfg->used_int_regs & (1 << X86_EBX))
2778 if (cfg->used_int_regs & (1 << X86_EDI))
2780 if (cfg->used_int_regs & (1 << X86_ESI))
2783 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
2785 if (cfg->used_int_regs & (1 << X86_ESI))
2786 x86_pop_reg (code, X86_ESI);
2787 if (cfg->used_int_regs & (1 << X86_EDI))
2788 x86_pop_reg (code, X86_EDI);
2789 if (cfg->used_int_regs & (1 << X86_EBX))
2790 x86_pop_reg (code, X86_EBX);
2792 /* restore ESP/EBP */
2794 offset = code - cfg->native_code;
2795 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2796 x86_jump32 (code, 0);
2798 cfg->disable_aot = TRUE;
2802 /* ensure ins->sreg1 is not NULL
2803 * note that cmp DWORD PTR [eax], eax is one byte shorter than
2804 * cmp DWORD PTR [eax], 0
2806 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
2809 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
2810 x86_push_reg (code, hreg);
2811 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
2812 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
2813 x86_pop_reg (code, hreg);
2822 call = (MonoCallInst*)ins;
2823 if (ins->flags & MONO_INST_HAS_METHOD)
2824 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2826 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2827 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
2828 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
2829 * bytes to pop, we want to use pops. GCC does this (note it won't happen
2830 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
2831 * smart enough to do that optimization yet
2833 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
2834 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
2835 * (most likely from locality benefits). People with other processors should
2836 * check on theirs to see what happens.
2838 if (call->stack_usage == 4) {
2839 /* we want to use registers that won't get used soon, so use
2840 * ecx, as eax will get allocated first. edx is used by long calls,
2841 * so we can't use that.
2844 x86_pop_reg (code, X86_ECX);
2846 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2849 code = emit_move_return_value (cfg, ins, code);
2855 case OP_VOIDCALL_REG:
2857 call = (MonoCallInst*)ins;
2858 x86_call_reg (code, ins->sreg1);
2859 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
2860 if (call->stack_usage == 4)
2861 x86_pop_reg (code, X86_ECX);
2863 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2865 code = emit_move_return_value (cfg, ins, code);
2867 case OP_FCALL_MEMBASE:
2868 case OP_LCALL_MEMBASE:
2869 case OP_VCALL_MEMBASE:
2870 case OP_VCALL2_MEMBASE:
2871 case OP_VOIDCALL_MEMBASE:
2872 case OP_CALL_MEMBASE:
2873 call = (MonoCallInst*)ins;
2876 * Emit a few nops to simplify get_vcall_slot ().
2882 x86_call_membase (code, ins->sreg1, ins->inst_offset);
2883 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
2884 if (call->stack_usage == 4)
2885 x86_pop_reg (code, X86_ECX);
2887 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2889 code = emit_move_return_value (cfg, ins, code);
2892 x86_push_reg (code, ins->sreg1);
2894 case OP_X86_PUSH_IMM:
2895 x86_push_imm (code, ins->inst_imm);
2897 case OP_X86_PUSH_MEMBASE:
2898 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
2900 case OP_X86_PUSH_OBJ:
2901 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
2902 x86_push_reg (code, X86_EDI);
2903 x86_push_reg (code, X86_ESI);
2904 x86_push_reg (code, X86_ECX);
2905 if (ins->inst_offset)
2906 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
2908 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
2909 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2910 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
2912 x86_prefix (code, X86_REP_PREFIX);
2914 x86_pop_reg (code, X86_ECX);
2915 x86_pop_reg (code, X86_ESI);
2916 x86_pop_reg (code, X86_EDI);
2919 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
2921 case OP_X86_LEA_MEMBASE:
2922 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
2925 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
2928 /* keep alignment */
2929 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
2930 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
2931 code = mono_emit_stack_alloc (code, ins);
2932 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2934 case OP_LOCALLOC_IMM: {
2935 guint32 size = ins->inst_imm;
2936 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
2938 if (ins->flags & MONO_INST_INIT) {
2939 /* FIXME: Optimize this */
2940 x86_mov_reg_imm (code, ins->dreg, size);
2941 ins->sreg1 = ins->dreg;
2943 code = mono_emit_stack_alloc (code, ins);
2944 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2946 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
2947 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2952 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
2953 x86_push_reg (code, ins->sreg1);
2954 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
2955 (gpointer)"mono_arch_throw_exception");
2959 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
2960 x86_push_reg (code, ins->sreg1);
2961 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
2962 (gpointer)"mono_arch_rethrow_exception");
2965 case OP_CALL_HANDLER:
2966 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
2967 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2968 x86_call_imm (code, 0);
2969 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
2971 case OP_START_HANDLER: {
2972 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
2973 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
2976 case OP_ENDFINALLY: {
2977 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
2978 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
2982 case OP_ENDFILTER: {
2983 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
2984 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
2985 /* The local allocator will put the result into EAX */
2991 ins->inst_c0 = code - cfg->native_code;
2994 if (ins->inst_target_bb->native_offset) {
2995 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
2997 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2998 if ((cfg->opt & MONO_OPT_BRANCH) &&
2999 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3000 x86_jump8 (code, 0);
3002 x86_jump32 (code, 0);
3006 x86_jump_reg (code, ins->sreg1);
3019 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3020 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3022 case OP_COND_EXC_EQ:
3023 case OP_COND_EXC_NE_UN:
3024 case OP_COND_EXC_LT:
3025 case OP_COND_EXC_LT_UN:
3026 case OP_COND_EXC_GT:
3027 case OP_COND_EXC_GT_UN:
3028 case OP_COND_EXC_GE:
3029 case OP_COND_EXC_GE_UN:
3030 case OP_COND_EXC_LE:
3031 case OP_COND_EXC_LE_UN:
3032 case OP_COND_EXC_IEQ:
3033 case OP_COND_EXC_INE_UN:
3034 case OP_COND_EXC_ILT:
3035 case OP_COND_EXC_ILT_UN:
3036 case OP_COND_EXC_IGT:
3037 case OP_COND_EXC_IGT_UN:
3038 case OP_COND_EXC_IGE:
3039 case OP_COND_EXC_IGE_UN:
3040 case OP_COND_EXC_ILE:
3041 case OP_COND_EXC_ILE_UN:
3042 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3044 case OP_COND_EXC_OV:
3045 case OP_COND_EXC_NO:
3047 case OP_COND_EXC_NC:
3048 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3050 case OP_COND_EXC_IOV:
3051 case OP_COND_EXC_INO:
3052 case OP_COND_EXC_IC:
3053 case OP_COND_EXC_INC:
3054 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3066 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3074 case OP_CMOV_INE_UN:
3075 case OP_CMOV_IGE_UN:
3076 case OP_CMOV_IGT_UN:
3077 case OP_CMOV_ILE_UN:
3078 case OP_CMOV_ILT_UN:
3079 g_assert (ins->dreg == ins->sreg1);
3080 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3083 /* floating point opcodes */
3085 double d = *(double *)ins->inst_p0;
3087 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3089 } else if (d == 1.0) {
3092 if (cfg->compile_aot) {
3093 guint32 *val = (guint32*)&d;
3094 x86_push_imm (code, val [1]);
3095 x86_push_imm (code, val [0]);
3096 x86_fld_membase (code, X86_ESP, 0, TRUE);
3097 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3100 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3101 x86_fld (code, NULL, TRUE);
3107 float f = *(float *)ins->inst_p0;
3109 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3111 } else if (f == 1.0) {
3114 if (cfg->compile_aot) {
3115 guint32 val = *(guint32*)&f;
3116 x86_push_imm (code, val);
3117 x86_fld_membase (code, X86_ESP, 0, FALSE);
3118 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3121 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3122 x86_fld (code, NULL, FALSE);
3127 case OP_STORER8_MEMBASE_REG:
3128 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3130 case OP_LOADR8_MEMBASE:
3131 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3133 case OP_STORER4_MEMBASE_REG:
3134 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3136 case OP_LOADR4_MEMBASE:
3137 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3139 case OP_ICONV_TO_R4:
3140 x86_push_reg (code, ins->sreg1);
3141 x86_fild_membase (code, X86_ESP, 0, FALSE);
3142 /* Change precision */
3143 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3144 x86_fld_membase (code, X86_ESP, 0, FALSE);
3145 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3147 case OP_ICONV_TO_R8:
3148 x86_push_reg (code, ins->sreg1);
3149 x86_fild_membase (code, X86_ESP, 0, FALSE);
3150 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3152 case OP_ICONV_TO_R_UN:
3153 x86_push_imm (code, 0);
3154 x86_push_reg (code, ins->sreg1);
3155 x86_fild_membase (code, X86_ESP, 0, TRUE);
3156 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3158 case OP_X86_FP_LOAD_I8:
3159 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3161 case OP_X86_FP_LOAD_I4:
3162 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3164 case OP_FCONV_TO_R4:
3165 /* Change precision */
3166 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3167 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3168 x86_fld_membase (code, X86_ESP, 0, FALSE);
3169 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3171 case OP_FCONV_TO_I1:
3172 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3174 case OP_FCONV_TO_U1:
3175 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3177 case OP_FCONV_TO_I2:
3178 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3180 case OP_FCONV_TO_U2:
3181 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3183 case OP_FCONV_TO_I4:
3185 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3187 case OP_FCONV_TO_I8:
3188 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3189 x86_fnstcw_membase(code, X86_ESP, 0);
3190 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3191 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3192 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3193 x86_fldcw_membase (code, X86_ESP, 2);
3194 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3195 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3196 x86_pop_reg (code, ins->dreg);
3197 x86_pop_reg (code, ins->backend.reg3);
3198 x86_fldcw_membase (code, X86_ESP, 0);
3199 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3201 case OP_LCONV_TO_R8_2:
3202 x86_push_reg (code, ins->sreg2);
3203 x86_push_reg (code, ins->sreg1);
3204 x86_fild_membase (code, X86_ESP, 0, TRUE);
3205 /* Change precision */
3206 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3207 x86_fld_membase (code, X86_ESP, 0, TRUE);
3208 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3210 case OP_LCONV_TO_R4_2:
3211 x86_push_reg (code, ins->sreg2);
3212 x86_push_reg (code, ins->sreg1);
3213 x86_fild_membase (code, X86_ESP, 0, TRUE);
3214 /* Change precision */
3215 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3216 x86_fld_membase (code, X86_ESP, 0, FALSE);
3217 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3219 case OP_LCONV_TO_R_UN_2: {
3220 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3223 /* load 64bit integer to FP stack */
3224 x86_push_reg (code, ins->sreg2);
3225 x86_push_reg (code, ins->sreg1);
3226 x86_fild_membase (code, X86_ESP, 0, TRUE);
3228 /* test if lreg is negative */
3229 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3230 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3232 /* add correction constant mn */
3233 x86_fld80_mem (code, mn);
3234 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3236 x86_patch (br, code);
3238 /* Change precision */
3239 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3240 x86_fld_membase (code, X86_ESP, 0, TRUE);
3242 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3246 case OP_LCONV_TO_OVF_I:
3247 case OP_LCONV_TO_OVF_I4_2: {
3248 guint8 *br [3], *label [1];
3252 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3254 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3256 /* If the low word top bit is set, see if we are negative */
3257 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3258 /* We are not negative (no top bit set, check for our top word to be zero */
3259 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3260 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3263 /* throw exception */
3264 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3266 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3267 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3268 x86_jump8 (code, 0);
3270 x86_jump32 (code, 0);
3272 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3273 x86_jump32 (code, 0);
3277 x86_patch (br [0], code);
3278 /* our top bit is set, check that top word is 0xfffffff */
3279 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3281 x86_patch (br [1], code);
3282 /* nope, emit exception */
3283 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3284 x86_patch (br [2], label [0]);
3286 if (ins->dreg != ins->sreg1)
3287 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3291 /* Not needed on the fp stack */
3294 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3297 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3300 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3303 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3311 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3316 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3323 * it really doesn't make sense to inline all this code,
3324 * it's here just to show that things may not be as simple
3327 guchar *check_pos, *end_tan, *pop_jump;
3328 x86_push_reg (code, X86_EAX);
3331 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3333 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3334 x86_fstp (code, 0); /* pop the 1.0 */
3336 x86_jump8 (code, 0);
3338 x86_fp_op (code, X86_FADD, 0);
3342 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3344 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3347 x86_patch (pop_jump, code);
3348 x86_fstp (code, 0); /* pop the 1.0 */
3349 x86_patch (check_pos, code);
3350 x86_patch (end_tan, code);
3352 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3353 x86_pop_reg (code, X86_EAX);
3360 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3369 g_assert (cfg->opt & MONO_OPT_CMOV);
3370 g_assert (ins->dreg == ins->sreg1);
3371 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3372 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3375 g_assert (cfg->opt & MONO_OPT_CMOV);
3376 g_assert (ins->dreg == ins->sreg1);
3377 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3378 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3381 g_assert (cfg->opt & MONO_OPT_CMOV);
3382 g_assert (ins->dreg == ins->sreg1);
3383 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3384 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3387 g_assert (cfg->opt & MONO_OPT_CMOV);
3388 g_assert (ins->dreg == ins->sreg1);
3389 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3390 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3396 x86_fxch (code, ins->inst_imm);
3401 x86_push_reg (code, X86_EAX);
3402 /* we need to exchange ST(0) with ST(1) */
3405 /* this requires a loop, because fprem somtimes
3406 * returns a partial remainder */
3408 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3409 /* x86_fprem1 (code); */
3412 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3414 x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3419 x86_pop_reg (code, X86_EAX);
3423 if (cfg->opt & MONO_OPT_FCMOV) {
3424 x86_fcomip (code, 1);
3428 /* this overwrites EAX */
3429 EMIT_FPCOMPARE(code);
3430 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3433 if (cfg->opt & MONO_OPT_FCMOV) {
3434 /* zeroing the register at the start results in
3435 * shorter and faster code (we can also remove the widening op)
3437 guchar *unordered_check;
3438 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3439 x86_fcomip (code, 1);
3441 unordered_check = code;
3442 x86_branch8 (code, X86_CC_P, 0, FALSE);
3443 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3444 x86_patch (unordered_check, code);
3447 if (ins->dreg != X86_EAX)
3448 x86_push_reg (code, X86_EAX);
3450 EMIT_FPCOMPARE(code);
3451 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3452 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3453 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3454 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3456 if (ins->dreg != X86_EAX)
3457 x86_pop_reg (code, X86_EAX);
3461 if (cfg->opt & MONO_OPT_FCMOV) {
3462 /* zeroing the register at the start results in
3463 * shorter and faster code (we can also remove the widening op)
3465 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3466 x86_fcomip (code, 1);
3468 if (ins->opcode == OP_FCLT_UN) {
3469 guchar *unordered_check = code;
3470 guchar *jump_to_end;
3471 x86_branch8 (code, X86_CC_P, 0, FALSE);
3472 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3474 x86_jump8 (code, 0);
3475 x86_patch (unordered_check, code);
3476 x86_inc_reg (code, ins->dreg);
3477 x86_patch (jump_to_end, code);
3479 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3483 if (ins->dreg != X86_EAX)
3484 x86_push_reg (code, X86_EAX);
3486 EMIT_FPCOMPARE(code);
3487 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3488 if (ins->opcode == OP_FCLT_UN) {
3489 guchar *is_not_zero_check, *end_jump;
3490 is_not_zero_check = code;
3491 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3493 x86_jump8 (code, 0);
3494 x86_patch (is_not_zero_check, code);
3495 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3497 x86_patch (end_jump, code);
3499 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3500 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3502 if (ins->dreg != X86_EAX)
3503 x86_pop_reg (code, X86_EAX);
3507 if (cfg->opt & MONO_OPT_FCMOV) {
3508 /* zeroing the register at the start results in
3509 * shorter and faster code (we can also remove the widening op)
3511 guchar *unordered_check;
3512 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3513 x86_fcomip (code, 1);
3515 if (ins->opcode == OP_FCGT) {
3516 unordered_check = code;
3517 x86_branch8 (code, X86_CC_P, 0, FALSE);
3518 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3519 x86_patch (unordered_check, code);
3521 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3525 if (ins->dreg != X86_EAX)
3526 x86_push_reg (code, X86_EAX);
3528 EMIT_FPCOMPARE(code);
3529 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3530 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3531 if (ins->opcode == OP_FCGT_UN) {
3532 guchar *is_not_zero_check, *end_jump;
3533 is_not_zero_check = code;
3534 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3536 x86_jump8 (code, 0);
3537 x86_patch (is_not_zero_check, code);
3538 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3540 x86_patch (end_jump, code);
3542 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3543 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3545 if (ins->dreg != X86_EAX)
3546 x86_pop_reg (code, X86_EAX);
3549 if (cfg->opt & MONO_OPT_FCMOV) {
3550 guchar *jump = code;
3551 x86_branch8 (code, X86_CC_P, 0, TRUE);
3552 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3553 x86_patch (jump, code);
3556 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3557 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3560 /* Branch if C013 != 100 */
3561 if (cfg->opt & MONO_OPT_FCMOV) {
3562 /* branch if !ZF or (PF|CF) */
3563 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3564 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3565 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3568 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3569 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3572 if (cfg->opt & MONO_OPT_FCMOV) {
3573 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3576 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3579 if (cfg->opt & MONO_OPT_FCMOV) {
3580 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3581 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3584 if (ins->opcode == OP_FBLT_UN) {
3585 guchar *is_not_zero_check, *end_jump;
3586 is_not_zero_check = code;
3587 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3589 x86_jump8 (code, 0);
3590 x86_patch (is_not_zero_check, code);
3591 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3593 x86_patch (end_jump, code);
3595 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3599 if (cfg->opt & MONO_OPT_FCMOV) {
3600 if (ins->opcode == OP_FBGT) {
3603 /* skip branch if C1=1 */
3605 x86_branch8 (code, X86_CC_P, 0, FALSE);
3606 /* branch if (C0 | C3) = 1 */
3607 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3608 x86_patch (br1, code);
3610 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3614 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3615 if (ins->opcode == OP_FBGT_UN) {
3616 guchar *is_not_zero_check, *end_jump;
3617 is_not_zero_check = code;
3618 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3620 x86_jump8 (code, 0);
3621 x86_patch (is_not_zero_check, code);
3622 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3624 x86_patch (end_jump, code);
3626 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3629 /* Branch if C013 == 100 or 001 */
3630 if (cfg->opt & MONO_OPT_FCMOV) {
3633 /* skip branch if C1=1 */
3635 x86_branch8 (code, X86_CC_P, 0, FALSE);
3636 /* branch if (C0 | C3) = 1 */
3637 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3638 x86_patch (br1, code);
3641 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3642 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3643 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3644 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3647 /* Branch if C013 == 000 */
3648 if (cfg->opt & MONO_OPT_FCMOV) {
3649 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3652 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3655 /* Branch if C013=000 or 100 */
3656 if (cfg->opt & MONO_OPT_FCMOV) {
3659 /* skip branch if C1=1 */
3661 x86_branch8 (code, X86_CC_P, 0, FALSE);
3662 /* branch if C0=0 */
3663 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3664 x86_patch (br1, code);
3667 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
3668 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
3669 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3672 /* Branch if C013 != 001 */
3673 if (cfg->opt & MONO_OPT_FCMOV) {
3674 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3675 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3678 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3679 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3683 x86_push_reg (code, X86_EAX);
3686 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
3687 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3688 x86_pop_reg (code, X86_EAX);
3690 /* Have to clean up the fp stack before throwing the exception */
3692 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3695 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3697 x86_patch (br1, code);
3701 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
3704 case OP_MEMORY_BARRIER: {
3705 /* Not needed on x86 */
3708 case OP_ATOMIC_ADD_I4: {
3709 int dreg = ins->dreg;
3711 if (dreg == ins->inst_basereg) {
3712 x86_push_reg (code, ins->sreg2);
3716 if (dreg != ins->sreg2)
3717 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
3719 x86_prefix (code, X86_LOCK_PREFIX);
3720 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
3722 if (dreg != ins->dreg) {
3723 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
3724 x86_pop_reg (code, dreg);
3729 case OP_ATOMIC_ADD_NEW_I4: {
3730 int dreg = ins->dreg;
3732 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
3733 if (ins->sreg2 == dreg) {
3734 if (dreg == X86_EBX) {
3736 if (ins->inst_basereg == X86_EDI)
3740 if (ins->inst_basereg == X86_EBX)
3743 } else if (ins->inst_basereg == dreg) {
3744 if (dreg == X86_EBX) {
3746 if (ins->sreg2 == X86_EDI)
3750 if (ins->sreg2 == X86_EBX)
3755 if (dreg != ins->dreg) {
3756 x86_push_reg (code, dreg);
3759 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
3760 x86_prefix (code, X86_LOCK_PREFIX);
3761 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
3762 /* dreg contains the old value, add with sreg2 value */
3763 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
3765 if (ins->dreg != dreg) {
3766 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
3767 x86_pop_reg (code, dreg);
3772 case OP_ATOMIC_EXCHANGE_I4: {
3774 int sreg2 = ins->sreg2;
3775 int breg = ins->inst_basereg;
3777 /* cmpxchg uses eax as comperand, need to make sure we can use it
3778 * hack to overcome limits in x86 reg allocator
3779 * (req: dreg == eax and sreg2 != eax and breg != eax)
3781 g_assert (ins->dreg == X86_EAX);
3783 /* We need the EAX reg for the cmpxchg */
3784 if (ins->sreg2 == X86_EAX) {
3785 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
3786 x86_push_reg (code, sreg2);
3787 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
3790 if (breg == X86_EAX) {
3791 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
3792 x86_push_reg (code, breg);
3793 x86_mov_reg_reg (code, breg, X86_EAX, 4);
3796 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
3798 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
3799 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
3800 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
3801 x86_patch (br [1], br [0]);
3803 if (breg != ins->inst_basereg)
3804 x86_pop_reg (code, breg);
3806 if (ins->sreg2 != sreg2)
3807 x86_pop_reg (code, sreg2);
3811 case OP_ATOMIC_CAS_I4: {
3812 g_assert (ins->sreg3 == X86_EAX);
3813 g_assert (ins->sreg1 != X86_EAX);
3814 g_assert (ins->sreg1 != ins->sreg2);
3816 x86_prefix (code, X86_LOCK_PREFIX);
3817 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
3819 if (ins->dreg != X86_EAX)
3820 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3823 #ifdef MONO_ARCH_SIMD_INTRINSICS
3825 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
3828 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
3831 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
3834 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
3837 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
3840 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
3843 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
3844 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
3847 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
3850 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
3853 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
3856 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
3859 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
3862 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
3865 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
3868 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
3871 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
3874 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
3877 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
3880 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
3883 case OP_PSHUFLEW_HIGH:
3884 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
3885 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
3887 case OP_PSHUFLEW_LOW:
3888 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
3889 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
3892 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
3893 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
3897 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
3900 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
3903 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
3906 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
3909 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
3912 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
3915 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
3916 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
3919 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
3922 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
3925 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
3928 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
3931 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
3934 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
3937 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
3940 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
3943 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
3946 case OP_EXTRACT_MASK:
3947 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
3951 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
3954 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
3957 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
3961 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
3964 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
3967 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
3970 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
3974 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
3977 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
3980 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
3983 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
3987 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
3990 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
3993 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
3997 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4000 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4003 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4007 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4010 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4014 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4017 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4020 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4024 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4027 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4030 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4034 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4037 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4040 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4043 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4047 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4050 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4053 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4056 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4059 case OP_PSUM_ABS_DIFF:
4060 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4063 case OP_UNPACK_LOWB:
4064 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4066 case OP_UNPACK_LOWW:
4067 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4069 case OP_UNPACK_LOWD:
4070 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4072 case OP_UNPACK_LOWQ:
4073 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4075 case OP_UNPACK_LOWPS:
4076 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4078 case OP_UNPACK_LOWPD:
4079 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4082 case OP_UNPACK_HIGHB:
4083 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4085 case OP_UNPACK_HIGHW:
4086 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4088 case OP_UNPACK_HIGHD:
4089 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4091 case OP_UNPACK_HIGHQ:
4092 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4094 case OP_UNPACK_HIGHPS:
4095 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4097 case OP_UNPACK_HIGHPD:
4098 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4102 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4105 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4108 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4111 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4114 case OP_PADDB_SAT_UN:
4115 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4117 case OP_PSUBB_SAT_UN:
4118 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4120 case OP_PADDW_SAT_UN:
4121 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4123 case OP_PSUBW_SAT_UN:
4124 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4128 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4131 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4134 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4137 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4141 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4144 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4147 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4149 case OP_PMULW_HIGH_UN:
4150 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4153 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4157 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4160 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4164 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4167 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4171 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4174 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4178 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4181 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4185 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4188 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4192 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4195 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4199 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4202 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4206 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4209 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4213 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4216 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4220 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4222 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4223 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4227 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4229 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4230 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4234 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4236 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4237 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4241 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4243 case OP_EXTRACTX_U2:
4244 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4246 case OP_INSERTX_U1_SLOW:
4247 /*sreg1 is the extracted ireg (scratch)
4248 /sreg2 is the to be inserted ireg (scratch)
4249 /dreg is the xreg to receive the value*/
4251 /*clear the bits from the extracted word*/
4252 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4253 /*shift the value to insert if needed*/
4254 if (ins->inst_c0 & 1)
4255 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4256 /*join them together*/
4257 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4258 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4260 case OP_INSERTX_I4_SLOW:
4261 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4262 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4263 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4266 case OP_INSERTX_R4_SLOW:
4267 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4268 /*TODO if inst_c0 == 0 use movss*/
4269 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4270 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4272 case OP_INSERTX_R8_SLOW:
4273 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4275 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4277 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVSD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4280 case OP_STOREX_MEMBASE_REG:
4281 case OP_STOREX_MEMBASE:
4282 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4284 case OP_LOADX_MEMBASE:
4285 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4287 case OP_LOADX_ALIGNED_MEMBASE:
4288 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4290 case OP_STOREX_ALIGNED_MEMBASE_REG:
4291 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4293 case OP_STOREX_NTA_MEMBASE_REG:
4294 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4296 case OP_PREFETCH_MEMBASE:
4297 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4301 /*FIXME the peephole pass should have killed this*/
4302 if (ins->dreg != ins->sreg1)
4303 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4306 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4308 case OP_ICONV_TO_R8_RAW:
4309 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4310 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4313 case OP_FCONV_TO_R8_X:
4314 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4315 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4318 case OP_XCONV_R8_TO_I4:
4319 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4320 switch (ins->backend.source_opcode) {
4321 case OP_FCONV_TO_I1:
4322 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4324 case OP_FCONV_TO_U1:
4325 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4327 case OP_FCONV_TO_I2:
4328 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4330 case OP_FCONV_TO_U2:
4331 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4337 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4338 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4339 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4340 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4341 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4342 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4345 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4346 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4347 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4350 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4351 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4354 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4355 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4356 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4359 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4360 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4361 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4364 case OP_LIVERANGE_START: {
4365 if (cfg->verbose_level > 1)
4366 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4367 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4370 case OP_LIVERANGE_END: {
4371 if (cfg->verbose_level > 1)
4372 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4373 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4377 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4378 g_assert_not_reached ();
4381 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4382 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4383 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4384 g_assert_not_reached ();
4390 cfg->code_len = code - cfg->native_code;
4393 #endif /* DISABLE_JIT */
4396 mono_arch_register_lowlevel_calls (void)
4401 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4403 MonoJumpInfo *patch_info;
4404 gboolean compile_aot = !run_cctors;
4406 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4407 unsigned char *ip = patch_info->ip.i + code;
4408 const unsigned char *target;
4410 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4413 switch (patch_info->type) {
4414 case MONO_PATCH_INFO_BB:
4415 case MONO_PATCH_INFO_LABEL:
4418 /* No need to patch these */
4423 switch (patch_info->type) {
4424 case MONO_PATCH_INFO_IP:
4425 *((gconstpointer *)(ip)) = target;
4427 case MONO_PATCH_INFO_CLASS_INIT: {
4429 /* Might already been changed to a nop */
4430 x86_call_code (code, 0);
4431 x86_patch (ip, target);
4434 case MONO_PATCH_INFO_ABS:
4435 case MONO_PATCH_INFO_METHOD:
4436 case MONO_PATCH_INFO_METHOD_JUMP:
4437 case MONO_PATCH_INFO_INTERNAL_METHOD:
4438 case MONO_PATCH_INFO_BB:
4439 case MONO_PATCH_INFO_LABEL:
4440 case MONO_PATCH_INFO_RGCTX_FETCH:
4441 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
4442 case MONO_PATCH_INFO_MONITOR_ENTER:
4443 case MONO_PATCH_INFO_MONITOR_EXIT:
4444 x86_patch (ip, target);
4446 case MONO_PATCH_INFO_NONE:
4449 guint32 offset = mono_arch_get_patch_offset (ip);
4450 *((gconstpointer *)(ip + offset)) = target;
4458 mono_arch_emit_prolog (MonoCompile *cfg)
4460 MonoMethod *method = cfg->method;
4462 MonoMethodSignature *sig;
4464 int alloc_size, pos, max_offset, i, cfa_offset;
4466 gboolean need_stack_frame;
4468 cfg->code_size = MAX (mono_method_get_header (method)->code_size * 4, 10240);
4470 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4471 cfg->code_size += 512;
4473 code = cfg->native_code = g_malloc (cfg->code_size);
4475 /* Offset between RSP and the CFA */
4479 cfa_offset = sizeof (gpointer);
4480 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
4481 // IP saved at CFA - 4
4482 /* There is no IP reg on x86 */
4483 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
4485 need_stack_frame = needs_stack_frame (cfg);
4487 if (need_stack_frame) {
4488 x86_push_reg (code, X86_EBP);
4489 cfa_offset += sizeof (gpointer);
4490 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4491 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
4492 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
4493 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
4496 alloc_size = cfg->stack_offset;
4499 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4500 /* Might need to attach the thread to the JIT or change the domain for the callback */
4501 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4502 guint8 *buf, *no_domain_branch;
4504 code = mono_x86_emit_tls_get (code, X86_EAX, appdomain_tls_offset);
4505 x86_alu_reg_imm (code, X86_CMP, X86_EAX, GPOINTER_TO_UINT (cfg->domain));
4506 no_domain_branch = code;
4507 x86_branch8 (code, X86_CC_NE, 0, 0);
4508 code = mono_x86_emit_tls_get ( code, X86_EAX, lmf_tls_offset);
4509 x86_test_reg_reg (code, X86_EAX, X86_EAX);
4511 x86_branch8 (code, X86_CC_NE, 0, 0);
4512 x86_patch (no_domain_branch, code);
4513 x86_push_imm (code, cfg->domain);
4514 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4515 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
4516 x86_patch (buf, code);
4517 #ifdef PLATFORM_WIN32
4518 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4519 /* FIXME: Add a separate key for LMF to avoid this */
4520 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4524 g_assert (!cfg->compile_aot);
4525 x86_push_imm (code, cfg->domain);
4526 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4527 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
4531 if (method->save_lmf) {
4532 pos += sizeof (MonoLMF);
4534 if (cfg->compile_aot)
4535 cfg->disable_aot = TRUE;
4537 /* save the current IP */
4538 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
4539 x86_push_imm_template (code);
4540 cfa_offset += sizeof (gpointer);
4542 /* save all caller saved regs */
4543 x86_push_reg (code, X86_EBP);
4544 cfa_offset += sizeof (gpointer);
4545 x86_push_reg (code, X86_ESI);
4546 cfa_offset += sizeof (gpointer);
4547 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
4548 x86_push_reg (code, X86_EDI);
4549 cfa_offset += sizeof (gpointer);
4550 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
4551 x86_push_reg (code, X86_EBX);
4552 cfa_offset += sizeof (gpointer);
4553 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
4555 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
4557 * Optimized version which uses the mono_lmf TLS variable instead of indirection
4558 * through the mono_lmf_addr TLS variable.
4560 /* %eax = previous_lmf */
4561 x86_prefix (code, X86_GS_PREFIX);
4562 x86_mov_reg_mem (code, X86_EAX, lmf_tls_offset, 4);
4563 /* skip esp + method_info + lmf */
4564 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 12);
4565 /* push previous_lmf */
4566 x86_push_reg (code, X86_EAX);
4568 x86_prefix (code, X86_GS_PREFIX);
4569 x86_mov_mem_reg (code, lmf_tls_offset, X86_ESP, 4);
4571 /* get the address of lmf for the current thread */
4573 * This is performance critical so we try to use some tricks to make
4577 if (lmf_addr_tls_offset != -1) {
4578 /* Load lmf quicky using the GS register */
4579 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
4580 #ifdef PLATFORM_WIN32
4581 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4582 /* FIXME: Add a separate key for LMF to avoid this */
4583 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4586 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
4589 /* Skip esp + method info */
4590 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
4593 x86_push_reg (code, X86_EAX);
4594 /* push *lfm (previous_lmf) */
4595 x86_push_membase (code, X86_EAX, 0);
4597 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
4601 if (cfg->used_int_regs & (1 << X86_EBX)) {
4602 x86_push_reg (code, X86_EBX);
4604 cfa_offset += sizeof (gpointer);
4605 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
4608 if (cfg->used_int_regs & (1 << X86_EDI)) {
4609 x86_push_reg (code, X86_EDI);
4611 cfa_offset += sizeof (gpointer);
4612 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
4615 if (cfg->used_int_regs & (1 << X86_ESI)) {
4616 x86_push_reg (code, X86_ESI);
4618 cfa_offset += sizeof (gpointer);
4619 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
4625 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
4626 if (mono_do_x86_stack_align && need_stack_frame) {
4627 int tot = alloc_size + pos + 4; /* ret ip */
4628 if (need_stack_frame)
4630 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
4632 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
4636 /* See mono_emit_stack_alloc */
4637 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4638 guint32 remaining_size = alloc_size;
4639 while (remaining_size >= 0x1000) {
4640 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
4641 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
4642 remaining_size -= 0x1000;
4645 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
4647 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
4650 g_assert (need_stack_frame);
4653 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
4654 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
4655 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
4658 #if DEBUG_STACK_ALIGNMENT
4659 /* check the stack is aligned */
4660 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
4661 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
4662 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
4663 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
4664 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
4665 x86_breakpoint (code);
4669 /* compute max_offset in order to use short forward jumps */
4671 if (cfg->opt & MONO_OPT_BRANCH) {
4672 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4674 bb->max_offset = max_offset;
4676 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4678 /* max alignment for loops */
4679 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4680 max_offset += LOOP_ALIGNMENT;
4682 MONO_BB_FOR_EACH_INS (bb, ins) {
4683 if (ins->opcode == OP_LABEL)
4684 ins->inst_c1 = max_offset;
4686 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4691 /* store runtime generic context */
4692 if (cfg->rgctx_var) {
4693 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
4695 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
4698 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4699 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4701 /* load arguments allocated to register from the stack */
4702 sig = mono_method_signature (method);
4705 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4706 inst = cfg->args [pos];
4707 if (inst->opcode == OP_REGVAR) {
4708 g_assert (need_stack_frame);
4709 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
4710 if (cfg->verbose_level > 2)
4711 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
4716 cfg->code_len = code - cfg->native_code;
4718 g_assert (cfg->code_len < cfg->code_size);
4724 mono_arch_emit_epilog (MonoCompile *cfg)
4726 MonoMethod *method = cfg->method;
4727 MonoMethodSignature *sig = mono_method_signature (method);
4729 guint32 stack_to_pop;
4731 int max_epilog_size = 16;
4733 gboolean need_stack_frame = needs_stack_frame (cfg);
4735 if (cfg->method->save_lmf)
4736 max_epilog_size += 128;
4738 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4739 cfg->code_size *= 2;
4740 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4741 mono_jit_stats.code_reallocs++;
4744 code = cfg->native_code + cfg->code_len;
4746 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4747 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4749 /* the code restoring the registers must be kept in sync with OP_JMP */
4752 if (method->save_lmf) {
4753 gint32 prev_lmf_reg;
4754 gint32 lmf_offset = -sizeof (MonoLMF);
4756 /* check if we need to restore protection of the stack after a stack overflow */
4757 if (mono_get_jit_tls_offset () != -1) {
4759 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
4760 /* we load the value in a separate instruction: this mechanism may be
4761 * used later as a safer way to do thread interruption
4763 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
4764 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
4766 x86_branch8 (code, X86_CC_Z, 0, FALSE);
4767 /* note that the call trampoline will preserve eax/edx */
4768 x86_call_reg (code, X86_ECX);
4769 x86_patch (patch, code);
4771 /* FIXME: maybe save the jit tls in the prolog */
4773 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
4775 * Optimized version which uses the mono_lmf TLS variable instead of indirection
4776 * through the mono_lmf_addr TLS variable.
4778 /* reg = previous_lmf */
4779 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
4781 /* lmf = previous_lmf */
4782 x86_prefix (code, X86_GS_PREFIX);
4783 x86_mov_mem_reg (code, lmf_tls_offset, X86_ECX, 4);
4785 /* Find a spare register */
4786 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
4789 prev_lmf_reg = X86_EDI;
4790 cfg->used_int_regs |= (1 << X86_EDI);
4793 prev_lmf_reg = X86_EDX;
4797 /* reg = previous_lmf */
4798 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
4801 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
4803 /* *(lmf) = previous_lmf */
4804 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
4807 /* restore caller saved regs */
4808 if (cfg->used_int_regs & (1 << X86_EBX)) {
4809 x86_mov_reg_membase (code, X86_EBX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
4812 if (cfg->used_int_regs & (1 << X86_EDI)) {
4813 x86_mov_reg_membase (code, X86_EDI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
4815 if (cfg->used_int_regs & (1 << X86_ESI)) {
4816 x86_mov_reg_membase (code, X86_ESI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
4819 /* EBP is restored by LEAVE */
4821 if (cfg->used_int_regs & (1 << X86_EBX)) {
4824 if (cfg->used_int_regs & (1 << X86_EDI)) {
4827 if (cfg->used_int_regs & (1 << X86_ESI)) {
4832 g_assert (need_stack_frame);
4833 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
4836 if (cfg->used_int_regs & (1 << X86_ESI)) {
4837 x86_pop_reg (code, X86_ESI);
4839 if (cfg->used_int_regs & (1 << X86_EDI)) {
4840 x86_pop_reg (code, X86_EDI);
4842 if (cfg->used_int_regs & (1 << X86_EBX)) {
4843 x86_pop_reg (code, X86_EBX);
4847 /* Load returned vtypes into registers if needed */
4848 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
4849 if (cinfo->ret.storage == ArgValuetypeInReg) {
4850 for (quad = 0; quad < 2; quad ++) {
4851 switch (cinfo->ret.pair_storage [quad]) {
4853 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
4855 case ArgOnFloatFpStack:
4856 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
4858 case ArgOnDoubleFpStack:
4859 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
4864 g_assert_not_reached ();
4869 if (need_stack_frame)
4872 if (CALLCONV_IS_STDCALL (sig)) {
4873 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
4875 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
4876 } else if (MONO_TYPE_ISSTRUCT (mono_method_signature (cfg->method)->ret) && (cinfo->ret.storage == ArgOnStack))
4882 g_assert (need_stack_frame);
4883 x86_ret_imm (code, stack_to_pop);
4888 cfg->code_len = code - cfg->native_code;
4890 g_assert (cfg->code_len < cfg->code_size);
4894 mono_arch_emit_exceptions (MonoCompile *cfg)
4896 MonoJumpInfo *patch_info;
4899 MonoClass *exc_classes [16];
4900 guint8 *exc_throw_start [16], *exc_throw_end [16];
4904 /* Compute needed space */
4905 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4906 if (patch_info->type == MONO_PATCH_INFO_EXC)
4911 * make sure we have enough space for exceptions
4912 * 16 is the size of two push_imm instructions and a call
4914 if (cfg->compile_aot)
4915 code_size = exc_count * 32;
4917 code_size = exc_count * 16;
4919 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4920 cfg->code_size *= 2;
4921 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4922 mono_jit_stats.code_reallocs++;
4925 code = cfg->native_code + cfg->code_len;
4928 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4929 switch (patch_info->type) {
4930 case MONO_PATCH_INFO_EXC: {
4931 MonoClass *exc_class;
4935 x86_patch (patch_info->ip.i + cfg->native_code, code);
4937 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4938 g_assert (exc_class);
4939 throw_ip = patch_info->ip.i;
4941 /* Find a throw sequence for the same exception class */
4942 for (i = 0; i < nthrows; ++i)
4943 if (exc_classes [i] == exc_class)
4946 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
4947 x86_jump_code (code, exc_throw_start [i]);
4948 patch_info->type = MONO_PATCH_INFO_NONE;
4953 /* Compute size of code following the push <OFFSET> */
4956 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
4958 if ((code - cfg->native_code) - throw_ip < 126 - size) {
4959 /* Use the shorter form */
4961 x86_push_imm (code, 0);
4965 x86_push_imm (code, 0xf0f0f0f0);
4970 exc_classes [nthrows] = exc_class;
4971 exc_throw_start [nthrows] = code;
4974 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
4975 patch_info->data.name = "mono_arch_throw_corlib_exception";
4976 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4977 patch_info->ip.i = code - cfg->native_code;
4978 x86_call_code (code, 0);
4979 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
4984 exc_throw_end [nthrows] = code;
4996 cfg->code_len = code - cfg->native_code;
4998 g_assert (cfg->code_len < cfg->code_size);
5002 mono_arch_flush_icache (guint8 *code, gint size)
5008 mono_arch_flush_register_windows (void)
5013 mono_arch_is_inst_imm (gint64 imm)
5019 * Support for fast access to the thread-local lmf structure using the GS
5020 * segment register on NPTL + kernel 2.6.x.
5023 static gboolean tls_offset_inited = FALSE;
5026 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5028 if (!tls_offset_inited) {
5029 if (!getenv ("MONO_NO_TLS")) {
5030 #ifdef PLATFORM_WIN32
5032 * We need to init this multiple times, since when we are first called, the key might not
5033 * be initialized yet.
5035 appdomain_tls_offset = mono_domain_get_tls_key ();
5036 lmf_tls_offset = mono_get_jit_tls_key ();
5038 /* Only 64 tls entries can be accessed using inline code */
5039 if (appdomain_tls_offset >= 64)
5040 appdomain_tls_offset = -1;
5041 if (lmf_tls_offset >= 64)
5042 lmf_tls_offset = -1;
5045 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5047 tls_offset_inited = TRUE;
5048 appdomain_tls_offset = mono_domain_get_tls_offset ();
5049 lmf_tls_offset = mono_get_lmf_tls_offset ();
5050 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5057 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5061 #ifdef MONO_ARCH_HAVE_IMT
5063 // Linear handler, the bsearch head compare is shorter
5064 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5065 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5066 // x86_patch(ins,target)
5067 //[1 + 5] x86_jump_mem(inst,mem)
5070 #define BR_SMALL_SIZE 2
5071 #define BR_LARGE_SIZE 5
5072 #define JUMP_IMM_SIZE 6
5073 #define ENABLE_WRONG_METHOD_CHECK 0
5076 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5078 int i, distance = 0;
5079 for (i = start; i < target; ++i)
5080 distance += imt_entries [i]->chunk_size;
5085 * LOCKING: called with the domain lock held
5088 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5089 gpointer fail_tramp)
5093 guint8 *code, *start;
5095 for (i = 0; i < count; ++i) {
5096 MonoIMTCheckItem *item = imt_entries [i];
5097 if (item->is_equals) {
5098 if (item->check_target_idx) {
5099 if (!item->compare_done)
5100 item->chunk_size += CMP_SIZE;
5101 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5104 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5106 item->chunk_size += JUMP_IMM_SIZE;
5107 #if ENABLE_WRONG_METHOD_CHECK
5108 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5113 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5114 imt_entries [item->check_target_idx]->compare_done = TRUE;
5116 size += item->chunk_size;
5119 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5121 code = mono_domain_code_reserve (domain, size);
5123 for (i = 0; i < count; ++i) {
5124 MonoIMTCheckItem *item = imt_entries [i];
5125 item->code_target = code;
5126 if (item->is_equals) {
5127 if (item->check_target_idx) {
5128 if (!item->compare_done)
5129 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5130 item->jmp_code = code;
5131 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5132 if (item->has_target_code)
5133 x86_jump_code (code, item->value.target_code);
5135 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5138 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5139 item->jmp_code = code;
5140 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5141 if (item->has_target_code)
5142 x86_jump_code (code, item->value.target_code);
5144 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5145 x86_patch (item->jmp_code, code);
5146 x86_jump_code (code, fail_tramp);
5147 item->jmp_code = NULL;
5149 /* enable the commented code to assert on wrong method */
5150 #if ENABLE_WRONG_METHOD_CHECK
5151 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5152 item->jmp_code = code;
5153 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5155 if (item->has_target_code)
5156 x86_jump_code (code, item->value.target_code);
5158 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5159 #if ENABLE_WRONG_METHOD_CHECK
5160 x86_patch (item->jmp_code, code);
5161 x86_breakpoint (code);
5162 item->jmp_code = NULL;
5167 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5168 item->jmp_code = code;
5169 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5170 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5172 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5175 /* patch the branches to get to the target items */
5176 for (i = 0; i < count; ++i) {
5177 MonoIMTCheckItem *item = imt_entries [i];
5178 if (item->jmp_code) {
5179 if (item->check_target_idx) {
5180 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5186 mono_stats.imt_thunks_size += code - start;
5187 g_assert (code - start <= size);
5192 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5194 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5198 mono_arch_find_this_argument (mgreg_t *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
5200 MonoMethodSignature *sig = mono_method_signature (method);
5201 CallInfo *cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5202 int this_argument_offset;
5203 MonoObject *this_argument;
5206 * this is the offset of the this arg from esp as saved at the start of
5207 * mono_arch_create_trampoline_code () in tramp-x86.c.
5209 this_argument_offset = 5;
5210 if (MONO_TYPE_ISSTRUCT (sig->ret) && (cinfo->ret.storage == ArgOnStack))
5211 this_argument_offset++;
5213 this_argument = * (MonoObject**) (((guint8*) regs [X86_ESP]) + this_argument_offset * sizeof (gpointer));
5216 return this_argument;
5221 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5223 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5227 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5229 MonoInst *ins = NULL;
5232 if (cmethod->klass == mono_defaults.math_class) {
5233 if (strcmp (cmethod->name, "Sin") == 0) {
5235 } else if (strcmp (cmethod->name, "Cos") == 0) {
5237 } else if (strcmp (cmethod->name, "Tan") == 0) {
5239 } else if (strcmp (cmethod->name, "Atan") == 0) {
5241 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5243 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5245 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5250 MONO_INST_NEW (cfg, ins, opcode);
5251 ins->type = STACK_R8;
5252 ins->dreg = mono_alloc_freg (cfg);
5253 ins->sreg1 = args [0]->dreg;
5254 MONO_ADD_INS (cfg->cbb, ins);
5257 if (cfg->opt & MONO_OPT_CMOV) {
5260 if (strcmp (cmethod->name, "Min") == 0) {
5261 if (fsig->params [0]->type == MONO_TYPE_I4)
5263 } else if (strcmp (cmethod->name, "Max") == 0) {
5264 if (fsig->params [0]->type == MONO_TYPE_I4)
5269 MONO_INST_NEW (cfg, ins, opcode);
5270 ins->type = STACK_I4;
5271 ins->dreg = mono_alloc_ireg (cfg);
5272 ins->sreg1 = args [0]->dreg;
5273 ins->sreg2 = args [1]->dreg;
5274 MONO_ADD_INS (cfg->cbb, ins);
5279 /* OP_FREM is not IEEE compatible */
5280 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5281 MONO_INST_NEW (cfg, ins, OP_FREM);
5282 ins->inst_i0 = args [0];
5283 ins->inst_i1 = args [1];
5292 mono_arch_print_tree (MonoInst *tree, int arity)
5297 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5303 if (appdomain_tls_offset == -1)
5306 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5307 ins->inst_offset = appdomain_tls_offset;
5312 mono_arch_get_patch_offset (guint8 *code)
5314 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5316 else if ((code [0] == 0xba))
5318 else if ((code [0] == 0x68))
5321 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5322 /* push <OFFSET>(<REG>) */
5324 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5325 /* call *<OFFSET>(<REG>) */
5327 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5330 else if ((code [0] == 0x58) && (code [1] == 0x05))
5331 /* pop %eax; add <OFFSET>, %eax */
5333 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5334 /* pop <REG>; add <OFFSET>, <REG> */
5336 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5337 /* mov <REG>, imm */
5340 g_assert_not_reached ();
5346 * mono_breakpoint_clean_code:
5348 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5349 * breakpoints in the original code, they are removed in the copy.
5351 * Returns TRUE if no sw breakpoint was present.
5354 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5357 gboolean can_write = TRUE;
5359 * If method_start is non-NULL we need to perform bound checks, since we access memory
5360 * at code - offset we could go before the start of the method and end up in a different
5361 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5364 if (!method_start || code - offset >= method_start) {
5365 memcpy (buf, code - offset, size);
5367 int diff = code - method_start;
5368 memset (buf, 0, size);
5369 memcpy (buf + offset - diff, method_start, diff + size - offset);
5372 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5373 int idx = mono_breakpoint_info_index [i];
5377 ptr = mono_breakpoint_info [idx].address;
5378 if (ptr >= code && ptr < code + size) {
5379 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5381 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5382 buf [ptr - code] = saved_byte;
5389 mono_arch_get_vcall_slot (guint8 *code, mgreg_t *regs, int *displacement)
5395 mono_breakpoint_clean_code (NULL, code, 8, buf, sizeof (buf));
5403 * A given byte sequence can match more than case here, so we have to be
5404 * really careful about the ordering of the cases. Longer sequences
5406 * There are two types of calls:
5407 * - direct calls: 0xff address_byte 8/32 bits displacement
5408 * - indirect calls: nop nop nop <call>
5409 * The nops make sure we don't confuse the instruction preceeding an indirect
5410 * call with a direct call.
5412 if ((code [1] != 0xe8) && (code [3] == 0xff) && ((code [4] & 0x18) == 0x10) && ((code [4] >> 6) == 1)) {
5413 reg = code [4] & 0x07;
5414 disp = (signed char)code [5];
5415 } else if ((code [0] == 0xff) && ((code [1] & 0x18) == 0x10) && ((code [1] >> 6) == 2)) {
5416 reg = code [1] & 0x07;
5417 disp = *((gint32*)(code + 2));
5418 } else if ((code [1] == 0xe8)) {
5420 } else if ((code [4] == 0xff) && (((code [5] >> 6) & 0x3) == 0) && (((code [5] >> 3) & 0x7) == 2)) {
5422 * This is a interface call
5423 * 8b 40 30 mov 0x30(%eax),%eax
5424 * ff 10 call *(%eax)
5427 reg = code [5] & 0x07;
5432 *displacement = disp;
5433 return (gpointer)regs [reg];
5437 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig,
5438 mgreg_t *regs, guint8 *code)
5440 guint32 esp = regs [X86_ESP];
5441 CallInfo *cinfo = NULL;
5446 * Avoid expensive calls to get_generic_context_from_code () + get_call_info
5449 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5451 gsctx = mono_get_generic_context_from_code (code);
5452 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5454 offset = cinfo->args [0].offset;
5460 * The stack looks like:
5463 * <possible vtype return address>
5465 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
5467 res = (((MonoObject**)esp) [5 + (offset / 4)]);
5473 #define MAX_ARCH_DELEGATE_PARAMS 10
5476 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5478 guint8 *code, *start;
5480 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5483 /* FIXME: Support more cases */
5484 if (MONO_TYPE_ISSTRUCT (sig->ret))
5488 * The stack contains:
5494 static guint8* cached = NULL;
5498 start = code = mono_global_codeman_reserve (64);
5500 /* Replace the this argument with the target */
5501 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5502 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
5503 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5504 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5506 g_assert ((code - start) < 64);
5508 mono_debug_add_delegate_trampoline (start, code - start);
5510 mono_memory_barrier ();
5514 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5516 /* 8 for mov_reg and jump, plus 8 for each parameter */
5517 int code_reserve = 8 + (sig->param_count * 8);
5519 for (i = 0; i < sig->param_count; ++i)
5520 if (!mono_is_regsize_var (sig->params [i]))
5523 code = cache [sig->param_count];
5528 * The stack contains:
5529 * <args in reverse order>
5534 * <args in reverse order>
5537 * without unbalancing the stack.
5538 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
5539 * and leaving original spot of first arg as placeholder in stack so
5540 * when callee pops stack everything works.
5543 start = code = mono_global_codeman_reserve (code_reserve);
5545 /* store delegate for access to method_ptr */
5546 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
5549 for (i = 0; i < sig->param_count; ++i) {
5550 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
5551 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
5554 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5556 g_assert ((code - start) < code_reserve);
5558 mono_debug_add_delegate_trampoline (start, code - start);
5560 mono_memory_barrier ();
5562 cache [sig->param_count] = start;
5569 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5572 case X86_EAX: return (gpointer)ctx->eax;
5573 case X86_EBX: return (gpointer)ctx->ebx;
5574 case X86_ECX: return (gpointer)ctx->ecx;
5575 case X86_EDX: return (gpointer)ctx->edx;
5576 case X86_ESP: return (gpointer)ctx->esp;
5577 case X86_EBP: return (gpointer)ctx->ebp;
5578 case X86_ESI: return (gpointer)ctx->esi;
5579 case X86_EDI: return (gpointer)ctx->edi;
5580 default: g_assert_not_reached ();
5584 #ifdef MONO_ARCH_SIMD_INTRINSICS
5587 get_float_to_x_spill_area (MonoCompile *cfg)
5589 if (!cfg->fconv_to_r8_x_var) {
5590 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
5591 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
5593 return cfg->fconv_to_r8_x_var;
5597 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
5600 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
5603 int dreg, src_opcode;
5605 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
5608 switch (src_opcode = ins->opcode) {
5609 case OP_FCONV_TO_I1:
5610 case OP_FCONV_TO_U1:
5611 case OP_FCONV_TO_I2:
5612 case OP_FCONV_TO_U2:
5613 case OP_FCONV_TO_I4:
5620 /* dreg is the IREG and sreg1 is the FREG */
5621 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
5622 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
5623 fconv->sreg1 = ins->sreg1;
5624 fconv->dreg = mono_alloc_ireg (cfg);
5625 fconv->type = STACK_VTYPE;
5626 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
5628 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
5632 ins->opcode = OP_XCONV_R8_TO_I4;
5634 ins->klass = mono_defaults.int32_class;
5635 ins->sreg1 = fconv->dreg;
5637 ins->type = STACK_I4;
5638 ins->backend.source_opcode = src_opcode;
5641 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
5644 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
5649 if (long_ins->opcode == OP_LNEG) {
5651 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
5652 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
5653 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
5658 #ifdef MONO_ARCH_SIMD_INTRINSICS
5660 if (!(cfg->opt & MONO_OPT_SIMD))
5663 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
5664 switch (long_ins->opcode) {
5666 vreg = long_ins->sreg1;
5668 if (long_ins->inst_c0) {
5669 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
5670 ins->klass = long_ins->klass;
5671 ins->sreg1 = long_ins->sreg1;
5673 ins->type = STACK_VTYPE;
5674 ins->dreg = vreg = alloc_ireg (cfg);
5675 MONO_ADD_INS (cfg->cbb, ins);
5678 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
5679 ins->klass = mono_defaults.int32_class;
5681 ins->type = STACK_I4;
5682 ins->dreg = long_ins->dreg + 1;
5683 MONO_ADD_INS (cfg->cbb, ins);
5685 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
5686 ins->klass = long_ins->klass;
5687 ins->sreg1 = long_ins->sreg1;
5688 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
5689 ins->type = STACK_VTYPE;
5690 ins->dreg = vreg = alloc_ireg (cfg);
5691 MONO_ADD_INS (cfg->cbb, ins);
5693 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
5694 ins->klass = mono_defaults.int32_class;
5696 ins->type = STACK_I4;
5697 ins->dreg = long_ins->dreg + 2;
5698 MONO_ADD_INS (cfg->cbb, ins);
5700 long_ins->opcode = OP_NOP;
5702 case OP_INSERTX_I8_SLOW:
5703 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
5704 ins->dreg = long_ins->dreg;
5705 ins->sreg1 = long_ins->dreg;
5706 ins->sreg2 = long_ins->sreg2 + 1;
5707 ins->inst_c0 = long_ins->inst_c0 * 2;
5708 MONO_ADD_INS (cfg->cbb, ins);
5710 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
5711 ins->dreg = long_ins->dreg;
5712 ins->sreg1 = long_ins->dreg;
5713 ins->sreg2 = long_ins->sreg2 + 2;
5714 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
5715 MONO_ADD_INS (cfg->cbb, ins);
5717 long_ins->opcode = OP_NOP;
5720 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
5721 ins->dreg = long_ins->dreg;
5722 ins->sreg1 = long_ins->sreg1 + 1;
5723 ins->klass = long_ins->klass;
5724 ins->type = STACK_VTYPE;
5725 MONO_ADD_INS (cfg->cbb, ins);
5727 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
5728 ins->dreg = long_ins->dreg;
5729 ins->sreg1 = long_ins->dreg;
5730 ins->sreg2 = long_ins->sreg1 + 2;
5732 ins->klass = long_ins->klass;
5733 ins->type = STACK_VTYPE;
5734 MONO_ADD_INS (cfg->cbb, ins);
5736 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
5737 ins->dreg = long_ins->dreg;
5738 ins->sreg1 = long_ins->dreg;;
5739 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
5740 ins->klass = long_ins->klass;
5741 ins->type = STACK_VTYPE;
5742 MONO_ADD_INS (cfg->cbb, ins);
5744 long_ins->opcode = OP_NOP;
5747 #endif /* MONO_ARCH_SIMD_INTRINSICS */
5751 #define DBG_SIGNAL SIGBUS
5753 #define DBG_SIGNAL SIGSEGV
5756 /* Soft Debug support */
5757 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
5760 * mono_arch_set_breakpoint:
5762 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
5763 * The location should contain code emitted by OP_SEQ_POINT.
5766 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
5771 * In production, we will use int3 (has to fix the size in the md
5772 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
5775 g_assert (code [0] == 0x90);
5776 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
5780 * mono_arch_clear_breakpoint:
5782 * Clear the breakpoint at IP.
5785 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
5790 for (i = 0; i < 6; ++i)
5795 * mono_arch_start_single_stepping:
5797 * Start single stepping.
5800 mono_arch_start_single_stepping (void)
5802 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
5806 * mono_arch_stop_single_stepping:
5808 * Stop single stepping.
5811 mono_arch_stop_single_stepping (void)
5813 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
5817 * mono_arch_is_single_step_event:
5819 * Return whenever the machine state in SIGCTX corresponds to a single
5823 mono_arch_is_single_step_event (void *info, void *sigctx)
5825 #ifdef PLATFORM_WIN32
5826 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
5829 siginfo_t* sinfo = (siginfo_t*) info;
5830 /* Sometimes the address is off by 4 */
5831 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
5839 mono_arch_is_breakpoint_event (void *info, void *sigctx)
5841 #ifdef PLATFORM_WIN32
5842 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
5845 siginfo_t* sinfo = (siginfo_t*)info;
5846 /* Sometimes the address is off by 4 */
5847 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
5855 * mono_arch_get_ip_for_breakpoint:
5857 * See mini-amd64.c for docs.
5860 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
5862 guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
5867 #define BREAKPOINT_SIZE 6
5870 * mono_arch_get_ip_for_single_step:
5872 * See mini-amd64.c for docs.
5875 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
5877 guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
5879 /* Size of x86_alu_reg_imm */
5886 * mono_arch_skip_breakpoint:
5888 * See mini-amd64.c for docs.
5891 mono_arch_skip_breakpoint (MonoContext *ctx)
5893 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
5897 * mono_arch_skip_single_step:
5899 * See mini-amd64.c for docs.
5902 mono_arch_skip_single_step (MonoContext *ctx)
5904 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
5908 * mono_arch_get_seq_point_info:
5910 * See mini-amd64.c for docs.
5913 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)