2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
12 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
21 #include <mono/metadata/abi-details.h>
22 #include <mono/metadata/appdomain.h>
23 #include <mono/metadata/debug-helpers.h>
24 #include <mono/metadata/threads.h>
25 #include <mono/metadata/profiler-private.h>
26 #include <mono/metadata/mono-debug.h>
27 #include <mono/metadata/gc-internals.h>
28 #include <mono/utils/mono-math.h>
29 #include <mono/utils/mono-counters.h>
30 #include <mono/utils/mono-mmap.h>
31 #include <mono/utils/mono-memory-model.h>
32 #include <mono/utils/mono-hwcap-x86.h>
33 #include <mono/utils/mono-threads.h>
43 static gboolean optimize_for_xen = TRUE;
45 #define optimize_for_xen 0
49 /* The single step trampoline */
50 static gpointer ss_trampoline;
52 /* The breakpoint trampoline */
53 static gpointer bp_trampoline;
55 /* This mutex protects architecture specific caches */
56 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
57 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
58 static mono_mutex_t mini_arch_mutex;
60 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
65 /* Under windows, the default pinvoke calling convention is stdcall */
66 #define CALLCONV_IS_STDCALL(sig) ((sig)->pinvoke && ((sig)->call_convention == MONO_CALL_STDCALL || (sig)->call_convention == MONO_CALL_DEFAULT || (sig)->call_convention == MONO_CALL_THISCALL))
68 #define CALLCONV_IS_STDCALL(sig) ((sig)->pinvoke && ((sig)->call_convention == MONO_CALL_STDCALL || (sig)->call_convention == MONO_CALL_THISCALL))
71 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
73 #define OP_SEQ_POINT_BP_OFFSET 7
76 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
79 mono_arch_regname (int reg)
82 case X86_EAX: return "%eax";
83 case X86_EBX: return "%ebx";
84 case X86_ECX: return "%ecx";
85 case X86_EDX: return "%edx";
86 case X86_ESP: return "%esp";
87 case X86_EBP: return "%ebp";
88 case X86_EDI: return "%edi";
89 case X86_ESI: return "%esi";
95 mono_arch_fregname (int reg)
120 mono_arch_xregname (int reg)
145 mono_x86_patch (unsigned char* code, gpointer target)
147 x86_patch (code, (unsigned char*)target);
150 #define FLOAT_PARAM_REGS 0
152 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
154 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
159 switch (sig->call_convention) {
160 case MONO_CALL_THISCALL:
161 return thiscall_param_regs;
167 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
168 #define SMALL_STRUCTS_IN_REGS
169 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
173 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
175 ainfo->offset = *stack_size;
177 if (!param_regs || param_regs [*gr] == X86_NREG) {
178 ainfo->storage = ArgOnStack;
180 (*stack_size) += sizeof (gpointer);
183 ainfo->storage = ArgInIReg;
184 ainfo->reg = param_regs [*gr];
190 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
192 ainfo->offset = *stack_size;
194 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
196 ainfo->storage = ArgOnStack;
197 (*stack_size) += sizeof (gpointer) * 2;
202 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
204 ainfo->offset = *stack_size;
206 if (*gr >= FLOAT_PARAM_REGS) {
207 ainfo->storage = ArgOnStack;
208 (*stack_size) += is_double ? 8 : 4;
209 ainfo->nslots = is_double ? 2 : 1;
212 /* A double register */
214 ainfo->storage = ArgInDoubleSSEReg;
216 ainfo->storage = ArgInFloatSSEReg;
224 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
226 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
231 klass = mono_class_from_mono_type (type);
232 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
234 #if defined(TARGET_WIN32)
236 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
237 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
238 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
239 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
240 * it must be represented in call and cannot be dropped.
242 if (size == 0 && MONO_TYPE_ISSTRUCT (type) && sig->pinvoke) {
243 /* Empty structs (1 byte size) needs to be represented in a stack slot */
244 ainfo->pass_empty_struct = TRUE;
249 #ifdef SMALL_STRUCTS_IN_REGS
250 if (sig->pinvoke && is_return) {
251 MonoMarshalType *info;
253 info = mono_marshal_load_type_info (klass);
256 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
258 /* Ignore empty struct return value, if used. */
259 if (info->num_fields == 0 && ainfo->pass_empty_struct) {
260 ainfo->storage = ArgValuetypeInReg;
265 * Windows x86 ABI for returning structs of size 4 or 8 bytes (regardless of type) dictates that
266 * values are passed in EDX:EAX register pairs, https://msdn.microsoft.com/en-us/library/984x0h58.aspx.
267 * This is different compared to for example float or double return types (not in struct) that will be returned
268 * in ST(0), https://msdn.microsoft.com/en-us/library/ha59cbfz.aspx.
270 * Apples OSX x86 ABI for returning structs of size 4 or 8 bytes uses a slightly different approach.
271 * If a struct includes only one scalar value, it will be handled with the same rules as scalar values.
272 * This means that structs with one float or double will be returned in ST(0). For more details,
273 * https://developer.apple.com/library/mac/documentation/DeveloperTools/Conceptual/LowLevelABI/130-IA-32_Function_Calling_Conventions/IA32.html.
275 #if !defined(TARGET_WIN32)
277 /* Special case structs with only a float member */
278 if (info->num_fields == 1) {
279 int ftype = mini_get_underlying_type (info->fields [0].field->type)->type;
280 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
281 ainfo->storage = ArgValuetypeInReg;
282 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
285 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
286 ainfo->storage = ArgValuetypeInReg;
287 ainfo->pair_storage [0] = ArgOnFloatFpStack;
293 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
294 ainfo->storage = ArgValuetypeInReg;
295 ainfo->pair_storage [0] = ArgInIReg;
296 ainfo->pair_regs [0] = return_regs [0];
297 if (info->native_size > 4) {
298 ainfo->pair_storage [1] = ArgInIReg;
299 ainfo->pair_regs [1] = return_regs [1];
306 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
307 g_assert (size <= 4);
308 ainfo->storage = ArgValuetypeInReg;
309 ainfo->reg = param_regs [*gr];
314 ainfo->offset = *stack_size;
315 ainfo->storage = ArgOnStack;
316 *stack_size += ALIGN_TO (size, sizeof (gpointer));
317 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
323 * Obtain information about a call according to the calling convention.
324 * For x86 ELF, see the "System V Application Binary Interface Intel386
325 * Architecture Processor Supplment, Fourth Edition" document for more
327 * For x86 win32, see https://msdn.microsoft.com/en-us/library/984x0h58.aspx.
330 get_call_info_internal (CallInfo *cinfo, MonoMethodSignature *sig)
332 guint32 i, gr, fr, pstart;
333 const guint32 *param_regs;
335 int n = sig->hasthis + sig->param_count;
336 guint32 stack_size = 0;
337 gboolean is_pinvoke = sig->pinvoke;
343 param_regs = callconv_param_regs(sig);
347 ret_type = mini_get_underlying_type (sig->ret);
348 switch (ret_type->type) {
358 case MONO_TYPE_FNPTR:
359 case MONO_TYPE_CLASS:
360 case MONO_TYPE_OBJECT:
361 case MONO_TYPE_SZARRAY:
362 case MONO_TYPE_ARRAY:
363 case MONO_TYPE_STRING:
364 cinfo->ret.storage = ArgInIReg;
365 cinfo->ret.reg = X86_EAX;
369 cinfo->ret.storage = ArgInIReg;
370 cinfo->ret.reg = X86_EAX;
371 cinfo->ret.is_pair = TRUE;
374 cinfo->ret.storage = ArgOnFloatFpStack;
377 cinfo->ret.storage = ArgOnDoubleFpStack;
379 case MONO_TYPE_GENERICINST:
380 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
381 cinfo->ret.storage = ArgInIReg;
382 cinfo->ret.reg = X86_EAX;
385 if (mini_is_gsharedvt_type (ret_type)) {
386 cinfo->ret.storage = ArgOnStack;
387 cinfo->vtype_retaddr = TRUE;
391 case MONO_TYPE_VALUETYPE:
392 case MONO_TYPE_TYPEDBYREF: {
393 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
395 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
396 if (cinfo->ret.storage == ArgOnStack) {
397 cinfo->vtype_retaddr = TRUE;
398 /* The caller passes the address where the value is stored */
404 g_assert (mini_is_gsharedvt_type (ret_type));
405 cinfo->ret.storage = ArgOnStack;
406 cinfo->vtype_retaddr = TRUE;
409 cinfo->ret.storage = ArgNone;
412 g_error ("Can't handle as return value 0x%x", ret_type->type);
418 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
419 * the first argument, allowing 'this' to be always passed in the first arg reg.
420 * Also do this if the first argument is a reference type, since virtual calls
421 * are sometimes made using calli without sig->hasthis set, like in the delegate
424 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
426 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
428 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
431 cinfo->vret_arg_offset = stack_size;
432 add_general (&gr, NULL, &stack_size, &cinfo->ret);
433 cinfo->vret_arg_index = 1;
437 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
439 if (cinfo->vtype_retaddr)
440 add_general (&gr, NULL, &stack_size, &cinfo->ret);
443 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
444 fr = FLOAT_PARAM_REGS;
446 /* Emit the signature cookie just before the implicit arguments */
447 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
450 for (i = pstart; i < sig->param_count; ++i) {
451 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
454 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
455 /* We allways pass the sig cookie on the stack for simplicity */
457 * Prevent implicit arguments + the sig cookie from being passed
460 fr = FLOAT_PARAM_REGS;
462 /* Emit the signature cookie just before the implicit arguments */
463 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
466 if (sig->params [i]->byref) {
467 add_general (&gr, param_regs, &stack_size, ainfo);
470 ptype = mini_get_underlying_type (sig->params [i]);
471 switch (ptype->type) {
474 add_general (&gr, param_regs, &stack_size, ainfo);
478 add_general (&gr, param_regs, &stack_size, ainfo);
482 add_general (&gr, param_regs, &stack_size, ainfo);
487 case MONO_TYPE_FNPTR:
488 case MONO_TYPE_CLASS:
489 case MONO_TYPE_OBJECT:
490 case MONO_TYPE_STRING:
491 case MONO_TYPE_SZARRAY:
492 case MONO_TYPE_ARRAY:
493 add_general (&gr, param_regs, &stack_size, ainfo);
495 case MONO_TYPE_GENERICINST:
496 if (!mono_type_generic_inst_is_valuetype (ptype)) {
497 add_general (&gr, param_regs, &stack_size, ainfo);
500 if (mini_is_gsharedvt_type (ptype)) {
501 /* gsharedvt arguments are passed by ref */
502 add_general (&gr, param_regs, &stack_size, ainfo);
503 g_assert (ainfo->storage == ArgOnStack);
504 ainfo->storage = ArgGSharedVt;
508 case MONO_TYPE_VALUETYPE:
509 case MONO_TYPE_TYPEDBYREF:
510 add_valuetype (sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
514 add_general_pair (&gr, param_regs, &stack_size, ainfo);
517 add_float (&fr, &stack_size, ainfo, FALSE);
520 add_float (&fr, &stack_size, ainfo, TRUE);
524 /* gsharedvt arguments are passed by ref */
525 g_assert (mini_is_gsharedvt_type (ptype));
526 add_general (&gr, param_regs, &stack_size, ainfo);
527 g_assert (ainfo->storage == ArgOnStack);
528 ainfo->storage = ArgGSharedVt;
531 g_error ("unexpected type 0x%x", ptype->type);
532 g_assert_not_reached ();
536 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
537 fr = FLOAT_PARAM_REGS;
539 /* Emit the signature cookie just before the implicit arguments */
540 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
543 if (cinfo->vtype_retaddr) {
544 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
545 cinfo->callee_stack_pop = 4;
546 } else if (CALLCONV_IS_STDCALL (sig)) {
547 /* Have to compensate for the stack space popped by the native callee */
548 cinfo->callee_stack_pop = stack_size;
551 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
552 cinfo->need_stack_align = TRUE;
553 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
554 stack_size += cinfo->stack_align_amount;
557 cinfo->stack_usage = stack_size;
558 cinfo->reg_usage = gr;
559 cinfo->freg_usage = fr;
564 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
566 int n = sig->hasthis + sig->param_count;
570 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
572 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
574 return get_call_info_internal (cinfo, sig);
578 * mono_arch_get_argument_info:
579 * @csig: a method signature
580 * @param_count: the number of parameters to consider
581 * @arg_info: an array to store the result infos
583 * Gathers information on parameters such as size, alignment and
584 * padding. arg_info should be large enought to hold param_count + 1 entries.
586 * Returns the size of the argument area on the stack.
587 * This should be signal safe, since it is called from
588 * mono_arch_unwind_frame ().
589 * FIXME: The metadata calls might not be signal safe.
592 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
594 int len, k, args_size = 0;
600 /* Avoid g_malloc as it is not signal safe */
601 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
602 cinfo = (CallInfo*)g_newa (guint8*, len);
603 memset (cinfo, 0, len);
605 cinfo = get_call_info_internal (cinfo, csig);
607 arg_info [0].offset = offset;
609 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
610 args_size += sizeof (gpointer);
615 args_size += sizeof (gpointer);
619 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
620 /* Emitted after this */
621 args_size += sizeof (gpointer);
625 arg_info [0].size = args_size;
627 for (k = 0; k < param_count; k++) {
628 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
630 /* ignore alignment for now */
633 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
634 arg_info [k].pad = pad;
636 arg_info [k + 1].pad = 0;
637 arg_info [k + 1].size = size;
639 arg_info [k + 1].offset = offset;
642 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
643 /* Emitted after the first arg */
644 args_size += sizeof (gpointer);
649 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
650 align = MONO_ARCH_FRAME_ALIGNMENT;
653 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
654 arg_info [k].pad = pad;
660 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
662 MonoType *callee_ret;
666 if (cfg->compile_aot && !cfg->full_aot)
667 /* OP_TAILCALL doesn't work with AOT */
670 c1 = get_call_info (NULL, caller_sig);
671 c2 = get_call_info (NULL, callee_sig);
673 * Tail calls with more callee stack usage than the caller cannot be supported, since
674 * the extra stack space would be left on the stack after the tail call.
676 res = c1->stack_usage >= c2->stack_usage;
677 callee_ret = mini_get_underlying_type (callee_sig->ret);
678 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
679 /* An address on the callee's stack is passed as the first argument */
689 * Initialize the cpu to execute managed code.
692 mono_arch_cpu_init (void)
694 /* spec compliance requires running with double precision */
698 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
699 fpcw &= ~X86_FPCW_PRECC_MASK;
700 fpcw |= X86_FPCW_PREC_DOUBLE;
701 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
702 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
704 _control87 (_PC_53, MCW_PC);
709 * Initialize architecture specific code.
712 mono_arch_init (void)
714 mono_os_mutex_init_recursive (&mini_arch_mutex);
717 bp_trampoline = mini_get_breakpoint_trampoline ();
719 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
720 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
721 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
722 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
727 * Cleanup architecture specific code.
730 mono_arch_cleanup (void)
732 mono_os_mutex_destroy (&mini_arch_mutex);
736 * This function returns the optimizations supported on this cpu.
739 mono_arch_cpu_optimizations (guint32 *exclude_mask)
745 if (mono_hwcap_x86_has_cmov) {
746 opts |= MONO_OPT_CMOV;
748 if (mono_hwcap_x86_has_fcmov)
749 opts |= MONO_OPT_FCMOV;
751 *exclude_mask |= MONO_OPT_FCMOV;
753 *exclude_mask |= MONO_OPT_CMOV;
756 if (mono_hwcap_x86_has_sse2)
757 opts |= MONO_OPT_SSE2;
759 *exclude_mask |= MONO_OPT_SSE2;
761 #ifdef MONO_ARCH_SIMD_INTRINSICS
762 /*SIMD intrinsics require at least SSE2.*/
763 if (!mono_hwcap_x86_has_sse2)
764 *exclude_mask |= MONO_OPT_SIMD;
771 * This function test for all SSE functions supported.
773 * Returns a bitmask corresponding to all supported versions.
777 mono_arch_cpu_enumerate_simd_versions (void)
779 guint32 sse_opts = 0;
781 if (mono_hwcap_x86_has_sse1)
782 sse_opts |= SIMD_VERSION_SSE1;
784 if (mono_hwcap_x86_has_sse2)
785 sse_opts |= SIMD_VERSION_SSE2;
787 if (mono_hwcap_x86_has_sse3)
788 sse_opts |= SIMD_VERSION_SSE3;
790 if (mono_hwcap_x86_has_ssse3)
791 sse_opts |= SIMD_VERSION_SSSE3;
793 if (mono_hwcap_x86_has_sse41)
794 sse_opts |= SIMD_VERSION_SSE41;
796 if (mono_hwcap_x86_has_sse42)
797 sse_opts |= SIMD_VERSION_SSE42;
799 if (mono_hwcap_x86_has_sse4a)
800 sse_opts |= SIMD_VERSION_SSE4a;
806 * Determine whenever the trap whose info is in SIGINFO is caused by
810 mono_arch_is_int_overflow (void *sigctx, void *info)
815 mono_sigctx_to_monoctx (sigctx, &ctx);
817 ip = (guint8*)ctx.eip;
819 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
823 switch (x86_modrm_rm (ip [1])) {
843 g_assert_not_reached ();
855 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
860 for (i = 0; i < cfg->num_varinfo; i++) {
861 MonoInst *ins = cfg->varinfo [i];
862 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
865 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
868 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
869 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
872 /* we dont allocate I1 to registers because there is no simply way to sign extend
873 * 8bit quantities in caller saved registers on x86 */
874 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
875 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
876 g_assert (i == vmv->idx);
877 vars = g_list_prepend (vars, vmv);
881 vars = mono_varlist_sort (cfg, vars, 0);
887 mono_arch_get_global_int_regs (MonoCompile *cfg)
891 /* we can use 3 registers for global allocation */
892 regs = g_list_prepend (regs, (gpointer)X86_EBX);
893 regs = g_list_prepend (regs, (gpointer)X86_ESI);
894 regs = g_list_prepend (regs, (gpointer)X86_EDI);
900 * mono_arch_regalloc_cost:
902 * Return the cost, in number of memory references, of the action of
903 * allocating the variable VMV into a register during global register
907 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
909 MonoInst *ins = cfg->varinfo [vmv->idx];
911 if (cfg->method->save_lmf)
912 /* The register is already saved */
913 return (ins->opcode == OP_ARG) ? 1 : 0;
915 /* push+pop+possible load if it is an argument */
916 return (ins->opcode == OP_ARG) ? 3 : 2;
920 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
922 static int inited = FALSE;
923 static int count = 0;
925 if (cfg->arch.need_stack_frame_inited) {
926 g_assert (cfg->arch.need_stack_frame == flag);
930 cfg->arch.need_stack_frame = flag;
931 cfg->arch.need_stack_frame_inited = TRUE;
937 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
942 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
946 needs_stack_frame (MonoCompile *cfg)
948 MonoMethodSignature *sig;
949 MonoMethodHeader *header;
950 gboolean result = FALSE;
952 #if defined(__APPLE__)
953 /*OSX requires stack frame code to have the correct alignment. */
957 if (cfg->arch.need_stack_frame_inited)
958 return cfg->arch.need_stack_frame;
960 header = cfg->header;
961 sig = mono_method_signature (cfg->method);
963 if (cfg->disable_omit_fp)
965 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
967 else if (cfg->method->save_lmf)
969 else if (cfg->stack_offset)
971 else if (cfg->param_area)
973 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
975 else if (header->num_clauses)
977 else if (sig->param_count + sig->hasthis)
979 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
981 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
982 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
985 set_needs_stack_frame (cfg, result);
987 return cfg->arch.need_stack_frame;
991 * Set var information according to the calling convention. X86 version.
992 * The locals var stuff should most likely be split in another method.
995 mono_arch_allocate_vars (MonoCompile *cfg)
997 MonoMethodSignature *sig;
998 MonoMethodHeader *header;
1000 guint32 locals_stack_size, locals_stack_align;
1005 header = cfg->header;
1006 sig = mono_method_signature (cfg->method);
1008 if (!cfg->arch.cinfo)
1009 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1010 cinfo = (CallInfo *)cfg->arch.cinfo;
1012 cfg->frame_reg = X86_EBP;
1015 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1016 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1017 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1020 /* Reserve space to save LMF and caller saved registers */
1022 if (cfg->method->save_lmf) {
1023 /* The LMF var is allocated normally */
1025 if (cfg->used_int_regs & (1 << X86_EBX)) {
1029 if (cfg->used_int_regs & (1 << X86_EDI)) {
1033 if (cfg->used_int_regs & (1 << X86_ESI)) {
1038 switch (cinfo->ret.storage) {
1039 case ArgValuetypeInReg:
1040 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1042 cfg->ret->opcode = OP_REGOFFSET;
1043 cfg->ret->inst_basereg = X86_EBP;
1044 cfg->ret->inst_offset = - offset;
1050 /* Allocate locals */
1051 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1052 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1053 char *mname = mono_method_full_name (cfg->method, TRUE);
1054 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1058 if (locals_stack_align) {
1059 int prev_offset = offset;
1061 offset += (locals_stack_align - 1);
1062 offset &= ~(locals_stack_align - 1);
1064 while (prev_offset < offset) {
1066 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1069 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1070 cfg->locals_max_stack_offset = - offset;
1072 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1073 * have locals larger than 8 bytes we need to make sure that
1074 * they have the appropriate offset.
1076 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1077 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1078 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1079 if (offsets [i] != -1) {
1080 MonoInst *inst = cfg->varinfo [i];
1081 inst->opcode = OP_REGOFFSET;
1082 inst->inst_basereg = X86_EBP;
1083 inst->inst_offset = - (offset + offsets [i]);
1084 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1087 offset += locals_stack_size;
1091 * Allocate arguments+return value
1094 switch (cinfo->ret.storage) {
1096 if (cfg->vret_addr) {
1098 * In the new IR, the cfg->vret_addr variable represents the
1099 * vtype return value.
1101 cfg->vret_addr->opcode = OP_REGOFFSET;
1102 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1103 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1104 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1105 printf ("vret_addr =");
1106 mono_print_ins (cfg->vret_addr);
1109 cfg->ret->opcode = OP_REGOFFSET;
1110 cfg->ret->inst_basereg = X86_EBP;
1111 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1114 case ArgValuetypeInReg:
1117 cfg->ret->opcode = OP_REGVAR;
1118 cfg->ret->inst_c0 = cinfo->ret.reg;
1119 cfg->ret->dreg = cinfo->ret.reg;
1122 case ArgOnFloatFpStack:
1123 case ArgOnDoubleFpStack:
1126 g_assert_not_reached ();
1129 if (sig->call_convention == MONO_CALL_VARARG) {
1130 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1131 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1134 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1135 ArgInfo *ainfo = &cinfo->args [i];
1136 inst = cfg->args [i];
1137 if (inst->opcode != OP_REGVAR) {
1138 inst->opcode = OP_REGOFFSET;
1139 inst->inst_basereg = X86_EBP;
1140 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1144 cfg->stack_offset = offset;
1148 mono_arch_create_vars (MonoCompile *cfg)
1151 MonoMethodSignature *sig;
1154 sig = mono_method_signature (cfg->method);
1156 if (!cfg->arch.cinfo)
1157 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1158 cinfo = (CallInfo *)cfg->arch.cinfo;
1160 sig_ret = mini_get_underlying_type (sig->ret);
1162 if (cinfo->ret.storage == ArgValuetypeInReg)
1163 cfg->ret_var_is_local = TRUE;
1164 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (sig_ret))) {
1165 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1168 if (cfg->gen_sdb_seq_points) {
1171 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1172 ins->flags |= MONO_INST_VOLATILE;
1173 cfg->arch.ss_tramp_var = ins;
1175 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1176 ins->flags |= MONO_INST_VOLATILE;
1177 cfg->arch.bp_tramp_var = ins;
1180 if (cfg->method->save_lmf) {
1181 cfg->create_lmf_var = TRUE;
1184 cfg->lmf_ir_mono_lmf = TRUE;
1188 cfg->arch_eh_jit_info = 1;
1192 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1193 * so we try to do it just once when we have multiple fp arguments in a row.
1194 * We don't use this mechanism generally because for int arguments the generated code
1195 * is slightly bigger and new generation cpus optimize away the dependency chains
1196 * created by push instructions on the esp value.
1197 * fp_arg_setup is the first argument in the execution sequence where the esp register
1200 static G_GNUC_UNUSED int
1201 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1206 for (; start_arg < sig->param_count; ++start_arg) {
1207 t = mini_get_underlying_type (sig->params [start_arg]);
1208 if (!t->byref && t->type == MONO_TYPE_R8) {
1209 fp_space += sizeof (double);
1210 *fp_arg_setup = start_arg;
1219 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1221 MonoMethodSignature *tmp_sig;
1225 * mono_ArgIterator_Setup assumes the signature cookie is
1226 * passed first and all the arguments which were before it are
1227 * passed on the stack after the signature. So compensate by
1228 * passing a different signature.
1230 tmp_sig = mono_metadata_signature_dup (call->signature);
1231 tmp_sig->param_count -= call->signature->sentinelpos;
1232 tmp_sig->sentinelpos = 0;
1233 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1235 if (cfg->compile_aot) {
1236 sig_reg = mono_alloc_ireg (cfg);
1237 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1238 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1240 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1246 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1251 LLVMCallInfo *linfo;
1252 MonoType *t, *sig_ret;
1254 n = sig->param_count + sig->hasthis;
1256 cinfo = get_call_info (cfg->mempool, sig);
1259 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1262 * LLVM always uses the native ABI while we use our own ABI, the
1263 * only difference is the handling of vtypes:
1264 * - we only pass/receive them in registers in some cases, and only
1265 * in 1 or 2 integer registers.
1267 if (cinfo->ret.storage == ArgValuetypeInReg) {
1269 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1270 cfg->disable_llvm = TRUE;
1274 cfg->exception_message = g_strdup ("vtype ret in call");
1275 cfg->disable_llvm = TRUE;
1277 linfo->ret.storage = LLVMArgVtypeInReg;
1278 for (j = 0; j < 2; ++j)
1279 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1283 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage == ArgInIReg) {
1284 /* Vtype returned using a hidden argument */
1285 linfo->ret.storage = LLVMArgVtypeRetAddr;
1286 linfo->vret_arg_index = cinfo->vret_arg_index;
1289 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage != ArgInIReg) {
1291 cfg->exception_message = g_strdup ("vtype ret in call");
1292 cfg->disable_llvm = TRUE;
1295 for (i = 0; i < n; ++i) {
1296 ainfo = cinfo->args + i;
1298 if (i >= sig->hasthis)
1299 t = sig->params [i - sig->hasthis];
1301 t = &mono_defaults.int_class->byval_arg;
1303 linfo->args [i].storage = LLVMArgNone;
1305 switch (ainfo->storage) {
1307 linfo->args [i].storage = LLVMArgNormal;
1309 case ArgInDoubleSSEReg:
1310 case ArgInFloatSSEReg:
1311 linfo->args [i].storage = LLVMArgNormal;
1314 if (mini_type_is_vtype (t)) {
1315 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1316 /* LLVM seems to allocate argument space for empty structures too */
1317 linfo->args [i].storage = LLVMArgNone;
1319 linfo->args [i].storage = LLVMArgVtypeByVal;
1321 linfo->args [i].storage = LLVMArgNormal;
1324 case ArgValuetypeInReg:
1326 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1327 cfg->disable_llvm = TRUE;
1331 cfg->exception_message = g_strdup ("vtype arg");
1332 cfg->disable_llvm = TRUE;
1334 linfo->args [i].storage = LLVMArgVtypeInReg;
1335 for (j = 0; j < 2; ++j)
1336 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1340 linfo->args [i].storage = LLVMArgGSharedVt;
1343 cfg->exception_message = g_strdup ("ainfo->storage");
1344 cfg->disable_llvm = TRUE;
1354 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1356 if (cfg->compute_gc_maps) {
1359 /* Needs checking if the feature will be enabled again */
1360 g_assert_not_reached ();
1362 /* On x86, the offsets are from the sp value before the start of the call sequence */
1364 t = &mono_defaults.int_class->byval_arg;
1365 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1370 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1374 MonoMethodSignature *sig;
1377 int sentinelpos = 0, sp_offset = 0;
1379 sig = call->signature;
1380 n = sig->param_count + sig->hasthis;
1381 sig_ret = mini_get_underlying_type (sig->ret);
1383 cinfo = get_call_info (cfg->mempool, sig);
1384 call->call_info = cinfo;
1386 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1387 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1389 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1390 if (cinfo->ret.storage == ArgValuetypeInReg && cinfo->ret.pair_storage[0] != ArgNone ) {
1392 * Tell the JIT to use a more efficient calling convention: call using
1393 * OP_CALL, compute the result location after the call, and save the
1396 call->vret_in_reg = TRUE;
1397 #if defined(__APPLE__)
1398 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1399 call->vret_in_reg_fp = TRUE;
1402 NULLIFY_INS (call->vret_var);
1406 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1408 /* Handle the case where there are no implicit arguments */
1409 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1410 emit_sig_cookie (cfg, call, cinfo);
1411 sp_offset = cinfo->sig_cookie.offset;
1412 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1415 /* Arguments are pushed in the reverse order */
1416 for (i = n - 1; i >= 0; i --) {
1417 ArgInfo *ainfo = cinfo->args + i;
1418 MonoType *orig_type, *t;
1421 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1424 /* Push the vret arg before the first argument */
1425 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1426 vtarg->type = STACK_MP;
1427 vtarg->inst_destbasereg = X86_ESP;
1428 vtarg->sreg1 = call->vret_var->dreg;
1429 vtarg->inst_offset = cinfo->ret.offset;
1430 MONO_ADD_INS (cfg->cbb, vtarg);
1431 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1434 if (i >= sig->hasthis)
1435 t = sig->params [i - sig->hasthis];
1437 t = &mono_defaults.int_class->byval_arg;
1439 t = mini_get_underlying_type (t);
1441 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1443 in = call->args [i];
1444 arg->cil_code = in->cil_code;
1445 arg->sreg1 = in->dreg;
1446 arg->type = in->type;
1448 g_assert (in->dreg != -1);
1450 if (ainfo->storage == ArgGSharedVt) {
1451 arg->opcode = OP_OUTARG_VT;
1452 arg->sreg1 = in->dreg;
1453 arg->klass = in->klass;
1454 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1455 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1457 MONO_ADD_INS (cfg->cbb, arg);
1458 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1462 g_assert (in->klass);
1464 if (t->type == MONO_TYPE_TYPEDBYREF) {
1465 size = sizeof (MonoTypedRef);
1466 align = sizeof (gpointer);
1469 size = mini_type_stack_size_full (&in->klass->byval_arg, &align, sig->pinvoke);
1472 if (size > 0 || ainfo->pass_empty_struct) {
1473 arg->opcode = OP_OUTARG_VT;
1474 arg->sreg1 = in->dreg;
1475 arg->klass = in->klass;
1476 arg->backend.size = size;
1477 arg->inst_p0 = call;
1478 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1479 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1481 MONO_ADD_INS (cfg->cbb, arg);
1482 if (ainfo->storage != ArgValuetypeInReg) {
1483 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1487 switch (ainfo->storage) {
1490 if (t->type == MONO_TYPE_R4) {
1491 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1493 } else if (t->type == MONO_TYPE_R8) {
1494 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1496 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1497 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, MONO_LVREG_MS (in->dreg));
1498 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, MONO_LVREG_LS (in->dreg));
1501 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1505 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1510 arg->opcode = OP_MOVE;
1511 arg->dreg = ainfo->reg;
1512 MONO_ADD_INS (cfg->cbb, arg);
1516 g_assert_not_reached ();
1519 if (cfg->compute_gc_maps) {
1521 /* FIXME: The == STACK_OBJ check might be fragile ? */
1522 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1524 if (call->need_unbox_trampoline)
1525 /* The unbox trampoline transforms this into a managed pointer */
1526 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.int_class->this_arg);
1528 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.object_class->byval_arg);
1530 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1534 for (j = 0; j < argsize; j += 4)
1535 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1540 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1541 /* Emit the signature cookie just before the implicit arguments */
1542 emit_sig_cookie (cfg, call, cinfo);
1543 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1547 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1550 if (cinfo->ret.storage == ArgValuetypeInReg) {
1553 else if (cinfo->ret.storage == ArgInIReg) {
1555 /* The return address is passed in a register */
1556 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1557 vtarg->sreg1 = call->inst.dreg;
1558 vtarg->dreg = mono_alloc_ireg (cfg);
1559 MONO_ADD_INS (cfg->cbb, vtarg);
1561 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1562 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1563 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1564 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1568 call->stack_usage = cinfo->stack_usage;
1569 call->stack_align_amount = cinfo->stack_align_amount;
1573 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1575 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1576 ArgInfo *ainfo = ins->inst_p1;
1577 int size = ins->backend.size;
1579 if (ainfo->storage == ArgValuetypeInReg) {
1580 int dreg = mono_alloc_ireg (cfg);
1583 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1586 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1589 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1593 g_assert_not_reached ();
1595 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1598 if (cfg->gsharedvt && mini_is_gsharedvt_klass (ins->klass)) {
1600 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1601 } else if (size <= 4) {
1602 int dreg = mono_alloc_ireg (cfg);
1603 if (ainfo->pass_empty_struct) {
1604 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
1605 MONO_EMIT_NEW_ICONST (cfg, dreg, 0);
1607 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1609 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1610 } else if (size <= 20) {
1611 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1613 // FIXME: Code growth
1614 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1620 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1622 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
1625 if (ret->type == MONO_TYPE_R4) {
1626 if (COMPILE_LLVM (cfg))
1627 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1630 } else if (ret->type == MONO_TYPE_R8) {
1631 if (COMPILE_LLVM (cfg))
1632 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1635 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1636 if (COMPILE_LLVM (cfg))
1637 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1639 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, MONO_LVREG_LS (val->dreg));
1640 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, MONO_LVREG_MS (val->dreg));
1646 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1650 * Allow tracing to work with this interface (with an optional argument)
1653 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1657 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1658 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1660 /* if some args are passed in registers, we need to save them here */
1661 x86_push_reg (code, X86_EBP);
1663 if (cfg->compile_aot) {
1664 x86_push_imm (code, cfg->method);
1665 x86_mov_reg_imm (code, X86_EAX, func);
1666 x86_call_reg (code, X86_EAX);
1668 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1669 x86_push_imm (code, cfg->method);
1670 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1671 x86_call_code (code, 0);
1673 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1687 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1690 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1691 MonoMethod *method = cfg->method;
1692 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
1694 switch (ret_type->type) {
1695 case MONO_TYPE_VOID:
1696 /* special case string .ctor icall */
1697 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1698 save_mode = SAVE_EAX;
1699 stack_usage = enable_arguments ? 8 : 4;
1701 save_mode = SAVE_NONE;
1705 save_mode = SAVE_EAX_EDX;
1706 stack_usage = enable_arguments ? 16 : 8;
1710 save_mode = SAVE_FP;
1711 stack_usage = enable_arguments ? 16 : 8;
1713 case MONO_TYPE_GENERICINST:
1714 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1715 save_mode = SAVE_EAX;
1716 stack_usage = enable_arguments ? 8 : 4;
1720 case MONO_TYPE_VALUETYPE:
1721 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1722 save_mode = SAVE_STRUCT;
1723 stack_usage = enable_arguments ? 4 : 0;
1726 save_mode = SAVE_EAX;
1727 stack_usage = enable_arguments ? 8 : 4;
1731 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1733 switch (save_mode) {
1735 x86_push_reg (code, X86_EDX);
1736 x86_push_reg (code, X86_EAX);
1737 if (enable_arguments) {
1738 x86_push_reg (code, X86_EDX);
1739 x86_push_reg (code, X86_EAX);
1744 x86_push_reg (code, X86_EAX);
1745 if (enable_arguments) {
1746 x86_push_reg (code, X86_EAX);
1751 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1752 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1753 if (enable_arguments) {
1754 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1755 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1760 if (enable_arguments) {
1761 x86_push_membase (code, X86_EBP, 8);
1770 if (cfg->compile_aot) {
1771 x86_push_imm (code, method);
1772 x86_mov_reg_imm (code, X86_EAX, func);
1773 x86_call_reg (code, X86_EAX);
1775 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1776 x86_push_imm (code, method);
1777 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1778 x86_call_code (code, 0);
1781 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1783 switch (save_mode) {
1785 x86_pop_reg (code, X86_EAX);
1786 x86_pop_reg (code, X86_EDX);
1789 x86_pop_reg (code, X86_EAX);
1792 x86_fld_membase (code, X86_ESP, 0, TRUE);
1793 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1800 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1805 #define EMIT_COND_BRANCH(ins,cond,sign) \
1806 if (ins->inst_true_bb->native_offset) { \
1807 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1809 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1810 if ((cfg->opt & MONO_OPT_BRANCH) && \
1811 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1812 x86_branch8 (code, cond, 0, sign); \
1814 x86_branch32 (code, cond, 0, sign); \
1818 * Emit an exception if condition is fail and
1819 * if possible do a directly branch to target
1821 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1823 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1824 if (tins == NULL) { \
1825 mono_add_patch_info (cfg, code - cfg->native_code, \
1826 MONO_PATCH_INFO_EXC, exc_name); \
1827 x86_branch32 (code, cond, 0, signed); \
1829 EMIT_COND_BRANCH (tins, cond, signed); \
1833 #define EMIT_FPCOMPARE(code) do { \
1834 x86_fcompp (code); \
1835 x86_fnstsw (code); \
1840 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1842 gboolean needs_paddings = TRUE;
1844 MonoJumpInfo *jinfo = NULL;
1846 if (cfg->abs_patches) {
1847 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1848 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1849 needs_paddings = FALSE;
1852 if (cfg->compile_aot)
1853 needs_paddings = FALSE;
1854 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1855 This is required for code patching to be safe on SMP machines.
1857 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1858 if (needs_paddings && pad_size)
1859 x86_padding (code, 4 - pad_size);
1861 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1862 x86_call_code (code, 0);
1867 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1870 * mono_peephole_pass_1:
1872 * Perform peephole opts which should/can be performed before local regalloc
1875 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1879 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1880 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1882 switch (ins->opcode) {
1885 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1887 * X86_LEA is like ADD, but doesn't have the
1888 * sreg1==dreg restriction.
1890 ins->opcode = OP_X86_LEA_MEMBASE;
1891 ins->inst_basereg = ins->sreg1;
1892 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1893 ins->opcode = OP_X86_INC_REG;
1897 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1898 ins->opcode = OP_X86_LEA_MEMBASE;
1899 ins->inst_basereg = ins->sreg1;
1900 ins->inst_imm = -ins->inst_imm;
1901 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1902 ins->opcode = OP_X86_DEC_REG;
1904 case OP_COMPARE_IMM:
1905 case OP_ICOMPARE_IMM:
1906 /* OP_COMPARE_IMM (reg, 0)
1908 * OP_X86_TEST_NULL (reg)
1911 ins->opcode = OP_X86_TEST_NULL;
1913 case OP_X86_COMPARE_MEMBASE_IMM:
1915 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1916 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1918 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1919 * OP_COMPARE_IMM reg, imm
1921 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1923 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1924 ins->inst_basereg == last_ins->inst_destbasereg &&
1925 ins->inst_offset == last_ins->inst_offset) {
1926 ins->opcode = OP_COMPARE_IMM;
1927 ins->sreg1 = last_ins->sreg1;
1929 /* check if we can remove cmp reg,0 with test null */
1931 ins->opcode = OP_X86_TEST_NULL;
1935 case OP_X86_PUSH_MEMBASE:
1936 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1937 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1938 ins->inst_basereg == last_ins->inst_destbasereg &&
1939 ins->inst_offset == last_ins->inst_offset) {
1940 ins->opcode = OP_X86_PUSH;
1941 ins->sreg1 = last_ins->sreg1;
1946 mono_peephole_ins (bb, ins);
1951 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1955 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1956 switch (ins->opcode) {
1958 /* reg = 0 -> XOR (reg, reg) */
1959 /* XOR sets cflags on x86, so we cant do it always */
1960 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1963 ins->opcode = OP_IXOR;
1964 ins->sreg1 = ins->dreg;
1965 ins->sreg2 = ins->dreg;
1968 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1969 * since it takes 3 bytes instead of 7.
1971 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
1972 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1973 ins2->opcode = OP_STORE_MEMBASE_REG;
1974 ins2->sreg1 = ins->dreg;
1976 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1977 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1978 ins2->sreg1 = ins->dreg;
1980 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1981 /* Continue iteration */
1990 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1991 ins->opcode = OP_X86_INC_REG;
1995 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1996 ins->opcode = OP_X86_DEC_REG;
2000 mono_peephole_ins (bb, ins);
2005 * mono_arch_lowering_pass:
2007 * Converts complex opcodes into simpler ones so that each IR instruction
2008 * corresponds to one machine instruction.
2011 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2013 MonoInst *ins, *next;
2016 * FIXME: Need to add more instructions, but the current machine
2017 * description can't model some parts of the composite instructions like
2020 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2021 switch (ins->opcode) {
2024 case OP_IDIV_UN_IMM:
2025 case OP_IREM_UN_IMM:
2027 * Keep the cases where we could generated optimized code, otherwise convert
2028 * to the non-imm variant.
2030 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2032 mono_decompose_op_imm (cfg, bb, ins);
2039 bb->max_vreg = cfg->next_vreg;
2043 branch_cc_table [] = {
2044 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2045 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2046 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2049 /* Maps CMP_... constants to X86_CC_... constants */
2052 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2053 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2057 cc_signed_table [] = {
2058 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2059 FALSE, FALSE, FALSE, FALSE
2062 static unsigned char*
2063 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2065 #define XMM_TEMP_REG 0
2066 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2067 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2068 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2069 /* optimize by assigning a local var for this use so we avoid
2070 * the stack manipulations */
2071 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2072 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2073 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2074 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2075 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2077 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2079 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2082 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2083 x86_fnstcw_membase(code, X86_ESP, 0);
2084 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2085 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2086 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2087 x86_fldcw_membase (code, X86_ESP, 2);
2089 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2090 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2091 x86_pop_reg (code, dreg);
2092 /* FIXME: need the high register
2093 * x86_pop_reg (code, dreg_high);
2096 x86_push_reg (code, X86_EAX); // SP = SP - 4
2097 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2098 x86_pop_reg (code, dreg);
2100 x86_fldcw_membase (code, X86_ESP, 0);
2101 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2104 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2106 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2110 static unsigned char*
2111 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2113 int sreg = tree->sreg1;
2114 int need_touch = FALSE;
2116 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2125 * If requested stack size is larger than one page,
2126 * perform stack-touch operation
2129 * Generate stack probe code.
2130 * Under Windows, it is necessary to allocate one page at a time,
2131 * "touching" stack after each successful sub-allocation. This is
2132 * because of the way stack growth is implemented - there is a
2133 * guard page before the lowest stack page that is currently commited.
2134 * Stack normally grows sequentially so OS traps access to the
2135 * guard page and commits more pages when needed.
2137 x86_test_reg_imm (code, sreg, ~0xFFF);
2138 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2140 br[2] = code; /* loop */
2141 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2142 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2145 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2146 * that follows only initializes the last part of the area.
2148 /* Same as the init code below with size==0x1000 */
2149 if (tree->flags & MONO_INST_INIT) {
2150 x86_push_reg (code, X86_EAX);
2151 x86_push_reg (code, X86_ECX);
2152 x86_push_reg (code, X86_EDI);
2153 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2154 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2155 if (cfg->param_area)
2156 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2158 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2160 x86_prefix (code, X86_REP_PREFIX);
2162 x86_pop_reg (code, X86_EDI);
2163 x86_pop_reg (code, X86_ECX);
2164 x86_pop_reg (code, X86_EAX);
2167 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2168 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2169 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2170 x86_patch (br[3], br[2]);
2171 x86_test_reg_reg (code, sreg, sreg);
2172 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2173 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2175 br[1] = code; x86_jump8 (code, 0);
2177 x86_patch (br[0], code);
2178 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2179 x86_patch (br[1], code);
2180 x86_patch (br[4], code);
2183 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2185 if (tree->flags & MONO_INST_INIT) {
2187 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2188 x86_push_reg (code, X86_EAX);
2191 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2192 x86_push_reg (code, X86_ECX);
2195 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2196 x86_push_reg (code, X86_EDI);
2200 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2201 if (sreg != X86_ECX)
2202 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2203 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2205 if (cfg->param_area)
2206 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2208 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2210 x86_prefix (code, X86_REP_PREFIX);
2213 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2214 x86_pop_reg (code, X86_EDI);
2215 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2216 x86_pop_reg (code, X86_ECX);
2217 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2218 x86_pop_reg (code, X86_EAX);
2225 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2227 /* Move return value to the target register */
2228 switch (ins->opcode) {
2231 case OP_CALL_MEMBASE:
2232 if (ins->dreg != X86_EAX)
2233 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2243 static int tls_gs_offset;
2247 mono_x86_have_tls_get (void)
2250 static gboolean have_tls_get = FALSE;
2251 static gboolean inited = FALSE;
2254 return have_tls_get;
2256 #ifdef MONO_HAVE_FAST_TLS
2259 ins = (guint32*)pthread_getspecific;
2261 * We're looking for these two instructions:
2263 * mov 0x4(%esp),%eax
2264 * mov %gs:[offset](,%eax,4),%eax
2266 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2267 tls_gs_offset = ins [2];
2272 return have_tls_get;
2273 #elif defined(TARGET_ANDROID)
2281 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2283 #if defined(__APPLE__)
2284 x86_prefix (code, X86_GS_PREFIX);
2285 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2286 #elif defined(TARGET_WIN32)
2287 g_assert_not_reached ();
2289 x86_prefix (code, X86_GS_PREFIX);
2290 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2296 * mono_x86_emit_tls_get:
2297 * @code: buffer to store code to
2298 * @dreg: hard register where to place the result
2299 * @tls_offset: offset info
2301 * mono_x86_emit_tls_get emits in @code the native code that puts in
2302 * the dreg register the item in the thread local storage identified
2305 * Returns: a pointer to the end of the stored code
2308 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2310 #if defined(__APPLE__)
2311 x86_prefix (code, X86_GS_PREFIX);
2312 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2313 #elif defined(TARGET_WIN32)
2315 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2316 * Journal and/or a disassembly of the TlsGet () function.
2318 x86_prefix (code, X86_FS_PREFIX);
2319 x86_mov_reg_mem (code, dreg, 0x18, 4);
2320 if (tls_offset < 64) {
2321 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2325 g_assert (tls_offset < 0x440);
2326 /* Load TEB->TlsExpansionSlots */
2327 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2328 x86_test_reg_reg (code, dreg, dreg);
2330 x86_branch (code, X86_CC_EQ, code, TRUE);
2331 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2332 x86_patch (buf [0], code);
2335 if (optimize_for_xen) {
2336 x86_prefix (code, X86_GS_PREFIX);
2337 x86_mov_reg_mem (code, dreg, 0, 4);
2338 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2340 x86_prefix (code, X86_GS_PREFIX);
2341 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2348 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2350 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2351 #if defined(__APPLE__) || defined(__linux__)
2352 if (dreg != offset_reg)
2353 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2354 x86_prefix (code, X86_GS_PREFIX);
2355 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2357 g_assert_not_reached ();
2363 mono_x86_emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2365 return emit_tls_get_reg (code, dreg, offset_reg);
2369 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2371 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2373 g_assert_not_reached ();
2374 #elif defined(__APPLE__) || defined(__linux__)
2375 x86_prefix (code, X86_GS_PREFIX);
2376 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2378 g_assert_not_reached ();
2384 * mono_arch_translate_tls_offset:
2386 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2389 mono_arch_translate_tls_offset (int offset)
2392 return tls_gs_offset + (offset * 4);
2401 * Emit code to initialize an LMF structure at LMF_OFFSET.
2404 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2406 /* save all caller saved regs */
2407 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2408 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2409 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2410 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2411 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2412 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2413 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2415 /* save the current IP */
2416 if (cfg->compile_aot) {
2417 /* This pushes the current ip */
2418 x86_call_imm (code, 0);
2419 x86_pop_reg (code, X86_EAX);
2421 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2422 x86_mov_reg_imm (code, X86_EAX, 0);
2424 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2426 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2427 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2428 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2429 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2430 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2431 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2432 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2433 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2434 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2439 /* benchmark and set based on cpu */
2440 #define LOOP_ALIGNMENT 8
2441 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2445 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2450 guint8 *code = cfg->native_code + cfg->code_len;
2453 if (cfg->opt & MONO_OPT_LOOP) {
2454 int pad, align = LOOP_ALIGNMENT;
2455 /* set alignment depending on cpu */
2456 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2458 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2459 x86_padding (code, pad);
2460 cfg->code_len += pad;
2461 bb->native_offset = cfg->code_len;
2465 if (cfg->verbose_level > 2)
2466 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2468 cpos = bb->max_offset;
2470 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
2471 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2472 g_assert (!cfg->compile_aot);
2475 cov->data [bb->dfn].cil_code = bb->cil_code;
2476 /* this is not thread save, but good enough */
2477 x86_inc_mem (code, &cov->data [bb->dfn].count);
2480 offset = code - cfg->native_code;
2482 mono_debug_open_block (cfg, bb, offset);
2484 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2485 x86_breakpoint (code);
2487 MONO_BB_FOR_EACH_INS (bb, ins) {
2488 offset = code - cfg->native_code;
2490 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2492 #define EXTRA_CODE_SPACE (16)
2494 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2495 cfg->code_size *= 2;
2496 cfg->native_code = mono_realloc_native_code(cfg);
2497 code = cfg->native_code + offset;
2498 cfg->stat_code_reallocs++;
2501 if (cfg->debug_info)
2502 mono_debug_record_line_number (cfg, ins, offset);
2504 switch (ins->opcode) {
2506 x86_mul_reg (code, ins->sreg2, TRUE);
2509 x86_mul_reg (code, ins->sreg2, FALSE);
2511 case OP_X86_SETEQ_MEMBASE:
2512 case OP_X86_SETNE_MEMBASE:
2513 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2514 ins->inst_basereg, ins->inst_offset, TRUE);
2516 case OP_STOREI1_MEMBASE_IMM:
2517 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2519 case OP_STOREI2_MEMBASE_IMM:
2520 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2522 case OP_STORE_MEMBASE_IMM:
2523 case OP_STOREI4_MEMBASE_IMM:
2524 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2526 case OP_STOREI1_MEMBASE_REG:
2527 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2529 case OP_STOREI2_MEMBASE_REG:
2530 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2532 case OP_STORE_MEMBASE_REG:
2533 case OP_STOREI4_MEMBASE_REG:
2534 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2536 case OP_STORE_MEM_IMM:
2537 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2540 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2544 /* These are created by the cprop pass so they use inst_imm as the source */
2545 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2548 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2551 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2553 case OP_LOAD_MEMBASE:
2554 case OP_LOADI4_MEMBASE:
2555 case OP_LOADU4_MEMBASE:
2556 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2558 case OP_LOADU1_MEMBASE:
2559 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2561 case OP_LOADI1_MEMBASE:
2562 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2564 case OP_LOADU2_MEMBASE:
2565 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2567 case OP_LOADI2_MEMBASE:
2568 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2570 case OP_ICONV_TO_I1:
2572 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2574 case OP_ICONV_TO_I2:
2576 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2578 case OP_ICONV_TO_U1:
2579 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2581 case OP_ICONV_TO_U2:
2582 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2586 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2588 case OP_COMPARE_IMM:
2589 case OP_ICOMPARE_IMM:
2590 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2592 case OP_X86_COMPARE_MEMBASE_REG:
2593 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2595 case OP_X86_COMPARE_MEMBASE_IMM:
2596 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2598 case OP_X86_COMPARE_MEMBASE8_IMM:
2599 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2601 case OP_X86_COMPARE_REG_MEMBASE:
2602 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2604 case OP_X86_COMPARE_MEM_IMM:
2605 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2607 case OP_X86_TEST_NULL:
2608 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2610 case OP_X86_ADD_MEMBASE_IMM:
2611 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2613 case OP_X86_ADD_REG_MEMBASE:
2614 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2616 case OP_X86_SUB_MEMBASE_IMM:
2617 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2619 case OP_X86_SUB_REG_MEMBASE:
2620 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2622 case OP_X86_AND_MEMBASE_IMM:
2623 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2625 case OP_X86_OR_MEMBASE_IMM:
2626 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2628 case OP_X86_XOR_MEMBASE_IMM:
2629 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2631 case OP_X86_ADD_MEMBASE_REG:
2632 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2634 case OP_X86_SUB_MEMBASE_REG:
2635 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2637 case OP_X86_AND_MEMBASE_REG:
2638 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2640 case OP_X86_OR_MEMBASE_REG:
2641 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2643 case OP_X86_XOR_MEMBASE_REG:
2644 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2646 case OP_X86_INC_MEMBASE:
2647 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2649 case OP_X86_INC_REG:
2650 x86_inc_reg (code, ins->dreg);
2652 case OP_X86_DEC_MEMBASE:
2653 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2655 case OP_X86_DEC_REG:
2656 x86_dec_reg (code, ins->dreg);
2658 case OP_X86_MUL_REG_MEMBASE:
2659 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2661 case OP_X86_AND_REG_MEMBASE:
2662 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2664 case OP_X86_OR_REG_MEMBASE:
2665 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2667 case OP_X86_XOR_REG_MEMBASE:
2668 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2671 x86_breakpoint (code);
2673 case OP_RELAXED_NOP:
2674 x86_prefix (code, X86_REP_PREFIX);
2682 case OP_DUMMY_STORE:
2683 case OP_DUMMY_ICONST:
2684 case OP_DUMMY_R8CONST:
2685 case OP_NOT_REACHED:
2688 case OP_IL_SEQ_POINT:
2689 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2691 case OP_SEQ_POINT: {
2694 if (cfg->compile_aot)
2697 /* Have to use ecx as a temp reg since this can occur after OP_SETRET */
2700 * We do this _before_ the breakpoint, so single stepping after
2701 * a breakpoint is hit will step to the next IL offset.
2703 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
2704 MonoInst *var = cfg->arch.ss_tramp_var;
2708 g_assert (var->opcode == OP_REGOFFSET);
2709 /* Load ss_tramp_var */
2710 /* This is equal to &ss_trampoline */
2711 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, sizeof (mgreg_t));
2712 x86_alu_membase_imm (code, X86_CMP, X86_ECX, 0, 0);
2713 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2714 x86_call_membase (code, X86_ECX, 0);
2715 x86_patch (br [0], code);
2719 * Many parts of sdb depend on the ip after the single step trampoline call to be equal to the seq point offset.
2720 * This means we have to put the loading of bp_tramp_var after the offset.
2723 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2725 MonoInst *var = cfg->arch.bp_tramp_var;
2728 g_assert (var->opcode == OP_REGOFFSET);
2729 /* Load the address of the bp trampoline */
2730 /* This needs to be constant size */
2731 guint8 *start = code;
2732 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, 4);
2733 if (code < start + OP_SEQ_POINT_BP_OFFSET) {
2734 int size = start + OP_SEQ_POINT_BP_OFFSET - code;
2735 x86_padding (code, size);
2738 * A placeholder for a possible breakpoint inserted by
2739 * mono_arch_set_breakpoint ().
2741 for (i = 0; i < 2; ++i)
2744 * Add an additional nop so skipping the bp doesn't cause the ip to point
2745 * to another IL offset.
2753 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2757 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2762 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2766 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2771 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2775 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2780 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2784 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2787 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2791 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2796 * The code is the same for div/rem, the allocator will allocate dreg
2797 * to RAX/RDX as appropriate.
2799 if (ins->sreg2 == X86_EDX) {
2800 /* cdq clobbers this */
2801 x86_push_reg (code, ins->sreg2);
2803 x86_div_membase (code, X86_ESP, 0, TRUE);
2804 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2807 x86_div_reg (code, ins->sreg2, TRUE);
2812 if (ins->sreg2 == X86_EDX) {
2813 x86_push_reg (code, ins->sreg2);
2814 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2815 x86_div_membase (code, X86_ESP, 0, FALSE);
2816 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2818 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2819 x86_div_reg (code, ins->sreg2, FALSE);
2823 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2825 x86_div_reg (code, ins->sreg2, TRUE);
2828 int power = mono_is_power_of_two (ins->inst_imm);
2830 g_assert (ins->sreg1 == X86_EAX);
2831 g_assert (ins->dreg == X86_EAX);
2832 g_assert (power >= 0);
2835 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2837 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2839 * If the divident is >= 0, this does not nothing. If it is positive, it
2840 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2842 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2843 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2844 } else if (power == 0) {
2845 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2847 /* Based on gcc code */
2849 /* Add compensation for negative dividents */
2851 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2852 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2853 /* Compute remainder */
2854 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2855 /* Remove compensation */
2856 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2861 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2865 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2868 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2872 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2875 g_assert (ins->sreg2 == X86_ECX);
2876 x86_shift_reg (code, X86_SHL, ins->dreg);
2879 g_assert (ins->sreg2 == X86_ECX);
2880 x86_shift_reg (code, X86_SAR, ins->dreg);
2884 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2887 case OP_ISHR_UN_IMM:
2888 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2891 g_assert (ins->sreg2 == X86_ECX);
2892 x86_shift_reg (code, X86_SHR, ins->dreg);
2896 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2899 guint8 *jump_to_end;
2901 /* handle shifts below 32 bits */
2902 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2903 x86_shift_reg (code, X86_SHL, ins->sreg1);
2905 x86_test_reg_imm (code, X86_ECX, 32);
2906 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2908 /* handle shift over 32 bit */
2909 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2910 x86_clear_reg (code, ins->sreg1);
2912 x86_patch (jump_to_end, code);
2916 guint8 *jump_to_end;
2918 /* handle shifts below 32 bits */
2919 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2920 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2922 x86_test_reg_imm (code, X86_ECX, 32);
2923 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2925 /* handle shifts over 31 bits */
2926 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2927 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2929 x86_patch (jump_to_end, code);
2933 guint8 *jump_to_end;
2935 /* handle shifts below 32 bits */
2936 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2937 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2939 x86_test_reg_imm (code, X86_ECX, 32);
2940 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2942 /* handle shifts over 31 bits */
2943 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2944 x86_clear_reg (code, ins->backend.reg3);
2946 x86_patch (jump_to_end, code);
2950 if (ins->inst_imm >= 32) {
2951 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2952 x86_clear_reg (code, ins->sreg1);
2953 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2955 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2956 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2960 if (ins->inst_imm >= 32) {
2961 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2962 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2963 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2965 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2966 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2969 case OP_LSHR_UN_IMM:
2970 if (ins->inst_imm >= 32) {
2971 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2972 x86_clear_reg (code, ins->backend.reg3);
2973 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2975 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2976 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2980 x86_not_reg (code, ins->sreg1);
2983 x86_neg_reg (code, ins->sreg1);
2987 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2991 switch (ins->inst_imm) {
2995 if (ins->dreg != ins->sreg1)
2996 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2997 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3000 /* LEA r1, [r2 + r2*2] */
3001 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3004 /* LEA r1, [r2 + r2*4] */
3005 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3008 /* LEA r1, [r2 + r2*2] */
3010 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3011 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3014 /* LEA r1, [r2 + r2*8] */
3015 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3018 /* LEA r1, [r2 + r2*4] */
3020 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3021 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3024 /* LEA r1, [r2 + r2*2] */
3026 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3027 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3030 /* LEA r1, [r2 + r2*4] */
3031 /* LEA r1, [r1 + r1*4] */
3032 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3033 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3036 /* LEA r1, [r2 + r2*4] */
3038 /* LEA r1, [r1 + r1*4] */
3039 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3040 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3041 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3044 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3049 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3050 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3052 case OP_IMUL_OVF_UN: {
3053 /* the mul operation and the exception check should most likely be split */
3054 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3055 /*g_assert (ins->sreg2 == X86_EAX);
3056 g_assert (ins->dreg == X86_EAX);*/
3057 if (ins->sreg2 == X86_EAX) {
3058 non_eax_reg = ins->sreg1;
3059 } else if (ins->sreg1 == X86_EAX) {
3060 non_eax_reg = ins->sreg2;
3062 /* no need to save since we're going to store to it anyway */
3063 if (ins->dreg != X86_EAX) {
3065 x86_push_reg (code, X86_EAX);
3067 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3068 non_eax_reg = ins->sreg2;
3070 if (ins->dreg == X86_EDX) {
3073 x86_push_reg (code, X86_EAX);
3077 x86_push_reg (code, X86_EDX);
3079 x86_mul_reg (code, non_eax_reg, FALSE);
3080 /* save before the check since pop and mov don't change the flags */
3081 if (ins->dreg != X86_EAX)
3082 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3084 x86_pop_reg (code, X86_EDX);
3086 x86_pop_reg (code, X86_EAX);
3087 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3091 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3094 g_assert_not_reached ();
3095 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3096 x86_mov_reg_imm (code, ins->dreg, 0);
3099 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3100 x86_mov_reg_imm (code, ins->dreg, 0);
3102 case OP_LOAD_GOTADDR:
3103 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3104 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3107 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3108 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3110 case OP_X86_PUSH_GOT_ENTRY:
3111 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3112 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3115 if (ins->dreg != ins->sreg1)
3116 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3119 MonoCallInst *call = (MonoCallInst*)ins;
3122 ins->flags |= MONO_INST_GC_CALLSITE;
3123 ins->backend.pc_offset = code - cfg->native_code;
3125 /* reset offset to make max_len work */
3126 offset = code - cfg->native_code;
3128 g_assert (!cfg->method->save_lmf);
3130 /* restore callee saved registers */
3131 for (i = 0; i < X86_NREG; ++i)
3132 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3134 if (cfg->used_int_regs & (1 << X86_ESI)) {
3135 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3138 if (cfg->used_int_regs & (1 << X86_EDI)) {
3139 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3142 if (cfg->used_int_regs & (1 << X86_EBX)) {
3143 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3147 /* Copy arguments on the stack to our argument area */
3148 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3149 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3150 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3153 /* restore ESP/EBP */
3155 offset = code - cfg->native_code;
3156 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3157 x86_jump32 (code, 0);
3159 ins->flags |= MONO_INST_GC_CALLSITE;
3160 cfg->disable_aot = TRUE;
3164 /* ensure ins->sreg1 is not NULL
3165 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3166 * cmp DWORD PTR [eax], 0
3168 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3171 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3172 x86_push_reg (code, hreg);
3173 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3174 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3175 x86_pop_reg (code, hreg);
3188 case OP_VOIDCALL_REG:
3190 case OP_FCALL_MEMBASE:
3191 case OP_LCALL_MEMBASE:
3192 case OP_VCALL_MEMBASE:
3193 case OP_VCALL2_MEMBASE:
3194 case OP_VOIDCALL_MEMBASE:
3195 case OP_CALL_MEMBASE: {
3198 call = (MonoCallInst*)ins;
3199 cinfo = (CallInfo*)call->call_info;
3201 switch (ins->opcode) {
3208 if (ins->flags & MONO_INST_HAS_METHOD)
3209 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3211 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3217 case OP_VOIDCALL_REG:
3219 x86_call_reg (code, ins->sreg1);
3221 case OP_FCALL_MEMBASE:
3222 case OP_LCALL_MEMBASE:
3223 case OP_VCALL_MEMBASE:
3224 case OP_VCALL2_MEMBASE:
3225 case OP_VOIDCALL_MEMBASE:
3226 case OP_CALL_MEMBASE:
3227 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3230 g_assert_not_reached ();
3233 ins->flags |= MONO_INST_GC_CALLSITE;
3234 ins->backend.pc_offset = code - cfg->native_code;
3235 if (cinfo->callee_stack_pop) {
3236 /* Have to compensate for the stack space popped by the callee */
3237 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3239 code = emit_move_return_value (cfg, ins, code);
3243 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3245 case OP_X86_LEA_MEMBASE:
3246 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3249 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3252 /* keep alignment */
3253 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3254 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3255 code = mono_emit_stack_alloc (cfg, code, ins);
3256 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3257 if (cfg->param_area)
3258 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3260 case OP_LOCALLOC_IMM: {
3261 guint32 size = ins->inst_imm;
3262 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3264 if (ins->flags & MONO_INST_INIT) {
3265 /* FIXME: Optimize this */
3266 x86_mov_reg_imm (code, ins->dreg, size);
3267 ins->sreg1 = ins->dreg;
3269 code = mono_emit_stack_alloc (cfg, code, ins);
3270 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3272 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3273 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3275 if (cfg->param_area)
3276 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3280 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3281 x86_push_reg (code, ins->sreg1);
3282 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3283 (gpointer)"mono_arch_throw_exception");
3284 ins->flags |= MONO_INST_GC_CALLSITE;
3285 ins->backend.pc_offset = code - cfg->native_code;
3289 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3290 x86_push_reg (code, ins->sreg1);
3291 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3292 (gpointer)"mono_arch_rethrow_exception");
3293 ins->flags |= MONO_INST_GC_CALLSITE;
3294 ins->backend.pc_offset = code - cfg->native_code;
3297 case OP_CALL_HANDLER:
3298 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3299 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3300 x86_call_imm (code, 0);
3301 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3302 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3304 case OP_START_HANDLER: {
3305 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3306 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3307 if (cfg->param_area)
3308 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3311 case OP_ENDFINALLY: {
3312 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3313 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3317 case OP_ENDFILTER: {
3318 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3319 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3320 /* The local allocator will put the result into EAX */
3325 if (ins->dreg != X86_EAX)
3326 x86_mov_reg_reg (code, ins->dreg, X86_EAX, sizeof (gpointer));
3330 ins->inst_c0 = code - cfg->native_code;
3333 if (ins->inst_target_bb->native_offset) {
3334 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3336 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3337 if ((cfg->opt & MONO_OPT_BRANCH) &&
3338 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3339 x86_jump8 (code, 0);
3341 x86_jump32 (code, 0);
3345 x86_jump_reg (code, ins->sreg1);
3364 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3365 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3367 case OP_COND_EXC_EQ:
3368 case OP_COND_EXC_NE_UN:
3369 case OP_COND_EXC_LT:
3370 case OP_COND_EXC_LT_UN:
3371 case OP_COND_EXC_GT:
3372 case OP_COND_EXC_GT_UN:
3373 case OP_COND_EXC_GE:
3374 case OP_COND_EXC_GE_UN:
3375 case OP_COND_EXC_LE:
3376 case OP_COND_EXC_LE_UN:
3377 case OP_COND_EXC_IEQ:
3378 case OP_COND_EXC_INE_UN:
3379 case OP_COND_EXC_ILT:
3380 case OP_COND_EXC_ILT_UN:
3381 case OP_COND_EXC_IGT:
3382 case OP_COND_EXC_IGT_UN:
3383 case OP_COND_EXC_IGE:
3384 case OP_COND_EXC_IGE_UN:
3385 case OP_COND_EXC_ILE:
3386 case OP_COND_EXC_ILE_UN:
3387 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3389 case OP_COND_EXC_OV:
3390 case OP_COND_EXC_NO:
3392 case OP_COND_EXC_NC:
3393 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3395 case OP_COND_EXC_IOV:
3396 case OP_COND_EXC_INO:
3397 case OP_COND_EXC_IC:
3398 case OP_COND_EXC_INC:
3399 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3411 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3419 case OP_CMOV_INE_UN:
3420 case OP_CMOV_IGE_UN:
3421 case OP_CMOV_IGT_UN:
3422 case OP_CMOV_ILE_UN:
3423 case OP_CMOV_ILT_UN:
3424 g_assert (ins->dreg == ins->sreg1);
3425 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3428 /* floating point opcodes */
3430 double d = *(double *)ins->inst_p0;
3432 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3434 } else if (d == 1.0) {
3437 if (cfg->compile_aot) {
3438 guint32 *val = (guint32*)&d;
3439 x86_push_imm (code, val [1]);
3440 x86_push_imm (code, val [0]);
3441 x86_fld_membase (code, X86_ESP, 0, TRUE);
3442 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3445 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3446 x86_fld (code, NULL, TRUE);
3452 float f = *(float *)ins->inst_p0;
3454 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3456 } else if (f == 1.0) {
3459 if (cfg->compile_aot) {
3460 guint32 val = *(guint32*)&f;
3461 x86_push_imm (code, val);
3462 x86_fld_membase (code, X86_ESP, 0, FALSE);
3463 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3466 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3467 x86_fld (code, NULL, FALSE);
3472 case OP_STORER8_MEMBASE_REG:
3473 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3475 case OP_LOADR8_MEMBASE:
3476 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3478 case OP_STORER4_MEMBASE_REG:
3479 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3481 case OP_LOADR4_MEMBASE:
3482 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3484 case OP_ICONV_TO_R4:
3485 x86_push_reg (code, ins->sreg1);
3486 x86_fild_membase (code, X86_ESP, 0, FALSE);
3487 /* Change precision */
3488 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3489 x86_fld_membase (code, X86_ESP, 0, FALSE);
3490 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3492 case OP_ICONV_TO_R8:
3493 x86_push_reg (code, ins->sreg1);
3494 x86_fild_membase (code, X86_ESP, 0, FALSE);
3495 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3497 case OP_ICONV_TO_R_UN:
3498 x86_push_imm (code, 0);
3499 x86_push_reg (code, ins->sreg1);
3500 x86_fild_membase (code, X86_ESP, 0, TRUE);
3501 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3503 case OP_X86_FP_LOAD_I8:
3504 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3506 case OP_X86_FP_LOAD_I4:
3507 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3509 case OP_FCONV_TO_R4:
3510 /* Change precision */
3511 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3512 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3513 x86_fld_membase (code, X86_ESP, 0, FALSE);
3514 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3516 case OP_FCONV_TO_I1:
3517 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3519 case OP_FCONV_TO_U1:
3520 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3522 case OP_FCONV_TO_I2:
3523 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3525 case OP_FCONV_TO_U2:
3526 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3528 case OP_FCONV_TO_I4:
3530 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3532 case OP_FCONV_TO_I8:
3533 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3534 x86_fnstcw_membase(code, X86_ESP, 0);
3535 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3536 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3537 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3538 x86_fldcw_membase (code, X86_ESP, 2);
3539 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3540 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3541 x86_pop_reg (code, ins->dreg);
3542 x86_pop_reg (code, ins->backend.reg3);
3543 x86_fldcw_membase (code, X86_ESP, 0);
3544 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3546 case OP_LCONV_TO_R8_2:
3547 x86_push_reg (code, ins->sreg2);
3548 x86_push_reg (code, ins->sreg1);
3549 x86_fild_membase (code, X86_ESP, 0, TRUE);
3550 /* Change precision */
3551 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3552 x86_fld_membase (code, X86_ESP, 0, TRUE);
3553 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3555 case OP_LCONV_TO_R4_2:
3556 x86_push_reg (code, ins->sreg2);
3557 x86_push_reg (code, ins->sreg1);
3558 x86_fild_membase (code, X86_ESP, 0, TRUE);
3559 /* Change precision */
3560 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3561 x86_fld_membase (code, X86_ESP, 0, FALSE);
3562 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3564 case OP_LCONV_TO_R_UN_2: {
3565 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3568 /* load 64bit integer to FP stack */
3569 x86_push_reg (code, ins->sreg2);
3570 x86_push_reg (code, ins->sreg1);
3571 x86_fild_membase (code, X86_ESP, 0, TRUE);
3573 /* test if lreg is negative */
3574 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3575 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3577 /* add correction constant mn */
3578 if (cfg->compile_aot) {
3579 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3580 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3581 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3582 x86_fld80_membase (code, X86_ESP, 2);
3583 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3585 x86_fld80_mem (code, mn);
3587 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3589 x86_patch (br, code);
3591 /* Change precision */
3592 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3593 x86_fld_membase (code, X86_ESP, 0, TRUE);
3595 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3599 case OP_LCONV_TO_OVF_I:
3600 case OP_LCONV_TO_OVF_I4_2: {
3601 guint8 *br [3], *label [1];
3605 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3607 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3609 /* If the low word top bit is set, see if we are negative */
3610 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3611 /* We are not negative (no top bit set, check for our top word to be zero */
3612 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3613 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3616 /* throw exception */
3617 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3619 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3620 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3621 x86_jump8 (code, 0);
3623 x86_jump32 (code, 0);
3625 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3626 x86_jump32 (code, 0);
3630 x86_patch (br [0], code);
3631 /* our top bit is set, check that top word is 0xfffffff */
3632 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3634 x86_patch (br [1], code);
3635 /* nope, emit exception */
3636 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3637 x86_patch (br [2], label [0]);
3639 if (ins->dreg != ins->sreg1)
3640 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3644 /* Not needed on the fp stack */
3646 case OP_MOVE_F_TO_I4:
3647 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
3648 x86_mov_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, 4);
3650 case OP_MOVE_I4_TO_F:
3651 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
3652 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
3655 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3658 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3661 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3664 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3672 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3677 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3684 * it really doesn't make sense to inline all this code,
3685 * it's here just to show that things may not be as simple
3688 guchar *check_pos, *end_tan, *pop_jump;
3689 x86_push_reg (code, X86_EAX);
3692 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3694 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3695 x86_fstp (code, 0); /* pop the 1.0 */
3697 x86_jump8 (code, 0);
3699 x86_fp_op (code, X86_FADD, 0);
3703 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3705 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3708 x86_patch (pop_jump, code);
3709 x86_fstp (code, 0); /* pop the 1.0 */
3710 x86_patch (check_pos, code);
3711 x86_patch (end_tan, code);
3713 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3714 x86_pop_reg (code, X86_EAX);
3721 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3730 g_assert (cfg->opt & MONO_OPT_CMOV);
3731 g_assert (ins->dreg == ins->sreg1);
3732 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3733 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3736 g_assert (cfg->opt & MONO_OPT_CMOV);
3737 g_assert (ins->dreg == ins->sreg1);
3738 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3739 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3742 g_assert (cfg->opt & MONO_OPT_CMOV);
3743 g_assert (ins->dreg == ins->sreg1);
3744 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3745 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3748 g_assert (cfg->opt & MONO_OPT_CMOV);
3749 g_assert (ins->dreg == ins->sreg1);
3750 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3751 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3757 x86_fxch (code, ins->inst_imm);
3762 x86_push_reg (code, X86_EAX);
3763 /* we need to exchange ST(0) with ST(1) */
3766 /* this requires a loop, because fprem somtimes
3767 * returns a partial remainder */
3769 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3770 /* x86_fprem1 (code); */
3773 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3775 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3781 x86_pop_reg (code, X86_EAX);
3785 if (cfg->opt & MONO_OPT_FCMOV) {
3786 x86_fcomip (code, 1);
3790 /* this overwrites EAX */
3791 EMIT_FPCOMPARE(code);
3792 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3796 if (cfg->opt & MONO_OPT_FCMOV) {
3797 /* zeroing the register at the start results in
3798 * shorter and faster code (we can also remove the widening op)
3800 guchar *unordered_check;
3801 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3802 x86_fcomip (code, 1);
3804 unordered_check = code;
3805 x86_branch8 (code, X86_CC_P, 0, FALSE);
3806 if (ins->opcode == OP_FCEQ) {
3807 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3808 x86_patch (unordered_check, code);
3810 guchar *jump_to_end;
3811 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3813 x86_jump8 (code, 0);
3814 x86_patch (unordered_check, code);
3815 x86_inc_reg (code, ins->dreg);
3816 x86_patch (jump_to_end, code);
3821 if (ins->dreg != X86_EAX)
3822 x86_push_reg (code, X86_EAX);
3824 EMIT_FPCOMPARE(code);
3825 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3826 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3827 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3828 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3830 if (ins->dreg != X86_EAX)
3831 x86_pop_reg (code, X86_EAX);
3835 if (cfg->opt & MONO_OPT_FCMOV) {
3836 /* zeroing the register at the start results in
3837 * shorter and faster code (we can also remove the widening op)
3839 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3840 x86_fcomip (code, 1);
3842 if (ins->opcode == OP_FCLT_UN) {
3843 guchar *unordered_check = code;
3844 guchar *jump_to_end;
3845 x86_branch8 (code, X86_CC_P, 0, FALSE);
3846 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3848 x86_jump8 (code, 0);
3849 x86_patch (unordered_check, code);
3850 x86_inc_reg (code, ins->dreg);
3851 x86_patch (jump_to_end, code);
3853 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3857 if (ins->dreg != X86_EAX)
3858 x86_push_reg (code, X86_EAX);
3860 EMIT_FPCOMPARE(code);
3861 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3862 if (ins->opcode == OP_FCLT_UN) {
3863 guchar *is_not_zero_check, *end_jump;
3864 is_not_zero_check = code;
3865 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3867 x86_jump8 (code, 0);
3868 x86_patch (is_not_zero_check, code);
3869 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3871 x86_patch (end_jump, code);
3873 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3874 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3876 if (ins->dreg != X86_EAX)
3877 x86_pop_reg (code, X86_EAX);
3880 guchar *unordered_check;
3881 guchar *jump_to_end;
3882 if (cfg->opt & MONO_OPT_FCMOV) {
3883 /* zeroing the register at the start results in
3884 * shorter and faster code (we can also remove the widening op)
3886 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3887 x86_fcomip (code, 1);
3889 unordered_check = code;
3890 x86_branch8 (code, X86_CC_P, 0, FALSE);
3891 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3892 x86_patch (unordered_check, code);
3895 if (ins->dreg != X86_EAX)
3896 x86_push_reg (code, X86_EAX);
3898 EMIT_FPCOMPARE(code);
3899 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3900 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3901 unordered_check = code;
3902 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3904 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3905 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3906 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3908 x86_jump8 (code, 0);
3909 x86_patch (unordered_check, code);
3910 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3911 x86_patch (jump_to_end, code);
3913 if (ins->dreg != X86_EAX)
3914 x86_pop_reg (code, X86_EAX);
3919 if (cfg->opt & MONO_OPT_FCMOV) {
3920 /* zeroing the register at the start results in
3921 * shorter and faster code (we can also remove the widening op)
3923 guchar *unordered_check;
3924 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3925 x86_fcomip (code, 1);
3927 if (ins->opcode == OP_FCGT) {
3928 unordered_check = code;
3929 x86_branch8 (code, X86_CC_P, 0, FALSE);
3930 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3931 x86_patch (unordered_check, code);
3933 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3937 if (ins->dreg != X86_EAX)
3938 x86_push_reg (code, X86_EAX);
3940 EMIT_FPCOMPARE(code);
3941 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3942 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3943 if (ins->opcode == OP_FCGT_UN) {
3944 guchar *is_not_zero_check, *end_jump;
3945 is_not_zero_check = code;
3946 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3948 x86_jump8 (code, 0);
3949 x86_patch (is_not_zero_check, code);
3950 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3952 x86_patch (end_jump, code);
3954 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3955 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3957 if (ins->dreg != X86_EAX)
3958 x86_pop_reg (code, X86_EAX);
3961 guchar *unordered_check;
3962 guchar *jump_to_end;
3963 if (cfg->opt & MONO_OPT_FCMOV) {
3964 /* zeroing the register at the start results in
3965 * shorter and faster code (we can also remove the widening op)
3967 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3968 x86_fcomip (code, 1);
3970 unordered_check = code;
3971 x86_branch8 (code, X86_CC_P, 0, FALSE);
3972 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
3973 x86_patch (unordered_check, code);
3976 if (ins->dreg != X86_EAX)
3977 x86_push_reg (code, X86_EAX);
3979 EMIT_FPCOMPARE(code);
3980 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3981 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3982 unordered_check = code;
3983 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3985 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3986 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
3987 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3989 x86_jump8 (code, 0);
3990 x86_patch (unordered_check, code);
3991 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3992 x86_patch (jump_to_end, code);
3994 if (ins->dreg != X86_EAX)
3995 x86_pop_reg (code, X86_EAX);
3999 if (cfg->opt & MONO_OPT_FCMOV) {
4000 guchar *jump = code;
4001 x86_branch8 (code, X86_CC_P, 0, TRUE);
4002 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4003 x86_patch (jump, code);
4006 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4007 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4010 /* Branch if C013 != 100 */
4011 if (cfg->opt & MONO_OPT_FCMOV) {
4012 /* branch if !ZF or (PF|CF) */
4013 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4014 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4015 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4018 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4019 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4022 if (cfg->opt & MONO_OPT_FCMOV) {
4023 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4026 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4029 if (cfg->opt & MONO_OPT_FCMOV) {
4030 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4031 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4034 if (ins->opcode == OP_FBLT_UN) {
4035 guchar *is_not_zero_check, *end_jump;
4036 is_not_zero_check = code;
4037 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4039 x86_jump8 (code, 0);
4040 x86_patch (is_not_zero_check, code);
4041 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4043 x86_patch (end_jump, code);
4045 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4049 if (cfg->opt & MONO_OPT_FCMOV) {
4050 if (ins->opcode == OP_FBGT) {
4053 /* skip branch if C1=1 */
4055 x86_branch8 (code, X86_CC_P, 0, FALSE);
4056 /* branch if (C0 | C3) = 1 */
4057 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4058 x86_patch (br1, code);
4060 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4064 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4065 if (ins->opcode == OP_FBGT_UN) {
4066 guchar *is_not_zero_check, *end_jump;
4067 is_not_zero_check = code;
4068 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4070 x86_jump8 (code, 0);
4071 x86_patch (is_not_zero_check, code);
4072 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4074 x86_patch (end_jump, code);
4076 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4079 /* Branch if C013 == 100 or 001 */
4080 if (cfg->opt & MONO_OPT_FCMOV) {
4083 /* skip branch if C1=1 */
4085 x86_branch8 (code, X86_CC_P, 0, FALSE);
4086 /* branch if (C0 | C3) = 1 */
4087 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4088 x86_patch (br1, code);
4091 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4092 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4093 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4094 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4097 /* Branch if C013 == 000 */
4098 if (cfg->opt & MONO_OPT_FCMOV) {
4099 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4102 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4105 /* Branch if C013=000 or 100 */
4106 if (cfg->opt & MONO_OPT_FCMOV) {
4109 /* skip branch if C1=1 */
4111 x86_branch8 (code, X86_CC_P, 0, FALSE);
4112 /* branch if C0=0 */
4113 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4114 x86_patch (br1, code);
4117 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4118 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4119 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4122 /* Branch if C013 != 001 */
4123 if (cfg->opt & MONO_OPT_FCMOV) {
4124 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4125 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4128 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4129 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4133 x86_push_reg (code, X86_EAX);
4136 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4137 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4138 x86_pop_reg (code, X86_EAX);
4140 /* Have to clean up the fp stack before throwing the exception */
4142 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4145 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
4147 x86_patch (br1, code);
4151 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4154 case OP_TLS_GET_REG: {
4155 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4159 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4162 case OP_TLS_SET_REG: {
4163 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4166 case OP_MEMORY_BARRIER: {
4167 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4168 x86_prefix (code, X86_LOCK_PREFIX);
4169 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4173 case OP_ATOMIC_ADD_I4: {
4174 int dreg = ins->dreg;
4176 g_assert (cfg->has_atomic_add_i4);
4178 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4179 if (ins->sreg2 == dreg) {
4180 if (dreg == X86_EBX) {
4182 if (ins->inst_basereg == X86_EDI)
4186 if (ins->inst_basereg == X86_EBX)
4189 } else if (ins->inst_basereg == dreg) {
4190 if (dreg == X86_EBX) {
4192 if (ins->sreg2 == X86_EDI)
4196 if (ins->sreg2 == X86_EBX)
4201 if (dreg != ins->dreg) {
4202 x86_push_reg (code, dreg);
4205 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4206 x86_prefix (code, X86_LOCK_PREFIX);
4207 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4208 /* dreg contains the old value, add with sreg2 value */
4209 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4211 if (ins->dreg != dreg) {
4212 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4213 x86_pop_reg (code, dreg);
4218 case OP_ATOMIC_EXCHANGE_I4: {
4220 int sreg2 = ins->sreg2;
4221 int breg = ins->inst_basereg;
4223 g_assert (cfg->has_atomic_exchange_i4);
4225 /* cmpxchg uses eax as comperand, need to make sure we can use it
4226 * hack to overcome limits in x86 reg allocator
4227 * (req: dreg == eax and sreg2 != eax and breg != eax)
4229 g_assert (ins->dreg == X86_EAX);
4231 /* We need the EAX reg for the cmpxchg */
4232 if (ins->sreg2 == X86_EAX) {
4233 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4234 x86_push_reg (code, sreg2);
4235 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4238 if (breg == X86_EAX) {
4239 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4240 x86_push_reg (code, breg);
4241 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4244 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4246 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4247 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4248 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4249 x86_patch (br [1], br [0]);
4251 if (breg != ins->inst_basereg)
4252 x86_pop_reg (code, breg);
4254 if (ins->sreg2 != sreg2)
4255 x86_pop_reg (code, sreg2);
4259 case OP_ATOMIC_CAS_I4: {
4260 g_assert (ins->dreg == X86_EAX);
4261 g_assert (ins->sreg3 == X86_EAX);
4262 g_assert (ins->sreg1 != X86_EAX);
4263 g_assert (ins->sreg1 != ins->sreg2);
4265 x86_prefix (code, X86_LOCK_PREFIX);
4266 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4269 case OP_ATOMIC_LOAD_I1: {
4270 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4273 case OP_ATOMIC_LOAD_U1: {
4274 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4277 case OP_ATOMIC_LOAD_I2: {
4278 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4281 case OP_ATOMIC_LOAD_U2: {
4282 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4285 case OP_ATOMIC_LOAD_I4:
4286 case OP_ATOMIC_LOAD_U4: {
4287 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4290 case OP_ATOMIC_LOAD_R4:
4291 case OP_ATOMIC_LOAD_R8: {
4292 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4295 case OP_ATOMIC_STORE_I1:
4296 case OP_ATOMIC_STORE_U1:
4297 case OP_ATOMIC_STORE_I2:
4298 case OP_ATOMIC_STORE_U2:
4299 case OP_ATOMIC_STORE_I4:
4300 case OP_ATOMIC_STORE_U4: {
4303 switch (ins->opcode) {
4304 case OP_ATOMIC_STORE_I1:
4305 case OP_ATOMIC_STORE_U1:
4308 case OP_ATOMIC_STORE_I2:
4309 case OP_ATOMIC_STORE_U2:
4312 case OP_ATOMIC_STORE_I4:
4313 case OP_ATOMIC_STORE_U4:
4318 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4320 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4324 case OP_ATOMIC_STORE_R4:
4325 case OP_ATOMIC_STORE_R8: {
4326 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4328 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4332 case OP_CARD_TABLE_WBARRIER: {
4333 int ptr = ins->sreg1;
4334 int value = ins->sreg2;
4336 int nursery_shift, card_table_shift;
4337 gpointer card_table_mask;
4338 size_t nursery_size;
4339 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4340 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4341 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4344 * We need one register we can clobber, we choose EDX and make sreg1
4345 * fixed EAX to work around limitations in the local register allocator.
4346 * sreg2 might get allocated to EDX, but that is not a problem since
4347 * we use it before clobbering EDX.
4349 g_assert (ins->sreg1 == X86_EAX);
4352 * This is the code we produce:
4355 * edx >>= nursery_shift
4356 * cmp edx, (nursery_start >> nursery_shift)
4359 * edx >>= card_table_shift
4360 * card_table[edx] = 1
4364 if (card_table_nursery_check) {
4365 if (value != X86_EDX)
4366 x86_mov_reg_reg (code, X86_EDX, value, 4);
4367 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4368 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4369 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4371 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4372 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4373 if (card_table_mask)
4374 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4375 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4376 if (card_table_nursery_check)
4377 x86_patch (br, code);
4380 #ifdef MONO_ARCH_SIMD_INTRINSICS
4382 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4385 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4388 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4391 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4394 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4397 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4400 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4401 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4404 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4407 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4410 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4413 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4416 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4419 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4422 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4425 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4428 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4431 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4434 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4437 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4440 case OP_PSHUFLEW_HIGH:
4441 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4442 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4444 case OP_PSHUFLEW_LOW:
4445 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4446 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4449 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4450 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4453 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4454 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4457 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4458 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4462 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4465 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4468 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4471 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4474 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4477 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4480 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4481 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4484 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4487 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4490 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4493 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4496 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4499 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4502 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4505 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4508 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4511 case OP_EXTRACT_MASK:
4512 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4516 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4519 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4522 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4526 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4529 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4532 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4535 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4539 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4542 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4545 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4548 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4552 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4555 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4558 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4562 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4565 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4568 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4572 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4575 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4579 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4582 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4585 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4589 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4592 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4595 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4599 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4602 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4605 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4608 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4612 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4615 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4618 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4621 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4624 case OP_PSUM_ABS_DIFF:
4625 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4628 case OP_UNPACK_LOWB:
4629 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4631 case OP_UNPACK_LOWW:
4632 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4634 case OP_UNPACK_LOWD:
4635 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4637 case OP_UNPACK_LOWQ:
4638 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4640 case OP_UNPACK_LOWPS:
4641 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4643 case OP_UNPACK_LOWPD:
4644 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4647 case OP_UNPACK_HIGHB:
4648 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4650 case OP_UNPACK_HIGHW:
4651 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4653 case OP_UNPACK_HIGHD:
4654 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4656 case OP_UNPACK_HIGHQ:
4657 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4659 case OP_UNPACK_HIGHPS:
4660 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4662 case OP_UNPACK_HIGHPD:
4663 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4667 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4670 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4673 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4676 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4679 case OP_PADDB_SAT_UN:
4680 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4682 case OP_PSUBB_SAT_UN:
4683 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4685 case OP_PADDW_SAT_UN:
4686 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4688 case OP_PSUBW_SAT_UN:
4689 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4693 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4696 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4699 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4702 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4706 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4709 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4712 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4714 case OP_PMULW_HIGH_UN:
4715 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4718 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4722 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4725 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4729 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4732 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4736 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4739 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4743 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4746 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4750 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4753 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4757 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4760 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4764 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4767 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4771 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4774 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4778 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4781 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4785 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4787 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4788 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4792 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4794 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4795 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4799 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4801 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4802 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4806 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4808 case OP_EXTRACTX_U2:
4809 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4811 case OP_INSERTX_U1_SLOW:
4812 /*sreg1 is the extracted ireg (scratch)
4813 /sreg2 is the to be inserted ireg (scratch)
4814 /dreg is the xreg to receive the value*/
4816 /*clear the bits from the extracted word*/
4817 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4818 /*shift the value to insert if needed*/
4819 if (ins->inst_c0 & 1)
4820 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4821 /*join them together*/
4822 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4823 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4825 case OP_INSERTX_I4_SLOW:
4826 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4827 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4828 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4831 case OP_INSERTX_R4_SLOW:
4832 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4833 /*TODO if inst_c0 == 0 use movss*/
4834 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4835 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4837 case OP_INSERTX_R8_SLOW:
4838 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4839 if (cfg->verbose_level)
4840 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4842 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4844 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4847 case OP_STOREX_MEMBASE_REG:
4848 case OP_STOREX_MEMBASE:
4849 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4851 case OP_LOADX_MEMBASE:
4852 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4854 case OP_LOADX_ALIGNED_MEMBASE:
4855 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4857 case OP_STOREX_ALIGNED_MEMBASE_REG:
4858 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4860 case OP_STOREX_NTA_MEMBASE_REG:
4861 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4863 case OP_PREFETCH_MEMBASE:
4864 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4868 /*FIXME the peephole pass should have killed this*/
4869 if (ins->dreg != ins->sreg1)
4870 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4873 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4876 case OP_FCONV_TO_R8_X:
4877 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4878 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4881 case OP_XCONV_R8_TO_I4:
4882 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4883 switch (ins->backend.source_opcode) {
4884 case OP_FCONV_TO_I1:
4885 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4887 case OP_FCONV_TO_U1:
4888 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4890 case OP_FCONV_TO_I2:
4891 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4893 case OP_FCONV_TO_U2:
4894 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4900 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4901 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4902 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4903 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4904 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4905 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4908 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4909 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4910 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4913 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4914 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4917 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4918 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4919 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4922 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4923 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4924 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4928 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4931 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4934 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4937 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4940 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4943 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4946 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4949 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4953 case OP_LIVERANGE_START: {
4954 if (cfg->verbose_level > 1)
4955 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4956 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4959 case OP_LIVERANGE_END: {
4960 if (cfg->verbose_level > 1)
4961 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4962 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4965 case OP_GC_SAFE_POINT: {
4968 g_assert (mono_threads_is_coop_enabled ());
4970 x86_test_membase_imm (code, ins->sreg1, 0, 1);
4971 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4972 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
4973 x86_patch (br [0], code);
4977 case OP_GC_LIVENESS_DEF:
4978 case OP_GC_LIVENESS_USE:
4979 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4980 ins->backend.pc_offset = code - cfg->native_code;
4982 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4983 ins->backend.pc_offset = code - cfg->native_code;
4984 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4987 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
4990 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
4993 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4994 g_assert_not_reached ();
4997 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4998 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4999 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5000 g_assert_not_reached ();
5006 cfg->code_len = code - cfg->native_code;
5009 #endif /* DISABLE_JIT */
5012 mono_arch_register_lowlevel_calls (void)
5017 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5019 unsigned char *ip = ji->ip.i + code;
5022 case MONO_PATCH_INFO_IP:
5023 *((gconstpointer *)(ip)) = target;
5025 case MONO_PATCH_INFO_ABS:
5026 case MONO_PATCH_INFO_METHOD:
5027 case MONO_PATCH_INFO_METHOD_JUMP:
5028 case MONO_PATCH_INFO_INTERNAL_METHOD:
5029 case MONO_PATCH_INFO_BB:
5030 case MONO_PATCH_INFO_LABEL:
5031 case MONO_PATCH_INFO_RGCTX_FETCH:
5032 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5033 x86_patch (ip, (unsigned char*)target);
5035 case MONO_PATCH_INFO_NONE:
5037 case MONO_PATCH_INFO_R4:
5038 case MONO_PATCH_INFO_R8: {
5039 guint32 offset = mono_arch_get_patch_offset (ip);
5040 *((gconstpointer *)(ip + offset)) = target;
5044 guint32 offset = mono_arch_get_patch_offset (ip);
5045 *((gconstpointer *)(ip + offset)) = target;
5051 static G_GNUC_UNUSED void
5052 stack_unaligned (MonoMethod *m, gpointer caller)
5054 printf ("%s\n", mono_method_full_name (m, TRUE));
5055 g_assert_not_reached ();
5059 mono_arch_emit_prolog (MonoCompile *cfg)
5061 MonoMethod *method = cfg->method;
5063 MonoMethodSignature *sig;
5067 int alloc_size, pos, max_offset, i, cfa_offset;
5069 gboolean need_stack_frame;
5071 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5073 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5074 cfg->code_size += 512;
5076 code = cfg->native_code = g_malloc (cfg->code_size);
5082 /* Check that the stack is aligned on osx */
5083 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5084 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5085 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5087 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5088 x86_push_membase (code, X86_ESP, 0);
5089 x86_push_imm (code, cfg->method);
5090 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5091 x86_call_reg (code, X86_EAX);
5092 x86_patch (br [0], code);
5096 /* Offset between RSP and the CFA */
5100 cfa_offset = sizeof (gpointer);
5101 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5102 // IP saved at CFA - 4
5103 /* There is no IP reg on x86 */
5104 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5105 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5107 need_stack_frame = needs_stack_frame (cfg);
5109 if (need_stack_frame) {
5110 x86_push_reg (code, X86_EBP);
5111 cfa_offset += sizeof (gpointer);
5112 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5113 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5114 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5115 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5116 /* These are handled automatically by the stack marking code */
5117 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5119 cfg->frame_reg = X86_ESP;
5122 cfg->stack_offset += cfg->param_area;
5123 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5125 alloc_size = cfg->stack_offset;
5128 if (!method->save_lmf) {
5129 if (cfg->used_int_regs & (1 << X86_EBX)) {
5130 x86_push_reg (code, X86_EBX);
5132 cfa_offset += sizeof (gpointer);
5133 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5134 /* These are handled automatically by the stack marking code */
5135 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5138 if (cfg->used_int_regs & (1 << X86_EDI)) {
5139 x86_push_reg (code, X86_EDI);
5141 cfa_offset += sizeof (gpointer);
5142 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5143 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5146 if (cfg->used_int_regs & (1 << X86_ESI)) {
5147 x86_push_reg (code, X86_ESI);
5149 cfa_offset += sizeof (gpointer);
5150 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5151 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5157 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5158 if (mono_do_x86_stack_align && need_stack_frame) {
5159 int tot = alloc_size + pos + 4; /* ret ip */
5160 if (need_stack_frame)
5162 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5164 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5165 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5166 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5170 cfg->arch.sp_fp_offset = alloc_size + pos;
5173 /* See mono_emit_stack_alloc */
5174 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5175 guint32 remaining_size = alloc_size;
5176 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5177 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5178 guint32 offset = code - cfg->native_code;
5179 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5180 while (required_code_size >= (cfg->code_size - offset))
5181 cfg->code_size *= 2;
5182 cfg->native_code = mono_realloc_native_code(cfg);
5183 code = cfg->native_code + offset;
5184 cfg->stat_code_reallocs++;
5186 while (remaining_size >= 0x1000) {
5187 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5188 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5189 remaining_size -= 0x1000;
5192 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5194 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5197 g_assert (need_stack_frame);
5200 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5201 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5202 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5205 #if DEBUG_STACK_ALIGNMENT
5206 /* check the stack is aligned */
5207 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5208 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5209 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5210 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5211 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5212 x86_breakpoint (code);
5216 /* compute max_offset in order to use short forward jumps */
5218 if (cfg->opt & MONO_OPT_BRANCH) {
5219 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5221 bb->max_offset = max_offset;
5223 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5225 /* max alignment for loops */
5226 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5227 max_offset += LOOP_ALIGNMENT;
5228 MONO_BB_FOR_EACH_INS (bb, ins) {
5229 if (ins->opcode == OP_LABEL)
5230 ins->inst_c1 = max_offset;
5231 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5236 /* store runtime generic context */
5237 if (cfg->rgctx_var) {
5238 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5240 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5243 if (method->save_lmf)
5244 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5246 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5247 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5252 if (cfg->arch.ss_tramp_var) {
5253 /* Initialize ss_tramp_var */
5254 ins = cfg->arch.ss_tramp_var;
5255 g_assert (ins->opcode == OP_REGOFFSET);
5257 g_assert (!cfg->compile_aot);
5258 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&ss_trampoline, 4);
5261 if (cfg->arch.bp_tramp_var) {
5262 /* Initialize bp_tramp_var */
5263 ins = cfg->arch.bp_tramp_var;
5264 g_assert (ins->opcode == OP_REGOFFSET);
5266 g_assert (!cfg->compile_aot);
5267 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&bp_trampoline, 4);
5271 /* load arguments allocated to register from the stack */
5272 sig = mono_method_signature (method);
5275 cinfo = (CallInfo *)cfg->arch.cinfo;
5277 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5278 inst = cfg->args [pos];
5279 ainfo = &cinfo->args [pos];
5280 if (inst->opcode == OP_REGVAR) {
5281 g_assert (need_stack_frame);
5282 x86_mov_reg_membase (code, inst->dreg, X86_EBP, ainfo->offset + ARGS_OFFSET, 4);
5283 if (cfg->verbose_level > 2)
5284 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5289 cfg->code_len = code - cfg->native_code;
5291 g_assert (cfg->code_len < cfg->code_size);
5297 mono_arch_emit_epilog (MonoCompile *cfg)
5299 MonoMethod *method = cfg->method;
5300 MonoMethodSignature *sig = mono_method_signature (method);
5302 guint32 stack_to_pop;
5304 int max_epilog_size = 16;
5306 gboolean need_stack_frame = needs_stack_frame (cfg);
5308 if (cfg->method->save_lmf)
5309 max_epilog_size += 128;
5311 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5312 cfg->code_size *= 2;
5313 cfg->native_code = mono_realloc_native_code(cfg);
5314 cfg->stat_code_reallocs++;
5317 code = cfg->native_code + cfg->code_len;
5319 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5320 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5322 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5325 if (method->save_lmf) {
5326 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5328 gboolean supported = FALSE;
5330 if (cfg->compile_aot) {
5331 #if defined(MONO_HAVE_FAST_TLS)
5334 } else if (mono_get_jit_tls_offset () != -1) {
5338 /* check if we need to restore protection of the stack after a stack overflow */
5340 if (cfg->compile_aot) {
5341 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5343 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5345 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5348 /* we load the value in a separate instruction: this mechanism may be
5349 * used later as a safer way to do thread interruption
5351 x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5352 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5354 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5355 /* note that the call trampoline will preserve eax/edx */
5356 x86_call_reg (code, X86_ECX);
5357 x86_patch (patch, code);
5359 /* FIXME: maybe save the jit tls in the prolog */
5362 /* restore caller saved regs */
5363 if (cfg->used_int_regs & (1 << X86_EBX)) {
5364 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5367 if (cfg->used_int_regs & (1 << X86_EDI)) {
5368 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5370 if (cfg->used_int_regs & (1 << X86_ESI)) {
5371 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5374 /* EBP is restored by LEAVE */
5376 for (i = 0; i < X86_NREG; ++i) {
5377 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5383 g_assert (need_stack_frame);
5384 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5388 g_assert (need_stack_frame);
5389 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5392 if (cfg->used_int_regs & (1 << X86_ESI)) {
5393 x86_pop_reg (code, X86_ESI);
5395 if (cfg->used_int_regs & (1 << X86_EDI)) {
5396 x86_pop_reg (code, X86_EDI);
5398 if (cfg->used_int_regs & (1 << X86_EBX)) {
5399 x86_pop_reg (code, X86_EBX);
5403 /* Load returned vtypes into registers if needed */
5404 cinfo = (CallInfo *)cfg->arch.cinfo;
5405 if (cinfo->ret.storage == ArgValuetypeInReg) {
5406 for (quad = 0; quad < 2; quad ++) {
5407 switch (cinfo->ret.pair_storage [quad]) {
5409 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5411 case ArgOnFloatFpStack:
5412 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5414 case ArgOnDoubleFpStack:
5415 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5420 g_assert_not_reached ();
5425 if (need_stack_frame)
5428 if (CALLCONV_IS_STDCALL (sig)) {
5429 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5431 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
5432 } else if (cinfo->callee_stack_pop)
5433 stack_to_pop = cinfo->callee_stack_pop;
5438 g_assert (need_stack_frame);
5439 x86_ret_imm (code, stack_to_pop);
5444 cfg->code_len = code - cfg->native_code;
5446 g_assert (cfg->code_len < cfg->code_size);
5450 mono_arch_emit_exceptions (MonoCompile *cfg)
5452 MonoJumpInfo *patch_info;
5455 MonoClass *exc_classes [16];
5456 guint8 *exc_throw_start [16], *exc_throw_end [16];
5460 /* Compute needed space */
5461 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5462 if (patch_info->type == MONO_PATCH_INFO_EXC)
5467 * make sure we have enough space for exceptions
5468 * 16 is the size of two push_imm instructions and a call
5470 if (cfg->compile_aot)
5471 code_size = exc_count * 32;
5473 code_size = exc_count * 16;
5475 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5476 cfg->code_size *= 2;
5477 cfg->native_code = mono_realloc_native_code(cfg);
5478 cfg->stat_code_reallocs++;
5481 code = cfg->native_code + cfg->code_len;
5484 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5485 switch (patch_info->type) {
5486 case MONO_PATCH_INFO_EXC: {
5487 MonoClass *exc_class;
5491 x86_patch (patch_info->ip.i + cfg->native_code, code);
5493 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5494 throw_ip = patch_info->ip.i;
5496 /* Find a throw sequence for the same exception class */
5497 for (i = 0; i < nthrows; ++i)
5498 if (exc_classes [i] == exc_class)
5501 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5502 x86_jump_code (code, exc_throw_start [i]);
5503 patch_info->type = MONO_PATCH_INFO_NONE;
5508 /* Compute size of code following the push <OFFSET> */
5511 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5513 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5514 /* Use the shorter form */
5516 x86_push_imm (code, 0);
5520 x86_push_imm (code, 0xf0f0f0f0);
5525 exc_classes [nthrows] = exc_class;
5526 exc_throw_start [nthrows] = code;
5529 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5530 patch_info->data.name = "mono_arch_throw_corlib_exception";
5531 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5532 patch_info->ip.i = code - cfg->native_code;
5533 x86_call_code (code, 0);
5534 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5539 exc_throw_end [nthrows] = code;
5551 cfg->code_len = code - cfg->native_code;
5553 g_assert (cfg->code_len < cfg->code_size);
5557 mono_arch_flush_icache (guint8 *code, gint size)
5563 mono_arch_flush_register_windows (void)
5568 mono_arch_is_inst_imm (gint64 imm)
5574 mono_arch_finish_init (void)
5576 if (!g_getenv ("MONO_NO_TLS")) {
5577 #ifndef TARGET_WIN32
5579 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5586 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5590 // Linear handler, the bsearch head compare is shorter
5591 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5592 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5593 // x86_patch(ins,target)
5594 //[1 + 5] x86_jump_mem(inst,mem)
5597 #define BR_SMALL_SIZE 2
5598 #define BR_LARGE_SIZE 5
5599 #define JUMP_IMM_SIZE 6
5600 #define ENABLE_WRONG_METHOD_CHECK 0
5604 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5606 int i, distance = 0;
5607 for (i = start; i < target; ++i)
5608 distance += imt_entries [i]->chunk_size;
5613 * LOCKING: called with the domain lock held
5616 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5617 gpointer fail_tramp)
5621 guint8 *code, *start;
5624 for (i = 0; i < count; ++i) {
5625 MonoIMTCheckItem *item = imt_entries [i];
5626 if (item->is_equals) {
5627 if (item->check_target_idx) {
5628 if (!item->compare_done)
5629 item->chunk_size += CMP_SIZE;
5630 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5633 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5635 item->chunk_size += JUMP_IMM_SIZE;
5636 #if ENABLE_WRONG_METHOD_CHECK
5637 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5642 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5643 imt_entries [item->check_target_idx]->compare_done = TRUE;
5645 size += item->chunk_size;
5648 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5650 code = mono_domain_code_reserve (domain, size);
5653 unwind_ops = mono_arch_get_cie_program ();
5655 for (i = 0; i < count; ++i) {
5656 MonoIMTCheckItem *item = imt_entries [i];
5657 item->code_target = code;
5658 if (item->is_equals) {
5659 if (item->check_target_idx) {
5660 if (!item->compare_done)
5661 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5662 item->jmp_code = code;
5663 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5664 if (item->has_target_code)
5665 x86_jump_code (code, item->value.target_code);
5667 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5670 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5671 item->jmp_code = code;
5672 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5673 if (item->has_target_code)
5674 x86_jump_code (code, item->value.target_code);
5676 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5677 x86_patch (item->jmp_code, code);
5678 x86_jump_code (code, fail_tramp);
5679 item->jmp_code = NULL;
5681 /* enable the commented code to assert on wrong method */
5682 #if ENABLE_WRONG_METHOD_CHECK
5683 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5684 item->jmp_code = code;
5685 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5687 if (item->has_target_code)
5688 x86_jump_code (code, item->value.target_code);
5690 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5691 #if ENABLE_WRONG_METHOD_CHECK
5692 x86_patch (item->jmp_code, code);
5693 x86_breakpoint (code);
5694 item->jmp_code = NULL;
5699 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5700 item->jmp_code = code;
5701 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5702 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5704 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5707 /* patch the branches to get to the target items */
5708 for (i = 0; i < count; ++i) {
5709 MonoIMTCheckItem *item = imt_entries [i];
5710 if (item->jmp_code) {
5711 if (item->check_target_idx) {
5712 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5718 mono_stats.imt_thunks_size += code - start;
5719 g_assert (code - start <= size);
5723 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5724 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5728 if (mono_jit_map_is_enabled ()) {
5731 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5733 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5734 mono_emit_jit_tramp (start, code - start, buff);
5738 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
5740 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
5746 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5748 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5752 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5754 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5758 mono_arch_get_cie_program (void)
5762 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5763 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5769 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5771 MonoInst *ins = NULL;
5774 if (cmethod->klass == mono_defaults.math_class) {
5775 if (strcmp (cmethod->name, "Sin") == 0) {
5777 } else if (strcmp (cmethod->name, "Cos") == 0) {
5779 } else if (strcmp (cmethod->name, "Tan") == 0) {
5781 } else if (strcmp (cmethod->name, "Atan") == 0) {
5783 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5785 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5787 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5791 if (opcode && fsig->param_count == 1) {
5792 MONO_INST_NEW (cfg, ins, opcode);
5793 ins->type = STACK_R8;
5794 ins->dreg = mono_alloc_freg (cfg);
5795 ins->sreg1 = args [0]->dreg;
5796 MONO_ADD_INS (cfg->cbb, ins);
5799 if (cfg->opt & MONO_OPT_CMOV) {
5802 if (strcmp (cmethod->name, "Min") == 0) {
5803 if (fsig->params [0]->type == MONO_TYPE_I4)
5805 } else if (strcmp (cmethod->name, "Max") == 0) {
5806 if (fsig->params [0]->type == MONO_TYPE_I4)
5810 if (opcode && fsig->param_count == 2) {
5811 MONO_INST_NEW (cfg, ins, opcode);
5812 ins->type = STACK_I4;
5813 ins->dreg = mono_alloc_ireg (cfg);
5814 ins->sreg1 = args [0]->dreg;
5815 ins->sreg2 = args [1]->dreg;
5816 MONO_ADD_INS (cfg->cbb, ins);
5821 /* OP_FREM is not IEEE compatible */
5822 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
5823 MONO_INST_NEW (cfg, ins, OP_FREM);
5824 ins->inst_i0 = args [0];
5825 ins->inst_i1 = args [1];
5834 mono_arch_print_tree (MonoInst *tree, int arity)
5840 mono_arch_get_patch_offset (guint8 *code)
5842 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5844 else if (code [0] == 0xba)
5846 else if (code [0] == 0x68)
5849 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5850 /* push <OFFSET>(<REG>) */
5852 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5853 /* call *<OFFSET>(<REG>) */
5855 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5858 else if ((code [0] == 0x58) && (code [1] == 0x05))
5859 /* pop %eax; add <OFFSET>, %eax */
5861 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5862 /* pop <REG>; add <OFFSET>, <REG> */
5864 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5865 /* mov <REG>, imm */
5868 g_assert_not_reached ();
5874 * mono_breakpoint_clean_code:
5876 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5877 * breakpoints in the original code, they are removed in the copy.
5879 * Returns TRUE if no sw breakpoint was present.
5882 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5885 * If method_start is non-NULL we need to perform bound checks, since we access memory
5886 * at code - offset we could go before the start of the method and end up in a different
5887 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5890 if (!method_start || code - offset >= method_start) {
5891 memcpy (buf, code - offset, size);
5893 int diff = code - method_start;
5894 memset (buf, 0, size);
5895 memcpy (buf + offset - diff, method_start, diff + size - offset);
5901 * mono_x86_get_this_arg_offset:
5903 * Return the offset of the stack location where this is passed during a virtual
5907 mono_x86_get_this_arg_offset (MonoMethodSignature *sig)
5913 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
5915 guint32 esp = regs [X86_ESP];
5922 * The stack looks like:
5926 res = ((MonoObject**)esp) [0];
5930 #define MAX_ARCH_DELEGATE_PARAMS 10
5933 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
5935 guint8 *code, *start;
5936 int code_reserve = 64;
5939 unwind_ops = mono_arch_get_cie_program ();
5942 * The stack contains:
5948 start = code = mono_global_codeman_reserve (code_reserve);
5950 /* Replace the this argument with the target */
5951 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5952 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
5953 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5954 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
5956 g_assert ((code - start) < code_reserve);
5959 /* 8 for mov_reg and jump, plus 8 for each parameter */
5960 code_reserve = 8 + (param_count * 8);
5962 * The stack contains:
5963 * <args in reverse order>
5968 * <args in reverse order>
5971 * without unbalancing the stack.
5972 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
5973 * and leaving original spot of first arg as placeholder in stack so
5974 * when callee pops stack everything works.
5977 start = code = mono_global_codeman_reserve (code_reserve);
5979 /* store delegate for access to method_ptr */
5980 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
5983 for (i = 0; i < param_count; ++i) {
5984 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
5985 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
5988 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
5990 g_assert ((code - start) < code_reserve);
5994 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
5996 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
5997 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
6001 if (mono_jit_map_is_enabled ()) {
6004 buff = (char*)"delegate_invoke_has_target";
6006 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6007 mono_emit_jit_tramp (start, code - start, buff);
6011 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6016 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
6019 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
6021 guint8 *code, *start;
6026 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
6030 * The stack contains:
6034 start = code = mono_global_codeman_reserve (size);
6036 unwind_ops = mono_arch_get_cie_program ();
6038 /* Replace the this argument with the target */
6039 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6040 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6041 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6044 /* Load the IMT reg */
6045 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
6048 /* Load the vtable */
6049 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
6050 x86_jump_membase (code, X86_EAX, offset);
6051 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6053 tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
6054 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
6055 g_free (tramp_name);
6062 mono_arch_get_delegate_invoke_impls (void)
6065 MonoTrampInfo *info;
6068 get_delegate_invoke_impl (&info, TRUE, 0);
6069 res = g_slist_prepend (res, info);
6071 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
6072 get_delegate_invoke_impl (&info, FALSE, i);
6073 res = g_slist_prepend (res, info);
6076 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
6077 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
6078 res = g_slist_prepend (res, info);
6080 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
6081 res = g_slist_prepend (res, info);
6088 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6090 guint8 *code, *start;
6092 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6095 /* FIXME: Support more cases */
6096 if (MONO_TYPE_ISSTRUCT (sig->ret))
6100 * The stack contains:
6106 static guint8* cached = NULL;
6110 if (mono_aot_only) {
6111 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6113 MonoTrampInfo *info;
6114 start = get_delegate_invoke_impl (&info, TRUE, 0);
6115 mono_tramp_info_register (info, NULL);
6118 mono_memory_barrier ();
6122 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6125 for (i = 0; i < sig->param_count; ++i)
6126 if (!mono_is_regsize_var (sig->params [i]))
6129 code = cache [sig->param_count];
6133 if (mono_aot_only) {
6134 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6135 start = mono_aot_get_trampoline (name);
6138 MonoTrampInfo *info;
6139 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
6140 mono_tramp_info_register (info, NULL);
6143 mono_memory_barrier ();
6145 cache [sig->param_count] = start;
6152 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
6154 MonoTrampInfo *info;
6157 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
6159 mono_tramp_info_register (info, NULL);
6164 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6167 case X86_EAX: return ctx->eax;
6168 case X86_EBX: return ctx->ebx;
6169 case X86_ECX: return ctx->ecx;
6170 case X86_EDX: return ctx->edx;
6171 case X86_ESP: return ctx->esp;
6172 case X86_EBP: return ctx->ebp;
6173 case X86_ESI: return ctx->esi;
6174 case X86_EDI: return ctx->edi;
6176 g_assert_not_reached ();
6182 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6210 g_assert_not_reached ();
6214 #ifdef MONO_ARCH_SIMD_INTRINSICS
6217 get_float_to_x_spill_area (MonoCompile *cfg)
6219 if (!cfg->fconv_to_r8_x_var) {
6220 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6221 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6223 return cfg->fconv_to_r8_x_var;
6227 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6230 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6233 int dreg, src_opcode;
6235 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6238 switch (src_opcode = ins->opcode) {
6239 case OP_FCONV_TO_I1:
6240 case OP_FCONV_TO_U1:
6241 case OP_FCONV_TO_I2:
6242 case OP_FCONV_TO_U2:
6243 case OP_FCONV_TO_I4:
6250 /* dreg is the IREG and sreg1 is the FREG */
6251 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6252 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6253 fconv->sreg1 = ins->sreg1;
6254 fconv->dreg = mono_alloc_ireg (cfg);
6255 fconv->type = STACK_VTYPE;
6256 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6258 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6262 ins->opcode = OP_XCONV_R8_TO_I4;
6264 ins->klass = mono_defaults.int32_class;
6265 ins->sreg1 = fconv->dreg;
6267 ins->type = STACK_I4;
6268 ins->backend.source_opcode = src_opcode;
6271 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6274 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6279 if (long_ins->opcode == OP_LNEG) {
6281 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
6282 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
6283 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->dreg));
6288 #ifdef MONO_ARCH_SIMD_INTRINSICS
6290 if (!(cfg->opt & MONO_OPT_SIMD))
6293 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6294 switch (long_ins->opcode) {
6296 vreg = long_ins->sreg1;
6298 if (long_ins->inst_c0) {
6299 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6300 ins->klass = long_ins->klass;
6301 ins->sreg1 = long_ins->sreg1;
6303 ins->type = STACK_VTYPE;
6304 ins->dreg = vreg = alloc_ireg (cfg);
6305 MONO_ADD_INS (cfg->cbb, ins);
6308 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6309 ins->klass = mono_defaults.int32_class;
6311 ins->type = STACK_I4;
6312 ins->dreg = MONO_LVREG_LS (long_ins->dreg);
6313 MONO_ADD_INS (cfg->cbb, ins);
6315 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6316 ins->klass = long_ins->klass;
6317 ins->sreg1 = long_ins->sreg1;
6318 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6319 ins->type = STACK_VTYPE;
6320 ins->dreg = vreg = alloc_ireg (cfg);
6321 MONO_ADD_INS (cfg->cbb, ins);
6323 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6324 ins->klass = mono_defaults.int32_class;
6326 ins->type = STACK_I4;
6327 ins->dreg = MONO_LVREG_MS (long_ins->dreg);
6328 MONO_ADD_INS (cfg->cbb, ins);
6330 long_ins->opcode = OP_NOP;
6332 case OP_INSERTX_I8_SLOW:
6333 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6334 ins->dreg = long_ins->dreg;
6335 ins->sreg1 = long_ins->dreg;
6336 ins->sreg2 = MONO_LVREG_LS (long_ins->sreg2);
6337 ins->inst_c0 = long_ins->inst_c0 * 2;
6338 MONO_ADD_INS (cfg->cbb, ins);
6340 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6341 ins->dreg = long_ins->dreg;
6342 ins->sreg1 = long_ins->dreg;
6343 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg2);
6344 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6345 MONO_ADD_INS (cfg->cbb, ins);
6347 long_ins->opcode = OP_NOP;
6350 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6351 ins->dreg = long_ins->dreg;
6352 ins->sreg1 = MONO_LVREG_LS (long_ins->sreg1);
6353 ins->klass = long_ins->klass;
6354 ins->type = STACK_VTYPE;
6355 MONO_ADD_INS (cfg->cbb, ins);
6357 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6358 ins->dreg = long_ins->dreg;
6359 ins->sreg1 = long_ins->dreg;
6360 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg1);
6362 ins->klass = long_ins->klass;
6363 ins->type = STACK_VTYPE;
6364 MONO_ADD_INS (cfg->cbb, ins);
6366 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6367 ins->dreg = long_ins->dreg;
6368 ins->sreg1 = long_ins->dreg;;
6369 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6370 ins->klass = long_ins->klass;
6371 ins->type = STACK_VTYPE;
6372 MONO_ADD_INS (cfg->cbb, ins);
6374 long_ins->opcode = OP_NOP;
6377 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6380 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6382 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6385 gpointer *sp, old_value;
6388 offset = clause->exvar_offset;
6391 bp = MONO_CONTEXT_GET_BP (ctx);
6392 sp = *(gpointer*)(bp + offset);
6395 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6404 * mono_aot_emit_load_got_addr:
6406 * Emit code to load the got address.
6407 * On x86, the result is placed into EBX.
6410 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6412 x86_call_imm (code, 0);
6414 * The patch needs to point to the pop, since the GOT offset needs
6415 * to be added to that address.
6418 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6420 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6421 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6422 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6428 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6431 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6433 g_assert_not_reached ();
6434 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6439 * mono_arch_emit_load_aotconst:
6441 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6442 * TARGET from the mscorlib GOT in full-aot code.
6443 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6447 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
6449 /* Load the mscorlib got address */
6450 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6451 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6452 /* arch_emit_got_access () patches this */
6453 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6458 /* Can't put this into mini-x86.h */
6460 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6463 mono_arch_get_trampolines (gboolean aot)
6465 MonoTrampInfo *info;
6466 GSList *tramps = NULL;
6468 mono_x86_get_signal_exception_trampoline (&info, aot);
6470 tramps = g_slist_append (tramps, info);
6475 /* Soft Debug support */
6476 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6479 * mono_arch_set_breakpoint:
6481 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6482 * The location should contain code emitted by OP_SEQ_POINT.
6485 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6487 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6489 g_assert (code [0] == 0x90);
6490 x86_call_membase (code, X86_ECX, 0);
6494 * mono_arch_clear_breakpoint:
6496 * Clear the breakpoint at IP.
6499 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6501 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6504 for (i = 0; i < 2; ++i)
6509 * mono_arch_start_single_stepping:
6511 * Start single stepping.
6514 mono_arch_start_single_stepping (void)
6516 ss_trampoline = mini_get_single_step_trampoline ();
6520 * mono_arch_stop_single_stepping:
6522 * Stop single stepping.
6525 mono_arch_stop_single_stepping (void)
6527 ss_trampoline = NULL;
6531 * mono_arch_is_single_step_event:
6533 * Return whenever the machine state in SIGCTX corresponds to a single
6537 mono_arch_is_single_step_event (void *info, void *sigctx)
6539 /* We use soft breakpoints */
6544 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6546 /* We use soft breakpoints */
6550 #define BREAKPOINT_SIZE 2
6553 * mono_arch_skip_breakpoint:
6555 * See mini-amd64.c for docs.
6558 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6560 g_assert_not_reached ();
6564 * mono_arch_skip_single_step:
6566 * See mini-amd64.c for docs.
6569 mono_arch_skip_single_step (MonoContext *ctx)
6571 g_assert_not_reached ();
6575 * mono_arch_get_seq_point_info:
6577 * See mini-amd64.c for docs.
6580 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6587 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6589 ext->lmf.previous_lmf = (gsize)prev_lmf;
6590 /* Mark that this is a MonoLMFExt */
6591 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6592 ext->lmf.ebp = (gssize)ext;
6598 mono_arch_opcode_supported (int opcode)
6601 case OP_ATOMIC_ADD_I4:
6602 case OP_ATOMIC_EXCHANGE_I4:
6603 case OP_ATOMIC_CAS_I4:
6604 case OP_ATOMIC_LOAD_I1:
6605 case OP_ATOMIC_LOAD_I2:
6606 case OP_ATOMIC_LOAD_I4:
6607 case OP_ATOMIC_LOAD_U1:
6608 case OP_ATOMIC_LOAD_U2:
6609 case OP_ATOMIC_LOAD_U4:
6610 case OP_ATOMIC_LOAD_R4:
6611 case OP_ATOMIC_LOAD_R8:
6612 case OP_ATOMIC_STORE_I1:
6613 case OP_ATOMIC_STORE_I2:
6614 case OP_ATOMIC_STORE_I4:
6615 case OP_ATOMIC_STORE_U1:
6616 case OP_ATOMIC_STORE_U2:
6617 case OP_ATOMIC_STORE_U4:
6618 case OP_ATOMIC_STORE_R4:
6619 case OP_ATOMIC_STORE_R8:
6627 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
6629 return get_call_info (mp, sig);