2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * (C) 2003 Ximian, Inc.
18 #include <mono/metadata/appdomain.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/metadata/threads.h>
21 #include <mono/metadata/profiler-private.h>
22 #include <mono/metadata/mono-debug.h>
23 #include <mono/utils/mono-math.h>
24 #include <mono/utils/mono-counters.h>
25 #include <mono/utils/mono-mmap.h>
32 /* On windows, these hold the key returned by TlsAlloc () */
33 static gint lmf_tls_offset = -1;
34 static gint lmf_addr_tls_offset = -1;
35 static gint appdomain_tls_offset = -1;
38 static gboolean optimize_for_xen = TRUE;
40 #define optimize_for_xen 0
44 static gboolean is_win32 = TRUE;
46 static gboolean is_win32 = FALSE;
49 /* This mutex protects architecture specific caches */
50 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
51 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
52 static CRITICAL_SECTION mini_arch_mutex;
54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
59 /* Under windows, the default pinvoke calling convention is stdcall */
60 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT))
62 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL)
66 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
69 * The code generated for sequence points reads from this location, which is
70 * made read-only when single stepping is enabled.
72 static gpointer ss_trigger_page;
74 /* Enabled breakpoints read from this trigger page */
75 static gpointer bp_trigger_page;
78 mono_arch_regname (int reg)
81 case X86_EAX: return "%eax";
82 case X86_EBX: return "%ebx";
83 case X86_ECX: return "%ecx";
84 case X86_EDX: return "%edx";
85 case X86_ESP: return "%esp";
86 case X86_EBP: return "%ebp";
87 case X86_EDI: return "%edi";
88 case X86_ESI: return "%esi";
94 mono_arch_fregname (int reg)
119 mono_arch_xregname (int reg)
144 mono_x86_patch (unsigned char* code, gpointer target)
146 x86_patch (code, (unsigned char*)target);
165 /* Only if storage == ArgValuetypeInReg */
166 ArgStorage pair_storage [2];
175 gboolean need_stack_align;
176 guint32 stack_align_amount;
184 #define FLOAT_PARAM_REGS 0
186 static X86_Reg_No param_regs [] = { 0 };
188 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
189 #define SMALL_STRUCTS_IN_REGS
190 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
194 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
196 ainfo->offset = *stack_size;
198 if (*gr >= PARAM_REGS) {
199 ainfo->storage = ArgOnStack;
200 (*stack_size) += sizeof (gpointer);
203 ainfo->storage = ArgInIReg;
204 ainfo->reg = param_regs [*gr];
210 add_general_pair (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
212 ainfo->offset = *stack_size;
214 g_assert (PARAM_REGS == 0);
216 ainfo->storage = ArgOnStack;
217 (*stack_size) += sizeof (gpointer) * 2;
221 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
223 ainfo->offset = *stack_size;
225 if (*gr >= FLOAT_PARAM_REGS) {
226 ainfo->storage = ArgOnStack;
227 (*stack_size) += is_double ? 8 : 4;
230 /* A double register */
232 ainfo->storage = ArgInDoubleSSEReg;
234 ainfo->storage = ArgInFloatSSEReg;
242 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
244 guint32 *gr, guint32 *fr, guint32 *stack_size)
249 klass = mono_class_from_mono_type (type);
250 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
252 #ifdef SMALL_STRUCTS_IN_REGS
253 if (sig->pinvoke && is_return) {
254 MonoMarshalType *info;
257 * the exact rules are not very well documented, the code below seems to work with the
258 * code generated by gcc 3.3.3 -mno-cygwin.
260 info = mono_marshal_load_type_info (klass);
263 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
265 /* Special case structs with only a float member */
266 if ((info->native_size == 8) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R8)) {
267 ainfo->storage = ArgValuetypeInReg;
268 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
271 if ((info->native_size == 4) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R4)) {
272 ainfo->storage = ArgValuetypeInReg;
273 ainfo->pair_storage [0] = ArgOnFloatFpStack;
276 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
277 ainfo->storage = ArgValuetypeInReg;
278 ainfo->pair_storage [0] = ArgInIReg;
279 ainfo->pair_regs [0] = return_regs [0];
280 if (info->native_size > 4) {
281 ainfo->pair_storage [1] = ArgInIReg;
282 ainfo->pair_regs [1] = return_regs [1];
289 ainfo->offset = *stack_size;
290 ainfo->storage = ArgOnStack;
291 *stack_size += ALIGN_TO (size, sizeof (gpointer));
297 * Obtain information about a call according to the calling convention.
298 * For x86 ELF, see the "System V Application Binary Interface Intel386
299 * Architecture Processor Supplment, Fourth Edition" document for more
301 * For x86 win32, see ???.
304 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig, gboolean is_pinvoke)
308 int n = sig->hasthis + sig->param_count;
309 guint32 stack_size = 0;
316 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
317 switch (ret_type->type) {
318 case MONO_TYPE_BOOLEAN:
329 case MONO_TYPE_FNPTR:
330 case MONO_TYPE_CLASS:
331 case MONO_TYPE_OBJECT:
332 case MONO_TYPE_SZARRAY:
333 case MONO_TYPE_ARRAY:
334 case MONO_TYPE_STRING:
335 cinfo->ret.storage = ArgInIReg;
336 cinfo->ret.reg = X86_EAX;
340 cinfo->ret.storage = ArgInIReg;
341 cinfo->ret.reg = X86_EAX;
344 cinfo->ret.storage = ArgOnFloatFpStack;
347 cinfo->ret.storage = ArgOnDoubleFpStack;
349 case MONO_TYPE_GENERICINST:
350 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
351 cinfo->ret.storage = ArgInIReg;
352 cinfo->ret.reg = X86_EAX;
356 case MONO_TYPE_VALUETYPE: {
357 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
359 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
360 if (cinfo->ret.storage == ArgOnStack)
361 /* The caller passes the address where the value is stored */
362 add_general (&gr, &stack_size, &cinfo->ret);
365 case MONO_TYPE_TYPEDBYREF:
366 /* Same as a valuetype with size 24 */
367 add_general (&gr, &stack_size, &cinfo->ret);
371 cinfo->ret.storage = ArgNone;
374 g_error ("Can't handle as return value 0x%x", sig->ret->type);
380 add_general (&gr, &stack_size, cinfo->args + 0);
382 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
384 fr = FLOAT_PARAM_REGS;
386 /* Emit the signature cookie just before the implicit arguments */
387 add_general (&gr, &stack_size, &cinfo->sig_cookie);
390 for (i = 0; i < sig->param_count; ++i) {
391 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
394 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
395 /* We allways pass the sig cookie on the stack for simplicity */
397 * Prevent implicit arguments + the sig cookie from being passed
401 fr = FLOAT_PARAM_REGS;
403 /* Emit the signature cookie just before the implicit arguments */
404 add_general (&gr, &stack_size, &cinfo->sig_cookie);
407 if (sig->params [i]->byref) {
408 add_general (&gr, &stack_size, ainfo);
411 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
412 switch (ptype->type) {
413 case MONO_TYPE_BOOLEAN:
416 add_general (&gr, &stack_size, ainfo);
421 add_general (&gr, &stack_size, ainfo);
425 add_general (&gr, &stack_size, ainfo);
430 case MONO_TYPE_FNPTR:
431 case MONO_TYPE_CLASS:
432 case MONO_TYPE_OBJECT:
433 case MONO_TYPE_STRING:
434 case MONO_TYPE_SZARRAY:
435 case MONO_TYPE_ARRAY:
436 add_general (&gr, &stack_size, ainfo);
438 case MONO_TYPE_GENERICINST:
439 if (!mono_type_generic_inst_is_valuetype (ptype)) {
440 add_general (&gr, &stack_size, ainfo);
444 case MONO_TYPE_VALUETYPE:
445 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
447 case MONO_TYPE_TYPEDBYREF:
448 stack_size += sizeof (MonoTypedRef);
449 ainfo->storage = ArgOnStack;
453 add_general_pair (&gr, &stack_size, ainfo);
456 add_float (&fr, &stack_size, ainfo, FALSE);
459 add_float (&fr, &stack_size, ainfo, TRUE);
462 g_error ("unexpected type 0x%x", ptype->type);
463 g_assert_not_reached ();
467 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
469 fr = FLOAT_PARAM_REGS;
471 /* Emit the signature cookie just before the implicit arguments */
472 add_general (&gr, &stack_size, &cinfo->sig_cookie);
475 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
476 cinfo->need_stack_align = TRUE;
477 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
478 stack_size += cinfo->stack_align_amount;
481 cinfo->stack_usage = stack_size;
482 cinfo->reg_usage = gr;
483 cinfo->freg_usage = fr;
488 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
490 int n = sig->hasthis + sig->param_count;
494 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
496 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
498 return get_call_info_internal (gsctx, cinfo, sig, is_pinvoke);
502 * mono_arch_get_argument_info:
503 * @csig: a method signature
504 * @param_count: the number of parameters to consider
505 * @arg_info: an array to store the result infos
507 * Gathers information on parameters such as size, alignment and
508 * padding. arg_info should be large enought to hold param_count + 1 entries.
510 * Returns the size of the argument area on the stack.
511 * This should be signal safe, since it is called from
512 * mono_arch_find_jit_info_ext ().
513 * FIXME: The metadata calls might not be signal safe.
516 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
518 int k, args_size = 0;
524 /* Avoid g_malloc as it is not signal safe */
525 cinfo = (CallInfo*)g_newa (guint8*, sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1)));
527 cinfo = get_call_info_internal (NULL, cinfo, csig, FALSE);
529 if (MONO_TYPE_ISSTRUCT (csig->ret) && (cinfo->ret.storage == ArgOnStack)) {
530 args_size += sizeof (gpointer);
534 arg_info [0].offset = offset;
537 args_size += sizeof (gpointer);
541 arg_info [0].size = args_size;
543 for (k = 0; k < param_count; k++) {
544 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
546 /* ignore alignment for now */
549 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
550 arg_info [k].pad = pad;
552 arg_info [k + 1].pad = 0;
553 arg_info [k + 1].size = size;
555 arg_info [k + 1].offset = offset;
559 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
560 align = MONO_ARCH_FRAME_ALIGNMENT;
563 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
564 arg_info [k].pad = pad;
569 static const guchar cpuid_impl [] = {
570 0x55, /* push %ebp */
571 0x89, 0xe5, /* mov %esp,%ebp */
572 0x53, /* push %ebx */
573 0x8b, 0x45, 0x08, /* mov 0x8(%ebp),%eax */
574 0x0f, 0xa2, /* cpuid */
575 0x50, /* push %eax */
576 0x8b, 0x45, 0x10, /* mov 0x10(%ebp),%eax */
577 0x89, 0x18, /* mov %ebx,(%eax) */
578 0x8b, 0x45, 0x14, /* mov 0x14(%ebp),%eax */
579 0x89, 0x08, /* mov %ecx,(%eax) */
580 0x8b, 0x45, 0x18, /* mov 0x18(%ebp),%eax */
581 0x89, 0x10, /* mov %edx,(%eax) */
583 0x8b, 0x55, 0x0c, /* mov 0xc(%ebp),%edx */
584 0x89, 0x02, /* mov %eax,(%edx) */
590 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
593 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
597 __asm__ __volatile__ (
600 "movl %%eax, %%edx\n"
601 "xorl $0x200000, %%eax\n"
606 "xorl %%edx, %%eax\n"
607 "andl $0x200000, %%eax\n"
629 /* Have to use the code manager to get around WinXP DEP */
630 static CpuidFunc func = NULL;
633 ptr = mono_global_codeman_reserve (sizeof (cpuid_impl));
634 memcpy (ptr, cpuid_impl, sizeof (cpuid_impl));
635 func = (CpuidFunc)ptr;
637 func (id, p_eax, p_ebx, p_ecx, p_edx);
640 * We use this approach because of issues with gcc and pic code, see:
641 * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
642 __asm__ __volatile__ ("cpuid"
643 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
652 * Initialize the cpu to execute managed code.
655 mono_arch_cpu_init (void)
657 /* spec compliance requires running with double precision */
661 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
662 fpcw &= ~X86_FPCW_PRECC_MASK;
663 fpcw |= X86_FPCW_PREC_DOUBLE;
664 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
665 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
667 _control87 (_PC_53, MCW_PC);
672 * Initialize architecture specific code.
675 mono_arch_init (void)
677 InitializeCriticalSection (&mini_arch_mutex);
679 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
680 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
681 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
685 * Cleanup architecture specific code.
688 mono_arch_cleanup (void)
690 DeleteCriticalSection (&mini_arch_mutex);
694 * This function returns the optimizations supported on this cpu.
697 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
699 int eax, ebx, ecx, edx;
705 /* The cpuid function allocates from the global codeman */
708 /* Feature Flags function, flags returned in EDX. */
709 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
710 if (edx & (1 << 15)) {
711 opts |= MONO_OPT_CMOV;
713 opts |= MONO_OPT_FCMOV;
715 *exclude_mask |= MONO_OPT_FCMOV;
717 *exclude_mask |= MONO_OPT_CMOV;
719 opts |= MONO_OPT_SSE2;
721 *exclude_mask |= MONO_OPT_SSE2;
723 #ifdef MONO_ARCH_SIMD_INTRINSICS
724 /*SIMD intrinsics require at least SSE2.*/
725 if (!(opts & MONO_OPT_SSE2))
726 *exclude_mask |= MONO_OPT_SIMD;
733 * This function test for all SSE functions supported.
735 * Returns a bitmask corresponding to all supported versions.
739 mono_arch_cpu_enumerate_simd_versions (void)
741 int eax, ebx, ecx, edx;
742 guint32 sse_opts = 0;
745 /* The cpuid function allocates from the global codeman */
748 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
750 sse_opts |= SIMD_VERSION_SSE1;
752 sse_opts |= SIMD_VERSION_SSE2;
754 sse_opts |= SIMD_VERSION_SSE3;
756 sse_opts |= SIMD_VERSION_SSSE3;
758 sse_opts |= SIMD_VERSION_SSE41;
760 sse_opts |= SIMD_VERSION_SSE42;
763 /* Yes, all this needs to be done to check for sse4a.
764 See: "Amd: CPUID Specification"
766 if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
767 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
768 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
769 cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
771 sse_opts |= SIMD_VERSION_SSE4a;
780 * Determine whenever the trap whose info is in SIGINFO is caused by
784 mono_arch_is_int_overflow (void *sigctx, void *info)
789 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
791 ip = (guint8*)ctx.eip;
793 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
797 switch (x86_modrm_rm (ip [1])) {
817 g_assert_not_reached ();
829 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
834 for (i = 0; i < cfg->num_varinfo; i++) {
835 MonoInst *ins = cfg->varinfo [i];
836 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
839 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
842 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
843 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
846 /* we dont allocate I1 to registers because there is no simply way to sign extend
847 * 8bit quantities in caller saved registers on x86 */
848 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
849 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
850 g_assert (i == vmv->idx);
851 vars = g_list_prepend (vars, vmv);
855 vars = mono_varlist_sort (cfg, vars, 0);
861 mono_arch_get_global_int_regs (MonoCompile *cfg)
865 /* we can use 3 registers for global allocation */
866 regs = g_list_prepend (regs, (gpointer)X86_EBX);
867 regs = g_list_prepend (regs, (gpointer)X86_ESI);
868 regs = g_list_prepend (regs, (gpointer)X86_EDI);
874 * mono_arch_regalloc_cost:
876 * Return the cost, in number of memory references, of the action of
877 * allocating the variable VMV into a register during global register
881 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
883 MonoInst *ins = cfg->varinfo [vmv->idx];
885 if (cfg->method->save_lmf)
886 /* The register is already saved */
887 return (ins->opcode == OP_ARG) ? 1 : 0;
889 /* push+pop+possible load if it is an argument */
890 return (ins->opcode == OP_ARG) ? 3 : 2;
894 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
896 static int inited = FALSE;
897 static int count = 0;
899 if (cfg->arch.need_stack_frame_inited) {
900 g_assert (cfg->arch.need_stack_frame == flag);
904 cfg->arch.need_stack_frame = flag;
905 cfg->arch.need_stack_frame_inited = TRUE;
911 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
916 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
920 needs_stack_frame (MonoCompile *cfg)
922 MonoMethodSignature *sig;
923 MonoMethodHeader *header;
924 gboolean result = FALSE;
926 #if defined(__APPLE__)
927 /*OSX requires stack frame code to have the correct alignment. */
931 if (cfg->arch.need_stack_frame_inited)
932 return cfg->arch.need_stack_frame;
934 header = cfg->header;
935 sig = mono_method_signature (cfg->method);
937 if (cfg->disable_omit_fp)
939 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
941 else if (cfg->method->save_lmf)
943 else if (cfg->stack_offset)
945 else if (cfg->param_area)
947 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
949 else if (header->num_clauses)
951 else if (sig->param_count + sig->hasthis)
953 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
955 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
956 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
959 set_needs_stack_frame (cfg, result);
961 return cfg->arch.need_stack_frame;
965 * Set var information according to the calling convention. X86 version.
966 * The locals var stuff should most likely be split in another method.
969 mono_arch_allocate_vars (MonoCompile *cfg)
971 MonoMethodSignature *sig;
972 MonoMethodHeader *header;
974 guint32 locals_stack_size, locals_stack_align;
979 header = cfg->header;
980 sig = mono_method_signature (cfg->method);
982 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
984 cfg->frame_reg = X86_EBP;
987 /* Reserve space to save LMF and caller saved registers */
989 if (cfg->method->save_lmf) {
990 offset += sizeof (MonoLMF);
992 if (cfg->used_int_regs & (1 << X86_EBX)) {
996 if (cfg->used_int_regs & (1 << X86_EDI)) {
1000 if (cfg->used_int_regs & (1 << X86_ESI)) {
1005 switch (cinfo->ret.storage) {
1006 case ArgValuetypeInReg:
1007 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1009 cfg->ret->opcode = OP_REGOFFSET;
1010 cfg->ret->inst_basereg = X86_EBP;
1011 cfg->ret->inst_offset = - offset;
1017 /* Allocate locals */
1018 offsets = mono_allocate_stack_slots (cfg, &locals_stack_size, &locals_stack_align);
1019 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1020 char *mname = mono_method_full_name (cfg->method, TRUE);
1021 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1022 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1026 if (locals_stack_align) {
1027 offset += (locals_stack_align - 1);
1028 offset &= ~(locals_stack_align - 1);
1031 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1032 * have locals larger than 8 bytes we need to make sure that
1033 * they have the appropriate offset.
1035 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1036 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1037 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1038 if (offsets [i] != -1) {
1039 MonoInst *inst = cfg->varinfo [i];
1040 inst->opcode = OP_REGOFFSET;
1041 inst->inst_basereg = X86_EBP;
1042 inst->inst_offset = - (offset + offsets [i]);
1043 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1046 offset += locals_stack_size;
1050 * Allocate arguments+return value
1053 switch (cinfo->ret.storage) {
1055 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1057 * In the new IR, the cfg->vret_addr variable represents the
1058 * vtype return value.
1060 cfg->vret_addr->opcode = OP_REGOFFSET;
1061 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1062 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1063 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1064 printf ("vret_addr =");
1065 mono_print_ins (cfg->vret_addr);
1068 cfg->ret->opcode = OP_REGOFFSET;
1069 cfg->ret->inst_basereg = X86_EBP;
1070 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1073 case ArgValuetypeInReg:
1076 cfg->ret->opcode = OP_REGVAR;
1077 cfg->ret->inst_c0 = cinfo->ret.reg;
1078 cfg->ret->dreg = cinfo->ret.reg;
1081 case ArgOnFloatFpStack:
1082 case ArgOnDoubleFpStack:
1085 g_assert_not_reached ();
1088 if (sig->call_convention == MONO_CALL_VARARG) {
1089 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1090 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1093 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1094 ArgInfo *ainfo = &cinfo->args [i];
1095 inst = cfg->args [i];
1096 if (inst->opcode != OP_REGVAR) {
1097 inst->opcode = OP_REGOFFSET;
1098 inst->inst_basereg = X86_EBP;
1100 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1103 cfg->stack_offset = offset;
1107 mono_arch_create_vars (MonoCompile *cfg)
1109 MonoMethodSignature *sig;
1112 sig = mono_method_signature (cfg->method);
1114 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1116 if (cinfo->ret.storage == ArgValuetypeInReg)
1117 cfg->ret_var_is_local = TRUE;
1118 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1119 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1124 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1125 * so we try to do it just once when we have multiple fp arguments in a row.
1126 * We don't use this mechanism generally because for int arguments the generated code
1127 * is slightly bigger and new generation cpus optimize away the dependency chains
1128 * created by push instructions on the esp value.
1129 * fp_arg_setup is the first argument in the execution sequence where the esp register
1132 static G_GNUC_UNUSED int
1133 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1138 for (; start_arg < sig->param_count; ++start_arg) {
1139 t = mini_type_get_underlying_type (NULL, sig->params [start_arg]);
1140 if (!t->byref && t->type == MONO_TYPE_R8) {
1141 fp_space += sizeof (double);
1142 *fp_arg_setup = start_arg;
1151 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1153 MonoMethodSignature *tmp_sig;
1155 /* FIXME: Add support for signature tokens to AOT */
1156 cfg->disable_aot = TRUE;
1159 * mono_ArgIterator_Setup assumes the signature cookie is
1160 * passed first and all the arguments which were before it are
1161 * passed on the stack after the signature. So compensate by
1162 * passing a different signature.
1164 tmp_sig = mono_metadata_signature_dup (call->signature);
1165 tmp_sig->param_count -= call->signature->sentinelpos;
1166 tmp_sig->sentinelpos = 0;
1167 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1169 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1174 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1179 LLVMCallInfo *linfo;
1182 n = sig->param_count + sig->hasthis;
1184 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1186 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1189 * LLVM always uses the native ABI while we use our own ABI, the
1190 * only difference is the handling of vtypes:
1191 * - we only pass/receive them in registers in some cases, and only
1192 * in 1 or 2 integer registers.
1194 if (cinfo->ret.storage == ArgValuetypeInReg) {
1196 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1197 cfg->disable_llvm = TRUE;
1201 cfg->exception_message = g_strdup ("vtype ret in call");
1202 cfg->disable_llvm = TRUE;
1204 linfo->ret.storage = LLVMArgVtypeInReg;
1205 for (j = 0; j < 2; ++j)
1206 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1210 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1211 /* Vtype returned using a hidden argument */
1212 linfo->ret.storage = LLVMArgVtypeRetAddr;
1215 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != ArgInIReg) {
1217 cfg->exception_message = g_strdup ("vtype ret in call");
1218 cfg->disable_llvm = TRUE;
1221 for (i = 0; i < n; ++i) {
1222 ainfo = cinfo->args + i;
1224 if (i >= sig->hasthis)
1225 t = sig->params [i - sig->hasthis];
1227 t = &mono_defaults.int_class->byval_arg;
1229 linfo->args [i].storage = LLVMArgNone;
1231 switch (ainfo->storage) {
1233 linfo->args [i].storage = LLVMArgInIReg;
1235 case ArgInDoubleSSEReg:
1236 case ArgInFloatSSEReg:
1237 linfo->args [i].storage = LLVMArgInFPReg;
1240 if (MONO_TYPE_ISSTRUCT (t)) {
1241 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1242 /* LLVM seems to allocate argument space for empty structures too */
1243 linfo->args [i].storage = LLVMArgNone;
1245 linfo->args [i].storage = LLVMArgVtypeByVal;
1247 linfo->args [i].storage = LLVMArgInIReg;
1249 if (t->type == MONO_TYPE_R4)
1250 linfo->args [i].storage = LLVMArgInFPReg;
1251 else if (t->type == MONO_TYPE_R8)
1252 linfo->args [i].storage = LLVMArgInFPReg;
1256 case ArgValuetypeInReg:
1258 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1259 cfg->disable_llvm = TRUE;
1263 cfg->exception_message = g_strdup ("vtype arg");
1264 cfg->disable_llvm = TRUE;
1266 linfo->args [i].storage = LLVMArgVtypeInReg;
1267 for (j = 0; j < 2; ++j)
1268 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1272 cfg->exception_message = g_strdup ("ainfo->storage");
1273 cfg->disable_llvm = TRUE;
1283 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1286 MonoMethodSignature *sig;
1289 int sentinelpos = 0;
1291 sig = call->signature;
1292 n = sig->param_count + sig->hasthis;
1294 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1296 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1297 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1299 if (cinfo->need_stack_align) {
1300 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1301 arg->dreg = X86_ESP;
1302 arg->sreg1 = X86_ESP;
1303 arg->inst_imm = cinfo->stack_align_amount;
1304 MONO_ADD_INS (cfg->cbb, arg);
1307 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1308 if (cinfo->ret.storage == ArgValuetypeInReg) {
1310 * Tell the JIT to use a more efficient calling convention: call using
1311 * OP_CALL, compute the result location after the call, and save the
1314 call->vret_in_reg = TRUE;
1316 NULLIFY_INS (call->vret_var);
1320 /* Handle the case where there are no implicit arguments */
1321 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1322 emit_sig_cookie (cfg, call, cinfo);
1325 /* Arguments are pushed in the reverse order */
1326 for (i = n - 1; i >= 0; i --) {
1327 ArgInfo *ainfo = cinfo->args + i;
1330 if (i >= sig->hasthis)
1331 t = sig->params [i - sig->hasthis];
1333 t = &mono_defaults.int_class->byval_arg;
1334 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1336 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1338 in = call->args [i];
1339 arg->cil_code = in->cil_code;
1340 arg->sreg1 = in->dreg;
1341 arg->type = in->type;
1343 g_assert (in->dreg != -1);
1345 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1349 g_assert (in->klass);
1351 if (t->type == MONO_TYPE_TYPEDBYREF) {
1352 size = sizeof (MonoTypedRef);
1353 align = sizeof (gpointer);
1356 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1360 arg->opcode = OP_OUTARG_VT;
1361 arg->sreg1 = in->dreg;
1362 arg->klass = in->klass;
1363 arg->backend.size = size;
1365 MONO_ADD_INS (cfg->cbb, arg);
1369 switch (ainfo->storage) {
1371 arg->opcode = OP_X86_PUSH;
1373 if (t->type == MONO_TYPE_R4) {
1374 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1375 arg->opcode = OP_STORER4_MEMBASE_REG;
1376 arg->inst_destbasereg = X86_ESP;
1377 arg->inst_offset = 0;
1378 } else if (t->type == MONO_TYPE_R8) {
1379 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1380 arg->opcode = OP_STORER8_MEMBASE_REG;
1381 arg->inst_destbasereg = X86_ESP;
1382 arg->inst_offset = 0;
1383 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1385 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1390 g_assert_not_reached ();
1393 MONO_ADD_INS (cfg->cbb, arg);
1396 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1397 /* Emit the signature cookie just before the implicit arguments */
1398 emit_sig_cookie (cfg, call, cinfo);
1402 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1405 if (cinfo->ret.storage == ArgValuetypeInReg) {
1408 else if (cinfo->ret.storage == ArgInIReg) {
1410 /* The return address is passed in a register */
1411 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1412 vtarg->sreg1 = call->inst.dreg;
1413 vtarg->dreg = mono_alloc_ireg (cfg);
1414 MONO_ADD_INS (cfg->cbb, vtarg);
1416 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1419 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1420 vtarg->type = STACK_MP;
1421 vtarg->sreg1 = call->vret_var->dreg;
1422 MONO_ADD_INS (cfg->cbb, vtarg);
1425 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1426 if (cinfo->ret.storage != ArgValuetypeInReg)
1427 cinfo->stack_usage -= 4;
1430 call->stack_usage = cinfo->stack_usage;
1434 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1437 int size = ins->backend.size;
1440 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1441 arg->sreg1 = src->dreg;
1443 MONO_ADD_INS (cfg->cbb, arg);
1444 } else if (size <= 20) {
1445 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1446 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1448 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1449 arg->inst_basereg = src->dreg;
1450 arg->inst_offset = 0;
1451 arg->inst_imm = size;
1453 MONO_ADD_INS (cfg->cbb, arg);
1458 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1460 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1463 if (ret->type == MONO_TYPE_R4) {
1464 if (COMPILE_LLVM (cfg))
1465 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1468 } else if (ret->type == MONO_TYPE_R8) {
1469 if (COMPILE_LLVM (cfg))
1470 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1473 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1474 if (COMPILE_LLVM (cfg))
1475 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1477 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1478 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1484 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1488 * Allow tracing to work with this interface (with an optional argument)
1491 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1495 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1496 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1498 /* if some args are passed in registers, we need to save them here */
1499 x86_push_reg (code, X86_EBP);
1501 if (cfg->compile_aot) {
1502 x86_push_imm (code, cfg->method);
1503 x86_mov_reg_imm (code, X86_EAX, func);
1504 x86_call_reg (code, X86_EAX);
1506 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1507 x86_push_imm (code, cfg->method);
1508 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1509 x86_call_code (code, 0);
1511 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1525 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1528 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1529 MonoMethod *method = cfg->method;
1530 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1532 switch (ret_type->type) {
1533 case MONO_TYPE_VOID:
1534 /* special case string .ctor icall */
1535 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1536 save_mode = SAVE_EAX;
1537 stack_usage = enable_arguments ? 8 : 4;
1539 save_mode = SAVE_NONE;
1543 save_mode = SAVE_EAX_EDX;
1544 stack_usage = enable_arguments ? 16 : 8;
1548 save_mode = SAVE_FP;
1549 stack_usage = enable_arguments ? 16 : 8;
1551 case MONO_TYPE_GENERICINST:
1552 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1553 save_mode = SAVE_EAX;
1554 stack_usage = enable_arguments ? 8 : 4;
1558 case MONO_TYPE_VALUETYPE:
1559 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1560 save_mode = SAVE_STRUCT;
1561 stack_usage = enable_arguments ? 4 : 0;
1564 save_mode = SAVE_EAX;
1565 stack_usage = enable_arguments ? 8 : 4;
1569 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1571 switch (save_mode) {
1573 x86_push_reg (code, X86_EDX);
1574 x86_push_reg (code, X86_EAX);
1575 if (enable_arguments) {
1576 x86_push_reg (code, X86_EDX);
1577 x86_push_reg (code, X86_EAX);
1582 x86_push_reg (code, X86_EAX);
1583 if (enable_arguments) {
1584 x86_push_reg (code, X86_EAX);
1589 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1590 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1591 if (enable_arguments) {
1592 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1593 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1598 if (enable_arguments) {
1599 x86_push_membase (code, X86_EBP, 8);
1608 if (cfg->compile_aot) {
1609 x86_push_imm (code, method);
1610 x86_mov_reg_imm (code, X86_EAX, func);
1611 x86_call_reg (code, X86_EAX);
1613 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1614 x86_push_imm (code, method);
1615 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1616 x86_call_code (code, 0);
1619 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1621 switch (save_mode) {
1623 x86_pop_reg (code, X86_EAX);
1624 x86_pop_reg (code, X86_EDX);
1627 x86_pop_reg (code, X86_EAX);
1630 x86_fld_membase (code, X86_ESP, 0, TRUE);
1631 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1638 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1643 #define EMIT_COND_BRANCH(ins,cond,sign) \
1644 if (ins->inst_true_bb->native_offset) { \
1645 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1647 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1648 if ((cfg->opt & MONO_OPT_BRANCH) && \
1649 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1650 x86_branch8 (code, cond, 0, sign); \
1652 x86_branch32 (code, cond, 0, sign); \
1656 * Emit an exception if condition is fail and
1657 * if possible do a directly branch to target
1659 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1661 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1662 if (tins == NULL) { \
1663 mono_add_patch_info (cfg, code - cfg->native_code, \
1664 MONO_PATCH_INFO_EXC, exc_name); \
1665 x86_branch32 (code, cond, 0, signed); \
1667 EMIT_COND_BRANCH (tins, cond, signed); \
1671 #define EMIT_FPCOMPARE(code) do { \
1672 x86_fcompp (code); \
1673 x86_fnstsw (code); \
1678 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1680 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1681 x86_call_code (code, 0);
1686 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1689 * mono_peephole_pass_1:
1691 * Perform peephole opts which should/can be performed before local regalloc
1694 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1698 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1699 MonoInst *last_ins = ins->prev;
1701 switch (ins->opcode) {
1704 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1706 * X86_LEA is like ADD, but doesn't have the
1707 * sreg1==dreg restriction.
1709 ins->opcode = OP_X86_LEA_MEMBASE;
1710 ins->inst_basereg = ins->sreg1;
1711 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1712 ins->opcode = OP_X86_INC_REG;
1716 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1717 ins->opcode = OP_X86_LEA_MEMBASE;
1718 ins->inst_basereg = ins->sreg1;
1719 ins->inst_imm = -ins->inst_imm;
1720 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1721 ins->opcode = OP_X86_DEC_REG;
1723 case OP_COMPARE_IMM:
1724 case OP_ICOMPARE_IMM:
1725 /* OP_COMPARE_IMM (reg, 0)
1727 * OP_X86_TEST_NULL (reg)
1730 ins->opcode = OP_X86_TEST_NULL;
1732 case OP_X86_COMPARE_MEMBASE_IMM:
1734 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1735 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1737 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1738 * OP_COMPARE_IMM reg, imm
1740 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1742 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1743 ins->inst_basereg == last_ins->inst_destbasereg &&
1744 ins->inst_offset == last_ins->inst_offset) {
1745 ins->opcode = OP_COMPARE_IMM;
1746 ins->sreg1 = last_ins->sreg1;
1748 /* check if we can remove cmp reg,0 with test null */
1750 ins->opcode = OP_X86_TEST_NULL;
1754 case OP_X86_PUSH_MEMBASE:
1755 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1756 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1757 ins->inst_basereg == last_ins->inst_destbasereg &&
1758 ins->inst_offset == last_ins->inst_offset) {
1759 ins->opcode = OP_X86_PUSH;
1760 ins->sreg1 = last_ins->sreg1;
1765 mono_peephole_ins (bb, ins);
1770 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1774 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1775 switch (ins->opcode) {
1777 /* reg = 0 -> XOR (reg, reg) */
1778 /* XOR sets cflags on x86, so we cant do it always */
1779 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1782 ins->opcode = OP_IXOR;
1783 ins->sreg1 = ins->dreg;
1784 ins->sreg2 = ins->dreg;
1787 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1788 * since it takes 3 bytes instead of 7.
1790 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
1791 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1792 ins2->opcode = OP_STORE_MEMBASE_REG;
1793 ins2->sreg1 = ins->dreg;
1795 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1796 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1797 ins2->sreg1 = ins->dreg;
1799 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1800 /* Continue iteration */
1809 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1810 ins->opcode = OP_X86_INC_REG;
1814 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1815 ins->opcode = OP_X86_DEC_REG;
1819 mono_peephole_ins (bb, ins);
1824 * mono_arch_lowering_pass:
1826 * Converts complex opcodes into simpler ones so that each IR instruction
1827 * corresponds to one machine instruction.
1830 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1832 MonoInst *ins, *next;
1835 * FIXME: Need to add more instructions, but the current machine
1836 * description can't model some parts of the composite instructions like
1839 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
1840 switch (ins->opcode) {
1843 case OP_IDIV_UN_IMM:
1844 case OP_IREM_UN_IMM:
1846 * Keep the cases where we could generated optimized code, otherwise convert
1847 * to the non-imm variant.
1849 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
1851 mono_decompose_op_imm (cfg, bb, ins);
1858 bb->max_vreg = cfg->next_vreg;
1862 branch_cc_table [] = {
1863 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1864 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1865 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1868 /* Maps CMP_... constants to X86_CC_... constants */
1871 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
1872 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
1876 cc_signed_table [] = {
1877 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
1878 FALSE, FALSE, FALSE, FALSE
1881 static unsigned char*
1882 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
1884 #define XMM_TEMP_REG 0
1885 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
1886 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
1887 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
1888 /* optimize by assigning a local var for this use so we avoid
1889 * the stack manipulations */
1890 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1891 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1892 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
1893 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
1894 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1896 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
1898 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
1901 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
1902 x86_fnstcw_membase(code, X86_ESP, 0);
1903 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
1904 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
1905 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
1906 x86_fldcw_membase (code, X86_ESP, 2);
1908 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1909 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
1910 x86_pop_reg (code, dreg);
1911 /* FIXME: need the high register
1912 * x86_pop_reg (code, dreg_high);
1915 x86_push_reg (code, X86_EAX); // SP = SP - 4
1916 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
1917 x86_pop_reg (code, dreg);
1919 x86_fldcw_membase (code, X86_ESP, 0);
1920 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
1923 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
1925 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
1929 static unsigned char*
1930 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
1932 int sreg = tree->sreg1;
1933 int need_touch = FALSE;
1935 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
1944 * If requested stack size is larger than one page,
1945 * perform stack-touch operation
1948 * Generate stack probe code.
1949 * Under Windows, it is necessary to allocate one page at a time,
1950 * "touching" stack after each successful sub-allocation. This is
1951 * because of the way stack growth is implemented - there is a
1952 * guard page before the lowest stack page that is currently commited.
1953 * Stack normally grows sequentially so OS traps access to the
1954 * guard page and commits more pages when needed.
1956 x86_test_reg_imm (code, sreg, ~0xFFF);
1957 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1959 br[2] = code; /* loop */
1960 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
1961 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
1964 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
1965 * that follows only initializes the last part of the area.
1967 /* Same as the init code below with size==0x1000 */
1968 if (tree->flags & MONO_INST_INIT) {
1969 x86_push_reg (code, X86_EAX);
1970 x86_push_reg (code, X86_ECX);
1971 x86_push_reg (code, X86_EDI);
1972 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
1973 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
1974 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
1976 x86_prefix (code, X86_REP_PREFIX);
1978 x86_pop_reg (code, X86_EDI);
1979 x86_pop_reg (code, X86_ECX);
1980 x86_pop_reg (code, X86_EAX);
1983 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
1984 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
1985 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
1986 x86_patch (br[3], br[2]);
1987 x86_test_reg_reg (code, sreg, sreg);
1988 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1989 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
1991 br[1] = code; x86_jump8 (code, 0);
1993 x86_patch (br[0], code);
1994 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
1995 x86_patch (br[1], code);
1996 x86_patch (br[4], code);
1999 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2001 if (tree->flags & MONO_INST_INIT) {
2003 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2004 x86_push_reg (code, X86_EAX);
2007 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2008 x86_push_reg (code, X86_ECX);
2011 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2012 x86_push_reg (code, X86_EDI);
2016 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2017 if (sreg != X86_ECX)
2018 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2019 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2021 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2023 x86_prefix (code, X86_REP_PREFIX);
2026 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2027 x86_pop_reg (code, X86_EDI);
2028 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2029 x86_pop_reg (code, X86_ECX);
2030 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2031 x86_pop_reg (code, X86_EAX);
2038 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2040 /* Move return value to the target register */
2041 switch (ins->opcode) {
2044 case OP_CALL_MEMBASE:
2045 if (ins->dreg != X86_EAX)
2046 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2056 mono_x86_have_tls_get (void)
2059 guint32 *ins = (guint32*)pthread_getspecific;
2061 * We're looking for these two instructions:
2063 * mov 0x4(%esp),%eax
2064 * mov %gs:0x48(,%eax,4),%eax
2066 return ins [0] == 0x0424448b && ins [1] == 0x85048b65 && ins [2] == 0x00000048;
2073 * mono_x86_emit_tls_get:
2074 * @code: buffer to store code to
2075 * @dreg: hard register where to place the result
2076 * @tls_offset: offset info
2078 * mono_x86_emit_tls_get emits in @code the native code that puts in
2079 * the dreg register the item in the thread local storage identified
2082 * Returns: a pointer to the end of the stored code
2085 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2087 #if defined(__APPLE__)
2088 x86_prefix (code, X86_GS_PREFIX);
2089 x86_mov_reg_mem (code, dreg, 0x48 + tls_offset * 4, 4);
2090 #elif defined(TARGET_WIN32)
2092 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2093 * Journal and/or a disassembly of the TlsGet () function.
2095 g_assert (tls_offset < 64);
2096 x86_prefix (code, X86_FS_PREFIX);
2097 x86_mov_reg_mem (code, dreg, 0x18, 4);
2098 /* Dunno what this does but TlsGetValue () contains it */
2099 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2100 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2102 if (optimize_for_xen) {
2103 x86_prefix (code, X86_GS_PREFIX);
2104 x86_mov_reg_mem (code, dreg, 0, 4);
2105 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2107 x86_prefix (code, X86_GS_PREFIX);
2108 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2115 * emit_load_volatile_arguments:
2117 * Load volatile arguments from the stack to the original input registers.
2118 * Required before a tail call.
2121 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2123 MonoMethod *method = cfg->method;
2124 MonoMethodSignature *sig;
2129 /* FIXME: Generate intermediate code instead */
2131 sig = mono_method_signature (method);
2133 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
2135 /* This is the opposite of the code in emit_prolog */
2137 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2138 ArgInfo *ainfo = cinfo->args + i;
2140 inst = cfg->args [i];
2142 if (sig->hasthis && (i == 0))
2143 arg_type = &mono_defaults.object_class->byval_arg;
2145 arg_type = sig->params [i - sig->hasthis];
2148 * On x86, the arguments are either in their original stack locations, or in
2151 if (inst->opcode == OP_REGVAR) {
2152 g_assert (ainfo->storage == ArgOnStack);
2154 x86_mov_membase_reg (code, X86_EBP, inst->inst_offset, inst->dreg, 4);
2161 #define REAL_PRINT_REG(text,reg) \
2162 mono_assert (reg >= 0); \
2163 x86_push_reg (code, X86_EAX); \
2164 x86_push_reg (code, X86_EDX); \
2165 x86_push_reg (code, X86_ECX); \
2166 x86_push_reg (code, reg); \
2167 x86_push_imm (code, reg); \
2168 x86_push_imm (code, text " %d %p\n"); \
2169 x86_mov_reg_imm (code, X86_EAX, printf); \
2170 x86_call_reg (code, X86_EAX); \
2171 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2172 x86_pop_reg (code, X86_ECX); \
2173 x86_pop_reg (code, X86_EDX); \
2174 x86_pop_reg (code, X86_EAX);
2176 /* benchmark and set based on cpu */
2177 #define LOOP_ALIGNMENT 8
2178 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2183 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2188 guint8 *code = cfg->native_code + cfg->code_len;
2191 if (cfg->opt & MONO_OPT_LOOP) {
2192 int pad, align = LOOP_ALIGNMENT;
2193 /* set alignment depending on cpu */
2194 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2196 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2197 x86_padding (code, pad);
2198 cfg->code_len += pad;
2199 bb->native_offset = cfg->code_len;
2203 if (cfg->verbose_level > 2)
2204 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2206 cpos = bb->max_offset;
2208 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2209 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2210 g_assert (!cfg->compile_aot);
2213 cov->data [bb->dfn].cil_code = bb->cil_code;
2214 /* this is not thread save, but good enough */
2215 x86_inc_mem (code, &cov->data [bb->dfn].count);
2218 offset = code - cfg->native_code;
2220 mono_debug_open_block (cfg, bb, offset);
2222 MONO_BB_FOR_EACH_INS (bb, ins) {
2223 offset = code - cfg->native_code;
2225 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2227 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2228 cfg->code_size *= 2;
2229 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2230 code = cfg->native_code + offset;
2231 mono_jit_stats.code_reallocs++;
2234 if (cfg->debug_info)
2235 mono_debug_record_line_number (cfg, ins, offset);
2237 switch (ins->opcode) {
2239 x86_mul_reg (code, ins->sreg2, TRUE);
2242 x86_mul_reg (code, ins->sreg2, FALSE);
2244 case OP_X86_SETEQ_MEMBASE:
2245 case OP_X86_SETNE_MEMBASE:
2246 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2247 ins->inst_basereg, ins->inst_offset, TRUE);
2249 case OP_STOREI1_MEMBASE_IMM:
2250 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2252 case OP_STOREI2_MEMBASE_IMM:
2253 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2255 case OP_STORE_MEMBASE_IMM:
2256 case OP_STOREI4_MEMBASE_IMM:
2257 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2259 case OP_STOREI1_MEMBASE_REG:
2260 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2262 case OP_STOREI2_MEMBASE_REG:
2263 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2265 case OP_STORE_MEMBASE_REG:
2266 case OP_STOREI4_MEMBASE_REG:
2267 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2269 case OP_STORE_MEM_IMM:
2270 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2273 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2277 /* These are created by the cprop pass so they use inst_imm as the source */
2278 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2281 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2284 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2286 case OP_LOAD_MEMBASE:
2287 case OP_LOADI4_MEMBASE:
2288 case OP_LOADU4_MEMBASE:
2289 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2291 case OP_LOADU1_MEMBASE:
2292 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2294 case OP_LOADI1_MEMBASE:
2295 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2297 case OP_LOADU2_MEMBASE:
2298 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2300 case OP_LOADI2_MEMBASE:
2301 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2303 case OP_ICONV_TO_I1:
2305 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2307 case OP_ICONV_TO_I2:
2309 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2311 case OP_ICONV_TO_U1:
2312 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2314 case OP_ICONV_TO_U2:
2315 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2319 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2321 case OP_COMPARE_IMM:
2322 case OP_ICOMPARE_IMM:
2323 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2325 case OP_X86_COMPARE_MEMBASE_REG:
2326 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2328 case OP_X86_COMPARE_MEMBASE_IMM:
2329 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2331 case OP_X86_COMPARE_MEMBASE8_IMM:
2332 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2334 case OP_X86_COMPARE_REG_MEMBASE:
2335 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2337 case OP_X86_COMPARE_MEM_IMM:
2338 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2340 case OP_X86_TEST_NULL:
2341 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2343 case OP_X86_ADD_MEMBASE_IMM:
2344 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2346 case OP_X86_ADD_REG_MEMBASE:
2347 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2349 case OP_X86_SUB_MEMBASE_IMM:
2350 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2352 case OP_X86_SUB_REG_MEMBASE:
2353 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2355 case OP_X86_AND_MEMBASE_IMM:
2356 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2358 case OP_X86_OR_MEMBASE_IMM:
2359 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2361 case OP_X86_XOR_MEMBASE_IMM:
2362 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2364 case OP_X86_ADD_MEMBASE_REG:
2365 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2367 case OP_X86_SUB_MEMBASE_REG:
2368 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2370 case OP_X86_AND_MEMBASE_REG:
2371 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2373 case OP_X86_OR_MEMBASE_REG:
2374 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2376 case OP_X86_XOR_MEMBASE_REG:
2377 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2379 case OP_X86_INC_MEMBASE:
2380 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2382 case OP_X86_INC_REG:
2383 x86_inc_reg (code, ins->dreg);
2385 case OP_X86_DEC_MEMBASE:
2386 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2388 case OP_X86_DEC_REG:
2389 x86_dec_reg (code, ins->dreg);
2391 case OP_X86_MUL_REG_MEMBASE:
2392 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2394 case OP_X86_AND_REG_MEMBASE:
2395 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2397 case OP_X86_OR_REG_MEMBASE:
2398 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2400 case OP_X86_XOR_REG_MEMBASE:
2401 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2404 x86_breakpoint (code);
2406 case OP_RELAXED_NOP:
2407 x86_prefix (code, X86_REP_PREFIX);
2415 case OP_DUMMY_STORE:
2416 case OP_NOT_REACHED:
2419 case OP_SEQ_POINT: {
2422 if (cfg->compile_aot)
2426 * Read from the single stepping trigger page. This will cause a
2427 * SIGSEGV when single stepping is enabled.
2428 * We do this _before_ the breakpoint, so single stepping after
2429 * a breakpoint is hit will step to the next IL offset.
2431 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2432 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2434 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2437 * A placeholder for a possible breakpoint inserted by
2438 * mono_arch_set_breakpoint ().
2440 for (i = 0; i < 6; ++i)
2447 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2451 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2456 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2460 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2465 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2469 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2474 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2478 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2481 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2485 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2490 * The code is the same for div/rem, the allocator will allocate dreg
2491 * to RAX/RDX as appropriate.
2493 if (ins->sreg2 == X86_EDX) {
2494 /* cdq clobbers this */
2495 x86_push_reg (code, ins->sreg2);
2497 x86_div_membase (code, X86_ESP, 0, TRUE);
2498 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2501 x86_div_reg (code, ins->sreg2, TRUE);
2506 if (ins->sreg2 == X86_EDX) {
2507 x86_push_reg (code, ins->sreg2);
2508 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2509 x86_div_membase (code, X86_ESP, 0, FALSE);
2510 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2512 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2513 x86_div_reg (code, ins->sreg2, FALSE);
2517 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2519 x86_div_reg (code, ins->sreg2, TRUE);
2522 int power = mono_is_power_of_two (ins->inst_imm);
2524 g_assert (ins->sreg1 == X86_EAX);
2525 g_assert (ins->dreg == X86_EAX);
2526 g_assert (power >= 0);
2529 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2531 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2533 * If the divident is >= 0, this does not nothing. If it is positive, it
2534 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2536 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2537 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2538 } else if (power == 0) {
2539 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2541 /* Based on gcc code */
2543 /* Add compensation for negative dividents */
2545 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2546 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2547 /* Compute remainder */
2548 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2549 /* Remove compensation */
2550 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2555 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2559 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2562 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2566 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2569 g_assert (ins->sreg2 == X86_ECX);
2570 x86_shift_reg (code, X86_SHL, ins->dreg);
2573 g_assert (ins->sreg2 == X86_ECX);
2574 x86_shift_reg (code, X86_SAR, ins->dreg);
2578 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2581 case OP_ISHR_UN_IMM:
2582 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2585 g_assert (ins->sreg2 == X86_ECX);
2586 x86_shift_reg (code, X86_SHR, ins->dreg);
2590 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2593 guint8 *jump_to_end;
2595 /* handle shifts below 32 bits */
2596 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2597 x86_shift_reg (code, X86_SHL, ins->sreg1);
2599 x86_test_reg_imm (code, X86_ECX, 32);
2600 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2602 /* handle shift over 32 bit */
2603 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2604 x86_clear_reg (code, ins->sreg1);
2606 x86_patch (jump_to_end, code);
2610 guint8 *jump_to_end;
2612 /* handle shifts below 32 bits */
2613 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2614 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2616 x86_test_reg_imm (code, X86_ECX, 32);
2617 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2619 /* handle shifts over 31 bits */
2620 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2621 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2623 x86_patch (jump_to_end, code);
2627 guint8 *jump_to_end;
2629 /* handle shifts below 32 bits */
2630 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2631 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2633 x86_test_reg_imm (code, X86_ECX, 32);
2634 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2636 /* handle shifts over 31 bits */
2637 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2638 x86_clear_reg (code, ins->backend.reg3);
2640 x86_patch (jump_to_end, code);
2644 if (ins->inst_imm >= 32) {
2645 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2646 x86_clear_reg (code, ins->sreg1);
2647 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2649 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2650 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2654 if (ins->inst_imm >= 32) {
2655 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2656 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2657 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2659 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2660 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2663 case OP_LSHR_UN_IMM:
2664 if (ins->inst_imm >= 32) {
2665 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2666 x86_clear_reg (code, ins->backend.reg3);
2667 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2669 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2670 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2674 x86_not_reg (code, ins->sreg1);
2677 x86_neg_reg (code, ins->sreg1);
2681 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2685 switch (ins->inst_imm) {
2689 if (ins->dreg != ins->sreg1)
2690 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2691 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2694 /* LEA r1, [r2 + r2*2] */
2695 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2698 /* LEA r1, [r2 + r2*4] */
2699 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2702 /* LEA r1, [r2 + r2*2] */
2704 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2705 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2708 /* LEA r1, [r2 + r2*8] */
2709 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2712 /* LEA r1, [r2 + r2*4] */
2714 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2715 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2718 /* LEA r1, [r2 + r2*2] */
2720 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2721 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2724 /* LEA r1, [r2 + r2*4] */
2725 /* LEA r1, [r1 + r1*4] */
2726 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2727 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2730 /* LEA r1, [r2 + r2*4] */
2732 /* LEA r1, [r1 + r1*4] */
2733 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2734 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2735 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2738 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2743 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2744 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2746 case OP_IMUL_OVF_UN: {
2747 /* the mul operation and the exception check should most likely be split */
2748 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2749 /*g_assert (ins->sreg2 == X86_EAX);
2750 g_assert (ins->dreg == X86_EAX);*/
2751 if (ins->sreg2 == X86_EAX) {
2752 non_eax_reg = ins->sreg1;
2753 } else if (ins->sreg1 == X86_EAX) {
2754 non_eax_reg = ins->sreg2;
2756 /* no need to save since we're going to store to it anyway */
2757 if (ins->dreg != X86_EAX) {
2759 x86_push_reg (code, X86_EAX);
2761 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
2762 non_eax_reg = ins->sreg2;
2764 if (ins->dreg == X86_EDX) {
2767 x86_push_reg (code, X86_EAX);
2769 } else if (ins->dreg != X86_EAX) {
2771 x86_push_reg (code, X86_EDX);
2773 x86_mul_reg (code, non_eax_reg, FALSE);
2774 /* save before the check since pop and mov don't change the flags */
2775 if (ins->dreg != X86_EAX)
2776 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2778 x86_pop_reg (code, X86_EDX);
2780 x86_pop_reg (code, X86_EAX);
2781 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2785 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
2788 g_assert_not_reached ();
2789 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2790 x86_mov_reg_imm (code, ins->dreg, 0);
2793 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2794 x86_mov_reg_imm (code, ins->dreg, 0);
2796 case OP_LOAD_GOTADDR:
2797 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
2798 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
2801 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2802 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
2804 case OP_X86_PUSH_GOT_ENTRY:
2805 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2806 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
2809 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2813 * Note: this 'frame destruction' logic is useful for tail calls, too.
2814 * Keep in sync with the code in emit_epilog.
2818 /* FIXME: no tracing support... */
2819 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2820 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2821 /* reset offset to make max_len work */
2822 offset = code - cfg->native_code;
2824 g_assert (!cfg->method->save_lmf);
2826 code = emit_load_volatile_arguments (cfg, code);
2828 if (cfg->used_int_regs & (1 << X86_EBX))
2830 if (cfg->used_int_regs & (1 << X86_EDI))
2832 if (cfg->used_int_regs & (1 << X86_ESI))
2835 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
2837 if (cfg->used_int_regs & (1 << X86_ESI))
2838 x86_pop_reg (code, X86_ESI);
2839 if (cfg->used_int_regs & (1 << X86_EDI))
2840 x86_pop_reg (code, X86_EDI);
2841 if (cfg->used_int_regs & (1 << X86_EBX))
2842 x86_pop_reg (code, X86_EBX);
2844 /* restore ESP/EBP */
2846 offset = code - cfg->native_code;
2847 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2848 x86_jump32 (code, 0);
2850 cfg->disable_aot = TRUE;
2854 /* ensure ins->sreg1 is not NULL
2855 * note that cmp DWORD PTR [eax], eax is one byte shorter than
2856 * cmp DWORD PTR [eax], 0
2858 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
2861 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
2862 x86_push_reg (code, hreg);
2863 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
2864 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
2865 x86_pop_reg (code, hreg);
2874 call = (MonoCallInst*)ins;
2875 if (ins->flags & MONO_INST_HAS_METHOD)
2876 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2878 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2879 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
2880 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
2881 * bytes to pop, we want to use pops. GCC does this (note it won't happen
2882 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
2883 * smart enough to do that optimization yet
2885 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
2886 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
2887 * (most likely from locality benefits). People with other processors should
2888 * check on theirs to see what happens.
2890 if (call->stack_usage == 4) {
2891 /* we want to use registers that won't get used soon, so use
2892 * ecx, as eax will get allocated first. edx is used by long calls,
2893 * so we can't use that.
2896 x86_pop_reg (code, X86_ECX);
2898 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2901 code = emit_move_return_value (cfg, ins, code);
2907 case OP_VOIDCALL_REG:
2909 call = (MonoCallInst*)ins;
2910 x86_call_reg (code, ins->sreg1);
2911 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
2912 if (call->stack_usage == 4)
2913 x86_pop_reg (code, X86_ECX);
2915 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2917 code = emit_move_return_value (cfg, ins, code);
2919 case OP_FCALL_MEMBASE:
2920 case OP_LCALL_MEMBASE:
2921 case OP_VCALL_MEMBASE:
2922 case OP_VCALL2_MEMBASE:
2923 case OP_VOIDCALL_MEMBASE:
2924 case OP_CALL_MEMBASE:
2925 call = (MonoCallInst*)ins;
2928 * Emit a few nops to simplify get_vcall_slot ().
2934 x86_call_membase (code, ins->sreg1, ins->inst_offset);
2935 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
2936 if (call->stack_usage == 4)
2937 x86_pop_reg (code, X86_ECX);
2939 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2941 code = emit_move_return_value (cfg, ins, code);
2944 x86_push_reg (code, ins->sreg1);
2946 case OP_X86_PUSH_IMM:
2947 x86_push_imm (code, ins->inst_imm);
2949 case OP_X86_PUSH_MEMBASE:
2950 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
2952 case OP_X86_PUSH_OBJ:
2953 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
2954 x86_push_reg (code, X86_EDI);
2955 x86_push_reg (code, X86_ESI);
2956 x86_push_reg (code, X86_ECX);
2957 if (ins->inst_offset)
2958 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
2960 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
2961 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2962 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
2964 x86_prefix (code, X86_REP_PREFIX);
2966 x86_pop_reg (code, X86_ECX);
2967 x86_pop_reg (code, X86_ESI);
2968 x86_pop_reg (code, X86_EDI);
2971 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
2973 case OP_X86_LEA_MEMBASE:
2974 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
2977 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
2980 /* keep alignment */
2981 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
2982 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
2983 code = mono_emit_stack_alloc (code, ins);
2984 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2986 case OP_LOCALLOC_IMM: {
2987 guint32 size = ins->inst_imm;
2988 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
2990 if (ins->flags & MONO_INST_INIT) {
2991 /* FIXME: Optimize this */
2992 x86_mov_reg_imm (code, ins->dreg, size);
2993 ins->sreg1 = ins->dreg;
2995 code = mono_emit_stack_alloc (code, ins);
2996 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2998 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
2999 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3004 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3005 x86_push_reg (code, ins->sreg1);
3006 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3007 (gpointer)"mono_arch_throw_exception");
3011 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3012 x86_push_reg (code, ins->sreg1);
3013 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3014 (gpointer)"mono_arch_rethrow_exception");
3017 case OP_CALL_HANDLER:
3018 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3019 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3020 x86_call_imm (code, 0);
3021 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3022 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3024 case OP_START_HANDLER: {
3025 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3026 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3029 case OP_ENDFINALLY: {
3030 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3031 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3035 case OP_ENDFILTER: {
3036 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3037 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3038 /* The local allocator will put the result into EAX */
3044 ins->inst_c0 = code - cfg->native_code;
3047 if (ins->inst_target_bb->native_offset) {
3048 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3050 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3051 if ((cfg->opt & MONO_OPT_BRANCH) &&
3052 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3053 x86_jump8 (code, 0);
3055 x86_jump32 (code, 0);
3059 x86_jump_reg (code, ins->sreg1);
3072 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3073 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3075 case OP_COND_EXC_EQ:
3076 case OP_COND_EXC_NE_UN:
3077 case OP_COND_EXC_LT:
3078 case OP_COND_EXC_LT_UN:
3079 case OP_COND_EXC_GT:
3080 case OP_COND_EXC_GT_UN:
3081 case OP_COND_EXC_GE:
3082 case OP_COND_EXC_GE_UN:
3083 case OP_COND_EXC_LE:
3084 case OP_COND_EXC_LE_UN:
3085 case OP_COND_EXC_IEQ:
3086 case OP_COND_EXC_INE_UN:
3087 case OP_COND_EXC_ILT:
3088 case OP_COND_EXC_ILT_UN:
3089 case OP_COND_EXC_IGT:
3090 case OP_COND_EXC_IGT_UN:
3091 case OP_COND_EXC_IGE:
3092 case OP_COND_EXC_IGE_UN:
3093 case OP_COND_EXC_ILE:
3094 case OP_COND_EXC_ILE_UN:
3095 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3097 case OP_COND_EXC_OV:
3098 case OP_COND_EXC_NO:
3100 case OP_COND_EXC_NC:
3101 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3103 case OP_COND_EXC_IOV:
3104 case OP_COND_EXC_INO:
3105 case OP_COND_EXC_IC:
3106 case OP_COND_EXC_INC:
3107 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3119 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3127 case OP_CMOV_INE_UN:
3128 case OP_CMOV_IGE_UN:
3129 case OP_CMOV_IGT_UN:
3130 case OP_CMOV_ILE_UN:
3131 case OP_CMOV_ILT_UN:
3132 g_assert (ins->dreg == ins->sreg1);
3133 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3136 /* floating point opcodes */
3138 double d = *(double *)ins->inst_p0;
3140 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3142 } else if (d == 1.0) {
3145 if (cfg->compile_aot) {
3146 guint32 *val = (guint32*)&d;
3147 x86_push_imm (code, val [1]);
3148 x86_push_imm (code, val [0]);
3149 x86_fld_membase (code, X86_ESP, 0, TRUE);
3150 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3153 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3154 x86_fld (code, NULL, TRUE);
3160 float f = *(float *)ins->inst_p0;
3162 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3164 } else if (f == 1.0) {
3167 if (cfg->compile_aot) {
3168 guint32 val = *(guint32*)&f;
3169 x86_push_imm (code, val);
3170 x86_fld_membase (code, X86_ESP, 0, FALSE);
3171 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3174 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3175 x86_fld (code, NULL, FALSE);
3180 case OP_STORER8_MEMBASE_REG:
3181 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3183 case OP_LOADR8_MEMBASE:
3184 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3186 case OP_STORER4_MEMBASE_REG:
3187 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3189 case OP_LOADR4_MEMBASE:
3190 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3192 case OP_ICONV_TO_R4:
3193 x86_push_reg (code, ins->sreg1);
3194 x86_fild_membase (code, X86_ESP, 0, FALSE);
3195 /* Change precision */
3196 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3197 x86_fld_membase (code, X86_ESP, 0, FALSE);
3198 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3200 case OP_ICONV_TO_R8:
3201 x86_push_reg (code, ins->sreg1);
3202 x86_fild_membase (code, X86_ESP, 0, FALSE);
3203 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3205 case OP_ICONV_TO_R_UN:
3206 x86_push_imm (code, 0);
3207 x86_push_reg (code, ins->sreg1);
3208 x86_fild_membase (code, X86_ESP, 0, TRUE);
3209 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3211 case OP_X86_FP_LOAD_I8:
3212 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3214 case OP_X86_FP_LOAD_I4:
3215 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3217 case OP_FCONV_TO_R4:
3218 /* Change precision */
3219 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3220 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3221 x86_fld_membase (code, X86_ESP, 0, FALSE);
3222 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3224 case OP_FCONV_TO_I1:
3225 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3227 case OP_FCONV_TO_U1:
3228 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3230 case OP_FCONV_TO_I2:
3231 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3233 case OP_FCONV_TO_U2:
3234 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3236 case OP_FCONV_TO_I4:
3238 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3240 case OP_FCONV_TO_I8:
3241 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3242 x86_fnstcw_membase(code, X86_ESP, 0);
3243 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3244 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3245 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3246 x86_fldcw_membase (code, X86_ESP, 2);
3247 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3248 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3249 x86_pop_reg (code, ins->dreg);
3250 x86_pop_reg (code, ins->backend.reg3);
3251 x86_fldcw_membase (code, X86_ESP, 0);
3252 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3254 case OP_LCONV_TO_R8_2:
3255 x86_push_reg (code, ins->sreg2);
3256 x86_push_reg (code, ins->sreg1);
3257 x86_fild_membase (code, X86_ESP, 0, TRUE);
3258 /* Change precision */
3259 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3260 x86_fld_membase (code, X86_ESP, 0, TRUE);
3261 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3263 case OP_LCONV_TO_R4_2:
3264 x86_push_reg (code, ins->sreg2);
3265 x86_push_reg (code, ins->sreg1);
3266 x86_fild_membase (code, X86_ESP, 0, TRUE);
3267 /* Change precision */
3268 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3269 x86_fld_membase (code, X86_ESP, 0, FALSE);
3270 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3272 case OP_LCONV_TO_R_UN_2: {
3273 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3276 /* load 64bit integer to FP stack */
3277 x86_push_reg (code, ins->sreg2);
3278 x86_push_reg (code, ins->sreg1);
3279 x86_fild_membase (code, X86_ESP, 0, TRUE);
3281 /* test if lreg is negative */
3282 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3283 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3285 /* add correction constant mn */
3286 x86_fld80_mem (code, mn);
3287 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3289 x86_patch (br, code);
3291 /* Change precision */
3292 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3293 x86_fld_membase (code, X86_ESP, 0, TRUE);
3295 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3299 case OP_LCONV_TO_OVF_I:
3300 case OP_LCONV_TO_OVF_I4_2: {
3301 guint8 *br [3], *label [1];
3305 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3307 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3309 /* If the low word top bit is set, see if we are negative */
3310 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3311 /* We are not negative (no top bit set, check for our top word to be zero */
3312 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3313 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3316 /* throw exception */
3317 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3319 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3320 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3321 x86_jump8 (code, 0);
3323 x86_jump32 (code, 0);
3325 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3326 x86_jump32 (code, 0);
3330 x86_patch (br [0], code);
3331 /* our top bit is set, check that top word is 0xfffffff */
3332 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3334 x86_patch (br [1], code);
3335 /* nope, emit exception */
3336 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3337 x86_patch (br [2], label [0]);
3339 if (ins->dreg != ins->sreg1)
3340 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3344 /* Not needed on the fp stack */
3347 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3350 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3353 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3356 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3364 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3369 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3376 * it really doesn't make sense to inline all this code,
3377 * it's here just to show that things may not be as simple
3380 guchar *check_pos, *end_tan, *pop_jump;
3381 x86_push_reg (code, X86_EAX);
3384 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3386 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3387 x86_fstp (code, 0); /* pop the 1.0 */
3389 x86_jump8 (code, 0);
3391 x86_fp_op (code, X86_FADD, 0);
3395 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3397 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3400 x86_patch (pop_jump, code);
3401 x86_fstp (code, 0); /* pop the 1.0 */
3402 x86_patch (check_pos, code);
3403 x86_patch (end_tan, code);
3405 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3406 x86_pop_reg (code, X86_EAX);
3413 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3422 g_assert (cfg->opt & MONO_OPT_CMOV);
3423 g_assert (ins->dreg == ins->sreg1);
3424 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3425 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3428 g_assert (cfg->opt & MONO_OPT_CMOV);
3429 g_assert (ins->dreg == ins->sreg1);
3430 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3431 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3434 g_assert (cfg->opt & MONO_OPT_CMOV);
3435 g_assert (ins->dreg == ins->sreg1);
3436 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3437 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3440 g_assert (cfg->opt & MONO_OPT_CMOV);
3441 g_assert (ins->dreg == ins->sreg1);
3442 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3443 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3449 x86_fxch (code, ins->inst_imm);
3454 x86_push_reg (code, X86_EAX);
3455 /* we need to exchange ST(0) with ST(1) */
3458 /* this requires a loop, because fprem somtimes
3459 * returns a partial remainder */
3461 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3462 /* x86_fprem1 (code); */
3465 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3467 x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3472 x86_pop_reg (code, X86_EAX);
3476 if (cfg->opt & MONO_OPT_FCMOV) {
3477 x86_fcomip (code, 1);
3481 /* this overwrites EAX */
3482 EMIT_FPCOMPARE(code);
3483 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3486 if (cfg->opt & MONO_OPT_FCMOV) {
3487 /* zeroing the register at the start results in
3488 * shorter and faster code (we can also remove the widening op)
3490 guchar *unordered_check;
3491 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3492 x86_fcomip (code, 1);
3494 unordered_check = code;
3495 x86_branch8 (code, X86_CC_P, 0, FALSE);
3496 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3497 x86_patch (unordered_check, code);
3500 if (ins->dreg != X86_EAX)
3501 x86_push_reg (code, X86_EAX);
3503 EMIT_FPCOMPARE(code);
3504 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3505 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3506 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3507 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3509 if (ins->dreg != X86_EAX)
3510 x86_pop_reg (code, X86_EAX);
3514 if (cfg->opt & MONO_OPT_FCMOV) {
3515 /* zeroing the register at the start results in
3516 * shorter and faster code (we can also remove the widening op)
3518 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3519 x86_fcomip (code, 1);
3521 if (ins->opcode == OP_FCLT_UN) {
3522 guchar *unordered_check = code;
3523 guchar *jump_to_end;
3524 x86_branch8 (code, X86_CC_P, 0, FALSE);
3525 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3527 x86_jump8 (code, 0);
3528 x86_patch (unordered_check, code);
3529 x86_inc_reg (code, ins->dreg);
3530 x86_patch (jump_to_end, code);
3532 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3536 if (ins->dreg != X86_EAX)
3537 x86_push_reg (code, X86_EAX);
3539 EMIT_FPCOMPARE(code);
3540 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3541 if (ins->opcode == OP_FCLT_UN) {
3542 guchar *is_not_zero_check, *end_jump;
3543 is_not_zero_check = code;
3544 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3546 x86_jump8 (code, 0);
3547 x86_patch (is_not_zero_check, code);
3548 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3550 x86_patch (end_jump, code);
3552 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3553 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3555 if (ins->dreg != X86_EAX)
3556 x86_pop_reg (code, X86_EAX);
3560 if (cfg->opt & MONO_OPT_FCMOV) {
3561 /* zeroing the register at the start results in
3562 * shorter and faster code (we can also remove the widening op)
3564 guchar *unordered_check;
3565 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3566 x86_fcomip (code, 1);
3568 if (ins->opcode == OP_FCGT) {
3569 unordered_check = code;
3570 x86_branch8 (code, X86_CC_P, 0, FALSE);
3571 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3572 x86_patch (unordered_check, code);
3574 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3578 if (ins->dreg != X86_EAX)
3579 x86_push_reg (code, X86_EAX);
3581 EMIT_FPCOMPARE(code);
3582 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3583 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3584 if (ins->opcode == OP_FCGT_UN) {
3585 guchar *is_not_zero_check, *end_jump;
3586 is_not_zero_check = code;
3587 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3589 x86_jump8 (code, 0);
3590 x86_patch (is_not_zero_check, code);
3591 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3593 x86_patch (end_jump, code);
3595 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3596 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3598 if (ins->dreg != X86_EAX)
3599 x86_pop_reg (code, X86_EAX);
3602 if (cfg->opt & MONO_OPT_FCMOV) {
3603 guchar *jump = code;
3604 x86_branch8 (code, X86_CC_P, 0, TRUE);
3605 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3606 x86_patch (jump, code);
3609 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3610 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3613 /* Branch if C013 != 100 */
3614 if (cfg->opt & MONO_OPT_FCMOV) {
3615 /* branch if !ZF or (PF|CF) */
3616 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3617 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3618 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3621 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3622 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3625 if (cfg->opt & MONO_OPT_FCMOV) {
3626 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3629 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3632 if (cfg->opt & MONO_OPT_FCMOV) {
3633 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3634 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3637 if (ins->opcode == OP_FBLT_UN) {
3638 guchar *is_not_zero_check, *end_jump;
3639 is_not_zero_check = code;
3640 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3642 x86_jump8 (code, 0);
3643 x86_patch (is_not_zero_check, code);
3644 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3646 x86_patch (end_jump, code);
3648 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3652 if (cfg->opt & MONO_OPT_FCMOV) {
3653 if (ins->opcode == OP_FBGT) {
3656 /* skip branch if C1=1 */
3658 x86_branch8 (code, X86_CC_P, 0, FALSE);
3659 /* branch if (C0 | C3) = 1 */
3660 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3661 x86_patch (br1, code);
3663 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3667 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3668 if (ins->opcode == OP_FBGT_UN) {
3669 guchar *is_not_zero_check, *end_jump;
3670 is_not_zero_check = code;
3671 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3673 x86_jump8 (code, 0);
3674 x86_patch (is_not_zero_check, code);
3675 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3677 x86_patch (end_jump, code);
3679 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3682 /* Branch if C013 == 100 or 001 */
3683 if (cfg->opt & MONO_OPT_FCMOV) {
3686 /* skip branch if C1=1 */
3688 x86_branch8 (code, X86_CC_P, 0, FALSE);
3689 /* branch if (C0 | C3) = 1 */
3690 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3691 x86_patch (br1, code);
3694 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3695 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3696 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3697 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3700 /* Branch if C013 == 000 */
3701 if (cfg->opt & MONO_OPT_FCMOV) {
3702 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3705 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3708 /* Branch if C013=000 or 100 */
3709 if (cfg->opt & MONO_OPT_FCMOV) {
3712 /* skip branch if C1=1 */
3714 x86_branch8 (code, X86_CC_P, 0, FALSE);
3715 /* branch if C0=0 */
3716 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3717 x86_patch (br1, code);
3720 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
3721 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
3722 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3725 /* Branch if C013 != 001 */
3726 if (cfg->opt & MONO_OPT_FCMOV) {
3727 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3728 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3731 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3732 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3736 x86_push_reg (code, X86_EAX);
3739 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
3740 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3741 x86_pop_reg (code, X86_EAX);
3743 /* Have to clean up the fp stack before throwing the exception */
3745 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3748 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3750 x86_patch (br1, code);
3754 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
3757 case OP_MEMORY_BARRIER: {
3758 /* Not needed on x86 */
3761 case OP_ATOMIC_ADD_I4: {
3762 int dreg = ins->dreg;
3764 if (dreg == ins->inst_basereg) {
3765 x86_push_reg (code, ins->sreg2);
3769 if (dreg != ins->sreg2)
3770 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
3772 x86_prefix (code, X86_LOCK_PREFIX);
3773 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
3775 if (dreg != ins->dreg) {
3776 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
3777 x86_pop_reg (code, dreg);
3782 case OP_ATOMIC_ADD_NEW_I4: {
3783 int dreg = ins->dreg;
3785 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
3786 if (ins->sreg2 == dreg) {
3787 if (dreg == X86_EBX) {
3789 if (ins->inst_basereg == X86_EDI)
3793 if (ins->inst_basereg == X86_EBX)
3796 } else if (ins->inst_basereg == dreg) {
3797 if (dreg == X86_EBX) {
3799 if (ins->sreg2 == X86_EDI)
3803 if (ins->sreg2 == X86_EBX)
3808 if (dreg != ins->dreg) {
3809 x86_push_reg (code, dreg);
3812 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
3813 x86_prefix (code, X86_LOCK_PREFIX);
3814 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
3815 /* dreg contains the old value, add with sreg2 value */
3816 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
3818 if (ins->dreg != dreg) {
3819 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
3820 x86_pop_reg (code, dreg);
3825 case OP_ATOMIC_EXCHANGE_I4: {
3827 int sreg2 = ins->sreg2;
3828 int breg = ins->inst_basereg;
3830 /* cmpxchg uses eax as comperand, need to make sure we can use it
3831 * hack to overcome limits in x86 reg allocator
3832 * (req: dreg == eax and sreg2 != eax and breg != eax)
3834 g_assert (ins->dreg == X86_EAX);
3836 /* We need the EAX reg for the cmpxchg */
3837 if (ins->sreg2 == X86_EAX) {
3838 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
3839 x86_push_reg (code, sreg2);
3840 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
3843 if (breg == X86_EAX) {
3844 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
3845 x86_push_reg (code, breg);
3846 x86_mov_reg_reg (code, breg, X86_EAX, 4);
3849 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
3851 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
3852 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
3853 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
3854 x86_patch (br [1], br [0]);
3856 if (breg != ins->inst_basereg)
3857 x86_pop_reg (code, breg);
3859 if (ins->sreg2 != sreg2)
3860 x86_pop_reg (code, sreg2);
3864 case OP_ATOMIC_CAS_I4: {
3865 g_assert (ins->sreg3 == X86_EAX);
3866 g_assert (ins->sreg1 != X86_EAX);
3867 g_assert (ins->sreg1 != ins->sreg2);
3869 x86_prefix (code, X86_LOCK_PREFIX);
3870 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
3872 if (ins->dreg != X86_EAX)
3873 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3876 #ifdef MONO_ARCH_SIMD_INTRINSICS
3878 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
3881 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
3884 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
3887 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
3890 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
3893 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
3896 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
3897 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
3900 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
3903 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
3906 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
3909 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
3912 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
3915 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
3918 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
3921 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
3924 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
3927 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
3930 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
3933 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
3936 case OP_PSHUFLEW_HIGH:
3937 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
3938 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
3940 case OP_PSHUFLEW_LOW:
3941 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
3942 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
3945 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
3946 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
3950 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
3953 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
3956 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
3959 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
3962 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
3965 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
3968 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
3969 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
3972 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
3975 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
3978 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
3981 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
3984 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
3987 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
3990 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
3993 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
3996 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
3999 case OP_EXTRACT_MASK:
4000 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4004 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4007 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4010 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4014 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4017 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4020 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4023 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4027 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4030 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4033 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4036 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4040 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4043 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4046 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4050 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4053 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4056 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4060 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4063 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4067 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4070 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4073 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4077 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4080 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4083 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4087 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4090 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4093 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4096 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4100 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4103 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4106 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4109 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4112 case OP_PSUM_ABS_DIFF:
4113 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4116 case OP_UNPACK_LOWB:
4117 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4119 case OP_UNPACK_LOWW:
4120 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4122 case OP_UNPACK_LOWD:
4123 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4125 case OP_UNPACK_LOWQ:
4126 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4128 case OP_UNPACK_LOWPS:
4129 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4131 case OP_UNPACK_LOWPD:
4132 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4135 case OP_UNPACK_HIGHB:
4136 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4138 case OP_UNPACK_HIGHW:
4139 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4141 case OP_UNPACK_HIGHD:
4142 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4144 case OP_UNPACK_HIGHQ:
4145 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4147 case OP_UNPACK_HIGHPS:
4148 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4150 case OP_UNPACK_HIGHPD:
4151 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4155 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4158 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4161 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4164 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4167 case OP_PADDB_SAT_UN:
4168 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4170 case OP_PSUBB_SAT_UN:
4171 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4173 case OP_PADDW_SAT_UN:
4174 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4176 case OP_PSUBW_SAT_UN:
4177 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4181 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4184 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4187 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4190 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4194 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4197 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4200 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4202 case OP_PMULW_HIGH_UN:
4203 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4206 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4210 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4213 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4217 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4220 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4224 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4227 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4231 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4234 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4238 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4241 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4245 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4248 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4252 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4255 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4259 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4262 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4266 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4269 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4273 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4275 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4276 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4280 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4282 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4283 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4287 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4289 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4290 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4294 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4296 case OP_EXTRACTX_U2:
4297 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4299 case OP_INSERTX_U1_SLOW:
4300 /*sreg1 is the extracted ireg (scratch)
4301 /sreg2 is the to be inserted ireg (scratch)
4302 /dreg is the xreg to receive the value*/
4304 /*clear the bits from the extracted word*/
4305 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4306 /*shift the value to insert if needed*/
4307 if (ins->inst_c0 & 1)
4308 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4309 /*join them together*/
4310 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4311 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4313 case OP_INSERTX_I4_SLOW:
4314 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4315 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4316 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4319 case OP_INSERTX_R4_SLOW:
4320 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4321 /*TODO if inst_c0 == 0 use movss*/
4322 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4323 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4325 case OP_INSERTX_R8_SLOW:
4326 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4328 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4330 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVSD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4333 case OP_STOREX_MEMBASE_REG:
4334 case OP_STOREX_MEMBASE:
4335 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4337 case OP_LOADX_MEMBASE:
4338 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4340 case OP_LOADX_ALIGNED_MEMBASE:
4341 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4343 case OP_STOREX_ALIGNED_MEMBASE_REG:
4344 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4346 case OP_STOREX_NTA_MEMBASE_REG:
4347 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4349 case OP_PREFETCH_MEMBASE:
4350 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4354 /*FIXME the peephole pass should have killed this*/
4355 if (ins->dreg != ins->sreg1)
4356 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4359 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4361 case OP_ICONV_TO_R8_RAW:
4362 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4363 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4366 case OP_FCONV_TO_R8_X:
4367 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4368 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4371 case OP_XCONV_R8_TO_I4:
4372 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4373 switch (ins->backend.source_opcode) {
4374 case OP_FCONV_TO_I1:
4375 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4377 case OP_FCONV_TO_U1:
4378 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4380 case OP_FCONV_TO_I2:
4381 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4383 case OP_FCONV_TO_U2:
4384 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4390 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4391 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4392 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4393 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4394 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4395 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4398 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4399 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4400 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4403 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4404 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4407 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4408 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4409 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4412 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4413 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4414 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4417 case OP_LIVERANGE_START: {
4418 if (cfg->verbose_level > 1)
4419 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4420 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4423 case OP_LIVERANGE_END: {
4424 if (cfg->verbose_level > 1)
4425 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4426 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4430 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4431 g_assert_not_reached ();
4434 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4435 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4436 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4437 g_assert_not_reached ();
4443 cfg->code_len = code - cfg->native_code;
4446 #endif /* DISABLE_JIT */
4449 mono_arch_register_lowlevel_calls (void)
4454 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4456 MonoJumpInfo *patch_info;
4457 gboolean compile_aot = !run_cctors;
4459 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4460 unsigned char *ip = patch_info->ip.i + code;
4461 const unsigned char *target;
4463 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4466 switch (patch_info->type) {
4467 case MONO_PATCH_INFO_BB:
4468 case MONO_PATCH_INFO_LABEL:
4471 /* No need to patch these */
4476 switch (patch_info->type) {
4477 case MONO_PATCH_INFO_IP:
4478 *((gconstpointer *)(ip)) = target;
4480 case MONO_PATCH_INFO_CLASS_INIT: {
4482 /* Might already been changed to a nop */
4483 x86_call_code (code, 0);
4484 x86_patch (ip, target);
4487 case MONO_PATCH_INFO_ABS:
4488 case MONO_PATCH_INFO_METHOD:
4489 case MONO_PATCH_INFO_METHOD_JUMP:
4490 case MONO_PATCH_INFO_INTERNAL_METHOD:
4491 case MONO_PATCH_INFO_BB:
4492 case MONO_PATCH_INFO_LABEL:
4493 case MONO_PATCH_INFO_RGCTX_FETCH:
4494 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
4495 case MONO_PATCH_INFO_MONITOR_ENTER:
4496 case MONO_PATCH_INFO_MONITOR_EXIT:
4497 x86_patch (ip, target);
4499 case MONO_PATCH_INFO_NONE:
4502 guint32 offset = mono_arch_get_patch_offset (ip);
4503 *((gconstpointer *)(ip + offset)) = target;
4511 mono_arch_emit_prolog (MonoCompile *cfg)
4513 MonoMethod *method = cfg->method;
4515 MonoMethodSignature *sig;
4517 int alloc_size, pos, max_offset, i, cfa_offset;
4519 gboolean need_stack_frame;
4521 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
4523 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4524 cfg->code_size += 512;
4526 code = cfg->native_code = g_malloc (cfg->code_size);
4528 /* Offset between RSP and the CFA */
4532 cfa_offset = sizeof (gpointer);
4533 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
4534 // IP saved at CFA - 4
4535 /* There is no IP reg on x86 */
4536 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
4538 need_stack_frame = needs_stack_frame (cfg);
4540 if (need_stack_frame) {
4541 x86_push_reg (code, X86_EBP);
4542 cfa_offset += sizeof (gpointer);
4543 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4544 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
4545 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
4546 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
4549 alloc_size = cfg->stack_offset;
4552 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4553 /* Might need to attach the thread to the JIT or change the domain for the callback */
4554 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4555 guint8 *buf, *no_domain_branch;
4557 code = mono_x86_emit_tls_get (code, X86_EAX, appdomain_tls_offset);
4558 x86_alu_reg_imm (code, X86_CMP, X86_EAX, GPOINTER_TO_UINT (cfg->domain));
4559 no_domain_branch = code;
4560 x86_branch8 (code, X86_CC_NE, 0, 0);
4561 code = mono_x86_emit_tls_get ( code, X86_EAX, lmf_tls_offset);
4562 x86_test_reg_reg (code, X86_EAX, X86_EAX);
4564 x86_branch8 (code, X86_CC_NE, 0, 0);
4565 x86_patch (no_domain_branch, code);
4566 x86_push_imm (code, cfg->domain);
4567 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4568 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
4569 x86_patch (buf, code);
4571 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4572 /* FIXME: Add a separate key for LMF to avoid this */
4573 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4577 if (cfg->compile_aot)
4578 x86_push_imm (code, 0);
4580 x86_push_imm (code, cfg->domain);
4581 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4582 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
4586 if (method->save_lmf) {
4587 pos += sizeof (MonoLMF);
4589 /* save the current IP */
4590 if (cfg->compile_aot) {
4591 /* This pushes the current ip */
4592 x86_call_imm (code, 0);
4594 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
4595 x86_push_imm_template (code);
4597 cfa_offset += sizeof (gpointer);
4599 /* save all caller saved regs */
4600 x86_push_reg (code, X86_EBP);
4601 cfa_offset += sizeof (gpointer);
4602 x86_push_reg (code, X86_ESI);
4603 cfa_offset += sizeof (gpointer);
4604 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
4605 x86_push_reg (code, X86_EDI);
4606 cfa_offset += sizeof (gpointer);
4607 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
4608 x86_push_reg (code, X86_EBX);
4609 cfa_offset += sizeof (gpointer);
4610 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
4612 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
4614 * Optimized version which uses the mono_lmf TLS variable instead of indirection
4615 * through the mono_lmf_addr TLS variable.
4617 /* %eax = previous_lmf */
4618 x86_prefix (code, X86_GS_PREFIX);
4619 x86_mov_reg_mem (code, X86_EAX, lmf_tls_offset, 4);
4620 /* skip esp + method_info + lmf */
4621 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 12);
4622 /* push previous_lmf */
4623 x86_push_reg (code, X86_EAX);
4625 x86_prefix (code, X86_GS_PREFIX);
4626 x86_mov_mem_reg (code, lmf_tls_offset, X86_ESP, 4);
4628 /* get the address of lmf for the current thread */
4630 * This is performance critical so we try to use some tricks to make
4634 if (lmf_addr_tls_offset != -1) {
4635 /* Load lmf quicky using the GS register */
4636 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
4638 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4639 /* FIXME: Add a separate key for LMF to avoid this */
4640 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4643 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
4646 /* Skip esp + method info */
4647 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
4650 x86_push_reg (code, X86_EAX);
4651 /* push *lfm (previous_lmf) */
4652 x86_push_membase (code, X86_EAX, 0);
4654 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
4658 if (cfg->used_int_regs & (1 << X86_EBX)) {
4659 x86_push_reg (code, X86_EBX);
4661 cfa_offset += sizeof (gpointer);
4662 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
4665 if (cfg->used_int_regs & (1 << X86_EDI)) {
4666 x86_push_reg (code, X86_EDI);
4668 cfa_offset += sizeof (gpointer);
4669 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
4672 if (cfg->used_int_regs & (1 << X86_ESI)) {
4673 x86_push_reg (code, X86_ESI);
4675 cfa_offset += sizeof (gpointer);
4676 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
4682 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
4683 if (mono_do_x86_stack_align && need_stack_frame) {
4684 int tot = alloc_size + pos + 4; /* ret ip */
4685 if (need_stack_frame)
4687 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
4689 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
4693 /* See mono_emit_stack_alloc */
4694 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4695 guint32 remaining_size = alloc_size;
4696 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
4697 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
4698 guint32 offset = code - cfg->native_code;
4699 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
4700 while (required_code_size >= (cfg->code_size - offset))
4701 cfg->code_size *= 2;
4702 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4703 code = cfg->native_code + offset;
4704 mono_jit_stats.code_reallocs++;
4706 while (remaining_size >= 0x1000) {
4707 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
4708 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
4709 remaining_size -= 0x1000;
4712 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
4714 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
4717 g_assert (need_stack_frame);
4720 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
4721 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
4722 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
4725 #if DEBUG_STACK_ALIGNMENT
4726 /* check the stack is aligned */
4727 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
4728 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
4729 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
4730 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
4731 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
4732 x86_breakpoint (code);
4736 /* compute max_offset in order to use short forward jumps */
4738 if (cfg->opt & MONO_OPT_BRANCH) {
4739 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4741 bb->max_offset = max_offset;
4743 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4745 /* max alignment for loops */
4746 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4747 max_offset += LOOP_ALIGNMENT;
4749 MONO_BB_FOR_EACH_INS (bb, ins) {
4750 if (ins->opcode == OP_LABEL)
4751 ins->inst_c1 = max_offset;
4753 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4758 /* store runtime generic context */
4759 if (cfg->rgctx_var) {
4760 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
4762 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
4765 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4766 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4768 /* load arguments allocated to register from the stack */
4769 sig = mono_method_signature (method);
4772 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4773 inst = cfg->args [pos];
4774 if (inst->opcode == OP_REGVAR) {
4775 g_assert (need_stack_frame);
4776 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
4777 if (cfg->verbose_level > 2)
4778 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
4783 cfg->code_len = code - cfg->native_code;
4785 g_assert (cfg->code_len < cfg->code_size);
4791 mono_arch_emit_epilog (MonoCompile *cfg)
4793 MonoMethod *method = cfg->method;
4794 MonoMethodSignature *sig = mono_method_signature (method);
4796 guint32 stack_to_pop;
4798 int max_epilog_size = 16;
4800 gboolean need_stack_frame = needs_stack_frame (cfg);
4802 if (cfg->method->save_lmf)
4803 max_epilog_size += 128;
4805 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4806 cfg->code_size *= 2;
4807 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4808 mono_jit_stats.code_reallocs++;
4811 code = cfg->native_code + cfg->code_len;
4813 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4814 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4816 /* the code restoring the registers must be kept in sync with OP_JMP */
4819 if (method->save_lmf) {
4820 gint32 prev_lmf_reg;
4821 gint32 lmf_offset = -sizeof (MonoLMF);
4823 /* check if we need to restore protection of the stack after a stack overflow */
4824 if (mono_get_jit_tls_offset () != -1) {
4826 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
4827 /* we load the value in a separate instruction: this mechanism may be
4828 * used later as a safer way to do thread interruption
4830 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
4831 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
4833 x86_branch8 (code, X86_CC_Z, 0, FALSE);
4834 /* note that the call trampoline will preserve eax/edx */
4835 x86_call_reg (code, X86_ECX);
4836 x86_patch (patch, code);
4838 /* FIXME: maybe save the jit tls in the prolog */
4840 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
4842 * Optimized version which uses the mono_lmf TLS variable instead of indirection
4843 * through the mono_lmf_addr TLS variable.
4845 /* reg = previous_lmf */
4846 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
4848 /* lmf = previous_lmf */
4849 x86_prefix (code, X86_GS_PREFIX);
4850 x86_mov_mem_reg (code, lmf_tls_offset, X86_ECX, 4);
4852 /* Find a spare register */
4853 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
4856 prev_lmf_reg = X86_EDI;
4857 cfg->used_int_regs |= (1 << X86_EDI);
4860 prev_lmf_reg = X86_EDX;
4864 /* reg = previous_lmf */
4865 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
4868 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
4870 /* *(lmf) = previous_lmf */
4871 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
4874 /* restore caller saved regs */
4875 if (cfg->used_int_regs & (1 << X86_EBX)) {
4876 x86_mov_reg_membase (code, X86_EBX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
4879 if (cfg->used_int_regs & (1 << X86_EDI)) {
4880 x86_mov_reg_membase (code, X86_EDI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
4882 if (cfg->used_int_regs & (1 << X86_ESI)) {
4883 x86_mov_reg_membase (code, X86_ESI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
4886 /* EBP is restored by LEAVE */
4888 if (cfg->used_int_regs & (1 << X86_EBX)) {
4891 if (cfg->used_int_regs & (1 << X86_EDI)) {
4894 if (cfg->used_int_regs & (1 << X86_ESI)) {
4899 g_assert (need_stack_frame);
4900 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
4903 if (cfg->used_int_regs & (1 << X86_ESI)) {
4904 x86_pop_reg (code, X86_ESI);
4906 if (cfg->used_int_regs & (1 << X86_EDI)) {
4907 x86_pop_reg (code, X86_EDI);
4909 if (cfg->used_int_regs & (1 << X86_EBX)) {
4910 x86_pop_reg (code, X86_EBX);
4914 /* Load returned vtypes into registers if needed */
4915 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
4916 if (cinfo->ret.storage == ArgValuetypeInReg) {
4917 for (quad = 0; quad < 2; quad ++) {
4918 switch (cinfo->ret.pair_storage [quad]) {
4920 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
4922 case ArgOnFloatFpStack:
4923 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
4925 case ArgOnDoubleFpStack:
4926 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
4931 g_assert_not_reached ();
4936 if (need_stack_frame)
4939 if (CALLCONV_IS_STDCALL (sig)) {
4940 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
4942 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
4943 } else if (MONO_TYPE_ISSTRUCT (mono_method_signature (cfg->method)->ret) && (cinfo->ret.storage == ArgOnStack))
4949 g_assert (need_stack_frame);
4950 x86_ret_imm (code, stack_to_pop);
4955 cfg->code_len = code - cfg->native_code;
4957 g_assert (cfg->code_len < cfg->code_size);
4961 mono_arch_emit_exceptions (MonoCompile *cfg)
4963 MonoJumpInfo *patch_info;
4966 MonoClass *exc_classes [16];
4967 guint8 *exc_throw_start [16], *exc_throw_end [16];
4971 /* Compute needed space */
4972 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4973 if (patch_info->type == MONO_PATCH_INFO_EXC)
4978 * make sure we have enough space for exceptions
4979 * 16 is the size of two push_imm instructions and a call
4981 if (cfg->compile_aot)
4982 code_size = exc_count * 32;
4984 code_size = exc_count * 16;
4986 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4987 cfg->code_size *= 2;
4988 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4989 mono_jit_stats.code_reallocs++;
4992 code = cfg->native_code + cfg->code_len;
4995 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4996 switch (patch_info->type) {
4997 case MONO_PATCH_INFO_EXC: {
4998 MonoClass *exc_class;
5002 x86_patch (patch_info->ip.i + cfg->native_code, code);
5004 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5005 g_assert (exc_class);
5006 throw_ip = patch_info->ip.i;
5008 /* Find a throw sequence for the same exception class */
5009 for (i = 0; i < nthrows; ++i)
5010 if (exc_classes [i] == exc_class)
5013 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5014 x86_jump_code (code, exc_throw_start [i]);
5015 patch_info->type = MONO_PATCH_INFO_NONE;
5020 /* Compute size of code following the push <OFFSET> */
5023 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5025 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5026 /* Use the shorter form */
5028 x86_push_imm (code, 0);
5032 x86_push_imm (code, 0xf0f0f0f0);
5037 exc_classes [nthrows] = exc_class;
5038 exc_throw_start [nthrows] = code;
5041 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5042 patch_info->data.name = "mono_arch_throw_corlib_exception";
5043 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5044 patch_info->ip.i = code - cfg->native_code;
5045 x86_call_code (code, 0);
5046 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5051 exc_throw_end [nthrows] = code;
5063 cfg->code_len = code - cfg->native_code;
5065 g_assert (cfg->code_len < cfg->code_size);
5069 mono_arch_flush_icache (guint8 *code, gint size)
5075 mono_arch_flush_register_windows (void)
5080 mono_arch_is_inst_imm (gint64 imm)
5086 * Support for fast access to the thread-local lmf structure using the GS
5087 * segment register on NPTL + kernel 2.6.x.
5090 static gboolean tls_offset_inited = FALSE;
5093 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5095 if (!tls_offset_inited) {
5096 if (!getenv ("MONO_NO_TLS")) {
5099 * We need to init this multiple times, since when we are first called, the key might not
5100 * be initialized yet.
5102 appdomain_tls_offset = mono_domain_get_tls_key ();
5103 lmf_tls_offset = mono_get_jit_tls_key ();
5105 /* Only 64 tls entries can be accessed using inline code */
5106 if (appdomain_tls_offset >= 64)
5107 appdomain_tls_offset = -1;
5108 if (lmf_tls_offset >= 64)
5109 lmf_tls_offset = -1;
5112 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5114 tls_offset_inited = TRUE;
5115 appdomain_tls_offset = mono_domain_get_tls_offset ();
5116 lmf_tls_offset = mono_get_lmf_tls_offset ();
5117 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5124 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5128 #ifdef MONO_ARCH_HAVE_IMT
5130 // Linear handler, the bsearch head compare is shorter
5131 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5132 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5133 // x86_patch(ins,target)
5134 //[1 + 5] x86_jump_mem(inst,mem)
5137 #define BR_SMALL_SIZE 2
5138 #define BR_LARGE_SIZE 5
5139 #define JUMP_IMM_SIZE 6
5140 #define ENABLE_WRONG_METHOD_CHECK 0
5144 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5146 int i, distance = 0;
5147 for (i = start; i < target; ++i)
5148 distance += imt_entries [i]->chunk_size;
5153 * LOCKING: called with the domain lock held
5156 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5157 gpointer fail_tramp)
5161 guint8 *code, *start;
5163 for (i = 0; i < count; ++i) {
5164 MonoIMTCheckItem *item = imt_entries [i];
5165 if (item->is_equals) {
5166 if (item->check_target_idx) {
5167 if (!item->compare_done)
5168 item->chunk_size += CMP_SIZE;
5169 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5172 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5174 item->chunk_size += JUMP_IMM_SIZE;
5175 #if ENABLE_WRONG_METHOD_CHECK
5176 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5181 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5182 imt_entries [item->check_target_idx]->compare_done = TRUE;
5184 size += item->chunk_size;
5187 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5189 code = mono_domain_code_reserve (domain, size);
5191 for (i = 0; i < count; ++i) {
5192 MonoIMTCheckItem *item = imt_entries [i];
5193 item->code_target = code;
5194 if (item->is_equals) {
5195 if (item->check_target_idx) {
5196 if (!item->compare_done)
5197 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5198 item->jmp_code = code;
5199 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5200 if (item->has_target_code)
5201 x86_jump_code (code, item->value.target_code);
5203 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5206 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5207 item->jmp_code = code;
5208 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5209 if (item->has_target_code)
5210 x86_jump_code (code, item->value.target_code);
5212 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5213 x86_patch (item->jmp_code, code);
5214 x86_jump_code (code, fail_tramp);
5215 item->jmp_code = NULL;
5217 /* enable the commented code to assert on wrong method */
5218 #if ENABLE_WRONG_METHOD_CHECK
5219 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5220 item->jmp_code = code;
5221 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5223 if (item->has_target_code)
5224 x86_jump_code (code, item->value.target_code);
5226 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5227 #if ENABLE_WRONG_METHOD_CHECK
5228 x86_patch (item->jmp_code, code);
5229 x86_breakpoint (code);
5230 item->jmp_code = NULL;
5235 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5236 item->jmp_code = code;
5237 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5238 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5240 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5243 /* patch the branches to get to the target items */
5244 for (i = 0; i < count; ++i) {
5245 MonoIMTCheckItem *item = imt_entries [i];
5246 if (item->jmp_code) {
5247 if (item->check_target_idx) {
5248 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5254 mono_stats.imt_thunks_size += code - start;
5255 g_assert (code - start <= size);
5259 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5260 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5269 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5271 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5276 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5278 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5282 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5284 MonoInst *ins = NULL;
5287 if (cmethod->klass == mono_defaults.math_class) {
5288 if (strcmp (cmethod->name, "Sin") == 0) {
5290 } else if (strcmp (cmethod->name, "Cos") == 0) {
5292 } else if (strcmp (cmethod->name, "Tan") == 0) {
5294 } else if (strcmp (cmethod->name, "Atan") == 0) {
5296 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5298 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5300 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5305 MONO_INST_NEW (cfg, ins, opcode);
5306 ins->type = STACK_R8;
5307 ins->dreg = mono_alloc_freg (cfg);
5308 ins->sreg1 = args [0]->dreg;
5309 MONO_ADD_INS (cfg->cbb, ins);
5312 if (cfg->opt & MONO_OPT_CMOV) {
5315 if (strcmp (cmethod->name, "Min") == 0) {
5316 if (fsig->params [0]->type == MONO_TYPE_I4)
5318 } else if (strcmp (cmethod->name, "Max") == 0) {
5319 if (fsig->params [0]->type == MONO_TYPE_I4)
5324 MONO_INST_NEW (cfg, ins, opcode);
5325 ins->type = STACK_I4;
5326 ins->dreg = mono_alloc_ireg (cfg);
5327 ins->sreg1 = args [0]->dreg;
5328 ins->sreg2 = args [1]->dreg;
5329 MONO_ADD_INS (cfg->cbb, ins);
5334 /* OP_FREM is not IEEE compatible */
5335 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5336 MONO_INST_NEW (cfg, ins, OP_FREM);
5337 ins->inst_i0 = args [0];
5338 ins->inst_i1 = args [1];
5347 mono_arch_print_tree (MonoInst *tree, int arity)
5352 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5358 if (appdomain_tls_offset == -1)
5361 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5362 ins->inst_offset = appdomain_tls_offset;
5367 mono_arch_get_patch_offset (guint8 *code)
5369 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5371 else if ((code [0] == 0xba))
5373 else if ((code [0] == 0x68))
5376 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5377 /* push <OFFSET>(<REG>) */
5379 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5380 /* call *<OFFSET>(<REG>) */
5382 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5385 else if ((code [0] == 0x58) && (code [1] == 0x05))
5386 /* pop %eax; add <OFFSET>, %eax */
5388 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5389 /* pop <REG>; add <OFFSET>, <REG> */
5391 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5392 /* mov <REG>, imm */
5395 g_assert_not_reached ();
5401 * mono_breakpoint_clean_code:
5403 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5404 * breakpoints in the original code, they are removed in the copy.
5406 * Returns TRUE if no sw breakpoint was present.
5409 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5412 gboolean can_write = TRUE;
5414 * If method_start is non-NULL we need to perform bound checks, since we access memory
5415 * at code - offset we could go before the start of the method and end up in a different
5416 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5419 if (!method_start || code - offset >= method_start) {
5420 memcpy (buf, code - offset, size);
5422 int diff = code - method_start;
5423 memset (buf, 0, size);
5424 memcpy (buf + offset - diff, method_start, diff + size - offset);
5427 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5428 int idx = mono_breakpoint_info_index [i];
5432 ptr = mono_breakpoint_info [idx].address;
5433 if (ptr >= code && ptr < code + size) {
5434 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5436 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5437 buf [ptr - code] = saved_byte;
5444 mono_arch_get_vcall_slot (guint8 *code, mgreg_t *regs, int *displacement)
5450 mono_breakpoint_clean_code (NULL, code, 8, buf, sizeof (buf));
5458 * A given byte sequence can match more than case here, so we have to be
5459 * really careful about the ordering of the cases. Longer sequences
5461 * There are two types of calls:
5462 * - direct calls: 0xff address_byte 8/32 bits displacement
5463 * - indirect calls: nop nop nop <call>
5464 * The nops make sure we don't confuse the instruction preceeding an indirect
5465 * call with a direct call.
5467 if ((code [1] != 0xe8) && (code [3] == 0xff) && ((code [4] & 0x18) == 0x10) && ((code [4] >> 6) == 1)) {
5468 reg = code [4] & 0x07;
5469 disp = (signed char)code [5];
5470 } else if ((code [0] == 0xff) && ((code [1] & 0x18) == 0x10) && ((code [1] >> 6) == 2)) {
5471 reg = code [1] & 0x07;
5472 disp = *((gint32*)(code + 2));
5473 } else if ((code [1] == 0xe8)) {
5475 } else if ((code [4] == 0xff) && (((code [5] >> 6) & 0x3) == 0) && (((code [5] >> 3) & 0x7) == 2)) {
5477 * This is a interface call
5478 * 8b 40 30 mov 0x30(%eax),%eax
5479 * ff 10 call *(%eax)
5482 reg = code [5] & 0x07;
5487 *displacement = disp;
5488 return (gpointer)regs [reg];
5492 * mono_x86_get_this_arg_offset:
5494 * Return the offset of the stack location where this is passed during a virtual
5498 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
5500 CallInfo *cinfo = NULL;
5503 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5504 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5506 offset = cinfo->args [0].offset;
5515 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig,
5516 mgreg_t *regs, guint8 *code)
5518 guint32 esp = regs [X86_ESP];
5519 CallInfo *cinfo = NULL;
5524 * Avoid expensive calls to get_generic_context_from_code () + get_call_info
5527 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5529 gsctx = mono_get_generic_context_from_code (code);
5530 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5532 offset = cinfo->args [0].offset;
5538 * The stack looks like:
5541 * <possible vtype return address>
5543 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
5545 res = (((MonoObject**)esp) [5 + (offset / 4)]);
5551 #define MAX_ARCH_DELEGATE_PARAMS 10
5554 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
5556 guint8 *code, *start;
5559 * The stack contains:
5565 start = code = mono_global_codeman_reserve (64);
5567 /* Replace the this argument with the target */
5568 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5569 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
5570 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5571 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5573 g_assert ((code - start) < 64);
5576 /* 8 for mov_reg and jump, plus 8 for each parameter */
5577 int code_reserve = 8 + (param_count * 8);
5580 * The stack contains:
5581 * <args in reverse order>
5586 * <args in reverse order>
5589 * without unbalancing the stack.
5590 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
5591 * and leaving original spot of first arg as placeholder in stack so
5592 * when callee pops stack everything works.
5595 start = code = mono_global_codeman_reserve (code_reserve);
5597 /* store delegate for access to method_ptr */
5598 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
5601 for (i = 0; i < param_count; ++i) {
5602 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
5603 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
5606 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5608 g_assert ((code - start) < code_reserve);
5611 mono_debug_add_delegate_trampoline (start, code - start);
5614 *code_len = code - start;
5620 mono_arch_get_delegate_invoke_impls (void)
5627 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
5628 res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len));
5630 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
5631 code = get_delegate_invoke_impl (FALSE, i, &code_len);
5632 res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len));
5639 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5641 guint8 *code, *start;
5643 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5646 /* FIXME: Support more cases */
5647 if (MONO_TYPE_ISSTRUCT (sig->ret))
5651 * The stack contains:
5657 static guint8* cached = NULL;
5661 if (mono_aot_only) {
5662 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
5663 start = mono_aot_get_named_code (name);
5666 start = get_delegate_invoke_impl (TRUE, 0, NULL);
5669 mono_memory_barrier ();
5673 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5676 for (i = 0; i < sig->param_count; ++i)
5677 if (!mono_is_regsize_var (sig->params [i]))
5680 code = cache [sig->param_count];
5684 if (mono_aot_only) {
5685 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
5686 start = mono_aot_get_named_code (name);
5689 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
5692 mono_memory_barrier ();
5694 cache [sig->param_count] = start;
5701 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5704 case X86_EAX: return (gpointer)ctx->eax;
5705 case X86_EBX: return (gpointer)ctx->ebx;
5706 case X86_ECX: return (gpointer)ctx->ecx;
5707 case X86_EDX: return (gpointer)ctx->edx;
5708 case X86_ESP: return (gpointer)ctx->esp;
5709 case X86_EBP: return (gpointer)ctx->ebp;
5710 case X86_ESI: return (gpointer)ctx->esi;
5711 case X86_EDI: return (gpointer)ctx->edi;
5712 default: g_assert_not_reached ();
5716 #ifdef MONO_ARCH_SIMD_INTRINSICS
5719 get_float_to_x_spill_area (MonoCompile *cfg)
5721 if (!cfg->fconv_to_r8_x_var) {
5722 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
5723 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
5725 return cfg->fconv_to_r8_x_var;
5729 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
5732 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
5735 int dreg, src_opcode;
5737 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
5740 switch (src_opcode = ins->opcode) {
5741 case OP_FCONV_TO_I1:
5742 case OP_FCONV_TO_U1:
5743 case OP_FCONV_TO_I2:
5744 case OP_FCONV_TO_U2:
5745 case OP_FCONV_TO_I4:
5752 /* dreg is the IREG and sreg1 is the FREG */
5753 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
5754 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
5755 fconv->sreg1 = ins->sreg1;
5756 fconv->dreg = mono_alloc_ireg (cfg);
5757 fconv->type = STACK_VTYPE;
5758 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
5760 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
5764 ins->opcode = OP_XCONV_R8_TO_I4;
5766 ins->klass = mono_defaults.int32_class;
5767 ins->sreg1 = fconv->dreg;
5769 ins->type = STACK_I4;
5770 ins->backend.source_opcode = src_opcode;
5773 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
5776 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
5781 if (long_ins->opcode == OP_LNEG) {
5783 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
5784 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
5785 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
5790 #ifdef MONO_ARCH_SIMD_INTRINSICS
5792 if (!(cfg->opt & MONO_OPT_SIMD))
5795 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
5796 switch (long_ins->opcode) {
5798 vreg = long_ins->sreg1;
5800 if (long_ins->inst_c0) {
5801 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
5802 ins->klass = long_ins->klass;
5803 ins->sreg1 = long_ins->sreg1;
5805 ins->type = STACK_VTYPE;
5806 ins->dreg = vreg = alloc_ireg (cfg);
5807 MONO_ADD_INS (cfg->cbb, ins);
5810 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
5811 ins->klass = mono_defaults.int32_class;
5813 ins->type = STACK_I4;
5814 ins->dreg = long_ins->dreg + 1;
5815 MONO_ADD_INS (cfg->cbb, ins);
5817 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
5818 ins->klass = long_ins->klass;
5819 ins->sreg1 = long_ins->sreg1;
5820 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
5821 ins->type = STACK_VTYPE;
5822 ins->dreg = vreg = alloc_ireg (cfg);
5823 MONO_ADD_INS (cfg->cbb, ins);
5825 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
5826 ins->klass = mono_defaults.int32_class;
5828 ins->type = STACK_I4;
5829 ins->dreg = long_ins->dreg + 2;
5830 MONO_ADD_INS (cfg->cbb, ins);
5832 long_ins->opcode = OP_NOP;
5834 case OP_INSERTX_I8_SLOW:
5835 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
5836 ins->dreg = long_ins->dreg;
5837 ins->sreg1 = long_ins->dreg;
5838 ins->sreg2 = long_ins->sreg2 + 1;
5839 ins->inst_c0 = long_ins->inst_c0 * 2;
5840 MONO_ADD_INS (cfg->cbb, ins);
5842 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
5843 ins->dreg = long_ins->dreg;
5844 ins->sreg1 = long_ins->dreg;
5845 ins->sreg2 = long_ins->sreg2 + 2;
5846 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
5847 MONO_ADD_INS (cfg->cbb, ins);
5849 long_ins->opcode = OP_NOP;
5852 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
5853 ins->dreg = long_ins->dreg;
5854 ins->sreg1 = long_ins->sreg1 + 1;
5855 ins->klass = long_ins->klass;
5856 ins->type = STACK_VTYPE;
5857 MONO_ADD_INS (cfg->cbb, ins);
5859 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
5860 ins->dreg = long_ins->dreg;
5861 ins->sreg1 = long_ins->dreg;
5862 ins->sreg2 = long_ins->sreg1 + 2;
5864 ins->klass = long_ins->klass;
5865 ins->type = STACK_VTYPE;
5866 MONO_ADD_INS (cfg->cbb, ins);
5868 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
5869 ins->dreg = long_ins->dreg;
5870 ins->sreg1 = long_ins->dreg;;
5871 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
5872 ins->klass = long_ins->klass;
5873 ins->type = STACK_VTYPE;
5874 MONO_ADD_INS (cfg->cbb, ins);
5876 long_ins->opcode = OP_NOP;
5879 #endif /* MONO_ARCH_SIMD_INTRINSICS */
5882 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
5884 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
5887 gpointer *sp, old_value;
5889 const unsigned char *handler;
5891 /*Decode the first instruction to figure out where did we store the spvar*/
5892 /*Our jit MUST generate the following:
5894 Which is encoded as: 0x89 mod_rm.
5895 mod_rm (esp, ebp, imm) which can be: (imm will never be zero)
5896 mod (reg + imm8): 01 reg(esp): 100 rm(ebp): 101 -> 01100101 (0x65)
5897 mod (reg + imm32): 10 reg(esp): 100 rm(ebp): 101 -> 10100101 (0xA5)
5899 handler = clause->handler_start;
5901 if (*handler != 0x89)
5906 if (*handler == 0x65)
5907 offset = *(signed char*)(handler + 1);
5908 else if (*handler == 0xA5)
5909 offset = *(int*)(handler + 1);
5914 bp = MONO_CONTEXT_GET_BP (ctx);
5915 sp = *(gpointer*)(bp + offset);
5918 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
5927 * mono_aot_emit_load_got_addr:
5929 * Emit code to load the got address.
5930 * On x86, the result is placed into EBX.
5933 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
5935 x86_call_imm (code, 0);
5937 * The patch needs to point to the pop, since the GOT offset needs
5938 * to be added to that address.
5941 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
5943 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
5944 x86_pop_reg (code, MONO_ARCH_GOT_REG);
5945 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
5951 * mono_ppc_emit_load_aotconst:
5953 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
5954 * TARGET from the mscorlib GOT in full-aot code.
5955 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
5959 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
5961 /* Load the mscorlib got address */
5962 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
5963 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
5964 /* arch_emit_got_access () patches this */
5965 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
5971 #define DBG_SIGNAL SIGBUS
5973 #define DBG_SIGNAL SIGSEGV
5976 /* Soft Debug support */
5977 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
5980 * mono_arch_set_breakpoint:
5982 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
5983 * The location should contain code emitted by OP_SEQ_POINT.
5986 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
5991 * In production, we will use int3 (has to fix the size in the md
5992 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
5995 g_assert (code [0] == 0x90);
5996 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6000 * mono_arch_clear_breakpoint:
6002 * Clear the breakpoint at IP.
6005 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6010 for (i = 0; i < 6; ++i)
6015 * mono_arch_start_single_stepping:
6017 * Start single stepping.
6020 mono_arch_start_single_stepping (void)
6022 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6026 * mono_arch_stop_single_stepping:
6028 * Stop single stepping.
6031 mono_arch_stop_single_stepping (void)
6033 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6037 * mono_arch_is_single_step_event:
6039 * Return whenever the machine state in SIGCTX corresponds to a single
6043 mono_arch_is_single_step_event (void *info, void *sigctx)
6046 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info; /* Sometimes the address is off by 4 */
6047 if ((einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6052 siginfo_t* sinfo = (siginfo_t*) info;
6053 /* Sometimes the address is off by 4 */
6054 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6062 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6065 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info; /* Sometimes the address is off by 4 */
6066 if ((einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6071 siginfo_t* sinfo = (siginfo_t*)info;
6072 /* Sometimes the address is off by 4 */
6073 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6081 * mono_arch_get_ip_for_breakpoint:
6083 * See mini-amd64.c for docs.
6086 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
6088 guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
6093 #define BREAKPOINT_SIZE 6
6096 * mono_arch_get_ip_for_single_step:
6098 * See mini-amd64.c for docs.
6101 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
6103 guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
6105 /* Size of x86_alu_reg_imm */
6112 * mono_arch_skip_breakpoint:
6114 * See mini-amd64.c for docs.
6117 mono_arch_skip_breakpoint (MonoContext *ctx)
6119 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6123 * mono_arch_skip_single_step:
6125 * See mini-amd64.c for docs.
6128 mono_arch_skip_single_step (MonoContext *ctx)
6130 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6134 * mono_arch_get_seq_point_info:
6136 * See mini-amd64.c for docs.
6139 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)