2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * (C) 2003 Ximian, Inc.
18 #include <mono/metadata/appdomain.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/metadata/threads.h>
21 #include <mono/metadata/profiler-private.h>
22 #include <mono/metadata/mono-debug.h>
23 #include <mono/metadata/gc-internal.h>
24 #include <mono/utils/mono-math.h>
25 #include <mono/utils/mono-counters.h>
26 #include <mono/utils/mono-mmap.h>
33 /* On windows, these hold the key returned by TlsAlloc () */
34 static gint lmf_tls_offset = -1;
35 static gint lmf_addr_tls_offset = -1;
36 static gint appdomain_tls_offset = -1;
39 static gboolean optimize_for_xen = TRUE;
41 #define optimize_for_xen 0
45 static gboolean is_win32 = TRUE;
47 static gboolean is_win32 = FALSE;
50 /* This mutex protects architecture specific caches */
51 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
52 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
53 static CRITICAL_SECTION mini_arch_mutex;
55 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
60 /* Under windows, the default pinvoke calling convention is stdcall */
61 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT))
63 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL)
66 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
72 #ifdef __native_client_codegen__
73 const guint kNaClAlignment = kNaClAlignmentX86;
74 const guint kNaClAlignmentMask = kNaClAlignmentMaskX86;
76 /* Default alignment for Native Client is 32-byte. */
77 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
79 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
80 /* Check that alignment doesn't cross an alignment boundary. */
82 mono_arch_nacl_pad (guint8 *code, int pad)
84 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
86 if (pad == 0) return code;
87 /* assertion: alignment cannot cross a block boundary */
88 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
89 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
90 while (pad >= kMaxPadding) {
91 x86_padding (code, kMaxPadding);
94 if (pad != 0) x86_padding (code, pad);
99 mono_arch_nacl_skip_nops (guint8 *code)
101 x86_skip_nops (code);
105 #endif /* __native_client_codegen__ */
108 * The code generated for sequence points reads from this location, which is
109 * made read-only when single stepping is enabled.
111 static gpointer ss_trigger_page;
113 /* Enabled breakpoints read from this trigger page */
114 static gpointer bp_trigger_page;
117 mono_arch_regname (int reg)
120 case X86_EAX: return "%eax";
121 case X86_EBX: return "%ebx";
122 case X86_ECX: return "%ecx";
123 case X86_EDX: return "%edx";
124 case X86_ESP: return "%esp";
125 case X86_EBP: return "%ebp";
126 case X86_EDI: return "%edi";
127 case X86_ESI: return "%esi";
133 mono_arch_fregname (int reg)
158 mono_arch_xregname (int reg)
183 mono_x86_patch (unsigned char* code, gpointer target)
185 x86_patch (code, (unsigned char*)target);
204 /* Only if storage == ArgValuetypeInReg */
205 ArgStorage pair_storage [2];
214 gboolean need_stack_align;
215 guint32 stack_align_amount;
216 gboolean vtype_retaddr;
217 /* The index of the vret arg in the argument list */
226 #define FLOAT_PARAM_REGS 0
228 static X86_Reg_No param_regs [] = { 0 };
230 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
231 #define SMALL_STRUCTS_IN_REGS
232 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
236 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
238 ainfo->offset = *stack_size;
240 if (*gr >= PARAM_REGS) {
241 ainfo->storage = ArgOnStack;
242 (*stack_size) += sizeof (gpointer);
245 ainfo->storage = ArgInIReg;
246 ainfo->reg = param_regs [*gr];
252 add_general_pair (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
254 ainfo->offset = *stack_size;
256 g_assert (PARAM_REGS == 0);
258 ainfo->storage = ArgOnStack;
259 (*stack_size) += sizeof (gpointer) * 2;
263 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
265 ainfo->offset = *stack_size;
267 if (*gr >= FLOAT_PARAM_REGS) {
268 ainfo->storage = ArgOnStack;
269 (*stack_size) += is_double ? 8 : 4;
272 /* A double register */
274 ainfo->storage = ArgInDoubleSSEReg;
276 ainfo->storage = ArgInFloatSSEReg;
284 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
286 guint32 *gr, guint32 *fr, guint32 *stack_size)
291 klass = mono_class_from_mono_type (type);
292 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
294 #ifdef SMALL_STRUCTS_IN_REGS
295 if (sig->pinvoke && is_return) {
296 MonoMarshalType *info;
299 * the exact rules are not very well documented, the code below seems to work with the
300 * code generated by gcc 3.3.3 -mno-cygwin.
302 info = mono_marshal_load_type_info (klass);
305 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
307 /* Special case structs with only a float member */
308 if ((info->native_size == 8) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R8)) {
309 ainfo->storage = ArgValuetypeInReg;
310 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
313 if ((info->native_size == 4) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R4)) {
314 ainfo->storage = ArgValuetypeInReg;
315 ainfo->pair_storage [0] = ArgOnFloatFpStack;
318 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
319 ainfo->storage = ArgValuetypeInReg;
320 ainfo->pair_storage [0] = ArgInIReg;
321 ainfo->pair_regs [0] = return_regs [0];
322 if (info->native_size > 4) {
323 ainfo->pair_storage [1] = ArgInIReg;
324 ainfo->pair_regs [1] = return_regs [1];
331 ainfo->offset = *stack_size;
332 ainfo->storage = ArgOnStack;
333 *stack_size += ALIGN_TO (size, sizeof (gpointer));
339 * Obtain information about a call according to the calling convention.
340 * For x86 ELF, see the "System V Application Binary Interface Intel386
341 * Architecture Processor Supplment, Fourth Edition" document for more
343 * For x86 win32, see ???.
346 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
348 guint32 i, gr, fr, pstart;
350 int n = sig->hasthis + sig->param_count;
351 guint32 stack_size = 0;
352 gboolean is_pinvoke = sig->pinvoke;
359 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
360 switch (ret_type->type) {
361 case MONO_TYPE_BOOLEAN:
372 case MONO_TYPE_FNPTR:
373 case MONO_TYPE_CLASS:
374 case MONO_TYPE_OBJECT:
375 case MONO_TYPE_SZARRAY:
376 case MONO_TYPE_ARRAY:
377 case MONO_TYPE_STRING:
378 cinfo->ret.storage = ArgInIReg;
379 cinfo->ret.reg = X86_EAX;
383 cinfo->ret.storage = ArgInIReg;
384 cinfo->ret.reg = X86_EAX;
387 cinfo->ret.storage = ArgOnFloatFpStack;
390 cinfo->ret.storage = ArgOnDoubleFpStack;
392 case MONO_TYPE_GENERICINST:
393 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
394 cinfo->ret.storage = ArgInIReg;
395 cinfo->ret.reg = X86_EAX;
399 case MONO_TYPE_VALUETYPE: {
400 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
402 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
403 if (cinfo->ret.storage == ArgOnStack) {
404 cinfo->vtype_retaddr = TRUE;
405 /* The caller passes the address where the value is stored */
409 case MONO_TYPE_TYPEDBYREF:
410 /* Same as a valuetype with size 12 */
411 cinfo->vtype_retaddr = TRUE;
414 cinfo->ret.storage = ArgNone;
417 g_error ("Can't handle as return value 0x%x", sig->ret->type);
423 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
424 * the first argument, allowing 'this' to be always passed in the first arg reg.
425 * Also do this if the first argument is a reference type, since virtual calls
426 * are sometimes made using calli without sig->hasthis set, like in the delegate
429 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
431 add_general (&gr, &stack_size, cinfo->args + 0);
433 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
436 add_general (&gr, &stack_size, &cinfo->ret);
437 cinfo->vret_arg_index = 1;
441 add_general (&gr, &stack_size, cinfo->args + 0);
443 if (cinfo->vtype_retaddr)
444 add_general (&gr, &stack_size, &cinfo->ret);
447 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
449 fr = FLOAT_PARAM_REGS;
451 /* Emit the signature cookie just before the implicit arguments */
452 add_general (&gr, &stack_size, &cinfo->sig_cookie);
455 for (i = pstart; i < sig->param_count; ++i) {
456 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
459 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
460 /* We allways pass the sig cookie on the stack for simplicity */
462 * Prevent implicit arguments + the sig cookie from being passed
466 fr = FLOAT_PARAM_REGS;
468 /* Emit the signature cookie just before the implicit arguments */
469 add_general (&gr, &stack_size, &cinfo->sig_cookie);
472 if (sig->params [i]->byref) {
473 add_general (&gr, &stack_size, ainfo);
476 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
477 switch (ptype->type) {
478 case MONO_TYPE_BOOLEAN:
481 add_general (&gr, &stack_size, ainfo);
486 add_general (&gr, &stack_size, ainfo);
490 add_general (&gr, &stack_size, ainfo);
495 case MONO_TYPE_FNPTR:
496 case MONO_TYPE_CLASS:
497 case MONO_TYPE_OBJECT:
498 case MONO_TYPE_STRING:
499 case MONO_TYPE_SZARRAY:
500 case MONO_TYPE_ARRAY:
501 add_general (&gr, &stack_size, ainfo);
503 case MONO_TYPE_GENERICINST:
504 if (!mono_type_generic_inst_is_valuetype (ptype)) {
505 add_general (&gr, &stack_size, ainfo);
509 case MONO_TYPE_VALUETYPE:
510 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
512 case MONO_TYPE_TYPEDBYREF:
513 stack_size += sizeof (MonoTypedRef);
514 ainfo->storage = ArgOnStack;
518 add_general_pair (&gr, &stack_size, ainfo);
521 add_float (&fr, &stack_size, ainfo, FALSE);
524 add_float (&fr, &stack_size, ainfo, TRUE);
527 g_error ("unexpected type 0x%x", ptype->type);
528 g_assert_not_reached ();
532 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
534 fr = FLOAT_PARAM_REGS;
536 /* Emit the signature cookie just before the implicit arguments */
537 add_general (&gr, &stack_size, &cinfo->sig_cookie);
540 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
541 cinfo->need_stack_align = TRUE;
542 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
543 stack_size += cinfo->stack_align_amount;
546 cinfo->stack_usage = stack_size;
547 cinfo->reg_usage = gr;
548 cinfo->freg_usage = fr;
553 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
555 int n = sig->hasthis + sig->param_count;
559 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
561 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
563 return get_call_info_internal (gsctx, cinfo, sig);
567 * mono_arch_get_argument_info:
568 * @csig: a method signature
569 * @param_count: the number of parameters to consider
570 * @arg_info: an array to store the result infos
572 * Gathers information on parameters such as size, alignment and
573 * padding. arg_info should be large enought to hold param_count + 1 entries.
575 * Returns the size of the argument area on the stack.
576 * This should be signal safe, since it is called from
577 * mono_arch_find_jit_info ().
578 * FIXME: The metadata calls might not be signal safe.
581 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
583 int len, k, args_size = 0;
589 /* Avoid g_malloc as it is not signal safe */
590 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
591 cinfo = (CallInfo*)g_newa (guint8*, len);
592 memset (cinfo, 0, len);
594 cinfo = get_call_info_internal (NULL, cinfo, csig);
596 arg_info [0].offset = offset;
598 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
599 args_size += sizeof (gpointer);
604 args_size += sizeof (gpointer);
608 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
609 /* Emitted after this */
610 args_size += sizeof (gpointer);
614 arg_info [0].size = args_size;
616 for (k = 0; k < param_count; k++) {
617 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
619 /* ignore alignment for now */
622 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
623 arg_info [k].pad = pad;
625 arg_info [k + 1].pad = 0;
626 arg_info [k + 1].size = size;
628 arg_info [k + 1].offset = offset;
631 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
632 /* Emitted after the first arg */
633 args_size += sizeof (gpointer);
638 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
639 align = MONO_ARCH_FRAME_ALIGNMENT;
642 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
643 arg_info [k].pad = pad;
649 mono_x86_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
654 c1 = get_call_info (NULL, NULL, caller_sig);
655 c2 = get_call_info (NULL, NULL, callee_sig);
656 res = c1->stack_usage >= c2->stack_usage;
657 if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
658 /* An address on the callee's stack is passed as the first argument */
667 static const guchar cpuid_impl [] = {
668 0x55, /* push %ebp */
669 0x89, 0xe5, /* mov %esp,%ebp */
670 0x53, /* push %ebx */
671 0x8b, 0x45, 0x08, /* mov 0x8(%ebp),%eax */
672 0x0f, 0xa2, /* cpuid */
673 0x50, /* push %eax */
674 0x8b, 0x45, 0x10, /* mov 0x10(%ebp),%eax */
675 0x89, 0x18, /* mov %ebx,(%eax) */
676 0x8b, 0x45, 0x14, /* mov 0x14(%ebp),%eax */
677 0x89, 0x08, /* mov %ecx,(%eax) */
678 0x8b, 0x45, 0x18, /* mov 0x18(%ebp),%eax */
679 0x89, 0x10, /* mov %edx,(%eax) */
681 0x8b, 0x55, 0x0c, /* mov 0xc(%ebp),%edx */
682 0x89, 0x02, /* mov %eax,(%edx) */
688 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
691 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
693 #if defined(__native_client__)
694 /* Taken from below, the bug listed in the comment is */
695 /* only valid for non-static cases. */
696 __asm__ __volatile__ ("cpuid"
697 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
703 __asm__ __volatile__ (
706 "movl %%eax, %%edx\n"
707 "xorl $0x200000, %%eax\n"
712 "xorl %%edx, %%eax\n"
713 "andl $0x200000, %%eax\n"
735 /* Have to use the code manager to get around WinXP DEP */
736 static CpuidFunc func = NULL;
739 ptr = mono_global_codeman_reserve (sizeof (cpuid_impl));
740 memcpy (ptr, cpuid_impl, sizeof (cpuid_impl));
741 func = (CpuidFunc)ptr;
743 func (id, p_eax, p_ebx, p_ecx, p_edx);
746 * We use this approach because of issues with gcc and pic code, see:
747 * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
748 __asm__ __volatile__ ("cpuid"
749 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
759 * Initialize the cpu to execute managed code.
762 mono_arch_cpu_init (void)
764 /* spec compliance requires running with double precision */
768 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
769 fpcw &= ~X86_FPCW_PRECC_MASK;
770 fpcw |= X86_FPCW_PREC_DOUBLE;
771 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
772 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
774 _control87 (_PC_53, MCW_PC);
779 * Initialize architecture specific code.
782 mono_arch_init (void)
784 InitializeCriticalSection (&mini_arch_mutex);
786 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
787 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
788 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
790 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
791 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
795 * Cleanup architecture specific code.
798 mono_arch_cleanup (void)
800 DeleteCriticalSection (&mini_arch_mutex);
804 * This function returns the optimizations supported on this cpu.
807 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
809 #if !defined(__native_client__)
810 int eax, ebx, ecx, edx;
816 /* The cpuid function allocates from the global codeman */
819 /* Feature Flags function, flags returned in EDX. */
820 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
821 if (edx & (1 << 15)) {
822 opts |= MONO_OPT_CMOV;
824 opts |= MONO_OPT_FCMOV;
826 *exclude_mask |= MONO_OPT_FCMOV;
828 *exclude_mask |= MONO_OPT_CMOV;
830 opts |= MONO_OPT_SSE2;
832 *exclude_mask |= MONO_OPT_SSE2;
834 #ifdef MONO_ARCH_SIMD_INTRINSICS
835 /*SIMD intrinsics require at least SSE2.*/
836 if (!(opts & MONO_OPT_SSE2))
837 *exclude_mask |= MONO_OPT_SIMD;
842 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
847 * This function test for all SSE functions supported.
849 * Returns a bitmask corresponding to all supported versions.
853 mono_arch_cpu_enumerate_simd_versions (void)
855 int eax, ebx, ecx, edx;
856 guint32 sse_opts = 0;
859 /* The cpuid function allocates from the global codeman */
862 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
864 sse_opts |= SIMD_VERSION_SSE1;
866 sse_opts |= SIMD_VERSION_SSE2;
868 sse_opts |= SIMD_VERSION_SSE3;
870 sse_opts |= SIMD_VERSION_SSSE3;
872 sse_opts |= SIMD_VERSION_SSE41;
874 sse_opts |= SIMD_VERSION_SSE42;
877 /* Yes, all this needs to be done to check for sse4a.
878 See: "Amd: CPUID Specification"
880 if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
881 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
882 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
883 cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
885 sse_opts |= SIMD_VERSION_SSE4a;
894 * Determine whenever the trap whose info is in SIGINFO is caused by
898 mono_arch_is_int_overflow (void *sigctx, void *info)
903 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
905 ip = (guint8*)ctx.eip;
907 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
911 switch (x86_modrm_rm (ip [1])) {
931 g_assert_not_reached ();
943 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
948 for (i = 0; i < cfg->num_varinfo; i++) {
949 MonoInst *ins = cfg->varinfo [i];
950 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
953 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
956 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
957 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
960 /* we dont allocate I1 to registers because there is no simply way to sign extend
961 * 8bit quantities in caller saved registers on x86 */
962 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
963 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
964 g_assert (i == vmv->idx);
965 vars = g_list_prepend (vars, vmv);
969 vars = mono_varlist_sort (cfg, vars, 0);
975 mono_arch_get_global_int_regs (MonoCompile *cfg)
979 /* we can use 3 registers for global allocation */
980 regs = g_list_prepend (regs, (gpointer)X86_EBX);
981 regs = g_list_prepend (regs, (gpointer)X86_ESI);
982 regs = g_list_prepend (regs, (gpointer)X86_EDI);
988 * mono_arch_regalloc_cost:
990 * Return the cost, in number of memory references, of the action of
991 * allocating the variable VMV into a register during global register
995 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
997 MonoInst *ins = cfg->varinfo [vmv->idx];
999 if (cfg->method->save_lmf)
1000 /* The register is already saved */
1001 return (ins->opcode == OP_ARG) ? 1 : 0;
1003 /* push+pop+possible load if it is an argument */
1004 return (ins->opcode == OP_ARG) ? 3 : 2;
1008 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
1010 static int inited = FALSE;
1011 static int count = 0;
1013 if (cfg->arch.need_stack_frame_inited) {
1014 g_assert (cfg->arch.need_stack_frame == flag);
1018 cfg->arch.need_stack_frame = flag;
1019 cfg->arch.need_stack_frame_inited = TRUE;
1025 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
1030 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
1034 needs_stack_frame (MonoCompile *cfg)
1036 MonoMethodSignature *sig;
1037 MonoMethodHeader *header;
1038 gboolean result = FALSE;
1040 #if defined(__APPLE__)
1041 /*OSX requires stack frame code to have the correct alignment. */
1045 if (cfg->arch.need_stack_frame_inited)
1046 return cfg->arch.need_stack_frame;
1048 header = cfg->header;
1049 sig = mono_method_signature (cfg->method);
1051 if (cfg->disable_omit_fp)
1053 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1055 else if (cfg->method->save_lmf)
1057 else if (cfg->stack_offset)
1059 else if (cfg->param_area)
1061 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1063 else if (header->num_clauses)
1065 else if (sig->param_count + sig->hasthis)
1067 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1069 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1070 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1073 set_needs_stack_frame (cfg, result);
1075 return cfg->arch.need_stack_frame;
1079 * Set var information according to the calling convention. X86 version.
1080 * The locals var stuff should most likely be split in another method.
1083 mono_arch_allocate_vars (MonoCompile *cfg)
1085 MonoMethodSignature *sig;
1086 MonoMethodHeader *header;
1088 guint32 locals_stack_size, locals_stack_align;
1093 header = cfg->header;
1094 sig = mono_method_signature (cfg->method);
1096 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1098 cfg->frame_reg = X86_EBP;
1101 /* Reserve space to save LMF and caller saved registers */
1103 if (cfg->method->save_lmf) {
1104 offset += sizeof (MonoLMF);
1106 if (cfg->used_int_regs & (1 << X86_EBX)) {
1110 if (cfg->used_int_regs & (1 << X86_EDI)) {
1114 if (cfg->used_int_regs & (1 << X86_ESI)) {
1119 switch (cinfo->ret.storage) {
1120 case ArgValuetypeInReg:
1121 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1123 cfg->ret->opcode = OP_REGOFFSET;
1124 cfg->ret->inst_basereg = X86_EBP;
1125 cfg->ret->inst_offset = - offset;
1131 /* Allocate locals */
1132 offsets = mono_allocate_stack_slots (cfg, &locals_stack_size, &locals_stack_align);
1133 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1134 char *mname = mono_method_full_name (cfg->method, TRUE);
1135 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1136 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1140 if (locals_stack_align) {
1141 offset += (locals_stack_align - 1);
1142 offset &= ~(locals_stack_align - 1);
1144 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1145 cfg->locals_max_stack_offset = - offset;
1147 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1148 * have locals larger than 8 bytes we need to make sure that
1149 * they have the appropriate offset.
1151 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1152 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1153 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1154 if (offsets [i] != -1) {
1155 MonoInst *inst = cfg->varinfo [i];
1156 inst->opcode = OP_REGOFFSET;
1157 inst->inst_basereg = X86_EBP;
1158 inst->inst_offset = - (offset + offsets [i]);
1159 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1162 offset += locals_stack_size;
1166 * Allocate arguments+return value
1169 switch (cinfo->ret.storage) {
1171 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1173 * In the new IR, the cfg->vret_addr variable represents the
1174 * vtype return value.
1176 cfg->vret_addr->opcode = OP_REGOFFSET;
1177 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1178 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1179 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1180 printf ("vret_addr =");
1181 mono_print_ins (cfg->vret_addr);
1184 cfg->ret->opcode = OP_REGOFFSET;
1185 cfg->ret->inst_basereg = X86_EBP;
1186 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1189 case ArgValuetypeInReg:
1192 cfg->ret->opcode = OP_REGVAR;
1193 cfg->ret->inst_c0 = cinfo->ret.reg;
1194 cfg->ret->dreg = cinfo->ret.reg;
1197 case ArgOnFloatFpStack:
1198 case ArgOnDoubleFpStack:
1201 g_assert_not_reached ();
1204 if (sig->call_convention == MONO_CALL_VARARG) {
1205 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1206 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1209 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1210 ArgInfo *ainfo = &cinfo->args [i];
1211 inst = cfg->args [i];
1212 if (inst->opcode != OP_REGVAR) {
1213 inst->opcode = OP_REGOFFSET;
1214 inst->inst_basereg = X86_EBP;
1216 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1219 cfg->stack_offset = offset;
1223 mono_arch_create_vars (MonoCompile *cfg)
1225 MonoMethodSignature *sig;
1228 sig = mono_method_signature (cfg->method);
1230 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1232 if (cinfo->ret.storage == ArgValuetypeInReg)
1233 cfg->ret_var_is_local = TRUE;
1234 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1235 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1240 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1241 * so we try to do it just once when we have multiple fp arguments in a row.
1242 * We don't use this mechanism generally because for int arguments the generated code
1243 * is slightly bigger and new generation cpus optimize away the dependency chains
1244 * created by push instructions on the esp value.
1245 * fp_arg_setup is the first argument in the execution sequence where the esp register
1248 static G_GNUC_UNUSED int
1249 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1254 for (; start_arg < sig->param_count; ++start_arg) {
1255 t = mini_type_get_underlying_type (NULL, sig->params [start_arg]);
1256 if (!t->byref && t->type == MONO_TYPE_R8) {
1257 fp_space += sizeof (double);
1258 *fp_arg_setup = start_arg;
1267 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1269 MonoMethodSignature *tmp_sig;
1271 /* FIXME: Add support for signature tokens to AOT */
1272 cfg->disable_aot = TRUE;
1275 * mono_ArgIterator_Setup assumes the signature cookie is
1276 * passed first and all the arguments which were before it are
1277 * passed on the stack after the signature. So compensate by
1278 * passing a different signature.
1280 tmp_sig = mono_metadata_signature_dup (call->signature);
1281 tmp_sig->param_count -= call->signature->sentinelpos;
1282 tmp_sig->sentinelpos = 0;
1283 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1285 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1290 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1295 LLVMCallInfo *linfo;
1298 n = sig->param_count + sig->hasthis;
1300 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1302 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1305 * LLVM always uses the native ABI while we use our own ABI, the
1306 * only difference is the handling of vtypes:
1307 * - we only pass/receive them in registers in some cases, and only
1308 * in 1 or 2 integer registers.
1310 if (cinfo->ret.storage == ArgValuetypeInReg) {
1312 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1313 cfg->disable_llvm = TRUE;
1317 cfg->exception_message = g_strdup ("vtype ret in call");
1318 cfg->disable_llvm = TRUE;
1320 linfo->ret.storage = LLVMArgVtypeInReg;
1321 for (j = 0; j < 2; ++j)
1322 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1326 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1327 /* Vtype returned using a hidden argument */
1328 linfo->ret.storage = LLVMArgVtypeRetAddr;
1329 linfo->vret_arg_index = cinfo->vret_arg_index;
1332 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != ArgInIReg) {
1334 cfg->exception_message = g_strdup ("vtype ret in call");
1335 cfg->disable_llvm = TRUE;
1338 for (i = 0; i < n; ++i) {
1339 ainfo = cinfo->args + i;
1341 if (i >= sig->hasthis)
1342 t = sig->params [i - sig->hasthis];
1344 t = &mono_defaults.int_class->byval_arg;
1346 linfo->args [i].storage = LLVMArgNone;
1348 switch (ainfo->storage) {
1350 linfo->args [i].storage = LLVMArgInIReg;
1352 case ArgInDoubleSSEReg:
1353 case ArgInFloatSSEReg:
1354 linfo->args [i].storage = LLVMArgInFPReg;
1357 if (MONO_TYPE_ISSTRUCT (t)) {
1358 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1359 /* LLVM seems to allocate argument space for empty structures too */
1360 linfo->args [i].storage = LLVMArgNone;
1362 linfo->args [i].storage = LLVMArgVtypeByVal;
1364 linfo->args [i].storage = LLVMArgInIReg;
1366 if (t->type == MONO_TYPE_R4)
1367 linfo->args [i].storage = LLVMArgInFPReg;
1368 else if (t->type == MONO_TYPE_R8)
1369 linfo->args [i].storage = LLVMArgInFPReg;
1373 case ArgValuetypeInReg:
1375 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1376 cfg->disable_llvm = TRUE;
1380 cfg->exception_message = g_strdup ("vtype arg");
1381 cfg->disable_llvm = TRUE;
1383 linfo->args [i].storage = LLVMArgVtypeInReg;
1384 for (j = 0; j < 2; ++j)
1385 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1389 cfg->exception_message = g_strdup ("ainfo->storage");
1390 cfg->disable_llvm = TRUE;
1400 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1403 MonoMethodSignature *sig;
1406 int sentinelpos = 0;
1408 sig = call->signature;
1409 n = sig->param_count + sig->hasthis;
1411 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1413 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1414 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1416 if (cinfo->need_stack_align) {
1417 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1418 arg->dreg = X86_ESP;
1419 arg->sreg1 = X86_ESP;
1420 arg->inst_imm = cinfo->stack_align_amount;
1421 MONO_ADD_INS (cfg->cbb, arg);
1424 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1425 if (cinfo->ret.storage == ArgValuetypeInReg) {
1427 * Tell the JIT to use a more efficient calling convention: call using
1428 * OP_CALL, compute the result location after the call, and save the
1431 call->vret_in_reg = TRUE;
1433 NULLIFY_INS (call->vret_var);
1437 /* Handle the case where there are no implicit arguments */
1438 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1439 emit_sig_cookie (cfg, call, cinfo);
1442 /* Arguments are pushed in the reverse order */
1443 for (i = n - 1; i >= 0; i --) {
1444 ArgInfo *ainfo = cinfo->args + i;
1447 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1448 /* Push the vret arg before the first argument */
1450 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1451 vtarg->type = STACK_MP;
1452 vtarg->sreg1 = call->vret_var->dreg;
1453 MONO_ADD_INS (cfg->cbb, vtarg);
1456 if (i >= sig->hasthis)
1457 t = sig->params [i - sig->hasthis];
1459 t = &mono_defaults.int_class->byval_arg;
1460 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1462 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1464 in = call->args [i];
1465 arg->cil_code = in->cil_code;
1466 arg->sreg1 = in->dreg;
1467 arg->type = in->type;
1469 g_assert (in->dreg != -1);
1471 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1475 g_assert (in->klass);
1477 if (t->type == MONO_TYPE_TYPEDBYREF) {
1478 size = sizeof (MonoTypedRef);
1479 align = sizeof (gpointer);
1482 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1486 arg->opcode = OP_OUTARG_VT;
1487 arg->sreg1 = in->dreg;
1488 arg->klass = in->klass;
1489 arg->backend.size = size;
1491 MONO_ADD_INS (cfg->cbb, arg);
1495 switch (ainfo->storage) {
1497 arg->opcode = OP_X86_PUSH;
1499 if (t->type == MONO_TYPE_R4) {
1500 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1501 arg->opcode = OP_STORER4_MEMBASE_REG;
1502 arg->inst_destbasereg = X86_ESP;
1503 arg->inst_offset = 0;
1504 } else if (t->type == MONO_TYPE_R8) {
1505 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1506 arg->opcode = OP_STORER8_MEMBASE_REG;
1507 arg->inst_destbasereg = X86_ESP;
1508 arg->inst_offset = 0;
1509 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1511 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1516 g_assert_not_reached ();
1519 MONO_ADD_INS (cfg->cbb, arg);
1522 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1523 /* Emit the signature cookie just before the implicit arguments */
1524 emit_sig_cookie (cfg, call, cinfo);
1528 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1531 if (cinfo->ret.storage == ArgValuetypeInReg) {
1534 else if (cinfo->ret.storage == ArgInIReg) {
1536 /* The return address is passed in a register */
1537 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1538 vtarg->sreg1 = call->inst.dreg;
1539 vtarg->dreg = mono_alloc_ireg (cfg);
1540 MONO_ADD_INS (cfg->cbb, vtarg);
1542 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1543 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1545 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1546 vtarg->type = STACK_MP;
1547 vtarg->sreg1 = call->vret_var->dreg;
1548 MONO_ADD_INS (cfg->cbb, vtarg);
1551 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1552 if (cinfo->ret.storage != ArgValuetypeInReg)
1553 cinfo->stack_usage -= 4;
1556 call->stack_usage = cinfo->stack_usage;
1560 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1563 int size = ins->backend.size;
1566 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1567 arg->sreg1 = src->dreg;
1569 MONO_ADD_INS (cfg->cbb, arg);
1570 } else if (size <= 20) {
1571 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1572 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1574 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1575 arg->inst_basereg = src->dreg;
1576 arg->inst_offset = 0;
1577 arg->inst_imm = size;
1579 MONO_ADD_INS (cfg->cbb, arg);
1584 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1586 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1589 if (ret->type == MONO_TYPE_R4) {
1590 if (COMPILE_LLVM (cfg))
1591 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1594 } else if (ret->type == MONO_TYPE_R8) {
1595 if (COMPILE_LLVM (cfg))
1596 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1599 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1600 if (COMPILE_LLVM (cfg))
1601 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1603 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1604 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1610 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1614 * Allow tracing to work with this interface (with an optional argument)
1617 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1621 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1622 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1624 /* if some args are passed in registers, we need to save them here */
1625 x86_push_reg (code, X86_EBP);
1627 if (cfg->compile_aot) {
1628 x86_push_imm (code, cfg->method);
1629 x86_mov_reg_imm (code, X86_EAX, func);
1630 x86_call_reg (code, X86_EAX);
1632 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1633 x86_push_imm (code, cfg->method);
1634 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1635 x86_call_code (code, 0);
1637 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1651 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1654 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1655 MonoMethod *method = cfg->method;
1656 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1658 switch (ret_type->type) {
1659 case MONO_TYPE_VOID:
1660 /* special case string .ctor icall */
1661 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1662 save_mode = SAVE_EAX;
1663 stack_usage = enable_arguments ? 8 : 4;
1665 save_mode = SAVE_NONE;
1669 save_mode = SAVE_EAX_EDX;
1670 stack_usage = enable_arguments ? 16 : 8;
1674 save_mode = SAVE_FP;
1675 stack_usage = enable_arguments ? 16 : 8;
1677 case MONO_TYPE_GENERICINST:
1678 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1679 save_mode = SAVE_EAX;
1680 stack_usage = enable_arguments ? 8 : 4;
1684 case MONO_TYPE_VALUETYPE:
1685 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1686 save_mode = SAVE_STRUCT;
1687 stack_usage = enable_arguments ? 4 : 0;
1690 save_mode = SAVE_EAX;
1691 stack_usage = enable_arguments ? 8 : 4;
1695 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1697 switch (save_mode) {
1699 x86_push_reg (code, X86_EDX);
1700 x86_push_reg (code, X86_EAX);
1701 if (enable_arguments) {
1702 x86_push_reg (code, X86_EDX);
1703 x86_push_reg (code, X86_EAX);
1708 x86_push_reg (code, X86_EAX);
1709 if (enable_arguments) {
1710 x86_push_reg (code, X86_EAX);
1715 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1716 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1717 if (enable_arguments) {
1718 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1719 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1724 if (enable_arguments) {
1725 x86_push_membase (code, X86_EBP, 8);
1734 if (cfg->compile_aot) {
1735 x86_push_imm (code, method);
1736 x86_mov_reg_imm (code, X86_EAX, func);
1737 x86_call_reg (code, X86_EAX);
1739 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1740 x86_push_imm (code, method);
1741 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1742 x86_call_code (code, 0);
1745 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1747 switch (save_mode) {
1749 x86_pop_reg (code, X86_EAX);
1750 x86_pop_reg (code, X86_EDX);
1753 x86_pop_reg (code, X86_EAX);
1756 x86_fld_membase (code, X86_ESP, 0, TRUE);
1757 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1764 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1769 #define EMIT_COND_BRANCH(ins,cond,sign) \
1770 if (ins->inst_true_bb->native_offset) { \
1771 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1773 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1774 if ((cfg->opt & MONO_OPT_BRANCH) && \
1775 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1776 x86_branch8 (code, cond, 0, sign); \
1778 x86_branch32 (code, cond, 0, sign); \
1782 * Emit an exception if condition is fail and
1783 * if possible do a directly branch to target
1785 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1787 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1788 if (tins == NULL) { \
1789 mono_add_patch_info (cfg, code - cfg->native_code, \
1790 MONO_PATCH_INFO_EXC, exc_name); \
1791 x86_branch32 (code, cond, 0, signed); \
1793 EMIT_COND_BRANCH (tins, cond, signed); \
1797 #define EMIT_FPCOMPARE(code) do { \
1798 x86_fcompp (code); \
1799 x86_fnstsw (code); \
1804 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1806 gboolean needs_paddings = TRUE;
1809 if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
1811 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1813 if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && strstr (cfg->method->name, info->name))
1814 needs_paddings = FALSE; /* A call to the wrapped function */
1818 if (cfg->compile_aot)
1819 needs_paddings = FALSE;
1820 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1821 This is required for code patching to be safe on SMP machines.
1823 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1824 if (needs_paddings && pad_size)
1825 x86_padding (code, pad_size);
1827 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1828 x86_call_code (code, 0);
1833 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1836 * mono_peephole_pass_1:
1838 * Perform peephole opts which should/can be performed before local regalloc
1841 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1845 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1846 MonoInst *last_ins = ins->prev;
1848 switch (ins->opcode) {
1851 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1853 * X86_LEA is like ADD, but doesn't have the
1854 * sreg1==dreg restriction.
1856 ins->opcode = OP_X86_LEA_MEMBASE;
1857 ins->inst_basereg = ins->sreg1;
1858 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1859 ins->opcode = OP_X86_INC_REG;
1863 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1864 ins->opcode = OP_X86_LEA_MEMBASE;
1865 ins->inst_basereg = ins->sreg1;
1866 ins->inst_imm = -ins->inst_imm;
1867 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1868 ins->opcode = OP_X86_DEC_REG;
1870 case OP_COMPARE_IMM:
1871 case OP_ICOMPARE_IMM:
1872 /* OP_COMPARE_IMM (reg, 0)
1874 * OP_X86_TEST_NULL (reg)
1877 ins->opcode = OP_X86_TEST_NULL;
1879 case OP_X86_COMPARE_MEMBASE_IMM:
1881 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1882 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1884 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1885 * OP_COMPARE_IMM reg, imm
1887 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1889 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1890 ins->inst_basereg == last_ins->inst_destbasereg &&
1891 ins->inst_offset == last_ins->inst_offset) {
1892 ins->opcode = OP_COMPARE_IMM;
1893 ins->sreg1 = last_ins->sreg1;
1895 /* check if we can remove cmp reg,0 with test null */
1897 ins->opcode = OP_X86_TEST_NULL;
1901 case OP_X86_PUSH_MEMBASE:
1902 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1903 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1904 ins->inst_basereg == last_ins->inst_destbasereg &&
1905 ins->inst_offset == last_ins->inst_offset) {
1906 ins->opcode = OP_X86_PUSH;
1907 ins->sreg1 = last_ins->sreg1;
1912 mono_peephole_ins (bb, ins);
1917 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1921 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1922 switch (ins->opcode) {
1924 /* reg = 0 -> XOR (reg, reg) */
1925 /* XOR sets cflags on x86, so we cant do it always */
1926 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1929 ins->opcode = OP_IXOR;
1930 ins->sreg1 = ins->dreg;
1931 ins->sreg2 = ins->dreg;
1934 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1935 * since it takes 3 bytes instead of 7.
1937 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
1938 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1939 ins2->opcode = OP_STORE_MEMBASE_REG;
1940 ins2->sreg1 = ins->dreg;
1942 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1943 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1944 ins2->sreg1 = ins->dreg;
1946 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1947 /* Continue iteration */
1956 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1957 ins->opcode = OP_X86_INC_REG;
1961 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1962 ins->opcode = OP_X86_DEC_REG;
1966 mono_peephole_ins (bb, ins);
1971 * mono_arch_lowering_pass:
1973 * Converts complex opcodes into simpler ones so that each IR instruction
1974 * corresponds to one machine instruction.
1977 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1979 MonoInst *ins, *next;
1982 * FIXME: Need to add more instructions, but the current machine
1983 * description can't model some parts of the composite instructions like
1986 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
1987 switch (ins->opcode) {
1990 case OP_IDIV_UN_IMM:
1991 case OP_IREM_UN_IMM:
1993 * Keep the cases where we could generated optimized code, otherwise convert
1994 * to the non-imm variant.
1996 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
1998 mono_decompose_op_imm (cfg, bb, ins);
2005 bb->max_vreg = cfg->next_vreg;
2009 branch_cc_table [] = {
2010 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2011 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2012 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2015 /* Maps CMP_... constants to X86_CC_... constants */
2018 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2019 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2023 cc_signed_table [] = {
2024 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2025 FALSE, FALSE, FALSE, FALSE
2028 static unsigned char*
2029 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2031 #define XMM_TEMP_REG 0
2032 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2033 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2034 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2035 /* optimize by assigning a local var for this use so we avoid
2036 * the stack manipulations */
2037 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2038 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2039 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2040 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2041 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2043 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2045 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2048 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2049 x86_fnstcw_membase(code, X86_ESP, 0);
2050 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2051 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2052 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2053 x86_fldcw_membase (code, X86_ESP, 2);
2055 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2056 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2057 x86_pop_reg (code, dreg);
2058 /* FIXME: need the high register
2059 * x86_pop_reg (code, dreg_high);
2062 x86_push_reg (code, X86_EAX); // SP = SP - 4
2063 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2064 x86_pop_reg (code, dreg);
2066 x86_fldcw_membase (code, X86_ESP, 0);
2067 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2070 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2072 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2076 static unsigned char*
2077 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2079 int sreg = tree->sreg1;
2080 int need_touch = FALSE;
2082 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2091 * If requested stack size is larger than one page,
2092 * perform stack-touch operation
2095 * Generate stack probe code.
2096 * Under Windows, it is necessary to allocate one page at a time,
2097 * "touching" stack after each successful sub-allocation. This is
2098 * because of the way stack growth is implemented - there is a
2099 * guard page before the lowest stack page that is currently commited.
2100 * Stack normally grows sequentially so OS traps access to the
2101 * guard page and commits more pages when needed.
2103 x86_test_reg_imm (code, sreg, ~0xFFF);
2104 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2106 br[2] = code; /* loop */
2107 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2108 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2111 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2112 * that follows only initializes the last part of the area.
2114 /* Same as the init code below with size==0x1000 */
2115 if (tree->flags & MONO_INST_INIT) {
2116 x86_push_reg (code, X86_EAX);
2117 x86_push_reg (code, X86_ECX);
2118 x86_push_reg (code, X86_EDI);
2119 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2120 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2121 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2123 x86_prefix (code, X86_REP_PREFIX);
2125 x86_pop_reg (code, X86_EDI);
2126 x86_pop_reg (code, X86_ECX);
2127 x86_pop_reg (code, X86_EAX);
2130 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2131 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2132 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2133 x86_patch (br[3], br[2]);
2134 x86_test_reg_reg (code, sreg, sreg);
2135 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2136 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2138 br[1] = code; x86_jump8 (code, 0);
2140 x86_patch (br[0], code);
2141 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2142 x86_patch (br[1], code);
2143 x86_patch (br[4], code);
2146 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2148 if (tree->flags & MONO_INST_INIT) {
2150 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2151 x86_push_reg (code, X86_EAX);
2154 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2155 x86_push_reg (code, X86_ECX);
2158 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2159 x86_push_reg (code, X86_EDI);
2163 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2164 if (sreg != X86_ECX)
2165 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2166 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2168 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2170 x86_prefix (code, X86_REP_PREFIX);
2173 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2174 x86_pop_reg (code, X86_EDI);
2175 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2176 x86_pop_reg (code, X86_ECX);
2177 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2178 x86_pop_reg (code, X86_EAX);
2185 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2187 /* Move return value to the target register */
2188 switch (ins->opcode) {
2191 case OP_CALL_MEMBASE:
2192 if (ins->dreg != X86_EAX)
2193 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2203 mono_x86_have_tls_get (void)
2206 guint32 *ins = (guint32*)pthread_getspecific;
2208 * We're looking for these two instructions:
2210 * mov 0x4(%esp),%eax
2211 * mov %gs:0x48(,%eax,4),%eax
2213 return ins [0] == 0x0424448b && ins [1] == 0x85048b65 && ins [2] == 0x00000048;
2220 * mono_x86_emit_tls_get:
2221 * @code: buffer to store code to
2222 * @dreg: hard register where to place the result
2223 * @tls_offset: offset info
2225 * mono_x86_emit_tls_get emits in @code the native code that puts in
2226 * the dreg register the item in the thread local storage identified
2229 * Returns: a pointer to the end of the stored code
2232 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2234 #if defined(__APPLE__)
2235 x86_prefix (code, X86_GS_PREFIX);
2236 x86_mov_reg_mem (code, dreg, 0x48 + tls_offset * 4, 4);
2237 #elif defined(TARGET_WIN32)
2239 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2240 * Journal and/or a disassembly of the TlsGet () function.
2242 g_assert (tls_offset < 64);
2243 x86_prefix (code, X86_FS_PREFIX);
2244 x86_mov_reg_mem (code, dreg, 0x18, 4);
2245 /* Dunno what this does but TlsGetValue () contains it */
2246 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2247 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2249 if (optimize_for_xen) {
2250 x86_prefix (code, X86_GS_PREFIX);
2251 x86_mov_reg_mem (code, dreg, 0, 4);
2252 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2254 x86_prefix (code, X86_GS_PREFIX);
2255 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2262 * emit_load_volatile_arguments:
2264 * Load volatile arguments from the stack to the original input registers.
2265 * Required before a tail call.
2268 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2270 MonoMethod *method = cfg->method;
2271 MonoMethodSignature *sig;
2276 /* FIXME: Generate intermediate code instead */
2278 sig = mono_method_signature (method);
2280 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2282 /* This is the opposite of the code in emit_prolog */
2284 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2285 ArgInfo *ainfo = cinfo->args + i;
2287 inst = cfg->args [i];
2289 if (sig->hasthis && (i == 0))
2290 arg_type = &mono_defaults.object_class->byval_arg;
2292 arg_type = sig->params [i - sig->hasthis];
2295 * On x86, the arguments are either in their original stack locations, or in
2298 if (inst->opcode == OP_REGVAR) {
2299 g_assert (ainfo->storage == ArgOnStack);
2301 x86_mov_membase_reg (code, X86_EBP, inst->inst_offset, inst->dreg, 4);
2308 #define REAL_PRINT_REG(text,reg) \
2309 mono_assert (reg >= 0); \
2310 x86_push_reg (code, X86_EAX); \
2311 x86_push_reg (code, X86_EDX); \
2312 x86_push_reg (code, X86_ECX); \
2313 x86_push_reg (code, reg); \
2314 x86_push_imm (code, reg); \
2315 x86_push_imm (code, text " %d %p\n"); \
2316 x86_mov_reg_imm (code, X86_EAX, printf); \
2317 x86_call_reg (code, X86_EAX); \
2318 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2319 x86_pop_reg (code, X86_ECX); \
2320 x86_pop_reg (code, X86_EDX); \
2321 x86_pop_reg (code, X86_EAX);
2323 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2324 #ifdef __native__client_codegen__
2325 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2328 /* benchmark and set based on cpu */
2329 #define LOOP_ALIGNMENT 8
2330 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2334 #if defined(__native_client__) || defined(__native_client_codegen__)
2338 #ifdef __native_client_gc__
2339 __nacl_suspend_thread_if_needed();
2345 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2350 guint8 *code = cfg->native_code + cfg->code_len;
2353 if (cfg->opt & MONO_OPT_LOOP) {
2354 int pad, align = LOOP_ALIGNMENT;
2355 /* set alignment depending on cpu */
2356 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2358 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2359 x86_padding (code, pad);
2360 cfg->code_len += pad;
2361 bb->native_offset = cfg->code_len;
2364 #ifdef __native_client_codegen__
2366 /* For Native Client, all indirect call/jump targets must be */
2367 /* 32-byte aligned. Exception handler blocks are jumped to */
2368 /* indirectly as well. */
2369 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2370 (bb->flags & BB_EXCEPTION_HANDLER);
2372 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2373 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2374 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2375 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2376 cfg->code_len += pad;
2377 bb->native_offset = cfg->code_len;
2380 #endif /* __native_client_codegen__ */
2381 if (cfg->verbose_level > 2)
2382 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2384 cpos = bb->max_offset;
2386 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2387 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2388 g_assert (!cfg->compile_aot);
2391 cov->data [bb->dfn].cil_code = bb->cil_code;
2392 /* this is not thread save, but good enough */
2393 x86_inc_mem (code, &cov->data [bb->dfn].count);
2396 offset = code - cfg->native_code;
2398 mono_debug_open_block (cfg, bb, offset);
2400 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2401 x86_breakpoint (code);
2403 MONO_BB_FOR_EACH_INS (bb, ins) {
2404 offset = code - cfg->native_code;
2406 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2408 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2410 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2411 cfg->code_size *= 2;
2412 cfg->native_code = mono_realloc_native_code(cfg);
2413 code = cfg->native_code + offset;
2414 mono_jit_stats.code_reallocs++;
2417 if (cfg->debug_info)
2418 mono_debug_record_line_number (cfg, ins, offset);
2420 switch (ins->opcode) {
2422 x86_mul_reg (code, ins->sreg2, TRUE);
2425 x86_mul_reg (code, ins->sreg2, FALSE);
2427 case OP_X86_SETEQ_MEMBASE:
2428 case OP_X86_SETNE_MEMBASE:
2429 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2430 ins->inst_basereg, ins->inst_offset, TRUE);
2432 case OP_STOREI1_MEMBASE_IMM:
2433 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2435 case OP_STOREI2_MEMBASE_IMM:
2436 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2438 case OP_STORE_MEMBASE_IMM:
2439 case OP_STOREI4_MEMBASE_IMM:
2440 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2442 case OP_STOREI1_MEMBASE_REG:
2443 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2445 case OP_STOREI2_MEMBASE_REG:
2446 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2448 case OP_STORE_MEMBASE_REG:
2449 case OP_STOREI4_MEMBASE_REG:
2450 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2452 case OP_STORE_MEM_IMM:
2453 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2456 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2460 /* These are created by the cprop pass so they use inst_imm as the source */
2461 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2464 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2467 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2469 case OP_LOAD_MEMBASE:
2470 case OP_LOADI4_MEMBASE:
2471 case OP_LOADU4_MEMBASE:
2472 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2474 case OP_LOADU1_MEMBASE:
2475 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2477 case OP_LOADI1_MEMBASE:
2478 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2480 case OP_LOADU2_MEMBASE:
2481 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2483 case OP_LOADI2_MEMBASE:
2484 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2486 case OP_ICONV_TO_I1:
2488 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2490 case OP_ICONV_TO_I2:
2492 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2494 case OP_ICONV_TO_U1:
2495 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2497 case OP_ICONV_TO_U2:
2498 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2502 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2504 case OP_COMPARE_IMM:
2505 case OP_ICOMPARE_IMM:
2506 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2508 case OP_X86_COMPARE_MEMBASE_REG:
2509 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2511 case OP_X86_COMPARE_MEMBASE_IMM:
2512 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2514 case OP_X86_COMPARE_MEMBASE8_IMM:
2515 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2517 case OP_X86_COMPARE_REG_MEMBASE:
2518 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2520 case OP_X86_COMPARE_MEM_IMM:
2521 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2523 case OP_X86_TEST_NULL:
2524 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2526 case OP_X86_ADD_MEMBASE_IMM:
2527 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2529 case OP_X86_ADD_REG_MEMBASE:
2530 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2532 case OP_X86_SUB_MEMBASE_IMM:
2533 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2535 case OP_X86_SUB_REG_MEMBASE:
2536 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2538 case OP_X86_AND_MEMBASE_IMM:
2539 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2541 case OP_X86_OR_MEMBASE_IMM:
2542 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2544 case OP_X86_XOR_MEMBASE_IMM:
2545 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2547 case OP_X86_ADD_MEMBASE_REG:
2548 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2550 case OP_X86_SUB_MEMBASE_REG:
2551 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2553 case OP_X86_AND_MEMBASE_REG:
2554 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2556 case OP_X86_OR_MEMBASE_REG:
2557 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2559 case OP_X86_XOR_MEMBASE_REG:
2560 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2562 case OP_X86_INC_MEMBASE:
2563 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2565 case OP_X86_INC_REG:
2566 x86_inc_reg (code, ins->dreg);
2568 case OP_X86_DEC_MEMBASE:
2569 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2571 case OP_X86_DEC_REG:
2572 x86_dec_reg (code, ins->dreg);
2574 case OP_X86_MUL_REG_MEMBASE:
2575 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2577 case OP_X86_AND_REG_MEMBASE:
2578 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2580 case OP_X86_OR_REG_MEMBASE:
2581 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2583 case OP_X86_XOR_REG_MEMBASE:
2584 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2587 x86_breakpoint (code);
2589 case OP_RELAXED_NOP:
2590 x86_prefix (code, X86_REP_PREFIX);
2598 case OP_DUMMY_STORE:
2599 case OP_NOT_REACHED:
2602 case OP_SEQ_POINT: {
2605 if (cfg->compile_aot)
2609 * Read from the single stepping trigger page. This will cause a
2610 * SIGSEGV when single stepping is enabled.
2611 * We do this _before_ the breakpoint, so single stepping after
2612 * a breakpoint is hit will step to the next IL offset.
2614 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2615 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2617 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2620 * A placeholder for a possible breakpoint inserted by
2621 * mono_arch_set_breakpoint ().
2623 for (i = 0; i < 6; ++i)
2630 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2634 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2639 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2643 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2648 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2652 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2657 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2661 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2664 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2668 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2673 * The code is the same for div/rem, the allocator will allocate dreg
2674 * to RAX/RDX as appropriate.
2676 if (ins->sreg2 == X86_EDX) {
2677 /* cdq clobbers this */
2678 x86_push_reg (code, ins->sreg2);
2680 x86_div_membase (code, X86_ESP, 0, TRUE);
2681 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2684 x86_div_reg (code, ins->sreg2, TRUE);
2689 if (ins->sreg2 == X86_EDX) {
2690 x86_push_reg (code, ins->sreg2);
2691 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2692 x86_div_membase (code, X86_ESP, 0, FALSE);
2693 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2695 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2696 x86_div_reg (code, ins->sreg2, FALSE);
2700 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2702 x86_div_reg (code, ins->sreg2, TRUE);
2705 int power = mono_is_power_of_two (ins->inst_imm);
2707 g_assert (ins->sreg1 == X86_EAX);
2708 g_assert (ins->dreg == X86_EAX);
2709 g_assert (power >= 0);
2712 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2714 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2716 * If the divident is >= 0, this does not nothing. If it is positive, it
2717 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2719 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2720 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2721 } else if (power == 0) {
2722 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2724 /* Based on gcc code */
2726 /* Add compensation for negative dividents */
2728 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2729 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2730 /* Compute remainder */
2731 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2732 /* Remove compensation */
2733 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2738 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2742 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2745 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2749 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2752 g_assert (ins->sreg2 == X86_ECX);
2753 x86_shift_reg (code, X86_SHL, ins->dreg);
2756 g_assert (ins->sreg2 == X86_ECX);
2757 x86_shift_reg (code, X86_SAR, ins->dreg);
2761 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2764 case OP_ISHR_UN_IMM:
2765 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2768 g_assert (ins->sreg2 == X86_ECX);
2769 x86_shift_reg (code, X86_SHR, ins->dreg);
2773 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2776 guint8 *jump_to_end;
2778 /* handle shifts below 32 bits */
2779 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2780 x86_shift_reg (code, X86_SHL, ins->sreg1);
2782 x86_test_reg_imm (code, X86_ECX, 32);
2783 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2785 /* handle shift over 32 bit */
2786 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2787 x86_clear_reg (code, ins->sreg1);
2789 x86_patch (jump_to_end, code);
2793 guint8 *jump_to_end;
2795 /* handle shifts below 32 bits */
2796 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2797 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2799 x86_test_reg_imm (code, X86_ECX, 32);
2800 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2802 /* handle shifts over 31 bits */
2803 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2804 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2806 x86_patch (jump_to_end, code);
2810 guint8 *jump_to_end;
2812 /* handle shifts below 32 bits */
2813 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2814 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2816 x86_test_reg_imm (code, X86_ECX, 32);
2817 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2819 /* handle shifts over 31 bits */
2820 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2821 x86_clear_reg (code, ins->backend.reg3);
2823 x86_patch (jump_to_end, code);
2827 if (ins->inst_imm >= 32) {
2828 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2829 x86_clear_reg (code, ins->sreg1);
2830 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2832 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2833 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2837 if (ins->inst_imm >= 32) {
2838 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2839 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2840 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2842 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2843 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2846 case OP_LSHR_UN_IMM:
2847 if (ins->inst_imm >= 32) {
2848 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2849 x86_clear_reg (code, ins->backend.reg3);
2850 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2852 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2853 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2857 x86_not_reg (code, ins->sreg1);
2860 x86_neg_reg (code, ins->sreg1);
2864 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2868 switch (ins->inst_imm) {
2872 if (ins->dreg != ins->sreg1)
2873 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2874 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2877 /* LEA r1, [r2 + r2*2] */
2878 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2881 /* LEA r1, [r2 + r2*4] */
2882 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2885 /* LEA r1, [r2 + r2*2] */
2887 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2888 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2891 /* LEA r1, [r2 + r2*8] */
2892 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2895 /* LEA r1, [r2 + r2*4] */
2897 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2898 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2901 /* LEA r1, [r2 + r2*2] */
2903 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2904 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2907 /* LEA r1, [r2 + r2*4] */
2908 /* LEA r1, [r1 + r1*4] */
2909 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2910 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2913 /* LEA r1, [r2 + r2*4] */
2915 /* LEA r1, [r1 + r1*4] */
2916 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2917 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2918 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2921 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2926 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2927 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2929 case OP_IMUL_OVF_UN: {
2930 /* the mul operation and the exception check should most likely be split */
2931 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2932 /*g_assert (ins->sreg2 == X86_EAX);
2933 g_assert (ins->dreg == X86_EAX);*/
2934 if (ins->sreg2 == X86_EAX) {
2935 non_eax_reg = ins->sreg1;
2936 } else if (ins->sreg1 == X86_EAX) {
2937 non_eax_reg = ins->sreg2;
2939 /* no need to save since we're going to store to it anyway */
2940 if (ins->dreg != X86_EAX) {
2942 x86_push_reg (code, X86_EAX);
2944 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
2945 non_eax_reg = ins->sreg2;
2947 if (ins->dreg == X86_EDX) {
2950 x86_push_reg (code, X86_EAX);
2952 } else if (ins->dreg != X86_EAX) {
2954 x86_push_reg (code, X86_EDX);
2956 x86_mul_reg (code, non_eax_reg, FALSE);
2957 /* save before the check since pop and mov don't change the flags */
2958 if (ins->dreg != X86_EAX)
2959 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2961 x86_pop_reg (code, X86_EDX);
2963 x86_pop_reg (code, X86_EAX);
2964 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2968 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
2971 g_assert_not_reached ();
2972 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2973 x86_mov_reg_imm (code, ins->dreg, 0);
2976 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2977 x86_mov_reg_imm (code, ins->dreg, 0);
2979 case OP_LOAD_GOTADDR:
2980 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
2981 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
2984 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2985 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
2987 case OP_X86_PUSH_GOT_ENTRY:
2988 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2989 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
2992 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2996 * Note: this 'frame destruction' logic is useful for tail calls, too.
2997 * Keep in sync with the code in emit_epilog.
3001 /* FIXME: no tracing support... */
3002 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3003 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3004 /* reset offset to make max_len work */
3005 offset = code - cfg->native_code;
3007 g_assert (!cfg->method->save_lmf);
3009 code = emit_load_volatile_arguments (cfg, code);
3011 if (cfg->used_int_regs & (1 << X86_EBX))
3013 if (cfg->used_int_regs & (1 << X86_EDI))
3015 if (cfg->used_int_regs & (1 << X86_ESI))
3018 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
3020 if (cfg->used_int_regs & (1 << X86_ESI))
3021 x86_pop_reg (code, X86_ESI);
3022 if (cfg->used_int_regs & (1 << X86_EDI))
3023 x86_pop_reg (code, X86_EDI);
3024 if (cfg->used_int_regs & (1 << X86_EBX))
3025 x86_pop_reg (code, X86_EBX);
3027 /* restore ESP/EBP */
3029 offset = code - cfg->native_code;
3030 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3031 x86_jump32 (code, 0);
3033 cfg->disable_aot = TRUE;
3037 MonoCallInst *call = (MonoCallInst*)ins;
3040 /* FIXME: no tracing support... */
3041 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3042 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3043 /* reset offset to make max_len work */
3044 offset = code - cfg->native_code;
3046 g_assert (!cfg->method->save_lmf);
3048 //code = emit_load_volatile_arguments (cfg, code);
3050 /* restore callee saved registers */
3051 for (i = 0; i < X86_NREG; ++i)
3052 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3054 if (cfg->used_int_regs & (1 << X86_ESI)) {
3055 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3058 if (cfg->used_int_regs & (1 << X86_EDI)) {
3059 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3062 if (cfg->used_int_regs & (1 << X86_EBX)) {
3063 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3067 /* Copy arguments on the stack to our argument area */
3068 for (i = 0; i < call->stack_usage; i += 4) {
3069 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3070 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3073 /* restore ESP/EBP */
3075 offset = code - cfg->native_code;
3076 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3077 x86_jump32 (code, 0);
3079 cfg->disable_aot = TRUE;
3083 /* ensure ins->sreg1 is not NULL
3084 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3085 * cmp DWORD PTR [eax], 0
3087 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3090 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3091 x86_push_reg (code, hreg);
3092 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3093 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3094 x86_pop_reg (code, hreg);
3103 call = (MonoCallInst*)ins;
3104 if (ins->flags & MONO_INST_HAS_METHOD)
3105 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3107 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3108 ins->flags |= MONO_INST_GC_CALLSITE;
3109 ins->backend.pc_offset = code - cfg->native_code;
3110 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3111 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
3112 * bytes to pop, we want to use pops. GCC does this (note it won't happen
3113 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
3114 * smart enough to do that optimization yet
3116 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
3117 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
3118 * (most likely from locality benefits). People with other processors should
3119 * check on theirs to see what happens.
3121 if (call->stack_usage == 4) {
3122 /* we want to use registers that won't get used soon, so use
3123 * ecx, as eax will get allocated first. edx is used by long calls,
3124 * so we can't use that.
3127 x86_pop_reg (code, X86_ECX);
3129 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3132 code = emit_move_return_value (cfg, ins, code);
3138 case OP_VOIDCALL_REG:
3140 call = (MonoCallInst*)ins;
3141 x86_call_reg (code, ins->sreg1);
3142 ins->flags |= MONO_INST_GC_CALLSITE;
3143 ins->backend.pc_offset = code - cfg->native_code;
3144 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3145 if (call->stack_usage == 4)
3146 x86_pop_reg (code, X86_ECX);
3148 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3150 code = emit_move_return_value (cfg, ins, code);
3152 case OP_FCALL_MEMBASE:
3153 case OP_LCALL_MEMBASE:
3154 case OP_VCALL_MEMBASE:
3155 case OP_VCALL2_MEMBASE:
3156 case OP_VOIDCALL_MEMBASE:
3157 case OP_CALL_MEMBASE:
3158 call = (MonoCallInst*)ins;
3160 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3161 ins->flags |= MONO_INST_GC_CALLSITE;
3162 ins->backend.pc_offset = code - cfg->native_code;
3163 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3164 if (call->stack_usage == 4)
3165 x86_pop_reg (code, X86_ECX);
3167 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3169 code = emit_move_return_value (cfg, ins, code);
3172 x86_push_reg (code, ins->sreg1);
3174 case OP_X86_PUSH_IMM:
3175 x86_push_imm (code, ins->inst_imm);
3177 case OP_X86_PUSH_MEMBASE:
3178 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
3180 case OP_X86_PUSH_OBJ:
3181 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
3182 x86_push_reg (code, X86_EDI);
3183 x86_push_reg (code, X86_ESI);
3184 x86_push_reg (code, X86_ECX);
3185 if (ins->inst_offset)
3186 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
3188 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
3189 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
3190 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
3192 x86_prefix (code, X86_REP_PREFIX);
3194 x86_pop_reg (code, X86_ECX);
3195 x86_pop_reg (code, X86_ESI);
3196 x86_pop_reg (code, X86_EDI);
3199 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3201 case OP_X86_LEA_MEMBASE:
3202 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3205 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3208 /* keep alignment */
3209 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3210 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3211 code = mono_emit_stack_alloc (code, ins);
3212 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3214 case OP_LOCALLOC_IMM: {
3215 guint32 size = ins->inst_imm;
3216 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3218 if (ins->flags & MONO_INST_INIT) {
3219 /* FIXME: Optimize this */
3220 x86_mov_reg_imm (code, ins->dreg, size);
3221 ins->sreg1 = ins->dreg;
3223 code = mono_emit_stack_alloc (code, ins);
3224 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3226 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3227 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3232 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3233 x86_push_reg (code, ins->sreg1);
3234 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3235 (gpointer)"mono_arch_throw_exception");
3236 ins->flags |= MONO_INST_GC_CALLSITE;
3237 ins->backend.pc_offset = code - cfg->native_code;
3241 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3242 x86_push_reg (code, ins->sreg1);
3243 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3244 (gpointer)"mono_arch_rethrow_exception");
3245 ins->flags |= MONO_INST_GC_CALLSITE;
3246 ins->backend.pc_offset = code - cfg->native_code;
3249 case OP_CALL_HANDLER:
3250 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3251 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3252 x86_call_imm (code, 0);
3253 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3254 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3256 case OP_START_HANDLER: {
3257 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3258 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3261 case OP_ENDFINALLY: {
3262 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3263 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3267 case OP_ENDFILTER: {
3268 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3269 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3270 /* The local allocator will put the result into EAX */
3276 ins->inst_c0 = code - cfg->native_code;
3279 if (ins->inst_target_bb->native_offset) {
3280 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3282 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3283 if ((cfg->opt & MONO_OPT_BRANCH) &&
3284 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3285 x86_jump8 (code, 0);
3287 x86_jump32 (code, 0);
3291 x86_jump_reg (code, ins->sreg1);
3304 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3305 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3307 case OP_COND_EXC_EQ:
3308 case OP_COND_EXC_NE_UN:
3309 case OP_COND_EXC_LT:
3310 case OP_COND_EXC_LT_UN:
3311 case OP_COND_EXC_GT:
3312 case OP_COND_EXC_GT_UN:
3313 case OP_COND_EXC_GE:
3314 case OP_COND_EXC_GE_UN:
3315 case OP_COND_EXC_LE:
3316 case OP_COND_EXC_LE_UN:
3317 case OP_COND_EXC_IEQ:
3318 case OP_COND_EXC_INE_UN:
3319 case OP_COND_EXC_ILT:
3320 case OP_COND_EXC_ILT_UN:
3321 case OP_COND_EXC_IGT:
3322 case OP_COND_EXC_IGT_UN:
3323 case OP_COND_EXC_IGE:
3324 case OP_COND_EXC_IGE_UN:
3325 case OP_COND_EXC_ILE:
3326 case OP_COND_EXC_ILE_UN:
3327 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3329 case OP_COND_EXC_OV:
3330 case OP_COND_EXC_NO:
3332 case OP_COND_EXC_NC:
3333 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3335 case OP_COND_EXC_IOV:
3336 case OP_COND_EXC_INO:
3337 case OP_COND_EXC_IC:
3338 case OP_COND_EXC_INC:
3339 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3351 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3359 case OP_CMOV_INE_UN:
3360 case OP_CMOV_IGE_UN:
3361 case OP_CMOV_IGT_UN:
3362 case OP_CMOV_ILE_UN:
3363 case OP_CMOV_ILT_UN:
3364 g_assert (ins->dreg == ins->sreg1);
3365 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3368 /* floating point opcodes */
3370 double d = *(double *)ins->inst_p0;
3372 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3374 } else if (d == 1.0) {
3377 if (cfg->compile_aot) {
3378 guint32 *val = (guint32*)&d;
3379 x86_push_imm (code, val [1]);
3380 x86_push_imm (code, val [0]);
3381 x86_fld_membase (code, X86_ESP, 0, TRUE);
3382 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3385 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3386 x86_fld (code, NULL, TRUE);
3392 float f = *(float *)ins->inst_p0;
3394 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3396 } else if (f == 1.0) {
3399 if (cfg->compile_aot) {
3400 guint32 val = *(guint32*)&f;
3401 x86_push_imm (code, val);
3402 x86_fld_membase (code, X86_ESP, 0, FALSE);
3403 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3406 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3407 x86_fld (code, NULL, FALSE);
3412 case OP_STORER8_MEMBASE_REG:
3413 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3415 case OP_LOADR8_MEMBASE:
3416 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3418 case OP_STORER4_MEMBASE_REG:
3419 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3421 case OP_LOADR4_MEMBASE:
3422 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3424 case OP_ICONV_TO_R4:
3425 x86_push_reg (code, ins->sreg1);
3426 x86_fild_membase (code, X86_ESP, 0, FALSE);
3427 /* Change precision */
3428 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3429 x86_fld_membase (code, X86_ESP, 0, FALSE);
3430 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3432 case OP_ICONV_TO_R8:
3433 x86_push_reg (code, ins->sreg1);
3434 x86_fild_membase (code, X86_ESP, 0, FALSE);
3435 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3437 case OP_ICONV_TO_R_UN:
3438 x86_push_imm (code, 0);
3439 x86_push_reg (code, ins->sreg1);
3440 x86_fild_membase (code, X86_ESP, 0, TRUE);
3441 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3443 case OP_X86_FP_LOAD_I8:
3444 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3446 case OP_X86_FP_LOAD_I4:
3447 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3449 case OP_FCONV_TO_R4:
3450 /* Change precision */
3451 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3452 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3453 x86_fld_membase (code, X86_ESP, 0, FALSE);
3454 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3456 case OP_FCONV_TO_I1:
3457 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3459 case OP_FCONV_TO_U1:
3460 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3462 case OP_FCONV_TO_I2:
3463 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3465 case OP_FCONV_TO_U2:
3466 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3468 case OP_FCONV_TO_I4:
3470 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3472 case OP_FCONV_TO_I8:
3473 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3474 x86_fnstcw_membase(code, X86_ESP, 0);
3475 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3476 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3477 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3478 x86_fldcw_membase (code, X86_ESP, 2);
3479 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3480 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3481 x86_pop_reg (code, ins->dreg);
3482 x86_pop_reg (code, ins->backend.reg3);
3483 x86_fldcw_membase (code, X86_ESP, 0);
3484 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3486 case OP_LCONV_TO_R8_2:
3487 x86_push_reg (code, ins->sreg2);
3488 x86_push_reg (code, ins->sreg1);
3489 x86_fild_membase (code, X86_ESP, 0, TRUE);
3490 /* Change precision */
3491 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3492 x86_fld_membase (code, X86_ESP, 0, TRUE);
3493 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3495 case OP_LCONV_TO_R4_2:
3496 x86_push_reg (code, ins->sreg2);
3497 x86_push_reg (code, ins->sreg1);
3498 x86_fild_membase (code, X86_ESP, 0, TRUE);
3499 /* Change precision */
3500 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3501 x86_fld_membase (code, X86_ESP, 0, FALSE);
3502 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3504 case OP_LCONV_TO_R_UN_2: {
3505 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3508 /* load 64bit integer to FP stack */
3509 x86_push_reg (code, ins->sreg2);
3510 x86_push_reg (code, ins->sreg1);
3511 x86_fild_membase (code, X86_ESP, 0, TRUE);
3513 /* test if lreg is negative */
3514 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3515 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3517 /* add correction constant mn */
3518 x86_fld80_mem (code, mn);
3519 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3521 x86_patch (br, code);
3523 /* Change precision */
3524 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3525 x86_fld_membase (code, X86_ESP, 0, TRUE);
3527 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3531 case OP_LCONV_TO_OVF_I:
3532 case OP_LCONV_TO_OVF_I4_2: {
3533 guint8 *br [3], *label [1];
3537 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3539 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3541 /* If the low word top bit is set, see if we are negative */
3542 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3543 /* We are not negative (no top bit set, check for our top word to be zero */
3544 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3545 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3548 /* throw exception */
3549 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3551 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3552 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3553 x86_jump8 (code, 0);
3555 x86_jump32 (code, 0);
3557 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3558 x86_jump32 (code, 0);
3562 x86_patch (br [0], code);
3563 /* our top bit is set, check that top word is 0xfffffff */
3564 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3566 x86_patch (br [1], code);
3567 /* nope, emit exception */
3568 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3569 x86_patch (br [2], label [0]);
3571 if (ins->dreg != ins->sreg1)
3572 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3576 /* Not needed on the fp stack */
3579 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3582 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3585 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3588 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3596 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3601 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3608 * it really doesn't make sense to inline all this code,
3609 * it's here just to show that things may not be as simple
3612 guchar *check_pos, *end_tan, *pop_jump;
3613 x86_push_reg (code, X86_EAX);
3616 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3618 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3619 x86_fstp (code, 0); /* pop the 1.0 */
3621 x86_jump8 (code, 0);
3623 x86_fp_op (code, X86_FADD, 0);
3627 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3629 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3632 x86_patch (pop_jump, code);
3633 x86_fstp (code, 0); /* pop the 1.0 */
3634 x86_patch (check_pos, code);
3635 x86_patch (end_tan, code);
3637 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3638 x86_pop_reg (code, X86_EAX);
3645 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3654 g_assert (cfg->opt & MONO_OPT_CMOV);
3655 g_assert (ins->dreg == ins->sreg1);
3656 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3657 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3660 g_assert (cfg->opt & MONO_OPT_CMOV);
3661 g_assert (ins->dreg == ins->sreg1);
3662 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3663 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3666 g_assert (cfg->opt & MONO_OPT_CMOV);
3667 g_assert (ins->dreg == ins->sreg1);
3668 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3669 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3672 g_assert (cfg->opt & MONO_OPT_CMOV);
3673 g_assert (ins->dreg == ins->sreg1);
3674 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3675 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3681 x86_fxch (code, ins->inst_imm);
3686 x86_push_reg (code, X86_EAX);
3687 /* we need to exchange ST(0) with ST(1) */
3690 /* this requires a loop, because fprem somtimes
3691 * returns a partial remainder */
3693 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3694 /* x86_fprem1 (code); */
3697 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3699 x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3704 x86_pop_reg (code, X86_EAX);
3708 if (cfg->opt & MONO_OPT_FCMOV) {
3709 x86_fcomip (code, 1);
3713 /* this overwrites EAX */
3714 EMIT_FPCOMPARE(code);
3715 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3718 if (cfg->opt & MONO_OPT_FCMOV) {
3719 /* zeroing the register at the start results in
3720 * shorter and faster code (we can also remove the widening op)
3722 guchar *unordered_check;
3723 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3724 x86_fcomip (code, 1);
3726 unordered_check = code;
3727 x86_branch8 (code, X86_CC_P, 0, FALSE);
3728 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3729 x86_patch (unordered_check, code);
3732 if (ins->dreg != X86_EAX)
3733 x86_push_reg (code, X86_EAX);
3735 EMIT_FPCOMPARE(code);
3736 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3737 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3738 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3739 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3741 if (ins->dreg != X86_EAX)
3742 x86_pop_reg (code, X86_EAX);
3746 if (cfg->opt & MONO_OPT_FCMOV) {
3747 /* zeroing the register at the start results in
3748 * shorter and faster code (we can also remove the widening op)
3750 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3751 x86_fcomip (code, 1);
3753 if (ins->opcode == OP_FCLT_UN) {
3754 guchar *unordered_check = code;
3755 guchar *jump_to_end;
3756 x86_branch8 (code, X86_CC_P, 0, FALSE);
3757 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3759 x86_jump8 (code, 0);
3760 x86_patch (unordered_check, code);
3761 x86_inc_reg (code, ins->dreg);
3762 x86_patch (jump_to_end, code);
3764 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3768 if (ins->dreg != X86_EAX)
3769 x86_push_reg (code, X86_EAX);
3771 EMIT_FPCOMPARE(code);
3772 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3773 if (ins->opcode == OP_FCLT_UN) {
3774 guchar *is_not_zero_check, *end_jump;
3775 is_not_zero_check = code;
3776 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3778 x86_jump8 (code, 0);
3779 x86_patch (is_not_zero_check, code);
3780 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3782 x86_patch (end_jump, code);
3784 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3785 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3787 if (ins->dreg != X86_EAX)
3788 x86_pop_reg (code, X86_EAX);
3792 if (cfg->opt & MONO_OPT_FCMOV) {
3793 /* zeroing the register at the start results in
3794 * shorter and faster code (we can also remove the widening op)
3796 guchar *unordered_check;
3797 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3798 x86_fcomip (code, 1);
3800 if (ins->opcode == OP_FCGT) {
3801 unordered_check = code;
3802 x86_branch8 (code, X86_CC_P, 0, FALSE);
3803 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3804 x86_patch (unordered_check, code);
3806 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3810 if (ins->dreg != X86_EAX)
3811 x86_push_reg (code, X86_EAX);
3813 EMIT_FPCOMPARE(code);
3814 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3815 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3816 if (ins->opcode == OP_FCGT_UN) {
3817 guchar *is_not_zero_check, *end_jump;
3818 is_not_zero_check = code;
3819 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3821 x86_jump8 (code, 0);
3822 x86_patch (is_not_zero_check, code);
3823 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3825 x86_patch (end_jump, code);
3827 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3828 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3830 if (ins->dreg != X86_EAX)
3831 x86_pop_reg (code, X86_EAX);
3834 if (cfg->opt & MONO_OPT_FCMOV) {
3835 guchar *jump = code;
3836 x86_branch8 (code, X86_CC_P, 0, TRUE);
3837 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3838 x86_patch (jump, code);
3841 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3842 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3845 /* Branch if C013 != 100 */
3846 if (cfg->opt & MONO_OPT_FCMOV) {
3847 /* branch if !ZF or (PF|CF) */
3848 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3849 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3850 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3853 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3854 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3857 if (cfg->opt & MONO_OPT_FCMOV) {
3858 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3861 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3864 if (cfg->opt & MONO_OPT_FCMOV) {
3865 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3866 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3869 if (ins->opcode == OP_FBLT_UN) {
3870 guchar *is_not_zero_check, *end_jump;
3871 is_not_zero_check = code;
3872 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3874 x86_jump8 (code, 0);
3875 x86_patch (is_not_zero_check, code);
3876 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3878 x86_patch (end_jump, code);
3880 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3884 if (cfg->opt & MONO_OPT_FCMOV) {
3885 if (ins->opcode == OP_FBGT) {
3888 /* skip branch if C1=1 */
3890 x86_branch8 (code, X86_CC_P, 0, FALSE);
3891 /* branch if (C0 | C3) = 1 */
3892 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3893 x86_patch (br1, code);
3895 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3899 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3900 if (ins->opcode == OP_FBGT_UN) {
3901 guchar *is_not_zero_check, *end_jump;
3902 is_not_zero_check = code;
3903 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3905 x86_jump8 (code, 0);
3906 x86_patch (is_not_zero_check, code);
3907 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3909 x86_patch (end_jump, code);
3911 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3914 /* Branch if C013 == 100 or 001 */
3915 if (cfg->opt & MONO_OPT_FCMOV) {
3918 /* skip branch if C1=1 */
3920 x86_branch8 (code, X86_CC_P, 0, FALSE);
3921 /* branch if (C0 | C3) = 1 */
3922 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3923 x86_patch (br1, code);
3926 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3927 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3928 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3929 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3932 /* Branch if C013 == 000 */
3933 if (cfg->opt & MONO_OPT_FCMOV) {
3934 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3937 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3940 /* Branch if C013=000 or 100 */
3941 if (cfg->opt & MONO_OPT_FCMOV) {
3944 /* skip branch if C1=1 */
3946 x86_branch8 (code, X86_CC_P, 0, FALSE);
3947 /* branch if C0=0 */
3948 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3949 x86_patch (br1, code);
3952 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
3953 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
3954 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3957 /* Branch if C013 != 001 */
3958 if (cfg->opt & MONO_OPT_FCMOV) {
3959 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3960 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3963 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3964 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3968 x86_push_reg (code, X86_EAX);
3971 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
3972 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3973 x86_pop_reg (code, X86_EAX);
3975 /* Have to clean up the fp stack before throwing the exception */
3977 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3980 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3982 x86_patch (br1, code);
3986 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
3989 case OP_MEMORY_BARRIER: {
3990 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
3991 x86_prefix (code, X86_LOCK_PREFIX);
3992 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
3995 case OP_ATOMIC_ADD_I4: {
3996 int dreg = ins->dreg;
3998 if (dreg == ins->inst_basereg) {
3999 x86_push_reg (code, ins->sreg2);
4003 if (dreg != ins->sreg2)
4004 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
4006 x86_prefix (code, X86_LOCK_PREFIX);
4007 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4009 if (dreg != ins->dreg) {
4010 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4011 x86_pop_reg (code, dreg);
4016 case OP_ATOMIC_ADD_NEW_I4: {
4017 int dreg = ins->dreg;
4019 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4020 if (ins->sreg2 == dreg) {
4021 if (dreg == X86_EBX) {
4023 if (ins->inst_basereg == X86_EDI)
4027 if (ins->inst_basereg == X86_EBX)
4030 } else if (ins->inst_basereg == dreg) {
4031 if (dreg == X86_EBX) {
4033 if (ins->sreg2 == X86_EDI)
4037 if (ins->sreg2 == X86_EBX)
4042 if (dreg != ins->dreg) {
4043 x86_push_reg (code, dreg);
4046 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4047 x86_prefix (code, X86_LOCK_PREFIX);
4048 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4049 /* dreg contains the old value, add with sreg2 value */
4050 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4052 if (ins->dreg != dreg) {
4053 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4054 x86_pop_reg (code, dreg);
4059 case OP_ATOMIC_EXCHANGE_I4: {
4061 int sreg2 = ins->sreg2;
4062 int breg = ins->inst_basereg;
4064 /* cmpxchg uses eax as comperand, need to make sure we can use it
4065 * hack to overcome limits in x86 reg allocator
4066 * (req: dreg == eax and sreg2 != eax and breg != eax)
4068 g_assert (ins->dreg == X86_EAX);
4070 /* We need the EAX reg for the cmpxchg */
4071 if (ins->sreg2 == X86_EAX) {
4072 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4073 x86_push_reg (code, sreg2);
4074 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4077 if (breg == X86_EAX) {
4078 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4079 x86_push_reg (code, breg);
4080 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4083 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4085 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4086 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4087 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4088 x86_patch (br [1], br [0]);
4090 if (breg != ins->inst_basereg)
4091 x86_pop_reg (code, breg);
4093 if (ins->sreg2 != sreg2)
4094 x86_pop_reg (code, sreg2);
4098 case OP_ATOMIC_CAS_I4: {
4099 g_assert (ins->dreg == X86_EAX);
4100 g_assert (ins->sreg3 == X86_EAX);
4101 g_assert (ins->sreg1 != X86_EAX);
4102 g_assert (ins->sreg1 != ins->sreg2);
4104 x86_prefix (code, X86_LOCK_PREFIX);
4105 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4108 case OP_CARD_TABLE_WBARRIER: {
4109 int ptr = ins->sreg1;
4110 int value = ins->sreg2;
4112 int nursery_shift, card_table_shift;
4113 gpointer card_table_mask;
4114 size_t nursery_size;
4115 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4116 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4119 * We need one register we can clobber, we choose EDX and make sreg1
4120 * fixed EAX to work around limitations in the local register allocator.
4121 * sreg2 might get allocated to EDX, but that is not a problem since
4122 * we use it before clobbering EDX.
4124 g_assert (ins->sreg1 == X86_EAX);
4127 * This is the code we produce:
4130 * edx >>= nursery_shift
4131 * cmp edx, (nursery_start >> nursery_shift)
4134 * edx >>= card_table_shift
4135 * card_table[edx] = 1
4139 if (value != X86_EDX)
4140 x86_mov_reg_reg (code, X86_EDX, value, 4);
4141 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4142 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4143 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4144 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4145 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4146 if (card_table_mask)
4147 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4148 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4149 x86_patch (br, code);
4152 #ifdef MONO_ARCH_SIMD_INTRINSICS
4154 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4157 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4160 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4163 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4166 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4169 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4172 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4173 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4176 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4179 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4182 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4185 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4188 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4191 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4194 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4197 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4200 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4203 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4206 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4209 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4212 case OP_PSHUFLEW_HIGH:
4213 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4214 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4216 case OP_PSHUFLEW_LOW:
4217 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4218 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4221 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4222 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4225 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4226 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4229 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4230 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4234 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4237 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4240 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4243 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4246 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4249 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4252 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4253 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4256 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4259 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4262 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4265 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4268 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4271 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4274 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4277 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4280 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4283 case OP_EXTRACT_MASK:
4284 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4288 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4291 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4294 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4298 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4301 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4304 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4307 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4311 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4314 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4317 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4320 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4324 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4327 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4330 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4334 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4337 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4340 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4344 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4347 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4351 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4354 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4357 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4361 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4364 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4367 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4371 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4374 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4377 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4380 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4384 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4387 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4390 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4393 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4396 case OP_PSUM_ABS_DIFF:
4397 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4400 case OP_UNPACK_LOWB:
4401 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4403 case OP_UNPACK_LOWW:
4404 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4406 case OP_UNPACK_LOWD:
4407 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4409 case OP_UNPACK_LOWQ:
4410 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4412 case OP_UNPACK_LOWPS:
4413 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4415 case OP_UNPACK_LOWPD:
4416 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4419 case OP_UNPACK_HIGHB:
4420 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4422 case OP_UNPACK_HIGHW:
4423 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4425 case OP_UNPACK_HIGHD:
4426 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4428 case OP_UNPACK_HIGHQ:
4429 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4431 case OP_UNPACK_HIGHPS:
4432 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4434 case OP_UNPACK_HIGHPD:
4435 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4439 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4442 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4445 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4448 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4451 case OP_PADDB_SAT_UN:
4452 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4454 case OP_PSUBB_SAT_UN:
4455 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4457 case OP_PADDW_SAT_UN:
4458 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4460 case OP_PSUBW_SAT_UN:
4461 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4465 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4468 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4471 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4474 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4478 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4481 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4484 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4486 case OP_PMULW_HIGH_UN:
4487 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4490 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4494 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4497 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4501 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4504 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4508 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4511 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4515 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4518 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4522 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4525 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4529 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4532 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4536 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4539 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4543 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4546 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4550 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4553 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4557 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4559 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4560 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4564 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4566 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4567 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4571 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4573 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4574 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4578 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4580 case OP_EXTRACTX_U2:
4581 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4583 case OP_INSERTX_U1_SLOW:
4584 /*sreg1 is the extracted ireg (scratch)
4585 /sreg2 is the to be inserted ireg (scratch)
4586 /dreg is the xreg to receive the value*/
4588 /*clear the bits from the extracted word*/
4589 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4590 /*shift the value to insert if needed*/
4591 if (ins->inst_c0 & 1)
4592 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4593 /*join them together*/
4594 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4595 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4597 case OP_INSERTX_I4_SLOW:
4598 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4599 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4600 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4603 case OP_INSERTX_R4_SLOW:
4604 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4605 /*TODO if inst_c0 == 0 use movss*/
4606 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4607 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4609 case OP_INSERTX_R8_SLOW:
4610 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4612 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4614 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVSD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4617 case OP_STOREX_MEMBASE_REG:
4618 case OP_STOREX_MEMBASE:
4619 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4621 case OP_LOADX_MEMBASE:
4622 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4624 case OP_LOADX_ALIGNED_MEMBASE:
4625 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4627 case OP_STOREX_ALIGNED_MEMBASE_REG:
4628 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4630 case OP_STOREX_NTA_MEMBASE_REG:
4631 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4633 case OP_PREFETCH_MEMBASE:
4634 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4638 /*FIXME the peephole pass should have killed this*/
4639 if (ins->dreg != ins->sreg1)
4640 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4643 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4645 case OP_ICONV_TO_R8_RAW:
4646 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4647 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4650 case OP_FCONV_TO_R8_X:
4651 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4652 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4655 case OP_XCONV_R8_TO_I4:
4656 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4657 switch (ins->backend.source_opcode) {
4658 case OP_FCONV_TO_I1:
4659 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4661 case OP_FCONV_TO_U1:
4662 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4664 case OP_FCONV_TO_I2:
4665 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4667 case OP_FCONV_TO_U2:
4668 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4674 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4675 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4676 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4677 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4678 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4679 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4682 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4683 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4684 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4687 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4688 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4691 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4692 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4693 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4696 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4697 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4698 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4702 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4705 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4708 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4711 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4714 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4717 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4720 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4723 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4727 case OP_LIVERANGE_START: {
4728 if (cfg->verbose_level > 1)
4729 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4730 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4733 case OP_LIVERANGE_END: {
4734 if (cfg->verbose_level > 1)
4735 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4736 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4739 case OP_NACL_GC_SAFE_POINT: {
4740 #if defined(__native_client_codegen__)
4741 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
4745 case OP_GC_LIVENESS_DEF:
4746 case OP_GC_LIVENESS_USE:
4747 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4748 ins->backend.pc_offset = code - cfg->native_code;
4750 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4751 ins->backend.pc_offset = code - cfg->native_code;
4752 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4755 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4756 g_assert_not_reached ();
4759 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4760 #ifndef __native_client_codegen__
4761 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4762 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4763 g_assert_not_reached ();
4764 #endif /* __native_client_codegen__ */
4770 cfg->code_len = code - cfg->native_code;
4773 #endif /* DISABLE_JIT */
4776 mono_arch_register_lowlevel_calls (void)
4781 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4783 MonoJumpInfo *patch_info;
4784 gboolean compile_aot = !run_cctors;
4786 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4787 unsigned char *ip = patch_info->ip.i + code;
4788 const unsigned char *target;
4790 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4793 switch (patch_info->type) {
4794 case MONO_PATCH_INFO_BB:
4795 case MONO_PATCH_INFO_LABEL:
4798 /* No need to patch these */
4803 switch (patch_info->type) {
4804 case MONO_PATCH_INFO_IP:
4805 *((gconstpointer *)(ip)) = target;
4807 case MONO_PATCH_INFO_CLASS_INIT: {
4809 /* Might already been changed to a nop */
4810 x86_call_code (code, 0);
4811 x86_patch (ip, target);
4814 case MONO_PATCH_INFO_ABS:
4815 case MONO_PATCH_INFO_METHOD:
4816 case MONO_PATCH_INFO_METHOD_JUMP:
4817 case MONO_PATCH_INFO_INTERNAL_METHOD:
4818 case MONO_PATCH_INFO_BB:
4819 case MONO_PATCH_INFO_LABEL:
4820 case MONO_PATCH_INFO_RGCTX_FETCH:
4821 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
4822 case MONO_PATCH_INFO_MONITOR_ENTER:
4823 case MONO_PATCH_INFO_MONITOR_EXIT:
4824 #if defined(__native_client_codegen__) && defined(__native_client__)
4825 if (nacl_is_code_address (code)) {
4826 /* For tail calls, code is patched after being installed */
4827 /* but not through the normal "patch callsite" method. */
4828 unsigned char buf[kNaClAlignment];
4829 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
4830 unsigned char *_target = target;
4832 /* All patch targets modified in x86_patch */
4833 /* are IP relative. */
4834 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
4835 memcpy (buf, aligned_code, kNaClAlignment);
4836 /* Patch a temp buffer of bundle size, */
4837 /* then install to actual location. */
4838 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
4839 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
4840 g_assert (ret == 0);
4843 x86_patch (ip, target);
4846 x86_patch (ip, target);
4849 case MONO_PATCH_INFO_NONE:
4851 case MONO_PATCH_INFO_R4:
4852 case MONO_PATCH_INFO_R8: {
4853 guint32 offset = mono_arch_get_patch_offset (ip);
4854 *((gconstpointer *)(ip + offset)) = target;
4858 guint32 offset = mono_arch_get_patch_offset (ip);
4859 #if !defined(__native_client__)
4860 *((gconstpointer *)(ip + offset)) = target;
4862 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
4871 mono_arch_emit_prolog (MonoCompile *cfg)
4873 MonoMethod *method = cfg->method;
4875 MonoMethodSignature *sig;
4877 int alloc_size, pos, max_offset, i, cfa_offset;
4879 gboolean need_stack_frame;
4880 #ifdef __native_client_codegen__
4881 guint alignment_check;
4884 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
4886 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4887 cfg->code_size += 512;
4889 #if defined(__default_codegen__)
4890 code = cfg->native_code = g_malloc (cfg->code_size);
4891 #elif defined(__native_client_codegen__)
4892 /* native_code_alloc is not 32-byte aligned, native_code is. */
4893 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
4895 /* Align native_code to next nearest kNaclAlignment byte. */
4896 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
4897 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
4899 code = cfg->native_code;
4901 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
4902 g_assert(alignment_check == 0);
4905 /* Offset between RSP and the CFA */
4909 cfa_offset = sizeof (gpointer);
4910 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
4911 // IP saved at CFA - 4
4912 /* There is no IP reg on x86 */
4913 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
4915 need_stack_frame = needs_stack_frame (cfg);
4917 if (need_stack_frame) {
4918 x86_push_reg (code, X86_EBP);
4919 cfa_offset += sizeof (gpointer);
4920 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4921 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
4922 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
4923 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
4925 cfg->frame_reg = X86_ESP;
4928 alloc_size = cfg->stack_offset;
4931 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4932 /* Might need to attach the thread to the JIT or change the domain for the callback */
4933 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4934 guint8 *buf, *no_domain_branch;
4936 code = mono_x86_emit_tls_get (code, X86_EAX, appdomain_tls_offset);
4937 x86_alu_reg_imm (code, X86_CMP, X86_EAX, GPOINTER_TO_UINT (cfg->domain));
4938 no_domain_branch = code;
4939 x86_branch8 (code, X86_CC_NE, 0, 0);
4940 code = mono_x86_emit_tls_get ( code, X86_EAX, lmf_tls_offset);
4941 x86_test_reg_reg (code, X86_EAX, X86_EAX);
4943 x86_branch8 (code, X86_CC_NE, 0, 0);
4944 x86_patch (no_domain_branch, code);
4945 x86_push_imm (code, cfg->domain);
4946 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4947 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
4948 x86_patch (buf, code);
4950 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4951 /* FIXME: Add a separate key for LMF to avoid this */
4952 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4956 if (cfg->compile_aot) {
4958 * This goes before the saving of callee saved regs, so save the got reg
4961 x86_push_reg (code, MONO_ARCH_GOT_REG);
4962 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
4963 x86_push_imm (code, 0);
4965 x86_push_imm (code, cfg->domain);
4967 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4968 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
4969 if (cfg->compile_aot)
4970 x86_pop_reg (code, MONO_ARCH_GOT_REG);
4974 if (method->save_lmf) {
4975 pos += sizeof (MonoLMF);
4977 /* save the current IP */
4978 if (cfg->compile_aot) {
4979 /* This pushes the current ip */
4980 x86_call_imm (code, 0);
4982 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
4983 x86_push_imm_template (code);
4985 cfa_offset += sizeof (gpointer);
4987 /* save all caller saved regs */
4988 x86_push_reg (code, X86_EBP);
4989 cfa_offset += sizeof (gpointer);
4990 x86_push_reg (code, X86_ESI);
4991 cfa_offset += sizeof (gpointer);
4992 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
4993 x86_push_reg (code, X86_EDI);
4994 cfa_offset += sizeof (gpointer);
4995 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
4996 x86_push_reg (code, X86_EBX);
4997 cfa_offset += sizeof (gpointer);
4998 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5000 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5002 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5003 * through the mono_lmf_addr TLS variable.
5005 /* %eax = previous_lmf */
5006 x86_prefix (code, X86_GS_PREFIX);
5007 x86_mov_reg_mem (code, X86_EAX, lmf_tls_offset, 4);
5008 /* skip esp + method_info + lmf */
5009 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 12);
5010 /* push previous_lmf */
5011 x86_push_reg (code, X86_EAX);
5013 x86_prefix (code, X86_GS_PREFIX);
5014 x86_mov_mem_reg (code, lmf_tls_offset, X86_ESP, 4);
5016 /* get the address of lmf for the current thread */
5018 * This is performance critical so we try to use some tricks to make
5022 if (lmf_addr_tls_offset != -1) {
5023 /* Load lmf quicky using the GS register */
5024 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
5026 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5027 /* FIXME: Add a separate key for LMF to avoid this */
5028 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5031 if (cfg->compile_aot)
5032 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
5033 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
5036 /* Skip esp + method info */
5037 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
5040 x86_push_reg (code, X86_EAX);
5041 /* push *lfm (previous_lmf) */
5042 x86_push_membase (code, X86_EAX, 0);
5044 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
5048 if (cfg->used_int_regs & (1 << X86_EBX)) {
5049 x86_push_reg (code, X86_EBX);
5051 cfa_offset += sizeof (gpointer);
5052 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5055 if (cfg->used_int_regs & (1 << X86_EDI)) {
5056 x86_push_reg (code, X86_EDI);
5058 cfa_offset += sizeof (gpointer);
5059 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5062 if (cfg->used_int_regs & (1 << X86_ESI)) {
5063 x86_push_reg (code, X86_ESI);
5065 cfa_offset += sizeof (gpointer);
5066 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5072 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5073 if (mono_do_x86_stack_align && need_stack_frame) {
5074 int tot = alloc_size + pos + 4; /* ret ip */
5075 if (need_stack_frame)
5077 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5079 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5083 /* See mono_emit_stack_alloc */
5084 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5085 guint32 remaining_size = alloc_size;
5086 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5087 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5088 guint32 offset = code - cfg->native_code;
5089 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5090 while (required_code_size >= (cfg->code_size - offset))
5091 cfg->code_size *= 2;
5092 cfg->native_code = mono_realloc_native_code(cfg);
5093 code = cfg->native_code + offset;
5094 mono_jit_stats.code_reallocs++;
5096 while (remaining_size >= 0x1000) {
5097 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5098 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5099 remaining_size -= 0x1000;
5102 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5104 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5107 g_assert (need_stack_frame);
5110 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5111 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5112 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5115 #if DEBUG_STACK_ALIGNMENT
5116 /* check the stack is aligned */
5117 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5118 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5119 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5120 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5121 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5122 x86_breakpoint (code);
5126 /* compute max_offset in order to use short forward jumps */
5128 if (cfg->opt & MONO_OPT_BRANCH) {
5129 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5131 bb->max_offset = max_offset;
5133 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5135 /* max alignment for loops */
5136 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5137 max_offset += LOOP_ALIGNMENT;
5138 #ifdef __native_client_codegen__
5139 /* max alignment for native client */
5140 max_offset += kNaClAlignment;
5142 MONO_BB_FOR_EACH_INS (bb, ins) {
5143 if (ins->opcode == OP_LABEL)
5144 ins->inst_c1 = max_offset;
5145 #ifdef __native_client_codegen__
5147 int space_in_block = kNaClAlignment -
5148 ((max_offset + cfg->code_len) & kNaClAlignmentMask);
5149 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5150 if (space_in_block < max_len && max_len < kNaClAlignment) {
5151 max_offset += space_in_block;
5154 #endif /* __native_client_codegen__ */
5155 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5160 /* store runtime generic context */
5161 if (cfg->rgctx_var) {
5162 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5164 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5167 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5168 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5170 /* load arguments allocated to register from the stack */
5171 sig = mono_method_signature (method);
5174 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5175 inst = cfg->args [pos];
5176 if (inst->opcode == OP_REGVAR) {
5177 g_assert (need_stack_frame);
5178 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5179 if (cfg->verbose_level > 2)
5180 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5185 cfg->code_len = code - cfg->native_code;
5187 g_assert (cfg->code_len < cfg->code_size);
5193 mono_arch_emit_epilog (MonoCompile *cfg)
5195 MonoMethod *method = cfg->method;
5196 MonoMethodSignature *sig = mono_method_signature (method);
5198 guint32 stack_to_pop;
5200 int max_epilog_size = 16;
5202 gboolean need_stack_frame = needs_stack_frame (cfg);
5204 if (cfg->method->save_lmf)
5205 max_epilog_size += 128;
5207 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5208 cfg->code_size *= 2;
5209 cfg->native_code = mono_realloc_native_code(cfg);
5210 mono_jit_stats.code_reallocs++;
5213 code = cfg->native_code + cfg->code_len;
5215 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5216 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5218 /* the code restoring the registers must be kept in sync with OP_JMP */
5221 if (method->save_lmf) {
5222 gint32 prev_lmf_reg;
5223 gint32 lmf_offset = -sizeof (MonoLMF);
5225 /* check if we need to restore protection of the stack after a stack overflow */
5226 if (mono_get_jit_tls_offset () != -1) {
5228 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5229 /* we load the value in a separate instruction: this mechanism may be
5230 * used later as a safer way to do thread interruption
5232 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5233 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5235 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5236 /* note that the call trampoline will preserve eax/edx */
5237 x86_call_reg (code, X86_ECX);
5238 x86_patch (patch, code);
5240 /* FIXME: maybe save the jit tls in the prolog */
5242 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5244 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5245 * through the mono_lmf_addr TLS variable.
5247 /* reg = previous_lmf */
5248 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5250 /* lmf = previous_lmf */
5251 x86_prefix (code, X86_GS_PREFIX);
5252 x86_mov_mem_reg (code, lmf_tls_offset, X86_ECX, 4);
5254 /* Find a spare register */
5255 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
5258 prev_lmf_reg = X86_EDI;
5259 cfg->used_int_regs |= (1 << X86_EDI);
5262 prev_lmf_reg = X86_EDX;
5266 /* reg = previous_lmf */
5267 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5270 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
5272 /* *(lmf) = previous_lmf */
5273 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
5276 /* restore caller saved regs */
5277 if (cfg->used_int_regs & (1 << X86_EBX)) {
5278 x86_mov_reg_membase (code, X86_EBX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
5281 if (cfg->used_int_regs & (1 << X86_EDI)) {
5282 x86_mov_reg_membase (code, X86_EDI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
5284 if (cfg->used_int_regs & (1 << X86_ESI)) {
5285 x86_mov_reg_membase (code, X86_ESI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
5288 /* EBP is restored by LEAVE */
5290 if (cfg->used_int_regs & (1 << X86_EBX)) {
5293 if (cfg->used_int_regs & (1 << X86_EDI)) {
5296 if (cfg->used_int_regs & (1 << X86_ESI)) {
5301 g_assert (need_stack_frame);
5302 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5305 if (cfg->used_int_regs & (1 << X86_ESI)) {
5306 x86_pop_reg (code, X86_ESI);
5308 if (cfg->used_int_regs & (1 << X86_EDI)) {
5309 x86_pop_reg (code, X86_EDI);
5311 if (cfg->used_int_regs & (1 << X86_EBX)) {
5312 x86_pop_reg (code, X86_EBX);
5316 /* Load returned vtypes into registers if needed */
5317 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5318 if (cinfo->ret.storage == ArgValuetypeInReg) {
5319 for (quad = 0; quad < 2; quad ++) {
5320 switch (cinfo->ret.pair_storage [quad]) {
5322 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5324 case ArgOnFloatFpStack:
5325 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5327 case ArgOnDoubleFpStack:
5328 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5333 g_assert_not_reached ();
5338 if (need_stack_frame)
5341 if (CALLCONV_IS_STDCALL (sig)) {
5342 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5344 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
5345 } else if (MONO_TYPE_ISSTRUCT (mono_method_signature (cfg->method)->ret) && (cinfo->ret.storage == ArgOnStack))
5351 g_assert (need_stack_frame);
5352 x86_ret_imm (code, stack_to_pop);
5357 cfg->code_len = code - cfg->native_code;
5359 g_assert (cfg->code_len < cfg->code_size);
5363 mono_arch_emit_exceptions (MonoCompile *cfg)
5365 MonoJumpInfo *patch_info;
5368 MonoClass *exc_classes [16];
5369 guint8 *exc_throw_start [16], *exc_throw_end [16];
5373 /* Compute needed space */
5374 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5375 if (patch_info->type == MONO_PATCH_INFO_EXC)
5380 * make sure we have enough space for exceptions
5381 * 16 is the size of two push_imm instructions and a call
5383 if (cfg->compile_aot)
5384 code_size = exc_count * 32;
5386 code_size = exc_count * 16;
5388 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5389 cfg->code_size *= 2;
5390 cfg->native_code = mono_realloc_native_code(cfg);
5391 mono_jit_stats.code_reallocs++;
5394 code = cfg->native_code + cfg->code_len;
5397 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5398 switch (patch_info->type) {
5399 case MONO_PATCH_INFO_EXC: {
5400 MonoClass *exc_class;
5404 x86_patch (patch_info->ip.i + cfg->native_code, code);
5406 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5407 g_assert (exc_class);
5408 throw_ip = patch_info->ip.i;
5410 /* Find a throw sequence for the same exception class */
5411 for (i = 0; i < nthrows; ++i)
5412 if (exc_classes [i] == exc_class)
5415 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5416 x86_jump_code (code, exc_throw_start [i]);
5417 patch_info->type = MONO_PATCH_INFO_NONE;
5422 /* Compute size of code following the push <OFFSET> */
5423 #if defined(__default_codegen__)
5425 #elif defined(__native_client_codegen__)
5426 code = mono_nacl_align (code);
5427 size = kNaClAlignment;
5429 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5431 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5432 /* Use the shorter form */
5434 x86_push_imm (code, 0);
5438 x86_push_imm (code, 0xf0f0f0f0);
5443 exc_classes [nthrows] = exc_class;
5444 exc_throw_start [nthrows] = code;
5447 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5448 patch_info->data.name = "mono_arch_throw_corlib_exception";
5449 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5450 patch_info->ip.i = code - cfg->native_code;
5451 x86_call_code (code, 0);
5452 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5457 exc_throw_end [nthrows] = code;
5469 cfg->code_len = code - cfg->native_code;
5471 g_assert (cfg->code_len < cfg->code_size);
5475 mono_arch_flush_icache (guint8 *code, gint size)
5481 mono_arch_flush_register_windows (void)
5486 mono_arch_is_inst_imm (gint64 imm)
5492 * Support for fast access to the thread-local lmf structure using the GS
5493 * segment register on NPTL + kernel 2.6.x.
5496 static gboolean tls_offset_inited = FALSE;
5499 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5501 if (!tls_offset_inited) {
5502 if (!getenv ("MONO_NO_TLS")) {
5505 * We need to init this multiple times, since when we are first called, the key might not
5506 * be initialized yet.
5508 appdomain_tls_offset = mono_domain_get_tls_key ();
5509 lmf_tls_offset = mono_get_jit_tls_key ();
5511 /* Only 64 tls entries can be accessed using inline code */
5512 if (appdomain_tls_offset >= 64)
5513 appdomain_tls_offset = -1;
5514 if (lmf_tls_offset >= 64)
5515 lmf_tls_offset = -1;
5518 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5520 tls_offset_inited = TRUE;
5521 appdomain_tls_offset = mono_domain_get_tls_offset ();
5522 lmf_tls_offset = mono_get_lmf_tls_offset ();
5523 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5530 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5534 #ifdef MONO_ARCH_HAVE_IMT
5536 // Linear handler, the bsearch head compare is shorter
5537 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5538 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5539 // x86_patch(ins,target)
5540 //[1 + 5] x86_jump_mem(inst,mem)
5543 #if defined(__default_codegen__)
5544 #define BR_SMALL_SIZE 2
5545 #define BR_LARGE_SIZE 5
5546 #elif defined(__native_client_codegen__)
5547 /* I suspect the size calculation below is actually incorrect. */
5548 /* TODO: fix the calculation that uses these sizes. */
5549 #define BR_SMALL_SIZE 16
5550 #define BR_LARGE_SIZE 12
5551 #endif /*__native_client_codegen__*/
5552 #define JUMP_IMM_SIZE 6
5553 #define ENABLE_WRONG_METHOD_CHECK 0
5557 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5559 int i, distance = 0;
5560 for (i = start; i < target; ++i)
5561 distance += imt_entries [i]->chunk_size;
5566 * LOCKING: called with the domain lock held
5569 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5570 gpointer fail_tramp)
5574 guint8 *code, *start;
5576 for (i = 0; i < count; ++i) {
5577 MonoIMTCheckItem *item = imt_entries [i];
5578 if (item->is_equals) {
5579 if (item->check_target_idx) {
5580 if (!item->compare_done)
5581 item->chunk_size += CMP_SIZE;
5582 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5585 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5587 item->chunk_size += JUMP_IMM_SIZE;
5588 #if ENABLE_WRONG_METHOD_CHECK
5589 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5594 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5595 imt_entries [item->check_target_idx]->compare_done = TRUE;
5597 size += item->chunk_size;
5599 #if defined(__native_client__) && defined(__native_client_codegen__)
5600 /* In Native Client, we don't re-use thunks, allocate from the */
5601 /* normal code manager paths. */
5602 code = mono_domain_code_reserve (domain, size);
5605 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5607 code = mono_domain_code_reserve (domain, size);
5610 for (i = 0; i < count; ++i) {
5611 MonoIMTCheckItem *item = imt_entries [i];
5612 item->code_target = code;
5613 if (item->is_equals) {
5614 if (item->check_target_idx) {
5615 if (!item->compare_done)
5616 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5617 item->jmp_code = code;
5618 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5619 if (item->has_target_code)
5620 x86_jump_code (code, item->value.target_code);
5622 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5625 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5626 item->jmp_code = code;
5627 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5628 if (item->has_target_code)
5629 x86_jump_code (code, item->value.target_code);
5631 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5632 x86_patch (item->jmp_code, code);
5633 x86_jump_code (code, fail_tramp);
5634 item->jmp_code = NULL;
5636 /* enable the commented code to assert on wrong method */
5637 #if ENABLE_WRONG_METHOD_CHECK
5638 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5639 item->jmp_code = code;
5640 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5642 if (item->has_target_code)
5643 x86_jump_code (code, item->value.target_code);
5645 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5646 #if ENABLE_WRONG_METHOD_CHECK
5647 x86_patch (item->jmp_code, code);
5648 x86_breakpoint (code);
5649 item->jmp_code = NULL;
5654 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5655 item->jmp_code = code;
5656 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5657 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5659 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5662 /* patch the branches to get to the target items */
5663 for (i = 0; i < count; ++i) {
5664 MonoIMTCheckItem *item = imt_entries [i];
5665 if (item->jmp_code) {
5666 if (item->check_target_idx) {
5667 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5673 mono_stats.imt_thunks_size += code - start;
5674 g_assert (code - start <= size);
5678 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5679 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5683 if (mono_jit_map_is_enabled ()) {
5686 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5688 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5689 mono_emit_jit_tramp (start, code - start, buff);
5693 nacl_domain_code_validate (domain, &start, size, &code);
5699 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5701 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5706 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5708 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5712 mono_arch_get_cie_program (void)
5716 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5717 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5723 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5725 MonoInst *ins = NULL;
5728 if (cmethod->klass == mono_defaults.math_class) {
5729 if (strcmp (cmethod->name, "Sin") == 0) {
5731 } else if (strcmp (cmethod->name, "Cos") == 0) {
5733 } else if (strcmp (cmethod->name, "Tan") == 0) {
5735 } else if (strcmp (cmethod->name, "Atan") == 0) {
5737 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5739 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5741 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5746 MONO_INST_NEW (cfg, ins, opcode);
5747 ins->type = STACK_R8;
5748 ins->dreg = mono_alloc_freg (cfg);
5749 ins->sreg1 = args [0]->dreg;
5750 MONO_ADD_INS (cfg->cbb, ins);
5753 if (cfg->opt & MONO_OPT_CMOV) {
5756 if (strcmp (cmethod->name, "Min") == 0) {
5757 if (fsig->params [0]->type == MONO_TYPE_I4)
5759 } else if (strcmp (cmethod->name, "Max") == 0) {
5760 if (fsig->params [0]->type == MONO_TYPE_I4)
5765 MONO_INST_NEW (cfg, ins, opcode);
5766 ins->type = STACK_I4;
5767 ins->dreg = mono_alloc_ireg (cfg);
5768 ins->sreg1 = args [0]->dreg;
5769 ins->sreg2 = args [1]->dreg;
5770 MONO_ADD_INS (cfg->cbb, ins);
5775 /* OP_FREM is not IEEE compatible */
5776 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5777 MONO_INST_NEW (cfg, ins, OP_FREM);
5778 ins->inst_i0 = args [0];
5779 ins->inst_i1 = args [1];
5788 mono_arch_print_tree (MonoInst *tree, int arity)
5793 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5799 if (appdomain_tls_offset == -1)
5802 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5803 ins->inst_offset = appdomain_tls_offset;
5808 mono_arch_get_patch_offset (guint8 *code)
5810 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5812 else if ((code [0] == 0xba))
5814 else if ((code [0] == 0x68))
5817 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5818 /* push <OFFSET>(<REG>) */
5820 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5821 /* call *<OFFSET>(<REG>) */
5823 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5826 else if ((code [0] == 0x58) && (code [1] == 0x05))
5827 /* pop %eax; add <OFFSET>, %eax */
5829 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5830 /* pop <REG>; add <OFFSET>, <REG> */
5832 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5833 /* mov <REG>, imm */
5836 g_assert_not_reached ();
5842 * mono_breakpoint_clean_code:
5844 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5845 * breakpoints in the original code, they are removed in the copy.
5847 * Returns TRUE if no sw breakpoint was present.
5850 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5853 gboolean can_write = TRUE;
5855 * If method_start is non-NULL we need to perform bound checks, since we access memory
5856 * at code - offset we could go before the start of the method and end up in a different
5857 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5860 if (!method_start || code - offset >= method_start) {
5861 memcpy (buf, code - offset, size);
5863 int diff = code - method_start;
5864 memset (buf, 0, size);
5865 memcpy (buf + offset - diff, method_start, diff + size - offset);
5868 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5869 int idx = mono_breakpoint_info_index [i];
5873 ptr = mono_breakpoint_info [idx].address;
5874 if (ptr >= code && ptr < code + size) {
5875 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5877 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5878 buf [ptr - code] = saved_byte;
5885 * mono_x86_get_this_arg_offset:
5887 * Return the offset of the stack location where this is passed during a virtual
5891 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
5897 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
5899 guint32 esp = regs [X86_ESP];
5900 CallInfo *cinfo = NULL;
5907 * The stack looks like:
5911 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
5913 res = (((MonoObject**)esp) [5 + (offset / 4)]);
5919 #define MAX_ARCH_DELEGATE_PARAMS 10
5922 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
5924 guint8 *code, *start;
5925 int code_reserve = 64;
5928 * The stack contains:
5934 start = code = mono_global_codeman_reserve (code_reserve);
5936 /* Replace the this argument with the target */
5937 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5938 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
5939 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5940 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5942 g_assert ((code - start) < code_reserve);
5945 /* 8 for mov_reg and jump, plus 8 for each parameter */
5946 #ifdef __native_client_codegen__
5947 /* TODO: calculate this size correctly */
5948 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
5950 code_reserve = 8 + (param_count * 8);
5951 #endif /* __native_client_codegen__ */
5953 * The stack contains:
5954 * <args in reverse order>
5959 * <args in reverse order>
5962 * without unbalancing the stack.
5963 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
5964 * and leaving original spot of first arg as placeholder in stack so
5965 * when callee pops stack everything works.
5968 start = code = mono_global_codeman_reserve (code_reserve);
5970 /* store delegate for access to method_ptr */
5971 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
5974 for (i = 0; i < param_count; ++i) {
5975 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
5976 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
5979 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5981 g_assert ((code - start) < code_reserve);
5984 nacl_global_codeman_validate(&start, code_reserve, &code);
5985 mono_debug_add_delegate_trampoline (start, code - start);
5988 *code_len = code - start;
5990 if (mono_jit_map_is_enabled ()) {
5993 buff = (char*)"delegate_invoke_has_target";
5995 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
5996 mono_emit_jit_tramp (start, code - start, buff);
6005 mono_arch_get_delegate_invoke_impls (void)
6012 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6013 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
6015 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6016 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6017 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
6024 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6026 guint8 *code, *start;
6028 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6031 /* FIXME: Support more cases */
6032 if (MONO_TYPE_ISSTRUCT (sig->ret))
6036 * The stack contains:
6042 static guint8* cached = NULL;
6047 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6049 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6051 mono_memory_barrier ();
6055 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6058 for (i = 0; i < sig->param_count; ++i)
6059 if (!mono_is_regsize_var (sig->params [i]))
6062 code = cache [sig->param_count];
6066 if (mono_aot_only) {
6067 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6068 start = mono_aot_get_trampoline (name);
6071 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6074 mono_memory_barrier ();
6076 cache [sig->param_count] = start;
6083 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6086 case X86_EAX: return (gpointer)ctx->eax;
6087 case X86_EBX: return (gpointer)ctx->ebx;
6088 case X86_ECX: return (gpointer)ctx->ecx;
6089 case X86_EDX: return (gpointer)ctx->edx;
6090 case X86_ESP: return (gpointer)ctx->esp;
6091 case X86_EBP: return (gpointer)ctx->ebp;
6092 case X86_ESI: return (gpointer)ctx->esi;
6093 case X86_EDI: return (gpointer)ctx->edi;
6094 default: g_assert_not_reached ();
6098 #ifdef MONO_ARCH_SIMD_INTRINSICS
6101 get_float_to_x_spill_area (MonoCompile *cfg)
6103 if (!cfg->fconv_to_r8_x_var) {
6104 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6105 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6107 return cfg->fconv_to_r8_x_var;
6111 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6114 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6117 int dreg, src_opcode;
6119 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6122 switch (src_opcode = ins->opcode) {
6123 case OP_FCONV_TO_I1:
6124 case OP_FCONV_TO_U1:
6125 case OP_FCONV_TO_I2:
6126 case OP_FCONV_TO_U2:
6127 case OP_FCONV_TO_I4:
6134 /* dreg is the IREG and sreg1 is the FREG */
6135 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6136 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6137 fconv->sreg1 = ins->sreg1;
6138 fconv->dreg = mono_alloc_ireg (cfg);
6139 fconv->type = STACK_VTYPE;
6140 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6142 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6146 ins->opcode = OP_XCONV_R8_TO_I4;
6148 ins->klass = mono_defaults.int32_class;
6149 ins->sreg1 = fconv->dreg;
6151 ins->type = STACK_I4;
6152 ins->backend.source_opcode = src_opcode;
6155 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6158 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6163 if (long_ins->opcode == OP_LNEG) {
6165 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6166 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6167 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6172 #ifdef MONO_ARCH_SIMD_INTRINSICS
6174 if (!(cfg->opt & MONO_OPT_SIMD))
6177 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6178 switch (long_ins->opcode) {
6180 vreg = long_ins->sreg1;
6182 if (long_ins->inst_c0) {
6183 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6184 ins->klass = long_ins->klass;
6185 ins->sreg1 = long_ins->sreg1;
6187 ins->type = STACK_VTYPE;
6188 ins->dreg = vreg = alloc_ireg (cfg);
6189 MONO_ADD_INS (cfg->cbb, ins);
6192 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6193 ins->klass = mono_defaults.int32_class;
6195 ins->type = STACK_I4;
6196 ins->dreg = long_ins->dreg + 1;
6197 MONO_ADD_INS (cfg->cbb, ins);
6199 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6200 ins->klass = long_ins->klass;
6201 ins->sreg1 = long_ins->sreg1;
6202 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6203 ins->type = STACK_VTYPE;
6204 ins->dreg = vreg = alloc_ireg (cfg);
6205 MONO_ADD_INS (cfg->cbb, ins);
6207 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6208 ins->klass = mono_defaults.int32_class;
6210 ins->type = STACK_I4;
6211 ins->dreg = long_ins->dreg + 2;
6212 MONO_ADD_INS (cfg->cbb, ins);
6214 long_ins->opcode = OP_NOP;
6216 case OP_INSERTX_I8_SLOW:
6217 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6218 ins->dreg = long_ins->dreg;
6219 ins->sreg1 = long_ins->dreg;
6220 ins->sreg2 = long_ins->sreg2 + 1;
6221 ins->inst_c0 = long_ins->inst_c0 * 2;
6222 MONO_ADD_INS (cfg->cbb, ins);
6224 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6225 ins->dreg = long_ins->dreg;
6226 ins->sreg1 = long_ins->dreg;
6227 ins->sreg2 = long_ins->sreg2 + 2;
6228 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6229 MONO_ADD_INS (cfg->cbb, ins);
6231 long_ins->opcode = OP_NOP;
6234 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6235 ins->dreg = long_ins->dreg;
6236 ins->sreg1 = long_ins->sreg1 + 1;
6237 ins->klass = long_ins->klass;
6238 ins->type = STACK_VTYPE;
6239 MONO_ADD_INS (cfg->cbb, ins);
6241 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6242 ins->dreg = long_ins->dreg;
6243 ins->sreg1 = long_ins->dreg;
6244 ins->sreg2 = long_ins->sreg1 + 2;
6246 ins->klass = long_ins->klass;
6247 ins->type = STACK_VTYPE;
6248 MONO_ADD_INS (cfg->cbb, ins);
6250 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6251 ins->dreg = long_ins->dreg;
6252 ins->sreg1 = long_ins->dreg;;
6253 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6254 ins->klass = long_ins->klass;
6255 ins->type = STACK_VTYPE;
6256 MONO_ADD_INS (cfg->cbb, ins);
6258 long_ins->opcode = OP_NOP;
6261 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6264 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6266 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6269 gpointer *sp, old_value;
6271 const unsigned char *handler;
6273 /*Decode the first instruction to figure out where did we store the spvar*/
6274 /*Our jit MUST generate the following:
6276 Which is encoded as: 0x89 mod_rm.
6277 mod_rm (esp, ebp, imm) which can be: (imm will never be zero)
6278 mod (reg + imm8): 01 reg(esp): 100 rm(ebp): 101 -> 01100101 (0x65)
6279 mod (reg + imm32): 10 reg(esp): 100 rm(ebp): 101 -> 10100101 (0xA5)
6281 handler = clause->handler_start;
6283 if (*handler != 0x89)
6288 if (*handler == 0x65)
6289 offset = *(signed char*)(handler + 1);
6290 else if (*handler == 0xA5)
6291 offset = *(int*)(handler + 1);
6296 bp = MONO_CONTEXT_GET_BP (ctx);
6297 sp = *(gpointer*)(bp + offset);
6300 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6309 * mono_aot_emit_load_got_addr:
6311 * Emit code to load the got address.
6312 * On x86, the result is placed into EBX.
6315 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6317 x86_call_imm (code, 0);
6319 * The patch needs to point to the pop, since the GOT offset needs
6320 * to be added to that address.
6323 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6325 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6326 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6327 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6333 * mono_ppc_emit_load_aotconst:
6335 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6336 * TARGET from the mscorlib GOT in full-aot code.
6337 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6341 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6343 /* Load the mscorlib got address */
6344 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6345 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6346 /* arch_emit_got_access () patches this */
6347 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6352 /* Can't put this into mini-x86.h */
6354 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6357 mono_arch_get_trampolines (gboolean aot)
6359 MonoTrampInfo *info;
6360 GSList *tramps = NULL;
6362 mono_x86_get_signal_exception_trampoline (&info, aot);
6364 tramps = g_slist_append (tramps, info);
6371 #define DBG_SIGNAL SIGBUS
6373 #define DBG_SIGNAL SIGSEGV
6376 /* Soft Debug support */
6377 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6380 * mono_arch_set_breakpoint:
6382 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6383 * The location should contain code emitted by OP_SEQ_POINT.
6386 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6391 * In production, we will use int3 (has to fix the size in the md
6392 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6395 g_assert (code [0] == 0x90);
6396 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6400 * mono_arch_clear_breakpoint:
6402 * Clear the breakpoint at IP.
6405 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6410 for (i = 0; i < 6; ++i)
6415 * mono_arch_start_single_stepping:
6417 * Start single stepping.
6420 mono_arch_start_single_stepping (void)
6422 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6426 * mono_arch_stop_single_stepping:
6428 * Stop single stepping.
6431 mono_arch_stop_single_stepping (void)
6433 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6437 * mono_arch_is_single_step_event:
6439 * Return whenever the machine state in SIGCTX corresponds to a single
6443 mono_arch_is_single_step_event (void *info, void *sigctx)
6446 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info; /* Sometimes the address is off by 4 */
6447 if ((einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6452 siginfo_t* sinfo = (siginfo_t*) info;
6453 /* Sometimes the address is off by 4 */
6454 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6462 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6465 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info; /* Sometimes the address is off by 4 */
6466 if ((einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6471 siginfo_t* sinfo = (siginfo_t*)info;
6472 /* Sometimes the address is off by 4 */
6473 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6481 * mono_arch_get_ip_for_breakpoint:
6483 * See mini-amd64.c for docs.
6486 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
6488 guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
6493 #define BREAKPOINT_SIZE 6
6496 * mono_arch_get_ip_for_single_step:
6498 * See mini-amd64.c for docs.
6501 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
6503 guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
6505 /* Size of x86_alu_reg_imm */
6512 * mono_arch_skip_breakpoint:
6514 * See mini-amd64.c for docs.
6517 mono_arch_skip_breakpoint (MonoContext *ctx)
6519 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6523 * mono_arch_skip_single_step:
6525 * See mini-amd64.c for docs.
6528 mono_arch_skip_single_step (MonoContext *ctx)
6530 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6534 * mono_arch_get_seq_point_info:
6536 * See mini-amd64.c for docs.
6539 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)