2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * (C) 2003 Ximian, Inc.
18 #include <mono/metadata/appdomain.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/metadata/threads.h>
21 #include <mono/metadata/profiler-private.h>
22 #include <mono/metadata/mono-debug.h>
23 #include <mono/utils/mono-math.h>
24 #include <mono/utils/mono-counters.h>
31 /* On windows, these hold the key returned by TlsAlloc () */
32 static gint lmf_tls_offset = -1;
33 static gint lmf_addr_tls_offset = -1;
34 static gint appdomain_tls_offset = -1;
37 static gboolean optimize_for_xen = TRUE;
39 #define optimize_for_xen 0
43 static gboolean is_win32 = TRUE;
45 static gboolean is_win32 = FALSE;
48 /* This mutex protects architecture specific caches */
49 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
50 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
51 static CRITICAL_SECTION mini_arch_mutex;
53 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
58 /* Under windows, the default pinvoke calling convention is stdcall */
59 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT))
61 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL)
65 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
68 mono_arch_regname (int reg)
71 case X86_EAX: return "%eax";
72 case X86_EBX: return "%ebx";
73 case X86_ECX: return "%ecx";
74 case X86_EDX: return "%edx";
75 case X86_ESP: return "%esp";
76 case X86_EBP: return "%ebp";
77 case X86_EDI: return "%edi";
78 case X86_ESI: return "%esi";
84 mono_arch_fregname (int reg)
109 mono_arch_xregname (int reg)
150 /* Only if storage == ArgValuetypeInReg */
151 ArgStorage pair_storage [2];
160 gboolean need_stack_align;
161 guint32 stack_align_amount;
169 #define FLOAT_PARAM_REGS 0
171 static X86_Reg_No param_regs [] = { 0 };
173 #if defined(PLATFORM_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
174 #define SMALL_STRUCTS_IN_REGS
175 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
179 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
181 ainfo->offset = *stack_size;
183 if (*gr >= PARAM_REGS) {
184 ainfo->storage = ArgOnStack;
185 (*stack_size) += sizeof (gpointer);
188 ainfo->storage = ArgInIReg;
189 ainfo->reg = param_regs [*gr];
195 add_general_pair (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
197 ainfo->offset = *stack_size;
199 g_assert (PARAM_REGS == 0);
201 ainfo->storage = ArgOnStack;
202 (*stack_size) += sizeof (gpointer) * 2;
206 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
208 ainfo->offset = *stack_size;
210 if (*gr >= FLOAT_PARAM_REGS) {
211 ainfo->storage = ArgOnStack;
212 (*stack_size) += is_double ? 8 : 4;
215 /* A double register */
217 ainfo->storage = ArgInDoubleSSEReg;
219 ainfo->storage = ArgInFloatSSEReg;
227 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
229 guint32 *gr, guint32 *fr, guint32 *stack_size)
234 klass = mono_class_from_mono_type (type);
235 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
237 #ifdef SMALL_STRUCTS_IN_REGS
238 if (sig->pinvoke && is_return) {
239 MonoMarshalType *info;
242 * the exact rules are not very well documented, the code below seems to work with the
243 * code generated by gcc 3.3.3 -mno-cygwin.
245 info = mono_marshal_load_type_info (klass);
248 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
250 /* Special case structs with only a float member */
251 if ((info->native_size == 8) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R8)) {
252 ainfo->storage = ArgValuetypeInReg;
253 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
256 if ((info->native_size == 4) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R4)) {
257 ainfo->storage = ArgValuetypeInReg;
258 ainfo->pair_storage [0] = ArgOnFloatFpStack;
261 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
262 ainfo->storage = ArgValuetypeInReg;
263 ainfo->pair_storage [0] = ArgInIReg;
264 ainfo->pair_regs [0] = return_regs [0];
265 if (info->native_size > 4) {
266 ainfo->pair_storage [1] = ArgInIReg;
267 ainfo->pair_regs [1] = return_regs [1];
274 ainfo->offset = *stack_size;
275 ainfo->storage = ArgOnStack;
276 *stack_size += ALIGN_TO (size, sizeof (gpointer));
282 * Obtain information about a call according to the calling convention.
283 * For x86 ELF, see the "System V Application Binary Interface Intel386
284 * Architecture Processor Supplment, Fourth Edition" document for more
286 * For x86 win32, see ???.
289 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
293 int n = sig->hasthis + sig->param_count;
294 guint32 stack_size = 0;
298 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
300 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
307 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
308 switch (ret_type->type) {
309 case MONO_TYPE_BOOLEAN:
320 case MONO_TYPE_FNPTR:
321 case MONO_TYPE_CLASS:
322 case MONO_TYPE_OBJECT:
323 case MONO_TYPE_SZARRAY:
324 case MONO_TYPE_ARRAY:
325 case MONO_TYPE_STRING:
326 cinfo->ret.storage = ArgInIReg;
327 cinfo->ret.reg = X86_EAX;
331 cinfo->ret.storage = ArgInIReg;
332 cinfo->ret.reg = X86_EAX;
335 cinfo->ret.storage = ArgOnFloatFpStack;
338 cinfo->ret.storage = ArgOnDoubleFpStack;
340 case MONO_TYPE_GENERICINST:
341 if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
342 cinfo->ret.storage = ArgInIReg;
343 cinfo->ret.reg = X86_EAX;
347 case MONO_TYPE_VALUETYPE: {
348 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
350 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
351 if (cinfo->ret.storage == ArgOnStack)
352 /* The caller passes the address where the value is stored */
353 add_general (&gr, &stack_size, &cinfo->ret);
356 case MONO_TYPE_TYPEDBYREF:
357 /* Same as a valuetype with size 24 */
358 add_general (&gr, &stack_size, &cinfo->ret);
362 cinfo->ret.storage = ArgNone;
365 g_error ("Can't handle as return value 0x%x", sig->ret->type);
371 add_general (&gr, &stack_size, cinfo->args + 0);
373 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
375 fr = FLOAT_PARAM_REGS;
377 /* Emit the signature cookie just before the implicit arguments */
378 add_general (&gr, &stack_size, &cinfo->sig_cookie);
381 for (i = 0; i < sig->param_count; ++i) {
382 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
385 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
386 /* We allways pass the sig cookie on the stack for simplicity */
388 * Prevent implicit arguments + the sig cookie from being passed
392 fr = FLOAT_PARAM_REGS;
394 /* Emit the signature cookie just before the implicit arguments */
395 add_general (&gr, &stack_size, &cinfo->sig_cookie);
398 if (sig->params [i]->byref) {
399 add_general (&gr, &stack_size, ainfo);
402 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
403 switch (ptype->type) {
404 case MONO_TYPE_BOOLEAN:
407 add_general (&gr, &stack_size, ainfo);
412 add_general (&gr, &stack_size, ainfo);
416 add_general (&gr, &stack_size, ainfo);
421 case MONO_TYPE_FNPTR:
422 case MONO_TYPE_CLASS:
423 case MONO_TYPE_OBJECT:
424 case MONO_TYPE_STRING:
425 case MONO_TYPE_SZARRAY:
426 case MONO_TYPE_ARRAY:
427 add_general (&gr, &stack_size, ainfo);
429 case MONO_TYPE_GENERICINST:
430 if (!mono_type_generic_inst_is_valuetype (sig->params [i])) {
431 add_general (&gr, &stack_size, ainfo);
435 case MONO_TYPE_VALUETYPE:
436 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
438 case MONO_TYPE_TYPEDBYREF:
439 stack_size += sizeof (MonoTypedRef);
440 ainfo->storage = ArgOnStack;
444 add_general_pair (&gr, &stack_size, ainfo);
447 add_float (&fr, &stack_size, ainfo, FALSE);
450 add_float (&fr, &stack_size, ainfo, TRUE);
453 g_error ("unexpected type 0x%x", ptype->type);
454 g_assert_not_reached ();
458 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
460 fr = FLOAT_PARAM_REGS;
462 /* Emit the signature cookie just before the implicit arguments */
463 add_general (&gr, &stack_size, &cinfo->sig_cookie);
466 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
467 cinfo->need_stack_align = TRUE;
468 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
469 stack_size += cinfo->stack_align_amount;
472 cinfo->stack_usage = stack_size;
473 cinfo->reg_usage = gr;
474 cinfo->freg_usage = fr;
479 * mono_arch_get_argument_info:
480 * @csig: a method signature
481 * @param_count: the number of parameters to consider
482 * @arg_info: an array to store the result infos
484 * Gathers information on parameters such as size, alignment and
485 * padding. arg_info should be large enought to hold param_count + 1 entries.
487 * Returns the size of the argument area on the stack.
490 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
492 int k, args_size = 0;
498 cinfo = get_call_info (NULL, NULL, csig, FALSE);
500 if (MONO_TYPE_ISSTRUCT (csig->ret) && (cinfo->ret.storage == ArgOnStack)) {
501 args_size += sizeof (gpointer);
505 arg_info [0].offset = offset;
508 args_size += sizeof (gpointer);
512 arg_info [0].size = args_size;
514 for (k = 0; k < param_count; k++) {
515 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
517 /* ignore alignment for now */
520 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
521 arg_info [k].pad = pad;
523 arg_info [k + 1].pad = 0;
524 arg_info [k + 1].size = size;
526 arg_info [k + 1].offset = offset;
530 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
531 align = MONO_ARCH_FRAME_ALIGNMENT;
534 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
535 arg_info [k].pad = pad;
542 static const guchar cpuid_impl [] = {
543 0x55, /* push %ebp */
544 0x89, 0xe5, /* mov %esp,%ebp */
545 0x53, /* push %ebx */
546 0x8b, 0x45, 0x08, /* mov 0x8(%ebp),%eax */
547 0x0f, 0xa2, /* cpuid */
548 0x50, /* push %eax */
549 0x8b, 0x45, 0x10, /* mov 0x10(%ebp),%eax */
550 0x89, 0x18, /* mov %ebx,(%eax) */
551 0x8b, 0x45, 0x14, /* mov 0x14(%ebp),%eax */
552 0x89, 0x08, /* mov %ecx,(%eax) */
553 0x8b, 0x45, 0x18, /* mov 0x18(%ebp),%eax */
554 0x89, 0x10, /* mov %edx,(%eax) */
556 0x8b, 0x55, 0x0c, /* mov 0xc(%ebp),%edx */
557 0x89, 0x02, /* mov %eax,(%edx) */
563 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
566 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
570 __asm__ __volatile__ (
573 "movl %%eax, %%edx\n"
574 "xorl $0x200000, %%eax\n"
579 "xorl %%edx, %%eax\n"
580 "andl $0x200000, %%eax\n"
602 /* Have to use the code manager to get around WinXP DEP */
603 static CpuidFunc func = NULL;
606 ptr = mono_global_codeman_reserve (sizeof (cpuid_impl));
607 memcpy (ptr, cpuid_impl, sizeof (cpuid_impl));
608 func = (CpuidFunc)ptr;
610 func (id, p_eax, p_ebx, p_ecx, p_edx);
613 * We use this approach because of issues with gcc and pic code, see:
614 * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
615 __asm__ __volatile__ ("cpuid"
616 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
625 * Initialize the cpu to execute managed code.
628 mono_arch_cpu_init (void)
630 /* spec compliance requires running with double precision */
634 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
635 fpcw &= ~X86_FPCW_PRECC_MASK;
636 fpcw |= X86_FPCW_PREC_DOUBLE;
637 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
638 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
640 _control87 (_PC_53, MCW_PC);
645 * Initialize architecture specific code.
648 mono_arch_init (void)
650 InitializeCriticalSection (&mini_arch_mutex);
654 * Cleanup architecture specific code.
657 mono_arch_cleanup (void)
659 DeleteCriticalSection (&mini_arch_mutex);
663 * This function returns the optimizations supported on this cpu.
666 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
668 int eax, ebx, ecx, edx;
672 /* Feature Flags function, flags returned in EDX. */
673 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
674 if (edx & (1 << 15)) {
675 opts |= MONO_OPT_CMOV;
677 opts |= MONO_OPT_FCMOV;
679 *exclude_mask |= MONO_OPT_FCMOV;
681 *exclude_mask |= MONO_OPT_CMOV;
683 opts |= MONO_OPT_SSE2;
685 *exclude_mask |= MONO_OPT_SSE2;
687 #ifdef MONO_ARCH_SIMD_INTRINSICS
688 /*SIMD intrinsics require at least SSE2.*/
689 if (!(opts & MONO_OPT_SSE2))
690 *exclude_mask |= MONO_OPT_SIMD;
697 * This function test for all SSE functions supported.
699 * Returns a bitmask corresponding to all supported versions.
701 * TODO detect other versions like SSE4a.
704 mono_arch_cpu_enumerate_simd_versions (void)
706 int eax, ebx, ecx, edx;
707 guint32 sse_opts = 0;
709 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
711 sse_opts |= 1 << SIMD_VERSION_SSE1;
713 sse_opts |= 1 << SIMD_VERSION_SSE2;
715 sse_opts |= 1 << SIMD_VERSION_SSE3;
717 sse_opts |= 1 << SIMD_VERSION_SSSE3;
719 sse_opts |= 1 << SIMD_VERSION_SSE41;
721 sse_opts |= 1 << SIMD_VERSION_SSE42;
727 * Determine whenever the trap whose info is in SIGINFO is caused by
731 mono_arch_is_int_overflow (void *sigctx, void *info)
736 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
738 ip = (guint8*)ctx.eip;
740 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
744 switch (x86_modrm_rm (ip [1])) {
764 g_assert_not_reached ();
776 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
781 for (i = 0; i < cfg->num_varinfo; i++) {
782 MonoInst *ins = cfg->varinfo [i];
783 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
786 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
789 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
790 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
793 /* we dont allocate I1 to registers because there is no simply way to sign extend
794 * 8bit quantities in caller saved registers on x86 */
795 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
796 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
797 g_assert (i == vmv->idx);
798 vars = g_list_prepend (vars, vmv);
802 vars = mono_varlist_sort (cfg, vars, 0);
808 mono_arch_get_global_int_regs (MonoCompile *cfg)
812 /* we can use 3 registers for global allocation */
813 regs = g_list_prepend (regs, (gpointer)X86_EBX);
814 regs = g_list_prepend (regs, (gpointer)X86_ESI);
815 regs = g_list_prepend (regs, (gpointer)X86_EDI);
821 * mono_arch_regalloc_cost:
823 * Return the cost, in number of memory references, of the action of
824 * allocating the variable VMV into a register during global register
828 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
830 MonoInst *ins = cfg->varinfo [vmv->idx];
832 if (cfg->method->save_lmf)
833 /* The register is already saved */
834 return (ins->opcode == OP_ARG) ? 1 : 0;
836 /* push+pop+possible load if it is an argument */
837 return (ins->opcode == OP_ARG) ? 3 : 2;
841 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
843 static int inited = FALSE;
844 static int count = 0;
846 if (cfg->arch.need_stack_frame_inited) {
847 g_assert (cfg->arch.need_stack_frame == flag);
851 cfg->arch.need_stack_frame = flag;
852 cfg->arch.need_stack_frame_inited = TRUE;
858 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
863 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
867 needs_stack_frame (MonoCompile *cfg)
869 MonoMethodSignature *sig;
870 MonoMethodHeader *header;
871 gboolean result = FALSE;
873 #if defined(__APPLE__)
874 /*OSX requires stack frame code to have the correct alignment. */
878 if (cfg->arch.need_stack_frame_inited)
879 return cfg->arch.need_stack_frame;
881 header = mono_method_get_header (cfg->method);
882 sig = mono_method_signature (cfg->method);
884 if (cfg->disable_omit_fp)
886 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
888 else if (cfg->method->save_lmf)
890 else if (cfg->stack_offset)
892 else if (cfg->param_area)
894 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
896 else if (header->num_clauses)
898 else if (sig->param_count + sig->hasthis)
900 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
902 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
903 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
906 set_needs_stack_frame (cfg, result);
908 return cfg->arch.need_stack_frame;
912 * Set var information according to the calling convention. X86 version.
913 * The locals var stuff should most likely be split in another method.
916 mono_arch_allocate_vars (MonoCompile *cfg)
918 MonoMethodSignature *sig;
919 MonoMethodHeader *header;
921 guint32 locals_stack_size, locals_stack_align;
926 header = mono_method_get_header (cfg->method);
927 sig = mono_method_signature (cfg->method);
929 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
931 cfg->frame_reg = X86_EBP;
934 /* Reserve space to save LMF and caller saved registers */
936 if (cfg->method->save_lmf) {
937 offset += sizeof (MonoLMF);
939 if (cfg->used_int_regs & (1 << X86_EBX)) {
943 if (cfg->used_int_regs & (1 << X86_EDI)) {
947 if (cfg->used_int_regs & (1 << X86_ESI)) {
952 switch (cinfo->ret.storage) {
953 case ArgValuetypeInReg:
954 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
956 cfg->ret->opcode = OP_REGOFFSET;
957 cfg->ret->inst_basereg = X86_EBP;
958 cfg->ret->inst_offset = - offset;
964 /* Allocate locals */
965 offsets = mono_allocate_stack_slots (cfg, &locals_stack_size, &locals_stack_align);
966 if (locals_stack_align) {
967 offset += (locals_stack_align - 1);
968 offset &= ~(locals_stack_align - 1);
971 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
972 * have locals larger than 8 bytes we need to make sure that
973 * they have the appropriate offset.
975 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
976 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
977 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
978 if (offsets [i] != -1) {
979 MonoInst *inst = cfg->varinfo [i];
980 inst->opcode = OP_REGOFFSET;
981 inst->inst_basereg = X86_EBP;
982 inst->inst_offset = - (offset + offsets [i]);
983 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
986 offset += locals_stack_size;
990 * Allocate arguments+return value
993 switch (cinfo->ret.storage) {
995 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
997 * In the new IR, the cfg->vret_addr variable represents the
998 * vtype return value.
1000 cfg->vret_addr->opcode = OP_REGOFFSET;
1001 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1002 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1003 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1004 printf ("vret_addr =");
1005 mono_print_ins (cfg->vret_addr);
1008 cfg->ret->opcode = OP_REGOFFSET;
1009 cfg->ret->inst_basereg = X86_EBP;
1010 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1013 case ArgValuetypeInReg:
1016 cfg->ret->opcode = OP_REGVAR;
1017 cfg->ret->inst_c0 = cinfo->ret.reg;
1018 cfg->ret->dreg = cinfo->ret.reg;
1021 case ArgOnFloatFpStack:
1022 case ArgOnDoubleFpStack:
1025 g_assert_not_reached ();
1028 if (sig->call_convention == MONO_CALL_VARARG) {
1029 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1030 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1033 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1034 ArgInfo *ainfo = &cinfo->args [i];
1035 inst = cfg->args [i];
1036 if (inst->opcode != OP_REGVAR) {
1037 inst->opcode = OP_REGOFFSET;
1038 inst->inst_basereg = X86_EBP;
1040 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1043 cfg->stack_offset = offset;
1047 mono_arch_create_vars (MonoCompile *cfg)
1049 MonoMethodSignature *sig;
1052 sig = mono_method_signature (cfg->method);
1054 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1056 if (cinfo->ret.storage == ArgValuetypeInReg)
1057 cfg->ret_var_is_local = TRUE;
1058 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1059 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1064 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1065 * so we try to do it just once when we have multiple fp arguments in a row.
1066 * We don't use this mechanism generally because for int arguments the generated code
1067 * is slightly bigger and new generation cpus optimize away the dependency chains
1068 * created by push instructions on the esp value.
1069 * fp_arg_setup is the first argument in the execution sequence where the esp register
1072 static G_GNUC_UNUSED int
1073 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1078 for (; start_arg < sig->param_count; ++start_arg) {
1079 t = mini_type_get_underlying_type (NULL, sig->params [start_arg]);
1080 if (!t->byref && t->type == MONO_TYPE_R8) {
1081 fp_space += sizeof (double);
1082 *fp_arg_setup = start_arg;
1091 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1093 MonoMethodSignature *tmp_sig;
1095 /* FIXME: Add support for signature tokens to AOT */
1096 cfg->disable_aot = TRUE;
1099 * mono_ArgIterator_Setup assumes the signature cookie is
1100 * passed first and all the arguments which were before it are
1101 * passed on the stack after the signature. So compensate by
1102 * passing a different signature.
1104 tmp_sig = mono_metadata_signature_dup (call->signature);
1105 tmp_sig->param_count -= call->signature->sentinelpos;
1106 tmp_sig->sentinelpos = 0;
1107 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1109 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1114 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1120 LLVMCallInfo *linfo;
1122 n = sig->param_count + sig->hasthis;
1124 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1126 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1129 * LLVM always uses the native ABI while we use our own ABI, the
1130 * only difference is the handling of vtypes:
1131 * - we only pass/receive them in registers in some cases, and only
1132 * in 1 or 2 integer registers.
1134 if (cinfo->ret.storage == ArgValuetypeInReg) {
1136 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1137 cfg->disable_llvm = TRUE;
1141 cfg->exception_message = g_strdup ("vtype ret in call");
1142 cfg->disable_llvm = TRUE;
1144 linfo->ret.storage = LLVMArgVtypeInReg;
1145 for (j = 0; j < 2; ++j)
1146 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1150 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1151 /* Vtype returned using a hidden argument */
1152 linfo->ret.storage = LLVMArgVtypeRetAddr;
1155 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != ArgInIReg) {
1157 cfg->exception_message = g_strdup ("vtype ret in call");
1158 cfg->disable_llvm = TRUE;
1161 for (i = 0; i < n; ++i) {
1162 ainfo = cinfo->args + i;
1164 linfo->args [i].storage = LLVMArgNone;
1166 switch (ainfo->storage) {
1168 linfo->args [i].storage = LLVMArgInIReg;
1170 case ArgInDoubleSSEReg:
1171 case ArgInFloatSSEReg:
1172 linfo->args [i].storage = LLVMArgInFPReg;
1175 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1176 linfo->args [i].storage = LLVMArgVtypeByVal;
1178 linfo->args [i].storage = LLVMArgInIReg;
1179 if (!sig->params [i - sig->hasthis]->byref) {
1180 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1181 linfo->args [i].storage = LLVMArgInFPReg;
1182 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1183 linfo->args [i].storage = LLVMArgInFPReg;
1188 case ArgValuetypeInReg:
1190 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1191 cfg->disable_llvm = TRUE;
1195 cfg->exception_message = g_strdup ("vtype arg");
1196 cfg->disable_llvm = TRUE;
1198 linfo->args [i].storage = LLVMArgVtypeInReg;
1199 for (j = 0; j < 2; ++j)
1200 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1204 cfg->exception_message = g_strdup ("ainfo->storage");
1205 cfg->disable_llvm = TRUE;
1215 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1218 MonoMethodSignature *sig;
1221 int sentinelpos = 0;
1223 sig = call->signature;
1224 n = sig->param_count + sig->hasthis;
1226 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1228 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1229 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1231 if (cinfo->need_stack_align) {
1232 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1233 arg->dreg = X86_ESP;
1234 arg->sreg1 = X86_ESP;
1235 arg->inst_imm = cinfo->stack_align_amount;
1236 MONO_ADD_INS (cfg->cbb, arg);
1239 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1240 if (cinfo->ret.storage == ArgValuetypeInReg) {
1242 * Tell the JIT to use a more efficient calling convention: call using
1243 * OP_CALL, compute the result location after the call, and save the
1246 call->vret_in_reg = TRUE;
1248 NULLIFY_INS (call->vret_var);
1252 /* Handle the case where there are no implicit arguments */
1253 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1254 emit_sig_cookie (cfg, call, cinfo);
1257 /* Arguments are pushed in the reverse order */
1258 for (i = n - 1; i >= 0; i --) {
1259 ArgInfo *ainfo = cinfo->args + i;
1262 if (i >= sig->hasthis)
1263 t = sig->params [i - sig->hasthis];
1265 t = &mono_defaults.int_class->byval_arg;
1266 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1268 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1270 in = call->args [i];
1271 arg->cil_code = in->cil_code;
1272 arg->sreg1 = in->dreg;
1273 arg->type = in->type;
1275 g_assert (in->dreg != -1);
1277 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1281 g_assert (in->klass);
1283 if (t->type == MONO_TYPE_TYPEDBYREF) {
1284 size = sizeof (MonoTypedRef);
1285 align = sizeof (gpointer);
1288 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1292 arg->opcode = OP_OUTARG_VT;
1293 arg->sreg1 = in->dreg;
1294 arg->klass = in->klass;
1295 arg->backend.size = size;
1297 MONO_ADD_INS (cfg->cbb, arg);
1301 switch (ainfo->storage) {
1303 arg->opcode = OP_X86_PUSH;
1305 if (t->type == MONO_TYPE_R4) {
1306 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1307 arg->opcode = OP_STORER4_MEMBASE_REG;
1308 arg->inst_destbasereg = X86_ESP;
1309 arg->inst_offset = 0;
1310 } else if (t->type == MONO_TYPE_R8) {
1311 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1312 arg->opcode = OP_STORER8_MEMBASE_REG;
1313 arg->inst_destbasereg = X86_ESP;
1314 arg->inst_offset = 0;
1315 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1317 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1322 g_assert_not_reached ();
1325 MONO_ADD_INS (cfg->cbb, arg);
1328 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1329 /* Emit the signature cookie just before the implicit arguments */
1330 emit_sig_cookie (cfg, call, cinfo);
1334 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1337 if (cinfo->ret.storage == ArgValuetypeInReg) {
1340 else if (cinfo->ret.storage == ArgInIReg) {
1342 /* The return address is passed in a register */
1343 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1344 vtarg->sreg1 = call->inst.dreg;
1345 vtarg->dreg = mono_alloc_ireg (cfg);
1346 MONO_ADD_INS (cfg->cbb, vtarg);
1348 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1351 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1352 vtarg->type = STACK_MP;
1353 vtarg->sreg1 = call->vret_var->dreg;
1354 MONO_ADD_INS (cfg->cbb, vtarg);
1357 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1358 if (cinfo->ret.storage != ArgValuetypeInReg)
1359 cinfo->stack_usage -= 4;
1362 call->stack_usage = cinfo->stack_usage;
1366 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1369 int size = ins->backend.size;
1372 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1373 arg->sreg1 = src->dreg;
1375 MONO_ADD_INS (cfg->cbb, arg);
1376 } else if (size <= 20) {
1377 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1378 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1380 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1381 arg->inst_basereg = src->dreg;
1382 arg->inst_offset = 0;
1383 arg->inst_imm = size;
1385 MONO_ADD_INS (cfg->cbb, arg);
1390 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1392 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1395 if (ret->type == MONO_TYPE_R4) {
1396 if (COMPILE_LLVM (cfg))
1397 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1400 } else if (ret->type == MONO_TYPE_R8) {
1401 if (COMPILE_LLVM (cfg))
1402 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1405 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1406 if (COMPILE_LLVM (cfg))
1407 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1409 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1410 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1416 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1420 * Allow tracing to work with this interface (with an optional argument)
1423 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1427 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1428 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1430 /* if some args are passed in registers, we need to save them here */
1431 x86_push_reg (code, X86_EBP);
1433 if (cfg->compile_aot) {
1434 x86_push_imm (code, cfg->method);
1435 x86_mov_reg_imm (code, X86_EAX, func);
1436 x86_call_reg (code, X86_EAX);
1438 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1439 x86_push_imm (code, cfg->method);
1440 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1441 x86_call_code (code, 0);
1443 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1457 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1460 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1461 MonoMethod *method = cfg->method;
1463 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret)->type) {
1464 case MONO_TYPE_VOID:
1465 /* special case string .ctor icall */
1466 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1467 save_mode = SAVE_EAX;
1468 stack_usage = enable_arguments ? 8 : 4;
1470 save_mode = SAVE_NONE;
1474 save_mode = SAVE_EAX_EDX;
1475 stack_usage = enable_arguments ? 16 : 8;
1479 save_mode = SAVE_FP;
1480 stack_usage = enable_arguments ? 16 : 8;
1482 case MONO_TYPE_GENERICINST:
1483 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
1484 save_mode = SAVE_EAX;
1485 stack_usage = enable_arguments ? 8 : 4;
1489 case MONO_TYPE_VALUETYPE:
1490 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1491 save_mode = SAVE_STRUCT;
1492 stack_usage = enable_arguments ? 4 : 0;
1495 save_mode = SAVE_EAX;
1496 stack_usage = enable_arguments ? 8 : 4;
1500 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1502 switch (save_mode) {
1504 x86_push_reg (code, X86_EDX);
1505 x86_push_reg (code, X86_EAX);
1506 if (enable_arguments) {
1507 x86_push_reg (code, X86_EDX);
1508 x86_push_reg (code, X86_EAX);
1513 x86_push_reg (code, X86_EAX);
1514 if (enable_arguments) {
1515 x86_push_reg (code, X86_EAX);
1520 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1521 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1522 if (enable_arguments) {
1523 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1524 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1529 if (enable_arguments) {
1530 x86_push_membase (code, X86_EBP, 8);
1539 if (cfg->compile_aot) {
1540 x86_push_imm (code, method);
1541 x86_mov_reg_imm (code, X86_EAX, func);
1542 x86_call_reg (code, X86_EAX);
1544 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1545 x86_push_imm (code, method);
1546 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1547 x86_call_code (code, 0);
1550 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1552 switch (save_mode) {
1554 x86_pop_reg (code, X86_EAX);
1555 x86_pop_reg (code, X86_EDX);
1558 x86_pop_reg (code, X86_EAX);
1561 x86_fld_membase (code, X86_ESP, 0, TRUE);
1562 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1569 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1574 #define EMIT_COND_BRANCH(ins,cond,sign) \
1575 if (ins->inst_true_bb->native_offset) { \
1576 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1578 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1579 if ((cfg->opt & MONO_OPT_BRANCH) && \
1580 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1581 x86_branch8 (code, cond, 0, sign); \
1583 x86_branch32 (code, cond, 0, sign); \
1587 * Emit an exception if condition is fail and
1588 * if possible do a directly branch to target
1590 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1592 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1593 if (tins == NULL) { \
1594 mono_add_patch_info (cfg, code - cfg->native_code, \
1595 MONO_PATCH_INFO_EXC, exc_name); \
1596 x86_branch32 (code, cond, 0, signed); \
1598 EMIT_COND_BRANCH (tins, cond, signed); \
1602 #define EMIT_FPCOMPARE(code) do { \
1603 x86_fcompp (code); \
1604 x86_fnstsw (code); \
1609 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1611 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1612 x86_call_code (code, 0);
1617 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1620 * mono_peephole_pass_1:
1622 * Perform peephole opts which should/can be performed before local regalloc
1625 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1629 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1630 MonoInst *last_ins = ins->prev;
1632 switch (ins->opcode) {
1635 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1637 * X86_LEA is like ADD, but doesn't have the
1638 * sreg1==dreg restriction.
1640 ins->opcode = OP_X86_LEA_MEMBASE;
1641 ins->inst_basereg = ins->sreg1;
1642 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1643 ins->opcode = OP_X86_INC_REG;
1647 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1648 ins->opcode = OP_X86_LEA_MEMBASE;
1649 ins->inst_basereg = ins->sreg1;
1650 ins->inst_imm = -ins->inst_imm;
1651 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1652 ins->opcode = OP_X86_DEC_REG;
1654 case OP_COMPARE_IMM:
1655 case OP_ICOMPARE_IMM:
1656 /* OP_COMPARE_IMM (reg, 0)
1658 * OP_X86_TEST_NULL (reg)
1661 ins->opcode = OP_X86_TEST_NULL;
1663 case OP_X86_COMPARE_MEMBASE_IMM:
1665 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1666 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1668 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1669 * OP_COMPARE_IMM reg, imm
1671 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1673 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1674 ins->inst_basereg == last_ins->inst_destbasereg &&
1675 ins->inst_offset == last_ins->inst_offset) {
1676 ins->opcode = OP_COMPARE_IMM;
1677 ins->sreg1 = last_ins->sreg1;
1679 /* check if we can remove cmp reg,0 with test null */
1681 ins->opcode = OP_X86_TEST_NULL;
1685 case OP_X86_PUSH_MEMBASE:
1686 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1687 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1688 ins->inst_basereg == last_ins->inst_destbasereg &&
1689 ins->inst_offset == last_ins->inst_offset) {
1690 ins->opcode = OP_X86_PUSH;
1691 ins->sreg1 = last_ins->sreg1;
1696 mono_peephole_ins (bb, ins);
1701 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1705 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1706 switch (ins->opcode) {
1708 /* reg = 0 -> XOR (reg, reg) */
1709 /* XOR sets cflags on x86, so we cant do it always */
1710 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1713 ins->opcode = OP_IXOR;
1714 ins->sreg1 = ins->dreg;
1715 ins->sreg2 = ins->dreg;
1718 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1719 * since it takes 3 bytes instead of 7.
1721 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
1722 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1723 ins2->opcode = OP_STORE_MEMBASE_REG;
1724 ins2->sreg1 = ins->dreg;
1726 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1727 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1728 ins2->sreg1 = ins->dreg;
1730 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1731 /* Continue iteration */
1740 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1741 ins->opcode = OP_X86_INC_REG;
1745 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1746 ins->opcode = OP_X86_DEC_REG;
1750 mono_peephole_ins (bb, ins);
1755 * mono_arch_lowering_pass:
1757 * Converts complex opcodes into simpler ones so that each IR instruction
1758 * corresponds to one machine instruction.
1761 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1763 MonoInst *ins, *next;
1766 * FIXME: Need to add more instructions, but the current machine
1767 * description can't model some parts of the composite instructions like
1770 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
1771 switch (ins->opcode) {
1774 case OP_IDIV_UN_IMM:
1775 case OP_IREM_UN_IMM:
1777 * Keep the cases where we could generated optimized code, otherwise convert
1778 * to the non-imm variant.
1780 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
1782 mono_decompose_op_imm (cfg, bb, ins);
1789 bb->max_vreg = cfg->next_vreg;
1793 branch_cc_table [] = {
1794 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1795 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1796 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1799 /* Maps CMP_... constants to X86_CC_... constants */
1802 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
1803 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
1807 cc_signed_table [] = {
1808 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
1809 FALSE, FALSE, FALSE, FALSE
1812 static unsigned char*
1813 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
1815 #define XMM_TEMP_REG 0
1816 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
1817 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
1818 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
1819 /* optimize by assigning a local var for this use so we avoid
1820 * the stack manipulations */
1821 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1822 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1823 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
1824 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
1825 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1827 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
1829 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
1832 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
1833 x86_fnstcw_membase(code, X86_ESP, 0);
1834 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
1835 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
1836 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
1837 x86_fldcw_membase (code, X86_ESP, 2);
1839 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1840 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
1841 x86_pop_reg (code, dreg);
1842 /* FIXME: need the high register
1843 * x86_pop_reg (code, dreg_high);
1846 x86_push_reg (code, X86_EAX); // SP = SP - 4
1847 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
1848 x86_pop_reg (code, dreg);
1850 x86_fldcw_membase (code, X86_ESP, 0);
1851 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
1854 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
1856 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
1860 static unsigned char*
1861 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
1863 int sreg = tree->sreg1;
1864 int need_touch = FALSE;
1866 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
1875 * If requested stack size is larger than one page,
1876 * perform stack-touch operation
1879 * Generate stack probe code.
1880 * Under Windows, it is necessary to allocate one page at a time,
1881 * "touching" stack after each successful sub-allocation. This is
1882 * because of the way stack growth is implemented - there is a
1883 * guard page before the lowest stack page that is currently commited.
1884 * Stack normally grows sequentially so OS traps access to the
1885 * guard page and commits more pages when needed.
1887 x86_test_reg_imm (code, sreg, ~0xFFF);
1888 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1890 br[2] = code; /* loop */
1891 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
1892 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
1895 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
1896 * that follows only initializes the last part of the area.
1898 /* Same as the init code below with size==0x1000 */
1899 if (tree->flags & MONO_INST_INIT) {
1900 x86_push_reg (code, X86_EAX);
1901 x86_push_reg (code, X86_ECX);
1902 x86_push_reg (code, X86_EDI);
1903 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
1904 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
1905 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
1907 x86_prefix (code, X86_REP_PREFIX);
1909 x86_pop_reg (code, X86_EDI);
1910 x86_pop_reg (code, X86_ECX);
1911 x86_pop_reg (code, X86_EAX);
1914 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
1915 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
1916 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
1917 x86_patch (br[3], br[2]);
1918 x86_test_reg_reg (code, sreg, sreg);
1919 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1920 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
1922 br[1] = code; x86_jump8 (code, 0);
1924 x86_patch (br[0], code);
1925 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
1926 x86_patch (br[1], code);
1927 x86_patch (br[4], code);
1930 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
1932 if (tree->flags & MONO_INST_INIT) {
1934 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
1935 x86_push_reg (code, X86_EAX);
1938 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
1939 x86_push_reg (code, X86_ECX);
1942 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
1943 x86_push_reg (code, X86_EDI);
1947 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
1948 if (sreg != X86_ECX)
1949 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
1950 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
1952 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
1954 x86_prefix (code, X86_REP_PREFIX);
1957 if (tree->dreg != X86_EDI && sreg != X86_EDI)
1958 x86_pop_reg (code, X86_EDI);
1959 if (tree->dreg != X86_ECX && sreg != X86_ECX)
1960 x86_pop_reg (code, X86_ECX);
1961 if (tree->dreg != X86_EAX && sreg != X86_EAX)
1962 x86_pop_reg (code, X86_EAX);
1969 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
1971 /* Move return value to the target register */
1972 switch (ins->opcode) {
1975 case OP_CALL_MEMBASE:
1976 if (ins->dreg != X86_EAX)
1977 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
1987 * mono_x86_emit_tls_get:
1988 * @code: buffer to store code to
1989 * @dreg: hard register where to place the result
1990 * @tls_offset: offset info
1992 * mono_x86_emit_tls_get emits in @code the native code that puts in
1993 * the dreg register the item in the thread local storage identified
1996 * Returns: a pointer to the end of the stored code
1999 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2001 #ifdef PLATFORM_WIN32
2003 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2004 * Journal and/or a disassembly of the TlsGet () function.
2006 g_assert (tls_offset < 64);
2007 x86_prefix (code, X86_FS_PREFIX);
2008 x86_mov_reg_mem (code, dreg, 0x18, 4);
2009 /* Dunno what this does but TlsGetValue () contains it */
2010 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2011 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2013 if (optimize_for_xen) {
2014 x86_prefix (code, X86_GS_PREFIX);
2015 x86_mov_reg_mem (code, dreg, 0, 4);
2016 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2018 x86_prefix (code, X86_GS_PREFIX);
2019 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2026 * emit_load_volatile_arguments:
2028 * Load volatile arguments from the stack to the original input registers.
2029 * Required before a tail call.
2032 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2034 MonoMethod *method = cfg->method;
2035 MonoMethodSignature *sig;
2040 /* FIXME: Generate intermediate code instead */
2042 sig = mono_method_signature (method);
2044 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
2046 /* This is the opposite of the code in emit_prolog */
2048 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2049 ArgInfo *ainfo = cinfo->args + i;
2051 inst = cfg->args [i];
2053 if (sig->hasthis && (i == 0))
2054 arg_type = &mono_defaults.object_class->byval_arg;
2056 arg_type = sig->params [i - sig->hasthis];
2059 * On x86, the arguments are either in their original stack locations, or in
2062 if (inst->opcode == OP_REGVAR) {
2063 g_assert (ainfo->storage == ArgOnStack);
2065 x86_mov_membase_reg (code, X86_EBP, inst->inst_offset, inst->dreg, 4);
2072 #define REAL_PRINT_REG(text,reg) \
2073 mono_assert (reg >= 0); \
2074 x86_push_reg (code, X86_EAX); \
2075 x86_push_reg (code, X86_EDX); \
2076 x86_push_reg (code, X86_ECX); \
2077 x86_push_reg (code, reg); \
2078 x86_push_imm (code, reg); \
2079 x86_push_imm (code, text " %d %p\n"); \
2080 x86_mov_reg_imm (code, X86_EAX, printf); \
2081 x86_call_reg (code, X86_EAX); \
2082 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2083 x86_pop_reg (code, X86_ECX); \
2084 x86_pop_reg (code, X86_EDX); \
2085 x86_pop_reg (code, X86_EAX);
2087 /* benchmark and set based on cpu */
2088 #define LOOP_ALIGNMENT 8
2089 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2094 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2099 guint8 *code = cfg->native_code + cfg->code_len;
2102 if (cfg->opt & MONO_OPT_LOOP) {
2103 int pad, align = LOOP_ALIGNMENT;
2104 /* set alignment depending on cpu */
2105 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2107 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2108 x86_padding (code, pad);
2109 cfg->code_len += pad;
2110 bb->native_offset = cfg->code_len;
2114 if (cfg->verbose_level > 2)
2115 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2117 cpos = bb->max_offset;
2119 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2120 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2121 g_assert (!cfg->compile_aot);
2124 cov->data [bb->dfn].cil_code = bb->cil_code;
2125 /* this is not thread save, but good enough */
2126 x86_inc_mem (code, &cov->data [bb->dfn].count);
2129 offset = code - cfg->native_code;
2131 mono_debug_open_block (cfg, bb, offset);
2133 MONO_BB_FOR_EACH_INS (bb, ins) {
2134 offset = code - cfg->native_code;
2136 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2138 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2139 cfg->code_size *= 2;
2140 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2141 code = cfg->native_code + offset;
2142 mono_jit_stats.code_reallocs++;
2145 if (cfg->debug_info)
2146 mono_debug_record_line_number (cfg, ins, offset);
2148 switch (ins->opcode) {
2150 x86_mul_reg (code, ins->sreg2, TRUE);
2153 x86_mul_reg (code, ins->sreg2, FALSE);
2155 case OP_X86_SETEQ_MEMBASE:
2156 case OP_X86_SETNE_MEMBASE:
2157 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2158 ins->inst_basereg, ins->inst_offset, TRUE);
2160 case OP_STOREI1_MEMBASE_IMM:
2161 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2163 case OP_STOREI2_MEMBASE_IMM:
2164 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2166 case OP_STORE_MEMBASE_IMM:
2167 case OP_STOREI4_MEMBASE_IMM:
2168 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2170 case OP_STOREI1_MEMBASE_REG:
2171 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2173 case OP_STOREI2_MEMBASE_REG:
2174 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2176 case OP_STORE_MEMBASE_REG:
2177 case OP_STOREI4_MEMBASE_REG:
2178 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2180 case OP_STORE_MEM_IMM:
2181 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2184 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2188 /* These are created by the cprop pass so they use inst_imm as the source */
2189 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2192 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2195 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2197 case OP_LOAD_MEMBASE:
2198 case OP_LOADI4_MEMBASE:
2199 case OP_LOADU4_MEMBASE:
2200 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2202 case OP_LOADU1_MEMBASE:
2203 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2205 case OP_LOADI1_MEMBASE:
2206 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2208 case OP_LOADU2_MEMBASE:
2209 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2211 case OP_LOADI2_MEMBASE:
2212 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2214 case OP_ICONV_TO_I1:
2216 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2218 case OP_ICONV_TO_I2:
2220 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2222 case OP_ICONV_TO_U1:
2223 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2225 case OP_ICONV_TO_U2:
2226 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2230 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2232 case OP_COMPARE_IMM:
2233 case OP_ICOMPARE_IMM:
2234 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2236 case OP_X86_COMPARE_MEMBASE_REG:
2237 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2239 case OP_X86_COMPARE_MEMBASE_IMM:
2240 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2242 case OP_X86_COMPARE_MEMBASE8_IMM:
2243 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2245 case OP_X86_COMPARE_REG_MEMBASE:
2246 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2248 case OP_X86_COMPARE_MEM_IMM:
2249 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2251 case OP_X86_TEST_NULL:
2252 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2254 case OP_X86_ADD_MEMBASE_IMM:
2255 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2257 case OP_X86_ADD_REG_MEMBASE:
2258 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2260 case OP_X86_SUB_MEMBASE_IMM:
2261 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2263 case OP_X86_SUB_REG_MEMBASE:
2264 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2266 case OP_X86_AND_MEMBASE_IMM:
2267 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2269 case OP_X86_OR_MEMBASE_IMM:
2270 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2272 case OP_X86_XOR_MEMBASE_IMM:
2273 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2275 case OP_X86_ADD_MEMBASE_REG:
2276 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2278 case OP_X86_SUB_MEMBASE_REG:
2279 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2281 case OP_X86_AND_MEMBASE_REG:
2282 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2284 case OP_X86_OR_MEMBASE_REG:
2285 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2287 case OP_X86_XOR_MEMBASE_REG:
2288 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2290 case OP_X86_INC_MEMBASE:
2291 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2293 case OP_X86_INC_REG:
2294 x86_inc_reg (code, ins->dreg);
2296 case OP_X86_DEC_MEMBASE:
2297 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2299 case OP_X86_DEC_REG:
2300 x86_dec_reg (code, ins->dreg);
2302 case OP_X86_MUL_REG_MEMBASE:
2303 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2305 case OP_X86_AND_REG_MEMBASE:
2306 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2308 case OP_X86_OR_REG_MEMBASE:
2309 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2311 case OP_X86_XOR_REG_MEMBASE:
2312 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2315 x86_breakpoint (code);
2317 case OP_RELAXED_NOP:
2318 x86_prefix (code, X86_REP_PREFIX);
2326 case OP_DUMMY_STORE:
2327 case OP_NOT_REACHED:
2333 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2337 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2342 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2346 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2351 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2355 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2360 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2364 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2367 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2371 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2376 * The code is the same for div/rem, the allocator will allocate dreg
2377 * to RAX/RDX as appropriate.
2379 if (ins->sreg2 == X86_EDX) {
2380 /* cdq clobbers this */
2381 x86_push_reg (code, ins->sreg2);
2383 x86_div_membase (code, X86_ESP, 0, TRUE);
2384 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2387 x86_div_reg (code, ins->sreg2, TRUE);
2392 if (ins->sreg2 == X86_EDX) {
2393 x86_push_reg (code, ins->sreg2);
2394 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2395 x86_div_membase (code, X86_ESP, 0, FALSE);
2396 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2398 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2399 x86_div_reg (code, ins->sreg2, FALSE);
2403 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2405 x86_div_reg (code, ins->sreg2, TRUE);
2408 int power = mono_is_power_of_two (ins->inst_imm);
2410 g_assert (ins->sreg1 == X86_EAX);
2411 g_assert (ins->dreg == X86_EAX);
2412 g_assert (power >= 0);
2415 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2417 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2419 * If the divident is >= 0, this does not nothing. If it is positive, it
2420 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2422 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2423 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2425 /* Based on gcc code */
2427 /* Add compensation for negative dividents */
2429 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2430 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2431 /* Compute remainder */
2432 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2433 /* Remove compensation */
2434 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2439 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2443 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2446 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2450 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2453 g_assert (ins->sreg2 == X86_ECX);
2454 x86_shift_reg (code, X86_SHL, ins->dreg);
2457 g_assert (ins->sreg2 == X86_ECX);
2458 x86_shift_reg (code, X86_SAR, ins->dreg);
2462 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2465 case OP_ISHR_UN_IMM:
2466 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2469 g_assert (ins->sreg2 == X86_ECX);
2470 x86_shift_reg (code, X86_SHR, ins->dreg);
2474 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2477 guint8 *jump_to_end;
2479 /* handle shifts below 32 bits */
2480 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2481 x86_shift_reg (code, X86_SHL, ins->sreg1);
2483 x86_test_reg_imm (code, X86_ECX, 32);
2484 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2486 /* handle shift over 32 bit */
2487 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2488 x86_clear_reg (code, ins->sreg1);
2490 x86_patch (jump_to_end, code);
2494 guint8 *jump_to_end;
2496 /* handle shifts below 32 bits */
2497 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2498 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2500 x86_test_reg_imm (code, X86_ECX, 32);
2501 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2503 /* handle shifts over 31 bits */
2504 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2505 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2507 x86_patch (jump_to_end, code);
2511 guint8 *jump_to_end;
2513 /* handle shifts below 32 bits */
2514 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2515 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2517 x86_test_reg_imm (code, X86_ECX, 32);
2518 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2520 /* handle shifts over 31 bits */
2521 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2522 x86_clear_reg (code, ins->backend.reg3);
2524 x86_patch (jump_to_end, code);
2528 if (ins->inst_imm >= 32) {
2529 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2530 x86_clear_reg (code, ins->sreg1);
2531 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2533 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2534 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2538 if (ins->inst_imm >= 32) {
2539 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2540 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2541 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2543 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2544 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2547 case OP_LSHR_UN_IMM:
2548 if (ins->inst_imm >= 32) {
2549 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2550 x86_clear_reg (code, ins->backend.reg3);
2551 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2553 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2554 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2558 x86_not_reg (code, ins->sreg1);
2561 x86_neg_reg (code, ins->sreg1);
2565 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2569 switch (ins->inst_imm) {
2573 if (ins->dreg != ins->sreg1)
2574 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2575 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2578 /* LEA r1, [r2 + r2*2] */
2579 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2582 /* LEA r1, [r2 + r2*4] */
2583 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2586 /* LEA r1, [r2 + r2*2] */
2588 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2589 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2592 /* LEA r1, [r2 + r2*8] */
2593 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2596 /* LEA r1, [r2 + r2*4] */
2598 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2599 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2602 /* LEA r1, [r2 + r2*2] */
2604 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2605 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2608 /* LEA r1, [r2 + r2*4] */
2609 /* LEA r1, [r1 + r1*4] */
2610 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2611 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2614 /* LEA r1, [r2 + r2*4] */
2616 /* LEA r1, [r1 + r1*4] */
2617 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2618 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2619 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2622 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2627 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2628 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2630 case OP_IMUL_OVF_UN: {
2631 /* the mul operation and the exception check should most likely be split */
2632 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2633 /*g_assert (ins->sreg2 == X86_EAX);
2634 g_assert (ins->dreg == X86_EAX);*/
2635 if (ins->sreg2 == X86_EAX) {
2636 non_eax_reg = ins->sreg1;
2637 } else if (ins->sreg1 == X86_EAX) {
2638 non_eax_reg = ins->sreg2;
2640 /* no need to save since we're going to store to it anyway */
2641 if (ins->dreg != X86_EAX) {
2643 x86_push_reg (code, X86_EAX);
2645 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
2646 non_eax_reg = ins->sreg2;
2648 if (ins->dreg == X86_EDX) {
2651 x86_push_reg (code, X86_EAX);
2653 } else if (ins->dreg != X86_EAX) {
2655 x86_push_reg (code, X86_EDX);
2657 x86_mul_reg (code, non_eax_reg, FALSE);
2658 /* save before the check since pop and mov don't change the flags */
2659 if (ins->dreg != X86_EAX)
2660 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2662 x86_pop_reg (code, X86_EDX);
2664 x86_pop_reg (code, X86_EAX);
2665 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2669 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
2672 g_assert_not_reached ();
2673 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2674 x86_mov_reg_imm (code, ins->dreg, 0);
2677 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2678 x86_mov_reg_imm (code, ins->dreg, 0);
2680 case OP_LOAD_GOTADDR:
2681 x86_call_imm (code, 0);
2683 * The patch needs to point to the pop, since the GOT offset needs
2684 * to be added to that address.
2686 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
2687 x86_pop_reg (code, ins->dreg);
2688 x86_alu_reg_imm (code, X86_ADD, ins->dreg, 0xf0f0f0f0);
2691 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2692 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
2694 case OP_X86_PUSH_GOT_ENTRY:
2695 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2696 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
2699 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2703 * Note: this 'frame destruction' logic is useful for tail calls, too.
2704 * Keep in sync with the code in emit_epilog.
2708 /* FIXME: no tracing support... */
2709 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2710 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2711 /* reset offset to make max_len work */
2712 offset = code - cfg->native_code;
2714 g_assert (!cfg->method->save_lmf);
2716 code = emit_load_volatile_arguments (cfg, code);
2718 if (cfg->used_int_regs & (1 << X86_EBX))
2720 if (cfg->used_int_regs & (1 << X86_EDI))
2722 if (cfg->used_int_regs & (1 << X86_ESI))
2725 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
2727 if (cfg->used_int_regs & (1 << X86_ESI))
2728 x86_pop_reg (code, X86_ESI);
2729 if (cfg->used_int_regs & (1 << X86_EDI))
2730 x86_pop_reg (code, X86_EDI);
2731 if (cfg->used_int_regs & (1 << X86_EBX))
2732 x86_pop_reg (code, X86_EBX);
2734 /* restore ESP/EBP */
2736 offset = code - cfg->native_code;
2737 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2738 x86_jump32 (code, 0);
2740 cfg->disable_aot = TRUE;
2744 /* ensure ins->sreg1 is not NULL
2745 * note that cmp DWORD PTR [eax], eax is one byte shorter than
2746 * cmp DWORD PTR [eax], 0
2748 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
2751 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
2752 x86_push_reg (code, hreg);
2753 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
2754 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
2755 x86_pop_reg (code, hreg);
2764 call = (MonoCallInst*)ins;
2765 if (ins->flags & MONO_INST_HAS_METHOD)
2766 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2768 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2769 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
2770 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
2771 * bytes to pop, we want to use pops. GCC does this (note it won't happen
2772 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
2773 * smart enough to do that optimization yet
2775 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
2776 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
2777 * (most likely from locality benefits). People with other processors should
2778 * check on theirs to see what happens.
2780 if (call->stack_usage == 4) {
2781 /* we want to use registers that won't get used soon, so use
2782 * ecx, as eax will get allocated first. edx is used by long calls,
2783 * so we can't use that.
2786 x86_pop_reg (code, X86_ECX);
2788 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2791 code = emit_move_return_value (cfg, ins, code);
2797 case OP_VOIDCALL_REG:
2799 call = (MonoCallInst*)ins;
2800 x86_call_reg (code, ins->sreg1);
2801 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
2802 if (call->stack_usage == 4)
2803 x86_pop_reg (code, X86_ECX);
2805 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2807 code = emit_move_return_value (cfg, ins, code);
2809 case OP_FCALL_MEMBASE:
2810 case OP_LCALL_MEMBASE:
2811 case OP_VCALL_MEMBASE:
2812 case OP_VCALL2_MEMBASE:
2813 case OP_VOIDCALL_MEMBASE:
2814 case OP_CALL_MEMBASE:
2815 call = (MonoCallInst*)ins;
2818 * Emit a few nops to simplify get_vcall_slot ().
2824 x86_call_membase (code, ins->sreg1, ins->inst_offset);
2825 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
2826 if (call->stack_usage == 4)
2827 x86_pop_reg (code, X86_ECX);
2829 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2831 code = emit_move_return_value (cfg, ins, code);
2834 x86_push_reg (code, ins->sreg1);
2836 case OP_X86_PUSH_IMM:
2837 x86_push_imm (code, ins->inst_imm);
2839 case OP_X86_PUSH_MEMBASE:
2840 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
2842 case OP_X86_PUSH_OBJ:
2843 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
2844 x86_push_reg (code, X86_EDI);
2845 x86_push_reg (code, X86_ESI);
2846 x86_push_reg (code, X86_ECX);
2847 if (ins->inst_offset)
2848 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
2850 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
2851 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2852 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
2854 x86_prefix (code, X86_REP_PREFIX);
2856 x86_pop_reg (code, X86_ECX);
2857 x86_pop_reg (code, X86_ESI);
2858 x86_pop_reg (code, X86_EDI);
2861 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
2863 case OP_X86_LEA_MEMBASE:
2864 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
2867 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
2870 /* keep alignment */
2871 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
2872 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
2873 code = mono_emit_stack_alloc (code, ins);
2874 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2876 case OP_LOCALLOC_IMM: {
2877 guint32 size = ins->inst_imm;
2878 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
2880 if (ins->flags & MONO_INST_INIT) {
2881 /* FIXME: Optimize this */
2882 x86_mov_reg_imm (code, ins->dreg, size);
2883 ins->sreg1 = ins->dreg;
2885 code = mono_emit_stack_alloc (code, ins);
2886 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2888 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
2889 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2894 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
2895 x86_push_reg (code, ins->sreg1);
2896 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
2897 (gpointer)"mono_arch_throw_exception");
2901 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
2902 x86_push_reg (code, ins->sreg1);
2903 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
2904 (gpointer)"mono_arch_rethrow_exception");
2907 case OP_CALL_HANDLER:
2908 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
2909 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2910 x86_call_imm (code, 0);
2911 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
2913 case OP_START_HANDLER: {
2914 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
2915 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
2918 case OP_ENDFINALLY: {
2919 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
2920 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
2924 case OP_ENDFILTER: {
2925 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
2926 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
2927 /* The local allocator will put the result into EAX */
2933 ins->inst_c0 = code - cfg->native_code;
2936 if (ins->inst_target_bb->native_offset) {
2937 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
2939 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2940 if ((cfg->opt & MONO_OPT_BRANCH) &&
2941 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
2942 x86_jump8 (code, 0);
2944 x86_jump32 (code, 0);
2948 x86_jump_reg (code, ins->sreg1);
2961 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
2962 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2964 case OP_COND_EXC_EQ:
2965 case OP_COND_EXC_NE_UN:
2966 case OP_COND_EXC_LT:
2967 case OP_COND_EXC_LT_UN:
2968 case OP_COND_EXC_GT:
2969 case OP_COND_EXC_GT_UN:
2970 case OP_COND_EXC_GE:
2971 case OP_COND_EXC_GE_UN:
2972 case OP_COND_EXC_LE:
2973 case OP_COND_EXC_LE_UN:
2974 case OP_COND_EXC_IEQ:
2975 case OP_COND_EXC_INE_UN:
2976 case OP_COND_EXC_ILT:
2977 case OP_COND_EXC_ILT_UN:
2978 case OP_COND_EXC_IGT:
2979 case OP_COND_EXC_IGT_UN:
2980 case OP_COND_EXC_IGE:
2981 case OP_COND_EXC_IGE_UN:
2982 case OP_COND_EXC_ILE:
2983 case OP_COND_EXC_ILE_UN:
2984 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
2986 case OP_COND_EXC_OV:
2987 case OP_COND_EXC_NO:
2989 case OP_COND_EXC_NC:
2990 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
2992 case OP_COND_EXC_IOV:
2993 case OP_COND_EXC_INO:
2994 case OP_COND_EXC_IC:
2995 case OP_COND_EXC_INC:
2996 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3008 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3016 case OP_CMOV_INE_UN:
3017 case OP_CMOV_IGE_UN:
3018 case OP_CMOV_IGT_UN:
3019 case OP_CMOV_ILE_UN:
3020 case OP_CMOV_ILT_UN:
3021 g_assert (ins->dreg == ins->sreg1);
3022 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3025 /* floating point opcodes */
3027 double d = *(double *)ins->inst_p0;
3029 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3031 } else if (d == 1.0) {
3034 if (cfg->compile_aot) {
3035 guint32 *val = (guint32*)&d;
3036 x86_push_imm (code, val [1]);
3037 x86_push_imm (code, val [0]);
3038 x86_fld_membase (code, X86_ESP, 0, TRUE);
3039 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3042 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3043 x86_fld (code, NULL, TRUE);
3049 float f = *(float *)ins->inst_p0;
3051 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3053 } else if (f == 1.0) {
3056 if (cfg->compile_aot) {
3057 guint32 val = *(guint32*)&f;
3058 x86_push_imm (code, val);
3059 x86_fld_membase (code, X86_ESP, 0, FALSE);
3060 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3063 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3064 x86_fld (code, NULL, FALSE);
3069 case OP_STORER8_MEMBASE_REG:
3070 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3072 case OP_LOADR8_MEMBASE:
3073 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3075 case OP_STORER4_MEMBASE_REG:
3076 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3078 case OP_LOADR4_MEMBASE:
3079 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3081 case OP_ICONV_TO_R4:
3082 x86_push_reg (code, ins->sreg1);
3083 x86_fild_membase (code, X86_ESP, 0, FALSE);
3084 /* Change precision */
3085 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3086 x86_fld_membase (code, X86_ESP, 0, FALSE);
3087 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3089 case OP_ICONV_TO_R8:
3090 x86_push_reg (code, ins->sreg1);
3091 x86_fild_membase (code, X86_ESP, 0, FALSE);
3092 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3094 case OP_ICONV_TO_R_UN:
3095 x86_push_imm (code, 0);
3096 x86_push_reg (code, ins->sreg1);
3097 x86_fild_membase (code, X86_ESP, 0, TRUE);
3098 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3100 case OP_X86_FP_LOAD_I8:
3101 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3103 case OP_X86_FP_LOAD_I4:
3104 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3106 case OP_FCONV_TO_R4:
3107 /* Change precision */
3108 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3109 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3110 x86_fld_membase (code, X86_ESP, 0, FALSE);
3111 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3113 case OP_FCONV_TO_I1:
3114 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3116 case OP_FCONV_TO_U1:
3117 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3119 case OP_FCONV_TO_I2:
3120 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3122 case OP_FCONV_TO_U2:
3123 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3125 case OP_FCONV_TO_I4:
3127 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3129 case OP_FCONV_TO_I8:
3130 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3131 x86_fnstcw_membase(code, X86_ESP, 0);
3132 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3133 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3134 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3135 x86_fldcw_membase (code, X86_ESP, 2);
3136 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3137 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3138 x86_pop_reg (code, ins->dreg);
3139 x86_pop_reg (code, ins->backend.reg3);
3140 x86_fldcw_membase (code, X86_ESP, 0);
3141 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3143 case OP_LCONV_TO_R8_2:
3144 x86_push_reg (code, ins->sreg2);
3145 x86_push_reg (code, ins->sreg1);
3146 x86_fild_membase (code, X86_ESP, 0, TRUE);
3147 /* Change precision */
3148 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3149 x86_fld_membase (code, X86_ESP, 0, TRUE);
3150 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3152 case OP_LCONV_TO_R4_2:
3153 x86_push_reg (code, ins->sreg2);
3154 x86_push_reg (code, ins->sreg1);
3155 x86_fild_membase (code, X86_ESP, 0, TRUE);
3156 /* Change precision */
3157 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3158 x86_fld_membase (code, X86_ESP, 0, FALSE);
3159 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3161 case OP_LCONV_TO_R_UN_2: {
3162 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3165 /* load 64bit integer to FP stack */
3166 x86_push_reg (code, ins->sreg2);
3167 x86_push_reg (code, ins->sreg1);
3168 x86_fild_membase (code, X86_ESP, 0, TRUE);
3170 /* test if lreg is negative */
3171 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3172 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3174 /* add correction constant mn */
3175 x86_fld80_mem (code, mn);
3176 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3178 x86_patch (br, code);
3180 /* Change precision */
3181 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3182 x86_fld_membase (code, X86_ESP, 0, TRUE);
3184 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3188 case OP_LCONV_TO_OVF_I:
3189 case OP_LCONV_TO_OVF_I4_2: {
3190 guint8 *br [3], *label [1];
3194 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3196 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3198 /* If the low word top bit is set, see if we are negative */
3199 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3200 /* We are not negative (no top bit set, check for our top word to be zero */
3201 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3202 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3205 /* throw exception */
3206 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3208 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3209 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3210 x86_jump8 (code, 0);
3212 x86_jump32 (code, 0);
3214 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3215 x86_jump32 (code, 0);
3219 x86_patch (br [0], code);
3220 /* our top bit is set, check that top word is 0xfffffff */
3221 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3223 x86_patch (br [1], code);
3224 /* nope, emit exception */
3225 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3226 x86_patch (br [2], label [0]);
3228 if (ins->dreg != ins->sreg1)
3229 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3233 /* Not needed on the fp stack */
3236 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3239 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3242 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3245 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3253 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3258 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3265 * it really doesn't make sense to inline all this code,
3266 * it's here just to show that things may not be as simple
3269 guchar *check_pos, *end_tan, *pop_jump;
3270 x86_push_reg (code, X86_EAX);
3273 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3275 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3276 x86_fstp (code, 0); /* pop the 1.0 */
3278 x86_jump8 (code, 0);
3280 x86_fp_op (code, X86_FADD, 0);
3284 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3286 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3289 x86_patch (pop_jump, code);
3290 x86_fstp (code, 0); /* pop the 1.0 */
3291 x86_patch (check_pos, code);
3292 x86_patch (end_tan, code);
3294 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3295 x86_pop_reg (code, X86_EAX);
3302 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3311 g_assert (cfg->opt & MONO_OPT_CMOV);
3312 g_assert (ins->dreg == ins->sreg1);
3313 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3314 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3317 g_assert (cfg->opt & MONO_OPT_CMOV);
3318 g_assert (ins->dreg == ins->sreg1);
3319 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3320 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3323 g_assert (cfg->opt & MONO_OPT_CMOV);
3324 g_assert (ins->dreg == ins->sreg1);
3325 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3326 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3329 g_assert (cfg->opt & MONO_OPT_CMOV);
3330 g_assert (ins->dreg == ins->sreg1);
3331 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3332 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3338 x86_fxch (code, ins->inst_imm);
3343 x86_push_reg (code, X86_EAX);
3344 /* we need to exchange ST(0) with ST(1) */
3347 /* this requires a loop, because fprem somtimes
3348 * returns a partial remainder */
3350 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3351 /* x86_fprem1 (code); */
3354 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3356 x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3361 x86_pop_reg (code, X86_EAX);
3365 if (cfg->opt & MONO_OPT_FCMOV) {
3366 x86_fcomip (code, 1);
3370 /* this overwrites EAX */
3371 EMIT_FPCOMPARE(code);
3372 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3375 if (cfg->opt & MONO_OPT_FCMOV) {
3376 /* zeroing the register at the start results in
3377 * shorter and faster code (we can also remove the widening op)
3379 guchar *unordered_check;
3380 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3381 x86_fcomip (code, 1);
3383 unordered_check = code;
3384 x86_branch8 (code, X86_CC_P, 0, FALSE);
3385 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3386 x86_patch (unordered_check, code);
3389 if (ins->dreg != X86_EAX)
3390 x86_push_reg (code, X86_EAX);
3392 EMIT_FPCOMPARE(code);
3393 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3394 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3395 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3396 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3398 if (ins->dreg != X86_EAX)
3399 x86_pop_reg (code, X86_EAX);
3403 if (cfg->opt & MONO_OPT_FCMOV) {
3404 /* zeroing the register at the start results in
3405 * shorter and faster code (we can also remove the widening op)
3407 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3408 x86_fcomip (code, 1);
3410 if (ins->opcode == OP_FCLT_UN) {
3411 guchar *unordered_check = code;
3412 guchar *jump_to_end;
3413 x86_branch8 (code, X86_CC_P, 0, FALSE);
3414 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3416 x86_jump8 (code, 0);
3417 x86_patch (unordered_check, code);
3418 x86_inc_reg (code, ins->dreg);
3419 x86_patch (jump_to_end, code);
3421 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3425 if (ins->dreg != X86_EAX)
3426 x86_push_reg (code, X86_EAX);
3428 EMIT_FPCOMPARE(code);
3429 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3430 if (ins->opcode == OP_FCLT_UN) {
3431 guchar *is_not_zero_check, *end_jump;
3432 is_not_zero_check = code;
3433 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3435 x86_jump8 (code, 0);
3436 x86_patch (is_not_zero_check, code);
3437 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3439 x86_patch (end_jump, code);
3441 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3442 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3444 if (ins->dreg != X86_EAX)
3445 x86_pop_reg (code, X86_EAX);
3449 if (cfg->opt & MONO_OPT_FCMOV) {
3450 /* zeroing the register at the start results in
3451 * shorter and faster code (we can also remove the widening op)
3453 guchar *unordered_check;
3454 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3455 x86_fcomip (code, 1);
3457 if (ins->opcode == OP_FCGT) {
3458 unordered_check = code;
3459 x86_branch8 (code, X86_CC_P, 0, FALSE);
3460 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3461 x86_patch (unordered_check, code);
3463 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3467 if (ins->dreg != X86_EAX)
3468 x86_push_reg (code, X86_EAX);
3470 EMIT_FPCOMPARE(code);
3471 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3472 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3473 if (ins->opcode == OP_FCGT_UN) {
3474 guchar *is_not_zero_check, *end_jump;
3475 is_not_zero_check = code;
3476 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3478 x86_jump8 (code, 0);
3479 x86_patch (is_not_zero_check, code);
3480 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3482 x86_patch (end_jump, code);
3484 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3485 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3487 if (ins->dreg != X86_EAX)
3488 x86_pop_reg (code, X86_EAX);
3491 if (cfg->opt & MONO_OPT_FCMOV) {
3492 guchar *jump = code;
3493 x86_branch8 (code, X86_CC_P, 0, TRUE);
3494 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3495 x86_patch (jump, code);
3498 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3499 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3502 /* Branch if C013 != 100 */
3503 if (cfg->opt & MONO_OPT_FCMOV) {
3504 /* branch if !ZF or (PF|CF) */
3505 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3506 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3507 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3510 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3511 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3514 if (cfg->opt & MONO_OPT_FCMOV) {
3515 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3518 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3521 if (cfg->opt & MONO_OPT_FCMOV) {
3522 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3523 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3526 if (ins->opcode == OP_FBLT_UN) {
3527 guchar *is_not_zero_check, *end_jump;
3528 is_not_zero_check = code;
3529 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3531 x86_jump8 (code, 0);
3532 x86_patch (is_not_zero_check, code);
3533 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3535 x86_patch (end_jump, code);
3537 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3541 if (cfg->opt & MONO_OPT_FCMOV) {
3542 if (ins->opcode == OP_FBGT) {
3545 /* skip branch if C1=1 */
3547 x86_branch8 (code, X86_CC_P, 0, FALSE);
3548 /* branch if (C0 | C3) = 1 */
3549 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3550 x86_patch (br1, code);
3552 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3556 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3557 if (ins->opcode == OP_FBGT_UN) {
3558 guchar *is_not_zero_check, *end_jump;
3559 is_not_zero_check = code;
3560 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3562 x86_jump8 (code, 0);
3563 x86_patch (is_not_zero_check, code);
3564 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3566 x86_patch (end_jump, code);
3568 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3571 /* Branch if C013 == 100 or 001 */
3572 if (cfg->opt & MONO_OPT_FCMOV) {
3575 /* skip branch if C1=1 */
3577 x86_branch8 (code, X86_CC_P, 0, FALSE);
3578 /* branch if (C0 | C3) = 1 */
3579 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3580 x86_patch (br1, code);
3583 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3584 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3585 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3586 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3589 /* Branch if C013 == 000 */
3590 if (cfg->opt & MONO_OPT_FCMOV) {
3591 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3594 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3597 /* Branch if C013=000 or 100 */
3598 if (cfg->opt & MONO_OPT_FCMOV) {
3601 /* skip branch if C1=1 */
3603 x86_branch8 (code, X86_CC_P, 0, FALSE);
3604 /* branch if C0=0 */
3605 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3606 x86_patch (br1, code);
3609 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
3610 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
3611 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3614 /* Branch if C013 != 001 */
3615 if (cfg->opt & MONO_OPT_FCMOV) {
3616 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3617 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3620 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3621 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3625 x86_push_reg (code, X86_EAX);
3628 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
3629 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3630 x86_pop_reg (code, X86_EAX);
3632 /* Have to clean up the fp stack before throwing the exception */
3634 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3637 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3639 x86_patch (br1, code);
3643 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
3646 case OP_MEMORY_BARRIER: {
3647 /* Not needed on x86 */
3650 case OP_ATOMIC_ADD_I4: {
3651 int dreg = ins->dreg;
3653 if (dreg == ins->inst_basereg) {
3654 x86_push_reg (code, ins->sreg2);
3658 if (dreg != ins->sreg2)
3659 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
3661 x86_prefix (code, X86_LOCK_PREFIX);
3662 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
3664 if (dreg != ins->dreg) {
3665 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
3666 x86_pop_reg (code, dreg);
3671 case OP_ATOMIC_ADD_NEW_I4: {
3672 int dreg = ins->dreg;
3674 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
3675 if (ins->sreg2 == dreg) {
3676 if (dreg == X86_EBX) {
3678 if (ins->inst_basereg == X86_EDI)
3682 if (ins->inst_basereg == X86_EBX)
3685 } else if (ins->inst_basereg == dreg) {
3686 if (dreg == X86_EBX) {
3688 if (ins->sreg2 == X86_EDI)
3692 if (ins->sreg2 == X86_EBX)
3697 if (dreg != ins->dreg) {
3698 x86_push_reg (code, dreg);
3701 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
3702 x86_prefix (code, X86_LOCK_PREFIX);
3703 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
3704 /* dreg contains the old value, add with sreg2 value */
3705 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
3707 if (ins->dreg != dreg) {
3708 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
3709 x86_pop_reg (code, dreg);
3714 case OP_ATOMIC_EXCHANGE_I4: {
3716 int sreg2 = ins->sreg2;
3717 int breg = ins->inst_basereg;
3719 /* cmpxchg uses eax as comperand, need to make sure we can use it
3720 * hack to overcome limits in x86 reg allocator
3721 * (req: dreg == eax and sreg2 != eax and breg != eax)
3723 g_assert (ins->dreg == X86_EAX);
3725 /* We need the EAX reg for the cmpxchg */
3726 if (ins->sreg2 == X86_EAX) {
3727 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
3728 x86_push_reg (code, sreg2);
3729 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
3732 if (breg == X86_EAX) {
3733 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
3734 x86_push_reg (code, breg);
3735 x86_mov_reg_reg (code, breg, X86_EAX, 4);
3738 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
3740 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
3741 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
3742 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
3743 x86_patch (br [1], br [0]);
3745 if (breg != ins->inst_basereg)
3746 x86_pop_reg (code, breg);
3748 if (ins->sreg2 != sreg2)
3749 x86_pop_reg (code, sreg2);
3753 case OP_ATOMIC_CAS_I4: {
3754 g_assert (ins->sreg3 == X86_EAX);
3755 g_assert (ins->sreg1 != X86_EAX);
3756 g_assert (ins->sreg1 != ins->sreg2);
3758 x86_prefix (code, X86_LOCK_PREFIX);
3759 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
3761 if (ins->dreg != X86_EAX)
3762 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3765 #ifdef MONO_ARCH_SIMD_INTRINSICS
3767 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
3770 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
3773 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
3776 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
3779 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
3782 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
3785 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
3786 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
3789 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
3792 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
3795 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
3798 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
3801 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
3804 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
3807 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
3810 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
3813 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
3816 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
3819 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
3822 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
3825 case OP_PSHUFLEW_HIGH:
3826 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
3827 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
3829 case OP_PSHUFLEW_LOW:
3830 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
3831 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
3834 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
3835 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
3839 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
3842 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
3845 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
3848 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
3851 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
3854 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
3857 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
3858 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
3861 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
3864 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
3867 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
3870 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
3873 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
3876 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
3879 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
3882 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
3885 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
3888 case OP_EXTRACT_MASK:
3889 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
3893 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
3896 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
3899 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
3903 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
3906 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
3909 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
3912 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
3916 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
3919 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
3922 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
3925 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
3929 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
3932 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
3935 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
3939 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
3942 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
3945 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
3949 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
3952 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
3956 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
3959 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
3962 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
3966 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
3969 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
3972 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
3976 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
3979 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
3982 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
3985 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
3989 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
3992 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
3995 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
3998 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4001 case OP_PSUM_ABS_DIFF:
4002 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4005 case OP_UNPACK_LOWB:
4006 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4008 case OP_UNPACK_LOWW:
4009 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4011 case OP_UNPACK_LOWD:
4012 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4014 case OP_UNPACK_LOWQ:
4015 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4017 case OP_UNPACK_LOWPS:
4018 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4020 case OP_UNPACK_LOWPD:
4021 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4024 case OP_UNPACK_HIGHB:
4025 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4027 case OP_UNPACK_HIGHW:
4028 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4030 case OP_UNPACK_HIGHD:
4031 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4033 case OP_UNPACK_HIGHQ:
4034 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4036 case OP_UNPACK_HIGHPS:
4037 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4039 case OP_UNPACK_HIGHPD:
4040 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4044 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4047 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4050 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4053 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4056 case OP_PADDB_SAT_UN:
4057 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4059 case OP_PSUBB_SAT_UN:
4060 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4062 case OP_PADDW_SAT_UN:
4063 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4065 case OP_PSUBW_SAT_UN:
4066 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4070 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4073 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4076 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4079 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4083 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4086 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4089 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4091 case OP_PMULW_HIGH_UN:
4092 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4095 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4099 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4102 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4106 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4109 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4113 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4116 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4120 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4123 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4127 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4130 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4134 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4137 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4141 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4144 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4148 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4151 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4155 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4158 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4162 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4164 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4165 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4169 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4171 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4172 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4176 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4178 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4179 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4183 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4185 case OP_EXTRACTX_U2:
4186 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4188 case OP_INSERTX_U1_SLOW:
4189 /*sreg1 is the extracted ireg (scratch)
4190 /sreg2 is the to be inserted ireg (scratch)
4191 /dreg is the xreg to receive the value*/
4193 /*clear the bits from the extracted word*/
4194 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4195 /*shift the value to insert if needed*/
4196 if (ins->inst_c0 & 1)
4197 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4198 /*join them together*/
4199 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4200 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4202 case OP_INSERTX_I4_SLOW:
4203 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4204 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4205 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4208 case OP_INSERTX_R4_SLOW:
4209 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4210 /*TODO if inst_c0 == 0 use movss*/
4211 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4212 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4214 case OP_INSERTX_R8_SLOW:
4215 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4217 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4219 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVSD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4222 case OP_STOREX_MEMBASE_REG:
4223 case OP_STOREX_MEMBASE:
4224 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4226 case OP_LOADX_MEMBASE:
4227 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4229 case OP_LOADX_ALIGNED_MEMBASE:
4230 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4232 case OP_STOREX_ALIGNED_MEMBASE_REG:
4233 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4235 case OP_STOREX_NTA_MEMBASE_REG:
4236 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4238 case OP_PREFETCH_MEMBASE:
4239 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4243 /*FIXME the peephole pass should have killed this*/
4244 if (ins->dreg != ins->sreg1)
4245 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4248 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4250 case OP_ICONV_TO_R8_RAW:
4251 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4252 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4255 case OP_FCONV_TO_R8_X:
4256 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4257 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4260 case OP_XCONV_R8_TO_I4:
4261 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4262 switch (ins->backend.source_opcode) {
4263 case OP_FCONV_TO_I1:
4264 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4266 case OP_FCONV_TO_U1:
4267 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4269 case OP_FCONV_TO_I2:
4270 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4272 case OP_FCONV_TO_U2:
4273 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4279 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4280 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4281 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4282 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4283 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4284 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4287 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4288 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4289 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4292 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4293 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4296 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4297 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4298 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4301 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4302 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4303 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4306 case OP_LIVERANGE_START: {
4307 if (cfg->verbose_level > 1)
4308 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4309 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4312 case OP_LIVERANGE_END: {
4313 if (cfg->verbose_level > 1)
4314 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4315 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4319 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4320 g_assert_not_reached ();
4323 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4324 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4325 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4326 g_assert_not_reached ();
4332 cfg->code_len = code - cfg->native_code;
4335 #endif /* DISABLE_JIT */
4338 mono_arch_register_lowlevel_calls (void)
4343 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4345 MonoJumpInfo *patch_info;
4346 gboolean compile_aot = !run_cctors;
4348 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4349 unsigned char *ip = patch_info->ip.i + code;
4350 const unsigned char *target;
4352 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4355 switch (patch_info->type) {
4356 case MONO_PATCH_INFO_BB:
4357 case MONO_PATCH_INFO_LABEL:
4360 /* No need to patch these */
4365 switch (patch_info->type) {
4366 case MONO_PATCH_INFO_IP:
4367 *((gconstpointer *)(ip)) = target;
4369 case MONO_PATCH_INFO_CLASS_INIT: {
4371 /* Might already been changed to a nop */
4372 x86_call_code (code, 0);
4373 x86_patch (ip, target);
4376 case MONO_PATCH_INFO_ABS:
4377 case MONO_PATCH_INFO_METHOD:
4378 case MONO_PATCH_INFO_METHOD_JUMP:
4379 case MONO_PATCH_INFO_INTERNAL_METHOD:
4380 case MONO_PATCH_INFO_BB:
4381 case MONO_PATCH_INFO_LABEL:
4382 case MONO_PATCH_INFO_RGCTX_FETCH:
4383 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
4384 case MONO_PATCH_INFO_MONITOR_ENTER:
4385 case MONO_PATCH_INFO_MONITOR_EXIT:
4386 x86_patch (ip, target);
4388 case MONO_PATCH_INFO_NONE:
4391 guint32 offset = mono_arch_get_patch_offset (ip);
4392 *((gconstpointer *)(ip + offset)) = target;
4400 mono_arch_emit_prolog (MonoCompile *cfg)
4402 MonoMethod *method = cfg->method;
4404 MonoMethodSignature *sig;
4406 int alloc_size, pos, max_offset, i, cfa_offset;
4408 gboolean need_stack_frame;
4410 cfg->code_size = MAX (mono_method_get_header (method)->code_size * 4, 10240);
4412 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4413 cfg->code_size += 512;
4415 code = cfg->native_code = g_malloc (cfg->code_size);
4417 /* Offset between RSP and the CFA */
4421 cfa_offset = sizeof (gpointer);
4422 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
4423 // IP saved at CFA - 4
4424 /* There is no IP reg on x86 */
4425 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
4427 need_stack_frame = needs_stack_frame (cfg);
4429 if (need_stack_frame) {
4430 x86_push_reg (code, X86_EBP);
4431 cfa_offset += sizeof (gpointer);
4432 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4433 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
4434 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
4435 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
4438 alloc_size = cfg->stack_offset;
4441 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4442 /* Might need to attach the thread to the JIT or change the domain for the callback */
4443 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4444 guint8 *buf, *no_domain_branch;
4446 code = mono_x86_emit_tls_get (code, X86_EAX, appdomain_tls_offset);
4447 x86_alu_reg_imm (code, X86_CMP, X86_EAX, GPOINTER_TO_UINT (cfg->domain));
4448 no_domain_branch = code;
4449 x86_branch8 (code, X86_CC_NE, 0, 0);
4450 code = mono_x86_emit_tls_get ( code, X86_EAX, lmf_tls_offset);
4451 x86_test_reg_reg (code, X86_EAX, X86_EAX);
4453 x86_branch8 (code, X86_CC_NE, 0, 0);
4454 x86_patch (no_domain_branch, code);
4455 x86_push_imm (code, cfg->domain);
4456 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4457 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
4458 x86_patch (buf, code);
4459 #ifdef PLATFORM_WIN32
4460 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4461 /* FIXME: Add a separate key for LMF to avoid this */
4462 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4466 g_assert (!cfg->compile_aot);
4467 x86_push_imm (code, cfg->domain);
4468 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4469 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
4473 if (method->save_lmf) {
4474 pos += sizeof (MonoLMF);
4476 /* save the current IP */
4477 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
4478 x86_push_imm_template (code);
4479 cfa_offset += sizeof (gpointer);
4481 /* save all caller saved regs */
4482 x86_push_reg (code, X86_EBP);
4483 cfa_offset += sizeof (gpointer);
4484 x86_push_reg (code, X86_ESI);
4485 cfa_offset += sizeof (gpointer);
4486 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
4487 x86_push_reg (code, X86_EDI);
4488 cfa_offset += sizeof (gpointer);
4489 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
4490 x86_push_reg (code, X86_EBX);
4491 cfa_offset += sizeof (gpointer);
4492 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
4494 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
4496 * Optimized version which uses the mono_lmf TLS variable instead of indirection
4497 * through the mono_lmf_addr TLS variable.
4499 /* %eax = previous_lmf */
4500 x86_prefix (code, X86_GS_PREFIX);
4501 x86_mov_reg_mem (code, X86_EAX, lmf_tls_offset, 4);
4502 /* skip esp + method_info + lmf */
4503 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 12);
4504 /* push previous_lmf */
4505 x86_push_reg (code, X86_EAX);
4507 x86_prefix (code, X86_GS_PREFIX);
4508 x86_mov_mem_reg (code, lmf_tls_offset, X86_ESP, 4);
4510 /* get the address of lmf for the current thread */
4512 * This is performance critical so we try to use some tricks to make
4516 if (lmf_addr_tls_offset != -1) {
4517 /* Load lmf quicky using the GS register */
4518 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
4519 #ifdef PLATFORM_WIN32
4520 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4521 /* FIXME: Add a separate key for LMF to avoid this */
4522 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4525 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
4528 /* Skip esp + method info */
4529 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
4532 x86_push_reg (code, X86_EAX);
4533 /* push *lfm (previous_lmf) */
4534 x86_push_membase (code, X86_EAX, 0);
4536 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
4540 if (cfg->used_int_regs & (1 << X86_EBX)) {
4541 x86_push_reg (code, X86_EBX);
4543 cfa_offset += sizeof (gpointer);
4544 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
4547 if (cfg->used_int_regs & (1 << X86_EDI)) {
4548 x86_push_reg (code, X86_EDI);
4550 cfa_offset += sizeof (gpointer);
4551 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
4554 if (cfg->used_int_regs & (1 << X86_ESI)) {
4555 x86_push_reg (code, X86_ESI);
4557 cfa_offset += sizeof (gpointer);
4558 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
4564 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
4565 if (mono_do_x86_stack_align && need_stack_frame) {
4566 int tot = alloc_size + pos + 4; /* ret ip */
4567 if (need_stack_frame)
4569 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
4571 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
4575 /* See mono_emit_stack_alloc */
4576 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4577 guint32 remaining_size = alloc_size;
4578 while (remaining_size >= 0x1000) {
4579 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
4580 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
4581 remaining_size -= 0x1000;
4584 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
4586 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
4589 g_assert (need_stack_frame);
4592 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
4593 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
4594 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
4597 #if DEBUG_STACK_ALIGNMENT
4598 /* check the stack is aligned */
4599 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
4600 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
4601 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
4602 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
4603 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
4604 x86_breakpoint (code);
4608 /* compute max_offset in order to use short forward jumps */
4610 if (cfg->opt & MONO_OPT_BRANCH) {
4611 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4613 bb->max_offset = max_offset;
4615 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4617 /* max alignment for loops */
4618 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4619 max_offset += LOOP_ALIGNMENT;
4621 MONO_BB_FOR_EACH_INS (bb, ins) {
4622 if (ins->opcode == OP_LABEL)
4623 ins->inst_c1 = max_offset;
4625 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4630 /* store runtime generic context */
4631 if (cfg->rgctx_var) {
4632 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
4634 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
4637 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4638 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4640 /* load arguments allocated to register from the stack */
4641 sig = mono_method_signature (method);
4644 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4645 inst = cfg->args [pos];
4646 if (inst->opcode == OP_REGVAR) {
4647 g_assert (need_stack_frame);
4648 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
4649 if (cfg->verbose_level > 2)
4650 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
4655 cfg->code_len = code - cfg->native_code;
4657 g_assert (cfg->code_len < cfg->code_size);
4663 mono_arch_emit_epilog (MonoCompile *cfg)
4665 MonoMethod *method = cfg->method;
4666 MonoMethodSignature *sig = mono_method_signature (method);
4668 guint32 stack_to_pop;
4670 int max_epilog_size = 16;
4672 gboolean need_stack_frame = needs_stack_frame (cfg);
4674 if (cfg->method->save_lmf)
4675 max_epilog_size += 128;
4677 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4678 cfg->code_size *= 2;
4679 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4680 mono_jit_stats.code_reallocs++;
4683 code = cfg->native_code + cfg->code_len;
4685 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4686 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4688 /* the code restoring the registers must be kept in sync with OP_JMP */
4691 if (method->save_lmf) {
4692 gint32 prev_lmf_reg;
4693 gint32 lmf_offset = -sizeof (MonoLMF);
4695 /* check if we need to restore protection of the stack after a stack overflow */
4696 if (mono_get_jit_tls_offset () != -1) {
4698 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
4699 /* we load the value in a separate instruction: this mechanism may be
4700 * used later as a safer way to do thread interruption
4702 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
4703 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
4705 x86_branch8 (code, X86_CC_Z, 0, FALSE);
4706 /* note that the call trampoline will preserve eax/edx */
4707 x86_call_reg (code, X86_ECX);
4708 x86_patch (patch, code);
4710 /* FIXME: maybe save the jit tls in the prolog */
4712 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
4714 * Optimized version which uses the mono_lmf TLS variable instead of indirection
4715 * through the mono_lmf_addr TLS variable.
4717 /* reg = previous_lmf */
4718 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
4720 /* lmf = previous_lmf */
4721 x86_prefix (code, X86_GS_PREFIX);
4722 x86_mov_mem_reg (code, lmf_tls_offset, X86_ECX, 4);
4724 /* Find a spare register */
4725 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
4728 prev_lmf_reg = X86_EDI;
4729 cfg->used_int_regs |= (1 << X86_EDI);
4732 prev_lmf_reg = X86_EDX;
4736 /* reg = previous_lmf */
4737 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
4740 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
4742 /* *(lmf) = previous_lmf */
4743 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
4746 /* restore caller saved regs */
4747 if (cfg->used_int_regs & (1 << X86_EBX)) {
4748 x86_mov_reg_membase (code, X86_EBX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
4751 if (cfg->used_int_regs & (1 << X86_EDI)) {
4752 x86_mov_reg_membase (code, X86_EDI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
4754 if (cfg->used_int_regs & (1 << X86_ESI)) {
4755 x86_mov_reg_membase (code, X86_ESI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
4758 /* EBP is restored by LEAVE */
4760 if (cfg->used_int_regs & (1 << X86_EBX)) {
4763 if (cfg->used_int_regs & (1 << X86_EDI)) {
4766 if (cfg->used_int_regs & (1 << X86_ESI)) {
4771 g_assert (need_stack_frame);
4772 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
4775 if (cfg->used_int_regs & (1 << X86_ESI)) {
4776 x86_pop_reg (code, X86_ESI);
4778 if (cfg->used_int_regs & (1 << X86_EDI)) {
4779 x86_pop_reg (code, X86_EDI);
4781 if (cfg->used_int_regs & (1 << X86_EBX)) {
4782 x86_pop_reg (code, X86_EBX);
4786 /* Load returned vtypes into registers if needed */
4787 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
4788 if (cinfo->ret.storage == ArgValuetypeInReg) {
4789 for (quad = 0; quad < 2; quad ++) {
4790 switch (cinfo->ret.pair_storage [quad]) {
4792 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
4794 case ArgOnFloatFpStack:
4795 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
4797 case ArgOnDoubleFpStack:
4798 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
4803 g_assert_not_reached ();
4808 if (need_stack_frame)
4811 if (CALLCONV_IS_STDCALL (sig)) {
4812 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
4814 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
4815 } else if (MONO_TYPE_ISSTRUCT (mono_method_signature (cfg->method)->ret) && (cinfo->ret.storage == ArgOnStack))
4821 g_assert (need_stack_frame);
4822 x86_ret_imm (code, stack_to_pop);
4827 cfg->code_len = code - cfg->native_code;
4829 g_assert (cfg->code_len < cfg->code_size);
4833 mono_arch_emit_exceptions (MonoCompile *cfg)
4835 MonoJumpInfo *patch_info;
4838 MonoClass *exc_classes [16];
4839 guint8 *exc_throw_start [16], *exc_throw_end [16];
4843 /* Compute needed space */
4844 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4845 if (patch_info->type == MONO_PATCH_INFO_EXC)
4850 * make sure we have enough space for exceptions
4851 * 16 is the size of two push_imm instructions and a call
4853 if (cfg->compile_aot)
4854 code_size = exc_count * 32;
4856 code_size = exc_count * 16;
4858 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4859 cfg->code_size *= 2;
4860 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4861 mono_jit_stats.code_reallocs++;
4864 code = cfg->native_code + cfg->code_len;
4867 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4868 switch (patch_info->type) {
4869 case MONO_PATCH_INFO_EXC: {
4870 MonoClass *exc_class;
4874 x86_patch (patch_info->ip.i + cfg->native_code, code);
4876 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4877 g_assert (exc_class);
4878 throw_ip = patch_info->ip.i;
4880 /* Find a throw sequence for the same exception class */
4881 for (i = 0; i < nthrows; ++i)
4882 if (exc_classes [i] == exc_class)
4885 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
4886 x86_jump_code (code, exc_throw_start [i]);
4887 patch_info->type = MONO_PATCH_INFO_NONE;
4892 /* Compute size of code following the push <OFFSET> */
4895 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
4897 if ((code - cfg->native_code) - throw_ip < 126 - size) {
4898 /* Use the shorter form */
4900 x86_push_imm (code, 0);
4904 x86_push_imm (code, 0xf0f0f0f0);
4909 exc_classes [nthrows] = exc_class;
4910 exc_throw_start [nthrows] = code;
4913 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
4914 patch_info->data.name = "mono_arch_throw_corlib_exception";
4915 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4916 patch_info->ip.i = code - cfg->native_code;
4917 x86_call_code (code, 0);
4918 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
4923 exc_throw_end [nthrows] = code;
4935 cfg->code_len = code - cfg->native_code;
4937 g_assert (cfg->code_len < cfg->code_size);
4941 mono_arch_flush_icache (guint8 *code, gint size)
4947 mono_arch_flush_register_windows (void)
4952 mono_arch_is_inst_imm (gint64 imm)
4958 * Support for fast access to the thread-local lmf structure using the GS
4959 * segment register on NPTL + kernel 2.6.x.
4962 static gboolean tls_offset_inited = FALSE;
4965 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
4967 if (!tls_offset_inited) {
4968 if (!getenv ("MONO_NO_TLS")) {
4969 #ifdef PLATFORM_WIN32
4971 * We need to init this multiple times, since when we are first called, the key might not
4972 * be initialized yet.
4974 appdomain_tls_offset = mono_domain_get_tls_key ();
4975 lmf_tls_offset = mono_get_jit_tls_key ();
4977 /* Only 64 tls entries can be accessed using inline code */
4978 if (appdomain_tls_offset >= 64)
4979 appdomain_tls_offset = -1;
4980 if (lmf_tls_offset >= 64)
4981 lmf_tls_offset = -1;
4984 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
4986 tls_offset_inited = TRUE;
4987 appdomain_tls_offset = mono_domain_get_tls_offset ();
4988 lmf_tls_offset = mono_get_lmf_tls_offset ();
4989 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
4996 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5000 #ifdef MONO_ARCH_HAVE_IMT
5002 // Linear handler, the bsearch head compare is shorter
5003 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5004 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5005 // x86_patch(ins,target)
5006 //[1 + 5] x86_jump_mem(inst,mem)
5009 #define BR_SMALL_SIZE 2
5010 #define BR_LARGE_SIZE 5
5011 #define JUMP_IMM_SIZE 6
5012 #define ENABLE_WRONG_METHOD_CHECK 0
5015 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5017 int i, distance = 0;
5018 for (i = start; i < target; ++i)
5019 distance += imt_entries [i]->chunk_size;
5024 * LOCKING: called with the domain lock held
5027 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5028 gpointer fail_tramp)
5032 guint8 *code, *start;
5034 for (i = 0; i < count; ++i) {
5035 MonoIMTCheckItem *item = imt_entries [i];
5036 if (item->is_equals) {
5037 if (item->check_target_idx) {
5038 if (!item->compare_done)
5039 item->chunk_size += CMP_SIZE;
5040 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5043 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5045 item->chunk_size += JUMP_IMM_SIZE;
5046 #if ENABLE_WRONG_METHOD_CHECK
5047 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5052 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5053 imt_entries [item->check_target_idx]->compare_done = TRUE;
5055 size += item->chunk_size;
5058 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5060 code = mono_domain_code_reserve (domain, size);
5062 for (i = 0; i < count; ++i) {
5063 MonoIMTCheckItem *item = imt_entries [i];
5064 item->code_target = code;
5065 if (item->is_equals) {
5066 if (item->check_target_idx) {
5067 if (!item->compare_done)
5068 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5069 item->jmp_code = code;
5070 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5071 if (item->has_target_code)
5072 x86_jump_code (code, item->value.target_code);
5074 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5077 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5078 item->jmp_code = code;
5079 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5080 if (item->has_target_code)
5081 x86_jump_code (code, item->value.target_code);
5083 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5084 x86_patch (item->jmp_code, code);
5085 x86_jump_code (code, fail_tramp);
5086 item->jmp_code = NULL;
5088 /* enable the commented code to assert on wrong method */
5089 #if ENABLE_WRONG_METHOD_CHECK
5090 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5091 item->jmp_code = code;
5092 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5094 if (item->has_target_code)
5095 x86_jump_code (code, item->value.target_code);
5097 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5098 #if ENABLE_WRONG_METHOD_CHECK
5099 x86_patch (item->jmp_code, code);
5100 x86_breakpoint (code);
5101 item->jmp_code = NULL;
5106 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5107 item->jmp_code = code;
5108 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5109 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5111 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5114 /* patch the branches to get to the target items */
5115 for (i = 0; i < count; ++i) {
5116 MonoIMTCheckItem *item = imt_entries [i];
5117 if (item->jmp_code) {
5118 if (item->check_target_idx) {
5119 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5125 mono_stats.imt_thunks_size += code - start;
5126 g_assert (code - start <= size);
5131 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5133 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5137 mono_arch_find_this_argument (mgreg_t *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
5139 MonoMethodSignature *sig = mono_method_signature (method);
5140 CallInfo *cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5141 int this_argument_offset;
5142 MonoObject *this_argument;
5145 * this is the offset of the this arg from esp as saved at the start of
5146 * mono_arch_create_trampoline_code () in tramp-x86.c.
5148 this_argument_offset = 5;
5149 if (MONO_TYPE_ISSTRUCT (sig->ret) && (cinfo->ret.storage == ArgOnStack))
5150 this_argument_offset++;
5152 this_argument = * (MonoObject**) (((guint8*) regs [X86_ESP]) + this_argument_offset * sizeof (gpointer));
5155 return this_argument;
5160 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5162 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5166 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5168 MonoInst *ins = NULL;
5171 if (cmethod->klass == mono_defaults.math_class) {
5172 if (strcmp (cmethod->name, "Sin") == 0) {
5174 } else if (strcmp (cmethod->name, "Cos") == 0) {
5176 } else if (strcmp (cmethod->name, "Tan") == 0) {
5178 } else if (strcmp (cmethod->name, "Atan") == 0) {
5180 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5182 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5184 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5189 MONO_INST_NEW (cfg, ins, opcode);
5190 ins->type = STACK_R8;
5191 ins->dreg = mono_alloc_freg (cfg);
5192 ins->sreg1 = args [0]->dreg;
5193 MONO_ADD_INS (cfg->cbb, ins);
5196 if (cfg->opt & MONO_OPT_CMOV) {
5199 if (strcmp (cmethod->name, "Min") == 0) {
5200 if (fsig->params [0]->type == MONO_TYPE_I4)
5202 } else if (strcmp (cmethod->name, "Max") == 0) {
5203 if (fsig->params [0]->type == MONO_TYPE_I4)
5208 MONO_INST_NEW (cfg, ins, opcode);
5209 ins->type = STACK_I4;
5210 ins->dreg = mono_alloc_ireg (cfg);
5211 ins->sreg1 = args [0]->dreg;
5212 ins->sreg2 = args [1]->dreg;
5213 MONO_ADD_INS (cfg->cbb, ins);
5218 /* OP_FREM is not IEEE compatible */
5219 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5220 MONO_INST_NEW (cfg, ins, OP_FREM);
5221 ins->inst_i0 = args [0];
5222 ins->inst_i1 = args [1];
5231 mono_arch_print_tree (MonoInst *tree, int arity)
5236 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5242 if (appdomain_tls_offset == -1)
5245 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5246 ins->inst_offset = appdomain_tls_offset;
5251 mono_arch_get_patch_offset (guint8 *code)
5253 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5255 else if ((code [0] == 0xba))
5257 else if ((code [0] == 0x68))
5260 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5261 /* push <OFFSET>(<REG>) */
5263 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5264 /* call *<OFFSET>(<REG>) */
5266 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5269 else if ((code [0] == 0x58) && (code [1] == 0x05))
5270 /* pop %eax; add <OFFSET>, %eax */
5272 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5273 /* pop <REG>; add <OFFSET>, <REG> */
5275 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5276 /* mov <REG>, imm */
5279 g_assert_not_reached ();
5285 * mono_breakpoint_clean_code:
5287 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5288 * breakpoints in the original code, they are removed in the copy.
5290 * Returns TRUE if no sw breakpoint was present.
5293 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5296 gboolean can_write = TRUE;
5298 * If method_start is non-NULL we need to perform bound checks, since we access memory
5299 * at code - offset we could go before the start of the method and end up in a different
5300 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5303 if (!method_start || code - offset >= method_start) {
5304 memcpy (buf, code - offset, size);
5306 int diff = code - method_start;
5307 memset (buf, 0, size);
5308 memcpy (buf + offset - diff, method_start, diff + size - offset);
5311 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5312 int idx = mono_breakpoint_info_index [i];
5316 ptr = mono_breakpoint_info [idx].address;
5317 if (ptr >= code && ptr < code + size) {
5318 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5320 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5321 buf [ptr - code] = saved_byte;
5328 mono_arch_get_vcall_slot (guint8 *code, mgreg_t *regs, int *displacement)
5334 mono_breakpoint_clean_code (NULL, code, 8, buf, sizeof (buf));
5342 * A given byte sequence can match more than case here, so we have to be
5343 * really careful about the ordering of the cases. Longer sequences
5345 * There are two types of calls:
5346 * - direct calls: 0xff address_byte 8/32 bits displacement
5347 * - indirect calls: nop nop nop <call>
5348 * The nops make sure we don't confuse the instruction preceeding an indirect
5349 * call with a direct call.
5351 if ((code [1] != 0xe8) && (code [3] == 0xff) && ((code [4] & 0x18) == 0x10) && ((code [4] >> 6) == 1)) {
5352 reg = code [4] & 0x07;
5353 disp = (signed char)code [5];
5354 } else if ((code [0] == 0xff) && ((code [1] & 0x18) == 0x10) && ((code [1] >> 6) == 2)) {
5355 reg = code [1] & 0x07;
5356 disp = *((gint32*)(code + 2));
5357 } else if ((code [1] == 0xe8)) {
5359 } else if ((code [4] == 0xff) && (((code [5] >> 6) & 0x3) == 0) && (((code [5] >> 3) & 0x7) == 2)) {
5361 * This is a interface call
5362 * 8b 40 30 mov 0x30(%eax),%eax
5363 * ff 10 call *(%eax)
5366 reg = code [5] & 0x07;
5371 *displacement = disp;
5372 return (gpointer)regs [reg];
5376 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig,
5377 mgreg_t *regs, guint8 *code)
5379 guint32 esp = regs [X86_ESP];
5380 CallInfo *cinfo = NULL;
5385 * Avoid expensive calls to get_generic_context_from_code () + get_call_info
5388 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5390 gsctx = mono_get_generic_context_from_code (code);
5391 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5393 offset = cinfo->args [0].offset;
5399 * The stack looks like:
5402 * <possible vtype return address>
5404 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
5406 res = (((MonoObject**)esp) [5 + (offset / 4)]);
5412 #define MAX_ARCH_DELEGATE_PARAMS 10
5415 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5417 guint8 *code, *start;
5419 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5422 /* FIXME: Support more cases */
5423 if (MONO_TYPE_ISSTRUCT (sig->ret))
5427 * The stack contains:
5433 static guint8* cached = NULL;
5437 start = code = mono_global_codeman_reserve (64);
5439 /* Replace the this argument with the target */
5440 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5441 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
5442 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5443 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5445 g_assert ((code - start) < 64);
5447 mono_debug_add_delegate_trampoline (start, code - start);
5449 mono_memory_barrier ();
5453 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5455 /* 8 for mov_reg and jump, plus 8 for each parameter */
5456 int code_reserve = 8 + (sig->param_count * 8);
5458 for (i = 0; i < sig->param_count; ++i)
5459 if (!mono_is_regsize_var (sig->params [i]))
5462 code = cache [sig->param_count];
5467 * The stack contains:
5468 * <args in reverse order>
5473 * <args in reverse order>
5476 * without unbalancing the stack.
5477 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
5478 * and leaving original spot of first arg as placeholder in stack so
5479 * when callee pops stack everything works.
5482 start = code = mono_global_codeman_reserve (code_reserve);
5484 /* store delegate for access to method_ptr */
5485 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
5488 for (i = 0; i < sig->param_count; ++i) {
5489 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
5490 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
5493 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5495 g_assert ((code - start) < code_reserve);
5497 mono_debug_add_delegate_trampoline (start, code - start);
5499 mono_memory_barrier ();
5501 cache [sig->param_count] = start;
5508 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5511 case X86_EAX: return (gpointer)ctx->eax;
5512 case X86_EBX: return (gpointer)ctx->ebx;
5513 case X86_ECX: return (gpointer)ctx->ecx;
5514 case X86_EDX: return (gpointer)ctx->edx;
5515 case X86_ESP: return (gpointer)ctx->esp;
5516 case X86_EBP: return (gpointer)ctx->ebp;
5517 case X86_ESI: return (gpointer)ctx->esi;
5518 case X86_EDI: return (gpointer)ctx->edi;
5519 default: g_assert_not_reached ();
5523 #ifdef MONO_ARCH_SIMD_INTRINSICS
5526 get_float_to_x_spill_area (MonoCompile *cfg)
5528 if (!cfg->fconv_to_r8_x_var) {
5529 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
5530 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
5532 return cfg->fconv_to_r8_x_var;
5536 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
5539 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
5542 int dreg, src_opcode;
5544 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
5547 switch (src_opcode = ins->opcode) {
5548 case OP_FCONV_TO_I1:
5549 case OP_FCONV_TO_U1:
5550 case OP_FCONV_TO_I2:
5551 case OP_FCONV_TO_U2:
5552 case OP_FCONV_TO_I4:
5559 /* dreg is the IREG and sreg1 is the FREG */
5560 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
5561 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
5562 fconv->sreg1 = ins->sreg1;
5563 fconv->dreg = mono_alloc_ireg (cfg);
5564 fconv->type = STACK_VTYPE;
5565 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
5567 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
5571 ins->opcode = OP_XCONV_R8_TO_I4;
5573 ins->klass = mono_defaults.int32_class;
5574 ins->sreg1 = fconv->dreg;
5576 ins->type = STACK_I4;
5577 ins->backend.source_opcode = src_opcode;
5580 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
5583 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
5588 if (long_ins->opcode == OP_LNEG) {
5590 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
5591 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
5592 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
5597 #ifdef MONO_ARCH_SIMD_INTRINSICS
5599 if (!(cfg->opt & MONO_OPT_SIMD))
5602 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
5603 switch (long_ins->opcode) {
5605 vreg = long_ins->sreg1;
5607 if (long_ins->inst_c0) {
5608 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
5609 ins->klass = long_ins->klass;
5610 ins->sreg1 = long_ins->sreg1;
5612 ins->type = STACK_VTYPE;
5613 ins->dreg = vreg = alloc_ireg (cfg);
5614 MONO_ADD_INS (cfg->cbb, ins);
5617 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
5618 ins->klass = mono_defaults.int32_class;
5620 ins->type = STACK_I4;
5621 ins->dreg = long_ins->dreg + 1;
5622 MONO_ADD_INS (cfg->cbb, ins);
5624 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
5625 ins->klass = long_ins->klass;
5626 ins->sreg1 = long_ins->sreg1;
5627 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
5628 ins->type = STACK_VTYPE;
5629 ins->dreg = vreg = alloc_ireg (cfg);
5630 MONO_ADD_INS (cfg->cbb, ins);
5632 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
5633 ins->klass = mono_defaults.int32_class;
5635 ins->type = STACK_I4;
5636 ins->dreg = long_ins->dreg + 2;
5637 MONO_ADD_INS (cfg->cbb, ins);
5639 long_ins->opcode = OP_NOP;
5641 case OP_INSERTX_I8_SLOW:
5642 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
5643 ins->dreg = long_ins->dreg;
5644 ins->sreg1 = long_ins->dreg;
5645 ins->sreg2 = long_ins->sreg2 + 1;
5646 ins->inst_c0 = long_ins->inst_c0 * 2;
5647 MONO_ADD_INS (cfg->cbb, ins);
5649 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
5650 ins->dreg = long_ins->dreg;
5651 ins->sreg1 = long_ins->dreg;
5652 ins->sreg2 = long_ins->sreg2 + 2;
5653 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
5654 MONO_ADD_INS (cfg->cbb, ins);
5656 long_ins->opcode = OP_NOP;
5659 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
5660 ins->dreg = long_ins->dreg;
5661 ins->sreg1 = long_ins->sreg1 + 1;
5662 ins->klass = long_ins->klass;
5663 ins->type = STACK_VTYPE;
5664 MONO_ADD_INS (cfg->cbb, ins);
5666 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
5667 ins->dreg = long_ins->dreg;
5668 ins->sreg1 = long_ins->dreg;
5669 ins->sreg2 = long_ins->sreg1 + 2;
5671 ins->klass = long_ins->klass;
5672 ins->type = STACK_VTYPE;
5673 MONO_ADD_INS (cfg->cbb, ins);
5675 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
5676 ins->dreg = long_ins->dreg;
5677 ins->sreg1 = long_ins->dreg;;
5678 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
5679 ins->klass = long_ins->klass;
5680 ins->type = STACK_VTYPE;
5681 MONO_ADD_INS (cfg->cbb, ins);
5683 long_ins->opcode = OP_NOP;
5686 #endif /* MONO_ARCH_SIMD_INTRINSICS */