2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/appdomain.h>
21 #include <mono/metadata/debug-helpers.h>
22 #include <mono/metadata/threads.h>
23 #include <mono/metadata/profiler-private.h>
24 #include <mono/metadata/mono-debug.h>
25 #include <mono/metadata/gc-internal.h>
26 #include <mono/utils/mono-math.h>
27 #include <mono/utils/mono-counters.h>
28 #include <mono/utils/mono-mmap.h>
29 #include <mono/utils/mono-memory-model.h>
30 #include <mono/utils/mono-hwcap-x86.h>
38 /* On windows, these hold the key returned by TlsAlloc () */
39 static gint lmf_tls_offset = -1;
41 static gint jit_tls_offset = -1;
43 static gint lmf_addr_tls_offset = -1;
45 static gint appdomain_tls_offset = -1;
48 static gboolean optimize_for_xen = TRUE;
50 #define optimize_for_xen 0
54 static gboolean is_win32 = TRUE;
56 static gboolean is_win32 = FALSE;
59 /* This mutex protects architecture specific caches */
60 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
61 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
62 static CRITICAL_SECTION mini_arch_mutex;
64 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
69 /* Under windows, the default pinvoke calling convention is stdcall */
70 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
72 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
75 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
78 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
81 #ifdef __native_client_codegen__
83 /* Default alignment for Native Client is 32-byte. */
84 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
86 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
87 /* Check that alignment doesn't cross an alignment boundary. */
89 mono_arch_nacl_pad (guint8 *code, int pad)
91 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
93 if (pad == 0) return code;
94 /* assertion: alignment cannot cross a block boundary */
95 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
96 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
97 while (pad >= kMaxPadding) {
98 x86_padding (code, kMaxPadding);
101 if (pad != 0) x86_padding (code, pad);
106 mono_arch_nacl_skip_nops (guint8 *code)
108 x86_skip_nops (code);
112 #endif /* __native_client_codegen__ */
115 * The code generated for sequence points reads from this location, which is
116 * made read-only when single stepping is enabled.
118 static gpointer ss_trigger_page;
120 /* Enabled breakpoints read from this trigger page */
121 static gpointer bp_trigger_page;
124 mono_arch_regname (int reg)
127 case X86_EAX: return "%eax";
128 case X86_EBX: return "%ebx";
129 case X86_ECX: return "%ecx";
130 case X86_EDX: return "%edx";
131 case X86_ESP: return "%esp";
132 case X86_EBP: return "%ebp";
133 case X86_EDI: return "%edi";
134 case X86_ESI: return "%esi";
140 mono_arch_fregname (int reg)
165 mono_arch_xregname (int reg)
190 mono_x86_patch (unsigned char* code, gpointer target)
192 x86_patch (code, (unsigned char*)target);
203 /* gsharedvt argument passed by addr */
215 /* Only if storage == ArgValuetypeInReg */
216 ArgStorage pair_storage [2];
225 gboolean need_stack_align;
226 guint32 stack_align_amount;
227 gboolean vtype_retaddr;
228 /* The index of the vret arg in the argument list */
236 #define FLOAT_PARAM_REGS 0
238 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
240 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
245 switch (sig->call_convention) {
246 case MONO_CALL_THISCALL:
247 return thiscall_param_regs;
253 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
254 #define SMALL_STRUCTS_IN_REGS
255 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
259 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
261 ainfo->offset = *stack_size;
263 if (!param_regs || param_regs [*gr] == X86_NREG) {
264 ainfo->storage = ArgOnStack;
266 (*stack_size) += sizeof (gpointer);
269 ainfo->storage = ArgInIReg;
270 ainfo->reg = param_regs [*gr];
276 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
278 ainfo->offset = *stack_size;
280 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
282 ainfo->storage = ArgOnStack;
283 (*stack_size) += sizeof (gpointer) * 2;
288 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
290 ainfo->offset = *stack_size;
292 if (*gr >= FLOAT_PARAM_REGS) {
293 ainfo->storage = ArgOnStack;
294 (*stack_size) += is_double ? 8 : 4;
295 ainfo->nslots = is_double ? 2 : 1;
298 /* A double register */
300 ainfo->storage = ArgInDoubleSSEReg;
302 ainfo->storage = ArgInFloatSSEReg;
310 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
312 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
317 klass = mono_class_from_mono_type (type);
318 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
320 #ifdef SMALL_STRUCTS_IN_REGS
321 if (sig->pinvoke && is_return) {
322 MonoMarshalType *info;
325 * the exact rules are not very well documented, the code below seems to work with the
326 * code generated by gcc 3.3.3 -mno-cygwin.
328 info = mono_marshal_load_type_info (klass);
331 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
333 /* Special case structs with only a float member */
334 if ((info->native_size == 8) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R8)) {
335 ainfo->storage = ArgValuetypeInReg;
336 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
339 if ((info->native_size == 4) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R4)) {
340 ainfo->storage = ArgValuetypeInReg;
341 ainfo->pair_storage [0] = ArgOnFloatFpStack;
344 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
345 ainfo->storage = ArgValuetypeInReg;
346 ainfo->pair_storage [0] = ArgInIReg;
347 ainfo->pair_regs [0] = return_regs [0];
348 if (info->native_size > 4) {
349 ainfo->pair_storage [1] = ArgInIReg;
350 ainfo->pair_regs [1] = return_regs [1];
357 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
358 g_assert (size <= 4);
359 ainfo->storage = ArgValuetypeInReg;
360 ainfo->reg = param_regs [*gr];
365 ainfo->offset = *stack_size;
366 ainfo->storage = ArgOnStack;
367 *stack_size += ALIGN_TO (size, sizeof (gpointer));
368 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
374 * Obtain information about a call according to the calling convention.
375 * For x86 ELF, see the "System V Application Binary Interface Intel386
376 * Architecture Processor Supplment, Fourth Edition" document for more
378 * For x86 win32, see ???.
381 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
383 guint32 i, gr, fr, pstart;
384 const guint32 *param_regs;
386 int n = sig->hasthis + sig->param_count;
387 guint32 stack_size = 0;
388 gboolean is_pinvoke = sig->pinvoke;
394 param_regs = callconv_param_regs(sig);
398 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
399 switch (ret_type->type) {
400 case MONO_TYPE_BOOLEAN:
411 case MONO_TYPE_FNPTR:
412 case MONO_TYPE_CLASS:
413 case MONO_TYPE_OBJECT:
414 case MONO_TYPE_SZARRAY:
415 case MONO_TYPE_ARRAY:
416 case MONO_TYPE_STRING:
417 cinfo->ret.storage = ArgInIReg;
418 cinfo->ret.reg = X86_EAX;
422 cinfo->ret.storage = ArgInIReg;
423 cinfo->ret.reg = X86_EAX;
424 cinfo->ret.is_pair = TRUE;
427 cinfo->ret.storage = ArgOnFloatFpStack;
430 cinfo->ret.storage = ArgOnDoubleFpStack;
432 case MONO_TYPE_GENERICINST:
433 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
434 cinfo->ret.storage = ArgInIReg;
435 cinfo->ret.reg = X86_EAX;
438 if (mini_is_gsharedvt_type_gsctx (gsctx, ret_type)) {
439 cinfo->ret.storage = ArgOnStack;
440 cinfo->vtype_retaddr = TRUE;
444 case MONO_TYPE_VALUETYPE:
445 case MONO_TYPE_TYPEDBYREF: {
446 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
448 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
449 if (cinfo->ret.storage == ArgOnStack) {
450 cinfo->vtype_retaddr = TRUE;
451 /* The caller passes the address where the value is stored */
457 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ret_type));
458 cinfo->ret.storage = ArgOnStack;
459 cinfo->vtype_retaddr = TRUE;
462 cinfo->ret.storage = ArgNone;
465 g_error ("Can't handle as return value 0x%x", sig->ret->type);
471 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
472 * the first argument, allowing 'this' to be always passed in the first arg reg.
473 * Also do this if the first argument is a reference type, since virtual calls
474 * are sometimes made using calli without sig->hasthis set, like in the delegate
477 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
479 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
481 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
484 cinfo->vret_arg_offset = stack_size;
485 add_general (&gr, NULL, &stack_size, &cinfo->ret);
486 cinfo->vret_arg_index = 1;
490 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
492 if (cinfo->vtype_retaddr)
493 add_general (&gr, NULL, &stack_size, &cinfo->ret);
496 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
497 fr = FLOAT_PARAM_REGS;
499 /* Emit the signature cookie just before the implicit arguments */
500 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
503 for (i = pstart; i < sig->param_count; ++i) {
504 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
507 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
508 /* We allways pass the sig cookie on the stack for simplicity */
510 * Prevent implicit arguments + the sig cookie from being passed
513 fr = FLOAT_PARAM_REGS;
515 /* Emit the signature cookie just before the implicit arguments */
516 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
519 if (sig->params [i]->byref) {
520 add_general (&gr, param_regs, &stack_size, ainfo);
523 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
524 switch (ptype->type) {
525 case MONO_TYPE_BOOLEAN:
528 add_general (&gr, param_regs, &stack_size, ainfo);
533 add_general (&gr, param_regs, &stack_size, ainfo);
537 add_general (&gr, param_regs, &stack_size, ainfo);
542 case MONO_TYPE_FNPTR:
543 case MONO_TYPE_CLASS:
544 case MONO_TYPE_OBJECT:
545 case MONO_TYPE_STRING:
546 case MONO_TYPE_SZARRAY:
547 case MONO_TYPE_ARRAY:
548 add_general (&gr, param_regs, &stack_size, ainfo);
550 case MONO_TYPE_GENERICINST:
551 if (!mono_type_generic_inst_is_valuetype (ptype)) {
552 add_general (&gr, param_regs, &stack_size, ainfo);
555 if (mini_is_gsharedvt_type_gsctx (gsctx, ptype)) {
556 /* gsharedvt arguments are passed by ref */
557 add_general (&gr, param_regs, &stack_size, ainfo);
558 g_assert (ainfo->storage == ArgOnStack);
559 ainfo->storage = ArgGSharedVt;
563 case MONO_TYPE_VALUETYPE:
564 case MONO_TYPE_TYPEDBYREF:
565 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
569 add_general_pair (&gr, param_regs, &stack_size, ainfo);
572 add_float (&fr, &stack_size, ainfo, FALSE);
575 add_float (&fr, &stack_size, ainfo, TRUE);
579 /* gsharedvt arguments are passed by ref */
580 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ptype));
581 add_general (&gr, param_regs, &stack_size, ainfo);
582 g_assert (ainfo->storage == ArgOnStack);
583 ainfo->storage = ArgGSharedVt;
586 g_error ("unexpected type 0x%x", ptype->type);
587 g_assert_not_reached ();
591 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
592 fr = FLOAT_PARAM_REGS;
594 /* Emit the signature cookie just before the implicit arguments */
595 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
598 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
599 cinfo->need_stack_align = TRUE;
600 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
601 stack_size += cinfo->stack_align_amount;
604 cinfo->stack_usage = stack_size;
605 cinfo->reg_usage = gr;
606 cinfo->freg_usage = fr;
611 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
613 int n = sig->hasthis + sig->param_count;
617 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
619 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
621 return get_call_info_internal (gsctx, cinfo, sig);
625 * mono_arch_get_argument_info:
626 * @csig: a method signature
627 * @param_count: the number of parameters to consider
628 * @arg_info: an array to store the result infos
630 * Gathers information on parameters such as size, alignment and
631 * padding. arg_info should be large enought to hold param_count + 1 entries.
633 * Returns the size of the argument area on the stack.
634 * This should be signal safe, since it is called from
635 * mono_arch_find_jit_info ().
636 * FIXME: The metadata calls might not be signal safe.
639 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
641 int len, k, args_size = 0;
647 /* Avoid g_malloc as it is not signal safe */
648 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
649 cinfo = (CallInfo*)g_newa (guint8*, len);
650 memset (cinfo, 0, len);
652 cinfo = get_call_info_internal (gsctx, cinfo, csig);
654 arg_info [0].offset = offset;
656 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
657 args_size += sizeof (gpointer);
662 args_size += sizeof (gpointer);
666 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
667 /* Emitted after this */
668 args_size += sizeof (gpointer);
672 arg_info [0].size = args_size;
674 for (k = 0; k < param_count; k++) {
675 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
677 /* ignore alignment for now */
680 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
681 arg_info [k].pad = pad;
683 arg_info [k + 1].pad = 0;
684 arg_info [k + 1].size = size;
686 arg_info [k + 1].offset = offset;
689 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
690 /* Emitted after the first arg */
691 args_size += sizeof (gpointer);
696 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
697 align = MONO_ARCH_FRAME_ALIGNMENT;
700 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
701 arg_info [k].pad = pad;
707 mono_x86_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
712 c1 = get_call_info (NULL, NULL, caller_sig);
713 c2 = get_call_info (NULL, NULL, callee_sig);
714 res = c1->stack_usage >= c2->stack_usage;
715 if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
716 /* An address on the callee's stack is passed as the first argument */
726 * Initialize the cpu to execute managed code.
729 mono_arch_cpu_init (void)
731 /* spec compliance requires running with double precision */
735 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
736 fpcw &= ~X86_FPCW_PRECC_MASK;
737 fpcw |= X86_FPCW_PREC_DOUBLE;
738 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
739 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
741 _control87 (_PC_53, MCW_PC);
746 * Initialize architecture specific code.
749 mono_arch_init (void)
751 InitializeCriticalSection (&mini_arch_mutex);
753 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
754 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
755 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
757 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
758 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
759 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
760 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
765 * Cleanup architecture specific code.
768 mono_arch_cleanup (void)
771 mono_vfree (ss_trigger_page, mono_pagesize ());
773 mono_vfree (bp_trigger_page, mono_pagesize ());
774 DeleteCriticalSection (&mini_arch_mutex);
778 * This function returns the optimizations supported on this cpu.
781 mono_arch_cpu_optimizations (guint32 *exclude_mask)
783 #if !defined(__native_client__)
788 if (mono_hwcap_x86_has_cmov) {
789 opts |= MONO_OPT_CMOV;
791 if (mono_hwcap_x86_has_fcmov)
792 opts |= MONO_OPT_FCMOV;
794 *exclude_mask |= MONO_OPT_FCMOV;
796 *exclude_mask |= MONO_OPT_CMOV;
799 if (mono_hwcap_x86_has_sse2)
800 opts |= MONO_OPT_SSE2;
802 *exclude_mask |= MONO_OPT_SSE2;
804 #ifdef MONO_ARCH_SIMD_INTRINSICS
805 /*SIMD intrinsics require at least SSE2.*/
806 if (!mono_hwcap_x86_has_sse2)
807 *exclude_mask |= MONO_OPT_SIMD;
812 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
817 * This function test for all SSE functions supported.
819 * Returns a bitmask corresponding to all supported versions.
823 mono_arch_cpu_enumerate_simd_versions (void)
825 guint32 sse_opts = 0;
827 if (mono_hwcap_x86_has_sse1)
828 sse_opts |= SIMD_VERSION_SSE1;
830 if (mono_hwcap_x86_has_sse2)
831 sse_opts |= SIMD_VERSION_SSE2;
833 if (mono_hwcap_x86_has_sse3)
834 sse_opts |= SIMD_VERSION_SSE3;
836 if (mono_hwcap_x86_has_ssse3)
837 sse_opts |= SIMD_VERSION_SSSE3;
839 if (mono_hwcap_x86_has_sse41)
840 sse_opts |= SIMD_VERSION_SSE41;
842 if (mono_hwcap_x86_has_sse42)
843 sse_opts |= SIMD_VERSION_SSE42;
845 if (mono_hwcap_x86_has_sse4a)
846 sse_opts |= SIMD_VERSION_SSE4a;
852 * Determine whenever the trap whose info is in SIGINFO is caused by
856 mono_arch_is_int_overflow (void *sigctx, void *info)
861 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
863 ip = (guint8*)ctx.eip;
865 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
869 switch (x86_modrm_rm (ip [1])) {
889 g_assert_not_reached ();
901 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
906 for (i = 0; i < cfg->num_varinfo; i++) {
907 MonoInst *ins = cfg->varinfo [i];
908 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
911 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
914 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
915 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
918 /* we dont allocate I1 to registers because there is no simply way to sign extend
919 * 8bit quantities in caller saved registers on x86 */
920 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
921 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
922 g_assert (i == vmv->idx);
923 vars = g_list_prepend (vars, vmv);
927 vars = mono_varlist_sort (cfg, vars, 0);
933 mono_arch_get_global_int_regs (MonoCompile *cfg)
937 /* we can use 3 registers for global allocation */
938 regs = g_list_prepend (regs, (gpointer)X86_EBX);
939 regs = g_list_prepend (regs, (gpointer)X86_ESI);
940 regs = g_list_prepend (regs, (gpointer)X86_EDI);
946 * mono_arch_regalloc_cost:
948 * Return the cost, in number of memory references, of the action of
949 * allocating the variable VMV into a register during global register
953 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
955 MonoInst *ins = cfg->varinfo [vmv->idx];
957 if (cfg->method->save_lmf)
958 /* The register is already saved */
959 return (ins->opcode == OP_ARG) ? 1 : 0;
961 /* push+pop+possible load if it is an argument */
962 return (ins->opcode == OP_ARG) ? 3 : 2;
966 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
968 static int inited = FALSE;
969 static int count = 0;
971 if (cfg->arch.need_stack_frame_inited) {
972 g_assert (cfg->arch.need_stack_frame == flag);
976 cfg->arch.need_stack_frame = flag;
977 cfg->arch.need_stack_frame_inited = TRUE;
983 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
988 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
992 needs_stack_frame (MonoCompile *cfg)
994 MonoMethodSignature *sig;
995 MonoMethodHeader *header;
996 gboolean result = FALSE;
998 #if defined(__APPLE__)
999 /*OSX requires stack frame code to have the correct alignment. */
1003 if (cfg->arch.need_stack_frame_inited)
1004 return cfg->arch.need_stack_frame;
1006 header = cfg->header;
1007 sig = mono_method_signature (cfg->method);
1009 if (cfg->disable_omit_fp)
1011 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1013 else if (cfg->method->save_lmf)
1015 else if (cfg->stack_offset)
1017 else if (cfg->param_area)
1019 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1021 else if (header->num_clauses)
1023 else if (sig->param_count + sig->hasthis)
1025 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1027 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1028 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1031 set_needs_stack_frame (cfg, result);
1033 return cfg->arch.need_stack_frame;
1037 * Set var information according to the calling convention. X86 version.
1038 * The locals var stuff should most likely be split in another method.
1041 mono_arch_allocate_vars (MonoCompile *cfg)
1043 MonoMethodSignature *sig;
1044 MonoMethodHeader *header;
1046 guint32 locals_stack_size, locals_stack_align;
1051 header = cfg->header;
1052 sig = mono_method_signature (cfg->method);
1054 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1056 cfg->frame_reg = X86_EBP;
1059 /* Reserve space to save LMF and caller saved registers */
1061 if (cfg->method->save_lmf) {
1062 offset += sizeof (MonoLMF);
1064 if (cfg->used_int_regs & (1 << X86_EBX)) {
1068 if (cfg->used_int_regs & (1 << X86_EDI)) {
1072 if (cfg->used_int_regs & (1 << X86_ESI)) {
1077 switch (cinfo->ret.storage) {
1078 case ArgValuetypeInReg:
1079 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1081 cfg->ret->opcode = OP_REGOFFSET;
1082 cfg->ret->inst_basereg = X86_EBP;
1083 cfg->ret->inst_offset = - offset;
1089 /* Allocate locals */
1090 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1091 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1092 char *mname = mono_method_full_name (cfg->method, TRUE);
1093 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1094 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1098 if (locals_stack_align) {
1099 int prev_offset = offset;
1101 offset += (locals_stack_align - 1);
1102 offset &= ~(locals_stack_align - 1);
1104 while (prev_offset < offset) {
1106 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1109 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1110 cfg->locals_max_stack_offset = - offset;
1112 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1113 * have locals larger than 8 bytes we need to make sure that
1114 * they have the appropriate offset.
1116 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1117 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1118 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1119 if (offsets [i] != -1) {
1120 MonoInst *inst = cfg->varinfo [i];
1121 inst->opcode = OP_REGOFFSET;
1122 inst->inst_basereg = X86_EBP;
1123 inst->inst_offset = - (offset + offsets [i]);
1124 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1127 offset += locals_stack_size;
1131 * Allocate arguments+return value
1134 switch (cinfo->ret.storage) {
1136 if (cfg->vret_addr) {
1138 * In the new IR, the cfg->vret_addr variable represents the
1139 * vtype return value.
1141 cfg->vret_addr->opcode = OP_REGOFFSET;
1142 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1143 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1144 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1145 printf ("vret_addr =");
1146 mono_print_ins (cfg->vret_addr);
1149 cfg->ret->opcode = OP_REGOFFSET;
1150 cfg->ret->inst_basereg = X86_EBP;
1151 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1154 case ArgValuetypeInReg:
1157 cfg->ret->opcode = OP_REGVAR;
1158 cfg->ret->inst_c0 = cinfo->ret.reg;
1159 cfg->ret->dreg = cinfo->ret.reg;
1162 case ArgOnFloatFpStack:
1163 case ArgOnDoubleFpStack:
1166 g_assert_not_reached ();
1169 if (sig->call_convention == MONO_CALL_VARARG) {
1170 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1171 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1174 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1175 ArgInfo *ainfo = &cinfo->args [i];
1176 inst = cfg->args [i];
1177 if (inst->opcode != OP_REGVAR) {
1178 inst->opcode = OP_REGOFFSET;
1179 inst->inst_basereg = X86_EBP;
1181 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1184 cfg->stack_offset = offset;
1188 mono_arch_create_vars (MonoCompile *cfg)
1190 MonoMethodSignature *sig;
1193 sig = mono_method_signature (cfg->method);
1195 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1197 if (cinfo->ret.storage == ArgValuetypeInReg)
1198 cfg->ret_var_is_local = TRUE;
1199 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig->ret) || mini_is_gsharedvt_variable_type (cfg, sig->ret))) {
1200 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1203 cfg->arch_eh_jit_info = 1;
1207 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1208 * so we try to do it just once when we have multiple fp arguments in a row.
1209 * We don't use this mechanism generally because for int arguments the generated code
1210 * is slightly bigger and new generation cpus optimize away the dependency chains
1211 * created by push instructions on the esp value.
1212 * fp_arg_setup is the first argument in the execution sequence where the esp register
1215 static G_GNUC_UNUSED int
1216 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1221 for (; start_arg < sig->param_count; ++start_arg) {
1222 t = mini_type_get_underlying_type (NULL, sig->params [start_arg]);
1223 if (!t->byref && t->type == MONO_TYPE_R8) {
1224 fp_space += sizeof (double);
1225 *fp_arg_setup = start_arg;
1234 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1236 MonoMethodSignature *tmp_sig;
1240 * mono_ArgIterator_Setup assumes the signature cookie is
1241 * passed first and all the arguments which were before it are
1242 * passed on the stack after the signature. So compensate by
1243 * passing a different signature.
1245 tmp_sig = mono_metadata_signature_dup (call->signature);
1246 tmp_sig->param_count -= call->signature->sentinelpos;
1247 tmp_sig->sentinelpos = 0;
1248 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1250 if (cfg->compile_aot) {
1251 sig_reg = mono_alloc_ireg (cfg);
1252 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1253 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, sig_reg);
1255 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1261 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1266 LLVMCallInfo *linfo;
1269 n = sig->param_count + sig->hasthis;
1271 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1273 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1276 * LLVM always uses the native ABI while we use our own ABI, the
1277 * only difference is the handling of vtypes:
1278 * - we only pass/receive them in registers in some cases, and only
1279 * in 1 or 2 integer registers.
1281 if (cinfo->ret.storage == ArgValuetypeInReg) {
1283 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1284 cfg->disable_llvm = TRUE;
1288 cfg->exception_message = g_strdup ("vtype ret in call");
1289 cfg->disable_llvm = TRUE;
1291 linfo->ret.storage = LLVMArgVtypeInReg;
1292 for (j = 0; j < 2; ++j)
1293 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1297 if (mini_type_is_vtype (cfg, sig->ret) && cinfo->ret.storage == ArgInIReg) {
1298 /* Vtype returned using a hidden argument */
1299 linfo->ret.storage = LLVMArgVtypeRetAddr;
1300 linfo->vret_arg_index = cinfo->vret_arg_index;
1303 if (mini_type_is_vtype (cfg, sig->ret) && cinfo->ret.storage != ArgInIReg) {
1305 cfg->exception_message = g_strdup ("vtype ret in call");
1306 cfg->disable_llvm = TRUE;
1309 for (i = 0; i < n; ++i) {
1310 ainfo = cinfo->args + i;
1312 if (i >= sig->hasthis)
1313 t = sig->params [i - sig->hasthis];
1315 t = &mono_defaults.int_class->byval_arg;
1317 linfo->args [i].storage = LLVMArgNone;
1319 switch (ainfo->storage) {
1321 linfo->args [i].storage = LLVMArgInIReg;
1323 case ArgInDoubleSSEReg:
1324 case ArgInFloatSSEReg:
1325 linfo->args [i].storage = LLVMArgInFPReg;
1328 if (mini_type_is_vtype (cfg, t)) {
1329 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1330 /* LLVM seems to allocate argument space for empty structures too */
1331 linfo->args [i].storage = LLVMArgNone;
1333 linfo->args [i].storage = LLVMArgVtypeByVal;
1335 linfo->args [i].storage = LLVMArgInIReg;
1337 if (t->type == MONO_TYPE_R4)
1338 linfo->args [i].storage = LLVMArgInFPReg;
1339 else if (t->type == MONO_TYPE_R8)
1340 linfo->args [i].storage = LLVMArgInFPReg;
1344 case ArgValuetypeInReg:
1346 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1347 cfg->disable_llvm = TRUE;
1351 cfg->exception_message = g_strdup ("vtype arg");
1352 cfg->disable_llvm = TRUE;
1354 linfo->args [i].storage = LLVMArgVtypeInReg;
1355 for (j = 0; j < 2; ++j)
1356 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1360 linfo->args [i].storage = LLVMArgGSharedVt;
1363 cfg->exception_message = g_strdup ("ainfo->storage");
1364 cfg->disable_llvm = TRUE;
1374 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1376 if (cfg->compute_gc_maps) {
1379 /* On x86, the offsets are from the sp value before the start of the call sequence */
1381 t = &mono_defaults.int_class->byval_arg;
1382 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1387 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1390 MonoMethodSignature *sig;
1393 int sentinelpos = 0, sp_offset = 0;
1395 sig = call->signature;
1396 n = sig->param_count + sig->hasthis;
1398 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1400 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1401 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1403 if (cinfo->need_stack_align) {
1404 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1405 arg->dreg = X86_ESP;
1406 arg->sreg1 = X86_ESP;
1407 arg->inst_imm = cinfo->stack_align_amount;
1408 MONO_ADD_INS (cfg->cbb, arg);
1409 for (i = 0; i < cinfo->stack_align_amount; i += sizeof (mgreg_t)) {
1412 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1416 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1417 if (cinfo->ret.storage == ArgValuetypeInReg) {
1419 * Tell the JIT to use a more efficient calling convention: call using
1420 * OP_CALL, compute the result location after the call, and save the
1423 call->vret_in_reg = TRUE;
1425 NULLIFY_INS (call->vret_var);
1429 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1431 /* Handle the case where there are no implicit arguments */
1432 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1433 emit_sig_cookie (cfg, call, cinfo);
1435 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1438 /* Arguments are pushed in the reverse order */
1439 for (i = n - 1; i >= 0; i --) {
1440 ArgInfo *ainfo = cinfo->args + i;
1441 MonoType *orig_type, *t;
1444 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1445 /* Push the vret arg before the first argument */
1447 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1448 vtarg->type = STACK_MP;
1449 vtarg->sreg1 = call->vret_var->dreg;
1450 MONO_ADD_INS (cfg->cbb, vtarg);
1452 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1455 if (i >= sig->hasthis)
1456 t = sig->params [i - sig->hasthis];
1458 t = &mono_defaults.int_class->byval_arg;
1460 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1462 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1464 in = call->args [i];
1465 arg->cil_code = in->cil_code;
1466 arg->sreg1 = in->dreg;
1467 arg->type = in->type;
1469 g_assert (in->dreg != -1);
1471 if (ainfo->storage == ArgGSharedVt) {
1472 arg->opcode = OP_OUTARG_VT;
1473 arg->sreg1 = in->dreg;
1474 arg->klass = in->klass;
1476 MONO_ADD_INS (cfg->cbb, arg);
1477 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1481 g_assert (in->klass);
1483 if (t->type == MONO_TYPE_TYPEDBYREF) {
1484 size = sizeof (MonoTypedRef);
1485 align = sizeof (gpointer);
1488 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1492 arg->opcode = OP_OUTARG_VT;
1493 arg->sreg1 = in->dreg;
1494 arg->klass = in->klass;
1495 arg->backend.size = size;
1496 arg->inst_p0 = call;
1497 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1498 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1500 MONO_ADD_INS (cfg->cbb, arg);
1501 if (ainfo->storage != ArgValuetypeInReg) {
1503 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1509 switch (ainfo->storage) {
1511 arg->opcode = OP_X86_PUSH;
1513 if (t->type == MONO_TYPE_R4) {
1514 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1515 arg->opcode = OP_STORER4_MEMBASE_REG;
1516 arg->inst_destbasereg = X86_ESP;
1517 arg->inst_offset = 0;
1519 } else if (t->type == MONO_TYPE_R8) {
1520 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1521 arg->opcode = OP_STORER8_MEMBASE_REG;
1522 arg->inst_destbasereg = X86_ESP;
1523 arg->inst_offset = 0;
1525 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1527 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1533 arg->opcode = OP_MOVE;
1534 arg->dreg = ainfo->reg;
1538 g_assert_not_reached ();
1541 MONO_ADD_INS (cfg->cbb, arg);
1543 sp_offset += argsize;
1545 if (cfg->compute_gc_maps) {
1547 /* FIXME: The == STACK_OBJ check might be fragile ? */
1548 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1550 if (call->need_unbox_trampoline)
1551 /* The unbox trampoline transforms this into a managed pointer */
1552 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.int_class->this_arg);
1554 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.object_class->byval_arg);
1556 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1560 for (j = 0; j < argsize; j += 4)
1561 emit_gc_param_slot_def (cfg, sp_offset - j, NULL);
1566 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1567 /* Emit the signature cookie just before the implicit arguments */
1568 emit_sig_cookie (cfg, call, cinfo);
1570 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1574 if (sig->ret && (MONO_TYPE_ISSTRUCT (sig->ret) || cinfo->vtype_retaddr)) {
1577 if (cinfo->ret.storage == ArgValuetypeInReg) {
1580 else if (cinfo->ret.storage == ArgInIReg) {
1582 /* The return address is passed in a register */
1583 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1584 vtarg->sreg1 = call->inst.dreg;
1585 vtarg->dreg = mono_alloc_ireg (cfg);
1586 MONO_ADD_INS (cfg->cbb, vtarg);
1588 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1589 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1591 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1592 vtarg->type = STACK_MP;
1593 vtarg->sreg1 = call->vret_var->dreg;
1594 MONO_ADD_INS (cfg->cbb, vtarg);
1596 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1599 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1600 if (cinfo->ret.storage != ArgValuetypeInReg)
1601 cinfo->stack_usage -= 4;
1604 call->stack_usage = cinfo->stack_usage;
1605 call->stack_align_amount = cinfo->stack_align_amount;
1606 cfg->arch.param_area_size = MAX (cfg->arch.param_area_size, sp_offset);
1610 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1612 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1613 ArgInfo *ainfo = ins->inst_p1;
1615 int size = ins->backend.size;
1617 if (ainfo->storage == ArgValuetypeInReg) {
1618 int dreg = mono_alloc_ireg (cfg);
1621 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1624 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1627 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1631 g_assert_not_reached ();
1633 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1636 if (cfg->gsharedvt && mini_is_gsharedvt_klass (cfg, ins->klass)) {
1638 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1639 arg->sreg1 = src->dreg;
1640 MONO_ADD_INS (cfg->cbb, arg);
1641 } else if (size <= 4) {
1642 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1643 arg->sreg1 = src->dreg;
1645 MONO_ADD_INS (cfg->cbb, arg);
1646 } else if (size <= 20) {
1647 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1648 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1650 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1651 arg->inst_basereg = src->dreg;
1652 arg->inst_offset = 0;
1653 arg->inst_imm = size;
1655 MONO_ADD_INS (cfg->cbb, arg);
1661 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1663 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1666 if (ret->type == MONO_TYPE_R4) {
1667 if (COMPILE_LLVM (cfg))
1668 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1671 } else if (ret->type == MONO_TYPE_R8) {
1672 if (COMPILE_LLVM (cfg))
1673 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1676 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1677 if (COMPILE_LLVM (cfg))
1678 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1680 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1681 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1687 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1691 * Allow tracing to work with this interface (with an optional argument)
1694 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1698 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1699 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1701 /* if some args are passed in registers, we need to save them here */
1702 x86_push_reg (code, X86_EBP);
1704 if (cfg->compile_aot) {
1705 x86_push_imm (code, cfg->method);
1706 x86_mov_reg_imm (code, X86_EAX, func);
1707 x86_call_reg (code, X86_EAX);
1709 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1710 x86_push_imm (code, cfg->method);
1711 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1712 x86_call_code (code, 0);
1714 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1728 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1731 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1732 MonoMethod *method = cfg->method;
1733 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1735 switch (ret_type->type) {
1736 case MONO_TYPE_VOID:
1737 /* special case string .ctor icall */
1738 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1739 save_mode = SAVE_EAX;
1740 stack_usage = enable_arguments ? 8 : 4;
1742 save_mode = SAVE_NONE;
1746 save_mode = SAVE_EAX_EDX;
1747 stack_usage = enable_arguments ? 16 : 8;
1751 save_mode = SAVE_FP;
1752 stack_usage = enable_arguments ? 16 : 8;
1754 case MONO_TYPE_GENERICINST:
1755 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1756 save_mode = SAVE_EAX;
1757 stack_usage = enable_arguments ? 8 : 4;
1761 case MONO_TYPE_VALUETYPE:
1762 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1763 save_mode = SAVE_STRUCT;
1764 stack_usage = enable_arguments ? 4 : 0;
1767 save_mode = SAVE_EAX;
1768 stack_usage = enable_arguments ? 8 : 4;
1772 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1774 switch (save_mode) {
1776 x86_push_reg (code, X86_EDX);
1777 x86_push_reg (code, X86_EAX);
1778 if (enable_arguments) {
1779 x86_push_reg (code, X86_EDX);
1780 x86_push_reg (code, X86_EAX);
1785 x86_push_reg (code, X86_EAX);
1786 if (enable_arguments) {
1787 x86_push_reg (code, X86_EAX);
1792 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1793 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1794 if (enable_arguments) {
1795 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1796 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1801 if (enable_arguments) {
1802 x86_push_membase (code, X86_EBP, 8);
1811 if (cfg->compile_aot) {
1812 x86_push_imm (code, method);
1813 x86_mov_reg_imm (code, X86_EAX, func);
1814 x86_call_reg (code, X86_EAX);
1816 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1817 x86_push_imm (code, method);
1818 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1819 x86_call_code (code, 0);
1822 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1824 switch (save_mode) {
1826 x86_pop_reg (code, X86_EAX);
1827 x86_pop_reg (code, X86_EDX);
1830 x86_pop_reg (code, X86_EAX);
1833 x86_fld_membase (code, X86_ESP, 0, TRUE);
1834 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1841 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1846 #define EMIT_COND_BRANCH(ins,cond,sign) \
1847 if (ins->inst_true_bb->native_offset) { \
1848 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1850 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1851 if ((cfg->opt & MONO_OPT_BRANCH) && \
1852 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1853 x86_branch8 (code, cond, 0, sign); \
1855 x86_branch32 (code, cond, 0, sign); \
1859 * Emit an exception if condition is fail and
1860 * if possible do a directly branch to target
1862 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1864 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1865 if (tins == NULL) { \
1866 mono_add_patch_info (cfg, code - cfg->native_code, \
1867 MONO_PATCH_INFO_EXC, exc_name); \
1868 x86_branch32 (code, cond, 0, signed); \
1870 EMIT_COND_BRANCH (tins, cond, signed); \
1874 #define EMIT_FPCOMPARE(code) do { \
1875 x86_fcompp (code); \
1876 x86_fnstsw (code); \
1881 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1883 gboolean needs_paddings = TRUE;
1885 MonoJumpInfo *jinfo = NULL;
1887 if (cfg->abs_patches) {
1888 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1889 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1890 needs_paddings = FALSE;
1893 if (cfg->compile_aot)
1894 needs_paddings = FALSE;
1895 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1896 This is required for code patching to be safe on SMP machines.
1898 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1899 #ifndef __native_client_codegen__
1900 if (needs_paddings && pad_size)
1901 x86_padding (code, 4 - pad_size);
1904 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1905 x86_call_code (code, 0);
1910 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1913 * mono_peephole_pass_1:
1915 * Perform peephole opts which should/can be performed before local regalloc
1918 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1922 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1923 MonoInst *last_ins = ins->prev;
1925 switch (ins->opcode) {
1928 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1930 * X86_LEA is like ADD, but doesn't have the
1931 * sreg1==dreg restriction.
1933 ins->opcode = OP_X86_LEA_MEMBASE;
1934 ins->inst_basereg = ins->sreg1;
1935 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1936 ins->opcode = OP_X86_INC_REG;
1940 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1941 ins->opcode = OP_X86_LEA_MEMBASE;
1942 ins->inst_basereg = ins->sreg1;
1943 ins->inst_imm = -ins->inst_imm;
1944 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1945 ins->opcode = OP_X86_DEC_REG;
1947 case OP_COMPARE_IMM:
1948 case OP_ICOMPARE_IMM:
1949 /* OP_COMPARE_IMM (reg, 0)
1951 * OP_X86_TEST_NULL (reg)
1954 ins->opcode = OP_X86_TEST_NULL;
1956 case OP_X86_COMPARE_MEMBASE_IMM:
1958 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1959 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1961 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1962 * OP_COMPARE_IMM reg, imm
1964 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1966 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1967 ins->inst_basereg == last_ins->inst_destbasereg &&
1968 ins->inst_offset == last_ins->inst_offset) {
1969 ins->opcode = OP_COMPARE_IMM;
1970 ins->sreg1 = last_ins->sreg1;
1972 /* check if we can remove cmp reg,0 with test null */
1974 ins->opcode = OP_X86_TEST_NULL;
1978 case OP_X86_PUSH_MEMBASE:
1979 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1980 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1981 ins->inst_basereg == last_ins->inst_destbasereg &&
1982 ins->inst_offset == last_ins->inst_offset) {
1983 ins->opcode = OP_X86_PUSH;
1984 ins->sreg1 = last_ins->sreg1;
1989 mono_peephole_ins (bb, ins);
1994 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1998 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1999 switch (ins->opcode) {
2001 /* reg = 0 -> XOR (reg, reg) */
2002 /* XOR sets cflags on x86, so we cant do it always */
2003 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2006 ins->opcode = OP_IXOR;
2007 ins->sreg1 = ins->dreg;
2008 ins->sreg2 = ins->dreg;
2011 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2012 * since it takes 3 bytes instead of 7.
2014 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2015 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2016 ins2->opcode = OP_STORE_MEMBASE_REG;
2017 ins2->sreg1 = ins->dreg;
2019 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2020 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2021 ins2->sreg1 = ins->dreg;
2023 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2024 /* Continue iteration */
2033 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2034 ins->opcode = OP_X86_INC_REG;
2038 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2039 ins->opcode = OP_X86_DEC_REG;
2043 mono_peephole_ins (bb, ins);
2048 * mono_arch_lowering_pass:
2050 * Converts complex opcodes into simpler ones so that each IR instruction
2051 * corresponds to one machine instruction.
2054 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2056 MonoInst *ins, *next;
2059 * FIXME: Need to add more instructions, but the current machine
2060 * description can't model some parts of the composite instructions like
2063 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2064 switch (ins->opcode) {
2067 case OP_IDIV_UN_IMM:
2068 case OP_IREM_UN_IMM:
2070 * Keep the cases where we could generated optimized code, otherwise convert
2071 * to the non-imm variant.
2073 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2075 mono_decompose_op_imm (cfg, bb, ins);
2082 bb->max_vreg = cfg->next_vreg;
2086 branch_cc_table [] = {
2087 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2088 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2089 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2092 /* Maps CMP_... constants to X86_CC_... constants */
2095 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2096 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2100 cc_signed_table [] = {
2101 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2102 FALSE, FALSE, FALSE, FALSE
2105 static unsigned char*
2106 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2108 #define XMM_TEMP_REG 0
2109 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2110 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2111 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2112 /* optimize by assigning a local var for this use so we avoid
2113 * the stack manipulations */
2114 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2115 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2116 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2117 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2118 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2120 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2122 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2125 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2126 x86_fnstcw_membase(code, X86_ESP, 0);
2127 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2128 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2129 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2130 x86_fldcw_membase (code, X86_ESP, 2);
2132 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2133 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2134 x86_pop_reg (code, dreg);
2135 /* FIXME: need the high register
2136 * x86_pop_reg (code, dreg_high);
2139 x86_push_reg (code, X86_EAX); // SP = SP - 4
2140 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2141 x86_pop_reg (code, dreg);
2143 x86_fldcw_membase (code, X86_ESP, 0);
2144 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2147 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2149 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2153 static unsigned char*
2154 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2156 int sreg = tree->sreg1;
2157 int need_touch = FALSE;
2159 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2168 * If requested stack size is larger than one page,
2169 * perform stack-touch operation
2172 * Generate stack probe code.
2173 * Under Windows, it is necessary to allocate one page at a time,
2174 * "touching" stack after each successful sub-allocation. This is
2175 * because of the way stack growth is implemented - there is a
2176 * guard page before the lowest stack page that is currently commited.
2177 * Stack normally grows sequentially so OS traps access to the
2178 * guard page and commits more pages when needed.
2180 x86_test_reg_imm (code, sreg, ~0xFFF);
2181 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2183 br[2] = code; /* loop */
2184 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2185 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2188 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2189 * that follows only initializes the last part of the area.
2191 /* Same as the init code below with size==0x1000 */
2192 if (tree->flags & MONO_INST_INIT) {
2193 x86_push_reg (code, X86_EAX);
2194 x86_push_reg (code, X86_ECX);
2195 x86_push_reg (code, X86_EDI);
2196 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2197 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2198 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2200 x86_prefix (code, X86_REP_PREFIX);
2202 x86_pop_reg (code, X86_EDI);
2203 x86_pop_reg (code, X86_ECX);
2204 x86_pop_reg (code, X86_EAX);
2207 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2208 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2209 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2210 x86_patch (br[3], br[2]);
2211 x86_test_reg_reg (code, sreg, sreg);
2212 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2213 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2215 br[1] = code; x86_jump8 (code, 0);
2217 x86_patch (br[0], code);
2218 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2219 x86_patch (br[1], code);
2220 x86_patch (br[4], code);
2223 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2225 if (tree->flags & MONO_INST_INIT) {
2227 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2228 x86_push_reg (code, X86_EAX);
2231 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2232 x86_push_reg (code, X86_ECX);
2235 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2236 x86_push_reg (code, X86_EDI);
2240 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2241 if (sreg != X86_ECX)
2242 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2243 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2245 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2247 x86_prefix (code, X86_REP_PREFIX);
2250 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2251 x86_pop_reg (code, X86_EDI);
2252 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2253 x86_pop_reg (code, X86_ECX);
2254 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2255 x86_pop_reg (code, X86_EAX);
2262 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2264 /* Move return value to the target register */
2265 switch (ins->opcode) {
2268 case OP_CALL_MEMBASE:
2269 if (ins->dreg != X86_EAX)
2270 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2280 static int tls_gs_offset;
2284 mono_x86_have_tls_get (void)
2287 static gboolean have_tls_get = FALSE;
2288 static gboolean inited = FALSE;
2292 return have_tls_get;
2294 ins = (guint32*)pthread_getspecific;
2296 * We're looking for these two instructions:
2298 * mov 0x4(%esp),%eax
2299 * mov %gs:[offset](,%eax,4),%eax
2301 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2302 tls_gs_offset = ins [2];
2306 return have_tls_get;
2307 #elif defined(TARGET_ANDROID)
2315 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2317 #if defined(__APPLE__)
2318 x86_prefix (code, X86_GS_PREFIX);
2319 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2320 #elif defined(TARGET_WIN32)
2321 g_assert_not_reached ();
2323 x86_prefix (code, X86_GS_PREFIX);
2324 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2330 * mono_x86_emit_tls_get:
2331 * @code: buffer to store code to
2332 * @dreg: hard register where to place the result
2333 * @tls_offset: offset info
2335 * mono_x86_emit_tls_get emits in @code the native code that puts in
2336 * the dreg register the item in the thread local storage identified
2339 * Returns: a pointer to the end of the stored code
2342 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2344 #if defined(__APPLE__)
2345 x86_prefix (code, X86_GS_PREFIX);
2346 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2347 #elif defined(TARGET_WIN32)
2349 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2350 * Journal and/or a disassembly of the TlsGet () function.
2352 g_assert (tls_offset < 64);
2353 x86_prefix (code, X86_FS_PREFIX);
2354 x86_mov_reg_mem (code, dreg, 0x18, 4);
2355 /* Dunno what this does but TlsGetValue () contains it */
2356 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2357 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2359 if (optimize_for_xen) {
2360 x86_prefix (code, X86_GS_PREFIX);
2361 x86_mov_reg_mem (code, dreg, 0, 4);
2362 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2364 x86_prefix (code, X86_GS_PREFIX);
2365 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2372 * emit_load_volatile_arguments:
2374 * Load volatile arguments from the stack to the original input registers.
2375 * Required before a tail call.
2378 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2380 MonoMethod *method = cfg->method;
2381 MonoMethodSignature *sig;
2386 /* FIXME: Generate intermediate code instead */
2388 sig = mono_method_signature (method);
2390 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2392 /* This is the opposite of the code in emit_prolog */
2394 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2395 ArgInfo *ainfo = cinfo->args + i;
2397 inst = cfg->args [i];
2399 if (sig->hasthis && (i == 0))
2400 arg_type = &mono_defaults.object_class->byval_arg;
2402 arg_type = sig->params [i - sig->hasthis];
2405 * On x86, the arguments are either in their original stack locations, or in
2408 if (inst->opcode == OP_REGVAR) {
2409 g_assert (ainfo->storage == ArgOnStack);
2411 x86_mov_membase_reg (code, X86_EBP, inst->inst_offset, inst->dreg, 4);
2418 #define REAL_PRINT_REG(text,reg) \
2419 mono_assert (reg >= 0); \
2420 x86_push_reg (code, X86_EAX); \
2421 x86_push_reg (code, X86_EDX); \
2422 x86_push_reg (code, X86_ECX); \
2423 x86_push_reg (code, reg); \
2424 x86_push_imm (code, reg); \
2425 x86_push_imm (code, text " %d %p\n"); \
2426 x86_mov_reg_imm (code, X86_EAX, printf); \
2427 x86_call_reg (code, X86_EAX); \
2428 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2429 x86_pop_reg (code, X86_ECX); \
2430 x86_pop_reg (code, X86_EDX); \
2431 x86_pop_reg (code, X86_EAX);
2433 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2434 #ifdef __native__client_codegen__
2435 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2438 /* benchmark and set based on cpu */
2439 #define LOOP_ALIGNMENT 8
2440 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2444 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2449 guint8 *code = cfg->native_code + cfg->code_len;
2452 if (cfg->opt & MONO_OPT_LOOP) {
2453 int pad, align = LOOP_ALIGNMENT;
2454 /* set alignment depending on cpu */
2455 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2457 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2458 x86_padding (code, pad);
2459 cfg->code_len += pad;
2460 bb->native_offset = cfg->code_len;
2463 #ifdef __native_client_codegen__
2465 /* For Native Client, all indirect call/jump targets must be */
2466 /* 32-byte aligned. Exception handler blocks are jumped to */
2467 /* indirectly as well. */
2468 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2469 (bb->flags & BB_EXCEPTION_HANDLER);
2471 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2472 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2473 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2474 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2475 cfg->code_len += pad;
2476 bb->native_offset = cfg->code_len;
2479 #endif /* __native_client_codegen__ */
2480 if (cfg->verbose_level > 2)
2481 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2483 cpos = bb->max_offset;
2485 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2486 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2487 g_assert (!cfg->compile_aot);
2490 cov->data [bb->dfn].cil_code = bb->cil_code;
2491 /* this is not thread save, but good enough */
2492 x86_inc_mem (code, &cov->data [bb->dfn].count);
2495 offset = code - cfg->native_code;
2497 mono_debug_open_block (cfg, bb, offset);
2499 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2500 x86_breakpoint (code);
2502 MONO_BB_FOR_EACH_INS (bb, ins) {
2503 offset = code - cfg->native_code;
2505 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2507 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2509 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2510 cfg->code_size *= 2;
2511 cfg->native_code = mono_realloc_native_code(cfg);
2512 code = cfg->native_code + offset;
2513 cfg->stat_code_reallocs++;
2516 if (cfg->debug_info)
2517 mono_debug_record_line_number (cfg, ins, offset);
2519 switch (ins->opcode) {
2521 x86_mul_reg (code, ins->sreg2, TRUE);
2524 x86_mul_reg (code, ins->sreg2, FALSE);
2526 case OP_X86_SETEQ_MEMBASE:
2527 case OP_X86_SETNE_MEMBASE:
2528 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2529 ins->inst_basereg, ins->inst_offset, TRUE);
2531 case OP_STOREI1_MEMBASE_IMM:
2532 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2534 case OP_STOREI2_MEMBASE_IMM:
2535 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2537 case OP_STORE_MEMBASE_IMM:
2538 case OP_STOREI4_MEMBASE_IMM:
2539 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2541 case OP_STOREI1_MEMBASE_REG:
2542 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2544 case OP_STOREI2_MEMBASE_REG:
2545 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2547 case OP_STORE_MEMBASE_REG:
2548 case OP_STOREI4_MEMBASE_REG:
2549 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2551 case OP_STORE_MEM_IMM:
2552 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2555 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2559 /* These are created by the cprop pass so they use inst_imm as the source */
2560 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2563 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2566 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2568 case OP_LOAD_MEMBASE:
2569 case OP_LOADI4_MEMBASE:
2570 case OP_LOADU4_MEMBASE:
2571 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2573 case OP_LOADU1_MEMBASE:
2574 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2576 case OP_LOADI1_MEMBASE:
2577 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2579 case OP_LOADU2_MEMBASE:
2580 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2582 case OP_LOADI2_MEMBASE:
2583 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2585 case OP_ICONV_TO_I1:
2587 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2589 case OP_ICONV_TO_I2:
2591 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2593 case OP_ICONV_TO_U1:
2594 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2596 case OP_ICONV_TO_U2:
2597 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2601 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2603 case OP_COMPARE_IMM:
2604 case OP_ICOMPARE_IMM:
2605 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2607 case OP_X86_COMPARE_MEMBASE_REG:
2608 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2610 case OP_X86_COMPARE_MEMBASE_IMM:
2611 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2613 case OP_X86_COMPARE_MEMBASE8_IMM:
2614 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2616 case OP_X86_COMPARE_REG_MEMBASE:
2617 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2619 case OP_X86_COMPARE_MEM_IMM:
2620 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2622 case OP_X86_TEST_NULL:
2623 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2625 case OP_X86_ADD_MEMBASE_IMM:
2626 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2628 case OP_X86_ADD_REG_MEMBASE:
2629 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2631 case OP_X86_SUB_MEMBASE_IMM:
2632 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2634 case OP_X86_SUB_REG_MEMBASE:
2635 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2637 case OP_X86_AND_MEMBASE_IMM:
2638 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2640 case OP_X86_OR_MEMBASE_IMM:
2641 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2643 case OP_X86_XOR_MEMBASE_IMM:
2644 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2646 case OP_X86_ADD_MEMBASE_REG:
2647 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2649 case OP_X86_SUB_MEMBASE_REG:
2650 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2652 case OP_X86_AND_MEMBASE_REG:
2653 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2655 case OP_X86_OR_MEMBASE_REG:
2656 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2658 case OP_X86_XOR_MEMBASE_REG:
2659 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2661 case OP_X86_INC_MEMBASE:
2662 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2664 case OP_X86_INC_REG:
2665 x86_inc_reg (code, ins->dreg);
2667 case OP_X86_DEC_MEMBASE:
2668 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2670 case OP_X86_DEC_REG:
2671 x86_dec_reg (code, ins->dreg);
2673 case OP_X86_MUL_REG_MEMBASE:
2674 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2676 case OP_X86_AND_REG_MEMBASE:
2677 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2679 case OP_X86_OR_REG_MEMBASE:
2680 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2682 case OP_X86_XOR_REG_MEMBASE:
2683 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2686 x86_breakpoint (code);
2688 case OP_RELAXED_NOP:
2689 x86_prefix (code, X86_REP_PREFIX);
2697 case OP_DUMMY_STORE:
2698 case OP_NOT_REACHED:
2701 case OP_SEQ_POINT: {
2704 if (cfg->compile_aot)
2708 * Read from the single stepping trigger page. This will cause a
2709 * SIGSEGV when single stepping is enabled.
2710 * We do this _before_ the breakpoint, so single stepping after
2711 * a breakpoint is hit will step to the next IL offset.
2713 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2714 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2716 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2719 * A placeholder for a possible breakpoint inserted by
2720 * mono_arch_set_breakpoint ().
2722 for (i = 0; i < 6; ++i)
2725 * Add an additional nop so skipping the bp doesn't cause the ip to point
2726 * to another IL offset.
2734 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2738 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2743 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2747 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2752 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2756 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2761 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2765 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2768 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2772 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2776 #if defined( __native_client_codegen__ )
2777 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2778 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2781 * The code is the same for div/rem, the allocator will allocate dreg
2782 * to RAX/RDX as appropriate.
2784 if (ins->sreg2 == X86_EDX) {
2785 /* cdq clobbers this */
2786 x86_push_reg (code, ins->sreg2);
2788 x86_div_membase (code, X86_ESP, 0, TRUE);
2789 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2792 x86_div_reg (code, ins->sreg2, TRUE);
2797 #if defined( __native_client_codegen__ )
2798 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2799 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2801 if (ins->sreg2 == X86_EDX) {
2802 x86_push_reg (code, ins->sreg2);
2803 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2804 x86_div_membase (code, X86_ESP, 0, FALSE);
2805 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2807 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2808 x86_div_reg (code, ins->sreg2, FALSE);
2812 #if defined( __native_client_codegen__ )
2813 if (ins->inst_imm == 0) {
2814 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2815 x86_jump32 (code, 0);
2819 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2821 x86_div_reg (code, ins->sreg2, TRUE);
2824 int power = mono_is_power_of_two (ins->inst_imm);
2826 g_assert (ins->sreg1 == X86_EAX);
2827 g_assert (ins->dreg == X86_EAX);
2828 g_assert (power >= 0);
2831 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2833 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2835 * If the divident is >= 0, this does not nothing. If it is positive, it
2836 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2838 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2839 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2840 } else if (power == 0) {
2841 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2843 /* Based on gcc code */
2845 /* Add compensation for negative dividents */
2847 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2848 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2849 /* Compute remainder */
2850 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2851 /* Remove compensation */
2852 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2857 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2861 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2864 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2868 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2871 g_assert (ins->sreg2 == X86_ECX);
2872 x86_shift_reg (code, X86_SHL, ins->dreg);
2875 g_assert (ins->sreg2 == X86_ECX);
2876 x86_shift_reg (code, X86_SAR, ins->dreg);
2880 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2883 case OP_ISHR_UN_IMM:
2884 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2887 g_assert (ins->sreg2 == X86_ECX);
2888 x86_shift_reg (code, X86_SHR, ins->dreg);
2892 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2895 guint8 *jump_to_end;
2897 /* handle shifts below 32 bits */
2898 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2899 x86_shift_reg (code, X86_SHL, ins->sreg1);
2901 x86_test_reg_imm (code, X86_ECX, 32);
2902 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2904 /* handle shift over 32 bit */
2905 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2906 x86_clear_reg (code, ins->sreg1);
2908 x86_patch (jump_to_end, code);
2912 guint8 *jump_to_end;
2914 /* handle shifts below 32 bits */
2915 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2916 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2918 x86_test_reg_imm (code, X86_ECX, 32);
2919 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2921 /* handle shifts over 31 bits */
2922 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2923 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2925 x86_patch (jump_to_end, code);
2929 guint8 *jump_to_end;
2931 /* handle shifts below 32 bits */
2932 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2933 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2935 x86_test_reg_imm (code, X86_ECX, 32);
2936 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2938 /* handle shifts over 31 bits */
2939 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2940 x86_clear_reg (code, ins->backend.reg3);
2942 x86_patch (jump_to_end, code);
2946 if (ins->inst_imm >= 32) {
2947 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2948 x86_clear_reg (code, ins->sreg1);
2949 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2951 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2952 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2956 if (ins->inst_imm >= 32) {
2957 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2958 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2959 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2961 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2962 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2965 case OP_LSHR_UN_IMM:
2966 if (ins->inst_imm >= 32) {
2967 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2968 x86_clear_reg (code, ins->backend.reg3);
2969 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2971 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2972 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2976 x86_not_reg (code, ins->sreg1);
2979 x86_neg_reg (code, ins->sreg1);
2983 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2987 switch (ins->inst_imm) {
2991 if (ins->dreg != ins->sreg1)
2992 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2993 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2996 /* LEA r1, [r2 + r2*2] */
2997 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3000 /* LEA r1, [r2 + r2*4] */
3001 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3004 /* LEA r1, [r2 + r2*2] */
3006 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3007 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3010 /* LEA r1, [r2 + r2*8] */
3011 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3014 /* LEA r1, [r2 + r2*4] */
3016 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3017 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3020 /* LEA r1, [r2 + r2*2] */
3022 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3023 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3026 /* LEA r1, [r2 + r2*4] */
3027 /* LEA r1, [r1 + r1*4] */
3028 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3029 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3032 /* LEA r1, [r2 + r2*4] */
3034 /* LEA r1, [r1 + r1*4] */
3035 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3036 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3037 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3040 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3045 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3046 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3048 case OP_IMUL_OVF_UN: {
3049 /* the mul operation and the exception check should most likely be split */
3050 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3051 /*g_assert (ins->sreg2 == X86_EAX);
3052 g_assert (ins->dreg == X86_EAX);*/
3053 if (ins->sreg2 == X86_EAX) {
3054 non_eax_reg = ins->sreg1;
3055 } else if (ins->sreg1 == X86_EAX) {
3056 non_eax_reg = ins->sreg2;
3058 /* no need to save since we're going to store to it anyway */
3059 if (ins->dreg != X86_EAX) {
3061 x86_push_reg (code, X86_EAX);
3063 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3064 non_eax_reg = ins->sreg2;
3066 if (ins->dreg == X86_EDX) {
3069 x86_push_reg (code, X86_EAX);
3071 } else if (ins->dreg != X86_EAX) {
3073 x86_push_reg (code, X86_EDX);
3075 x86_mul_reg (code, non_eax_reg, FALSE);
3076 /* save before the check since pop and mov don't change the flags */
3077 if (ins->dreg != X86_EAX)
3078 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3080 x86_pop_reg (code, X86_EDX);
3082 x86_pop_reg (code, X86_EAX);
3083 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3087 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3090 g_assert_not_reached ();
3091 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3092 x86_mov_reg_imm (code, ins->dreg, 0);
3095 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3096 x86_mov_reg_imm (code, ins->dreg, 0);
3098 case OP_LOAD_GOTADDR:
3099 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3100 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3103 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3104 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3106 case OP_X86_PUSH_GOT_ENTRY:
3107 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3108 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3111 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3115 * Note: this 'frame destruction' logic is useful for tail calls, too.
3116 * Keep in sync with the code in emit_epilog.
3120 /* FIXME: no tracing support... */
3121 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3122 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3123 /* reset offset to make max_len work */
3124 offset = code - cfg->native_code;
3126 g_assert (!cfg->method->save_lmf);
3128 code = emit_load_volatile_arguments (cfg, code);
3130 if (cfg->used_int_regs & (1 << X86_EBX))
3132 if (cfg->used_int_regs & (1 << X86_EDI))
3134 if (cfg->used_int_regs & (1 << X86_ESI))
3137 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
3139 if (cfg->used_int_regs & (1 << X86_ESI))
3140 x86_pop_reg (code, X86_ESI);
3141 if (cfg->used_int_regs & (1 << X86_EDI))
3142 x86_pop_reg (code, X86_EDI);
3143 if (cfg->used_int_regs & (1 << X86_EBX))
3144 x86_pop_reg (code, X86_EBX);
3146 /* restore ESP/EBP */
3148 offset = code - cfg->native_code;
3149 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3150 x86_jump32 (code, 0);
3152 cfg->disable_aot = TRUE;
3156 MonoCallInst *call = (MonoCallInst*)ins;
3159 ins->flags |= MONO_INST_GC_CALLSITE;
3160 ins->backend.pc_offset = code - cfg->native_code;
3162 /* FIXME: no tracing support... */
3163 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3164 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3165 /* reset offset to make max_len work */
3166 offset = code - cfg->native_code;
3168 g_assert (!cfg->method->save_lmf);
3170 //code = emit_load_volatile_arguments (cfg, code);
3172 /* restore callee saved registers */
3173 for (i = 0; i < X86_NREG; ++i)
3174 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3176 if (cfg->used_int_regs & (1 << X86_ESI)) {
3177 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3180 if (cfg->used_int_regs & (1 << X86_EDI)) {
3181 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3184 if (cfg->used_int_regs & (1 << X86_EBX)) {
3185 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3189 /* Copy arguments on the stack to our argument area */
3190 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3191 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3192 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3195 /* restore ESP/EBP */
3197 offset = code - cfg->native_code;
3198 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3199 x86_jump32 (code, 0);
3201 ins->flags |= MONO_INST_GC_CALLSITE;
3202 cfg->disable_aot = TRUE;
3206 /* ensure ins->sreg1 is not NULL
3207 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3208 * cmp DWORD PTR [eax], 0
3210 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3213 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3214 x86_push_reg (code, hreg);
3215 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3216 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3217 x86_pop_reg (code, hreg);
3226 call = (MonoCallInst*)ins;
3227 if (ins->flags & MONO_INST_HAS_METHOD)
3228 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3230 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3231 ins->flags |= MONO_INST_GC_CALLSITE;
3232 ins->backend.pc_offset = code - cfg->native_code;
3233 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3234 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
3235 * bytes to pop, we want to use pops. GCC does this (note it won't happen
3236 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
3237 * smart enough to do that optimization yet
3239 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
3240 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
3241 * (most likely from locality benefits). People with other processors should
3242 * check on theirs to see what happens.
3244 if (call->stack_usage == 4) {
3245 /* we want to use registers that won't get used soon, so use
3246 * ecx, as eax will get allocated first. edx is used by long calls,
3247 * so we can't use that.
3250 x86_pop_reg (code, X86_ECX);
3252 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3255 code = emit_move_return_value (cfg, ins, code);
3261 case OP_VOIDCALL_REG:
3263 call = (MonoCallInst*)ins;
3264 x86_call_reg (code, ins->sreg1);
3265 ins->flags |= MONO_INST_GC_CALLSITE;
3266 ins->backend.pc_offset = code - cfg->native_code;
3267 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3268 if (call->stack_usage == 4)
3269 x86_pop_reg (code, X86_ECX);
3271 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3273 code = emit_move_return_value (cfg, ins, code);
3275 case OP_FCALL_MEMBASE:
3276 case OP_LCALL_MEMBASE:
3277 case OP_VCALL_MEMBASE:
3278 case OP_VCALL2_MEMBASE:
3279 case OP_VOIDCALL_MEMBASE:
3280 case OP_CALL_MEMBASE:
3281 call = (MonoCallInst*)ins;
3283 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3284 ins->flags |= MONO_INST_GC_CALLSITE;
3285 ins->backend.pc_offset = code - cfg->native_code;
3286 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3287 if (call->stack_usage == 4)
3288 x86_pop_reg (code, X86_ECX);
3290 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3292 code = emit_move_return_value (cfg, ins, code);
3295 x86_push_reg (code, ins->sreg1);
3297 case OP_X86_PUSH_IMM:
3298 x86_push_imm (code, ins->inst_imm);
3300 case OP_X86_PUSH_MEMBASE:
3301 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
3303 case OP_X86_PUSH_OBJ:
3304 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
3305 x86_push_reg (code, X86_EDI);
3306 x86_push_reg (code, X86_ESI);
3307 x86_push_reg (code, X86_ECX);
3308 if (ins->inst_offset)
3309 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
3311 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
3312 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
3313 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
3315 x86_prefix (code, X86_REP_PREFIX);
3317 x86_pop_reg (code, X86_ECX);
3318 x86_pop_reg (code, X86_ESI);
3319 x86_pop_reg (code, X86_EDI);
3322 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3324 case OP_X86_LEA_MEMBASE:
3325 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3328 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3331 /* keep alignment */
3332 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3333 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3334 code = mono_emit_stack_alloc (code, ins);
3335 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3337 case OP_LOCALLOC_IMM: {
3338 guint32 size = ins->inst_imm;
3339 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3341 if (ins->flags & MONO_INST_INIT) {
3342 /* FIXME: Optimize this */
3343 x86_mov_reg_imm (code, ins->dreg, size);
3344 ins->sreg1 = ins->dreg;
3346 code = mono_emit_stack_alloc (code, ins);
3347 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3349 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3350 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3355 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3356 x86_push_reg (code, ins->sreg1);
3357 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3358 (gpointer)"mono_arch_throw_exception");
3359 ins->flags |= MONO_INST_GC_CALLSITE;
3360 ins->backend.pc_offset = code - cfg->native_code;
3364 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3365 x86_push_reg (code, ins->sreg1);
3366 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3367 (gpointer)"mono_arch_rethrow_exception");
3368 ins->flags |= MONO_INST_GC_CALLSITE;
3369 ins->backend.pc_offset = code - cfg->native_code;
3372 case OP_CALL_HANDLER:
3373 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3374 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3375 x86_call_imm (code, 0);
3376 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3377 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3379 case OP_START_HANDLER: {
3380 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3381 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3384 case OP_ENDFINALLY: {
3385 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3386 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3390 case OP_ENDFILTER: {
3391 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3392 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3393 /* The local allocator will put the result into EAX */
3399 ins->inst_c0 = code - cfg->native_code;
3402 if (ins->inst_target_bb->native_offset) {
3403 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3405 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3406 if ((cfg->opt & MONO_OPT_BRANCH) &&
3407 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3408 x86_jump8 (code, 0);
3410 x86_jump32 (code, 0);
3414 x86_jump_reg (code, ins->sreg1);
3427 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3428 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3430 case OP_COND_EXC_EQ:
3431 case OP_COND_EXC_NE_UN:
3432 case OP_COND_EXC_LT:
3433 case OP_COND_EXC_LT_UN:
3434 case OP_COND_EXC_GT:
3435 case OP_COND_EXC_GT_UN:
3436 case OP_COND_EXC_GE:
3437 case OP_COND_EXC_GE_UN:
3438 case OP_COND_EXC_LE:
3439 case OP_COND_EXC_LE_UN:
3440 case OP_COND_EXC_IEQ:
3441 case OP_COND_EXC_INE_UN:
3442 case OP_COND_EXC_ILT:
3443 case OP_COND_EXC_ILT_UN:
3444 case OP_COND_EXC_IGT:
3445 case OP_COND_EXC_IGT_UN:
3446 case OP_COND_EXC_IGE:
3447 case OP_COND_EXC_IGE_UN:
3448 case OP_COND_EXC_ILE:
3449 case OP_COND_EXC_ILE_UN:
3450 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3452 case OP_COND_EXC_OV:
3453 case OP_COND_EXC_NO:
3455 case OP_COND_EXC_NC:
3456 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3458 case OP_COND_EXC_IOV:
3459 case OP_COND_EXC_INO:
3460 case OP_COND_EXC_IC:
3461 case OP_COND_EXC_INC:
3462 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3474 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3482 case OP_CMOV_INE_UN:
3483 case OP_CMOV_IGE_UN:
3484 case OP_CMOV_IGT_UN:
3485 case OP_CMOV_ILE_UN:
3486 case OP_CMOV_ILT_UN:
3487 g_assert (ins->dreg == ins->sreg1);
3488 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3491 /* floating point opcodes */
3493 double d = *(double *)ins->inst_p0;
3495 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3497 } else if (d == 1.0) {
3500 if (cfg->compile_aot) {
3501 guint32 *val = (guint32*)&d;
3502 x86_push_imm (code, val [1]);
3503 x86_push_imm (code, val [0]);
3504 x86_fld_membase (code, X86_ESP, 0, TRUE);
3505 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3508 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3509 x86_fld (code, NULL, TRUE);
3515 float f = *(float *)ins->inst_p0;
3517 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3519 } else if (f == 1.0) {
3522 if (cfg->compile_aot) {
3523 guint32 val = *(guint32*)&f;
3524 x86_push_imm (code, val);
3525 x86_fld_membase (code, X86_ESP, 0, FALSE);
3526 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3529 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3530 x86_fld (code, NULL, FALSE);
3535 case OP_STORER8_MEMBASE_REG:
3536 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3538 case OP_LOADR8_MEMBASE:
3539 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3541 case OP_STORER4_MEMBASE_REG:
3542 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3544 case OP_LOADR4_MEMBASE:
3545 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3547 case OP_ICONV_TO_R4:
3548 x86_push_reg (code, ins->sreg1);
3549 x86_fild_membase (code, X86_ESP, 0, FALSE);
3550 /* Change precision */
3551 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3552 x86_fld_membase (code, X86_ESP, 0, FALSE);
3553 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3555 case OP_ICONV_TO_R8:
3556 x86_push_reg (code, ins->sreg1);
3557 x86_fild_membase (code, X86_ESP, 0, FALSE);
3558 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3560 case OP_ICONV_TO_R_UN:
3561 x86_push_imm (code, 0);
3562 x86_push_reg (code, ins->sreg1);
3563 x86_fild_membase (code, X86_ESP, 0, TRUE);
3564 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3566 case OP_X86_FP_LOAD_I8:
3567 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3569 case OP_X86_FP_LOAD_I4:
3570 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3572 case OP_FCONV_TO_R4:
3573 /* Change precision */
3574 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3575 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3576 x86_fld_membase (code, X86_ESP, 0, FALSE);
3577 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3579 case OP_FCONV_TO_I1:
3580 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3582 case OP_FCONV_TO_U1:
3583 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3585 case OP_FCONV_TO_I2:
3586 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3588 case OP_FCONV_TO_U2:
3589 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3591 case OP_FCONV_TO_I4:
3593 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3595 case OP_FCONV_TO_I8:
3596 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3597 x86_fnstcw_membase(code, X86_ESP, 0);
3598 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3599 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3600 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3601 x86_fldcw_membase (code, X86_ESP, 2);
3602 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3603 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3604 x86_pop_reg (code, ins->dreg);
3605 x86_pop_reg (code, ins->backend.reg3);
3606 x86_fldcw_membase (code, X86_ESP, 0);
3607 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3609 case OP_LCONV_TO_R8_2:
3610 x86_push_reg (code, ins->sreg2);
3611 x86_push_reg (code, ins->sreg1);
3612 x86_fild_membase (code, X86_ESP, 0, TRUE);
3613 /* Change precision */
3614 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3615 x86_fld_membase (code, X86_ESP, 0, TRUE);
3616 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3618 case OP_LCONV_TO_R4_2:
3619 x86_push_reg (code, ins->sreg2);
3620 x86_push_reg (code, ins->sreg1);
3621 x86_fild_membase (code, X86_ESP, 0, TRUE);
3622 /* Change precision */
3623 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3624 x86_fld_membase (code, X86_ESP, 0, FALSE);
3625 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3627 case OP_LCONV_TO_R_UN_2: {
3628 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3631 /* load 64bit integer to FP stack */
3632 x86_push_reg (code, ins->sreg2);
3633 x86_push_reg (code, ins->sreg1);
3634 x86_fild_membase (code, X86_ESP, 0, TRUE);
3636 /* test if lreg is negative */
3637 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3638 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3640 /* add correction constant mn */
3641 if (cfg->compile_aot) {
3642 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3643 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3644 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3645 x86_fld80_membase (code, X86_ESP, 2);
3646 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3648 x86_fld80_mem (code, mn);
3650 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3652 x86_patch (br, code);
3654 /* Change precision */
3655 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3656 x86_fld_membase (code, X86_ESP, 0, TRUE);
3658 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3662 case OP_LCONV_TO_OVF_I:
3663 case OP_LCONV_TO_OVF_I4_2: {
3664 guint8 *br [3], *label [1];
3668 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3670 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3672 /* If the low word top bit is set, see if we are negative */
3673 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3674 /* We are not negative (no top bit set, check for our top word to be zero */
3675 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3676 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3679 /* throw exception */
3680 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3682 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3683 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3684 x86_jump8 (code, 0);
3686 x86_jump32 (code, 0);
3688 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3689 x86_jump32 (code, 0);
3693 x86_patch (br [0], code);
3694 /* our top bit is set, check that top word is 0xfffffff */
3695 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3697 x86_patch (br [1], code);
3698 /* nope, emit exception */
3699 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3700 x86_patch (br [2], label [0]);
3702 if (ins->dreg != ins->sreg1)
3703 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3707 /* Not needed on the fp stack */
3710 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3713 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3716 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3719 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3727 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3732 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3739 * it really doesn't make sense to inline all this code,
3740 * it's here just to show that things may not be as simple
3743 guchar *check_pos, *end_tan, *pop_jump;
3744 x86_push_reg (code, X86_EAX);
3747 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3749 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3750 x86_fstp (code, 0); /* pop the 1.0 */
3752 x86_jump8 (code, 0);
3754 x86_fp_op (code, X86_FADD, 0);
3758 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3760 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3763 x86_patch (pop_jump, code);
3764 x86_fstp (code, 0); /* pop the 1.0 */
3765 x86_patch (check_pos, code);
3766 x86_patch (end_tan, code);
3768 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3769 x86_pop_reg (code, X86_EAX);
3776 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3785 g_assert (cfg->opt & MONO_OPT_CMOV);
3786 g_assert (ins->dreg == ins->sreg1);
3787 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3788 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3791 g_assert (cfg->opt & MONO_OPT_CMOV);
3792 g_assert (ins->dreg == ins->sreg1);
3793 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3794 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3797 g_assert (cfg->opt & MONO_OPT_CMOV);
3798 g_assert (ins->dreg == ins->sreg1);
3799 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3800 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3803 g_assert (cfg->opt & MONO_OPT_CMOV);
3804 g_assert (ins->dreg == ins->sreg1);
3805 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3806 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3812 x86_fxch (code, ins->inst_imm);
3817 x86_push_reg (code, X86_EAX);
3818 /* we need to exchange ST(0) with ST(1) */
3821 /* this requires a loop, because fprem somtimes
3822 * returns a partial remainder */
3824 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3825 /* x86_fprem1 (code); */
3828 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3830 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3836 x86_pop_reg (code, X86_EAX);
3840 if (cfg->opt & MONO_OPT_FCMOV) {
3841 x86_fcomip (code, 1);
3845 /* this overwrites EAX */
3846 EMIT_FPCOMPARE(code);
3847 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3850 if (cfg->opt & MONO_OPT_FCMOV) {
3851 /* zeroing the register at the start results in
3852 * shorter and faster code (we can also remove the widening op)
3854 guchar *unordered_check;
3855 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3856 x86_fcomip (code, 1);
3858 unordered_check = code;
3859 x86_branch8 (code, X86_CC_P, 0, FALSE);
3860 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3861 x86_patch (unordered_check, code);
3864 if (ins->dreg != X86_EAX)
3865 x86_push_reg (code, X86_EAX);
3867 EMIT_FPCOMPARE(code);
3868 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3869 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3870 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3871 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3873 if (ins->dreg != X86_EAX)
3874 x86_pop_reg (code, X86_EAX);
3878 if (cfg->opt & MONO_OPT_FCMOV) {
3879 /* zeroing the register at the start results in
3880 * shorter and faster code (we can also remove the widening op)
3882 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3883 x86_fcomip (code, 1);
3885 if (ins->opcode == OP_FCLT_UN) {
3886 guchar *unordered_check = code;
3887 guchar *jump_to_end;
3888 x86_branch8 (code, X86_CC_P, 0, FALSE);
3889 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3891 x86_jump8 (code, 0);
3892 x86_patch (unordered_check, code);
3893 x86_inc_reg (code, ins->dreg);
3894 x86_patch (jump_to_end, code);
3896 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3900 if (ins->dreg != X86_EAX)
3901 x86_push_reg (code, X86_EAX);
3903 EMIT_FPCOMPARE(code);
3904 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3905 if (ins->opcode == OP_FCLT_UN) {
3906 guchar *is_not_zero_check, *end_jump;
3907 is_not_zero_check = code;
3908 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3910 x86_jump8 (code, 0);
3911 x86_patch (is_not_zero_check, code);
3912 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3914 x86_patch (end_jump, code);
3916 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3917 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3919 if (ins->dreg != X86_EAX)
3920 x86_pop_reg (code, X86_EAX);
3924 if (cfg->opt & MONO_OPT_FCMOV) {
3925 /* zeroing the register at the start results in
3926 * shorter and faster code (we can also remove the widening op)
3928 guchar *unordered_check;
3929 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3930 x86_fcomip (code, 1);
3932 if (ins->opcode == OP_FCGT) {
3933 unordered_check = code;
3934 x86_branch8 (code, X86_CC_P, 0, FALSE);
3935 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3936 x86_patch (unordered_check, code);
3938 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3942 if (ins->dreg != X86_EAX)
3943 x86_push_reg (code, X86_EAX);
3945 EMIT_FPCOMPARE(code);
3946 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3947 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3948 if (ins->opcode == OP_FCGT_UN) {
3949 guchar *is_not_zero_check, *end_jump;
3950 is_not_zero_check = code;
3951 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3953 x86_jump8 (code, 0);
3954 x86_patch (is_not_zero_check, code);
3955 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3957 x86_patch (end_jump, code);
3959 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3960 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3962 if (ins->dreg != X86_EAX)
3963 x86_pop_reg (code, X86_EAX);
3966 if (cfg->opt & MONO_OPT_FCMOV) {
3967 guchar *jump = code;
3968 x86_branch8 (code, X86_CC_P, 0, TRUE);
3969 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3970 x86_patch (jump, code);
3973 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3974 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3977 /* Branch if C013 != 100 */
3978 if (cfg->opt & MONO_OPT_FCMOV) {
3979 /* branch if !ZF or (PF|CF) */
3980 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3981 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3982 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3985 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3986 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3989 if (cfg->opt & MONO_OPT_FCMOV) {
3990 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3993 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3996 if (cfg->opt & MONO_OPT_FCMOV) {
3997 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3998 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4001 if (ins->opcode == OP_FBLT_UN) {
4002 guchar *is_not_zero_check, *end_jump;
4003 is_not_zero_check = code;
4004 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4006 x86_jump8 (code, 0);
4007 x86_patch (is_not_zero_check, code);
4008 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4010 x86_patch (end_jump, code);
4012 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4016 if (cfg->opt & MONO_OPT_FCMOV) {
4017 if (ins->opcode == OP_FBGT) {
4020 /* skip branch if C1=1 */
4022 x86_branch8 (code, X86_CC_P, 0, FALSE);
4023 /* branch if (C0 | C3) = 1 */
4024 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4025 x86_patch (br1, code);
4027 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4031 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4032 if (ins->opcode == OP_FBGT_UN) {
4033 guchar *is_not_zero_check, *end_jump;
4034 is_not_zero_check = code;
4035 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4037 x86_jump8 (code, 0);
4038 x86_patch (is_not_zero_check, code);
4039 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4041 x86_patch (end_jump, code);
4043 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4046 /* Branch if C013 == 100 or 001 */
4047 if (cfg->opt & MONO_OPT_FCMOV) {
4050 /* skip branch if C1=1 */
4052 x86_branch8 (code, X86_CC_P, 0, FALSE);
4053 /* branch if (C0 | C3) = 1 */
4054 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4055 x86_patch (br1, code);
4058 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4059 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4060 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4061 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4064 /* Branch if C013 == 000 */
4065 if (cfg->opt & MONO_OPT_FCMOV) {
4066 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4069 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4072 /* Branch if C013=000 or 100 */
4073 if (cfg->opt & MONO_OPT_FCMOV) {
4076 /* skip branch if C1=1 */
4078 x86_branch8 (code, X86_CC_P, 0, FALSE);
4079 /* branch if C0=0 */
4080 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4081 x86_patch (br1, code);
4084 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4085 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4086 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4089 /* Branch if C013 != 001 */
4090 if (cfg->opt & MONO_OPT_FCMOV) {
4091 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4092 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4095 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4096 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4100 x86_push_reg (code, X86_EAX);
4103 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4104 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4105 x86_pop_reg (code, X86_EAX);
4107 /* Have to clean up the fp stack before throwing the exception */
4109 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4112 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4114 x86_patch (br1, code);
4118 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4121 case OP_TLS_GET_REG: {
4123 // FIXME: tls_gs_offset can change too, do these when calculating the tls offset
4124 if (ins->dreg != ins->sreg1)
4125 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
4126 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4128 x86_alu_reg_imm (code, X86_ADD, ins->dreg, tls_gs_offset);
4129 x86_prefix (code, X86_GS_PREFIX);
4130 x86_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof (gpointer));
4132 g_assert_not_reached ();
4136 case OP_MEMORY_BARRIER: {
4137 /* x86 only needs barrier for StoreLoad and FullBarrier */
4138 switch (ins->backend.memory_barrier_kind) {
4139 case StoreLoadBarrier:
4141 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4142 x86_prefix (code, X86_LOCK_PREFIX);
4143 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4148 case OP_ATOMIC_ADD_I4: {
4149 int dreg = ins->dreg;
4151 if (dreg == ins->inst_basereg) {
4152 x86_push_reg (code, ins->sreg2);
4156 if (dreg != ins->sreg2)
4157 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
4159 x86_prefix (code, X86_LOCK_PREFIX);
4160 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4162 if (dreg != ins->dreg) {
4163 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4164 x86_pop_reg (code, dreg);
4169 case OP_ATOMIC_ADD_NEW_I4: {
4170 int dreg = ins->dreg;
4172 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4173 if (ins->sreg2 == dreg) {
4174 if (dreg == X86_EBX) {
4176 if (ins->inst_basereg == X86_EDI)
4180 if (ins->inst_basereg == X86_EBX)
4183 } else if (ins->inst_basereg == dreg) {
4184 if (dreg == X86_EBX) {
4186 if (ins->sreg2 == X86_EDI)
4190 if (ins->sreg2 == X86_EBX)
4195 if (dreg != ins->dreg) {
4196 x86_push_reg (code, dreg);
4199 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4200 x86_prefix (code, X86_LOCK_PREFIX);
4201 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4202 /* dreg contains the old value, add with sreg2 value */
4203 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4205 if (ins->dreg != dreg) {
4206 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4207 x86_pop_reg (code, dreg);
4212 case OP_ATOMIC_EXCHANGE_I4: {
4214 int sreg2 = ins->sreg2;
4215 int breg = ins->inst_basereg;
4217 /* cmpxchg uses eax as comperand, need to make sure we can use it
4218 * hack to overcome limits in x86 reg allocator
4219 * (req: dreg == eax and sreg2 != eax and breg != eax)
4221 g_assert (ins->dreg == X86_EAX);
4223 /* We need the EAX reg for the cmpxchg */
4224 if (ins->sreg2 == X86_EAX) {
4225 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4226 x86_push_reg (code, sreg2);
4227 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4230 if (breg == X86_EAX) {
4231 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4232 x86_push_reg (code, breg);
4233 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4236 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4238 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4239 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4240 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4241 x86_patch (br [1], br [0]);
4243 if (breg != ins->inst_basereg)
4244 x86_pop_reg (code, breg);
4246 if (ins->sreg2 != sreg2)
4247 x86_pop_reg (code, sreg2);
4251 case OP_ATOMIC_CAS_I4: {
4252 g_assert (ins->dreg == X86_EAX);
4253 g_assert (ins->sreg3 == X86_EAX);
4254 g_assert (ins->sreg1 != X86_EAX);
4255 g_assert (ins->sreg1 != ins->sreg2);
4257 x86_prefix (code, X86_LOCK_PREFIX);
4258 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4261 case OP_CARD_TABLE_WBARRIER: {
4262 int ptr = ins->sreg1;
4263 int value = ins->sreg2;
4265 int nursery_shift, card_table_shift;
4266 gpointer card_table_mask;
4267 size_t nursery_size;
4268 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4269 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4270 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4273 * We need one register we can clobber, we choose EDX and make sreg1
4274 * fixed EAX to work around limitations in the local register allocator.
4275 * sreg2 might get allocated to EDX, but that is not a problem since
4276 * we use it before clobbering EDX.
4278 g_assert (ins->sreg1 == X86_EAX);
4281 * This is the code we produce:
4284 * edx >>= nursery_shift
4285 * cmp edx, (nursery_start >> nursery_shift)
4288 * edx >>= card_table_shift
4289 * card_table[edx] = 1
4293 if (card_table_nursery_check) {
4294 if (value != X86_EDX)
4295 x86_mov_reg_reg (code, X86_EDX, value, 4);
4296 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4297 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4298 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4300 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4301 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4302 if (card_table_mask)
4303 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4304 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4305 if (card_table_nursery_check)
4306 x86_patch (br, code);
4309 #ifdef MONO_ARCH_SIMD_INTRINSICS
4311 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4314 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4317 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4320 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4323 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4326 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4329 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4330 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4333 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4336 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4339 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4342 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4345 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4348 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4351 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4354 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4357 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4360 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4363 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4366 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4369 case OP_PSHUFLEW_HIGH:
4370 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4371 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4373 case OP_PSHUFLEW_LOW:
4374 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4375 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4378 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4379 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4382 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4383 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4386 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4387 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4391 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4394 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4397 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4400 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4403 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4406 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4409 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4410 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4413 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4416 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4419 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4422 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4425 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4428 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4431 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4434 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4437 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4440 case OP_EXTRACT_MASK:
4441 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4445 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4448 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4451 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4455 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4458 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4461 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4464 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4468 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4471 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4474 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4477 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4481 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4484 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4487 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4491 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4494 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4497 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4501 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4504 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4508 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4511 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4514 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4518 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4521 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4524 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4528 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4531 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4534 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4537 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4541 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4544 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4547 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4550 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4553 case OP_PSUM_ABS_DIFF:
4554 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4557 case OP_UNPACK_LOWB:
4558 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4560 case OP_UNPACK_LOWW:
4561 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4563 case OP_UNPACK_LOWD:
4564 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4566 case OP_UNPACK_LOWQ:
4567 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4569 case OP_UNPACK_LOWPS:
4570 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4572 case OP_UNPACK_LOWPD:
4573 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4576 case OP_UNPACK_HIGHB:
4577 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4579 case OP_UNPACK_HIGHW:
4580 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4582 case OP_UNPACK_HIGHD:
4583 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4585 case OP_UNPACK_HIGHQ:
4586 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4588 case OP_UNPACK_HIGHPS:
4589 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4591 case OP_UNPACK_HIGHPD:
4592 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4596 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4599 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4602 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4605 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4608 case OP_PADDB_SAT_UN:
4609 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4611 case OP_PSUBB_SAT_UN:
4612 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4614 case OP_PADDW_SAT_UN:
4615 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4617 case OP_PSUBW_SAT_UN:
4618 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4622 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4625 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4628 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4631 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4635 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4638 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4641 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4643 case OP_PMULW_HIGH_UN:
4644 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4647 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4651 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4654 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4658 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4661 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4665 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4668 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4672 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4675 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4679 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4682 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4686 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4689 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4693 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4696 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4700 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4703 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4707 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4710 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4714 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4716 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4717 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4721 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4723 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4724 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4728 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4730 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4731 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4735 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4737 case OP_EXTRACTX_U2:
4738 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4740 case OP_INSERTX_U1_SLOW:
4741 /*sreg1 is the extracted ireg (scratch)
4742 /sreg2 is the to be inserted ireg (scratch)
4743 /dreg is the xreg to receive the value*/
4745 /*clear the bits from the extracted word*/
4746 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4747 /*shift the value to insert if needed*/
4748 if (ins->inst_c0 & 1)
4749 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4750 /*join them together*/
4751 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4752 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4754 case OP_INSERTX_I4_SLOW:
4755 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4756 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4757 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4760 case OP_INSERTX_R4_SLOW:
4761 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4762 /*TODO if inst_c0 == 0 use movss*/
4763 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4764 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4766 case OP_INSERTX_R8_SLOW:
4767 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4768 if (cfg->verbose_level)
4769 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4771 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4773 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4776 case OP_STOREX_MEMBASE_REG:
4777 case OP_STOREX_MEMBASE:
4778 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4780 case OP_LOADX_MEMBASE:
4781 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4783 case OP_LOADX_ALIGNED_MEMBASE:
4784 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4786 case OP_STOREX_ALIGNED_MEMBASE_REG:
4787 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4789 case OP_STOREX_NTA_MEMBASE_REG:
4790 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4792 case OP_PREFETCH_MEMBASE:
4793 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4797 /*FIXME the peephole pass should have killed this*/
4798 if (ins->dreg != ins->sreg1)
4799 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4802 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4804 case OP_ICONV_TO_R8_RAW:
4805 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4806 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4809 case OP_FCONV_TO_R8_X:
4810 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4811 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4814 case OP_XCONV_R8_TO_I4:
4815 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4816 switch (ins->backend.source_opcode) {
4817 case OP_FCONV_TO_I1:
4818 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4820 case OP_FCONV_TO_U1:
4821 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4823 case OP_FCONV_TO_I2:
4824 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4826 case OP_FCONV_TO_U2:
4827 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4833 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4834 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4835 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4836 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4837 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4838 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4841 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4842 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4843 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4846 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4847 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4850 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4851 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4852 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4855 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4856 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4857 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4861 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4864 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4867 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4870 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4873 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4876 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4879 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4882 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4886 case OP_LIVERANGE_START: {
4887 if (cfg->verbose_level > 1)
4888 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4889 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4892 case OP_LIVERANGE_END: {
4893 if (cfg->verbose_level > 1)
4894 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4895 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4898 case OP_NACL_GC_SAFE_POINT: {
4899 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
4900 if (cfg->compile_aot)
4901 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
4905 x86_test_mem_imm8 (code, (gpointer)&__nacl_thread_suspension_needed, 0xFFFFFFFF);
4906 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4907 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
4908 x86_patch (br[0], code);
4913 case OP_GC_LIVENESS_DEF:
4914 case OP_GC_LIVENESS_USE:
4915 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4916 ins->backend.pc_offset = code - cfg->native_code;
4918 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4919 ins->backend.pc_offset = code - cfg->native_code;
4920 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4923 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4924 g_assert_not_reached ();
4927 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4928 #ifndef __native_client_codegen__
4929 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4930 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4931 g_assert_not_reached ();
4932 #endif /* __native_client_codegen__ */
4938 cfg->code_len = code - cfg->native_code;
4941 #endif /* DISABLE_JIT */
4944 mono_arch_register_lowlevel_calls (void)
4949 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4951 MonoJumpInfo *patch_info;
4952 gboolean compile_aot = !run_cctors;
4954 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4955 unsigned char *ip = patch_info->ip.i + code;
4956 const unsigned char *target;
4959 switch (patch_info->type) {
4960 case MONO_PATCH_INFO_BB:
4961 case MONO_PATCH_INFO_LABEL:
4964 /* No need to patch these */
4969 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4971 switch (patch_info->type) {
4972 case MONO_PATCH_INFO_IP:
4973 *((gconstpointer *)(ip)) = target;
4975 case MONO_PATCH_INFO_CLASS_INIT: {
4977 /* Might already been changed to a nop */
4978 x86_call_code (code, 0);
4979 x86_patch (ip, target);
4982 case MONO_PATCH_INFO_ABS:
4983 case MONO_PATCH_INFO_METHOD:
4984 case MONO_PATCH_INFO_METHOD_JUMP:
4985 case MONO_PATCH_INFO_INTERNAL_METHOD:
4986 case MONO_PATCH_INFO_BB:
4987 case MONO_PATCH_INFO_LABEL:
4988 case MONO_PATCH_INFO_RGCTX_FETCH:
4989 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
4990 case MONO_PATCH_INFO_MONITOR_ENTER:
4991 case MONO_PATCH_INFO_MONITOR_EXIT:
4992 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
4993 #if defined(__native_client_codegen__) && defined(__native_client__)
4994 if (nacl_is_code_address (code)) {
4995 /* For tail calls, code is patched after being installed */
4996 /* but not through the normal "patch callsite" method. */
4997 unsigned char buf[kNaClAlignment];
4998 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
4999 unsigned char *_target = target;
5001 /* All patch targets modified in x86_patch */
5002 /* are IP relative. */
5003 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5004 memcpy (buf, aligned_code, kNaClAlignment);
5005 /* Patch a temp buffer of bundle size, */
5006 /* then install to actual location. */
5007 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5008 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5009 g_assert (ret == 0);
5012 x86_patch (ip, target);
5015 x86_patch (ip, target);
5018 case MONO_PATCH_INFO_NONE:
5020 case MONO_PATCH_INFO_R4:
5021 case MONO_PATCH_INFO_R8: {
5022 guint32 offset = mono_arch_get_patch_offset (ip);
5023 *((gconstpointer *)(ip + offset)) = target;
5027 guint32 offset = mono_arch_get_patch_offset (ip);
5028 #if !defined(__native_client__)
5029 *((gconstpointer *)(ip + offset)) = target;
5031 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5039 static G_GNUC_UNUSED void
5040 stack_unaligned (MonoMethod *m, gpointer caller)
5042 printf ("%s\n", mono_method_full_name (m, TRUE));
5043 g_assert_not_reached ();
5047 mono_arch_emit_prolog (MonoCompile *cfg)
5049 MonoMethod *method = cfg->method;
5051 MonoMethodSignature *sig;
5053 int alloc_size, pos, max_offset, i, cfa_offset;
5055 gboolean need_stack_frame;
5056 #ifdef __native_client_codegen__
5057 guint alignment_check;
5060 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5062 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5063 cfg->code_size += 512;
5065 #if defined(__default_codegen__)
5066 code = cfg->native_code = g_malloc (cfg->code_size);
5067 #elif defined(__native_client_codegen__)
5068 /* native_code_alloc is not 32-byte aligned, native_code is. */
5069 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5070 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5072 /* Align native_code to next nearest kNaclAlignment byte. */
5073 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5074 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5076 code = cfg->native_code;
5078 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5079 g_assert(alignment_check == 0);
5086 /* Check that the stack is aligned on osx */
5087 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5088 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5089 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5091 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5092 x86_push_membase (code, X86_ESP, 0);
5093 x86_push_imm (code, cfg->method);
5094 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5095 x86_call_reg (code, X86_EAX);
5096 x86_patch (br [0], code);
5100 /* Offset between RSP and the CFA */
5104 cfa_offset = sizeof (gpointer);
5105 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5106 // IP saved at CFA - 4
5107 /* There is no IP reg on x86 */
5108 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5109 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5111 need_stack_frame = needs_stack_frame (cfg);
5113 if (need_stack_frame) {
5114 x86_push_reg (code, X86_EBP);
5115 cfa_offset += sizeof (gpointer);
5116 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5117 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5118 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5119 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5120 /* These are handled automatically by the stack marking code */
5121 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5123 cfg->frame_reg = X86_ESP;
5126 alloc_size = cfg->stack_offset;
5129 if (method->save_lmf) {
5130 pos += sizeof (MonoLMF);
5132 /* save the current IP */
5133 if (cfg->compile_aot) {
5134 /* This pushes the current ip */
5135 x86_call_imm (code, 0);
5137 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
5138 x86_push_imm_template (code);
5140 cfa_offset += sizeof (gpointer);
5141 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5143 /* save all caller saved regs */
5144 x86_push_reg (code, X86_EBP);
5145 cfa_offset += sizeof (gpointer);
5146 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5147 x86_push_reg (code, X86_ESI);
5148 cfa_offset += sizeof (gpointer);
5149 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5150 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5151 x86_push_reg (code, X86_EDI);
5152 cfa_offset += sizeof (gpointer);
5153 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5154 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5155 x86_push_reg (code, X86_EBX);
5156 cfa_offset += sizeof (gpointer);
5157 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5158 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5160 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5162 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5163 * through the mono_lmf_addr TLS variable.
5165 /* %eax = previous_lmf */
5166 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_tls_offset);
5167 /* skip esp + method_info + lmf */
5168 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 12);
5170 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5171 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + 4, SLOT_NOREF);
5172 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + 8, SLOT_NOREF);
5173 /* push previous_lmf */
5174 x86_push_reg (code, X86_EAX);
5176 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5178 code = mono_x86_emit_tls_set (code, X86_ESP, lmf_tls_offset);
5180 /* get the address of lmf for the current thread */
5182 * This is performance critical so we try to use some tricks to make
5185 gboolean have_fastpath = FALSE;
5188 if (jit_tls_offset != -1) {
5189 code = mono_x86_emit_tls_get (code, X86_EAX, jit_tls_offset);
5190 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5191 have_fastpath = TRUE;
5194 if (lmf_addr_tls_offset != -1) {
5195 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
5196 have_fastpath = TRUE;
5199 if (!have_fastpath) {
5200 if (cfg->compile_aot)
5201 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
5202 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
5205 /* Skip esp + method info */
5206 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
5209 x86_push_reg (code, X86_EAX);
5210 /* push *lfm (previous_lmf) */
5211 x86_push_membase (code, X86_EAX, 0);
5213 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
5217 if (cfg->used_int_regs & (1 << X86_EBX)) {
5218 x86_push_reg (code, X86_EBX);
5220 cfa_offset += sizeof (gpointer);
5221 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5222 /* These are handled automatically by the stack marking code */
5223 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5226 if (cfg->used_int_regs & (1 << X86_EDI)) {
5227 x86_push_reg (code, X86_EDI);
5229 cfa_offset += sizeof (gpointer);
5230 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5231 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5234 if (cfg->used_int_regs & (1 << X86_ESI)) {
5235 x86_push_reg (code, X86_ESI);
5237 cfa_offset += sizeof (gpointer);
5238 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5239 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5245 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5246 if (mono_do_x86_stack_align && need_stack_frame) {
5247 int tot = alloc_size + pos + 4; /* ret ip */
5248 if (need_stack_frame)
5250 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5252 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5253 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5254 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5258 cfg->arch.sp_fp_offset = alloc_size + pos;
5261 /* See mono_emit_stack_alloc */
5262 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5263 guint32 remaining_size = alloc_size;
5264 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5265 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5266 guint32 offset = code - cfg->native_code;
5267 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5268 while (required_code_size >= (cfg->code_size - offset))
5269 cfg->code_size *= 2;
5270 cfg->native_code = mono_realloc_native_code(cfg);
5271 code = cfg->native_code + offset;
5272 cfg->stat_code_reallocs++;
5274 while (remaining_size >= 0x1000) {
5275 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5276 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5277 remaining_size -= 0x1000;
5280 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5282 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5285 g_assert (need_stack_frame);
5288 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5289 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5290 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5293 #if DEBUG_STACK_ALIGNMENT
5294 /* check the stack is aligned */
5295 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5296 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5297 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5298 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5299 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5300 x86_breakpoint (code);
5304 /* compute max_offset in order to use short forward jumps */
5306 if (cfg->opt & MONO_OPT_BRANCH) {
5307 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5309 bb->max_offset = max_offset;
5311 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5313 /* max alignment for loops */
5314 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5315 max_offset += LOOP_ALIGNMENT;
5316 #ifdef __native_client_codegen__
5317 /* max alignment for native client */
5318 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5319 max_offset += kNaClAlignment;
5321 MONO_BB_FOR_EACH_INS (bb, ins) {
5322 if (ins->opcode == OP_LABEL)
5323 ins->inst_c1 = max_offset;
5324 #ifdef __native_client_codegen__
5325 switch (ins->opcode)
5337 case OP_VOIDCALL_REG:
5339 case OP_FCALL_MEMBASE:
5340 case OP_LCALL_MEMBASE:
5341 case OP_VCALL_MEMBASE:
5342 case OP_VCALL2_MEMBASE:
5343 case OP_VOIDCALL_MEMBASE:
5344 case OP_CALL_MEMBASE:
5345 max_offset += kNaClAlignment;
5348 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5351 #endif /* __native_client_codegen__ */
5352 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5357 /* store runtime generic context */
5358 if (cfg->rgctx_var) {
5359 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5361 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5364 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5365 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5367 /* load arguments allocated to register from the stack */
5368 sig = mono_method_signature (method);
5371 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5372 inst = cfg->args [pos];
5373 if (inst->opcode == OP_REGVAR) {
5374 g_assert (need_stack_frame);
5375 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5376 if (cfg->verbose_level > 2)
5377 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5382 cfg->code_len = code - cfg->native_code;
5384 g_assert (cfg->code_len < cfg->code_size);
5390 mono_arch_emit_epilog (MonoCompile *cfg)
5392 MonoMethod *method = cfg->method;
5393 MonoMethodSignature *sig = mono_method_signature (method);
5395 guint32 stack_to_pop;
5397 int max_epilog_size = 16;
5399 gboolean need_stack_frame = needs_stack_frame (cfg);
5401 if (cfg->method->save_lmf)
5402 max_epilog_size += 128;
5404 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5405 cfg->code_size *= 2;
5406 cfg->native_code = mono_realloc_native_code(cfg);
5407 cfg->stat_code_reallocs++;
5410 code = cfg->native_code + cfg->code_len;
5412 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5413 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5415 /* the code restoring the registers must be kept in sync with OP_JMP */
5418 if (method->save_lmf) {
5419 gint32 prev_lmf_reg;
5420 gint32 lmf_offset = -sizeof (MonoLMF);
5422 /* check if we need to restore protection of the stack after a stack overflow */
5423 if (mono_get_jit_tls_offset () != -1) {
5425 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5426 /* we load the value in a separate instruction: this mechanism may be
5427 * used later as a safer way to do thread interruption
5429 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5430 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5432 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5433 /* note that the call trampoline will preserve eax/edx */
5434 x86_call_reg (code, X86_ECX);
5435 x86_patch (patch, code);
5437 /* FIXME: maybe save the jit tls in the prolog */
5439 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5441 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5442 * through the mono_lmf_addr TLS variable.
5444 /* reg = previous_lmf */
5445 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5447 /* lmf = previous_lmf */
5448 code = mono_x86_emit_tls_set (code, X86_ECX, lmf_tls_offset);
5450 /* Find a spare register */
5451 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
5454 prev_lmf_reg = X86_EDI;
5455 cfg->used_int_regs |= (1 << X86_EDI);
5458 prev_lmf_reg = X86_EDX;
5462 /* reg = previous_lmf */
5463 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5466 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
5468 /* *(lmf) = previous_lmf */
5469 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
5472 /* restore caller saved regs */
5473 if (cfg->used_int_regs & (1 << X86_EBX)) {
5474 x86_mov_reg_membase (code, X86_EBX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
5477 if (cfg->used_int_regs & (1 << X86_EDI)) {
5478 x86_mov_reg_membase (code, X86_EDI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
5480 if (cfg->used_int_regs & (1 << X86_ESI)) {
5481 x86_mov_reg_membase (code, X86_ESI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
5484 /* EBP is restored by LEAVE */
5486 if (cfg->used_int_regs & (1 << X86_EBX)) {
5489 if (cfg->used_int_regs & (1 << X86_EDI)) {
5492 if (cfg->used_int_regs & (1 << X86_ESI)) {
5497 g_assert (need_stack_frame);
5498 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5501 if (cfg->used_int_regs & (1 << X86_ESI)) {
5502 x86_pop_reg (code, X86_ESI);
5504 if (cfg->used_int_regs & (1 << X86_EDI)) {
5505 x86_pop_reg (code, X86_EDI);
5507 if (cfg->used_int_regs & (1 << X86_EBX)) {
5508 x86_pop_reg (code, X86_EBX);
5512 /* Load returned vtypes into registers if needed */
5513 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5514 if (cinfo->ret.storage == ArgValuetypeInReg) {
5515 for (quad = 0; quad < 2; quad ++) {
5516 switch (cinfo->ret.pair_storage [quad]) {
5518 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5520 case ArgOnFloatFpStack:
5521 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5523 case ArgOnDoubleFpStack:
5524 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5529 g_assert_not_reached ();
5534 if (need_stack_frame)
5537 if (CALLCONV_IS_STDCALL (sig)) {
5538 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5540 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5541 } else if (cinfo->vtype_retaddr)
5547 g_assert (need_stack_frame);
5548 x86_ret_imm (code, stack_to_pop);
5553 cfg->code_len = code - cfg->native_code;
5555 g_assert (cfg->code_len < cfg->code_size);
5559 mono_arch_emit_exceptions (MonoCompile *cfg)
5561 MonoJumpInfo *patch_info;
5564 MonoClass *exc_classes [16];
5565 guint8 *exc_throw_start [16], *exc_throw_end [16];
5569 /* Compute needed space */
5570 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5571 if (patch_info->type == MONO_PATCH_INFO_EXC)
5576 * make sure we have enough space for exceptions
5577 * 16 is the size of two push_imm instructions and a call
5579 if (cfg->compile_aot)
5580 code_size = exc_count * 32;
5582 code_size = exc_count * 16;
5584 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5585 cfg->code_size *= 2;
5586 cfg->native_code = mono_realloc_native_code(cfg);
5587 cfg->stat_code_reallocs++;
5590 code = cfg->native_code + cfg->code_len;
5593 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5594 switch (patch_info->type) {
5595 case MONO_PATCH_INFO_EXC: {
5596 MonoClass *exc_class;
5600 x86_patch (patch_info->ip.i + cfg->native_code, code);
5602 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5603 g_assert (exc_class);
5604 throw_ip = patch_info->ip.i;
5606 /* Find a throw sequence for the same exception class */
5607 for (i = 0; i < nthrows; ++i)
5608 if (exc_classes [i] == exc_class)
5611 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5612 x86_jump_code (code, exc_throw_start [i]);
5613 patch_info->type = MONO_PATCH_INFO_NONE;
5618 /* Compute size of code following the push <OFFSET> */
5619 #if defined(__default_codegen__)
5621 #elif defined(__native_client_codegen__)
5622 code = mono_nacl_align (code);
5623 size = kNaClAlignment;
5625 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5627 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5628 /* Use the shorter form */
5630 x86_push_imm (code, 0);
5634 x86_push_imm (code, 0xf0f0f0f0);
5639 exc_classes [nthrows] = exc_class;
5640 exc_throw_start [nthrows] = code;
5643 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5644 patch_info->data.name = "mono_arch_throw_corlib_exception";
5645 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5646 patch_info->ip.i = code - cfg->native_code;
5647 x86_call_code (code, 0);
5648 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5653 exc_throw_end [nthrows] = code;
5665 cfg->code_len = code - cfg->native_code;
5667 g_assert (cfg->code_len < cfg->code_size);
5671 mono_arch_flush_icache (guint8 *code, gint size)
5677 mono_arch_flush_register_windows (void)
5682 mono_arch_is_inst_imm (gint64 imm)
5688 mono_arch_finish_init (void)
5690 if (!g_getenv ("MONO_NO_TLS")) {
5693 * We need to init this multiple times, since when we are first called, the key might not
5694 * be initialized yet.
5696 appdomain_tls_offset = mono_domain_get_tls_key ();
5697 jit_tls_offset = mono_get_jit_tls_key ();
5699 /* Only 64 tls entries can be accessed using inline code */
5700 if (appdomain_tls_offset >= 64)
5701 appdomain_tls_offset = -1;
5702 if (jit_tls_offset >= 64)
5703 jit_tls_offset = -1;
5706 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5708 appdomain_tls_offset = mono_domain_get_tls_offset ();
5709 lmf_tls_offset = mono_get_lmf_tls_offset ();
5710 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5716 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5720 #ifdef MONO_ARCH_HAVE_IMT
5722 // Linear handler, the bsearch head compare is shorter
5723 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5724 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5725 // x86_patch(ins,target)
5726 //[1 + 5] x86_jump_mem(inst,mem)
5729 #if defined(__default_codegen__)
5730 #define BR_SMALL_SIZE 2
5731 #define BR_LARGE_SIZE 5
5732 #elif defined(__native_client_codegen__)
5733 /* I suspect the size calculation below is actually incorrect. */
5734 /* TODO: fix the calculation that uses these sizes. */
5735 #define BR_SMALL_SIZE 16
5736 #define BR_LARGE_SIZE 12
5737 #endif /*__native_client_codegen__*/
5738 #define JUMP_IMM_SIZE 6
5739 #define ENABLE_WRONG_METHOD_CHECK 0
5743 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5745 int i, distance = 0;
5746 for (i = start; i < target; ++i)
5747 distance += imt_entries [i]->chunk_size;
5752 * LOCKING: called with the domain lock held
5755 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5756 gpointer fail_tramp)
5760 guint8 *code, *start;
5762 for (i = 0; i < count; ++i) {
5763 MonoIMTCheckItem *item = imt_entries [i];
5764 if (item->is_equals) {
5765 if (item->check_target_idx) {
5766 if (!item->compare_done)
5767 item->chunk_size += CMP_SIZE;
5768 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5771 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5773 item->chunk_size += JUMP_IMM_SIZE;
5774 #if ENABLE_WRONG_METHOD_CHECK
5775 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5780 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5781 imt_entries [item->check_target_idx]->compare_done = TRUE;
5783 size += item->chunk_size;
5785 #if defined(__native_client__) && defined(__native_client_codegen__)
5786 /* In Native Client, we don't re-use thunks, allocate from the */
5787 /* normal code manager paths. */
5788 size = NACL_BUNDLE_ALIGN_UP (size);
5789 code = mono_domain_code_reserve (domain, size);
5792 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5794 code = mono_domain_code_reserve (domain, size);
5797 for (i = 0; i < count; ++i) {
5798 MonoIMTCheckItem *item = imt_entries [i];
5799 item->code_target = code;
5800 if (item->is_equals) {
5801 if (item->check_target_idx) {
5802 if (!item->compare_done)
5803 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5804 item->jmp_code = code;
5805 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5806 if (item->has_target_code)
5807 x86_jump_code (code, item->value.target_code);
5809 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5812 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5813 item->jmp_code = code;
5814 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5815 if (item->has_target_code)
5816 x86_jump_code (code, item->value.target_code);
5818 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5819 x86_patch (item->jmp_code, code);
5820 x86_jump_code (code, fail_tramp);
5821 item->jmp_code = NULL;
5823 /* enable the commented code to assert on wrong method */
5824 #if ENABLE_WRONG_METHOD_CHECK
5825 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5826 item->jmp_code = code;
5827 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5829 if (item->has_target_code)
5830 x86_jump_code (code, item->value.target_code);
5832 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5833 #if ENABLE_WRONG_METHOD_CHECK
5834 x86_patch (item->jmp_code, code);
5835 x86_breakpoint (code);
5836 item->jmp_code = NULL;
5841 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5842 item->jmp_code = code;
5843 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5844 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5846 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5849 /* patch the branches to get to the target items */
5850 for (i = 0; i < count; ++i) {
5851 MonoIMTCheckItem *item = imt_entries [i];
5852 if (item->jmp_code) {
5853 if (item->check_target_idx) {
5854 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5860 mono_stats.imt_thunks_size += code - start;
5861 g_assert (code - start <= size);
5865 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5866 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5870 if (mono_jit_map_is_enabled ()) {
5873 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5875 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5876 mono_emit_jit_tramp (start, code - start, buff);
5880 nacl_domain_code_validate (domain, &start, size, &code);
5886 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5888 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5893 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5895 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5899 mono_arch_get_cie_program (void)
5903 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5904 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5910 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5912 MonoInst *ins = NULL;
5915 if (cmethod->klass == mono_defaults.math_class) {
5916 if (strcmp (cmethod->name, "Sin") == 0) {
5918 } else if (strcmp (cmethod->name, "Cos") == 0) {
5920 } else if (strcmp (cmethod->name, "Tan") == 0) {
5922 } else if (strcmp (cmethod->name, "Atan") == 0) {
5924 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5926 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5928 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5933 MONO_INST_NEW (cfg, ins, opcode);
5934 ins->type = STACK_R8;
5935 ins->dreg = mono_alloc_freg (cfg);
5936 ins->sreg1 = args [0]->dreg;
5937 MONO_ADD_INS (cfg->cbb, ins);
5940 if (cfg->opt & MONO_OPT_CMOV) {
5943 if (strcmp (cmethod->name, "Min") == 0) {
5944 if (fsig->params [0]->type == MONO_TYPE_I4)
5946 } else if (strcmp (cmethod->name, "Max") == 0) {
5947 if (fsig->params [0]->type == MONO_TYPE_I4)
5952 MONO_INST_NEW (cfg, ins, opcode);
5953 ins->type = STACK_I4;
5954 ins->dreg = mono_alloc_ireg (cfg);
5955 ins->sreg1 = args [0]->dreg;
5956 ins->sreg2 = args [1]->dreg;
5957 MONO_ADD_INS (cfg->cbb, ins);
5962 /* OP_FREM is not IEEE compatible */
5963 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5964 MONO_INST_NEW (cfg, ins, OP_FREM);
5965 ins->inst_i0 = args [0];
5966 ins->inst_i1 = args [1];
5975 mono_arch_print_tree (MonoInst *tree, int arity)
5980 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5986 if (appdomain_tls_offset == -1)
5989 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5990 ins->inst_offset = appdomain_tls_offset;
5995 mono_arch_get_patch_offset (guint8 *code)
5997 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5999 else if (code [0] == 0xba)
6001 else if (code [0] == 0x68)
6004 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
6005 /* push <OFFSET>(<REG>) */
6007 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
6008 /* call *<OFFSET>(<REG>) */
6010 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
6013 else if ((code [0] == 0x58) && (code [1] == 0x05))
6014 /* pop %eax; add <OFFSET>, %eax */
6016 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6017 /* pop <REG>; add <OFFSET>, <REG> */
6019 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6020 /* mov <REG>, imm */
6023 g_assert_not_reached ();
6029 * mono_breakpoint_clean_code:
6031 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6032 * breakpoints in the original code, they are removed in the copy.
6034 * Returns TRUE if no sw breakpoint was present.
6037 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6040 gboolean can_write = TRUE;
6042 * If method_start is non-NULL we need to perform bound checks, since we access memory
6043 * at code - offset we could go before the start of the method and end up in a different
6044 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6047 if (!method_start || code - offset >= method_start) {
6048 memcpy (buf, code - offset, size);
6050 int diff = code - method_start;
6051 memset (buf, 0, size);
6052 memcpy (buf + offset - diff, method_start, diff + size - offset);
6055 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6056 int idx = mono_breakpoint_info_index [i];
6060 ptr = mono_breakpoint_info [idx].address;
6061 if (ptr >= code && ptr < code + size) {
6062 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6064 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6065 buf [ptr - code] = saved_byte;
6072 * mono_x86_get_this_arg_offset:
6074 * Return the offset of the stack location where this is passed during a virtual
6078 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6084 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6086 guint32 esp = regs [X86_ESP];
6087 CallInfo *cinfo = NULL;
6094 * The stack looks like:
6098 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
6100 res = (((MonoObject**)esp) [5 + (offset / 4)]);
6106 #define MAX_ARCH_DELEGATE_PARAMS 10
6109 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6111 guint8 *code, *start;
6112 int code_reserve = 64;
6115 * The stack contains:
6121 start = code = mono_global_codeman_reserve (code_reserve);
6123 /* Replace the this argument with the target */
6124 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6125 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
6126 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6127 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6129 g_assert ((code - start) < code_reserve);
6132 /* 8 for mov_reg and jump, plus 8 for each parameter */
6133 #ifdef __native_client_codegen__
6134 /* TODO: calculate this size correctly */
6135 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6137 code_reserve = 8 + (param_count * 8);
6138 #endif /* __native_client_codegen__ */
6140 * The stack contains:
6141 * <args in reverse order>
6146 * <args in reverse order>
6149 * without unbalancing the stack.
6150 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6151 * and leaving original spot of first arg as placeholder in stack so
6152 * when callee pops stack everything works.
6155 start = code = mono_global_codeman_reserve (code_reserve);
6157 /* store delegate for access to method_ptr */
6158 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6161 for (i = 0; i < param_count; ++i) {
6162 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6163 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6166 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6168 g_assert ((code - start) < code_reserve);
6171 nacl_global_codeman_validate(&start, code_reserve, &code);
6172 mono_debug_add_delegate_trampoline (start, code - start);
6175 *code_len = code - start;
6177 if (mono_jit_map_is_enabled ()) {
6180 buff = (char*)"delegate_invoke_has_target";
6182 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6183 mono_emit_jit_tramp (start, code - start, buff);
6192 mono_arch_get_delegate_invoke_impls (void)
6200 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6201 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
6203 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6204 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6205 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
6206 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
6207 g_free (tramp_name);
6214 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6216 guint8 *code, *start;
6218 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6221 /* FIXME: Support more cases */
6222 if (MONO_TYPE_ISSTRUCT (sig->ret))
6226 * The stack contains:
6232 static guint8* cached = NULL;
6237 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6239 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6241 mono_memory_barrier ();
6245 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6248 for (i = 0; i < sig->param_count; ++i)
6249 if (!mono_is_regsize_var (sig->params [i]))
6252 code = cache [sig->param_count];
6256 if (mono_aot_only) {
6257 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6258 start = mono_aot_get_trampoline (name);
6261 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6264 mono_memory_barrier ();
6266 cache [sig->param_count] = start;
6273 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6276 case X86_EAX: return ctx->eax;
6277 case X86_EBX: return ctx->ebx;
6278 case X86_ECX: return ctx->ecx;
6279 case X86_EDX: return ctx->edx;
6280 case X86_ESP: return ctx->esp;
6281 case X86_EBP: return ctx->ebp;
6282 case X86_ESI: return ctx->esi;
6283 case X86_EDI: return ctx->edi;
6285 g_assert_not_reached ();
6291 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6319 g_assert_not_reached ();
6323 #ifdef MONO_ARCH_SIMD_INTRINSICS
6326 get_float_to_x_spill_area (MonoCompile *cfg)
6328 if (!cfg->fconv_to_r8_x_var) {
6329 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6330 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6332 return cfg->fconv_to_r8_x_var;
6336 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6339 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6342 int dreg, src_opcode;
6344 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6347 switch (src_opcode = ins->opcode) {
6348 case OP_FCONV_TO_I1:
6349 case OP_FCONV_TO_U1:
6350 case OP_FCONV_TO_I2:
6351 case OP_FCONV_TO_U2:
6352 case OP_FCONV_TO_I4:
6359 /* dreg is the IREG and sreg1 is the FREG */
6360 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6361 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6362 fconv->sreg1 = ins->sreg1;
6363 fconv->dreg = mono_alloc_ireg (cfg);
6364 fconv->type = STACK_VTYPE;
6365 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6367 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6371 ins->opcode = OP_XCONV_R8_TO_I4;
6373 ins->klass = mono_defaults.int32_class;
6374 ins->sreg1 = fconv->dreg;
6376 ins->type = STACK_I4;
6377 ins->backend.source_opcode = src_opcode;
6380 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6383 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6388 if (long_ins->opcode == OP_LNEG) {
6390 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6391 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6392 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6397 #ifdef MONO_ARCH_SIMD_INTRINSICS
6399 if (!(cfg->opt & MONO_OPT_SIMD))
6402 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6403 switch (long_ins->opcode) {
6405 vreg = long_ins->sreg1;
6407 if (long_ins->inst_c0) {
6408 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6409 ins->klass = long_ins->klass;
6410 ins->sreg1 = long_ins->sreg1;
6412 ins->type = STACK_VTYPE;
6413 ins->dreg = vreg = alloc_ireg (cfg);
6414 MONO_ADD_INS (cfg->cbb, ins);
6417 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6418 ins->klass = mono_defaults.int32_class;
6420 ins->type = STACK_I4;
6421 ins->dreg = long_ins->dreg + 1;
6422 MONO_ADD_INS (cfg->cbb, ins);
6424 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6425 ins->klass = long_ins->klass;
6426 ins->sreg1 = long_ins->sreg1;
6427 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6428 ins->type = STACK_VTYPE;
6429 ins->dreg = vreg = alloc_ireg (cfg);
6430 MONO_ADD_INS (cfg->cbb, ins);
6432 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6433 ins->klass = mono_defaults.int32_class;
6435 ins->type = STACK_I4;
6436 ins->dreg = long_ins->dreg + 2;
6437 MONO_ADD_INS (cfg->cbb, ins);
6439 long_ins->opcode = OP_NOP;
6441 case OP_INSERTX_I8_SLOW:
6442 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6443 ins->dreg = long_ins->dreg;
6444 ins->sreg1 = long_ins->dreg;
6445 ins->sreg2 = long_ins->sreg2 + 1;
6446 ins->inst_c0 = long_ins->inst_c0 * 2;
6447 MONO_ADD_INS (cfg->cbb, ins);
6449 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6450 ins->dreg = long_ins->dreg;
6451 ins->sreg1 = long_ins->dreg;
6452 ins->sreg2 = long_ins->sreg2 + 2;
6453 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6454 MONO_ADD_INS (cfg->cbb, ins);
6456 long_ins->opcode = OP_NOP;
6459 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6460 ins->dreg = long_ins->dreg;
6461 ins->sreg1 = long_ins->sreg1 + 1;
6462 ins->klass = long_ins->klass;
6463 ins->type = STACK_VTYPE;
6464 MONO_ADD_INS (cfg->cbb, ins);
6466 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6467 ins->dreg = long_ins->dreg;
6468 ins->sreg1 = long_ins->dreg;
6469 ins->sreg2 = long_ins->sreg1 + 2;
6471 ins->klass = long_ins->klass;
6472 ins->type = STACK_VTYPE;
6473 MONO_ADD_INS (cfg->cbb, ins);
6475 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6476 ins->dreg = long_ins->dreg;
6477 ins->sreg1 = long_ins->dreg;;
6478 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6479 ins->klass = long_ins->klass;
6480 ins->type = STACK_VTYPE;
6481 MONO_ADD_INS (cfg->cbb, ins);
6483 long_ins->opcode = OP_NOP;
6486 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6489 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6491 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6494 gpointer *sp, old_value;
6496 const unsigned char *handler;
6498 /*Decode the first instruction to figure out where did we store the spvar*/
6499 /*Our jit MUST generate the following:
6501 Which is encoded as: 0x89 mod_rm.
6502 mod_rm (esp, ebp, imm) which can be: (imm will never be zero)
6503 mod (reg + imm8): 01 reg(esp): 100 rm(ebp): 101 -> 01100101 (0x65)
6504 mod (reg + imm32): 10 reg(esp): 100 rm(ebp): 101 -> 10100101 (0xA5)
6506 handler = clause->handler_start;
6508 if (*handler != 0x89)
6513 if (*handler == 0x65)
6514 offset = *(signed char*)(handler + 1);
6515 else if (*handler == 0xA5)
6516 offset = *(int*)(handler + 1);
6521 bp = MONO_CONTEXT_GET_BP (ctx);
6522 sp = *(gpointer*)(bp + offset);
6525 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6534 * mono_aot_emit_load_got_addr:
6536 * Emit code to load the got address.
6537 * On x86, the result is placed into EBX.
6540 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6542 x86_call_imm (code, 0);
6544 * The patch needs to point to the pop, since the GOT offset needs
6545 * to be added to that address.
6548 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6550 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6551 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6552 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6558 * mono_ppc_emit_load_aotconst:
6560 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6561 * TARGET from the mscorlib GOT in full-aot code.
6562 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6566 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6568 /* Load the mscorlib got address */
6569 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6570 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6571 /* arch_emit_got_access () patches this */
6572 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6577 /* Can't put this into mini-x86.h */
6579 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6582 mono_arch_get_trampolines (gboolean aot)
6584 MonoTrampInfo *info;
6585 GSList *tramps = NULL;
6587 mono_x86_get_signal_exception_trampoline (&info, aot);
6589 tramps = g_slist_append (tramps, info);
6596 #define DBG_SIGNAL SIGBUS
6598 #define DBG_SIGNAL SIGSEGV
6601 /* Soft Debug support */
6602 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6605 * mono_arch_set_breakpoint:
6607 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6608 * The location should contain code emitted by OP_SEQ_POINT.
6611 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6616 * In production, we will use int3 (has to fix the size in the md
6617 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6620 g_assert (code [0] == 0x90);
6621 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6625 * mono_arch_clear_breakpoint:
6627 * Clear the breakpoint at IP.
6630 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6635 for (i = 0; i < 6; ++i)
6640 * mono_arch_start_single_stepping:
6642 * Start single stepping.
6645 mono_arch_start_single_stepping (void)
6647 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6651 * mono_arch_stop_single_stepping:
6653 * Stop single stepping.
6656 mono_arch_stop_single_stepping (void)
6658 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6662 * mono_arch_is_single_step_event:
6664 * Return whenever the machine state in SIGCTX corresponds to a single
6668 mono_arch_is_single_step_event (void *info, void *sigctx)
6671 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6673 if (((gpointer)einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6678 siginfo_t* sinfo = (siginfo_t*) info;
6679 /* Sometimes the address is off by 4 */
6680 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6688 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6691 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6692 if (((gpointer)einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6697 siginfo_t* sinfo = (siginfo_t*)info;
6698 /* Sometimes the address is off by 4 */
6699 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6706 #define BREAKPOINT_SIZE 6
6709 * mono_arch_skip_breakpoint:
6711 * See mini-amd64.c for docs.
6714 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6716 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6720 * mono_arch_skip_single_step:
6722 * See mini-amd64.c for docs.
6725 mono_arch_skip_single_step (MonoContext *ctx)
6727 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6731 * mono_arch_get_seq_point_info:
6733 * See mini-amd64.c for docs.
6736 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6744 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
6746 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6748 #endif /* !MONOTOUCH */