2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/appdomain.h>
21 #include <mono/metadata/debug-helpers.h>
22 #include <mono/metadata/threads.h>
23 #include <mono/metadata/profiler-private.h>
24 #include <mono/metadata/mono-debug.h>
25 #include <mono/metadata/gc-internal.h>
26 #include <mono/utils/mono-math.h>
27 #include <mono/utils/mono-counters.h>
28 #include <mono/utils/mono-mmap.h>
29 #include <mono/utils/mono-memory-model.h>
37 /* On windows, these hold the key returned by TlsAlloc () */
38 static gint lmf_tls_offset = -1;
39 static gint lmf_addr_tls_offset = -1;
40 static gint appdomain_tls_offset = -1;
43 static gboolean optimize_for_xen = TRUE;
45 #define optimize_for_xen 0
49 static gboolean is_win32 = TRUE;
51 static gboolean is_win32 = FALSE;
54 /* This mutex protects architecture specific caches */
55 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
56 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
57 static CRITICAL_SECTION mini_arch_mutex;
59 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
64 /* Under windows, the default pinvoke calling convention is stdcall */
65 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT))
67 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL)
70 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
73 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
76 #ifdef __native_client_codegen__
77 const guint kNaClAlignment = kNaClAlignmentX86;
78 const guint kNaClAlignmentMask = kNaClAlignmentMaskX86;
80 /* Default alignment for Native Client is 32-byte. */
81 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
83 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
84 /* Check that alignment doesn't cross an alignment boundary. */
86 mono_arch_nacl_pad (guint8 *code, int pad)
88 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
90 if (pad == 0) return code;
91 /* assertion: alignment cannot cross a block boundary */
92 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
93 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
94 while (pad >= kMaxPadding) {
95 x86_padding (code, kMaxPadding);
98 if (pad != 0) x86_padding (code, pad);
103 mono_arch_nacl_skip_nops (guint8 *code)
105 x86_skip_nops (code);
109 #endif /* __native_client_codegen__ */
112 * The code generated for sequence points reads from this location, which is
113 * made read-only when single stepping is enabled.
115 static gpointer ss_trigger_page;
117 /* Enabled breakpoints read from this trigger page */
118 static gpointer bp_trigger_page;
121 mono_arch_regname (int reg)
124 case X86_EAX: return "%eax";
125 case X86_EBX: return "%ebx";
126 case X86_ECX: return "%ecx";
127 case X86_EDX: return "%edx";
128 case X86_ESP: return "%esp";
129 case X86_EBP: return "%ebp";
130 case X86_EDI: return "%edi";
131 case X86_ESI: return "%esi";
137 mono_arch_fregname (int reg)
162 mono_arch_xregname (int reg)
187 mono_x86_patch (unsigned char* code, gpointer target)
189 x86_patch (code, (unsigned char*)target);
208 /* Only if storage == ArgValuetypeInReg */
209 ArgStorage pair_storage [2];
218 gboolean need_stack_align;
219 guint32 stack_align_amount;
220 gboolean vtype_retaddr;
221 /* The index of the vret arg in the argument list */
230 #define FLOAT_PARAM_REGS 0
232 static X86_Reg_No param_regs [] = { 0 };
234 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
235 #define SMALL_STRUCTS_IN_REGS
236 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
240 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
242 ainfo->offset = *stack_size;
244 if (*gr >= PARAM_REGS) {
245 ainfo->storage = ArgOnStack;
246 (*stack_size) += sizeof (gpointer);
249 ainfo->storage = ArgInIReg;
250 ainfo->reg = param_regs [*gr];
256 add_general_pair (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
258 ainfo->offset = *stack_size;
260 g_assert (PARAM_REGS == 0);
262 ainfo->storage = ArgOnStack;
263 (*stack_size) += sizeof (gpointer) * 2;
267 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
269 ainfo->offset = *stack_size;
271 if (*gr >= FLOAT_PARAM_REGS) {
272 ainfo->storage = ArgOnStack;
273 (*stack_size) += is_double ? 8 : 4;
276 /* A double register */
278 ainfo->storage = ArgInDoubleSSEReg;
280 ainfo->storage = ArgInFloatSSEReg;
288 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
290 guint32 *gr, guint32 *fr, guint32 *stack_size)
295 klass = mono_class_from_mono_type (type);
296 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
298 #ifdef SMALL_STRUCTS_IN_REGS
299 if (sig->pinvoke && is_return) {
300 MonoMarshalType *info;
303 * the exact rules are not very well documented, the code below seems to work with the
304 * code generated by gcc 3.3.3 -mno-cygwin.
306 info = mono_marshal_load_type_info (klass);
309 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
311 /* Special case structs with only a float member */
312 if ((info->native_size == 8) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R8)) {
313 ainfo->storage = ArgValuetypeInReg;
314 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
317 if ((info->native_size == 4) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R4)) {
318 ainfo->storage = ArgValuetypeInReg;
319 ainfo->pair_storage [0] = ArgOnFloatFpStack;
322 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
323 ainfo->storage = ArgValuetypeInReg;
324 ainfo->pair_storage [0] = ArgInIReg;
325 ainfo->pair_regs [0] = return_regs [0];
326 if (info->native_size > 4) {
327 ainfo->pair_storage [1] = ArgInIReg;
328 ainfo->pair_regs [1] = return_regs [1];
335 ainfo->offset = *stack_size;
336 ainfo->storage = ArgOnStack;
337 *stack_size += ALIGN_TO (size, sizeof (gpointer));
343 * Obtain information about a call according to the calling convention.
344 * For x86 ELF, see the "System V Application Binary Interface Intel386
345 * Architecture Processor Supplment, Fourth Edition" document for more
347 * For x86 win32, see ???.
350 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
352 guint32 i, gr, fr, pstart;
354 int n = sig->hasthis + sig->param_count;
355 guint32 stack_size = 0;
356 gboolean is_pinvoke = sig->pinvoke;
363 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
364 switch (ret_type->type) {
365 case MONO_TYPE_BOOLEAN:
376 case MONO_TYPE_FNPTR:
377 case MONO_TYPE_CLASS:
378 case MONO_TYPE_OBJECT:
379 case MONO_TYPE_SZARRAY:
380 case MONO_TYPE_ARRAY:
381 case MONO_TYPE_STRING:
382 cinfo->ret.storage = ArgInIReg;
383 cinfo->ret.reg = X86_EAX;
387 cinfo->ret.storage = ArgInIReg;
388 cinfo->ret.reg = X86_EAX;
391 cinfo->ret.storage = ArgOnFloatFpStack;
394 cinfo->ret.storage = ArgOnDoubleFpStack;
396 case MONO_TYPE_GENERICINST:
397 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
398 cinfo->ret.storage = ArgInIReg;
399 cinfo->ret.reg = X86_EAX;
403 case MONO_TYPE_VALUETYPE: {
404 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
406 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
407 if (cinfo->ret.storage == ArgOnStack) {
408 cinfo->vtype_retaddr = TRUE;
409 /* The caller passes the address where the value is stored */
413 case MONO_TYPE_TYPEDBYREF:
414 /* Same as a valuetype with size 12 */
415 cinfo->vtype_retaddr = TRUE;
418 cinfo->ret.storage = ArgNone;
421 g_error ("Can't handle as return value 0x%x", sig->ret->type);
427 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
428 * the first argument, allowing 'this' to be always passed in the first arg reg.
429 * Also do this if the first argument is a reference type, since virtual calls
430 * are sometimes made using calli without sig->hasthis set, like in the delegate
433 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
435 add_general (&gr, &stack_size, cinfo->args + 0);
437 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
440 add_general (&gr, &stack_size, &cinfo->ret);
441 cinfo->vret_arg_index = 1;
445 add_general (&gr, &stack_size, cinfo->args + 0);
447 if (cinfo->vtype_retaddr)
448 add_general (&gr, &stack_size, &cinfo->ret);
451 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
453 fr = FLOAT_PARAM_REGS;
455 /* Emit the signature cookie just before the implicit arguments */
456 add_general (&gr, &stack_size, &cinfo->sig_cookie);
459 for (i = pstart; i < sig->param_count; ++i) {
460 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
463 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
464 /* We allways pass the sig cookie on the stack for simplicity */
466 * Prevent implicit arguments + the sig cookie from being passed
470 fr = FLOAT_PARAM_REGS;
472 /* Emit the signature cookie just before the implicit arguments */
473 add_general (&gr, &stack_size, &cinfo->sig_cookie);
476 if (sig->params [i]->byref) {
477 add_general (&gr, &stack_size, ainfo);
480 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
481 switch (ptype->type) {
482 case MONO_TYPE_BOOLEAN:
485 add_general (&gr, &stack_size, ainfo);
490 add_general (&gr, &stack_size, ainfo);
494 add_general (&gr, &stack_size, ainfo);
499 case MONO_TYPE_FNPTR:
500 case MONO_TYPE_CLASS:
501 case MONO_TYPE_OBJECT:
502 case MONO_TYPE_STRING:
503 case MONO_TYPE_SZARRAY:
504 case MONO_TYPE_ARRAY:
505 add_general (&gr, &stack_size, ainfo);
507 case MONO_TYPE_GENERICINST:
508 if (!mono_type_generic_inst_is_valuetype (ptype)) {
509 add_general (&gr, &stack_size, ainfo);
513 case MONO_TYPE_VALUETYPE:
514 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
516 case MONO_TYPE_TYPEDBYREF:
517 stack_size += sizeof (MonoTypedRef);
518 ainfo->storage = ArgOnStack;
522 add_general_pair (&gr, &stack_size, ainfo);
525 add_float (&fr, &stack_size, ainfo, FALSE);
528 add_float (&fr, &stack_size, ainfo, TRUE);
531 g_error ("unexpected type 0x%x", ptype->type);
532 g_assert_not_reached ();
536 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
538 fr = FLOAT_PARAM_REGS;
540 /* Emit the signature cookie just before the implicit arguments */
541 add_general (&gr, &stack_size, &cinfo->sig_cookie);
544 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
545 cinfo->need_stack_align = TRUE;
546 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
547 stack_size += cinfo->stack_align_amount;
550 cinfo->stack_usage = stack_size;
551 cinfo->reg_usage = gr;
552 cinfo->freg_usage = fr;
557 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
559 int n = sig->hasthis + sig->param_count;
563 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
565 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
567 return get_call_info_internal (gsctx, cinfo, sig);
571 * mono_arch_get_argument_info:
572 * @csig: a method signature
573 * @param_count: the number of parameters to consider
574 * @arg_info: an array to store the result infos
576 * Gathers information on parameters such as size, alignment and
577 * padding. arg_info should be large enought to hold param_count + 1 entries.
579 * Returns the size of the argument area on the stack.
580 * This should be signal safe, since it is called from
581 * mono_arch_find_jit_info ().
582 * FIXME: The metadata calls might not be signal safe.
585 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
587 int len, k, args_size = 0;
593 /* Avoid g_malloc as it is not signal safe */
594 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
595 cinfo = (CallInfo*)g_newa (guint8*, len);
596 memset (cinfo, 0, len);
598 cinfo = get_call_info_internal (NULL, cinfo, csig);
600 arg_info [0].offset = offset;
602 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
603 args_size += sizeof (gpointer);
608 args_size += sizeof (gpointer);
612 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
613 /* Emitted after this */
614 args_size += sizeof (gpointer);
618 arg_info [0].size = args_size;
620 for (k = 0; k < param_count; k++) {
621 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
623 /* ignore alignment for now */
626 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
627 arg_info [k].pad = pad;
629 arg_info [k + 1].pad = 0;
630 arg_info [k + 1].size = size;
632 arg_info [k + 1].offset = offset;
635 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
636 /* Emitted after the first arg */
637 args_size += sizeof (gpointer);
642 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
643 align = MONO_ARCH_FRAME_ALIGNMENT;
646 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
647 arg_info [k].pad = pad;
653 mono_x86_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
658 c1 = get_call_info (NULL, NULL, caller_sig);
659 c2 = get_call_info (NULL, NULL, callee_sig);
660 res = c1->stack_usage >= c2->stack_usage;
661 if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
662 /* An address on the callee's stack is passed as the first argument */
671 static const guchar cpuid_impl [] = {
672 0x55, /* push %ebp */
673 0x89, 0xe5, /* mov %esp,%ebp */
674 0x53, /* push %ebx */
675 0x8b, 0x45, 0x08, /* mov 0x8(%ebp),%eax */
676 0x0f, 0xa2, /* cpuid */
677 0x50, /* push %eax */
678 0x8b, 0x45, 0x10, /* mov 0x10(%ebp),%eax */
679 0x89, 0x18, /* mov %ebx,(%eax) */
680 0x8b, 0x45, 0x14, /* mov 0x14(%ebp),%eax */
681 0x89, 0x08, /* mov %ecx,(%eax) */
682 0x8b, 0x45, 0x18, /* mov 0x18(%ebp),%eax */
683 0x89, 0x10, /* mov %edx,(%eax) */
685 0x8b, 0x55, 0x0c, /* mov 0xc(%ebp),%edx */
686 0x89, 0x02, /* mov %eax,(%edx) */
692 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
695 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
697 #if defined(__native_client__)
698 /* Taken from below, the bug listed in the comment is */
699 /* only valid for non-static cases. */
700 __asm__ __volatile__ ("cpuid"
701 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
707 __asm__ __volatile__ (
710 "movl %%eax, %%edx\n"
711 "xorl $0x200000, %%eax\n"
716 "xorl %%edx, %%eax\n"
717 "andl $0x200000, %%eax\n"
739 /* Have to use the code manager to get around WinXP DEP */
740 static CpuidFunc func = NULL;
743 ptr = mono_global_codeman_reserve (sizeof (cpuid_impl));
744 memcpy (ptr, cpuid_impl, sizeof (cpuid_impl));
745 func = (CpuidFunc)ptr;
747 func (id, p_eax, p_ebx, p_ecx, p_edx);
750 * We use this approach because of issues with gcc and pic code, see:
751 * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
752 __asm__ __volatile__ ("cpuid"
753 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
763 * Initialize the cpu to execute managed code.
766 mono_arch_cpu_init (void)
768 /* spec compliance requires running with double precision */
772 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
773 fpcw &= ~X86_FPCW_PRECC_MASK;
774 fpcw |= X86_FPCW_PREC_DOUBLE;
775 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
776 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
778 _control87 (_PC_53, MCW_PC);
783 * Initialize architecture specific code.
786 mono_arch_init (void)
788 InitializeCriticalSection (&mini_arch_mutex);
790 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
791 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
792 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
794 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
795 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
799 * Cleanup architecture specific code.
802 mono_arch_cleanup (void)
804 DeleteCriticalSection (&mini_arch_mutex);
808 * This function returns the optimizations supported on this cpu.
811 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
813 #if !defined(__native_client__)
814 int eax, ebx, ecx, edx;
820 /* The cpuid function allocates from the global codeman */
823 /* Feature Flags function, flags returned in EDX. */
824 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
825 if (edx & (1 << 15)) {
826 opts |= MONO_OPT_CMOV;
828 opts |= MONO_OPT_FCMOV;
830 *exclude_mask |= MONO_OPT_FCMOV;
832 *exclude_mask |= MONO_OPT_CMOV;
834 opts |= MONO_OPT_SSE2;
836 *exclude_mask |= MONO_OPT_SSE2;
838 #ifdef MONO_ARCH_SIMD_INTRINSICS
839 /*SIMD intrinsics require at least SSE2.*/
840 if (!(opts & MONO_OPT_SSE2))
841 *exclude_mask |= MONO_OPT_SIMD;
846 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
851 * This function test for all SSE functions supported.
853 * Returns a bitmask corresponding to all supported versions.
857 mono_arch_cpu_enumerate_simd_versions (void)
859 int eax, ebx, ecx, edx;
860 guint32 sse_opts = 0;
863 /* The cpuid function allocates from the global codeman */
866 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
868 sse_opts |= SIMD_VERSION_SSE1;
870 sse_opts |= SIMD_VERSION_SSE2;
872 sse_opts |= SIMD_VERSION_SSE3;
874 sse_opts |= SIMD_VERSION_SSSE3;
876 sse_opts |= SIMD_VERSION_SSE41;
878 sse_opts |= SIMD_VERSION_SSE42;
881 /* Yes, all this needs to be done to check for sse4a.
882 See: "Amd: CPUID Specification"
884 if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
885 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
886 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
887 cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
889 sse_opts |= SIMD_VERSION_SSE4a;
898 * Determine whenever the trap whose info is in SIGINFO is caused by
902 mono_arch_is_int_overflow (void *sigctx, void *info)
907 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
909 ip = (guint8*)ctx.eip;
911 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
915 switch (x86_modrm_rm (ip [1])) {
935 g_assert_not_reached ();
947 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
952 for (i = 0; i < cfg->num_varinfo; i++) {
953 MonoInst *ins = cfg->varinfo [i];
954 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
957 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
960 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
961 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
964 /* we dont allocate I1 to registers because there is no simply way to sign extend
965 * 8bit quantities in caller saved registers on x86 */
966 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
967 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
968 g_assert (i == vmv->idx);
969 vars = g_list_prepend (vars, vmv);
973 vars = mono_varlist_sort (cfg, vars, 0);
979 mono_arch_get_global_int_regs (MonoCompile *cfg)
983 /* we can use 3 registers for global allocation */
984 regs = g_list_prepend (regs, (gpointer)X86_EBX);
985 regs = g_list_prepend (regs, (gpointer)X86_ESI);
986 regs = g_list_prepend (regs, (gpointer)X86_EDI);
992 * mono_arch_regalloc_cost:
994 * Return the cost, in number of memory references, of the action of
995 * allocating the variable VMV into a register during global register
999 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1001 MonoInst *ins = cfg->varinfo [vmv->idx];
1003 if (cfg->method->save_lmf)
1004 /* The register is already saved */
1005 return (ins->opcode == OP_ARG) ? 1 : 0;
1007 /* push+pop+possible load if it is an argument */
1008 return (ins->opcode == OP_ARG) ? 3 : 2;
1012 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
1014 static int inited = FALSE;
1015 static int count = 0;
1017 if (cfg->arch.need_stack_frame_inited) {
1018 g_assert (cfg->arch.need_stack_frame == flag);
1022 cfg->arch.need_stack_frame = flag;
1023 cfg->arch.need_stack_frame_inited = TRUE;
1029 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
1034 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
1038 needs_stack_frame (MonoCompile *cfg)
1040 MonoMethodSignature *sig;
1041 MonoMethodHeader *header;
1042 gboolean result = FALSE;
1044 #if defined(__APPLE__)
1045 /*OSX requires stack frame code to have the correct alignment. */
1049 if (cfg->arch.need_stack_frame_inited)
1050 return cfg->arch.need_stack_frame;
1052 header = cfg->header;
1053 sig = mono_method_signature (cfg->method);
1055 if (cfg->disable_omit_fp)
1057 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1059 else if (cfg->method->save_lmf)
1061 else if (cfg->stack_offset)
1063 else if (cfg->param_area)
1065 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1067 else if (header->num_clauses)
1069 else if (sig->param_count + sig->hasthis)
1071 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1073 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1074 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1077 set_needs_stack_frame (cfg, result);
1079 return cfg->arch.need_stack_frame;
1083 * Set var information according to the calling convention. X86 version.
1084 * The locals var stuff should most likely be split in another method.
1087 mono_arch_allocate_vars (MonoCompile *cfg)
1089 MonoMethodSignature *sig;
1090 MonoMethodHeader *header;
1092 guint32 locals_stack_size, locals_stack_align;
1097 header = cfg->header;
1098 sig = mono_method_signature (cfg->method);
1100 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1102 cfg->frame_reg = X86_EBP;
1105 /* Reserve space to save LMF and caller saved registers */
1107 if (cfg->method->save_lmf) {
1108 offset += sizeof (MonoLMF);
1110 if (cfg->used_int_regs & (1 << X86_EBX)) {
1114 if (cfg->used_int_regs & (1 << X86_EDI)) {
1118 if (cfg->used_int_regs & (1 << X86_ESI)) {
1123 switch (cinfo->ret.storage) {
1124 case ArgValuetypeInReg:
1125 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1127 cfg->ret->opcode = OP_REGOFFSET;
1128 cfg->ret->inst_basereg = X86_EBP;
1129 cfg->ret->inst_offset = - offset;
1135 /* Allocate locals */
1136 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1137 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1138 char *mname = mono_method_full_name (cfg->method, TRUE);
1139 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1140 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1144 if (locals_stack_align) {
1145 int prev_offset = offset;
1147 offset += (locals_stack_align - 1);
1148 offset &= ~(locals_stack_align - 1);
1150 while (prev_offset < offset) {
1152 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1155 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1156 cfg->locals_max_stack_offset = - offset;
1158 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1159 * have locals larger than 8 bytes we need to make sure that
1160 * they have the appropriate offset.
1162 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1163 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1164 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1165 if (offsets [i] != -1) {
1166 MonoInst *inst = cfg->varinfo [i];
1167 inst->opcode = OP_REGOFFSET;
1168 inst->inst_basereg = X86_EBP;
1169 inst->inst_offset = - (offset + offsets [i]);
1170 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1173 offset += locals_stack_size;
1177 * Allocate arguments+return value
1180 switch (cinfo->ret.storage) {
1182 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1184 * In the new IR, the cfg->vret_addr variable represents the
1185 * vtype return value.
1187 cfg->vret_addr->opcode = OP_REGOFFSET;
1188 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1189 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1190 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1191 printf ("vret_addr =");
1192 mono_print_ins (cfg->vret_addr);
1195 cfg->ret->opcode = OP_REGOFFSET;
1196 cfg->ret->inst_basereg = X86_EBP;
1197 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1200 case ArgValuetypeInReg:
1203 cfg->ret->opcode = OP_REGVAR;
1204 cfg->ret->inst_c0 = cinfo->ret.reg;
1205 cfg->ret->dreg = cinfo->ret.reg;
1208 case ArgOnFloatFpStack:
1209 case ArgOnDoubleFpStack:
1212 g_assert_not_reached ();
1215 if (sig->call_convention == MONO_CALL_VARARG) {
1216 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1217 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1220 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1221 ArgInfo *ainfo = &cinfo->args [i];
1222 inst = cfg->args [i];
1223 if (inst->opcode != OP_REGVAR) {
1224 inst->opcode = OP_REGOFFSET;
1225 inst->inst_basereg = X86_EBP;
1227 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1230 cfg->stack_offset = offset;
1234 mono_arch_create_vars (MonoCompile *cfg)
1236 MonoMethodSignature *sig;
1239 sig = mono_method_signature (cfg->method);
1241 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1243 if (cinfo->ret.storage == ArgValuetypeInReg)
1244 cfg->ret_var_is_local = TRUE;
1245 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1246 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1249 cfg->arch_eh_jit_info = 1;
1253 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1254 * so we try to do it just once when we have multiple fp arguments in a row.
1255 * We don't use this mechanism generally because for int arguments the generated code
1256 * is slightly bigger and new generation cpus optimize away the dependency chains
1257 * created by push instructions on the esp value.
1258 * fp_arg_setup is the first argument in the execution sequence where the esp register
1261 static G_GNUC_UNUSED int
1262 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1267 for (; start_arg < sig->param_count; ++start_arg) {
1268 t = mini_type_get_underlying_type (NULL, sig->params [start_arg]);
1269 if (!t->byref && t->type == MONO_TYPE_R8) {
1270 fp_space += sizeof (double);
1271 *fp_arg_setup = start_arg;
1280 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1282 MonoMethodSignature *tmp_sig;
1286 * mono_ArgIterator_Setup assumes the signature cookie is
1287 * passed first and all the arguments which were before it are
1288 * passed on the stack after the signature. So compensate by
1289 * passing a different signature.
1291 tmp_sig = mono_metadata_signature_dup (call->signature);
1292 tmp_sig->param_count -= call->signature->sentinelpos;
1293 tmp_sig->sentinelpos = 0;
1294 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1296 if (cfg->compile_aot) {
1297 sig_reg = mono_alloc_ireg (cfg);
1298 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1299 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, sig_reg);
1301 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1307 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1312 LLVMCallInfo *linfo;
1315 n = sig->param_count + sig->hasthis;
1317 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1319 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1322 * LLVM always uses the native ABI while we use our own ABI, the
1323 * only difference is the handling of vtypes:
1324 * - we only pass/receive them in registers in some cases, and only
1325 * in 1 or 2 integer registers.
1327 if (cinfo->ret.storage == ArgValuetypeInReg) {
1329 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1330 cfg->disable_llvm = TRUE;
1334 cfg->exception_message = g_strdup ("vtype ret in call");
1335 cfg->disable_llvm = TRUE;
1337 linfo->ret.storage = LLVMArgVtypeInReg;
1338 for (j = 0; j < 2; ++j)
1339 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1343 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1344 /* Vtype returned using a hidden argument */
1345 linfo->ret.storage = LLVMArgVtypeRetAddr;
1346 linfo->vret_arg_index = cinfo->vret_arg_index;
1349 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != ArgInIReg) {
1351 cfg->exception_message = g_strdup ("vtype ret in call");
1352 cfg->disable_llvm = TRUE;
1355 for (i = 0; i < n; ++i) {
1356 ainfo = cinfo->args + i;
1358 if (i >= sig->hasthis)
1359 t = sig->params [i - sig->hasthis];
1361 t = &mono_defaults.int_class->byval_arg;
1363 linfo->args [i].storage = LLVMArgNone;
1365 switch (ainfo->storage) {
1367 linfo->args [i].storage = LLVMArgInIReg;
1369 case ArgInDoubleSSEReg:
1370 case ArgInFloatSSEReg:
1371 linfo->args [i].storage = LLVMArgInFPReg;
1374 if (MONO_TYPE_ISSTRUCT (t)) {
1375 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1376 /* LLVM seems to allocate argument space for empty structures too */
1377 linfo->args [i].storage = LLVMArgNone;
1379 linfo->args [i].storage = LLVMArgVtypeByVal;
1381 linfo->args [i].storage = LLVMArgInIReg;
1383 if (t->type == MONO_TYPE_R4)
1384 linfo->args [i].storage = LLVMArgInFPReg;
1385 else if (t->type == MONO_TYPE_R8)
1386 linfo->args [i].storage = LLVMArgInFPReg;
1390 case ArgValuetypeInReg:
1392 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1393 cfg->disable_llvm = TRUE;
1397 cfg->exception_message = g_strdup ("vtype arg");
1398 cfg->disable_llvm = TRUE;
1400 linfo->args [i].storage = LLVMArgVtypeInReg;
1401 for (j = 0; j < 2; ++j)
1402 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1406 cfg->exception_message = g_strdup ("ainfo->storage");
1407 cfg->disable_llvm = TRUE;
1417 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1419 if (cfg->compute_gc_maps) {
1422 /* On x86, the offsets are from the sp value before the start of the call sequence */
1424 t = &mono_defaults.int_class->byval_arg;
1425 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1430 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1433 MonoMethodSignature *sig;
1436 int sentinelpos = 0, sp_offset = 0;
1438 sig = call->signature;
1439 n = sig->param_count + sig->hasthis;
1441 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1443 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1444 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1446 if (cinfo->need_stack_align) {
1447 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1448 arg->dreg = X86_ESP;
1449 arg->sreg1 = X86_ESP;
1450 arg->inst_imm = cinfo->stack_align_amount;
1451 MONO_ADD_INS (cfg->cbb, arg);
1452 for (i = 0; i < cinfo->stack_align_amount; i += sizeof (mgreg_t)) {
1455 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1459 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1460 if (cinfo->ret.storage == ArgValuetypeInReg) {
1462 * Tell the JIT to use a more efficient calling convention: call using
1463 * OP_CALL, compute the result location after the call, and save the
1466 call->vret_in_reg = TRUE;
1468 NULLIFY_INS (call->vret_var);
1472 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1474 /* Handle the case where there are no implicit arguments */
1475 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1476 emit_sig_cookie (cfg, call, cinfo);
1478 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1481 /* Arguments are pushed in the reverse order */
1482 for (i = n - 1; i >= 0; i --) {
1483 ArgInfo *ainfo = cinfo->args + i;
1487 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1488 /* Push the vret arg before the first argument */
1490 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1491 vtarg->type = STACK_MP;
1492 vtarg->sreg1 = call->vret_var->dreg;
1493 MONO_ADD_INS (cfg->cbb, vtarg);
1495 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1498 if (i >= sig->hasthis)
1499 t = sig->params [i - sig->hasthis];
1501 t = &mono_defaults.int_class->byval_arg;
1502 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1504 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1506 in = call->args [i];
1507 arg->cil_code = in->cil_code;
1508 arg->sreg1 = in->dreg;
1509 arg->type = in->type;
1511 g_assert (in->dreg != -1);
1513 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1517 g_assert (in->klass);
1519 if (t->type == MONO_TYPE_TYPEDBYREF) {
1520 size = sizeof (MonoTypedRef);
1521 align = sizeof (gpointer);
1524 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1528 arg->opcode = OP_OUTARG_VT;
1529 arg->sreg1 = in->dreg;
1530 arg->klass = in->klass;
1531 arg->backend.size = size;
1533 MONO_ADD_INS (cfg->cbb, arg);
1535 emit_gc_param_slot_def (cfg, sp_offset, t);
1540 switch (ainfo->storage) {
1542 arg->opcode = OP_X86_PUSH;
1544 if (t->type == MONO_TYPE_R4) {
1545 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1546 arg->opcode = OP_STORER4_MEMBASE_REG;
1547 arg->inst_destbasereg = X86_ESP;
1548 arg->inst_offset = 0;
1550 } else if (t->type == MONO_TYPE_R8) {
1551 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1552 arg->opcode = OP_STORER8_MEMBASE_REG;
1553 arg->inst_destbasereg = X86_ESP;
1554 arg->inst_offset = 0;
1556 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1558 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1564 g_assert_not_reached ();
1567 MONO_ADD_INS (cfg->cbb, arg);
1569 sp_offset += argsize;
1571 if (cfg->compute_gc_maps) {
1573 /* FIXME: The == STACK_OBJ check might be fragile ? */
1574 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ)
1576 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.object_class->byval_arg);
1578 emit_gc_param_slot_def (cfg, sp_offset, t);
1581 for (j = 0; j < argsize; j += 4)
1582 emit_gc_param_slot_def (cfg, sp_offset - j, NULL);
1587 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1588 /* Emit the signature cookie just before the implicit arguments */
1589 emit_sig_cookie (cfg, call, cinfo);
1591 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1595 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1598 if (cinfo->ret.storage == ArgValuetypeInReg) {
1601 else if (cinfo->ret.storage == ArgInIReg) {
1603 /* The return address is passed in a register */
1604 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1605 vtarg->sreg1 = call->inst.dreg;
1606 vtarg->dreg = mono_alloc_ireg (cfg);
1607 MONO_ADD_INS (cfg->cbb, vtarg);
1609 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1610 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1612 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1613 vtarg->type = STACK_MP;
1614 vtarg->sreg1 = call->vret_var->dreg;
1615 MONO_ADD_INS (cfg->cbb, vtarg);
1617 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1620 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1621 if (cinfo->ret.storage != ArgValuetypeInReg)
1622 cinfo->stack_usage -= 4;
1625 call->stack_usage = cinfo->stack_usage;
1626 cfg->arch.param_area_size = MAX (cfg->arch.param_area_size, sp_offset);
1630 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1633 int size = ins->backend.size;
1636 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1637 arg->sreg1 = src->dreg;
1639 MONO_ADD_INS (cfg->cbb, arg);
1640 } else if (size <= 20) {
1641 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1642 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1644 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1645 arg->inst_basereg = src->dreg;
1646 arg->inst_offset = 0;
1647 arg->inst_imm = size;
1649 MONO_ADD_INS (cfg->cbb, arg);
1654 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1656 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1659 if (ret->type == MONO_TYPE_R4) {
1660 if (COMPILE_LLVM (cfg))
1661 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1664 } else if (ret->type == MONO_TYPE_R8) {
1665 if (COMPILE_LLVM (cfg))
1666 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1669 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1670 if (COMPILE_LLVM (cfg))
1671 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1673 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1674 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1680 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1684 * Allow tracing to work with this interface (with an optional argument)
1687 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1691 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1692 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1694 /* if some args are passed in registers, we need to save them here */
1695 x86_push_reg (code, X86_EBP);
1697 if (cfg->compile_aot) {
1698 x86_push_imm (code, cfg->method);
1699 x86_mov_reg_imm (code, X86_EAX, func);
1700 x86_call_reg (code, X86_EAX);
1702 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1703 x86_push_imm (code, cfg->method);
1704 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1705 x86_call_code (code, 0);
1707 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1721 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1724 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1725 MonoMethod *method = cfg->method;
1726 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1728 switch (ret_type->type) {
1729 case MONO_TYPE_VOID:
1730 /* special case string .ctor icall */
1731 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1732 save_mode = SAVE_EAX;
1733 stack_usage = enable_arguments ? 8 : 4;
1735 save_mode = SAVE_NONE;
1739 save_mode = SAVE_EAX_EDX;
1740 stack_usage = enable_arguments ? 16 : 8;
1744 save_mode = SAVE_FP;
1745 stack_usage = enable_arguments ? 16 : 8;
1747 case MONO_TYPE_GENERICINST:
1748 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1749 save_mode = SAVE_EAX;
1750 stack_usage = enable_arguments ? 8 : 4;
1754 case MONO_TYPE_VALUETYPE:
1755 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1756 save_mode = SAVE_STRUCT;
1757 stack_usage = enable_arguments ? 4 : 0;
1760 save_mode = SAVE_EAX;
1761 stack_usage = enable_arguments ? 8 : 4;
1765 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1767 switch (save_mode) {
1769 x86_push_reg (code, X86_EDX);
1770 x86_push_reg (code, X86_EAX);
1771 if (enable_arguments) {
1772 x86_push_reg (code, X86_EDX);
1773 x86_push_reg (code, X86_EAX);
1778 x86_push_reg (code, X86_EAX);
1779 if (enable_arguments) {
1780 x86_push_reg (code, X86_EAX);
1785 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1786 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1787 if (enable_arguments) {
1788 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1789 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1794 if (enable_arguments) {
1795 x86_push_membase (code, X86_EBP, 8);
1804 if (cfg->compile_aot) {
1805 x86_push_imm (code, method);
1806 x86_mov_reg_imm (code, X86_EAX, func);
1807 x86_call_reg (code, X86_EAX);
1809 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1810 x86_push_imm (code, method);
1811 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1812 x86_call_code (code, 0);
1815 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1817 switch (save_mode) {
1819 x86_pop_reg (code, X86_EAX);
1820 x86_pop_reg (code, X86_EDX);
1823 x86_pop_reg (code, X86_EAX);
1826 x86_fld_membase (code, X86_ESP, 0, TRUE);
1827 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1834 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1839 #define EMIT_COND_BRANCH(ins,cond,sign) \
1840 if (ins->inst_true_bb->native_offset) { \
1841 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1843 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1844 if ((cfg->opt & MONO_OPT_BRANCH) && \
1845 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1846 x86_branch8 (code, cond, 0, sign); \
1848 x86_branch32 (code, cond, 0, sign); \
1852 * Emit an exception if condition is fail and
1853 * if possible do a directly branch to target
1855 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1857 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1858 if (tins == NULL) { \
1859 mono_add_patch_info (cfg, code - cfg->native_code, \
1860 MONO_PATCH_INFO_EXC, exc_name); \
1861 x86_branch32 (code, cond, 0, signed); \
1863 EMIT_COND_BRANCH (tins, cond, signed); \
1867 #define EMIT_FPCOMPARE(code) do { \
1868 x86_fcompp (code); \
1869 x86_fnstsw (code); \
1874 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1876 gboolean needs_paddings = TRUE;
1879 if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
1881 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1883 if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && strstr (cfg->method->name, info->name))
1884 needs_paddings = FALSE; /* A call to the wrapped function */
1888 if (cfg->compile_aot)
1889 needs_paddings = FALSE;
1890 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1891 This is required for code patching to be safe on SMP machines.
1893 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1894 #ifndef __native_client_codegen__
1895 if (needs_paddings && pad_size)
1896 x86_padding (code, 4 - pad_size);
1899 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1900 x86_call_code (code, 0);
1905 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1908 * mono_peephole_pass_1:
1910 * Perform peephole opts which should/can be performed before local regalloc
1913 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1917 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1918 MonoInst *last_ins = ins->prev;
1920 switch (ins->opcode) {
1923 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1925 * X86_LEA is like ADD, but doesn't have the
1926 * sreg1==dreg restriction.
1928 ins->opcode = OP_X86_LEA_MEMBASE;
1929 ins->inst_basereg = ins->sreg1;
1930 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1931 ins->opcode = OP_X86_INC_REG;
1935 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1936 ins->opcode = OP_X86_LEA_MEMBASE;
1937 ins->inst_basereg = ins->sreg1;
1938 ins->inst_imm = -ins->inst_imm;
1939 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1940 ins->opcode = OP_X86_DEC_REG;
1942 case OP_COMPARE_IMM:
1943 case OP_ICOMPARE_IMM:
1944 /* OP_COMPARE_IMM (reg, 0)
1946 * OP_X86_TEST_NULL (reg)
1949 ins->opcode = OP_X86_TEST_NULL;
1951 case OP_X86_COMPARE_MEMBASE_IMM:
1953 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1954 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1956 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1957 * OP_COMPARE_IMM reg, imm
1959 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1961 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1962 ins->inst_basereg == last_ins->inst_destbasereg &&
1963 ins->inst_offset == last_ins->inst_offset) {
1964 ins->opcode = OP_COMPARE_IMM;
1965 ins->sreg1 = last_ins->sreg1;
1967 /* check if we can remove cmp reg,0 with test null */
1969 ins->opcode = OP_X86_TEST_NULL;
1973 case OP_X86_PUSH_MEMBASE:
1974 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1975 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1976 ins->inst_basereg == last_ins->inst_destbasereg &&
1977 ins->inst_offset == last_ins->inst_offset) {
1978 ins->opcode = OP_X86_PUSH;
1979 ins->sreg1 = last_ins->sreg1;
1984 mono_peephole_ins (bb, ins);
1989 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1993 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1994 switch (ins->opcode) {
1996 /* reg = 0 -> XOR (reg, reg) */
1997 /* XOR sets cflags on x86, so we cant do it always */
1998 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2001 ins->opcode = OP_IXOR;
2002 ins->sreg1 = ins->dreg;
2003 ins->sreg2 = ins->dreg;
2006 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2007 * since it takes 3 bytes instead of 7.
2009 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2010 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2011 ins2->opcode = OP_STORE_MEMBASE_REG;
2012 ins2->sreg1 = ins->dreg;
2014 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2015 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2016 ins2->sreg1 = ins->dreg;
2018 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2019 /* Continue iteration */
2028 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2029 ins->opcode = OP_X86_INC_REG;
2033 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2034 ins->opcode = OP_X86_DEC_REG;
2038 mono_peephole_ins (bb, ins);
2043 * mono_arch_lowering_pass:
2045 * Converts complex opcodes into simpler ones so that each IR instruction
2046 * corresponds to one machine instruction.
2049 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2051 MonoInst *ins, *next;
2054 * FIXME: Need to add more instructions, but the current machine
2055 * description can't model some parts of the composite instructions like
2058 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2059 switch (ins->opcode) {
2062 case OP_IDIV_UN_IMM:
2063 case OP_IREM_UN_IMM:
2065 * Keep the cases where we could generated optimized code, otherwise convert
2066 * to the non-imm variant.
2068 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2070 mono_decompose_op_imm (cfg, bb, ins);
2077 bb->max_vreg = cfg->next_vreg;
2081 branch_cc_table [] = {
2082 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2083 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2084 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2087 /* Maps CMP_... constants to X86_CC_... constants */
2090 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2091 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2095 cc_signed_table [] = {
2096 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2097 FALSE, FALSE, FALSE, FALSE
2100 static unsigned char*
2101 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2103 #define XMM_TEMP_REG 0
2104 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2105 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2106 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2107 /* optimize by assigning a local var for this use so we avoid
2108 * the stack manipulations */
2109 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2110 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2111 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2112 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2113 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2115 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2117 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2120 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2121 x86_fnstcw_membase(code, X86_ESP, 0);
2122 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2123 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2124 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2125 x86_fldcw_membase (code, X86_ESP, 2);
2127 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2128 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2129 x86_pop_reg (code, dreg);
2130 /* FIXME: need the high register
2131 * x86_pop_reg (code, dreg_high);
2134 x86_push_reg (code, X86_EAX); // SP = SP - 4
2135 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2136 x86_pop_reg (code, dreg);
2138 x86_fldcw_membase (code, X86_ESP, 0);
2139 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2142 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2144 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2148 static unsigned char*
2149 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2151 int sreg = tree->sreg1;
2152 int need_touch = FALSE;
2154 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2163 * If requested stack size is larger than one page,
2164 * perform stack-touch operation
2167 * Generate stack probe code.
2168 * Under Windows, it is necessary to allocate one page at a time,
2169 * "touching" stack after each successful sub-allocation. This is
2170 * because of the way stack growth is implemented - there is a
2171 * guard page before the lowest stack page that is currently commited.
2172 * Stack normally grows sequentially so OS traps access to the
2173 * guard page and commits more pages when needed.
2175 x86_test_reg_imm (code, sreg, ~0xFFF);
2176 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2178 br[2] = code; /* loop */
2179 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2180 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2183 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2184 * that follows only initializes the last part of the area.
2186 /* Same as the init code below with size==0x1000 */
2187 if (tree->flags & MONO_INST_INIT) {
2188 x86_push_reg (code, X86_EAX);
2189 x86_push_reg (code, X86_ECX);
2190 x86_push_reg (code, X86_EDI);
2191 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2192 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2193 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2195 x86_prefix (code, X86_REP_PREFIX);
2197 x86_pop_reg (code, X86_EDI);
2198 x86_pop_reg (code, X86_ECX);
2199 x86_pop_reg (code, X86_EAX);
2202 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2203 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2204 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2205 x86_patch (br[3], br[2]);
2206 x86_test_reg_reg (code, sreg, sreg);
2207 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2208 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2210 br[1] = code; x86_jump8 (code, 0);
2212 x86_patch (br[0], code);
2213 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2214 x86_patch (br[1], code);
2215 x86_patch (br[4], code);
2218 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2220 if (tree->flags & MONO_INST_INIT) {
2222 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2223 x86_push_reg (code, X86_EAX);
2226 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2227 x86_push_reg (code, X86_ECX);
2230 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2231 x86_push_reg (code, X86_EDI);
2235 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2236 if (sreg != X86_ECX)
2237 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2238 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2240 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2242 x86_prefix (code, X86_REP_PREFIX);
2245 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2246 x86_pop_reg (code, X86_EDI);
2247 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2248 x86_pop_reg (code, X86_ECX);
2249 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2250 x86_pop_reg (code, X86_EAX);
2257 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2259 /* Move return value to the target register */
2260 switch (ins->opcode) {
2263 case OP_CALL_MEMBASE:
2264 if (ins->dreg != X86_EAX)
2265 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2275 static int tls_gs_offset;
2279 mono_x86_have_tls_get (void)
2282 static gboolean have_tls_get = FALSE;
2283 static gboolean inited = FALSE;
2286 return have_tls_get;
2288 guint32 *ins = (guint32*)pthread_getspecific;
2290 * We're looking for these two instructions:
2292 * mov 0x4(%esp),%eax
2293 * mov %gs:[offset](,%eax,4),%eax
2295 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2296 tls_gs_offset = ins [2];
2300 return have_tls_get;
2301 #elif defined(TARGET_ANDROID)
2309 * mono_x86_emit_tls_get:
2310 * @code: buffer to store code to
2311 * @dreg: hard register where to place the result
2312 * @tls_offset: offset info
2314 * mono_x86_emit_tls_get emits in @code the native code that puts in
2315 * the dreg register the item in the thread local storage identified
2318 * Returns: a pointer to the end of the stored code
2321 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2323 #if defined(__APPLE__)
2324 x86_prefix (code, X86_GS_PREFIX);
2325 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2326 #elif defined(TARGET_WIN32)
2328 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2329 * Journal and/or a disassembly of the TlsGet () function.
2331 g_assert (tls_offset < 64);
2332 x86_prefix (code, X86_FS_PREFIX);
2333 x86_mov_reg_mem (code, dreg, 0x18, 4);
2334 /* Dunno what this does but TlsGetValue () contains it */
2335 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2336 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2338 if (optimize_for_xen) {
2339 x86_prefix (code, X86_GS_PREFIX);
2340 x86_mov_reg_mem (code, dreg, 0, 4);
2341 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2343 x86_prefix (code, X86_GS_PREFIX);
2344 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2351 * emit_load_volatile_arguments:
2353 * Load volatile arguments from the stack to the original input registers.
2354 * Required before a tail call.
2357 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2359 MonoMethod *method = cfg->method;
2360 MonoMethodSignature *sig;
2365 /* FIXME: Generate intermediate code instead */
2367 sig = mono_method_signature (method);
2369 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2371 /* This is the opposite of the code in emit_prolog */
2373 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2374 ArgInfo *ainfo = cinfo->args + i;
2376 inst = cfg->args [i];
2378 if (sig->hasthis && (i == 0))
2379 arg_type = &mono_defaults.object_class->byval_arg;
2381 arg_type = sig->params [i - sig->hasthis];
2384 * On x86, the arguments are either in their original stack locations, or in
2387 if (inst->opcode == OP_REGVAR) {
2388 g_assert (ainfo->storage == ArgOnStack);
2390 x86_mov_membase_reg (code, X86_EBP, inst->inst_offset, inst->dreg, 4);
2397 #define REAL_PRINT_REG(text,reg) \
2398 mono_assert (reg >= 0); \
2399 x86_push_reg (code, X86_EAX); \
2400 x86_push_reg (code, X86_EDX); \
2401 x86_push_reg (code, X86_ECX); \
2402 x86_push_reg (code, reg); \
2403 x86_push_imm (code, reg); \
2404 x86_push_imm (code, text " %d %p\n"); \
2405 x86_mov_reg_imm (code, X86_EAX, printf); \
2406 x86_call_reg (code, X86_EAX); \
2407 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2408 x86_pop_reg (code, X86_ECX); \
2409 x86_pop_reg (code, X86_EDX); \
2410 x86_pop_reg (code, X86_EAX);
2412 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2413 #ifdef __native__client_codegen__
2414 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2417 /* benchmark and set based on cpu */
2418 #define LOOP_ALIGNMENT 8
2419 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2423 #if defined(__native_client__) || defined(__native_client_codegen__)
2427 #ifdef __native_client_gc__
2428 __nacl_suspend_thread_if_needed();
2434 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2439 guint8 *code = cfg->native_code + cfg->code_len;
2442 if (cfg->opt & MONO_OPT_LOOP) {
2443 int pad, align = LOOP_ALIGNMENT;
2444 /* set alignment depending on cpu */
2445 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2447 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2448 x86_padding (code, pad);
2449 cfg->code_len += pad;
2450 bb->native_offset = cfg->code_len;
2453 #ifdef __native_client_codegen__
2455 /* For Native Client, all indirect call/jump targets must be */
2456 /* 32-byte aligned. Exception handler blocks are jumped to */
2457 /* indirectly as well. */
2458 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2459 (bb->flags & BB_EXCEPTION_HANDLER);
2461 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2462 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2463 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2464 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2465 cfg->code_len += pad;
2466 bb->native_offset = cfg->code_len;
2469 #endif /* __native_client_codegen__ */
2470 if (cfg->verbose_level > 2)
2471 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2473 cpos = bb->max_offset;
2475 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2476 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2477 g_assert (!cfg->compile_aot);
2480 cov->data [bb->dfn].cil_code = bb->cil_code;
2481 /* this is not thread save, but good enough */
2482 x86_inc_mem (code, &cov->data [bb->dfn].count);
2485 offset = code - cfg->native_code;
2487 mono_debug_open_block (cfg, bb, offset);
2489 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2490 x86_breakpoint (code);
2492 MONO_BB_FOR_EACH_INS (bb, ins) {
2493 offset = code - cfg->native_code;
2495 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2497 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2499 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2500 cfg->code_size *= 2;
2501 cfg->native_code = mono_realloc_native_code(cfg);
2502 code = cfg->native_code + offset;
2503 cfg->stat_code_reallocs++;
2506 if (cfg->debug_info)
2507 mono_debug_record_line_number (cfg, ins, offset);
2509 switch (ins->opcode) {
2511 x86_mul_reg (code, ins->sreg2, TRUE);
2514 x86_mul_reg (code, ins->sreg2, FALSE);
2516 case OP_X86_SETEQ_MEMBASE:
2517 case OP_X86_SETNE_MEMBASE:
2518 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2519 ins->inst_basereg, ins->inst_offset, TRUE);
2521 case OP_STOREI1_MEMBASE_IMM:
2522 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2524 case OP_STOREI2_MEMBASE_IMM:
2525 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2527 case OP_STORE_MEMBASE_IMM:
2528 case OP_STOREI4_MEMBASE_IMM:
2529 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2531 case OP_STOREI1_MEMBASE_REG:
2532 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2534 case OP_STOREI2_MEMBASE_REG:
2535 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2537 case OP_STORE_MEMBASE_REG:
2538 case OP_STOREI4_MEMBASE_REG:
2539 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2541 case OP_STORE_MEM_IMM:
2542 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2545 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2549 /* These are created by the cprop pass so they use inst_imm as the source */
2550 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2553 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2556 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2558 case OP_LOAD_MEMBASE:
2559 case OP_LOADI4_MEMBASE:
2560 case OP_LOADU4_MEMBASE:
2561 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2563 case OP_LOADU1_MEMBASE:
2564 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2566 case OP_LOADI1_MEMBASE:
2567 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2569 case OP_LOADU2_MEMBASE:
2570 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2572 case OP_LOADI2_MEMBASE:
2573 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2575 case OP_ICONV_TO_I1:
2577 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2579 case OP_ICONV_TO_I2:
2581 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2583 case OP_ICONV_TO_U1:
2584 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2586 case OP_ICONV_TO_U2:
2587 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2591 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2593 case OP_COMPARE_IMM:
2594 case OP_ICOMPARE_IMM:
2595 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2597 case OP_X86_COMPARE_MEMBASE_REG:
2598 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2600 case OP_X86_COMPARE_MEMBASE_IMM:
2601 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2603 case OP_X86_COMPARE_MEMBASE8_IMM:
2604 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2606 case OP_X86_COMPARE_REG_MEMBASE:
2607 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2609 case OP_X86_COMPARE_MEM_IMM:
2610 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2612 case OP_X86_TEST_NULL:
2613 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2615 case OP_X86_ADD_MEMBASE_IMM:
2616 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2618 case OP_X86_ADD_REG_MEMBASE:
2619 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2621 case OP_X86_SUB_MEMBASE_IMM:
2622 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2624 case OP_X86_SUB_REG_MEMBASE:
2625 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2627 case OP_X86_AND_MEMBASE_IMM:
2628 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2630 case OP_X86_OR_MEMBASE_IMM:
2631 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2633 case OP_X86_XOR_MEMBASE_IMM:
2634 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2636 case OP_X86_ADD_MEMBASE_REG:
2637 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2639 case OP_X86_SUB_MEMBASE_REG:
2640 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2642 case OP_X86_AND_MEMBASE_REG:
2643 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2645 case OP_X86_OR_MEMBASE_REG:
2646 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2648 case OP_X86_XOR_MEMBASE_REG:
2649 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2651 case OP_X86_INC_MEMBASE:
2652 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2654 case OP_X86_INC_REG:
2655 x86_inc_reg (code, ins->dreg);
2657 case OP_X86_DEC_MEMBASE:
2658 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2660 case OP_X86_DEC_REG:
2661 x86_dec_reg (code, ins->dreg);
2663 case OP_X86_MUL_REG_MEMBASE:
2664 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2666 case OP_X86_AND_REG_MEMBASE:
2667 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2669 case OP_X86_OR_REG_MEMBASE:
2670 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2672 case OP_X86_XOR_REG_MEMBASE:
2673 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2676 x86_breakpoint (code);
2678 case OP_RELAXED_NOP:
2679 x86_prefix (code, X86_REP_PREFIX);
2687 case OP_DUMMY_STORE:
2688 case OP_NOT_REACHED:
2691 case OP_SEQ_POINT: {
2694 if (cfg->compile_aot)
2698 * Read from the single stepping trigger page. This will cause a
2699 * SIGSEGV when single stepping is enabled.
2700 * We do this _before_ the breakpoint, so single stepping after
2701 * a breakpoint is hit will step to the next IL offset.
2703 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2704 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2706 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2709 * A placeholder for a possible breakpoint inserted by
2710 * mono_arch_set_breakpoint ().
2712 for (i = 0; i < 6; ++i)
2719 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2723 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2728 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2732 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2737 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2741 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2746 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2750 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2753 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2757 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2762 * The code is the same for div/rem, the allocator will allocate dreg
2763 * to RAX/RDX as appropriate.
2765 if (ins->sreg2 == X86_EDX) {
2766 /* cdq clobbers this */
2767 x86_push_reg (code, ins->sreg2);
2769 x86_div_membase (code, X86_ESP, 0, TRUE);
2770 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2773 x86_div_reg (code, ins->sreg2, TRUE);
2778 if (ins->sreg2 == X86_EDX) {
2779 x86_push_reg (code, ins->sreg2);
2780 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2781 x86_div_membase (code, X86_ESP, 0, FALSE);
2782 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2784 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2785 x86_div_reg (code, ins->sreg2, FALSE);
2789 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2791 x86_div_reg (code, ins->sreg2, TRUE);
2794 int power = mono_is_power_of_two (ins->inst_imm);
2796 g_assert (ins->sreg1 == X86_EAX);
2797 g_assert (ins->dreg == X86_EAX);
2798 g_assert (power >= 0);
2801 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2803 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2805 * If the divident is >= 0, this does not nothing. If it is positive, it
2806 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2808 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2809 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2810 } else if (power == 0) {
2811 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2813 /* Based on gcc code */
2815 /* Add compensation for negative dividents */
2817 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2818 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2819 /* Compute remainder */
2820 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2821 /* Remove compensation */
2822 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2827 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2831 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2834 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2838 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2841 g_assert (ins->sreg2 == X86_ECX);
2842 x86_shift_reg (code, X86_SHL, ins->dreg);
2845 g_assert (ins->sreg2 == X86_ECX);
2846 x86_shift_reg (code, X86_SAR, ins->dreg);
2850 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2853 case OP_ISHR_UN_IMM:
2854 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2857 g_assert (ins->sreg2 == X86_ECX);
2858 x86_shift_reg (code, X86_SHR, ins->dreg);
2862 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2865 guint8 *jump_to_end;
2867 /* handle shifts below 32 bits */
2868 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2869 x86_shift_reg (code, X86_SHL, ins->sreg1);
2871 x86_test_reg_imm (code, X86_ECX, 32);
2872 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2874 /* handle shift over 32 bit */
2875 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2876 x86_clear_reg (code, ins->sreg1);
2878 x86_patch (jump_to_end, code);
2882 guint8 *jump_to_end;
2884 /* handle shifts below 32 bits */
2885 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2886 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2888 x86_test_reg_imm (code, X86_ECX, 32);
2889 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2891 /* handle shifts over 31 bits */
2892 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2893 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2895 x86_patch (jump_to_end, code);
2899 guint8 *jump_to_end;
2901 /* handle shifts below 32 bits */
2902 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2903 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2905 x86_test_reg_imm (code, X86_ECX, 32);
2906 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2908 /* handle shifts over 31 bits */
2909 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2910 x86_clear_reg (code, ins->backend.reg3);
2912 x86_patch (jump_to_end, code);
2916 if (ins->inst_imm >= 32) {
2917 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2918 x86_clear_reg (code, ins->sreg1);
2919 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2921 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2922 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2926 if (ins->inst_imm >= 32) {
2927 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2928 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2929 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2931 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2932 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2935 case OP_LSHR_UN_IMM:
2936 if (ins->inst_imm >= 32) {
2937 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2938 x86_clear_reg (code, ins->backend.reg3);
2939 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2941 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2942 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2946 x86_not_reg (code, ins->sreg1);
2949 x86_neg_reg (code, ins->sreg1);
2953 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2957 switch (ins->inst_imm) {
2961 if (ins->dreg != ins->sreg1)
2962 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2963 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2966 /* LEA r1, [r2 + r2*2] */
2967 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2970 /* LEA r1, [r2 + r2*4] */
2971 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2974 /* LEA r1, [r2 + r2*2] */
2976 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2977 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2980 /* LEA r1, [r2 + r2*8] */
2981 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2984 /* LEA r1, [r2 + r2*4] */
2986 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2987 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2990 /* LEA r1, [r2 + r2*2] */
2992 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2993 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2996 /* LEA r1, [r2 + r2*4] */
2997 /* LEA r1, [r1 + r1*4] */
2998 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2999 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3002 /* LEA r1, [r2 + r2*4] */
3004 /* LEA r1, [r1 + r1*4] */
3005 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3006 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3007 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3010 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3015 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3016 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3018 case OP_IMUL_OVF_UN: {
3019 /* the mul operation and the exception check should most likely be split */
3020 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3021 /*g_assert (ins->sreg2 == X86_EAX);
3022 g_assert (ins->dreg == X86_EAX);*/
3023 if (ins->sreg2 == X86_EAX) {
3024 non_eax_reg = ins->sreg1;
3025 } else if (ins->sreg1 == X86_EAX) {
3026 non_eax_reg = ins->sreg2;
3028 /* no need to save since we're going to store to it anyway */
3029 if (ins->dreg != X86_EAX) {
3031 x86_push_reg (code, X86_EAX);
3033 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3034 non_eax_reg = ins->sreg2;
3036 if (ins->dreg == X86_EDX) {
3039 x86_push_reg (code, X86_EAX);
3041 } else if (ins->dreg != X86_EAX) {
3043 x86_push_reg (code, X86_EDX);
3045 x86_mul_reg (code, non_eax_reg, FALSE);
3046 /* save before the check since pop and mov don't change the flags */
3047 if (ins->dreg != X86_EAX)
3048 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3050 x86_pop_reg (code, X86_EDX);
3052 x86_pop_reg (code, X86_EAX);
3053 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3057 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3060 g_assert_not_reached ();
3061 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3062 x86_mov_reg_imm (code, ins->dreg, 0);
3065 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3066 x86_mov_reg_imm (code, ins->dreg, 0);
3068 case OP_LOAD_GOTADDR:
3069 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3070 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3073 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3074 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3076 case OP_X86_PUSH_GOT_ENTRY:
3077 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3078 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3081 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3085 * Note: this 'frame destruction' logic is useful for tail calls, too.
3086 * Keep in sync with the code in emit_epilog.
3090 /* FIXME: no tracing support... */
3091 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3092 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3093 /* reset offset to make max_len work */
3094 offset = code - cfg->native_code;
3096 g_assert (!cfg->method->save_lmf);
3098 code = emit_load_volatile_arguments (cfg, code);
3100 if (cfg->used_int_regs & (1 << X86_EBX))
3102 if (cfg->used_int_regs & (1 << X86_EDI))
3104 if (cfg->used_int_regs & (1 << X86_ESI))
3107 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
3109 if (cfg->used_int_regs & (1 << X86_ESI))
3110 x86_pop_reg (code, X86_ESI);
3111 if (cfg->used_int_regs & (1 << X86_EDI))
3112 x86_pop_reg (code, X86_EDI);
3113 if (cfg->used_int_regs & (1 << X86_EBX))
3114 x86_pop_reg (code, X86_EBX);
3116 /* restore ESP/EBP */
3118 offset = code - cfg->native_code;
3119 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3120 x86_jump32 (code, 0);
3122 cfg->disable_aot = TRUE;
3126 MonoCallInst *call = (MonoCallInst*)ins;
3129 /* FIXME: no tracing support... */
3130 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3131 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3132 /* reset offset to make max_len work */
3133 offset = code - cfg->native_code;
3135 g_assert (!cfg->method->save_lmf);
3137 //code = emit_load_volatile_arguments (cfg, code);
3139 /* restore callee saved registers */
3140 for (i = 0; i < X86_NREG; ++i)
3141 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3143 if (cfg->used_int_regs & (1 << X86_ESI)) {
3144 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3147 if (cfg->used_int_regs & (1 << X86_EDI)) {
3148 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3151 if (cfg->used_int_regs & (1 << X86_EBX)) {
3152 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3156 /* Copy arguments on the stack to our argument area */
3157 for (i = 0; i < call->stack_usage; i += 4) {
3158 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3159 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3162 /* restore ESP/EBP */
3164 offset = code - cfg->native_code;
3165 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3166 x86_jump32 (code, 0);
3168 ins->flags |= MONO_INST_GC_CALLSITE;
3169 cfg->disable_aot = TRUE;
3173 /* ensure ins->sreg1 is not NULL
3174 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3175 * cmp DWORD PTR [eax], 0
3177 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3180 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3181 x86_push_reg (code, hreg);
3182 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3183 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3184 x86_pop_reg (code, hreg);
3193 call = (MonoCallInst*)ins;
3194 if (ins->flags & MONO_INST_HAS_METHOD)
3195 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3197 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3198 ins->flags |= MONO_INST_GC_CALLSITE;
3199 ins->backend.pc_offset = code - cfg->native_code;
3200 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3201 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
3202 * bytes to pop, we want to use pops. GCC does this (note it won't happen
3203 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
3204 * smart enough to do that optimization yet
3206 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
3207 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
3208 * (most likely from locality benefits). People with other processors should
3209 * check on theirs to see what happens.
3211 if (call->stack_usage == 4) {
3212 /* we want to use registers that won't get used soon, so use
3213 * ecx, as eax will get allocated first. edx is used by long calls,
3214 * so we can't use that.
3217 x86_pop_reg (code, X86_ECX);
3219 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3222 code = emit_move_return_value (cfg, ins, code);
3228 case OP_VOIDCALL_REG:
3230 call = (MonoCallInst*)ins;
3231 x86_call_reg (code, ins->sreg1);
3232 ins->flags |= MONO_INST_GC_CALLSITE;
3233 ins->backend.pc_offset = code - cfg->native_code;
3234 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3235 if (call->stack_usage == 4)
3236 x86_pop_reg (code, X86_ECX);
3238 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3240 code = emit_move_return_value (cfg, ins, code);
3242 case OP_FCALL_MEMBASE:
3243 case OP_LCALL_MEMBASE:
3244 case OP_VCALL_MEMBASE:
3245 case OP_VCALL2_MEMBASE:
3246 case OP_VOIDCALL_MEMBASE:
3247 case OP_CALL_MEMBASE:
3248 call = (MonoCallInst*)ins;
3250 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3251 ins->flags |= MONO_INST_GC_CALLSITE;
3252 ins->backend.pc_offset = code - cfg->native_code;
3253 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3254 if (call->stack_usage == 4)
3255 x86_pop_reg (code, X86_ECX);
3257 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3259 code = emit_move_return_value (cfg, ins, code);
3262 x86_push_reg (code, ins->sreg1);
3264 case OP_X86_PUSH_IMM:
3265 x86_push_imm (code, ins->inst_imm);
3267 case OP_X86_PUSH_MEMBASE:
3268 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
3270 case OP_X86_PUSH_OBJ:
3271 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
3272 x86_push_reg (code, X86_EDI);
3273 x86_push_reg (code, X86_ESI);
3274 x86_push_reg (code, X86_ECX);
3275 if (ins->inst_offset)
3276 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
3278 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
3279 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
3280 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
3282 x86_prefix (code, X86_REP_PREFIX);
3284 x86_pop_reg (code, X86_ECX);
3285 x86_pop_reg (code, X86_ESI);
3286 x86_pop_reg (code, X86_EDI);
3289 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3291 case OP_X86_LEA_MEMBASE:
3292 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3295 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3298 /* keep alignment */
3299 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3300 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3301 code = mono_emit_stack_alloc (code, ins);
3302 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3304 case OP_LOCALLOC_IMM: {
3305 guint32 size = ins->inst_imm;
3306 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3308 if (ins->flags & MONO_INST_INIT) {
3309 /* FIXME: Optimize this */
3310 x86_mov_reg_imm (code, ins->dreg, size);
3311 ins->sreg1 = ins->dreg;
3313 code = mono_emit_stack_alloc (code, ins);
3314 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3316 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3317 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3322 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3323 x86_push_reg (code, ins->sreg1);
3324 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3325 (gpointer)"mono_arch_throw_exception");
3326 ins->flags |= MONO_INST_GC_CALLSITE;
3327 ins->backend.pc_offset = code - cfg->native_code;
3331 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3332 x86_push_reg (code, ins->sreg1);
3333 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3334 (gpointer)"mono_arch_rethrow_exception");
3335 ins->flags |= MONO_INST_GC_CALLSITE;
3336 ins->backend.pc_offset = code - cfg->native_code;
3339 case OP_CALL_HANDLER:
3340 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3341 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3342 x86_call_imm (code, 0);
3343 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3344 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3346 case OP_START_HANDLER: {
3347 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3348 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3351 case OP_ENDFINALLY: {
3352 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3353 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3357 case OP_ENDFILTER: {
3358 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3359 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3360 /* The local allocator will put the result into EAX */
3366 ins->inst_c0 = code - cfg->native_code;
3369 if (ins->inst_target_bb->native_offset) {
3370 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3372 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3373 if ((cfg->opt & MONO_OPT_BRANCH) &&
3374 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3375 x86_jump8 (code, 0);
3377 x86_jump32 (code, 0);
3381 x86_jump_reg (code, ins->sreg1);
3394 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3395 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3397 case OP_COND_EXC_EQ:
3398 case OP_COND_EXC_NE_UN:
3399 case OP_COND_EXC_LT:
3400 case OP_COND_EXC_LT_UN:
3401 case OP_COND_EXC_GT:
3402 case OP_COND_EXC_GT_UN:
3403 case OP_COND_EXC_GE:
3404 case OP_COND_EXC_GE_UN:
3405 case OP_COND_EXC_LE:
3406 case OP_COND_EXC_LE_UN:
3407 case OP_COND_EXC_IEQ:
3408 case OP_COND_EXC_INE_UN:
3409 case OP_COND_EXC_ILT:
3410 case OP_COND_EXC_ILT_UN:
3411 case OP_COND_EXC_IGT:
3412 case OP_COND_EXC_IGT_UN:
3413 case OP_COND_EXC_IGE:
3414 case OP_COND_EXC_IGE_UN:
3415 case OP_COND_EXC_ILE:
3416 case OP_COND_EXC_ILE_UN:
3417 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3419 case OP_COND_EXC_OV:
3420 case OP_COND_EXC_NO:
3422 case OP_COND_EXC_NC:
3423 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3425 case OP_COND_EXC_IOV:
3426 case OP_COND_EXC_INO:
3427 case OP_COND_EXC_IC:
3428 case OP_COND_EXC_INC:
3429 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3441 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3449 case OP_CMOV_INE_UN:
3450 case OP_CMOV_IGE_UN:
3451 case OP_CMOV_IGT_UN:
3452 case OP_CMOV_ILE_UN:
3453 case OP_CMOV_ILT_UN:
3454 g_assert (ins->dreg == ins->sreg1);
3455 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3458 /* floating point opcodes */
3460 double d = *(double *)ins->inst_p0;
3462 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3464 } else if (d == 1.0) {
3467 if (cfg->compile_aot) {
3468 guint32 *val = (guint32*)&d;
3469 x86_push_imm (code, val [1]);
3470 x86_push_imm (code, val [0]);
3471 x86_fld_membase (code, X86_ESP, 0, TRUE);
3472 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3475 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3476 x86_fld (code, NULL, TRUE);
3482 float f = *(float *)ins->inst_p0;
3484 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3486 } else if (f == 1.0) {
3489 if (cfg->compile_aot) {
3490 guint32 val = *(guint32*)&f;
3491 x86_push_imm (code, val);
3492 x86_fld_membase (code, X86_ESP, 0, FALSE);
3493 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3496 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3497 x86_fld (code, NULL, FALSE);
3502 case OP_STORER8_MEMBASE_REG:
3503 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3505 case OP_LOADR8_MEMBASE:
3506 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3508 case OP_STORER4_MEMBASE_REG:
3509 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3511 case OP_LOADR4_MEMBASE:
3512 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3514 case OP_ICONV_TO_R4:
3515 x86_push_reg (code, ins->sreg1);
3516 x86_fild_membase (code, X86_ESP, 0, FALSE);
3517 /* Change precision */
3518 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3519 x86_fld_membase (code, X86_ESP, 0, FALSE);
3520 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3522 case OP_ICONV_TO_R8:
3523 x86_push_reg (code, ins->sreg1);
3524 x86_fild_membase (code, X86_ESP, 0, FALSE);
3525 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3527 case OP_ICONV_TO_R_UN:
3528 x86_push_imm (code, 0);
3529 x86_push_reg (code, ins->sreg1);
3530 x86_fild_membase (code, X86_ESP, 0, TRUE);
3531 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3533 case OP_X86_FP_LOAD_I8:
3534 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3536 case OP_X86_FP_LOAD_I4:
3537 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3539 case OP_FCONV_TO_R4:
3540 /* Change precision */
3541 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3542 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3543 x86_fld_membase (code, X86_ESP, 0, FALSE);
3544 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3546 case OP_FCONV_TO_I1:
3547 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3549 case OP_FCONV_TO_U1:
3550 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3552 case OP_FCONV_TO_I2:
3553 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3555 case OP_FCONV_TO_U2:
3556 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3558 case OP_FCONV_TO_I4:
3560 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3562 case OP_FCONV_TO_I8:
3563 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3564 x86_fnstcw_membase(code, X86_ESP, 0);
3565 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3566 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3567 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3568 x86_fldcw_membase (code, X86_ESP, 2);
3569 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3570 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3571 x86_pop_reg (code, ins->dreg);
3572 x86_pop_reg (code, ins->backend.reg3);
3573 x86_fldcw_membase (code, X86_ESP, 0);
3574 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3576 case OP_LCONV_TO_R8_2:
3577 x86_push_reg (code, ins->sreg2);
3578 x86_push_reg (code, ins->sreg1);
3579 x86_fild_membase (code, X86_ESP, 0, TRUE);
3580 /* Change precision */
3581 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3582 x86_fld_membase (code, X86_ESP, 0, TRUE);
3583 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3585 case OP_LCONV_TO_R4_2:
3586 x86_push_reg (code, ins->sreg2);
3587 x86_push_reg (code, ins->sreg1);
3588 x86_fild_membase (code, X86_ESP, 0, TRUE);
3589 /* Change precision */
3590 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3591 x86_fld_membase (code, X86_ESP, 0, FALSE);
3592 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3594 case OP_LCONV_TO_R_UN_2: {
3595 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3598 /* load 64bit integer to FP stack */
3599 x86_push_reg (code, ins->sreg2);
3600 x86_push_reg (code, ins->sreg1);
3601 x86_fild_membase (code, X86_ESP, 0, TRUE);
3603 /* test if lreg is negative */
3604 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3605 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3607 /* add correction constant mn */
3608 x86_fld80_mem (code, mn);
3609 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3611 x86_patch (br, code);
3613 /* Change precision */
3614 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3615 x86_fld_membase (code, X86_ESP, 0, TRUE);
3617 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3621 case OP_LCONV_TO_OVF_I:
3622 case OP_LCONV_TO_OVF_I4_2: {
3623 guint8 *br [3], *label [1];
3627 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3629 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3631 /* If the low word top bit is set, see if we are negative */
3632 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3633 /* We are not negative (no top bit set, check for our top word to be zero */
3634 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3635 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3638 /* throw exception */
3639 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3641 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3642 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3643 x86_jump8 (code, 0);
3645 x86_jump32 (code, 0);
3647 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3648 x86_jump32 (code, 0);
3652 x86_patch (br [0], code);
3653 /* our top bit is set, check that top word is 0xfffffff */
3654 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3656 x86_patch (br [1], code);
3657 /* nope, emit exception */
3658 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3659 x86_patch (br [2], label [0]);
3661 if (ins->dreg != ins->sreg1)
3662 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3666 /* Not needed on the fp stack */
3669 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3672 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3675 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3678 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3686 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3691 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3698 * it really doesn't make sense to inline all this code,
3699 * it's here just to show that things may not be as simple
3702 guchar *check_pos, *end_tan, *pop_jump;
3703 x86_push_reg (code, X86_EAX);
3706 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3708 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3709 x86_fstp (code, 0); /* pop the 1.0 */
3711 x86_jump8 (code, 0);
3713 x86_fp_op (code, X86_FADD, 0);
3717 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3719 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3722 x86_patch (pop_jump, code);
3723 x86_fstp (code, 0); /* pop the 1.0 */
3724 x86_patch (check_pos, code);
3725 x86_patch (end_tan, code);
3727 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3728 x86_pop_reg (code, X86_EAX);
3735 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3744 g_assert (cfg->opt & MONO_OPT_CMOV);
3745 g_assert (ins->dreg == ins->sreg1);
3746 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3747 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3750 g_assert (cfg->opt & MONO_OPT_CMOV);
3751 g_assert (ins->dreg == ins->sreg1);
3752 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3753 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3756 g_assert (cfg->opt & MONO_OPT_CMOV);
3757 g_assert (ins->dreg == ins->sreg1);
3758 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3759 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3762 g_assert (cfg->opt & MONO_OPT_CMOV);
3763 g_assert (ins->dreg == ins->sreg1);
3764 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3765 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3771 x86_fxch (code, ins->inst_imm);
3776 x86_push_reg (code, X86_EAX);
3777 /* we need to exchange ST(0) with ST(1) */
3780 /* this requires a loop, because fprem somtimes
3781 * returns a partial remainder */
3783 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3784 /* x86_fprem1 (code); */
3787 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3789 x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3794 x86_pop_reg (code, X86_EAX);
3798 if (cfg->opt & MONO_OPT_FCMOV) {
3799 x86_fcomip (code, 1);
3803 /* this overwrites EAX */
3804 EMIT_FPCOMPARE(code);
3805 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3808 if (cfg->opt & MONO_OPT_FCMOV) {
3809 /* zeroing the register at the start results in
3810 * shorter and faster code (we can also remove the widening op)
3812 guchar *unordered_check;
3813 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3814 x86_fcomip (code, 1);
3816 unordered_check = code;
3817 x86_branch8 (code, X86_CC_P, 0, FALSE);
3818 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3819 x86_patch (unordered_check, code);
3822 if (ins->dreg != X86_EAX)
3823 x86_push_reg (code, X86_EAX);
3825 EMIT_FPCOMPARE(code);
3826 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3827 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3828 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3829 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3831 if (ins->dreg != X86_EAX)
3832 x86_pop_reg (code, X86_EAX);
3836 if (cfg->opt & MONO_OPT_FCMOV) {
3837 /* zeroing the register at the start results in
3838 * shorter and faster code (we can also remove the widening op)
3840 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3841 x86_fcomip (code, 1);
3843 if (ins->opcode == OP_FCLT_UN) {
3844 guchar *unordered_check = code;
3845 guchar *jump_to_end;
3846 x86_branch8 (code, X86_CC_P, 0, FALSE);
3847 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3849 x86_jump8 (code, 0);
3850 x86_patch (unordered_check, code);
3851 x86_inc_reg (code, ins->dreg);
3852 x86_patch (jump_to_end, code);
3854 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3858 if (ins->dreg != X86_EAX)
3859 x86_push_reg (code, X86_EAX);
3861 EMIT_FPCOMPARE(code);
3862 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3863 if (ins->opcode == OP_FCLT_UN) {
3864 guchar *is_not_zero_check, *end_jump;
3865 is_not_zero_check = code;
3866 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3868 x86_jump8 (code, 0);
3869 x86_patch (is_not_zero_check, code);
3870 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3872 x86_patch (end_jump, code);
3874 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3875 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3877 if (ins->dreg != X86_EAX)
3878 x86_pop_reg (code, X86_EAX);
3882 if (cfg->opt & MONO_OPT_FCMOV) {
3883 /* zeroing the register at the start results in
3884 * shorter and faster code (we can also remove the widening op)
3886 guchar *unordered_check;
3887 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3888 x86_fcomip (code, 1);
3890 if (ins->opcode == OP_FCGT) {
3891 unordered_check = code;
3892 x86_branch8 (code, X86_CC_P, 0, FALSE);
3893 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3894 x86_patch (unordered_check, code);
3896 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3900 if (ins->dreg != X86_EAX)
3901 x86_push_reg (code, X86_EAX);
3903 EMIT_FPCOMPARE(code);
3904 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3905 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3906 if (ins->opcode == OP_FCGT_UN) {
3907 guchar *is_not_zero_check, *end_jump;
3908 is_not_zero_check = code;
3909 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3911 x86_jump8 (code, 0);
3912 x86_patch (is_not_zero_check, code);
3913 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3915 x86_patch (end_jump, code);
3917 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3918 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3920 if (ins->dreg != X86_EAX)
3921 x86_pop_reg (code, X86_EAX);
3924 if (cfg->opt & MONO_OPT_FCMOV) {
3925 guchar *jump = code;
3926 x86_branch8 (code, X86_CC_P, 0, TRUE);
3927 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3928 x86_patch (jump, code);
3931 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3932 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3935 /* Branch if C013 != 100 */
3936 if (cfg->opt & MONO_OPT_FCMOV) {
3937 /* branch if !ZF or (PF|CF) */
3938 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3939 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3940 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3943 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3944 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3947 if (cfg->opt & MONO_OPT_FCMOV) {
3948 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3951 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3954 if (cfg->opt & MONO_OPT_FCMOV) {
3955 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3956 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3959 if (ins->opcode == OP_FBLT_UN) {
3960 guchar *is_not_zero_check, *end_jump;
3961 is_not_zero_check = code;
3962 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3964 x86_jump8 (code, 0);
3965 x86_patch (is_not_zero_check, code);
3966 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3968 x86_patch (end_jump, code);
3970 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3974 if (cfg->opt & MONO_OPT_FCMOV) {
3975 if (ins->opcode == OP_FBGT) {
3978 /* skip branch if C1=1 */
3980 x86_branch8 (code, X86_CC_P, 0, FALSE);
3981 /* branch if (C0 | C3) = 1 */
3982 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3983 x86_patch (br1, code);
3985 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3989 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3990 if (ins->opcode == OP_FBGT_UN) {
3991 guchar *is_not_zero_check, *end_jump;
3992 is_not_zero_check = code;
3993 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3995 x86_jump8 (code, 0);
3996 x86_patch (is_not_zero_check, code);
3997 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3999 x86_patch (end_jump, code);
4001 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4004 /* Branch if C013 == 100 or 001 */
4005 if (cfg->opt & MONO_OPT_FCMOV) {
4008 /* skip branch if C1=1 */
4010 x86_branch8 (code, X86_CC_P, 0, FALSE);
4011 /* branch if (C0 | C3) = 1 */
4012 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4013 x86_patch (br1, code);
4016 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4017 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4018 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4019 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4022 /* Branch if C013 == 000 */
4023 if (cfg->opt & MONO_OPT_FCMOV) {
4024 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4027 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4030 /* Branch if C013=000 or 100 */
4031 if (cfg->opt & MONO_OPT_FCMOV) {
4034 /* skip branch if C1=1 */
4036 x86_branch8 (code, X86_CC_P, 0, FALSE);
4037 /* branch if C0=0 */
4038 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4039 x86_patch (br1, code);
4042 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4043 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4044 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4047 /* Branch if C013 != 001 */
4048 if (cfg->opt & MONO_OPT_FCMOV) {
4049 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4050 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4053 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4054 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4058 x86_push_reg (code, X86_EAX);
4061 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4062 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4063 x86_pop_reg (code, X86_EAX);
4065 /* Have to clean up the fp stack before throwing the exception */
4067 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4070 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4072 x86_patch (br1, code);
4076 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4079 case OP_MEMORY_BARRIER: {
4080 /* x86 only needs barrier for StoreLoad and FullBarrier */
4081 switch (ins->backend.memory_barrier_kind) {
4082 case StoreLoadBarrier:
4084 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4085 x86_prefix (code, X86_LOCK_PREFIX);
4086 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4091 case OP_ATOMIC_ADD_I4: {
4092 int dreg = ins->dreg;
4094 if (dreg == ins->inst_basereg) {
4095 x86_push_reg (code, ins->sreg2);
4099 if (dreg != ins->sreg2)
4100 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
4102 x86_prefix (code, X86_LOCK_PREFIX);
4103 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4105 if (dreg != ins->dreg) {
4106 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4107 x86_pop_reg (code, dreg);
4112 case OP_ATOMIC_ADD_NEW_I4: {
4113 int dreg = ins->dreg;
4115 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4116 if (ins->sreg2 == dreg) {
4117 if (dreg == X86_EBX) {
4119 if (ins->inst_basereg == X86_EDI)
4123 if (ins->inst_basereg == X86_EBX)
4126 } else if (ins->inst_basereg == dreg) {
4127 if (dreg == X86_EBX) {
4129 if (ins->sreg2 == X86_EDI)
4133 if (ins->sreg2 == X86_EBX)
4138 if (dreg != ins->dreg) {
4139 x86_push_reg (code, dreg);
4142 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4143 x86_prefix (code, X86_LOCK_PREFIX);
4144 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4145 /* dreg contains the old value, add with sreg2 value */
4146 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4148 if (ins->dreg != dreg) {
4149 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4150 x86_pop_reg (code, dreg);
4155 case OP_ATOMIC_EXCHANGE_I4: {
4157 int sreg2 = ins->sreg2;
4158 int breg = ins->inst_basereg;
4160 /* cmpxchg uses eax as comperand, need to make sure we can use it
4161 * hack to overcome limits in x86 reg allocator
4162 * (req: dreg == eax and sreg2 != eax and breg != eax)
4164 g_assert (ins->dreg == X86_EAX);
4166 /* We need the EAX reg for the cmpxchg */
4167 if (ins->sreg2 == X86_EAX) {
4168 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4169 x86_push_reg (code, sreg2);
4170 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4173 if (breg == X86_EAX) {
4174 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4175 x86_push_reg (code, breg);
4176 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4179 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4181 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4182 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4183 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4184 x86_patch (br [1], br [0]);
4186 if (breg != ins->inst_basereg)
4187 x86_pop_reg (code, breg);
4189 if (ins->sreg2 != sreg2)
4190 x86_pop_reg (code, sreg2);
4194 case OP_ATOMIC_CAS_I4: {
4195 g_assert (ins->dreg == X86_EAX);
4196 g_assert (ins->sreg3 == X86_EAX);
4197 g_assert (ins->sreg1 != X86_EAX);
4198 g_assert (ins->sreg1 != ins->sreg2);
4200 x86_prefix (code, X86_LOCK_PREFIX);
4201 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4204 case OP_CARD_TABLE_WBARRIER: {
4205 int ptr = ins->sreg1;
4206 int value = ins->sreg2;
4208 int nursery_shift, card_table_shift;
4209 gpointer card_table_mask;
4210 size_t nursery_size;
4211 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4212 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4215 * We need one register we can clobber, we choose EDX and make sreg1
4216 * fixed EAX to work around limitations in the local register allocator.
4217 * sreg2 might get allocated to EDX, but that is not a problem since
4218 * we use it before clobbering EDX.
4220 g_assert (ins->sreg1 == X86_EAX);
4223 * This is the code we produce:
4226 * edx >>= nursery_shift
4227 * cmp edx, (nursery_start >> nursery_shift)
4230 * edx >>= card_table_shift
4231 * card_table[edx] = 1
4235 if (value != X86_EDX)
4236 x86_mov_reg_reg (code, X86_EDX, value, 4);
4237 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4238 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4239 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4240 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4241 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4242 if (card_table_mask)
4243 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4244 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4245 x86_patch (br, code);
4248 #ifdef MONO_ARCH_SIMD_INTRINSICS
4250 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4253 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4256 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4259 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4262 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4265 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4268 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4269 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4272 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4275 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4278 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4281 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4284 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4287 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4290 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4293 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4296 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4299 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4302 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4305 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4308 case OP_PSHUFLEW_HIGH:
4309 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4310 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4312 case OP_PSHUFLEW_LOW:
4313 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4314 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4317 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4318 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4321 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4322 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4325 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4326 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4330 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4333 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4336 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4339 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4342 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4345 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4348 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4349 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4352 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4355 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4358 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4361 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4364 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4367 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4370 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4373 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4376 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4379 case OP_EXTRACT_MASK:
4380 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4384 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4387 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4390 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4394 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4397 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4400 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4403 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4407 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4410 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4413 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4416 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4420 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4423 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4426 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4430 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4433 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4436 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4440 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4443 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4447 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4450 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4453 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4457 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4460 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4463 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4467 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4470 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4473 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4476 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4480 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4483 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4486 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4489 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4492 case OP_PSUM_ABS_DIFF:
4493 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4496 case OP_UNPACK_LOWB:
4497 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4499 case OP_UNPACK_LOWW:
4500 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4502 case OP_UNPACK_LOWD:
4503 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4505 case OP_UNPACK_LOWQ:
4506 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4508 case OP_UNPACK_LOWPS:
4509 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4511 case OP_UNPACK_LOWPD:
4512 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4515 case OP_UNPACK_HIGHB:
4516 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4518 case OP_UNPACK_HIGHW:
4519 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4521 case OP_UNPACK_HIGHD:
4522 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4524 case OP_UNPACK_HIGHQ:
4525 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4527 case OP_UNPACK_HIGHPS:
4528 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4530 case OP_UNPACK_HIGHPD:
4531 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4535 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4538 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4541 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4544 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4547 case OP_PADDB_SAT_UN:
4548 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4550 case OP_PSUBB_SAT_UN:
4551 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4553 case OP_PADDW_SAT_UN:
4554 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4556 case OP_PSUBW_SAT_UN:
4557 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4561 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4564 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4567 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4570 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4574 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4577 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4580 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4582 case OP_PMULW_HIGH_UN:
4583 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4586 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4590 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4593 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4597 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4600 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4604 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4607 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4611 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4614 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4618 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4621 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4625 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4628 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4632 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4635 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4639 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4642 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4646 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4649 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4653 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4655 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4656 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4660 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4662 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4663 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4667 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4669 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4670 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4674 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4676 case OP_EXTRACTX_U2:
4677 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4679 case OP_INSERTX_U1_SLOW:
4680 /*sreg1 is the extracted ireg (scratch)
4681 /sreg2 is the to be inserted ireg (scratch)
4682 /dreg is the xreg to receive the value*/
4684 /*clear the bits from the extracted word*/
4685 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4686 /*shift the value to insert if needed*/
4687 if (ins->inst_c0 & 1)
4688 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4689 /*join them together*/
4690 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4691 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4693 case OP_INSERTX_I4_SLOW:
4694 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4695 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4696 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4699 case OP_INSERTX_R4_SLOW:
4700 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4701 /*TODO if inst_c0 == 0 use movss*/
4702 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4703 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4705 case OP_INSERTX_R8_SLOW:
4706 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4707 if (cfg->verbose_level)
4708 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4710 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4712 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4715 case OP_STOREX_MEMBASE_REG:
4716 case OP_STOREX_MEMBASE:
4717 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4719 case OP_LOADX_MEMBASE:
4720 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4722 case OP_LOADX_ALIGNED_MEMBASE:
4723 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4725 case OP_STOREX_ALIGNED_MEMBASE_REG:
4726 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4728 case OP_STOREX_NTA_MEMBASE_REG:
4729 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4731 case OP_PREFETCH_MEMBASE:
4732 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4736 /*FIXME the peephole pass should have killed this*/
4737 if (ins->dreg != ins->sreg1)
4738 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4741 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4743 case OP_ICONV_TO_R8_RAW:
4744 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4745 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4748 case OP_FCONV_TO_R8_X:
4749 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4750 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4753 case OP_XCONV_R8_TO_I4:
4754 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4755 switch (ins->backend.source_opcode) {
4756 case OP_FCONV_TO_I1:
4757 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4759 case OP_FCONV_TO_U1:
4760 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4762 case OP_FCONV_TO_I2:
4763 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4765 case OP_FCONV_TO_U2:
4766 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4772 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4773 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4774 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4775 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4776 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4777 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4780 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4781 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4782 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4785 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4786 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4789 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4790 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4791 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4794 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4795 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4796 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4800 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4803 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4806 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4809 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4812 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4815 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4818 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4821 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4825 case OP_LIVERANGE_START: {
4826 if (cfg->verbose_level > 1)
4827 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4828 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4831 case OP_LIVERANGE_END: {
4832 if (cfg->verbose_level > 1)
4833 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4834 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4837 case OP_NACL_GC_SAFE_POINT: {
4838 #if defined(__native_client_codegen__)
4839 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
4843 case OP_GC_LIVENESS_DEF:
4844 case OP_GC_LIVENESS_USE:
4845 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4846 ins->backend.pc_offset = code - cfg->native_code;
4848 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4849 ins->backend.pc_offset = code - cfg->native_code;
4850 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4853 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4854 g_assert_not_reached ();
4857 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4858 #ifndef __native_client_codegen__
4859 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4860 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4861 g_assert_not_reached ();
4862 #endif /* __native_client_codegen__ */
4868 cfg->code_len = code - cfg->native_code;
4871 #endif /* DISABLE_JIT */
4874 mono_arch_register_lowlevel_calls (void)
4879 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4881 MonoJumpInfo *patch_info;
4882 gboolean compile_aot = !run_cctors;
4884 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4885 unsigned char *ip = patch_info->ip.i + code;
4886 const unsigned char *target;
4888 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4891 switch (patch_info->type) {
4892 case MONO_PATCH_INFO_BB:
4893 case MONO_PATCH_INFO_LABEL:
4896 /* No need to patch these */
4901 switch (patch_info->type) {
4902 case MONO_PATCH_INFO_IP:
4903 *((gconstpointer *)(ip)) = target;
4905 case MONO_PATCH_INFO_CLASS_INIT: {
4907 /* Might already been changed to a nop */
4908 x86_call_code (code, 0);
4909 x86_patch (ip, target);
4912 case MONO_PATCH_INFO_ABS:
4913 case MONO_PATCH_INFO_METHOD:
4914 case MONO_PATCH_INFO_METHOD_JUMP:
4915 case MONO_PATCH_INFO_INTERNAL_METHOD:
4916 case MONO_PATCH_INFO_BB:
4917 case MONO_PATCH_INFO_LABEL:
4918 case MONO_PATCH_INFO_RGCTX_FETCH:
4919 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
4920 case MONO_PATCH_INFO_MONITOR_ENTER:
4921 case MONO_PATCH_INFO_MONITOR_EXIT:
4922 #if defined(__native_client_codegen__) && defined(__native_client__)
4923 if (nacl_is_code_address (code)) {
4924 /* For tail calls, code is patched after being installed */
4925 /* but not through the normal "patch callsite" method. */
4926 unsigned char buf[kNaClAlignment];
4927 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
4928 unsigned char *_target = target;
4930 /* All patch targets modified in x86_patch */
4931 /* are IP relative. */
4932 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
4933 memcpy (buf, aligned_code, kNaClAlignment);
4934 /* Patch a temp buffer of bundle size, */
4935 /* then install to actual location. */
4936 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
4937 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
4938 g_assert (ret == 0);
4941 x86_patch (ip, target);
4944 x86_patch (ip, target);
4947 case MONO_PATCH_INFO_NONE:
4949 case MONO_PATCH_INFO_R4:
4950 case MONO_PATCH_INFO_R8: {
4951 guint32 offset = mono_arch_get_patch_offset (ip);
4952 *((gconstpointer *)(ip + offset)) = target;
4956 guint32 offset = mono_arch_get_patch_offset (ip);
4957 #if !defined(__native_client__)
4958 *((gconstpointer *)(ip + offset)) = target;
4960 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
4969 mono_arch_emit_prolog (MonoCompile *cfg)
4971 MonoMethod *method = cfg->method;
4973 MonoMethodSignature *sig;
4975 int alloc_size, pos, max_offset, i, cfa_offset;
4977 gboolean need_stack_frame;
4978 #ifdef __native_client_codegen__
4979 guint alignment_check;
4982 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
4984 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4985 cfg->code_size += 512;
4987 #if defined(__default_codegen__)
4988 code = cfg->native_code = g_malloc (cfg->code_size);
4989 #elif defined(__native_client_codegen__)
4990 /* native_code_alloc is not 32-byte aligned, native_code is. */
4991 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
4993 /* Align native_code to next nearest kNaclAlignment byte. */
4994 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
4995 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
4997 code = cfg->native_code;
4999 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5000 g_assert(alignment_check == 0);
5003 /* Offset between RSP and the CFA */
5007 cfa_offset = sizeof (gpointer);
5008 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5009 // IP saved at CFA - 4
5010 /* There is no IP reg on x86 */
5011 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5012 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5014 need_stack_frame = needs_stack_frame (cfg);
5016 if (need_stack_frame) {
5017 x86_push_reg (code, X86_EBP);
5018 cfa_offset += sizeof (gpointer);
5019 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5020 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5021 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5022 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5023 /* These are handled automatically by the stack marking code */
5024 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5026 cfg->frame_reg = X86_ESP;
5029 alloc_size = cfg->stack_offset;
5032 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
5033 /* Might need to attach the thread to the JIT or change the domain for the callback */
5034 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
5035 guint8 *buf, *no_domain_branch;
5037 code = mono_x86_emit_tls_get (code, X86_EAX, appdomain_tls_offset);
5038 x86_alu_reg_imm (code, X86_CMP, X86_EAX, GPOINTER_TO_UINT (cfg->domain));
5039 no_domain_branch = code;
5040 x86_branch8 (code, X86_CC_NE, 0, 0);
5041 code = mono_x86_emit_tls_get ( code, X86_EAX, lmf_tls_offset);
5042 x86_test_reg_reg (code, X86_EAX, X86_EAX);
5044 x86_branch8 (code, X86_CC_NE, 0, 0);
5045 x86_patch (no_domain_branch, code);
5047 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
5048 x86_push_imm (code, cfg->domain);
5049 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
5050 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
5051 x86_patch (buf, code);
5053 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5054 /* FIXME: Add a separate key for LMF to avoid this */
5055 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5059 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
5060 if (cfg->compile_aot) {
5062 * This goes before the saving of callee saved regs, so save the got reg
5065 x86_push_reg (code, MONO_ARCH_GOT_REG);
5066 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
5067 x86_push_imm (code, 0);
5069 x86_push_imm (code, cfg->domain);
5071 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
5072 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
5073 if (cfg->compile_aot)
5074 x86_pop_reg (code, MONO_ARCH_GOT_REG);
5078 if (method->save_lmf) {
5079 pos += sizeof (MonoLMF);
5081 /* save the current IP */
5082 if (cfg->compile_aot) {
5083 /* This pushes the current ip */
5084 x86_call_imm (code, 0);
5086 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
5087 x86_push_imm_template (code);
5089 cfa_offset += sizeof (gpointer);
5090 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5092 /* save all caller saved regs */
5093 x86_push_reg (code, X86_EBP);
5094 cfa_offset += sizeof (gpointer);
5095 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5096 x86_push_reg (code, X86_ESI);
5097 cfa_offset += sizeof (gpointer);
5098 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5099 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5100 x86_push_reg (code, X86_EDI);
5101 cfa_offset += sizeof (gpointer);
5102 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5103 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5104 x86_push_reg (code, X86_EBX);
5105 cfa_offset += sizeof (gpointer);
5106 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5107 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5109 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5111 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5112 * through the mono_lmf_addr TLS variable.
5114 /* %eax = previous_lmf */
5115 x86_prefix (code, X86_GS_PREFIX);
5116 x86_mov_reg_mem (code, X86_EAX, lmf_tls_offset, 4);
5117 /* skip esp + method_info + lmf */
5118 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 12);
5120 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5121 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + 4, SLOT_NOREF);
5122 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + 8, SLOT_NOREF);
5123 /* push previous_lmf */
5124 x86_push_reg (code, X86_EAX);
5126 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5128 x86_prefix (code, X86_GS_PREFIX);
5129 x86_mov_mem_reg (code, lmf_tls_offset, X86_ESP, 4);
5131 /* get the address of lmf for the current thread */
5133 * This is performance critical so we try to use some tricks to make
5137 if (lmf_addr_tls_offset != -1) {
5138 /* Load lmf quicky using the GS register */
5139 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
5141 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5142 /* FIXME: Add a separate key for LMF to avoid this */
5143 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5146 if (cfg->compile_aot)
5147 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
5148 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
5151 /* Skip esp + method info */
5152 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
5155 x86_push_reg (code, X86_EAX);
5156 /* push *lfm (previous_lmf) */
5157 x86_push_membase (code, X86_EAX, 0);
5159 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
5163 if (cfg->used_int_regs & (1 << X86_EBX)) {
5164 x86_push_reg (code, X86_EBX);
5166 cfa_offset += sizeof (gpointer);
5167 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5168 /* These are handled automatically by the stack marking code */
5169 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5172 if (cfg->used_int_regs & (1 << X86_EDI)) {
5173 x86_push_reg (code, X86_EDI);
5175 cfa_offset += sizeof (gpointer);
5176 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5177 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5180 if (cfg->used_int_regs & (1 << X86_ESI)) {
5181 x86_push_reg (code, X86_ESI);
5183 cfa_offset += sizeof (gpointer);
5184 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5185 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5191 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5192 if (mono_do_x86_stack_align && need_stack_frame) {
5193 int tot = alloc_size + pos + 4; /* ret ip */
5194 if (need_stack_frame)
5196 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5198 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5199 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5200 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5204 cfg->arch.sp_fp_offset = alloc_size + pos;
5207 /* See mono_emit_stack_alloc */
5208 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5209 guint32 remaining_size = alloc_size;
5210 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5211 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5212 guint32 offset = code - cfg->native_code;
5213 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5214 while (required_code_size >= (cfg->code_size - offset))
5215 cfg->code_size *= 2;
5216 cfg->native_code = mono_realloc_native_code(cfg);
5217 code = cfg->native_code + offset;
5218 cfg->stat_code_reallocs++;
5220 while (remaining_size >= 0x1000) {
5221 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5222 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5223 remaining_size -= 0x1000;
5226 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5228 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5231 g_assert (need_stack_frame);
5234 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5235 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5236 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5239 #if DEBUG_STACK_ALIGNMENT
5240 /* check the stack is aligned */
5241 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5242 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5243 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5244 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5245 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5246 x86_breakpoint (code);
5250 /* compute max_offset in order to use short forward jumps */
5252 if (cfg->opt & MONO_OPT_BRANCH) {
5253 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5255 bb->max_offset = max_offset;
5257 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5259 /* max alignment for loops */
5260 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5261 max_offset += LOOP_ALIGNMENT;
5262 #ifdef __native_client_codegen__
5263 /* max alignment for native client */
5264 max_offset += kNaClAlignment;
5266 MONO_BB_FOR_EACH_INS (bb, ins) {
5267 if (ins->opcode == OP_LABEL)
5268 ins->inst_c1 = max_offset;
5269 #ifdef __native_client_codegen__
5271 int space_in_block = kNaClAlignment -
5272 ((max_offset + cfg->code_len) & kNaClAlignmentMask);
5273 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5274 if (space_in_block < max_len && max_len < kNaClAlignment) {
5275 max_offset += space_in_block;
5278 #endif /* __native_client_codegen__ */
5279 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5284 /* store runtime generic context */
5285 if (cfg->rgctx_var) {
5286 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5288 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5291 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5292 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5294 /* load arguments allocated to register from the stack */
5295 sig = mono_method_signature (method);
5298 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5299 inst = cfg->args [pos];
5300 if (inst->opcode == OP_REGVAR) {
5301 g_assert (need_stack_frame);
5302 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5303 if (cfg->verbose_level > 2)
5304 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5309 cfg->code_len = code - cfg->native_code;
5311 g_assert (cfg->code_len < cfg->code_size);
5317 mono_arch_emit_epilog (MonoCompile *cfg)
5319 MonoMethod *method = cfg->method;
5320 MonoMethodSignature *sig = mono_method_signature (method);
5322 guint32 stack_to_pop;
5324 int max_epilog_size = 16;
5326 gboolean need_stack_frame = needs_stack_frame (cfg);
5328 if (cfg->method->save_lmf)
5329 max_epilog_size += 128;
5331 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5332 cfg->code_size *= 2;
5333 cfg->native_code = mono_realloc_native_code(cfg);
5334 cfg->stat_code_reallocs++;
5337 code = cfg->native_code + cfg->code_len;
5339 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5340 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5342 /* the code restoring the registers must be kept in sync with OP_JMP */
5345 if (method->save_lmf) {
5346 gint32 prev_lmf_reg;
5347 gint32 lmf_offset = -sizeof (MonoLMF);
5349 /* check if we need to restore protection of the stack after a stack overflow */
5350 if (mono_get_jit_tls_offset () != -1) {
5352 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5353 /* we load the value in a separate instruction: this mechanism may be
5354 * used later as a safer way to do thread interruption
5356 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5357 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5359 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5360 /* note that the call trampoline will preserve eax/edx */
5361 x86_call_reg (code, X86_ECX);
5362 x86_patch (patch, code);
5364 /* FIXME: maybe save the jit tls in the prolog */
5366 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5368 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5369 * through the mono_lmf_addr TLS variable.
5371 /* reg = previous_lmf */
5372 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5374 /* lmf = previous_lmf */
5375 x86_prefix (code, X86_GS_PREFIX);
5376 x86_mov_mem_reg (code, lmf_tls_offset, X86_ECX, 4);
5378 /* Find a spare register */
5379 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
5382 prev_lmf_reg = X86_EDI;
5383 cfg->used_int_regs |= (1 << X86_EDI);
5386 prev_lmf_reg = X86_EDX;
5390 /* reg = previous_lmf */
5391 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5394 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
5396 /* *(lmf) = previous_lmf */
5397 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
5400 /* restore caller saved regs */
5401 if (cfg->used_int_regs & (1 << X86_EBX)) {
5402 x86_mov_reg_membase (code, X86_EBX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
5405 if (cfg->used_int_regs & (1 << X86_EDI)) {
5406 x86_mov_reg_membase (code, X86_EDI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
5408 if (cfg->used_int_regs & (1 << X86_ESI)) {
5409 x86_mov_reg_membase (code, X86_ESI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
5412 /* EBP is restored by LEAVE */
5414 if (cfg->used_int_regs & (1 << X86_EBX)) {
5417 if (cfg->used_int_regs & (1 << X86_EDI)) {
5420 if (cfg->used_int_regs & (1 << X86_ESI)) {
5425 g_assert (need_stack_frame);
5426 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5429 if (cfg->used_int_regs & (1 << X86_ESI)) {
5430 x86_pop_reg (code, X86_ESI);
5432 if (cfg->used_int_regs & (1 << X86_EDI)) {
5433 x86_pop_reg (code, X86_EDI);
5435 if (cfg->used_int_regs & (1 << X86_EBX)) {
5436 x86_pop_reg (code, X86_EBX);
5440 /* Load returned vtypes into registers if needed */
5441 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5442 if (cinfo->ret.storage == ArgValuetypeInReg) {
5443 for (quad = 0; quad < 2; quad ++) {
5444 switch (cinfo->ret.pair_storage [quad]) {
5446 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5448 case ArgOnFloatFpStack:
5449 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5451 case ArgOnDoubleFpStack:
5452 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5457 g_assert_not_reached ();
5462 if (need_stack_frame)
5465 if (CALLCONV_IS_STDCALL (sig)) {
5466 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5468 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
5469 } else if (MONO_TYPE_ISSTRUCT (mono_method_signature (cfg->method)->ret) && (cinfo->ret.storage == ArgOnStack))
5475 g_assert (need_stack_frame);
5476 x86_ret_imm (code, stack_to_pop);
5481 cfg->code_len = code - cfg->native_code;
5483 g_assert (cfg->code_len < cfg->code_size);
5487 mono_arch_emit_exceptions (MonoCompile *cfg)
5489 MonoJumpInfo *patch_info;
5492 MonoClass *exc_classes [16];
5493 guint8 *exc_throw_start [16], *exc_throw_end [16];
5497 /* Compute needed space */
5498 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5499 if (patch_info->type == MONO_PATCH_INFO_EXC)
5504 * make sure we have enough space for exceptions
5505 * 16 is the size of two push_imm instructions and a call
5507 if (cfg->compile_aot)
5508 code_size = exc_count * 32;
5510 code_size = exc_count * 16;
5512 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5513 cfg->code_size *= 2;
5514 cfg->native_code = mono_realloc_native_code(cfg);
5515 cfg->stat_code_reallocs++;
5518 code = cfg->native_code + cfg->code_len;
5521 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5522 switch (patch_info->type) {
5523 case MONO_PATCH_INFO_EXC: {
5524 MonoClass *exc_class;
5528 x86_patch (patch_info->ip.i + cfg->native_code, code);
5530 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5531 g_assert (exc_class);
5532 throw_ip = patch_info->ip.i;
5534 /* Find a throw sequence for the same exception class */
5535 for (i = 0; i < nthrows; ++i)
5536 if (exc_classes [i] == exc_class)
5539 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5540 x86_jump_code (code, exc_throw_start [i]);
5541 patch_info->type = MONO_PATCH_INFO_NONE;
5546 /* Compute size of code following the push <OFFSET> */
5547 #if defined(__default_codegen__)
5549 #elif defined(__native_client_codegen__)
5550 code = mono_nacl_align (code);
5551 size = kNaClAlignment;
5553 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5555 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5556 /* Use the shorter form */
5558 x86_push_imm (code, 0);
5562 x86_push_imm (code, 0xf0f0f0f0);
5567 exc_classes [nthrows] = exc_class;
5568 exc_throw_start [nthrows] = code;
5571 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5572 patch_info->data.name = "mono_arch_throw_corlib_exception";
5573 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5574 patch_info->ip.i = code - cfg->native_code;
5575 x86_call_code (code, 0);
5576 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5581 exc_throw_end [nthrows] = code;
5593 cfg->code_len = code - cfg->native_code;
5595 g_assert (cfg->code_len < cfg->code_size);
5599 mono_arch_flush_icache (guint8 *code, gint size)
5605 mono_arch_flush_register_windows (void)
5610 mono_arch_is_inst_imm (gint64 imm)
5616 mono_arch_finish_init (void)
5618 if (!getenv ("MONO_NO_TLS")) {
5621 * We need to init this multiple times, since when we are first called, the key might not
5622 * be initialized yet.
5624 appdomain_tls_offset = mono_domain_get_tls_key ();
5625 lmf_tls_offset = mono_get_jit_tls_key ();
5627 /* Only 64 tls entries can be accessed using inline code */
5628 if (appdomain_tls_offset >= 64)
5629 appdomain_tls_offset = -1;
5630 if (lmf_tls_offset >= 64)
5631 lmf_tls_offset = -1;
5634 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5636 appdomain_tls_offset = mono_domain_get_tls_offset ();
5637 lmf_tls_offset = mono_get_lmf_tls_offset ();
5638 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5644 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5648 #ifdef MONO_ARCH_HAVE_IMT
5650 // Linear handler, the bsearch head compare is shorter
5651 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5652 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5653 // x86_patch(ins,target)
5654 //[1 + 5] x86_jump_mem(inst,mem)
5657 #if defined(__default_codegen__)
5658 #define BR_SMALL_SIZE 2
5659 #define BR_LARGE_SIZE 5
5660 #elif defined(__native_client_codegen__)
5661 /* I suspect the size calculation below is actually incorrect. */
5662 /* TODO: fix the calculation that uses these sizes. */
5663 #define BR_SMALL_SIZE 16
5664 #define BR_LARGE_SIZE 12
5665 #endif /*__native_client_codegen__*/
5666 #define JUMP_IMM_SIZE 6
5667 #define ENABLE_WRONG_METHOD_CHECK 0
5671 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5673 int i, distance = 0;
5674 for (i = start; i < target; ++i)
5675 distance += imt_entries [i]->chunk_size;
5680 * LOCKING: called with the domain lock held
5683 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5684 gpointer fail_tramp)
5688 guint8 *code, *start;
5690 for (i = 0; i < count; ++i) {
5691 MonoIMTCheckItem *item = imt_entries [i];
5692 if (item->is_equals) {
5693 if (item->check_target_idx) {
5694 if (!item->compare_done)
5695 item->chunk_size += CMP_SIZE;
5696 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5699 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5701 item->chunk_size += JUMP_IMM_SIZE;
5702 #if ENABLE_WRONG_METHOD_CHECK
5703 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5708 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5709 imt_entries [item->check_target_idx]->compare_done = TRUE;
5711 size += item->chunk_size;
5713 #if defined(__native_client__) && defined(__native_client_codegen__)
5714 /* In Native Client, we don't re-use thunks, allocate from the */
5715 /* normal code manager paths. */
5716 code = mono_domain_code_reserve (domain, size);
5719 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5721 code = mono_domain_code_reserve (domain, size);
5724 for (i = 0; i < count; ++i) {
5725 MonoIMTCheckItem *item = imt_entries [i];
5726 item->code_target = code;
5727 if (item->is_equals) {
5728 if (item->check_target_idx) {
5729 if (!item->compare_done)
5730 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5731 item->jmp_code = code;
5732 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5733 if (item->has_target_code)
5734 x86_jump_code (code, item->value.target_code);
5736 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5739 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5740 item->jmp_code = code;
5741 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5742 if (item->has_target_code)
5743 x86_jump_code (code, item->value.target_code);
5745 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5746 x86_patch (item->jmp_code, code);
5747 x86_jump_code (code, fail_tramp);
5748 item->jmp_code = NULL;
5750 /* enable the commented code to assert on wrong method */
5751 #if ENABLE_WRONG_METHOD_CHECK
5752 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5753 item->jmp_code = code;
5754 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5756 if (item->has_target_code)
5757 x86_jump_code (code, item->value.target_code);
5759 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5760 #if ENABLE_WRONG_METHOD_CHECK
5761 x86_patch (item->jmp_code, code);
5762 x86_breakpoint (code);
5763 item->jmp_code = NULL;
5768 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5769 item->jmp_code = code;
5770 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5771 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5773 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5776 /* patch the branches to get to the target items */
5777 for (i = 0; i < count; ++i) {
5778 MonoIMTCheckItem *item = imt_entries [i];
5779 if (item->jmp_code) {
5780 if (item->check_target_idx) {
5781 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5787 mono_stats.imt_thunks_size += code - start;
5788 g_assert (code - start <= size);
5792 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5793 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5797 if (mono_jit_map_is_enabled ()) {
5800 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5802 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5803 mono_emit_jit_tramp (start, code - start, buff);
5807 nacl_domain_code_validate (domain, &start, size, &code);
5813 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5815 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5820 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5822 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5826 mono_arch_get_cie_program (void)
5830 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5831 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5837 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5839 MonoInst *ins = NULL;
5842 if (cmethod->klass == mono_defaults.math_class) {
5843 if (strcmp (cmethod->name, "Sin") == 0) {
5845 } else if (strcmp (cmethod->name, "Cos") == 0) {
5847 } else if (strcmp (cmethod->name, "Tan") == 0) {
5849 } else if (strcmp (cmethod->name, "Atan") == 0) {
5851 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5853 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5855 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5860 MONO_INST_NEW (cfg, ins, opcode);
5861 ins->type = STACK_R8;
5862 ins->dreg = mono_alloc_freg (cfg);
5863 ins->sreg1 = args [0]->dreg;
5864 MONO_ADD_INS (cfg->cbb, ins);
5867 if (cfg->opt & MONO_OPT_CMOV) {
5870 if (strcmp (cmethod->name, "Min") == 0) {
5871 if (fsig->params [0]->type == MONO_TYPE_I4)
5873 } else if (strcmp (cmethod->name, "Max") == 0) {
5874 if (fsig->params [0]->type == MONO_TYPE_I4)
5879 MONO_INST_NEW (cfg, ins, opcode);
5880 ins->type = STACK_I4;
5881 ins->dreg = mono_alloc_ireg (cfg);
5882 ins->sreg1 = args [0]->dreg;
5883 ins->sreg2 = args [1]->dreg;
5884 MONO_ADD_INS (cfg->cbb, ins);
5889 /* OP_FREM is not IEEE compatible */
5890 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5891 MONO_INST_NEW (cfg, ins, OP_FREM);
5892 ins->inst_i0 = args [0];
5893 ins->inst_i1 = args [1];
5902 mono_arch_print_tree (MonoInst *tree, int arity)
5907 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5913 if (appdomain_tls_offset == -1)
5916 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5917 ins->inst_offset = appdomain_tls_offset;
5922 mono_arch_get_patch_offset (guint8 *code)
5924 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5926 else if ((code [0] == 0xba))
5928 else if ((code [0] == 0x68))
5931 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5932 /* push <OFFSET>(<REG>) */
5934 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5935 /* call *<OFFSET>(<REG>) */
5937 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5940 else if ((code [0] == 0x58) && (code [1] == 0x05))
5941 /* pop %eax; add <OFFSET>, %eax */
5943 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5944 /* pop <REG>; add <OFFSET>, <REG> */
5946 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5947 /* mov <REG>, imm */
5950 g_assert_not_reached ();
5956 * mono_breakpoint_clean_code:
5958 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5959 * breakpoints in the original code, they are removed in the copy.
5961 * Returns TRUE if no sw breakpoint was present.
5964 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5967 gboolean can_write = TRUE;
5969 * If method_start is non-NULL we need to perform bound checks, since we access memory
5970 * at code - offset we could go before the start of the method and end up in a different
5971 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5974 if (!method_start || code - offset >= method_start) {
5975 memcpy (buf, code - offset, size);
5977 int diff = code - method_start;
5978 memset (buf, 0, size);
5979 memcpy (buf + offset - diff, method_start, diff + size - offset);
5982 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5983 int idx = mono_breakpoint_info_index [i];
5987 ptr = mono_breakpoint_info [idx].address;
5988 if (ptr >= code && ptr < code + size) {
5989 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5991 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5992 buf [ptr - code] = saved_byte;
5999 * mono_x86_get_this_arg_offset:
6001 * Return the offset of the stack location where this is passed during a virtual
6005 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6011 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6013 guint32 esp = regs [X86_ESP];
6014 CallInfo *cinfo = NULL;
6021 * The stack looks like:
6025 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
6027 res = (((MonoObject**)esp) [5 + (offset / 4)]);
6033 #define MAX_ARCH_DELEGATE_PARAMS 10
6036 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6038 guint8 *code, *start;
6039 int code_reserve = 64;
6042 * The stack contains:
6048 start = code = mono_global_codeman_reserve (code_reserve);
6050 /* Replace the this argument with the target */
6051 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6052 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
6053 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6054 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6056 g_assert ((code - start) < code_reserve);
6059 /* 8 for mov_reg and jump, plus 8 for each parameter */
6060 #ifdef __native_client_codegen__
6061 /* TODO: calculate this size correctly */
6062 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6064 code_reserve = 8 + (param_count * 8);
6065 #endif /* __native_client_codegen__ */
6067 * The stack contains:
6068 * <args in reverse order>
6073 * <args in reverse order>
6076 * without unbalancing the stack.
6077 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6078 * and leaving original spot of first arg as placeholder in stack so
6079 * when callee pops stack everything works.
6082 start = code = mono_global_codeman_reserve (code_reserve);
6084 /* store delegate for access to method_ptr */
6085 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6088 for (i = 0; i < param_count; ++i) {
6089 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6090 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6093 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6095 g_assert ((code - start) < code_reserve);
6098 nacl_global_codeman_validate(&start, code_reserve, &code);
6099 mono_debug_add_delegate_trampoline (start, code - start);
6102 *code_len = code - start;
6104 if (mono_jit_map_is_enabled ()) {
6107 buff = (char*)"delegate_invoke_has_target";
6109 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6110 mono_emit_jit_tramp (start, code - start, buff);
6119 mono_arch_get_delegate_invoke_impls (void)
6126 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6127 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
6129 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6130 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6131 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
6138 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6140 guint8 *code, *start;
6142 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6145 /* FIXME: Support more cases */
6146 if (MONO_TYPE_ISSTRUCT (sig->ret))
6150 * The stack contains:
6156 static guint8* cached = NULL;
6161 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6163 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6165 mono_memory_barrier ();
6169 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6172 for (i = 0; i < sig->param_count; ++i)
6173 if (!mono_is_regsize_var (sig->params [i]))
6176 code = cache [sig->param_count];
6180 if (mono_aot_only) {
6181 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6182 start = mono_aot_get_trampoline (name);
6185 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6188 mono_memory_barrier ();
6190 cache [sig->param_count] = start;
6197 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6200 case X86_EAX: return ctx->eax;
6201 case X86_EBX: return ctx->ebx;
6202 case X86_ECX: return ctx->ecx;
6203 case X86_EDX: return ctx->edx;
6204 case X86_ESP: return ctx->esp;
6205 case X86_EBP: return ctx->ebp;
6206 case X86_ESI: return ctx->esi;
6207 case X86_EDI: return ctx->edi;
6209 g_assert_not_reached ();
6215 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6243 g_assert_not_reached ();
6247 #ifdef MONO_ARCH_SIMD_INTRINSICS
6250 get_float_to_x_spill_area (MonoCompile *cfg)
6252 if (!cfg->fconv_to_r8_x_var) {
6253 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6254 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6256 return cfg->fconv_to_r8_x_var;
6260 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6263 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6266 int dreg, src_opcode;
6268 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6271 switch (src_opcode = ins->opcode) {
6272 case OP_FCONV_TO_I1:
6273 case OP_FCONV_TO_U1:
6274 case OP_FCONV_TO_I2:
6275 case OP_FCONV_TO_U2:
6276 case OP_FCONV_TO_I4:
6283 /* dreg is the IREG and sreg1 is the FREG */
6284 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6285 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6286 fconv->sreg1 = ins->sreg1;
6287 fconv->dreg = mono_alloc_ireg (cfg);
6288 fconv->type = STACK_VTYPE;
6289 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6291 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6295 ins->opcode = OP_XCONV_R8_TO_I4;
6297 ins->klass = mono_defaults.int32_class;
6298 ins->sreg1 = fconv->dreg;
6300 ins->type = STACK_I4;
6301 ins->backend.source_opcode = src_opcode;
6304 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6307 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6312 if (long_ins->opcode == OP_LNEG) {
6314 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6315 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6316 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6321 #ifdef MONO_ARCH_SIMD_INTRINSICS
6323 if (!(cfg->opt & MONO_OPT_SIMD))
6326 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6327 switch (long_ins->opcode) {
6329 vreg = long_ins->sreg1;
6331 if (long_ins->inst_c0) {
6332 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6333 ins->klass = long_ins->klass;
6334 ins->sreg1 = long_ins->sreg1;
6336 ins->type = STACK_VTYPE;
6337 ins->dreg = vreg = alloc_ireg (cfg);
6338 MONO_ADD_INS (cfg->cbb, ins);
6341 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6342 ins->klass = mono_defaults.int32_class;
6344 ins->type = STACK_I4;
6345 ins->dreg = long_ins->dreg + 1;
6346 MONO_ADD_INS (cfg->cbb, ins);
6348 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6349 ins->klass = long_ins->klass;
6350 ins->sreg1 = long_ins->sreg1;
6351 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6352 ins->type = STACK_VTYPE;
6353 ins->dreg = vreg = alloc_ireg (cfg);
6354 MONO_ADD_INS (cfg->cbb, ins);
6356 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6357 ins->klass = mono_defaults.int32_class;
6359 ins->type = STACK_I4;
6360 ins->dreg = long_ins->dreg + 2;
6361 MONO_ADD_INS (cfg->cbb, ins);
6363 long_ins->opcode = OP_NOP;
6365 case OP_INSERTX_I8_SLOW:
6366 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6367 ins->dreg = long_ins->dreg;
6368 ins->sreg1 = long_ins->dreg;
6369 ins->sreg2 = long_ins->sreg2 + 1;
6370 ins->inst_c0 = long_ins->inst_c0 * 2;
6371 MONO_ADD_INS (cfg->cbb, ins);
6373 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6374 ins->dreg = long_ins->dreg;
6375 ins->sreg1 = long_ins->dreg;
6376 ins->sreg2 = long_ins->sreg2 + 2;
6377 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6378 MONO_ADD_INS (cfg->cbb, ins);
6380 long_ins->opcode = OP_NOP;
6383 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6384 ins->dreg = long_ins->dreg;
6385 ins->sreg1 = long_ins->sreg1 + 1;
6386 ins->klass = long_ins->klass;
6387 ins->type = STACK_VTYPE;
6388 MONO_ADD_INS (cfg->cbb, ins);
6390 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6391 ins->dreg = long_ins->dreg;
6392 ins->sreg1 = long_ins->dreg;
6393 ins->sreg2 = long_ins->sreg1 + 2;
6395 ins->klass = long_ins->klass;
6396 ins->type = STACK_VTYPE;
6397 MONO_ADD_INS (cfg->cbb, ins);
6399 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6400 ins->dreg = long_ins->dreg;
6401 ins->sreg1 = long_ins->dreg;;
6402 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6403 ins->klass = long_ins->klass;
6404 ins->type = STACK_VTYPE;
6405 MONO_ADD_INS (cfg->cbb, ins);
6407 long_ins->opcode = OP_NOP;
6410 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6413 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6415 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6418 gpointer *sp, old_value;
6420 const unsigned char *handler;
6422 /*Decode the first instruction to figure out where did we store the spvar*/
6423 /*Our jit MUST generate the following:
6425 Which is encoded as: 0x89 mod_rm.
6426 mod_rm (esp, ebp, imm) which can be: (imm will never be zero)
6427 mod (reg + imm8): 01 reg(esp): 100 rm(ebp): 101 -> 01100101 (0x65)
6428 mod (reg + imm32): 10 reg(esp): 100 rm(ebp): 101 -> 10100101 (0xA5)
6430 handler = clause->handler_start;
6432 if (*handler != 0x89)
6437 if (*handler == 0x65)
6438 offset = *(signed char*)(handler + 1);
6439 else if (*handler == 0xA5)
6440 offset = *(int*)(handler + 1);
6445 bp = MONO_CONTEXT_GET_BP (ctx);
6446 sp = *(gpointer*)(bp + offset);
6449 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6458 * mono_aot_emit_load_got_addr:
6460 * Emit code to load the got address.
6461 * On x86, the result is placed into EBX.
6464 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6466 x86_call_imm (code, 0);
6468 * The patch needs to point to the pop, since the GOT offset needs
6469 * to be added to that address.
6472 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6474 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6475 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6476 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6482 * mono_ppc_emit_load_aotconst:
6484 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6485 * TARGET from the mscorlib GOT in full-aot code.
6486 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6490 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6492 /* Load the mscorlib got address */
6493 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6494 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6495 /* arch_emit_got_access () patches this */
6496 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6501 /* Can't put this into mini-x86.h */
6503 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6506 mono_arch_get_trampolines (gboolean aot)
6508 MonoTrampInfo *info;
6509 GSList *tramps = NULL;
6511 mono_x86_get_signal_exception_trampoline (&info, aot);
6513 tramps = g_slist_append (tramps, info);
6520 #define DBG_SIGNAL SIGBUS
6522 #define DBG_SIGNAL SIGSEGV
6525 /* Soft Debug support */
6526 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6529 * mono_arch_set_breakpoint:
6531 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6532 * The location should contain code emitted by OP_SEQ_POINT.
6535 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6540 * In production, we will use int3 (has to fix the size in the md
6541 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6544 g_assert (code [0] == 0x90);
6545 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6549 * mono_arch_clear_breakpoint:
6551 * Clear the breakpoint at IP.
6554 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6559 for (i = 0; i < 6; ++i)
6564 * mono_arch_start_single_stepping:
6566 * Start single stepping.
6569 mono_arch_start_single_stepping (void)
6571 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6575 * mono_arch_stop_single_stepping:
6577 * Stop single stepping.
6580 mono_arch_stop_single_stepping (void)
6582 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6586 * mono_arch_is_single_step_event:
6588 * Return whenever the machine state in SIGCTX corresponds to a single
6592 mono_arch_is_single_step_event (void *info, void *sigctx)
6595 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6597 if ((einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6602 siginfo_t* sinfo = (siginfo_t*) info;
6603 /* Sometimes the address is off by 4 */
6604 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6612 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6615 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6616 if ((einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6621 siginfo_t* sinfo = (siginfo_t*)info;
6622 /* Sometimes the address is off by 4 */
6623 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6630 #define BREAKPOINT_SIZE 6
6633 * mono_arch_skip_breakpoint:
6635 * See mini-amd64.c for docs.
6638 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6640 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6644 * mono_arch_skip_single_step:
6646 * See mini-amd64.c for docs.
6649 mono_arch_skip_single_step (MonoContext *ctx)
6651 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6655 * mono_arch_get_seq_point_info:
6657 * See mini-amd64.c for docs.
6660 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)