mono/mini/mini-x86.c

   1 /*
   2  * mini-x86.c: x86 backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Paolo Molaro (lupus@ximian.com)
   6  *   Dietmar Maurer (dietmar@ximian.com)
   7  *   Patrik Torstensson
   8  *
   9  * (C) 2003 Ximian, Inc.
  10  */
  11 #include "mini.h"
  12 #include <string.h>
  13 #include <math.h>
  14
  15 #include <mono/metadata/appdomain.h>
  16 #include <mono/metadata/debug-helpers.h>
  17 #include <mono/metadata/profiler-private.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "trace.h"
  21 #include "mini-x86.h"
  22 #include "inssel.h"
  23 #include "cpu-pentium.h"
  24
  25 static gint lmf_tls_offset = -1;
  26
  27 #ifdef PLATFORM_WIN32
  28 /* Under windows, the default pinvoke calling convention is stdcall */
  29 #define CALLCONV_IS_STDCALL(call_conv) (((call_conv) == MONO_CALL_STDCALL) || ((call_conv) == MONO_CALL_DEFAULT))
  30 #else
  31 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  32 #endif
  33
  34 #define SIGNAL_STACK_SIZE (64 * 1024)
  35
  36 static gpointer mono_arch_get_lmf_addr (void);
  37
  38 const char*
  39 mono_arch_regname (int reg) {
  40         switch (reg) {
  41         case X86_EAX: return "%eax";
  42         case X86_EBX: return "%ebx";
  43         case X86_ECX: return "%ecx";
  44         case X86_EDX: return "%edx";
  45         case X86_ESP: return "%esp";    case X86_EBP: return "%ebp";
  46         case X86_EDI: return "%edi";
  47         case X86_ESI: return "%esi";
  48         }
  49         return "unknown";
  50 }
  51
  52 /*
  53  * mono_arch_get_argument_info:
  54  * @csig:  a method signature
  55  * @param_count: the number of parameters to consider
  56  * @arg_info: an array to store the result infos
  57  *
  58  * Gathers information on parameters such as size, alignment and
  59  * padding. arg_info should be large enought to hold param_count + 1 entries.
  60  *
  61  * Returns the size of the activation frame.
  62  */
  63 int
  64 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
  65 {
  66         int k, frame_size = 0;
  67         int size, align, pad;
  68         int offset = 8;
  69
  70         if (MONO_TYPE_ISSTRUCT (csig->ret)) {
  71                 frame_size += sizeof (gpointer);
  72                 offset += 4;
  73         }
  74
  75         arg_info [0].offset = offset;
  76
  77         if (csig->hasthis) {
  78                 frame_size += sizeof (gpointer);
  79                 offset += 4;
  80         }
  81
  82         arg_info [0].size = frame_size;
  83
  84         for (k = 0; k < param_count; k++) {
  85
  86                 if (csig->pinvoke)
  87                         size = mono_type_native_stack_size (csig->params [k], &align);
  88                 else
  89                         size = mono_type_stack_size (csig->params [k], &align);
  90
  91                 /* ignore alignment for now */
  92                 align = 1;
  93
  94                 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
  95                 arg_info [k].pad = pad;
  96                 frame_size += size;
  97                 arg_info [k + 1].pad = 0;
  98                 arg_info [k + 1].size = size;
  99                 offset += pad;
 100                 arg_info [k + 1].offset = offset;
 101                 offset += size;
 102         }
 103
 104         align = MONO_ARCH_FRAME_ALIGNMENT;
 105         frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 106         arg_info [k].pad = pad;
 107
 108         return frame_size;
 109 }
 110
 111 static const guchar cpuid_impl [] = {
 112         0x55,                           /* push   %ebp */
 113         0x89, 0xe5,                     /* mov    %esp,%ebp */
 114         0x53,                           /* push   %ebx */
 115         0x8b, 0x45, 0x08,               /* mov    0x8(%ebp),%eax */
 116         0x0f, 0xa2,                     /* cpuid   */
 117         0x50,                           /* push   %eax */
 118         0x8b, 0x45, 0x10,               /* mov    0x10(%ebp),%eax */
 119         0x89, 0x18,                     /* mov    %ebx,(%eax) */
 120         0x8b, 0x45, 0x14,               /* mov    0x14(%ebp),%eax */
 121         0x89, 0x08,                     /* mov    %ecx,(%eax) */
 122         0x8b, 0x45, 0x18,               /* mov    0x18(%ebp),%eax */
 123         0x89, 0x10,                     /* mov    %edx,(%eax) */
 124         0x58,                           /* pop    %eax */
 125         0x8b, 0x55, 0x0c,               /* mov    0xc(%ebp),%edx */
 126         0x89, 0x02,                     /* mov    %eax,(%edx) */
 127         0x5b,                           /* pop    %ebx */
 128         0xc9,                           /* leave   */
 129         0xc3,                           /* ret     */
 130 };
 131
 132 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
 133
 134 static int
 135 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 136 {
 137         int have_cpuid = 0;
 138         __asm__  __volatile__ (
 139                 "pushfl\n"
 140                 "popl %%eax\n"
 141                 "movl %%eax, %%edx\n"
 142                 "xorl $0x200000, %%eax\n"
 143                 "pushl %%eax\n"
 144                 "popfl\n"
 145                 "pushfl\n"
 146                 "popl %%eax\n"
 147                 "xorl %%edx, %%eax\n"
 148                 "andl $0x200000, %%eax\n"
 149                 "movl %%eax, %0"
 150                 : "=r" (have_cpuid)
 151                 :
 152                 : "%eax", "%edx"
 153         );
 154
 155         if (have_cpuid) {
 156                 CpuidFunc func = (CpuidFunc)cpuid_impl;
 157                 func (id, p_eax, p_ebx, p_ecx, p_edx);
 158                 /*
 159                  * We use this approach because of issues with gcc and pic code, see:
 160                  * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
 161                 __asm__ __volatile__ ("cpuid"
 162                         : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 163                         : "a" (id));
 164                 */
 165                 return 1;
 166         }
 167         return 0;
 168 }
 169
 170 /*
 171  * Initialize the cpu to execute managed code.
 172  */
 173 void
 174 mono_arch_cpu_init (void)
 175 {
 176         guint16 fpcw;
 177
 178         /* spec compliance requires running with double precision */
 179         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 180         fpcw &= ~X86_FPCW_PRECC_MASK;
 181         fpcw |= X86_FPCW_PREC_DOUBLE;
 182         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 183         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 184
 185 }
 186
 187 /*
 188  * This function returns the optimizations supported on this cpu.
 189  */
 190 guint32
 191 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 192 {
 193         int eax, ebx, ecx, edx;
 194         guint32 opts = 0;
 195
 196         *exclude_mask = 0;
 197         /* Feature Flags function, flags returned in EDX. */
 198         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 199                 if (edx & (1 << 15)) {
 200                         opts |= MONO_OPT_CMOV;
 201                         if (edx & 1)
 202                                 opts |= MONO_OPT_FCMOV;
 203                         else
 204                                 *exclude_mask |= MONO_OPT_FCMOV;
 205                 } else
 206                         *exclude_mask |= MONO_OPT_CMOV;
 207         }
 208         return opts;
 209 }
 210
 211 static gboolean
 212 is_regsize_var (MonoType *t) {
 213         if (t->byref)
 214                 return TRUE;
 215         switch (t->type) {
 216         case MONO_TYPE_I4:
 217         case MONO_TYPE_U4:
 218         case MONO_TYPE_I:
 219         case MONO_TYPE_U:
 220                 return TRUE;
 221         case MONO_TYPE_OBJECT:
 222         case MONO_TYPE_STRING:
 223         case MONO_TYPE_CLASS:
 224         case MONO_TYPE_SZARRAY:
 225         case MONO_TYPE_ARRAY:
 226                 return TRUE;
 227         case MONO_TYPE_VALUETYPE:
 228                 if (t->data.klass->enumtype)
 229                         return is_regsize_var (t->data.klass->enum_basetype);
 230                 return FALSE;
 231         }
 232         return FALSE;
 233 }
 234
 235 GList *
 236 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 237 {
 238         GList *vars = NULL;
 239         int i;
 240
 241         for (i = 0; i < cfg->num_varinfo; i++) {
 242                 MonoInst *ins = cfg->varinfo [i];
 243                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 244
 245                 /* unused vars */
 246                 if (vmv->range.first_use.abs_pos > vmv->range.last_use.abs_pos)
 247                         continue;
 248
 249                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 250                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 251                         continue;
 252
 253                 /* we dont allocate I1 to registers because there is no simply way to sign extend
 254                  * 8bit quantities in caller saved registers on x86 */
 255                 if (is_regsize_var (ins->inst_vtype) || (ins->inst_vtype->type == MONO_TYPE_BOOLEAN) ||
 256                     (ins->inst_vtype->type == MONO_TYPE_U1) || (ins->inst_vtype->type == MONO_TYPE_U2)||
 257                     (ins->inst_vtype->type == MONO_TYPE_I2) || (ins->inst_vtype->type == MONO_TYPE_CHAR)) {
 258                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 259                         g_assert (i == vmv->idx);
 260                         vars = g_list_prepend (vars, vmv);
 261                 }
 262         }
 263
 264         vars = mono_varlist_sort (cfg, vars, 0);
 265
 266         return vars;
 267 }
 268
 269 GList *
 270 mono_arch_get_global_int_regs (MonoCompile *cfg)
 271 {
 272         GList *regs = NULL;
 273
 274         /* we can use 3 registers for global allocation */
 275         regs = g_list_prepend (regs, (gpointer)X86_EBX);
 276         regs = g_list_prepend (regs, (gpointer)X86_ESI);
 277         regs = g_list_prepend (regs, (gpointer)X86_EDI);
 278
 279         return regs;
 280 }
 281
 282 /*
 283  * mono_arch_regalloc_cost:
 284  *
 285  *  Return the cost, in number of memory references, of the action of
 286  * allocating the variable VMV into a register during global register
 287  * allocation.
 288  */
 289 guint32
 290 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 291 {
 292         MonoInst *ins = cfg->varinfo [vmv->idx];
 293
 294         if (cfg->method->save_lmf)
 295                 /* The register is already saved */
 296                 return (ins->opcode == OP_ARG) ? 1 : 0;
 297         else
 298                 /* push+pop+possible load if it is an argument */
 299                 return (ins->opcode == OP_ARG) ? 3 : 2;
 300 }
 301
 302 /*
 303  * Set var information according to the calling convention. X86 version.
 304  * The locals var stuff should most likely be split in another method.
 305  */
 306 void
 307 mono_arch_allocate_vars (MonoCompile *m)
 308 {
 309         MonoMethodSignature *sig;
 310         MonoMethodHeader *header;
 311         MonoInst *inst;
 312         int i, offset, size, align, curinst;
 313
 314         header = ((MonoMethodNormal *)m->method)->header;
 315
 316         sig = m->method->signature;
 317
 318         offset = 8;
 319         curinst = 0;
 320         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
 321                 m->ret->opcode = OP_REGOFFSET;
 322                 m->ret->inst_basereg = X86_EBP;
 323                 m->ret->inst_offset = offset;
 324                 offset += sizeof (gpointer);
 325         } else {
 326                 /* FIXME: handle long and FP values */
 327                 switch (sig->ret->type) {
 328                 case MONO_TYPE_VOID:
 329                         break;
 330                 default:
 331                         m->ret->opcode = OP_REGVAR;
 332                         m->ret->inst_c0 = X86_EAX;
 333                         break;
 334                 }
 335         }
 336         if (sig->hasthis) {
 337                 inst = m->varinfo [curinst];
 338                 if (inst->opcode != OP_REGVAR) {
 339                         inst->opcode = OP_REGOFFSET;
 340                         inst->inst_basereg = X86_EBP;
 341                 }
 342                 inst->inst_offset = offset;
 343                 offset += sizeof (gpointer);
 344                 curinst++;
 345         }
 346
 347         if (sig->call_convention == MONO_CALL_VARARG) {
 348                 m->sig_cookie = offset;
 349                 offset += sizeof (gpointer);
 350         }
 351
 352         for (i = 0; i < sig->param_count; ++i) {
 353                 inst = m->varinfo [curinst];
 354                 if (inst->opcode != OP_REGVAR) {
 355                         inst->opcode = OP_REGOFFSET;
 356                         inst->inst_basereg = X86_EBP;
 357                 }
 358                 inst->inst_offset = offset;
 359                 size = mono_type_size (sig->params [i], &align);
 360                 size += 4 - 1;
 361                 size &= ~(4 - 1);
 362                 offset += size;
 363                 curinst++;
 364         }
 365
 366         offset = 0;
 367
 368         /* reserve space to save LMF and caller saved registers */
 369
 370         if (m->method->save_lmf) {
 371                 offset += sizeof (MonoLMF);
 372         } else {
 373                 if (m->used_int_regs & (1 << X86_EBX)) {
 374                         offset += 4;
 375                 }
 376
 377                 if (m->used_int_regs & (1 << X86_EDI)) {
 378                         offset += 4;
 379                 }
 380
 381                 if (m->used_int_regs & (1 << X86_ESI)) {
 382                         offset += 4;
 383                 }
 384         }
 385
 386         for (i = curinst; i < m->num_varinfo; ++i) {
 387                 inst = m->varinfo [i];
 388
 389                 if ((inst->flags & MONO_INST_IS_DEAD) || inst->opcode == OP_REGVAR)
 390                         continue;
 391
 392                 /* inst->unused indicates native sized value types, this is used by the
 393                 * pinvoke wrappers when they call functions returning structure */
 394                 if (inst->unused && MONO_TYPE_ISSTRUCT (inst->inst_vtype) && inst->inst_vtype->type != MONO_TYPE_TYPEDBYREF)
 395                         size = mono_class_native_size (inst->inst_vtype->data.klass, &align);
 396                 else
 397                         size = mono_type_size (inst->inst_vtype, &align);
 398
 399                 offset += size;
 400                 offset += align - 1;
 401                 offset &= ~(align - 1);
 402                 inst->opcode = OP_REGOFFSET;
 403                 inst->inst_basereg = X86_EBP;
 404                 inst->inst_offset = -offset;
 405                 //g_print ("allocating local %d to %d\n", i, -offset);
 406         }
 407         offset += (MONO_ARCH_FRAME_ALIGNMENT - 1);
 408         offset &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
 409
 410         /* change sign? */
 411         m->stack_offset = -offset;
 412 }
 413
 414 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
 415  * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
 416  */
 417
 418 /*
 419  * take the arguments and generate the arch-specific
 420  * instructions to properly call the function in call.
 421  * This includes pushing, moving arguments to the right register
 422  * etc.
 423  * Issue: who does the spilling if needed, and when?
 424  */
 425 MonoCallInst*
 426 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
 427         MonoInst *arg, *in;
 428         MonoMethodSignature *sig;
 429         int i, n, stack_size, type;
 430         MonoType *ptype;
 431
 432         stack_size = 0;
 433         /* add the vararg cookie before the non-implicit args */
 434         if (call->signature->call_convention == MONO_CALL_VARARG) {
 435                 MonoInst *sig_arg;
 436                 /* FIXME: Add support for signature tokens to AOT */
 437                 cfg->disable_aot = TRUE;
 438                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
 439                 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
 440                 sig_arg->inst_p0 = call->signature;
 441                 arg->inst_left = sig_arg;
 442                 arg->type = STACK_PTR;
 443                 /* prepend, so they get reversed */
 444                 arg->next = call->out_args;
 445                 call->out_args = arg;
 446                 stack_size += sizeof (gpointer);
 447         }
 448         sig = call->signature;
 449         n = sig->param_count + sig->hasthis;
 450
 451         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret))
 452                 stack_size += sizeof (gpointer);
 453         for (i = 0; i < n; ++i) {
 454                 if (is_virtual && i == 0) {
 455                         /* the argument will be attached to the call instrucion */
 456                         in = call->args [i];
 457                         stack_size += 4;
 458                 } else {
 459                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
 460                         in = call->args [i];
 461                         arg->cil_code = in->cil_code;
 462                         arg->inst_left = in;
 463                         arg->type = in->type;
 464                         /* prepend, so they get reversed */
 465                         arg->next = call->out_args;
 466                         call->out_args = arg;
 467                         if (i >= sig->hasthis) {
 468                                 ptype = sig->params [i - sig->hasthis];
 469                                 if (ptype->byref)
 470                                         type = MONO_TYPE_U;
 471                                 else
 472                                         type = ptype->type;
 473 handle_enum:
 474                                 /* FIXME: validate arguments... */
 475                                 switch (type) {
 476                                 case MONO_TYPE_I:
 477                                 case MONO_TYPE_U:
 478                                 case MONO_TYPE_BOOLEAN:
 479                                 case MONO_TYPE_CHAR:
 480                                 case MONO_TYPE_I1:
 481                                 case MONO_TYPE_U1:
 482                                 case MONO_TYPE_I2:
 483                                 case MONO_TYPE_U2:
 484                                 case MONO_TYPE_I4:
 485                                 case MONO_TYPE_U4:
 486                                 case MONO_TYPE_STRING:
 487                                 case MONO_TYPE_CLASS:
 488                                 case MONO_TYPE_OBJECT:
 489                                 case MONO_TYPE_PTR:
 490                                 case MONO_TYPE_FNPTR:
 491                                 case MONO_TYPE_ARRAY:
 492                                 case MONO_TYPE_SZARRAY:
 493                                         stack_size += 4;
 494                                         break;
 495                                 case MONO_TYPE_I8:
 496                                 case MONO_TYPE_U8:
 497                                         stack_size += 8;
 498                                         break;
 499                                 case MONO_TYPE_R4:
 500                                         stack_size += 4;
 501                                         arg->opcode = OP_OUTARG_R4;
 502                                         break;
 503                                 case MONO_TYPE_R8:
 504                                         stack_size += 8;
 505                                         arg->opcode = OP_OUTARG_R8;
 506                                         break;
 507                                 case MONO_TYPE_VALUETYPE:
 508                                         if (MONO_TYPE_ISSTRUCT (ptype)) {
 509                                                 int size;
 510                                                 if (sig->pinvoke)
 511                                                         size = mono_type_native_stack_size (&in->klass->byval_arg, NULL);
 512                                                 else
 513                                                         size = mono_type_stack_size (&in->klass->byval_arg, NULL);
 514
 515                                                 stack_size += size;
 516                                                 arg->opcode = OP_OUTARG_VT;
 517                                                 arg->klass = in->klass;
 518                                                 arg->unused = sig->pinvoke;
 519                                                 arg->inst_imm = size;
 520                                         } else {
 521                                                 type = ptype->data.klass->enum_basetype->type;
 522                                                 goto handle_enum;
 523                                         }
 524                                         break;
 525                                 case MONO_TYPE_TYPEDBYREF:
 526                                         stack_size += sizeof (MonoTypedRef);
 527                                         arg->opcode = OP_OUTARG_VT;
 528                                         arg->klass = in->klass;
 529                                         arg->unused = sig->pinvoke;
 530                                         arg->inst_imm = sizeof (MonoTypedRef);
 531                                         break;
 532                                 case MONO_TYPE_GENERICINST:
 533                                         type = ptype->data.generic_inst->generic_type->type;
 534                                         goto handle_enum;
 535
 536                                 default:
 537                                         g_error ("unknown type 0x%02x in mono_arch_call_opcode\n", type);
 538                                 }
 539                         } else {
 540                                 /* the this argument */
 541                                 stack_size += 4;
 542                         }
 543                 }
 544         }
 545         /* if the function returns a struct, the called method already does a ret $0x4 */
 546         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret))
 547                 stack_size -= 4;
 548         call->stack_usage = stack_size;
 549         /*
 550          * should set more info in call, such as the stack space
 551          * used by the args that needs to be added back to esp
 552          */
 553
 554         return call;
 555 }
 556
 557 /*
 558  * Allow tracing to work with this interface (with an optional argument)
 559  */
 560
 561 /*
 562  * This may be needed on some archs or for debugging support.
 563  */
 564 void
 565 mono_arch_instrument_mem_needs (MonoMethod *method, int *stack, int *code)
 566 {
 567         /* no stack room needed now (may be needed for FASTCALL-trace support) */
 568         *stack = 0;
 569         /* split prolog-epilog requirements? */
 570         *code = 50; /* max bytes needed: check this number */
 571 }
 572
 573 void*
 574 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
 575 {
 576         guchar *code = p;
 577
 578         /* if some args are passed in registers, we need to save them here */
 579         x86_push_reg (code, X86_EBP);
 580         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
 581         x86_push_imm (code, cfg->method);
 582         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
 583         x86_call_code (code, 0);
 584         x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
 585
 586         return code;
 587 }
 588
 589 enum {
 590         SAVE_NONE,
 591         SAVE_STRUCT,
 592         SAVE_EAX,
 593         SAVE_EAX_EDX,
 594         SAVE_FP
 595 };
 596
 597 void*
 598 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
 599 {
 600         guchar *code = p;
 601         int arg_size = 0, save_mode = SAVE_NONE;
 602         MonoMethod *method = cfg->method;
 603         int rtype = method->signature->ret->type;
 604
 605 handle_enum:
 606         switch (rtype) {
 607         case MONO_TYPE_VOID:
 608                 /* special case string .ctor icall */
 609                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
 610                         save_mode = SAVE_EAX;
 611                 else
 612                         save_mode = SAVE_NONE;
 613                 break;
 614         case MONO_TYPE_I8:
 615         case MONO_TYPE_U8:
 616                 save_mode = SAVE_EAX_EDX;
 617                 break;
 618         case MONO_TYPE_R4:
 619         case MONO_TYPE_R8:
 620                 save_mode = SAVE_FP;
 621                 break;
 622         case MONO_TYPE_VALUETYPE:
 623                 if (method->signature->ret->data.klass->enumtype) {
 624                         rtype = method->signature->ret->data.klass->enum_basetype->type;
 625                         goto handle_enum;
 626                 }
 627                 save_mode = SAVE_STRUCT;
 628                 break;
 629         default:
 630                 save_mode = SAVE_EAX;
 631                 break;
 632         }
 633
 634         switch (save_mode) {
 635         case SAVE_EAX_EDX:
 636                 x86_push_reg (code, X86_EDX);
 637                 x86_push_reg (code, X86_EAX);
 638                 if (enable_arguments) {
 639                         x86_push_reg (code, X86_EDX);
 640                         x86_push_reg (code, X86_EAX);
 641                         arg_size = 8;
 642                 }
 643                 break;
 644         case SAVE_EAX:
 645                 x86_push_reg (code, X86_EAX);
 646                 if (enable_arguments) {
 647                         x86_push_reg (code, X86_EAX);
 648                         arg_size = 4;
 649                 }
 650                 break;
 651         case SAVE_FP:
 652                 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
 653                 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
 654                 if (enable_arguments) {
 655                         x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
 656                         x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
 657                         arg_size = 8;
 658                 }
 659                 break;
 660         case SAVE_STRUCT:
 661                 if (enable_arguments) {
 662                         x86_push_membase (code, X86_EBP, 8);
 663                         arg_size = 4;
 664                 }
 665                 break;
 666         case SAVE_NONE:
 667         default:
 668                 break;
 669         }
 670
 671
 672         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
 673         x86_push_imm (code, method);
 674         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
 675         x86_call_code (code, 0);
 676         x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
 677
 678         switch (save_mode) {
 679         case SAVE_EAX_EDX:
 680                 x86_pop_reg (code, X86_EAX);
 681                 x86_pop_reg (code, X86_EDX);
 682                 break;
 683         case SAVE_EAX:
 684                 x86_pop_reg (code, X86_EAX);
 685                 break;
 686         case SAVE_FP:
 687                 x86_fld_membase (code, X86_ESP, 0, TRUE);
 688                 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
 689                 break;
 690         case SAVE_NONE:
 691         default:
 692                 break;
 693         }
 694
 695         return code;
 696 }
 697
 698 #define EMIT_COND_BRANCH(ins,cond,sign) \
 699 if (ins->flags & MONO_INST_BRLABEL) { \
 700         if (ins->inst_i0->inst_c0) { \
 701                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
 702         } else { \
 703                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
 704                 x86_branch32 (code, cond, 0, sign); \
 705         } \
 706 } else { \
 707         if (ins->inst_true_bb->native_offset) { \
 708                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
 709         } else { \
 710                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
 711                 if ((cfg->opt & MONO_OPT_BRANCH) && \
 712                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
 713                         x86_branch8 (code, cond, 0, sign); \
 714                 else \
 715                         x86_branch32 (code, cond, 0, sign); \
 716         } \
 717 }
 718
 719 /* emit an exception if condition is fail */
 720 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
 721         do {                                                        \
 722                 mono_add_patch_info (cfg, code - cfg->native_code,   \
 723                                     MONO_PATCH_INFO_EXC, exc_name);  \
 724                 x86_branch32 (code, cond, 0, signed);               \
 725         } while (0);
 726
 727 #define EMIT_FPCOMPARE(code) do { \
 728         x86_fcompp (code); \
 729         x86_fnstsw (code); \
 730 } while (0);
 731
 732 /* FIXME: Add more instructions */
 733 #define INST_IGNORES_CFLAGS(ins) (((ins)->opcode == CEE_BR) || ((ins)->opcode == OP_STORE_MEMBASE_IMM))
 734
 735 static void
 736 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
 737 {
 738         MonoInst *ins, *last_ins = NULL;
 739         ins = bb->code;
 740
 741         while (ins) {
 742
 743                 switch (ins->opcode) {
 744                 case OP_ICONST:
 745                         /* reg = 0 -> XOR (reg, reg) */
 746                         /* XOR sets cflags on x86, so we cant do it always */
 747                         if (ins->inst_c0 == 0 && ins->next && INST_IGNORES_CFLAGS (ins->next)) {
 748                                 ins->opcode = CEE_XOR;
 749                                 ins->sreg1 = ins->dreg;
 750                                 ins->sreg2 = ins->dreg;
 751                         }
 752                         break;
 753                 case OP_MUL_IMM:
 754                         /* remove unnecessary multiplication with 1 */
 755                         if (ins->inst_imm == 1) {
 756                                 if (ins->dreg != ins->sreg1) {
 757                                         ins->opcode = OP_MOVE;
 758                                 } else {
 759                                         last_ins->next = ins->next;
 760                                         ins = ins->next;
 761                                         continue;
 762                                 }
 763                         }
 764                         break;
 765                 case OP_COMPARE_IMM:
 766                         /* OP_COMPARE_IMM (reg, 0) --> OP_X86_TEST_NULL (reg) */
 767                         if (ins->inst_imm == 0 && ins->next &&
 768                             (ins->next->opcode == CEE_BEQ || ins->next->opcode == CEE_BNE_UN ||
 769                              ins->next->opcode == OP_CEQ)) {
 770                                 ins->opcode = OP_X86_TEST_NULL;
 771                         }
 772                         break;
 773                 case OP_LOAD_MEMBASE:
 774                 case OP_LOADI4_MEMBASE:
 775                         /*
 776                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
 777                          * OP_LOAD_MEMBASE offset(basereg), reg
 778                          */
 779                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
 780                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
 781                             ins->inst_basereg == last_ins->inst_destbasereg &&
 782                             ins->inst_offset == last_ins->inst_offset) {
 783                                 if (ins->dreg == last_ins->sreg1) {
 784                                         last_ins->next = ins->next;
 785                                         ins = ins->next;
 786                                         continue;
 787                                 } else {
 788                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
 789                                         ins->opcode = OP_MOVE;
 790                                         ins->sreg1 = last_ins->sreg1;
 791                                 }
 792
 793                         /*
 794                          * Note: reg1 must be different from the basereg in the second load
 795                          * OP_LOAD_MEMBASE offset(basereg), reg1
 796                          * OP_LOAD_MEMBASE offset(basereg), reg2
 797                          * -->
 798                          * OP_LOAD_MEMBASE offset(basereg), reg1
 799                          * OP_MOVE reg1, reg2
 800                          */
 801                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
 802                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
 803                               ins->inst_basereg != last_ins->dreg &&
 804                               ins->inst_basereg == last_ins->inst_basereg &&
 805                               ins->inst_offset == last_ins->inst_offset) {
 806
 807                                 if (ins->dreg == last_ins->dreg) {
 808                                         last_ins->next = ins->next;
 809                                         ins = ins->next;
 810                                         continue;
 811                                 } else {
 812                                         ins->opcode = OP_MOVE;
 813                                         ins->sreg1 = last_ins->dreg;
 814                                 }
 815
 816                                 //g_assert_not_reached ();
 817
 818 #if 0
 819                         /*
 820                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
 821                          * OP_LOAD_MEMBASE offset(basereg), reg
 822                          * -->
 823                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
 824                          * OP_ICONST reg, imm
 825                          */
 826                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
 827                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
 828                                    ins->inst_basereg == last_ins->inst_destbasereg &&
 829                                    ins->inst_offset == last_ins->inst_offset) {
 830                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
 831                                 ins->opcode = OP_ICONST;
 832                                 ins->inst_c0 = last_ins->inst_imm;
 833                                 g_assert_not_reached (); // check this rule
 834 #endif
 835                         }
 836                         break;
 837                 case OP_LOADU1_MEMBASE:
 838                 case OP_LOADI1_MEMBASE:
 839                   /*
 840                    * FIXME: Missing explanation
 841                    */
 842                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
 843                                         ins->inst_basereg == last_ins->inst_destbasereg &&
 844                                         ins->inst_offset == last_ins->inst_offset) {
 845                                 if (ins->dreg == last_ins->sreg1) {
 846                                         last_ins->next = ins->next;
 847                                         ins = ins->next;
 848                                         continue;
 849                                 } else {
 850                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
 851                                         ins->opcode = OP_MOVE;
 852                                         ins->sreg1 = last_ins->sreg1;
 853                                 }
 854                         }
 855                         break;
 856                 case OP_LOADU2_MEMBASE:
 857                 case OP_LOADI2_MEMBASE:
 858                   /*
 859                    * FIXME: Missing explanation
 860                    */
 861                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
 862                                         ins->inst_basereg == last_ins->inst_destbasereg &&
 863                                         ins->inst_offset == last_ins->inst_offset) {
 864                                 if (ins->dreg == last_ins->sreg1) {
 865                                         last_ins->next = ins->next;
 866                                         ins = ins->next;
 867                                         continue;
 868                                 } else {
 869                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
 870                                         ins->opcode = OP_MOVE;
 871                                         ins->sreg1 = last_ins->sreg1;
 872                                 }
 873                         }
 874                         break;
 875                 case CEE_CONV_I4:
 876                 case CEE_CONV_U4:
 877                 case OP_MOVE:
 878                         /*
 879                          * OP_MOVE reg, reg
 880                          */
 881                         if (ins->dreg == ins->sreg1) {
 882                                 if (last_ins)
 883                                         last_ins->next = ins->next;
 884                                 ins = ins->next;
 885                                 continue;
 886                         }
 887                         /*
 888                          * OP_MOVE sreg, dreg
 889                          * OP_MOVE dreg, sreg
 890                          */
 891                         if (last_ins && last_ins->opcode == OP_MOVE &&
 892                             ins->sreg1 == last_ins->dreg &&
 893                             ins->dreg == last_ins->sreg1) {
 894                                 last_ins->next = ins->next;
 895                                 ins = ins->next;
 896                                 continue;
 897                         }
 898                         break;
 899                 }
 900                 last_ins = ins;
 901                 ins = ins->next;
 902         }
 903         bb->last_ins = last_ins;
 904 }
 905
 906 static const int
 907 branch_cc_table [] = {
 908         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
 909         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
 910         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
 911 };
 912
 913 #define DEBUG(a) if (cfg->verbose_level > 1) a
 914 //#define DEBUG(a)
 915
 916 /*
 917  * returns the offset used by spillvar. It allocates a new
 918  * spill variable if necessary.
 919  */
 920 static int
 921 mono_spillvar_offset (MonoCompile *cfg, int spillvar)
 922 {
 923         MonoSpillInfo **si, *info;
 924         int i = 0;
 925
 926         si = &cfg->spill_info;
 927
 928         while (i <= spillvar) {
 929
 930                 if (!*si) {
 931                         *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
 932                         info->next = NULL;
 933                         cfg->stack_offset -= sizeof (gpointer);
 934                         info->offset = cfg->stack_offset;
 935                 }
 936
 937                 if (i == spillvar)
 938                         return (*si)->offset;
 939
 940                 i++;
 941                 si = &(*si)->next;
 942         }
 943
 944         g_assert_not_reached ();
 945         return 0;
 946 }
 947
 948 /*
 949  * returns the offset used by spillvar. It allocates a new
 950  * spill float variable if necessary.
 951  * (same as mono_spillvar_offset but for float)
 952  */
 953 static int
 954 mono_spillvar_offset_float (MonoCompile *cfg, int spillvar)
 955 {
 956         MonoSpillInfo **si, *info;
 957         int i = 0;
 958
 959         si = &cfg->spill_info_float;
 960
 961         while (i <= spillvar) {
 962
 963                 if (!*si) {
 964                         *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
 965                         info->next = NULL;
 966                         cfg->stack_offset -= sizeof (double);
 967                         info->offset = cfg->stack_offset;
 968                 }
 969
 970                 if (i == spillvar)
 971                         return (*si)->offset;
 972
 973                 i++;
 974                 si = &(*si)->next;
 975         }
 976
 977         g_assert_not_reached ();
 978         return 0;
 979 }
 980
 981 /*
 982  * Creates a store for spilled floating point items
 983  */
 984 static MonoInst*
 985 create_spilled_store_float (MonoCompile *cfg, int spill, int reg, MonoInst *ins)
 986 {
 987         MonoInst *store;
 988         MONO_INST_NEW (cfg, store, OP_STORER8_MEMBASE_REG);
 989         store->sreg1 = reg;
 990         store->inst_destbasereg = X86_EBP;
 991         store->inst_offset = mono_spillvar_offset_float (cfg, spill);
 992
 993         DEBUG (g_print ("SPILLED FLOAT STORE (%d at 0x%08x(%%sp)) (from %d)\n", spill, store->inst_offset, reg));
 994         return store;
 995 }
 996
 997 /*
 998  * Creates a load for spilled floating point items
 999  */
1000 static MonoInst*
1001 create_spilled_load_float (MonoCompile *cfg, int spill, int reg, MonoInst *ins)
1002 {
1003         MonoInst *load;
1004         MONO_INST_NEW (cfg, load, OP_LOADR8_SPILL_MEMBASE);
1005         load->dreg = reg;
1006         load->inst_basereg = X86_EBP;
1007         load->inst_offset = mono_spillvar_offset_float (cfg, spill);
1008
1009         DEBUG (g_print ("SPILLED FLOAT LOAD (%d at 0x%08x(%%sp)) (from %d)\n", spill, load->inst_offset, reg));
1010         return load;
1011 }
1012
1013 #define reg_is_freeable(r) ((r) >= 0 && (r) <= 7 && X86_IS_CALLEE ((r)))
1014
1015 typedef struct {
1016         int born_in;
1017         int killed_in;
1018         int last_use;
1019         int prev_use;
1020         int flags;              /* used to track fp spill/load */
1021 } RegTrack;
1022
1023 static const char*const * ins_spec = pentium_desc;
1024
1025 static void
1026 print_ins (int i, MonoInst *ins)
1027 {
1028         const char *spec = ins_spec [ins->opcode];
1029         g_print ("\t%-2d %s", i, mono_inst_name (ins->opcode));
1030         if (spec [MONO_INST_DEST]) {
1031                 if (ins->dreg >= MONO_MAX_IREGS)
1032                         g_print (" R%d <-", ins->dreg);
1033                 else
1034                         g_print (" %s <-", mono_arch_regname (ins->dreg));
1035         }
1036         if (spec [MONO_INST_SRC1]) {
1037                 if (ins->sreg1 >= MONO_MAX_IREGS)
1038                         g_print (" R%d", ins->sreg1);
1039                 else
1040                         g_print (" %s", mono_arch_regname (ins->sreg1));
1041         }
1042         if (spec [MONO_INST_SRC2]) {
1043                 if (ins->sreg2 >= MONO_MAX_IREGS)
1044                         g_print (" R%d", ins->sreg2);
1045                 else
1046                         g_print (" %s", mono_arch_regname (ins->sreg2));
1047         }
1048         if (spec [MONO_INST_CLOB])
1049                 g_print (" clobbers: %c", spec [MONO_INST_CLOB]);
1050         g_print ("\n");
1051 }
1052
1053 static void
1054 print_regtrack (RegTrack *t, int num)
1055 {
1056         int i;
1057         char buf [32];
1058         const char *r;
1059
1060         for (i = 0; i < num; ++i) {
1061                 if (!t [i].born_in)
1062                         continue;
1063                 if (i >= MONO_MAX_IREGS) {
1064                         g_snprintf (buf, sizeof(buf), "R%d", i);
1065                         r = buf;
1066                 } else
1067                         r = mono_arch_regname (i);
1068                 g_print ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].last_use);
1069         }
1070 }
1071
1072 typedef struct InstList InstList;
1073
1074 struct InstList {
1075         InstList *prev;
1076         InstList *next;
1077         MonoInst *data;
1078 };
1079
1080 static inline InstList*
1081 inst_list_prepend (MonoMemPool *pool, InstList *list, MonoInst *data)
1082 {
1083         InstList *item = mono_mempool_alloc (pool, sizeof (InstList));
1084         item->data = data;
1085         item->prev = NULL;
1086         item->next = list;
1087         if (list)
1088                 list->prev = item;
1089         return item;
1090 }
1091
1092 /*
1093  * Force the spilling of the variable in the symbolic register 'reg'.
1094  */
1095 static int
1096 get_register_force_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, int reg)
1097 {
1098         MonoInst *load;
1099         int i, sel, spill;
1100
1101         sel = cfg->rs->iassign [reg];
1102         /*i = cfg->rs->isymbolic [sel];
1103         g_assert (i == reg);*/
1104         i = reg;
1105         spill = ++cfg->spill_count;
1106         cfg->rs->iassign [i] = -spill - 1;
1107         mono_regstate_free_int (cfg->rs, sel);
1108         /* we need to create a spill var and insert a load to sel after the current instruction */
1109         MONO_INST_NEW (cfg, load, OP_LOAD_MEMBASE);
1110         load->dreg = sel;
1111         load->inst_basereg = X86_EBP;
1112         load->inst_offset = mono_spillvar_offset (cfg, spill);
1113         if (item->prev) {
1114                 while (ins->next != item->prev->data)
1115                         ins = ins->next;
1116         }
1117         load->next = ins->next;
1118         ins->next = load;
1119         DEBUG (g_print ("SPILLED LOAD (%d at 0x%08x(%%ebp)) R%d (freed %s)\n", spill, load->inst_offset, i, mono_arch_regname (sel)));
1120         i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
1121         g_assert (i == sel);
1122
1123         return sel;
1124 }
1125
1126 static int
1127 get_register_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, guint32 regmask, int reg)
1128 {
1129         MonoInst *load;
1130         int i, sel, spill;
1131
1132         DEBUG (g_print ("start regmask to assign R%d: 0x%08x (R%d <- R%d R%d)\n", reg, regmask, ins->dreg, ins->sreg1, ins->sreg2));
1133         /* exclude the registers in the current instruction */
1134         if (reg != ins->sreg1 && (reg_is_freeable (ins->sreg1) || (ins->sreg1 >= MONO_MAX_IREGS && cfg->rs->iassign [ins->sreg1] >= 0))) {
1135                 if (ins->sreg1 >= MONO_MAX_IREGS)
1136                         regmask &= ~ (1 << cfg->rs->iassign [ins->sreg1]);
1137                 else
1138                         regmask &= ~ (1 << ins->sreg1);
1139                 DEBUG (g_print ("excluding sreg1 %s\n", mono_arch_regname (ins->sreg1)));
1140         }
1141         if (reg != ins->sreg2 && (reg_is_freeable (ins->sreg2) || (ins->sreg2 >= MONO_MAX_IREGS && cfg->rs->iassign [ins->sreg2] >= 0))) {
1142                 if (ins->sreg2 >= MONO_MAX_IREGS)
1143                         regmask &= ~ (1 << cfg->rs->iassign [ins->sreg2]);
1144                 else
1145                         regmask &= ~ (1 << ins->sreg2);
1146                 DEBUG (g_print ("excluding sreg2 %s %d\n", mono_arch_regname (ins->sreg2), ins->sreg2));
1147         }
1148         if (reg != ins->dreg && reg_is_freeable (ins->dreg)) {
1149                 regmask &= ~ (1 << ins->dreg);
1150                 DEBUG (g_print ("excluding dreg %s\n", mono_arch_regname (ins->dreg)));
1151         }
1152
1153         DEBUG (g_print ("available regmask: 0x%08x\n", regmask));
1154         g_assert (regmask); /* need at least a register we can free */
1155         sel = -1;
1156         /* we should track prev_use and spill the register that's farther */
1157         for (i = 0; i < MONO_MAX_IREGS; ++i) {
1158                 if (regmask & (1 << i)) {
1159                         sel = i;
1160                         DEBUG (g_print ("selected register %s has assignment %d\n", mono_arch_regname (sel), cfg->rs->iassign [sel]));
1161                         break;
1162                 }
1163         }
1164         i = cfg->rs->isymbolic [sel];
1165         spill = ++cfg->spill_count;
1166         cfg->rs->iassign [i] = -spill - 1;
1167         mono_regstate_free_int (cfg->rs, sel);
1168         /* we need to create a spill var and insert a load to sel after the current instruction */
1169         MONO_INST_NEW (cfg, load, OP_LOAD_MEMBASE);
1170         load->dreg = sel;
1171         load->inst_basereg = X86_EBP;
1172         load->inst_offset = mono_spillvar_offset (cfg, spill);
1173         if (item->prev) {
1174                 while (ins->next != item->prev->data)
1175                         ins = ins->next;
1176         }
1177         load->next = ins->next;
1178         ins->next = load;
1179         DEBUG (g_print ("SPILLED LOAD (%d at 0x%08x(%%ebp)) R%d (freed %s)\n", spill, load->inst_offset, i, mono_arch_regname (sel)));
1180         i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
1181         g_assert (i == sel);
1182
1183         return sel;
1184 }
1185
1186 static MonoInst*
1187 create_copy_ins (MonoCompile *cfg, int dest, int src, MonoInst *ins)
1188 {
1189         MonoInst *copy;
1190         MONO_INST_NEW (cfg, copy, OP_MOVE);
1191         copy->dreg = dest;
1192         copy->sreg1 = src;
1193         if (ins) {
1194                 copy->next = ins->next;
1195                 ins->next = copy;
1196         }
1197         DEBUG (g_print ("\tforced copy from %s to %s\n", mono_arch_regname (src), mono_arch_regname (dest)));
1198         return copy;
1199 }
1200
1201 static MonoInst*
1202 create_spilled_store (MonoCompile *cfg, int spill, int reg, int prev_reg, MonoInst *ins)
1203 {
1204         MonoInst *store;
1205         MONO_INST_NEW (cfg, store, OP_STORE_MEMBASE_REG);
1206         store->sreg1 = reg;
1207         store->inst_destbasereg = X86_EBP;
1208         store->inst_offset = mono_spillvar_offset (cfg, spill);
1209         if (ins) {
1210                 store->next = ins->next;
1211                 ins->next = store;
1212         }
1213         DEBUG (g_print ("SPILLED STORE (%d at 0x%08x(%%ebp)) R%d (from %s)\n", spill, store->inst_offset, prev_reg, mono_arch_regname (reg)));
1214         return store;
1215 }
1216
1217 static void
1218 insert_before_ins (MonoInst *ins, InstList *item, MonoInst* to_insert)
1219 {
1220         MonoInst *prev;
1221         if (item->next) {
1222                 prev = item->next->data;
1223
1224                 while (prev->next != ins)
1225                         prev = prev->next;
1226                 to_insert->next = ins;
1227                 prev->next = to_insert;
1228         } else {
1229                 to_insert->next = ins;
1230         }
1231         /*
1232          * needed otherwise in the next instruction we can add an ins to the
1233          * end and that would get past this instruction.
1234          */
1235         item->data = to_insert;
1236 }
1237
1238
1239 #if  0
1240 static int
1241 alloc_int_reg (MonoCompile *cfg, InstList *curinst, MonoInst *ins, int sym_reg, guint32 allow_mask)
1242 {
1243         int val = cfg->rs->iassign [sym_reg];
1244         if (val < 0) {
1245                 int spill = 0;
1246                 if (val < -1) {
1247                         /* the register gets spilled after this inst */
1248                         spill = -val -1;
1249                 }
1250                 val = mono_regstate_alloc_int (cfg->rs, allow_mask);
1251                 if (val < 0)
1252                         val = get_register_spilling (cfg, curinst, ins, allow_mask, sym_reg);
1253                 cfg->rs->iassign [sym_reg] = val;
1254                 /* add option to store before the instruction for src registers */
1255                 if (spill)
1256                         create_spilled_store (cfg, spill, val, sym_reg, ins);
1257         }
1258         cfg->rs->isymbolic [val] = sym_reg;
1259         return val;
1260 }
1261 #endif
1262
1263 /* flags used in reginfo->flags */
1264 #define MONO_X86_FP_NEEDS_LOAD_SPILL    1
1265 #define MONO_X86_FP_NEEDS_SPILL                 2
1266 #define MONO_X86_FP_NEEDS_LOAD                  4
1267
1268 /*#include "cprop.c"*/
1269
1270 /*
1271  * Local register allocation.
1272  * We first scan the list of instructions and we save the liveness info of
1273  * each register (when the register is first used, when it's value is set etc.).
1274  * We also reverse the list of instructions (in the InstList list) because assigning
1275  * registers backwards allows for more tricks to be used.
1276  */
1277 void
1278 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1279 {
1280         MonoInst *ins;
1281         MonoRegState *rs = cfg->rs;
1282         int i, val, fpcount;
1283         RegTrack *reginfo, *reginfof;
1284         RegTrack *reginfo1, *reginfo2, *reginfod;
1285         InstList *tmp, *reversed = NULL;
1286         const char *spec;
1287         guint32 src1_mask, src2_mask, dest_mask;
1288         GList *fspill_list = NULL;
1289         int fspill = 0;
1290
1291         if (!bb->code)
1292                 return;
1293         rs->next_vireg = bb->max_ireg;
1294         rs->next_vfreg = bb->max_freg;
1295         mono_regstate_assign (rs);
1296         reginfo = g_malloc0 (sizeof (RegTrack) * rs->next_vireg);
1297         reginfof = g_malloc0 (sizeof (RegTrack) * rs->next_vfreg);
1298         rs->ifree_mask = X86_CALLEE_REGS;
1299
1300         ins = bb->code;
1301
1302         /*if (cfg->opt & MONO_OPT_COPYPROP)
1303                 local_copy_prop (cfg, ins);*/
1304
1305         i = 1;
1306         fpcount = 0;
1307         DEBUG (g_print ("LOCAL regalloc: basic block: %d\n", bb->block_num));
1308         /* forward pass on the instructions to collect register liveness info */
1309         while (ins) {
1310                 spec = ins_spec [ins->opcode];
1311                 DEBUG (print_ins (i, ins));
1312
1313                 if (spec [MONO_INST_SRC1]) {
1314                         if (spec [MONO_INST_SRC1] == 'f') {
1315                                 GList *spill;
1316                                 reginfo1 = reginfof;
1317
1318                                 spill = g_list_first (fspill_list);
1319                                 if (spill && fpcount < MONO_MAX_FREGS) {
1320                                         reginfo1 [ins->sreg1].flags |= MONO_X86_FP_NEEDS_LOAD;
1321                                         fspill_list = g_list_remove (fspill_list, spill->data);
1322                                 } else
1323                                         fpcount--;
1324                         }
1325                         else
1326                                 reginfo1 = reginfo;
1327                         reginfo1 [ins->sreg1].prev_use = reginfo1 [ins->sreg1].last_use;
1328                         reginfo1 [ins->sreg1].last_use = i;
1329                 } else {
1330                         ins->sreg1 = -1;
1331                 }
1332                 if (spec [MONO_INST_SRC2]) {
1333                         if (spec [MONO_INST_SRC2] == 'f') {
1334                                 GList *spill;
1335                                 reginfo2 = reginfof;
1336                                 spill = g_list_first (fspill_list);
1337                                 if (spill) {
1338                                         reginfo2 [ins->sreg2].flags |= MONO_X86_FP_NEEDS_LOAD;
1339                                         fspill_list = g_list_remove (fspill_list, spill->data);
1340                                         if (fpcount >= MONO_MAX_FREGS) {
1341                                                 fspill++;
1342                                                 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1343                                                 reginfo2 [ins->sreg2].flags |= MONO_X86_FP_NEEDS_LOAD_SPILL;
1344                                         }
1345                                 } else
1346                                         fpcount--;
1347                         }
1348                         else
1349                                 reginfo2 = reginfo;
1350                         reginfo2 [ins->sreg2].prev_use = reginfo2 [ins->sreg2].last_use;
1351                         reginfo2 [ins->sreg2].last_use = i;
1352                 } else {
1353                         ins->sreg2 = -1;
1354                 }
1355                 if (spec [MONO_INST_DEST]) {
1356                         if (spec [MONO_INST_DEST] == 'f') {
1357                                 reginfod = reginfof;
1358                                 if (fpcount >= MONO_MAX_FREGS) {
1359                                         reginfod [ins->dreg].flags |= MONO_X86_FP_NEEDS_SPILL;
1360                                         fspill++;
1361                                         fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1362                                         fpcount--;
1363                                 }
1364                                 fpcount++;
1365                         }
1366                         else
1367                                 reginfod = reginfo;
1368                         if (spec [MONO_INST_DEST] != 'b') /* it's not just a base register */
1369                                 reginfod [ins->dreg].killed_in = i;
1370                         reginfod [ins->dreg].prev_use = reginfod [ins->dreg].last_use;
1371                         reginfod [ins->dreg].last_use = i;
1372                         if (reginfod [ins->dreg].born_in == 0 || reginfod [ins->dreg].born_in > i)
1373                                 reginfod [ins->dreg].born_in = i;
1374                         if (spec [MONO_INST_DEST] == 'l') {
1375                                 /* result in eax:edx, the virtual register is allocated sequentially */
1376                                 reginfod [ins->dreg + 1].prev_use = reginfod [ins->dreg + 1].last_use;
1377                                 reginfod [ins->dreg + 1].last_use = i;
1378                                 if (reginfod [ins->dreg + 1].born_in == 0 || reginfod [ins->dreg + 1].born_in > i)
1379                                         reginfod [ins->dreg + 1].born_in = i;
1380                         }
1381                 } else {
1382                         ins->dreg = -1;
1383                 }
1384                 reversed = inst_list_prepend (cfg->mempool, reversed, ins);
1385                 ++i;
1386                 ins = ins->next;
1387         }
1388
1389         // todo: check if we have anything left on fp stack, in verify mode?
1390         fspill = 0;
1391
1392         DEBUG (print_regtrack (reginfo, rs->next_vireg));
1393         DEBUG (print_regtrack (reginfof, rs->next_vfreg));
1394         tmp = reversed;
1395         while (tmp) {
1396                 int prev_dreg, prev_sreg1, prev_sreg2;
1397                 dest_mask = src1_mask = src2_mask = X86_CALLEE_REGS;
1398                 --i;
1399                 ins = tmp->data;
1400                 spec = ins_spec [ins->opcode];
1401                 prev_dreg = -1;
1402                 DEBUG (g_print ("processing:"));
1403                 DEBUG (print_ins (i, ins));
1404                 if (spec [MONO_INST_CLOB] == 's') {
1405                         if (rs->ifree_mask & (1 << X86_ECX)) {
1406                                 DEBUG (g_print ("\tshortcut assignment of R%d to ECX\n", ins->sreg2));
1407                                 rs->iassign [ins->sreg2] = X86_ECX;
1408                                 rs->isymbolic [X86_ECX] = ins->sreg2;
1409                                 ins->sreg2 = X86_ECX;
1410                                 rs->ifree_mask &= ~ (1 << X86_ECX);
1411                         } else {
1412                                 int need_ecx_spill = TRUE;
1413                                 /*
1414                                  * we first check if src1/dreg is already assigned a register
1415                                  * and then we force a spill of the var assigned to ECX.
1416                                  */
1417                                 /* the destination register can't be ECX */
1418                                 dest_mask &= ~ (1 << X86_ECX);
1419                                 src1_mask &= ~ (1 << X86_ECX);
1420                                 val = rs->iassign [ins->dreg];
1421                                 /*
1422                                  * the destination register is already assigned to ECX:
1423                                  * we need to allocate another register for it and then
1424                                  * copy from this to ECX.
1425                                  */
1426                                 if (val == X86_ECX && ins->dreg != ins->sreg2) {
1427                                         int new_dest = mono_regstate_alloc_int (rs, dest_mask);
1428                                         if (new_dest < 0)
1429                                                 new_dest = get_register_spilling (cfg, tmp, ins, dest_mask, ins->dreg);
1430                                         g_assert (new_dest >= 0);
1431                                         ins->dreg = new_dest;
1432                                         create_copy_ins (cfg, X86_ECX, new_dest, ins);
1433                                         need_ecx_spill = FALSE;
1434                                         /*DEBUG (g_print ("\tforced spill of R%d\n", ins->dreg));
1435                                         val = get_register_force_spilling (cfg, tmp, ins, ins->dreg);
1436                                         rs->iassign [ins->dreg] = val;
1437                                         rs->isymbolic [val] = prev_dreg;
1438                                         ins->dreg = val;*/
1439                                 }
1440                                 val = rs->iassign [ins->sreg1];
1441                                 if (val == X86_ECX) {
1442                                         g_assert_not_reached ();
1443                                 } else if (val >= 0) {
1444                                         /*
1445                                          * the first src reg was already assigned to a register,
1446                                          * we need to copy it to the dest register because the
1447                                          * shift instruction clobbers the first operand.
1448                                          */
1449                                         MonoInst *copy = create_copy_ins (cfg, ins->dreg, val, NULL);
1450                                         insert_before_ins (ins, tmp, copy);
1451                                 }
1452                                 val = rs->iassign [ins->sreg2];
1453                                 if (val >= 0 && val != X86_ECX) {
1454                                         MonoInst *move = create_copy_ins (cfg, X86_ECX, val, NULL);
1455                                         DEBUG (g_print ("\tmoved arg from R%d (%d) to ECX\n", val, ins->sreg2));
1456                                         move->next = ins;
1457                                         g_assert_not_reached ();
1458                                         /* FIXME: where is move connected to the instruction list? */
1459                                         //tmp->prev->data->next = move;
1460                                 }
1461                                 if (need_ecx_spill && !(rs->ifree_mask & (1 << X86_ECX))) {
1462                                         DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [X86_ECX]));
1463                                         get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_ECX]);
1464                                         mono_regstate_free_int (rs, X86_ECX);
1465                                 }
1466                                 /* force-set sreg2 */
1467                                 rs->iassign [ins->sreg2] = X86_ECX;
1468                                 rs->isymbolic [X86_ECX] = ins->sreg2;
1469                                 ins->sreg2 = X86_ECX;
1470                                 rs->ifree_mask &= ~ (1 << X86_ECX);
1471                         }
1472                 } else if (spec [MONO_INST_CLOB] == 'd') { /* division */
1473                         int dest_reg = X86_EAX;
1474                         int clob_reg = X86_EDX;
1475                         if (spec [MONO_INST_DEST] == 'd') {
1476                                 dest_reg = X86_EDX; /* reminder */
1477                                 clob_reg = X86_EAX;
1478                         }
1479                         val = rs->iassign [ins->dreg];
1480                         if (0 && val >= 0 && val != dest_reg && !(rs->ifree_mask & (1 << dest_reg))) {
1481                                 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [dest_reg]));
1482                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [dest_reg]);
1483                                 mono_regstate_free_int (rs, dest_reg);
1484                         }
1485                         if (val < 0) {
1486                                 if (val < -1) {
1487                                         /* the register gets spilled after this inst */
1488                                         int spill = -val -1;
1489                                         dest_mask = 1 << clob_reg;
1490                                         prev_dreg = ins->dreg;
1491                                         val = mono_regstate_alloc_int (rs, dest_mask);
1492                                         if (val < 0)
1493                                                 val = get_register_spilling (cfg, tmp, ins, dest_mask, ins->dreg);
1494                                         rs->iassign [ins->dreg] = val;
1495                                         if (spill)
1496                                                 create_spilled_store (cfg, spill, val, prev_dreg, ins);
1497                                         DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_arch_regname (val), ins->dreg));
1498                                         rs->isymbolic [val] = prev_dreg;
1499                                         ins->dreg = val;
1500                                         if (val != dest_reg) { /* force a copy */
1501                                                 create_copy_ins (cfg, val, dest_reg, ins);
1502                                         }
1503                                 } else {
1504                                         DEBUG (g_print ("\tshortcut assignment of R%d to %s\n", ins->dreg, mono_arch_regname (dest_reg)));
1505                                         prev_dreg = ins->dreg;
1506                                         rs->iassign [ins->dreg] = dest_reg;
1507                                         rs->isymbolic [dest_reg] = ins->dreg;
1508                                         ins->dreg = dest_reg;
1509                                         rs->ifree_mask &= ~ (1 << dest_reg);
1510                                 }
1511                         } else {
1512                                 //DEBUG (g_print ("dest reg in div assigned: %s\n", mono_arch_regname (val)));
1513                                 if (val != dest_reg) { /* force a copy */
1514                                         create_copy_ins (cfg, val, dest_reg, ins);
1515                                         if (!(rs->ifree_mask & (1 << dest_reg)) && rs->isymbolic [dest_reg] >= MONO_MAX_IREGS) {
1516                                                 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [dest_reg]));
1517                                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [dest_reg]);
1518                                                 mono_regstate_free_int (rs, dest_reg);
1519                                         }
1520                                 }
1521                         }
1522                         if (!(rs->ifree_mask & (1 << clob_reg)) && (clob_reg != val) && (rs->isymbolic [clob_reg] >= 8)) {
1523                                 DEBUG (g_print ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1524                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [clob_reg]);
1525                                 mono_regstate_free_int (rs, clob_reg);
1526                         }
1527                         src1_mask = 1 << X86_EAX;
1528                         src2_mask = 1 << X86_ECX;
1529                 }
1530                 if (spec [MONO_INST_DEST] == 'l') {
1531                         if (!(rs->ifree_mask & (1 << X86_EAX))) {
1532                                 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [X86_EAX]));
1533                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_EAX]);
1534                                 mono_regstate_free_int (rs, X86_EAX);
1535                         }
1536                         if (!(rs->ifree_mask & (1 << X86_EDX))) {
1537                                 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [X86_EDX]));
1538                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_EDX]);
1539                                 mono_regstate_free_int (rs, X86_EDX);
1540                         }
1541                 }
1542
1543                 /* Track dreg */
1544                 if (spec [MONO_INST_DEST] == 'f') {
1545                         if (reginfof [ins->dreg].flags & MONO_X86_FP_NEEDS_SPILL) {
1546                                 GList *spill_node;
1547                                 MonoInst *store;
1548                                 spill_node = g_list_first (fspill_list);
1549                                 g_assert (spill_node);
1550
1551                                 store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->dreg, ins);
1552                                 insert_before_ins (ins, tmp, store);
1553                                 fspill_list = g_list_remove (fspill_list, spill_node->data);
1554                                 fspill--;
1555                         }
1556                 }
1557                 else if (ins->dreg >= MONO_MAX_IREGS) {
1558                         val = rs->iassign [ins->dreg];
1559                         prev_dreg = ins->dreg;
1560                         if (val < 0) {
1561                                 int spill = 0;
1562                                 if (val < -1) {
1563                                         /* the register gets spilled after this inst */
1564                                         spill = -val -1;
1565                                 }
1566                                 val = mono_regstate_alloc_int (rs, dest_mask);
1567                                 if (val < 0)
1568                                         val = get_register_spilling (cfg, tmp, ins, dest_mask, ins->dreg);
1569                                 rs->iassign [ins->dreg] = val;
1570                                 if (spill)
1571                                         create_spilled_store (cfg, spill, val, prev_dreg, ins);
1572                         }
1573                         DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_arch_regname (val), ins->dreg));
1574                         rs->isymbolic [val] = prev_dreg;
1575                         ins->dreg = val;
1576                         if (spec [MONO_INST_DEST] == 'l') {
1577                                 int hreg = prev_dreg + 1;
1578                                 val = rs->iassign [hreg];
1579                                 if (val < 0) {
1580                                         int spill = 0;
1581                                         if (val < -1) {
1582                                                 /* the register gets spilled after this inst */
1583                                                 spill = -val -1;
1584                                         }
1585                                         val = mono_regstate_alloc_int (rs, dest_mask);
1586                                         if (val < 0)
1587                                                 val = get_register_spilling (cfg, tmp, ins, dest_mask, hreg);
1588                                         rs->iassign [hreg] = val;
1589                                         if (spill)
1590                                                 create_spilled_store (cfg, spill, val, hreg, ins);
1591                                 }
1592                                 DEBUG (g_print ("\tassigned hreg %s to dest R%d\n", mono_arch_regname (val), hreg));
1593                                 rs->isymbolic [val] = hreg;
1594                                 /* FIXME:? ins->dreg = val; */
1595                                 if (ins->dreg == X86_EAX) {
1596                                         if (val != X86_EDX)
1597                                                 create_copy_ins (cfg, val, X86_EDX, ins);
1598                                 } else if (ins->dreg == X86_EDX) {
1599                                         if (val == X86_EAX) {
1600                                                 /* swap */
1601                                                 g_assert_not_reached ();
1602                                         } else {
1603                                                 /* two forced copies */
1604                                                 create_copy_ins (cfg, val, X86_EDX, ins);
1605                                                 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1606                                         }
1607                                 } else {
1608                                         if (val == X86_EDX) {
1609                                                 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1610                                         } else {
1611                                                 /* two forced copies */
1612                                                 create_copy_ins (cfg, val, X86_EDX, ins);
1613                                                 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1614                                         }
1615                                 }
1616                                 if (reg_is_freeable (val) && hreg >= 0 && reginfo [hreg].born_in >= i) {
1617                                         DEBUG (g_print ("\tfreeable %s (R%d)\n", mono_arch_regname (val), hreg));
1618                                         mono_regstate_free_int (rs, val);
1619                                 }
1620                         } else if (spec [MONO_INST_DEST] == 'a' && ins->dreg != X86_EAX && spec [MONO_INST_CLOB] != 'd') {
1621                                 /* this instruction only outputs to EAX, need to copy */
1622                                 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1623                         } else if (spec [MONO_INST_DEST] == 'd' && ins->dreg != X86_EDX && spec [MONO_INST_CLOB] != 'd') {
1624                                 create_copy_ins (cfg, ins->dreg, X86_EDX, ins);
1625                         }
1626                 }
1627                 if (spec [MONO_INST_DEST] != 'f' && reg_is_freeable (ins->dreg) && prev_dreg >= 0 && reginfo [prev_dreg].born_in >= i) {
1628                         DEBUG (g_print ("\tfreeable %s (R%d) (born in %d)\n", mono_arch_regname (ins->dreg), prev_dreg, reginfo [prev_dreg].born_in));
1629                         mono_regstate_free_int (rs, ins->dreg);
1630                 }
1631                 /* put src1 in EAX if it needs to be */
1632                 if (spec [MONO_INST_SRC1] == 'a') {
1633                         if (!(rs->ifree_mask & (1 << X86_EAX))) {
1634                                 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [X86_EAX]));
1635                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_EAX]);
1636                                 mono_regstate_free_int (rs, X86_EAX);
1637                         }
1638                         /* force-set sreg1 */
1639                         rs->iassign [ins->sreg1] = X86_EAX;
1640                         rs->isymbolic [X86_EAX] = ins->sreg1;
1641                         ins->sreg1 = X86_EAX;
1642                         rs->ifree_mask &= ~ (1 << X86_EAX);
1643                 }
1644
1645                 /* Track sreg1 */
1646                 if (spec [MONO_INST_SRC1] == 'f') {
1647                         if (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD) {
1648                                 MonoInst *load;
1649                                 MonoInst *store = NULL;
1650
1651                                 if (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD_SPILL) {
1652                                         GList *spill_node;
1653                                         spill_node = g_list_first (fspill_list);
1654                                         g_assert (spill_node);
1655
1656                                         store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->sreg1, ins);
1657                                         fspill_list = g_list_remove (fspill_list, spill_node->data);
1658                                 }
1659
1660                                 fspill++;
1661                                 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1662                                 load = create_spilled_load_float (cfg, fspill, ins->sreg1, ins);
1663                                 insert_before_ins (ins, tmp, load);
1664                                 if (store)
1665                                         insert_before_ins (load, tmp, store);
1666                         }
1667                 }
1668                 else if (ins->sreg1 >= MONO_MAX_IREGS) {
1669                         val = rs->iassign [ins->sreg1];
1670                         prev_sreg1 = ins->sreg1;
1671                         if (val < 0) {
1672                                 int spill = 0;
1673                                 if (val < -1) {
1674                                         /* the register gets spilled after this inst */
1675                                         spill = -val -1;
1676                                 }
1677                                 if (0 && ins->opcode == OP_MOVE) {
1678                                         /*
1679                                          * small optimization: the dest register is already allocated
1680                                          * but the src one is not: we can simply assign the same register
1681                                          * here and peephole will get rid of the instruction later.
1682                                          * This optimization may interfere with the clobbering handling:
1683                                          * it removes a mov operation that will be added again to handle clobbering.
1684                                          * There are also some other issues that should with make testjit.
1685                                          */
1686                                         mono_regstate_alloc_int (rs, 1 << ins->dreg);
1687                                         val = rs->iassign [ins->sreg1] = ins->dreg;
1688                                         //g_assert (val >= 0);
1689                                         DEBUG (g_print ("\tfast assigned sreg1 %s to R%d\n", mono_arch_regname (val), ins->sreg1));
1690                                 } else {
1691                                         //g_assert (val == -1); /* source cannot be spilled */
1692                                         val = mono_regstate_alloc_int (rs, src1_mask);
1693                                         if (val < 0)
1694                                                 val = get_register_spilling (cfg, tmp, ins, src1_mask, ins->sreg1);
1695                                         rs->iassign [ins->sreg1] = val;
1696                                         DEBUG (g_print ("\tassigned sreg1 %s to R%d\n", mono_arch_regname (val), ins->sreg1));
1697                                 }
1698                                 if (spill) {
1699                                         MonoInst *store = create_spilled_store (cfg, spill, val, prev_sreg1, NULL);
1700                                         insert_before_ins (ins, tmp, store);
1701                                 }
1702                         }
1703                         rs->isymbolic [val] = prev_sreg1;
1704                         ins->sreg1 = val;
1705                 } else {
1706                         prev_sreg1 = -1;
1707                 }
1708                 /* handle clobbering of sreg1 */
1709                 if ((spec [MONO_INST_CLOB] == '1' || spec [MONO_INST_CLOB] == 's') && ins->dreg != ins->sreg1) {
1710                         MonoInst *copy = create_copy_ins (cfg, ins->dreg, ins->sreg1, NULL);
1711                         DEBUG (g_print ("\tneed to copy sreg1 %s to dreg %s\n", mono_arch_regname (ins->sreg1), mono_arch_regname (ins->dreg)));
1712                         if (ins->sreg2 == -1 || spec [MONO_INST_CLOB] == 's') {
1713                                 /* note: the copy is inserted before the current instruction! */
1714                                 insert_before_ins (ins, tmp, copy);
1715                                 /* we set sreg1 to dest as well */
1716                                 prev_sreg1 = ins->sreg1 = ins->dreg;
1717                         } else {
1718                                 /* inserted after the operation */
1719                                 copy->next = ins->next;
1720                                 ins->next = copy;
1721                         }
1722                 }
1723                 /* track sreg2 */
1724                 if (spec [MONO_INST_SRC2] == 'f') {
1725                         if (reginfof [ins->sreg2].flags & MONO_X86_FP_NEEDS_LOAD) {
1726                                 MonoInst *load;
1727                                 MonoInst *store = NULL;
1728
1729                                 if (reginfof [ins->sreg2].flags & MONO_X86_FP_NEEDS_LOAD_SPILL) {
1730                                         GList *spill_node;
1731
1732                                         spill_node = g_list_first (fspill_list);
1733                                         g_assert (spill_node);
1734                                         if (spec [MONO_INST_SRC1] == 'f' && (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD_SPILL))
1735                                                 spill_node = g_list_next (spill_node);
1736
1737                                         store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->sreg2, ins);
1738                                         fspill_list = g_list_remove (fspill_list, spill_node->data);
1739                                 }
1740
1741                                 fspill++;
1742                                 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1743                                 load = create_spilled_load_float (cfg, fspill, ins->sreg2, ins);
1744                                 insert_before_ins (ins, tmp, load);
1745                                 if (store)
1746                                         insert_before_ins (load, tmp, store);
1747                         }
1748                 }
1749                 else if (ins->sreg2 >= MONO_MAX_IREGS) {
1750                         val = rs->iassign [ins->sreg2];
1751                         prev_sreg2 = ins->sreg2;
1752                         if (val < 0) {
1753                                 int spill = 0;
1754                                 if (val < -1) {
1755                                         /* the register gets spilled after this inst */
1756                                         spill = -val -1;
1757                                 }
1758                                 val = mono_regstate_alloc_int (rs, src2_mask);
1759                                 if (val < 0)
1760                                         val = get_register_spilling (cfg, tmp, ins, src2_mask, ins->sreg2);
1761                                 rs->iassign [ins->sreg2] = val;
1762                                 DEBUG (g_print ("\tassigned sreg2 %s to R%d\n", mono_arch_regname (val), ins->sreg2));
1763                                 if (spill)
1764                                         create_spilled_store (cfg, spill, val, prev_sreg2, ins);
1765                         }
1766                         rs->isymbolic [val] = prev_sreg2;
1767                         ins->sreg2 = val;
1768                         if (spec [MONO_INST_CLOB] == 's' && ins->sreg2 != X86_ECX) {
1769                                 DEBUG (g_print ("\tassigned sreg2 %s to R%d, but ECX is needed (R%d)\n", mono_arch_regname (val), ins->sreg2, rs->iassign [X86_ECX]));
1770                         }
1771                 } else {
1772                         prev_sreg2 = -1;
1773                 }
1774
1775                 if (spec [MONO_INST_CLOB] == 'c') {
1776                         int j, s;
1777                         guint32 clob_mask = X86_CALLEE_REGS;
1778                         for (j = 0; j < MONO_MAX_IREGS; ++j) {
1779                                 s = 1 << j;
1780                                 if ((clob_mask & s) && !(rs->ifree_mask & s) && j != ins->sreg1) {
1781                                         //g_warning ("register %s busy at call site\n", mono_arch_regname (j));
1782                                 }
1783                         }
1784                 }
1785                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
1786                         DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg1)));
1787                         mono_regstate_free_int (rs, ins->sreg1);
1788                 }
1789                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
1790                         DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg2)));
1791                         mono_regstate_free_int (rs, ins->sreg2);
1792                 }*/
1793
1794                 //DEBUG (print_ins (i, ins));
1795                 /* this may result from a insert_before call */
1796                 if (!tmp->next)
1797                         bb->code = tmp->data;
1798                 tmp = tmp->next;
1799         }
1800
1801         g_free (reginfo);
1802         g_free (reginfof);
1803         g_list_free (fspill_list);
1804 }
1805
1806 static unsigned char*
1807 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
1808 {
1809         x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
1810         x86_fnstcw_membase(code, X86_ESP, 0);
1811         x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
1812         x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
1813         x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
1814         x86_fldcw_membase (code, X86_ESP, 2);
1815         if (size == 8) {
1816                 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1817                 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
1818                 x86_pop_reg (code, dreg);
1819                 /* FIXME: need the high register
1820                  * x86_pop_reg (code, dreg_high);
1821                  */
1822         } else {
1823                 x86_push_reg (code, X86_EAX); // SP = SP - 4
1824                 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
1825                 x86_pop_reg (code, dreg);
1826         }
1827         x86_fldcw_membase (code, X86_ESP, 0);
1828         x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
1829
1830         if (size == 1)
1831                 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
1832         else if (size == 2)
1833                 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
1834         return code;
1835 }
1836
1837 static unsigned char*
1838 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
1839 {
1840         int sreg = tree->sreg1;
1841 #ifdef PLATFORM_WIN32
1842         guint8* br[5];
1843
1844         /*
1845          * Under Windows:
1846          * If requested stack size is larger than one page,
1847          * perform stack-touch operation
1848          */
1849         /*
1850          * Generate stack probe code.
1851          * Under Windows, it is necessary to allocate one page at a time,
1852          * "touching" stack after each successful sub-allocation. This is
1853          * because of the way stack growth is implemented - there is a
1854          * guard page before the lowest stack page that is currently commited.
1855          * Stack normally grows sequentially so OS traps access to the
1856          * guard page and commits more pages when needed.
1857          */
1858         x86_test_reg_imm (code, sreg, ~0xFFF);
1859         br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1860
1861         br[2] = code; /* loop */
1862         x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
1863         x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
1864         x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
1865         x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
1866         br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
1867         x86_patch (br[3], br[2]);
1868         x86_test_reg_reg (code, sreg, sreg);
1869         br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1870         x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
1871
1872         br[1] = code; x86_jump8 (code, 0);
1873
1874         x86_patch (br[0], code);
1875         x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
1876         x86_patch (br[1], code);
1877         x86_patch (br[4], code);
1878 #else /* PLATFORM_WIN32 */
1879         x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
1880 #endif
1881         if (tree->flags & MONO_INST_INIT) {
1882                 int offset = 0;
1883                 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
1884                         x86_push_reg (code, X86_EAX);
1885                         offset += 4;
1886                 }
1887                 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
1888                         x86_push_reg (code, X86_ECX);
1889                         offset += 4;
1890                 }
1891                 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
1892                         x86_push_reg (code, X86_EDI);
1893                         offset += 4;
1894                 }
1895
1896                 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
1897                 if (sreg != X86_ECX)
1898                         x86_mov_reg_reg (code, X86_ECX, sreg, 4);
1899                 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
1900
1901                 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
1902                 x86_cld (code);
1903                 x86_prefix (code, X86_REP_PREFIX);
1904                 x86_stosl (code);
1905
1906                 if (tree->dreg != X86_EDI && sreg != X86_EDI)
1907                         x86_pop_reg (code, X86_EDI);
1908                 if (tree->dreg != X86_ECX && sreg != X86_ECX)
1909                         x86_pop_reg (code, X86_ECX);
1910                 if (tree->dreg != X86_EAX && sreg != X86_EAX)
1911                         x86_pop_reg (code, X86_EAX);
1912         }
1913         return code;
1914 }
1915
1916 #define REAL_PRINT_REG(text,reg) \
1917 mono_assert (reg >= 0); \
1918 x86_push_reg (code, X86_EAX); \
1919 x86_push_reg (code, X86_EDX); \
1920 x86_push_reg (code, X86_ECX); \
1921 x86_push_reg (code, reg); \
1922 x86_push_imm (code, reg); \
1923 x86_push_imm (code, text " %d %p\n"); \
1924 x86_mov_reg_imm (code, X86_EAX, printf); \
1925 x86_call_reg (code, X86_EAX); \
1926 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
1927 x86_pop_reg (code, X86_ECX); \
1928 x86_pop_reg (code, X86_EDX); \
1929 x86_pop_reg (code, X86_EAX);
1930
1931 void
1932 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
1933 {
1934         MonoInst *ins;
1935         MonoCallInst *call;
1936         guint offset;
1937         guint8 *code = cfg->native_code + cfg->code_len;
1938         MonoInst *last_ins = NULL;
1939         guint last_offset = 0;
1940         int max_len, cpos;
1941
1942         if (cfg->opt & MONO_OPT_PEEPHOLE)
1943                 peephole_pass (cfg, bb);
1944
1945 #if 0
1946         /*
1947          * various stratgies to align BBs. Using real loop detection or simply
1948          * aligning every block leads to more consistent benchmark results,
1949          * but usually slows down the code
1950          * we should do the alignment outside this function or we should adjust
1951          * bb->native offset as well or the code is effectively slowed down!
1952          */
1953         /* align all blocks */
1954 //      if ((pad = (cfg->code_len & (align - 1)))) {
1955         /* poor man loop start detection */
1956 //      if (bb->code && bb->in_count && bb->in_bb [0]->cil_code > bb->cil_code && (pad = (cfg->code_len & (align - 1)))) {
1957         /* consider real loop detection and nesting level */
1958 //      if (bb->loop_blocks && bb->nesting < 3 && (pad = (cfg->code_len & (align - 1)))) {
1959         /* consider real loop detection */
1960         if (bb->loop_blocks && (pad = (cfg->code_len & (align - 1)))) {
1961                 pad = align - pad;
1962                 x86_padding (code, pad);
1963                 cfg->code_len += pad;
1964                 bb->native_offset = cfg->code_len;
1965         }
1966 #endif
1967
1968         if (cfg->verbose_level > 2)
1969                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
1970
1971         cpos = bb->max_offset;
1972
1973         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
1974                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
1975                 g_assert (!mono_compile_aot);
1976                 cpos += 6;
1977
1978                 cov->data [bb->dfn].cil_code = bb->cil_code;
1979                 /* this is not thread save, but good enough */
1980                 x86_inc_mem (code, &cov->data [bb->dfn].count);
1981         }
1982
1983         offset = code - cfg->native_code;
1984
1985         ins = bb->code;
1986         while (ins) {
1987                 offset = code - cfg->native_code;
1988
1989                 max_len = ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
1990
1991                 if (offset > (cfg->code_size - max_len - 16)) {
1992                         cfg->code_size *= 2;
1993                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
1994                         code = cfg->native_code + offset;
1995                         mono_jit_stats.code_reallocs++;
1996                 }
1997
1998                 mono_debug_record_line_number (cfg, ins, offset);
1999
2000                 switch (ins->opcode) {
2001                 case OP_BIGMUL:
2002                         x86_mul_reg (code, ins->sreg2, TRUE);
2003                         break;
2004                 case OP_BIGMUL_UN:
2005                         x86_mul_reg (code, ins->sreg2, FALSE);
2006                         break;
2007                 case OP_X86_SETEQ_MEMBASE:
2008                         x86_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2009                         break;
2010                 case OP_STOREI1_MEMBASE_IMM:
2011                         x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2012                         break;
2013                 case OP_STOREI2_MEMBASE_IMM:
2014                         x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2015                         break;
2016                 case OP_STORE_MEMBASE_IMM:
2017                 case OP_STOREI4_MEMBASE_IMM:
2018                         x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2019                         break;
2020                 case OP_STOREI1_MEMBASE_REG:
2021                         x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2022                         break;
2023                 case OP_STOREI2_MEMBASE_REG:
2024                         x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2025                         break;
2026                 case OP_STORE_MEMBASE_REG:
2027                 case OP_STOREI4_MEMBASE_REG:
2028                         x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2029                         break;
2030                 case CEE_LDIND_I:
2031                 case CEE_LDIND_I4:
2032                 case CEE_LDIND_U4:
2033                         x86_mov_reg_mem (code, ins->dreg, ins->inst_p0, 4);
2034                         break;
2035                 case OP_LOADU4_MEM:
2036                         x86_mov_reg_imm (code, ins->dreg, ins->inst_p0);
2037                         x86_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2038                         break;
2039                 case OP_LOAD_MEMBASE:
2040                 case OP_LOADI4_MEMBASE:
2041                 case OP_LOADU4_MEMBASE:
2042                         x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2043                         break;
2044                 case OP_LOADU1_MEMBASE:
2045                         x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2046                         break;
2047                 case OP_LOADI1_MEMBASE:
2048                         x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2049                         break;
2050                 case OP_LOADU2_MEMBASE:
2051                         x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2052                         break;
2053                 case OP_LOADI2_MEMBASE:
2054                         x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2055                         break;
2056                 case CEE_CONV_I1:
2057                         x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2058                         break;
2059                 case CEE_CONV_I2:
2060                         x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2061                         break;
2062                 case CEE_CONV_U1:
2063                         x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2064                         break;
2065                 case CEE_CONV_U2:
2066                         x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2067                         break;
2068                 case OP_COMPARE:
2069                         x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2070                         break;
2071                 case OP_COMPARE_IMM:
2072                         x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2073                         break;
2074                 case OP_X86_COMPARE_MEMBASE_REG:
2075                         x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2076                         break;
2077                 case OP_X86_COMPARE_MEMBASE_IMM:
2078                         x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2079                         break;
2080                 case OP_X86_COMPARE_REG_MEMBASE:
2081                         x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2082                         break;
2083                 case OP_X86_TEST_NULL:
2084                         x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2085                         break;
2086                 case OP_X86_ADD_MEMBASE_IMM:
2087                         x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2088                         break;
2089                 case OP_X86_SUB_MEMBASE_IMM:
2090                         x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2091                         break;
2092                 case OP_X86_INC_MEMBASE:
2093                         x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2094                         break;
2095                 case OP_X86_INC_REG:
2096                         x86_inc_reg (code, ins->dreg);
2097                         break;
2098                 case OP_X86_DEC_MEMBASE:
2099                         x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2100                         break;
2101                 case OP_X86_DEC_REG:
2102                         x86_dec_reg (code, ins->dreg);
2103                         break;
2104                 case CEE_BREAK:
2105                         x86_breakpoint (code);
2106                         break;
2107                 case OP_ADDCC:
2108                 case CEE_ADD:
2109                         x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2110                         break;
2111                 case OP_ADC:
2112                         x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2113                         break;
2114                 case OP_ADD_IMM:
2115                         x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2116                         break;
2117                 case OP_ADC_IMM:
2118                         x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2119                         break;
2120                 case OP_SUBCC:
2121                 case CEE_SUB:
2122                         x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2123                         break;
2124                 case OP_SBB:
2125                         x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2126                         break;
2127                 case OP_SUB_IMM:
2128                         x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2129                         break;
2130                 case OP_SBB_IMM:
2131                         x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2132                         break;
2133                 case CEE_AND:
2134                         x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2135                         break;
2136                 case OP_AND_IMM:
2137                         x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2138                         break;
2139                 case CEE_DIV:
2140                         x86_cdq (code);
2141                         x86_div_reg (code, ins->sreg2, TRUE);
2142                         break;
2143                 case CEE_DIV_UN:
2144                         x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2145                         x86_div_reg (code, ins->sreg2, FALSE);
2146                         break;
2147                 case OP_DIV_IMM:
2148                         x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2149                         x86_cdq (code);
2150                         x86_div_reg (code, ins->sreg2, TRUE);
2151                         break;
2152                 case CEE_REM:
2153                         x86_cdq (code);
2154                         x86_div_reg (code, ins->sreg2, TRUE);
2155                         break;
2156                 case CEE_REM_UN:
2157                         x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2158                         x86_div_reg (code, ins->sreg2, FALSE);
2159                         break;
2160                 case OP_REM_IMM:
2161                         x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2162                         x86_cdq (code);
2163                         x86_div_reg (code, ins->sreg2, TRUE);
2164                         break;
2165                 case CEE_OR:
2166                         x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2167                         break;
2168                 case OP_OR_IMM:
2169                         x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2170                         break;
2171                 case CEE_XOR:
2172                         x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2173                         break;
2174                 case OP_XOR_IMM:
2175                         x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2176                         break;
2177                 case CEE_SHL:
2178                         g_assert (ins->sreg2 == X86_ECX);
2179                         x86_shift_reg (code, X86_SHL, ins->dreg);
2180                         break;
2181                 case CEE_SHR:
2182                         g_assert (ins->sreg2 == X86_ECX);
2183                         x86_shift_reg (code, X86_SAR, ins->dreg);
2184                         break;
2185                 case OP_SHR_IMM:
2186                         x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2187                         break;
2188                 case OP_SHR_UN_IMM:
2189                         x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2190                         break;
2191                 case CEE_SHR_UN:
2192                         g_assert (ins->sreg2 == X86_ECX);
2193                         x86_shift_reg (code, X86_SHR, ins->dreg);
2194                         break;
2195                 case OP_SHL_IMM:
2196                         x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2197                         break;
2198                 case CEE_NOT:
2199                         x86_not_reg (code, ins->sreg1);
2200                         break;
2201                 case CEE_NEG:
2202                         x86_neg_reg (code, ins->sreg1);
2203                         break;
2204                 case OP_SEXT_I1:
2205                         x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2206                         break;
2207                 case OP_SEXT_I2:
2208                         x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2209                         break;
2210                 case CEE_MUL:
2211                         x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2212                         break;
2213                 case OP_MUL_IMM:
2214                         x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2215                         break;
2216                 case CEE_MUL_OVF:
2217                         x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2218                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2219                         break;
2220                 case CEE_MUL_OVF_UN: {
2221                         /* the mul operation and the exception check should most likely be split */
2222                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2223                         /*g_assert (ins->sreg2 == X86_EAX);
2224                         g_assert (ins->dreg == X86_EAX);*/
2225                         if (ins->sreg2 == X86_EAX) {
2226                                 non_eax_reg = ins->sreg1;
2227                         } else if (ins->sreg1 == X86_EAX) {
2228                                 non_eax_reg = ins->sreg2;
2229                         } else {
2230                                 /* no need to save since we're going to store to it anyway */
2231                                 if (ins->dreg != X86_EAX) {
2232                                         saved_eax = TRUE;
2233                                         x86_push_reg (code, X86_EAX);
2234                                 }
2235                                 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
2236                                 non_eax_reg = ins->sreg2;
2237                         }
2238                         if (ins->dreg == X86_EDX) {
2239                                 if (!saved_eax) {
2240                                         saved_eax = TRUE;
2241                                         x86_push_reg (code, X86_EAX);
2242                                 }
2243                         } else if (ins->dreg != X86_EAX) {
2244                                 saved_edx = TRUE;
2245                                 x86_push_reg (code, X86_EDX);
2246                         }
2247                         x86_mul_reg (code, non_eax_reg, FALSE);
2248                         /* save before the check since pop and mov don't change the flags */
2249                         if (ins->dreg != X86_EAX)
2250                                 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2251                         if (saved_edx)
2252                                 x86_pop_reg (code, X86_EDX);
2253                         if (saved_eax)
2254                                 x86_pop_reg (code, X86_EAX);
2255                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2256                         break;
2257                 }
2258                 case OP_ICONST:
2259                         x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
2260                         break;
2261                 case OP_AOTCONST:
2262                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2263                         x86_mov_reg_imm (code, ins->dreg, 0);
2264                         break;
2265                 case CEE_CONV_I4:
2266                 case OP_MOVE:
2267                         x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2268                         break;
2269                 case CEE_CONV_U4:
2270                         g_assert_not_reached ();
2271                 case CEE_JMP: {
2272                         /*
2273                          * Note: this 'frame destruction' logic is useful for tail calls, too.
2274                          * Keep in sync with the code in emit_epilog.
2275                          */
2276                         int pos = 0;
2277
2278                         /* FIXME: no tracing support... */
2279                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2280                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2281                         /* reset offset to make max_len work */
2282                         offset = code - cfg->native_code;
2283
2284                         g_assert (!cfg->method->save_lmf);
2285
2286                         if (cfg->used_int_regs & (1 << X86_EBX))
2287                                 pos -= 4;
2288                         if (cfg->used_int_regs & (1 << X86_EDI))
2289                                 pos -= 4;
2290                         if (cfg->used_int_regs & (1 << X86_ESI))
2291                                 pos -= 4;
2292                         if (pos)
2293                                 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
2294
2295                         if (cfg->used_int_regs & (1 << X86_ESI))
2296                                 x86_pop_reg (code, X86_ESI);
2297                         if (cfg->used_int_regs & (1 << X86_EDI))
2298                                 x86_pop_reg (code, X86_EDI);
2299                         if (cfg->used_int_regs & (1 << X86_EBX))
2300                                 x86_pop_reg (code, X86_EBX);
2301
2302                         /* restore ESP/EBP */
2303                         x86_leave (code);
2304                         offset = code - cfg->native_code;
2305                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2306                         x86_jump32 (code, 0);
2307                         break;
2308                 }
2309                 case OP_CHECK_THIS:
2310                         /* ensure ins->sreg1 is not NULL */
2311                         x86_alu_membase_imm (code, X86_CMP, ins->sreg1, 0, 0);
2312                         break;
2313                 case OP_ARGLIST: {
2314                         int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
2315                         x86_push_reg (code, hreg);
2316                         x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
2317                         x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
2318                         x86_pop_reg (code, hreg);
2319                         break;
2320                 }
2321                 case OP_FCALL:
2322                 case OP_LCALL:
2323                 case OP_VCALL:
2324                 case OP_VOIDCALL:
2325                 case CEE_CALL:
2326                         call = (MonoCallInst*)ins;
2327                         if (ins->flags & MONO_INST_HAS_METHOD)
2328                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
2329                         else {
2330                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
2331                         }
2332                         x86_call_code (code, 0);
2333                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2334                                 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2335                         break;
2336                 case OP_FCALL_REG:
2337                 case OP_LCALL_REG:
2338                 case OP_VCALL_REG:
2339                 case OP_VOIDCALL_REG:
2340                 case OP_CALL_REG:
2341                         call = (MonoCallInst*)ins;
2342                         x86_call_reg (code, ins->sreg1);
2343                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2344                                 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2345                         break;
2346                 case OP_FCALL_MEMBASE:
2347                 case OP_LCALL_MEMBASE:
2348                 case OP_VCALL_MEMBASE:
2349                 case OP_VOIDCALL_MEMBASE:
2350                 case OP_CALL_MEMBASE:
2351                         call = (MonoCallInst*)ins;
2352                         x86_call_membase (code, ins->sreg1, ins->inst_offset);
2353                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2354                                 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2355                         break;
2356                 case OP_OUTARG:
2357                 case OP_X86_PUSH:
2358                         x86_push_reg (code, ins->sreg1);
2359                         break;
2360                 case OP_X86_PUSH_IMM:
2361                         x86_push_imm (code, ins->inst_imm);
2362                         break;
2363                 case OP_X86_PUSH_MEMBASE:
2364                         x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
2365                         break;
2366                 case OP_X86_PUSH_OBJ:
2367                         x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
2368                         x86_push_reg (code, X86_EDI);
2369                         x86_push_reg (code, X86_ESI);
2370                         x86_push_reg (code, X86_ECX);
2371                         if (ins->inst_offset)
2372                                 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
2373                         else
2374                                 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
2375                         x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2376                         x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
2377                         x86_cld (code);
2378                         x86_prefix (code, X86_REP_PREFIX);
2379                         x86_movsd (code);
2380                         x86_pop_reg (code, X86_ECX);
2381                         x86_pop_reg (code, X86_ESI);
2382                         x86_pop_reg (code, X86_EDI);
2383                         break;
2384                 case OP_X86_LEA:
2385                         x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->unused);
2386                         break;
2387                 case OP_X86_LEA_MEMBASE:
2388                         x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
2389                         break;
2390                 case OP_X86_XCHG:
2391                         x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
2392                         break;
2393                 case OP_LOCALLOC:
2394                         /* keep alignment */
2395                         x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
2396                         x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
2397                         code = mono_emit_stack_alloc (code, ins);
2398                         x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2399                         break;
2400                 case CEE_RET:
2401                         x86_ret (code);
2402                         break;
2403                 case CEE_THROW: {
2404                         x86_push_reg (code, ins->sreg1);
2405                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2406                                              (gpointer)"mono_arch_throw_exception");
2407                         x86_call_code (code, 0);
2408                         break;
2409                 }
2410                 case OP_CALL_HANDLER:
2411                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2412                         x86_call_imm (code, 0);
2413                         break;
2414                 case OP_LABEL:
2415                         ins->inst_c0 = code - cfg->native_code;
2416                         break;
2417                 case CEE_BR:
2418                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
2419                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
2420                         //break;
2421                         if (ins->flags & MONO_INST_BRLABEL) {
2422                                 if (ins->inst_i0->inst_c0) {
2423                                         x86_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
2424                                 } else {
2425                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
2426                                         x86_jump32 (code, 0);
2427                                 }
2428                         } else {
2429                                 if (ins->inst_target_bb->native_offset) {
2430                                         x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
2431                                 } else {
2432                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2433                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
2434                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
2435                                                 x86_jump8 (code, 0);
2436                                         else
2437                                                 x86_jump32 (code, 0);
2438                                 }
2439                         }
2440                         break;
2441                 case OP_BR_REG:
2442                         x86_jump_reg (code, ins->sreg1);
2443                         break;
2444                 case OP_CEQ:
2445                         x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
2446                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2447                         break;
2448                 case OP_CLT:
2449                         x86_set_reg (code, X86_CC_LT, ins->dreg, TRUE);
2450                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2451                         break;
2452                 case OP_CLT_UN:
2453                         x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
2454                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2455                         break;
2456                 case OP_CGT:
2457                         x86_set_reg (code, X86_CC_GT, ins->dreg, TRUE);
2458                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2459                         break;
2460                 case OP_CGT_UN:
2461                         x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
2462                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2463                         break;
2464                 case OP_COND_EXC_EQ:
2465                 case OP_COND_EXC_NE_UN:
2466                 case OP_COND_EXC_LT:
2467                 case OP_COND_EXC_LT_UN:
2468                 case OP_COND_EXC_GT:
2469                 case OP_COND_EXC_GT_UN:
2470                 case OP_COND_EXC_GE:
2471                 case OP_COND_EXC_GE_UN:
2472                 case OP_COND_EXC_LE:
2473                 case OP_COND_EXC_LE_UN:
2474                 case OP_COND_EXC_OV:
2475                 case OP_COND_EXC_NO:
2476                 case OP_COND_EXC_C:
2477                 case OP_COND_EXC_NC:
2478                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
2479                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
2480                         break;
2481                 case CEE_BEQ:
2482                 case CEE_BNE_UN:
2483                 case CEE_BLT:
2484                 case CEE_BLT_UN:
2485                 case CEE_BGT:
2486                 case CEE_BGT_UN:
2487                 case CEE_BGE:
2488                 case CEE_BGE_UN:
2489                 case CEE_BLE:
2490                 case CEE_BLE_UN:
2491                         EMIT_COND_BRANCH (ins, branch_cc_table [ins->opcode - CEE_BEQ], (ins->opcode < CEE_BNE_UN));
2492                         break;
2493
2494                 /* floating point opcodes */
2495                 case OP_R8CONST: {
2496                         double d = *(double *)ins->inst_p0;
2497
2498                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
2499                                 x86_fldz (code);
2500                         } else if (d == 1.0) {
2501                                 x86_fld1 (code);
2502                         } else {
2503                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
2504                                 x86_fld (code, NULL, TRUE);
2505                         }
2506                         break;
2507                 }
2508                 case OP_R4CONST: {
2509                         float f = *(float *)ins->inst_p0;
2510
2511                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
2512                                 x86_fldz (code);
2513                         } else if (f == 1.0) {
2514                                 x86_fld1 (code);
2515                         } else {
2516                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
2517                                 x86_fld (code, NULL, FALSE);
2518                         }
2519                         break;
2520                 }
2521                 case OP_STORER8_MEMBASE_REG:
2522                         x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
2523                         break;
2524                 case OP_LOADR8_SPILL_MEMBASE:
2525                         x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
2526                         x86_fxch (code, 1);
2527                         break;
2528                 case OP_LOADR8_MEMBASE:
2529                         x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
2530                         break;
2531                 case OP_STORER4_MEMBASE_REG:
2532                         x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
2533                         break;
2534                 case OP_LOADR4_MEMBASE:
2535                         x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
2536                         break;
2537                 case CEE_CONV_R4: /* FIXME: change precision */
2538                 case CEE_CONV_R8:
2539                         x86_push_reg (code, ins->sreg1);
2540                         x86_fild_membase (code, X86_ESP, 0, FALSE);
2541                         x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2542                         break;
2543                 case OP_X86_FP_LOAD_I8:
2544                         x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
2545                         break;
2546                 case OP_X86_FP_LOAD_I4:
2547                         x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
2548                         break;
2549                 case OP_FCONV_TO_I1:
2550                         code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
2551                         break;
2552                 case OP_FCONV_TO_U1:
2553                         code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
2554                         break;
2555                 case OP_FCONV_TO_I2:
2556                         code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
2557                         break;
2558                 case OP_FCONV_TO_U2:
2559                         code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
2560                         break;
2561                 case OP_FCONV_TO_I4:
2562                 case OP_FCONV_TO_I:
2563                         code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
2564                         break;
2565                 case OP_FCONV_TO_I8:
2566                         /* we defined this instruction to output only to eax:edx */
2567                         x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2568                         x86_fnstcw_membase(code, X86_ESP, 0);
2569                         x86_mov_reg_membase (code, X86_EAX, X86_ESP, 0, 2);
2570                         x86_alu_reg_imm (code, X86_OR, X86_EAX, 0xc00);
2571                         x86_mov_membase_reg (code, X86_ESP, 2, X86_EAX, 2);
2572                         x86_fldcw_membase (code, X86_ESP, 2);
2573                         x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2574                         x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2575                         x86_pop_reg (code, X86_EAX);
2576                         x86_pop_reg (code, X86_EDX);
2577                         x86_fldcw_membase (code, X86_ESP, 0);
2578                         x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2579                         break;
2580                 case OP_LCONV_TO_R_UN: {
2581                         static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
2582                         guint8 *br;
2583
2584                         /* load 64bit integer to FP stack */
2585                         x86_push_imm (code, 0);
2586                         x86_push_reg (code, ins->sreg2);
2587                         x86_push_reg (code, ins->sreg1);
2588                         x86_fild_membase (code, X86_ESP, 0, TRUE);
2589                         /* store as 80bit FP value */
2590                         x86_fst80_membase (code, X86_ESP, 0);
2591
2592                         /* test if lreg is negative */
2593                         x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
2594                         br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
2595
2596                         /* add correction constant mn */
2597                         x86_fld80_mem (code, mn);
2598                         x86_fld80_membase (code, X86_ESP, 0);
2599                         x86_fp_op_reg (code, X86_FADD, 1, TRUE);
2600                         x86_fst80_membase (code, X86_ESP, 0);
2601
2602                         x86_patch (br, code);
2603
2604                         x86_fld80_membase (code, X86_ESP, 0);
2605                         x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
2606
2607                         break;
2608                 }
2609                 case OP_LCONV_TO_OVF_I: {
2610                         guint8 *br [3], *label [1];
2611
2612                         /*
2613                          * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
2614                          */
2615                         x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2616
2617                         /* If the low word top bit is set, see if we are negative */
2618                         br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
2619                         /* We are not negative (no top bit set, check for our top word to be zero */
2620                         x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
2621                         br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2622                         label [0] = code;
2623
2624                         /* throw exception */
2625                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
2626                         x86_jump32 (code, 0);
2627
2628                         x86_patch (br [0], code);
2629                         /* our top bit is set, check that top word is 0xfffffff */
2630                         x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
2631
2632                         x86_patch (br [1], code);
2633                         /* nope, emit exception */
2634                         br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
2635                         x86_patch (br [2], label [0]);
2636
2637                         if (ins->dreg != ins->sreg1)
2638                                 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2639                         break;
2640                 }
2641                 case OP_FADD:
2642                         x86_fp_op_reg (code, X86_FADD, 1, TRUE);
2643                         break;
2644                 case OP_FSUB:
2645                         x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
2646                         break;
2647                 case OP_FMUL:
2648                         x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
2649                         break;
2650                 case OP_FDIV:
2651                         x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
2652                         break;
2653                 case OP_FNEG:
2654                         x86_fchs (code);
2655                         break;
2656                 case OP_SIN:
2657                         x86_fsin (code);
2658                         break;
2659                 case OP_COS:
2660                         x86_fcos (code);
2661                         break;
2662                 case OP_ABS:
2663                         x86_fabs (code);
2664                         break;
2665                 case OP_TAN: {
2666                         /*
2667                          * it really doesn't make sense to inline all this code,
2668                          * it's here just to show that things may not be as simple
2669                          * as they appear.
2670                          */
2671                         guchar *check_pos, *end_tan, *pop_jump;
2672                         x86_push_reg (code, X86_EAX);
2673                         x86_fptan (code);
2674                         x86_fnstsw (code);
2675                         x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
2676                         check_pos = code;
2677                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
2678                         x86_fstp (code, 0); /* pop the 1.0 */
2679                         end_tan = code;
2680                         x86_jump8 (code, 0);
2681                         x86_fldpi (code);
2682                         x86_fp_op (code, X86_FADD, 0);
2683                         x86_fxch (code, 1);
2684                         x86_fprem1 (code);
2685                         x86_fstsw (code);
2686                         x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
2687                         pop_jump = code;
2688                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
2689                         x86_fstp (code, 1);
2690                         x86_fptan (code);
2691                         x86_patch (pop_jump, code);
2692                         x86_fstp (code, 0); /* pop the 1.0 */
2693                         x86_patch (check_pos, code);
2694                         x86_patch (end_tan, code);
2695                         x86_pop_reg (code, X86_EAX);
2696                         break;
2697                 }
2698                 case OP_ATAN:
2699                         x86_fld1 (code);
2700                         x86_fpatan (code);
2701                         break;
2702                 case OP_SQRT:
2703                         x86_fsqrt (code);
2704                         break;
2705                 case OP_X86_FPOP:
2706                         x86_fstp (code, 0);
2707                         break;
2708                 case OP_FREM: {
2709                         guint8 *l1, *l2;
2710
2711                         x86_push_reg (code, X86_EAX);
2712                         /* we need to exchange ST(0) with ST(1) */
2713                         x86_fxch (code, 1);
2714
2715                         /* this requires a loop, because fprem somtimes
2716                          * returns a partial remainder */
2717                         l1 = code;
2718                         /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
2719                         /* x86_fprem1 (code); */
2720                         x86_fprem (code);
2721                         x86_fnstsw (code);
2722                         x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
2723                         l2 = code + 2;
2724                         x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
2725
2726                         /* pop result */
2727                         x86_fstp (code, 1);
2728
2729                         x86_pop_reg (code, X86_EAX);
2730                         break;
2731                 }
2732                 case OP_FCOMPARE:
2733                         if (cfg->opt & MONO_OPT_FCMOV) {
2734                                 x86_fcomip (code, 1);
2735                                 x86_fstp (code, 0);
2736                                 break;
2737                         }
2738                         /* this overwrites EAX */
2739                         EMIT_FPCOMPARE(code);
2740                         x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
2741                         break;
2742                 case OP_FCEQ:
2743                         if (cfg->opt & MONO_OPT_FCMOV) {
2744                                 /* zeroing the register at the start results in
2745                                  * shorter and faster code (we can also remove the widening op)
2746                                  */
2747                                 guchar *unordered_check;
2748                                 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2749                                 x86_fcomip (code, 1);
2750                                 x86_fstp (code, 0);
2751                                 unordered_check = code;
2752                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
2753                                 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
2754                                 x86_patch (unordered_check, code);
2755                                 break;
2756                         }
2757                         if (ins->dreg != X86_EAX)
2758                                 x86_push_reg (code, X86_EAX);
2759
2760                         EMIT_FPCOMPARE(code);
2761                         x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
2762                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
2763                         x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
2764                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2765
2766                         if (ins->dreg != X86_EAX)
2767                                 x86_pop_reg (code, X86_EAX);
2768                         break;
2769                 case OP_FCLT:
2770                 case OP_FCLT_UN:
2771                         if (cfg->opt & MONO_OPT_FCMOV) {
2772                                 /* zeroing the register at the start results in
2773                                  * shorter and faster code (we can also remove the widening op)
2774                                  */
2775                                 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2776                                 x86_fcomip (code, 1);
2777                                 x86_fstp (code, 0);
2778                                 if (ins->opcode == OP_FCLT_UN) {
2779                                         guchar *unordered_check = code;
2780                                         guchar *jump_to_end;
2781                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
2782                                         x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
2783                                         jump_to_end = code;
2784                                         x86_jump8 (code, 0);
2785                                         x86_patch (unordered_check, code);
2786                                         x86_inc_reg (code, ins->dreg);
2787                                         x86_patch (jump_to_end, code);
2788                                 } else {
2789                                         x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
2790                                 }
2791                                 break;
2792                         }
2793                         if (ins->dreg != X86_EAX)
2794                                 x86_push_reg (code, X86_EAX);
2795
2796                         EMIT_FPCOMPARE(code);
2797                         x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
2798                         if (ins->opcode == OP_FCLT_UN) {
2799                                 guchar *is_not_zero_check, *end_jump;
2800                                 is_not_zero_check = code;
2801                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
2802                                 end_jump = code;
2803                                 x86_jump8 (code, 0);
2804                                 x86_patch (is_not_zero_check, code);
2805                                 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
2806
2807                                 x86_patch (end_jump, code);
2808                         }
2809                         x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
2810                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2811
2812                         if (ins->dreg != X86_EAX)
2813                                 x86_pop_reg (code, X86_EAX);
2814                         break;
2815                 case OP_FCGT:
2816                 case OP_FCGT_UN:
2817                         if (cfg->opt & MONO_OPT_FCMOV) {
2818                                 /* zeroing the register at the start results in
2819                                  * shorter and faster code (we can also remove the widening op)
2820                                  */
2821                                 guchar *unordered_check;
2822                                 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2823                                 x86_fcomip (code, 1);
2824                                 x86_fstp (code, 0);
2825                                 if (ins->opcode == OP_FCGT) {
2826                                         unordered_check = code;
2827                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
2828                                         x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
2829                                         x86_patch (unordered_check, code);
2830                                 } else {
2831                                         x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
2832                                 }
2833                                 break;
2834                         }
2835                         if (ins->dreg != X86_EAX)
2836                                 x86_push_reg (code, X86_EAX);
2837
2838                         EMIT_FPCOMPARE(code);
2839                         x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
2840                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
2841                         if (ins->opcode == OP_FCGT_UN) {
2842                                 guchar *is_not_zero_check, *end_jump;
2843                                 is_not_zero_check = code;
2844                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
2845                                 end_jump = code;
2846                                 x86_jump8 (code, 0);
2847                                 x86_patch (is_not_zero_check, code);
2848                                 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
2849
2850                                 x86_patch (end_jump, code);
2851                         }
2852                         x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
2853                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2854
2855                         if (ins->dreg != X86_EAX)
2856                                 x86_pop_reg (code, X86_EAX);
2857                         break;
2858                 case OP_FBEQ:
2859                         if (cfg->opt & MONO_OPT_FCMOV) {
2860                                 guchar *jump = code;
2861                                 x86_branch8 (code, X86_CC_P, 0, TRUE);
2862                                 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
2863                                 x86_patch (jump, code);
2864                                 break;
2865                         }
2866                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
2867                         EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
2868                         break;
2869                 case OP_FBNE_UN:
2870                         /* Branch if C013 != 100 */
2871                         if (cfg->opt & MONO_OPT_FCMOV) {
2872                                 /* branch if !ZF or (PF|CF) */
2873                                 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
2874                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
2875                                 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
2876                                 break;
2877                         }
2878                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
2879                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
2880                         break;
2881                 case OP_FBLT:
2882                         if (cfg->opt & MONO_OPT_FCMOV) {
2883                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
2884                                 break;
2885                         }
2886                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
2887                         break;
2888                 case OP_FBLT_UN:
2889                         if (cfg->opt & MONO_OPT_FCMOV) {
2890                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
2891                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
2892                                 break;
2893                         }
2894                         if (ins->opcode == OP_FBLT_UN) {
2895                                 guchar *is_not_zero_check, *end_jump;
2896                                 is_not_zero_check = code;
2897                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
2898                                 end_jump = code;
2899                                 x86_jump8 (code, 0);
2900                                 x86_patch (is_not_zero_check, code);
2901                                 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
2902
2903                                 x86_patch (end_jump, code);
2904                         }
2905                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
2906                         break;
2907                 case OP_FBGT:
2908                 case OP_FBGT_UN:
2909                         if (cfg->opt & MONO_OPT_FCMOV) {
2910                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
2911                                 break;
2912                         }
2913                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
2914                         if (ins->opcode == OP_FBGT_UN) {
2915                                 guchar *is_not_zero_check, *end_jump;
2916                                 is_not_zero_check = code;
2917                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
2918                                 end_jump = code;
2919                                 x86_jump8 (code, 0);
2920                                 x86_patch (is_not_zero_check, code);
2921                                 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
2922
2923                                 x86_patch (end_jump, code);
2924                         }
2925                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
2926                         break;
2927                 case OP_FBGE:
2928                         /* Branch if C013 == 100 or 001 */
2929                         if (cfg->opt & MONO_OPT_FCMOV) {
2930                                 guchar *br1;
2931
2932                                 /* skip branch if C1=1 */
2933                                 br1 = code;
2934                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
2935                                 /* branch if (C0 | C3) = 1 */
2936                                 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
2937                                 x86_patch (br1, code);
2938                                 break;
2939                         }
2940                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
2941                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
2942                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
2943                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
2944                         break;
2945                 case OP_FBGE_UN:
2946                         /* Branch if C013 == 000 */
2947                         if (cfg->opt & MONO_OPT_FCMOV) {
2948                                 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
2949                                 break;
2950                         }
2951                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
2952                         break;
2953                 case OP_FBLE:
2954                         /* Branch if C013=000 or 100 */
2955                         if (cfg->opt & MONO_OPT_FCMOV) {
2956                                 guchar *br1;
2957
2958                                 /* skip branch if C1=1 */
2959                                 br1 = code;
2960                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
2961                                 /* branch if C0=0 */
2962                                 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
2963                                 x86_patch (br1, code);
2964                                 break;
2965                         }
2966                         x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
2967                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
2968                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
2969                         break;
2970                 case OP_FBLE_UN:
2971                         /* Branch if C013 != 001 */
2972                         if (cfg->opt & MONO_OPT_FCMOV) {
2973                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
2974                                 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
2975                                 break;
2976                         }
2977                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
2978                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
2979                         break;
2980                 case CEE_CKFINITE: {
2981                         x86_push_reg (code, X86_EAX);
2982                         x86_fxam (code);
2983                         x86_fnstsw (code);
2984                         x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
2985                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
2986                         x86_pop_reg (code, X86_EAX);
2987                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
2988                         break;
2989                 }
2990                 default:
2991                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
2992                         g_assert_not_reached ();
2993                 }
2994
2995                 if ((code - cfg->native_code - offset) > max_len) {
2996                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
2997                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
2998                         g_assert_not_reached ();
2999                 }
3000
3001                 cpos += max_len;
3002
3003                 last_ins = ins;
3004                 last_offset = offset;
3005
3006                 ins = ins->next;
3007         }
3008
3009         cfg->code_len = code - cfg->native_code;
3010 }
3011
3012 void
3013 mono_arch_register_lowlevel_calls (void)
3014 {
3015         mono_register_jit_icall (mono_arch_get_lmf_addr, "mono_arch_get_lmf_addr", NULL, TRUE);
3016 }
3017
3018 void
3019 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3020 {
3021         MonoJumpInfo *patch_info;
3022
3023         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3024                 unsigned char *ip = patch_info->ip.i + code;
3025                 const unsigned char *target;
3026
3027                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3028
3029                 switch (patch_info->type) {
3030                 case MONO_PATCH_INFO_IP:
3031                         *((gpointer *)(ip)) = target;
3032                         continue;
3033                 case MONO_PATCH_INFO_METHOD_REL:
3034                         *((gpointer *)(ip)) = target;
3035                         continue;
3036                 case MONO_PATCH_INFO_SWITCH: {
3037                         *((gconstpointer *)(ip + 2)) = target;
3038                         /* we put into the table the absolute address, no need for x86_patch in this case */
3039                         continue;
3040                 }
3041                 case MONO_PATCH_INFO_IID:
3042                         *((guint32 *)(ip + 1)) = target;
3043                         continue;
3044                 case MONO_PATCH_INFO_CLASS_INIT: {
3045                         guint8 *code = ip;
3046                         /* Might already been changed to a nop */
3047                         x86_call_imm (code, 0);
3048                         break;
3049                 }
3050                 case MONO_PATCH_INFO_R4:
3051                 case MONO_PATCH_INFO_R8:
3052                         *((gconstpointer *)(ip + 2)) = target;
3053                         continue;
3054                 case MONO_PATCH_INFO_METHODCONST:
3055                 case MONO_PATCH_INFO_CLASS:
3056                 case MONO_PATCH_INFO_IMAGE:
3057                 case MONO_PATCH_INFO_FIELD:
3058                 case MONO_PATCH_INFO_VTABLE:
3059                 case MONO_PATCH_INFO_SFLDA:
3060                 case MONO_PATCH_INFO_EXC_NAME:
3061                 case MONO_PATCH_INFO_LDSTR:
3062                 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
3063                 case MONO_PATCH_INFO_LDTOKEN:
3064                         *((gconstpointer *)(ip + 1)) = target;
3065                         continue;
3066                 default:
3067                         break;
3068                 }
3069                 x86_patch (ip, target);
3070         }
3071 }
3072
3073 int
3074 mono_arch_max_epilog_size (MonoCompile *cfg)
3075 {
3076         int exc_count = 0, max_epilog_size = 16;
3077         MonoJumpInfo *patch_info;
3078
3079         if (cfg->method->save_lmf)
3080                 max_epilog_size += 128;
3081
3082         if (mono_jit_trace_calls != NULL)
3083                 max_epilog_size += 50;
3084
3085         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3086                 max_epilog_size += 50;
3087
3088         /* count the number of exception infos */
3089
3090         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
3091                 if (patch_info->type == MONO_PATCH_INFO_EXC)
3092                         exc_count++;
3093         }
3094
3095         /*
3096          * make sure we have enough space for exceptions
3097          * 16 is the size of two push_imm instructions and a call
3098          */
3099         max_epilog_size += exc_count*16;
3100
3101         return max_epilog_size;
3102 }
3103
3104 guint8 *
3105 mono_arch_emit_prolog (MonoCompile *cfg)
3106 {
3107         MonoMethod *method = cfg->method;
3108         MonoBasicBlock *bb;
3109         MonoMethodSignature *sig;
3110         MonoInst *inst;
3111         int alloc_size, pos, max_offset, i;
3112         guint8 *code;
3113
3114         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 256);
3115         code = cfg->native_code = g_malloc (cfg->code_size);
3116
3117         x86_push_reg (code, X86_EBP);
3118         x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
3119
3120         alloc_size = - cfg->stack_offset;
3121         pos = 0;
3122
3123         if (method->save_lmf) {
3124                 pos += sizeof (MonoLMF);
3125
3126                 /* save the current IP */
3127                 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
3128                 x86_push_imm (code, 0);
3129
3130                 /* save all caller saved regs */
3131                 x86_push_reg (code, X86_EBX);
3132                 x86_push_reg (code, X86_EDI);
3133                 x86_push_reg (code, X86_ESI);
3134                 x86_push_reg (code, X86_EBP);
3135
3136                 /* save method info */
3137                 x86_push_imm (code, method);
3138
3139                 /* get the address of lmf for the current thread */
3140                 /*
3141                  * This is performance critical so we try to use some tricks to make
3142                  * it fast.
3143                  */
3144                 if (lmf_tls_offset != -1) {
3145                         /* Load lmf quicky using the GS register */
3146                         x86_prefix (code, X86_GS_PREFIX);
3147                         x86_mov_reg_mem (code, X86_EAX, 0, 4);
3148                         x86_mov_reg_membase (code, X86_EAX, X86_EAX, lmf_tls_offset, 4);
3149                 }
3150                 else {
3151 #ifdef HAVE_KW_THREAD
3152                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3153                                                                  (gpointer)"mono_arch_get_lmf_addr");
3154 #else
3155                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3156                                                                  (gpointer)"mono_get_lmf_addr");
3157 #endif
3158                         x86_call_code (code, 0);
3159                 }
3160
3161                 /* push lmf */
3162                 x86_push_reg (code, X86_EAX);
3163                 /* push *lfm (previous_lmf) */
3164                 x86_push_membase (code, X86_EAX, 0);
3165                 /* *(lmf) = ESP */
3166                 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
3167         } else {
3168
3169                 if (cfg->used_int_regs & (1 << X86_EBX)) {
3170                         x86_push_reg (code, X86_EBX);
3171                         pos += 4;
3172                 }
3173
3174                 if (cfg->used_int_regs & (1 << X86_EDI)) {
3175                         x86_push_reg (code, X86_EDI);
3176                         pos += 4;
3177                 }
3178
3179                 if (cfg->used_int_regs & (1 << X86_ESI)) {
3180                         x86_push_reg (code, X86_ESI);
3181                         pos += 4;
3182                 }
3183         }
3184
3185         alloc_size -= pos;
3186
3187         if (alloc_size) {
3188                 /* See mono_emit_stack_alloc */
3189 #ifdef PLATFORM_WIN32
3190                 guint32 remaining_size = alloc_size;
3191                 while (remaining_size >= 0x1000) {
3192                         x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
3193                         x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
3194                         remaining_size -= 0x1000;
3195                 }
3196                 if (remaining_size)
3197                         x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
3198 #else
3199                 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
3200 #endif
3201         }
3202
3203         /* compute max_offset in order to use short forward jumps */
3204         max_offset = 0;
3205         if (cfg->opt & MONO_OPT_BRANCH) {
3206                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
3207                         MonoInst *ins = bb->code;
3208                         bb->max_offset = max_offset;
3209
3210                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
3211                                 max_offset += 6;
3212
3213                         while (ins) {
3214                                 max_offset += ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
3215                                 ins = ins->next;
3216                         }
3217                 }
3218         }
3219
3220         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3221                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
3222
3223         /* load arguments allocated to register from the stack */
3224         sig = method->signature;
3225         pos = 0;
3226
3227         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3228                 inst = cfg->varinfo [pos];
3229                 if (inst->opcode == OP_REGVAR) {
3230                         x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
3231                         if (cfg->verbose_level > 2)
3232                                 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
3233                 }
3234                 pos++;
3235         }
3236
3237         cfg->code_len = code - cfg->native_code;
3238
3239         return code;
3240 }
3241
3242 void
3243 mono_arch_emit_epilog (MonoCompile *cfg)
3244 {
3245         MonoJumpInfo *patch_info;
3246         MonoMethod *method = cfg->method;
3247         MonoMethodSignature *sig = method->signature;
3248         int pos;
3249         guint32 stack_to_pop;
3250         guint8 *code;
3251
3252         code = cfg->native_code + cfg->code_len;
3253
3254         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3255                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
3256
3257         /* the code restoring the registers must be kept in sync with CEE_JMP */
3258         pos = 0;
3259
3260         if (method->save_lmf) {
3261                 pos = -sizeof (MonoLMF);
3262         } else {
3263                 if (cfg->used_int_regs & (1 << X86_EBX)) {
3264                         pos -= 4;
3265                 }
3266                 if (cfg->used_int_regs & (1 << X86_EDI)) {
3267                         pos -= 4;
3268                 }
3269                 if (cfg->used_int_regs & (1 << X86_ESI)) {
3270                         pos -= 4;
3271                 }
3272         }
3273
3274         if (pos)
3275                 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
3276
3277         if (method->save_lmf) {
3278                 /* ebx = previous_lmf */
3279                 x86_pop_reg (code, X86_EBX);
3280                 /* edi = lmf */
3281                 x86_pop_reg (code, X86_EDI);
3282                 /* *(lmf) = previous_lmf */
3283                 x86_mov_membase_reg (code, X86_EDI, 0, X86_EBX, 4);
3284
3285                 /* discard method info */
3286                 x86_pop_reg (code, X86_ESI);
3287
3288                 /* restore caller saved regs */
3289                 x86_pop_reg (code, X86_EBP);
3290                 x86_pop_reg (code, X86_ESI);
3291                 x86_pop_reg (code, X86_EDI);
3292                 x86_pop_reg (code, X86_EBX);
3293
3294         } else {
3295
3296                 if (cfg->used_int_regs & (1 << X86_ESI)) {
3297                         x86_pop_reg (code, X86_ESI);
3298                 }
3299                 if (cfg->used_int_regs & (1 << X86_EDI)) {
3300                         x86_pop_reg (code, X86_EDI);
3301                 }
3302                 if (cfg->used_int_regs & (1 << X86_EBX)) {
3303                         x86_pop_reg (code, X86_EBX);
3304                 }
3305         }
3306
3307         x86_leave (code);
3308
3309         if (CALLCONV_IS_STDCALL (sig->call_convention)) {
3310           MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
3311
3312           stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
3313         }
3314         else
3315         if (MONO_TYPE_ISSTRUCT (cfg->method->signature->ret))
3316           stack_to_pop = 4;
3317         else
3318           stack_to_pop = 0;
3319
3320         if (stack_to_pop)
3321                 x86_ret_imm (code, stack_to_pop);
3322         else
3323                 x86_ret (code);
3324
3325         /* add code to raise exceptions */
3326         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
3327                 switch (patch_info->type) {
3328                 case MONO_PATCH_INFO_EXC:
3329                         x86_patch (patch_info->ip.i + cfg->native_code, code);
3330                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC_NAME, patch_info->data.target);
3331                         x86_push_imm (code, patch_info->data.target);
3332                         mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_METHOD_REL, (gpointer)patch_info->ip.i);
3333                         x86_push_imm (code, patch_info->ip.i + cfg->native_code);
3334                         patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
3335                         patch_info->data.name = "mono_arch_throw_exception_by_name";
3336                         patch_info->ip.i = code - cfg->native_code;
3337                         x86_jump_code (code, 0);
3338                         break;
3339                 default:
3340                         /* do nothing */
3341                         break;
3342                 }
3343         }
3344
3345         cfg->code_len = code - cfg->native_code;
3346
3347         g_assert (cfg->code_len < cfg->code_size);
3348
3349 }
3350
3351 void
3352 mono_arch_flush_icache (guint8 *code, gint size)
3353 {
3354         /* not needed */
3355 }
3356
3357 /*
3358  * Support for fast access to the thread-local lmf structure using the GS
3359  * segment register on NPTL + kernel 2.6.x.
3360  */
3361
3362 static gboolean tls_offset_inited = FALSE;
3363
3364 #ifdef HAVE_KW_THREAD
3365 static __thread gpointer mono_lmf_addr;
3366 #endif
3367
3368 static gpointer
3369 mono_arch_get_lmf_addr (void)
3370 {
3371 #ifdef HAVE_KW_THREAD
3372         return mono_lmf_addr;
3373 #else
3374         g_assert_not_reached ();
3375         return NULL;
3376 #endif
3377 }
3378
3379 void
3380 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
3381 {
3382 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3383         pthread_t self = pthread_self();
3384         pthread_attr_t attr;
3385         void *staddr = NULL;
3386         size_t stsize = 0;
3387         struct sigaltstack sa;
3388 #endif
3389
3390         if (!tls_offset_inited) {
3391                 guint8 *code;
3392
3393                 tls_offset_inited = TRUE;
3394
3395                 if (getenv ("MONO_NPTL")) {
3396                         /*
3397                          * Determine the offset of mono_lfm_addr inside the TLS structures
3398                          * by disassembling the function above.
3399                          */
3400                         code = (guint8*)&mono_arch_get_lmf_addr;
3401
3402                         /* This is generated by gcc 3.3.2 */
3403                         if ((code [0] == 0x55) && (code [1] == 0x89) && (code [2] == 0xe5) &&
3404                                 (code [3] == 0x65) && (code [4] == 0xa1) && (code [5] == 0x00) &&
3405                                 (code [6] == 0x00) && (code [7] == 0x00) && (code [8] == 0x00) &&
3406                                 (code [9] == 0x8b) && (code [10] == 0x80)) {
3407                                 lmf_tls_offset = *(int*)&(code [11]);
3408                         }
3409                 }
3410         }
3411
3412 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3413
3414         /* Determine stack boundaries */
3415         if (!mono_running_on_valgrind ()) {
3416                 pthread_getattr_np( self, &attr );
3417                 pthread_attr_getstack( &attr, &staddr, &stsize );
3418         }
3419
3420         /*
3421          * staddr seems to be wrong for the main thread, so we keep the value in
3422          * tls->end_of_stack
3423          */
3424         tls->stack_size = stsize;
3425
3426         /* Setup an alternate signal stack */
3427         tls->signal_stack = g_malloc (SIGNAL_STACK_SIZE);
3428         tls->signal_stack_size = SIGNAL_STACK_SIZE;
3429
3430         sa.ss_sp = tls->signal_stack;
3431         sa.ss_size = SIGNAL_STACK_SIZE;
3432         sa.ss_flags = SS_ONSTACK;
3433         sigaltstack (&sa, NULL);
3434 #endif
3435
3436 #ifdef HAVE_KW_THREAD
3437         mono_lmf_addr = &tls->lmf;
3438 #endif
3439 }
3440
3441 void
3442 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
3443 {
3444 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3445         struct sigaltstack sa;
3446
3447         sa.ss_sp = tls->signal_stack;
3448         sa.ss_size = SIGNAL_STACK_SIZE;
3449         sa.ss_flags = SS_DISABLE;
3450         sigaltstack  (&sa, NULL);
3451
3452         if (tls->signal_stack)
3453                 g_free (tls->signal_stack);
3454 #endif
3455 }
3456
3457 void
3458 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
3459 {
3460
3461         /* add the this argument */
3462         if (this_reg != -1) {
3463                 MonoInst *this;
3464                 MONO_INST_NEW (cfg, this, OP_OUTARG);
3465                 this->type = this_type;
3466                 this->sreg1 = this_reg;
3467                 mono_bblock_add_inst (cfg->cbb, this);
3468         }
3469
3470         if (vt_reg != -1) {
3471                 MonoInst *vtarg;
3472                 MONO_INST_NEW (cfg, vtarg, OP_OUTARG);
3473                 vtarg->type = STACK_MP;
3474                 vtarg->sreg1 = vt_reg;
3475                 mono_bblock_add_inst (cfg->cbb, vtarg);
3476         }
3477 }
3478
3479
3480 gint
3481 mono_arch_get_opcode_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
3482 {
3483         if (cmethod->klass == mono_defaults.math_class) {
3484                 if (strcmp (cmethod->name, "Sin") == 0)
3485                         return OP_SIN;
3486                 else if (strcmp (cmethod->name, "Cos") == 0)
3487                         return OP_COS;
3488                 else if (strcmp (cmethod->name, "Tan") == 0)
3489                         return OP_TAN;
3490                 else if (strcmp (cmethod->name, "Atan") == 0)
3491                         return OP_ATAN;
3492                 else if (strcmp (cmethod->name, "Sqrt") == 0)
3493                         return OP_SQRT;
3494                 else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8)
3495                         return OP_ABS;
3496 #if 0
3497                 /* OP_FREM is not IEEE compatible */
3498                 else if (strcmp (cmethod->name, "IEEERemainder") == 0)
3499                         return OP_FREM;
3500 #endif
3501                 else
3502                         return -1;
3503         } else {
3504                 return -1;
3505         }
3506         return -1;
3507 }
3508
3509