2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/abi-details.h>
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/metadata/gc-internals.h>
27 #include <mono/utils/mono-math.h>
28 #include <mono/utils/mono-counters.h>
29 #include <mono/utils/mono-mmap.h>
30 #include <mono/utils/mono-memory-model.h>
31 #include <mono/utils/mono-hwcap-x86.h>
32 #include <mono/utils/mono-threads.h>
42 static gboolean optimize_for_xen = TRUE;
44 #define optimize_for_xen 0
48 /* The single step trampoline */
49 static gpointer ss_trampoline;
51 /* The breakpoint trampoline */
52 static gpointer bp_trampoline;
54 /* This mutex protects architecture specific caches */
55 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
56 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
57 static mono_mutex_t mini_arch_mutex;
59 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
64 /* Under windows, the default pinvoke calling convention is stdcall */
65 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
67 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
70 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
72 #define OP_SEQ_POINT_BP_OFFSET 7
75 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
77 #ifdef __native_client_codegen__
79 /* Default alignment for Native Client is 32-byte. */
80 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
82 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
83 /* Check that alignment doesn't cross an alignment boundary. */
85 mono_arch_nacl_pad (guint8 *code, int pad)
87 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
89 if (pad == 0) return code;
90 /* assertion: alignment cannot cross a block boundary */
91 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
92 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
93 while (pad >= kMaxPadding) {
94 x86_padding (code, kMaxPadding);
97 if (pad != 0) x86_padding (code, pad);
102 mono_arch_nacl_skip_nops (guint8 *code)
104 x86_skip_nops (code);
108 #endif /* __native_client_codegen__ */
111 mono_arch_regname (int reg)
114 case X86_EAX: return "%eax";
115 case X86_EBX: return "%ebx";
116 case X86_ECX: return "%ecx";
117 case X86_EDX: return "%edx";
118 case X86_ESP: return "%esp";
119 case X86_EBP: return "%ebp";
120 case X86_EDI: return "%edi";
121 case X86_ESI: return "%esi";
127 mono_arch_fregname (int reg)
152 mono_arch_xregname (int reg)
177 mono_x86_patch (unsigned char* code, gpointer target)
179 x86_patch (code, (unsigned char*)target);
190 /* gsharedvt argument passed by addr */
202 /* Only if storage == ArgValuetypeInReg */
203 ArgStorage pair_storage [2];
212 gboolean need_stack_align;
213 guint32 stack_align_amount;
214 gboolean vtype_retaddr;
215 /* The index of the vret arg in the argument list */
218 /* Argument space popped by the callee */
219 int callee_stack_pop;
225 #define FLOAT_PARAM_REGS 0
227 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
229 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
234 switch (sig->call_convention) {
235 case MONO_CALL_THISCALL:
236 return thiscall_param_regs;
242 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
243 #define SMALL_STRUCTS_IN_REGS
244 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
248 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
250 ainfo->offset = *stack_size;
252 if (!param_regs || param_regs [*gr] == X86_NREG) {
253 ainfo->storage = ArgOnStack;
255 (*stack_size) += sizeof (gpointer);
258 ainfo->storage = ArgInIReg;
259 ainfo->reg = param_regs [*gr];
265 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
267 ainfo->offset = *stack_size;
269 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
271 ainfo->storage = ArgOnStack;
272 (*stack_size) += sizeof (gpointer) * 2;
277 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
279 ainfo->offset = *stack_size;
281 if (*gr >= FLOAT_PARAM_REGS) {
282 ainfo->storage = ArgOnStack;
283 (*stack_size) += is_double ? 8 : 4;
284 ainfo->nslots = is_double ? 2 : 1;
287 /* A double register */
289 ainfo->storage = ArgInDoubleSSEReg;
291 ainfo->storage = ArgInFloatSSEReg;
299 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
301 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
306 klass = mono_class_from_mono_type (type);
307 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
309 #ifdef SMALL_STRUCTS_IN_REGS
310 if (sig->pinvoke && is_return) {
311 MonoMarshalType *info;
314 * the exact rules are not very well documented, the code below seems to work with the
315 * code generated by gcc 3.3.3 -mno-cygwin.
317 info = mono_marshal_load_type_info (klass);
320 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
322 /* Special case structs with only a float member */
323 if (info->num_fields == 1) {
324 int ftype = mini_get_underlying_type (info->fields [0].field->type)->type;
325 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
326 ainfo->storage = ArgValuetypeInReg;
327 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
330 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
331 ainfo->storage = ArgValuetypeInReg;
332 ainfo->pair_storage [0] = ArgOnFloatFpStack;
336 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
337 ainfo->storage = ArgValuetypeInReg;
338 ainfo->pair_storage [0] = ArgInIReg;
339 ainfo->pair_regs [0] = return_regs [0];
340 if (info->native_size > 4) {
341 ainfo->pair_storage [1] = ArgInIReg;
342 ainfo->pair_regs [1] = return_regs [1];
349 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
350 g_assert (size <= 4);
351 ainfo->storage = ArgValuetypeInReg;
352 ainfo->reg = param_regs [*gr];
357 ainfo->offset = *stack_size;
358 ainfo->storage = ArgOnStack;
359 *stack_size += ALIGN_TO (size, sizeof (gpointer));
360 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
366 * Obtain information about a call according to the calling convention.
367 * For x86 ELF, see the "System V Application Binary Interface Intel386
368 * Architecture Processor Supplment, Fourth Edition" document for more
370 * For x86 win32, see ???.
373 get_call_info_internal (CallInfo *cinfo, MonoMethodSignature *sig)
375 guint32 i, gr, fr, pstart;
376 const guint32 *param_regs;
378 int n = sig->hasthis + sig->param_count;
379 guint32 stack_size = 0;
380 gboolean is_pinvoke = sig->pinvoke;
386 param_regs = callconv_param_regs(sig);
390 ret_type = mini_get_underlying_type (sig->ret);
391 switch (ret_type->type) {
401 case MONO_TYPE_FNPTR:
402 case MONO_TYPE_CLASS:
403 case MONO_TYPE_OBJECT:
404 case MONO_TYPE_SZARRAY:
405 case MONO_TYPE_ARRAY:
406 case MONO_TYPE_STRING:
407 cinfo->ret.storage = ArgInIReg;
408 cinfo->ret.reg = X86_EAX;
412 cinfo->ret.storage = ArgInIReg;
413 cinfo->ret.reg = X86_EAX;
414 cinfo->ret.is_pair = TRUE;
417 cinfo->ret.storage = ArgOnFloatFpStack;
420 cinfo->ret.storage = ArgOnDoubleFpStack;
422 case MONO_TYPE_GENERICINST:
423 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
424 cinfo->ret.storage = ArgInIReg;
425 cinfo->ret.reg = X86_EAX;
428 if (mini_is_gsharedvt_type (ret_type)) {
429 cinfo->ret.storage = ArgOnStack;
430 cinfo->vtype_retaddr = TRUE;
434 case MONO_TYPE_VALUETYPE:
435 case MONO_TYPE_TYPEDBYREF: {
436 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
438 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
439 if (cinfo->ret.storage == ArgOnStack) {
440 cinfo->vtype_retaddr = TRUE;
441 /* The caller passes the address where the value is stored */
447 g_assert (mini_is_gsharedvt_type (ret_type));
448 cinfo->ret.storage = ArgOnStack;
449 cinfo->vtype_retaddr = TRUE;
452 cinfo->ret.storage = ArgNone;
455 g_error ("Can't handle as return value 0x%x", ret_type->type);
461 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
462 * the first argument, allowing 'this' to be always passed in the first arg reg.
463 * Also do this if the first argument is a reference type, since virtual calls
464 * are sometimes made using calli without sig->hasthis set, like in the delegate
467 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
469 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
471 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
474 cinfo->vret_arg_offset = stack_size;
475 add_general (&gr, NULL, &stack_size, &cinfo->ret);
476 cinfo->vret_arg_index = 1;
480 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
482 if (cinfo->vtype_retaddr)
483 add_general (&gr, NULL, &stack_size, &cinfo->ret);
486 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
487 fr = FLOAT_PARAM_REGS;
489 /* Emit the signature cookie just before the implicit arguments */
490 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
493 for (i = pstart; i < sig->param_count; ++i) {
494 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
497 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
498 /* We allways pass the sig cookie on the stack for simplicity */
500 * Prevent implicit arguments + the sig cookie from being passed
503 fr = FLOAT_PARAM_REGS;
505 /* Emit the signature cookie just before the implicit arguments */
506 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
509 if (sig->params [i]->byref) {
510 add_general (&gr, param_regs, &stack_size, ainfo);
513 ptype = mini_get_underlying_type (sig->params [i]);
514 switch (ptype->type) {
517 add_general (&gr, param_regs, &stack_size, ainfo);
521 add_general (&gr, param_regs, &stack_size, ainfo);
525 add_general (&gr, param_regs, &stack_size, ainfo);
530 case MONO_TYPE_FNPTR:
531 case MONO_TYPE_CLASS:
532 case MONO_TYPE_OBJECT:
533 case MONO_TYPE_STRING:
534 case MONO_TYPE_SZARRAY:
535 case MONO_TYPE_ARRAY:
536 add_general (&gr, param_regs, &stack_size, ainfo);
538 case MONO_TYPE_GENERICINST:
539 if (!mono_type_generic_inst_is_valuetype (ptype)) {
540 add_general (&gr, param_regs, &stack_size, ainfo);
543 if (mini_is_gsharedvt_type (ptype)) {
544 /* gsharedvt arguments are passed by ref */
545 add_general (&gr, param_regs, &stack_size, ainfo);
546 g_assert (ainfo->storage == ArgOnStack);
547 ainfo->storage = ArgGSharedVt;
551 case MONO_TYPE_VALUETYPE:
552 case MONO_TYPE_TYPEDBYREF:
553 add_valuetype (sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
557 add_general_pair (&gr, param_regs, &stack_size, ainfo);
560 add_float (&fr, &stack_size, ainfo, FALSE);
563 add_float (&fr, &stack_size, ainfo, TRUE);
567 /* gsharedvt arguments are passed by ref */
568 g_assert (mini_is_gsharedvt_type (ptype));
569 add_general (&gr, param_regs, &stack_size, ainfo);
570 g_assert (ainfo->storage == ArgOnStack);
571 ainfo->storage = ArgGSharedVt;
574 g_error ("unexpected type 0x%x", ptype->type);
575 g_assert_not_reached ();
579 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
580 fr = FLOAT_PARAM_REGS;
582 /* Emit the signature cookie just before the implicit arguments */
583 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
586 if (cinfo->vtype_retaddr) {
587 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
588 cinfo->callee_stack_pop = 4;
589 } else if (CALLCONV_IS_STDCALL (sig) && sig->pinvoke) {
590 /* Have to compensate for the stack space popped by the native callee */
591 cinfo->callee_stack_pop = stack_size;
594 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
595 cinfo->need_stack_align = TRUE;
596 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
597 stack_size += cinfo->stack_align_amount;
600 cinfo->stack_usage = stack_size;
601 cinfo->reg_usage = gr;
602 cinfo->freg_usage = fr;
607 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
609 int n = sig->hasthis + sig->param_count;
613 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
615 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
617 return get_call_info_internal (cinfo, sig);
621 * mono_arch_get_argument_info:
622 * @csig: a method signature
623 * @param_count: the number of parameters to consider
624 * @arg_info: an array to store the result infos
626 * Gathers information on parameters such as size, alignment and
627 * padding. arg_info should be large enought to hold param_count + 1 entries.
629 * Returns the size of the argument area on the stack.
630 * This should be signal safe, since it is called from
631 * mono_arch_unwind_frame ().
632 * FIXME: The metadata calls might not be signal safe.
635 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
637 int len, k, args_size = 0;
643 /* Avoid g_malloc as it is not signal safe */
644 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
645 cinfo = (CallInfo*)g_newa (guint8*, len);
646 memset (cinfo, 0, len);
648 cinfo = get_call_info_internal (cinfo, csig);
650 arg_info [0].offset = offset;
652 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
653 args_size += sizeof (gpointer);
658 args_size += sizeof (gpointer);
662 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
663 /* Emitted after this */
664 args_size += sizeof (gpointer);
668 arg_info [0].size = args_size;
670 for (k = 0; k < param_count; k++) {
671 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
673 /* ignore alignment for now */
676 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
677 arg_info [k].pad = pad;
679 arg_info [k + 1].pad = 0;
680 arg_info [k + 1].size = size;
682 arg_info [k + 1].offset = offset;
685 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
686 /* Emitted after the first arg */
687 args_size += sizeof (gpointer);
692 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
693 align = MONO_ARCH_FRAME_ALIGNMENT;
696 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
697 arg_info [k].pad = pad;
703 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
705 MonoType *callee_ret;
709 if (cfg->compile_aot && !cfg->full_aot)
710 /* OP_TAILCALL doesn't work with AOT */
713 c1 = get_call_info (NULL, caller_sig);
714 c2 = get_call_info (NULL, callee_sig);
716 * Tail calls with more callee stack usage than the caller cannot be supported, since
717 * the extra stack space would be left on the stack after the tail call.
719 res = c1->stack_usage >= c2->stack_usage;
720 callee_ret = mini_get_underlying_type (callee_sig->ret);
721 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
722 /* An address on the callee's stack is passed as the first argument */
732 * Initialize the cpu to execute managed code.
735 mono_arch_cpu_init (void)
737 /* spec compliance requires running with double precision */
741 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
742 fpcw &= ~X86_FPCW_PRECC_MASK;
743 fpcw |= X86_FPCW_PREC_DOUBLE;
744 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
745 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
747 _control87 (_PC_53, MCW_PC);
752 * Initialize architecture specific code.
755 mono_arch_init (void)
757 mono_os_mutex_init_recursive (&mini_arch_mutex);
760 bp_trampoline = mini_get_breakpoint_trampoline ();
762 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
763 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
764 #if defined(ENABLE_GSHAREDVT)
765 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
770 * Cleanup architecture specific code.
773 mono_arch_cleanup (void)
775 mono_os_mutex_destroy (&mini_arch_mutex);
779 * This function returns the optimizations supported on this cpu.
782 mono_arch_cpu_optimizations (guint32 *exclude_mask)
784 #if !defined(__native_client__)
789 if (mono_hwcap_x86_has_cmov) {
790 opts |= MONO_OPT_CMOV;
792 if (mono_hwcap_x86_has_fcmov)
793 opts |= MONO_OPT_FCMOV;
795 *exclude_mask |= MONO_OPT_FCMOV;
797 *exclude_mask |= MONO_OPT_CMOV;
800 if (mono_hwcap_x86_has_sse2)
801 opts |= MONO_OPT_SSE2;
803 *exclude_mask |= MONO_OPT_SSE2;
805 #ifdef MONO_ARCH_SIMD_INTRINSICS
806 /*SIMD intrinsics require at least SSE2.*/
807 if (!mono_hwcap_x86_has_sse2)
808 *exclude_mask |= MONO_OPT_SIMD;
813 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
818 * This function test for all SSE functions supported.
820 * Returns a bitmask corresponding to all supported versions.
824 mono_arch_cpu_enumerate_simd_versions (void)
826 guint32 sse_opts = 0;
828 if (mono_hwcap_x86_has_sse1)
829 sse_opts |= SIMD_VERSION_SSE1;
831 if (mono_hwcap_x86_has_sse2)
832 sse_opts |= SIMD_VERSION_SSE2;
834 if (mono_hwcap_x86_has_sse3)
835 sse_opts |= SIMD_VERSION_SSE3;
837 if (mono_hwcap_x86_has_ssse3)
838 sse_opts |= SIMD_VERSION_SSSE3;
840 if (mono_hwcap_x86_has_sse41)
841 sse_opts |= SIMD_VERSION_SSE41;
843 if (mono_hwcap_x86_has_sse42)
844 sse_opts |= SIMD_VERSION_SSE42;
846 if (mono_hwcap_x86_has_sse4a)
847 sse_opts |= SIMD_VERSION_SSE4a;
853 * Determine whenever the trap whose info is in SIGINFO is caused by
857 mono_arch_is_int_overflow (void *sigctx, void *info)
862 mono_sigctx_to_monoctx (sigctx, &ctx);
864 ip = (guint8*)ctx.eip;
866 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
870 switch (x86_modrm_rm (ip [1])) {
890 g_assert_not_reached ();
902 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
907 for (i = 0; i < cfg->num_varinfo; i++) {
908 MonoInst *ins = cfg->varinfo [i];
909 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
912 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
915 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
916 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
919 /* we dont allocate I1 to registers because there is no simply way to sign extend
920 * 8bit quantities in caller saved registers on x86 */
921 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
922 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
923 g_assert (i == vmv->idx);
924 vars = g_list_prepend (vars, vmv);
928 vars = mono_varlist_sort (cfg, vars, 0);
934 mono_arch_get_global_int_regs (MonoCompile *cfg)
938 /* we can use 3 registers for global allocation */
939 regs = g_list_prepend (regs, (gpointer)X86_EBX);
940 regs = g_list_prepend (regs, (gpointer)X86_ESI);
941 regs = g_list_prepend (regs, (gpointer)X86_EDI);
947 * mono_arch_regalloc_cost:
949 * Return the cost, in number of memory references, of the action of
950 * allocating the variable VMV into a register during global register
954 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
956 MonoInst *ins = cfg->varinfo [vmv->idx];
958 if (cfg->method->save_lmf)
959 /* The register is already saved */
960 return (ins->opcode == OP_ARG) ? 1 : 0;
962 /* push+pop+possible load if it is an argument */
963 return (ins->opcode == OP_ARG) ? 3 : 2;
967 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
969 static int inited = FALSE;
970 static int count = 0;
972 if (cfg->arch.need_stack_frame_inited) {
973 g_assert (cfg->arch.need_stack_frame == flag);
977 cfg->arch.need_stack_frame = flag;
978 cfg->arch.need_stack_frame_inited = TRUE;
984 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
989 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
993 needs_stack_frame (MonoCompile *cfg)
995 MonoMethodSignature *sig;
996 MonoMethodHeader *header;
997 gboolean result = FALSE;
999 #if defined(__APPLE__)
1000 /*OSX requires stack frame code to have the correct alignment. */
1004 if (cfg->arch.need_stack_frame_inited)
1005 return cfg->arch.need_stack_frame;
1007 header = cfg->header;
1008 sig = mono_method_signature (cfg->method);
1010 if (cfg->disable_omit_fp)
1012 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1014 else if (cfg->method->save_lmf)
1016 else if (cfg->stack_offset)
1018 else if (cfg->param_area)
1020 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1022 else if (header->num_clauses)
1024 else if (sig->param_count + sig->hasthis)
1026 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1028 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1029 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1032 set_needs_stack_frame (cfg, result);
1034 return cfg->arch.need_stack_frame;
1038 * Set var information according to the calling convention. X86 version.
1039 * The locals var stuff should most likely be split in another method.
1042 mono_arch_allocate_vars (MonoCompile *cfg)
1044 MonoMethodSignature *sig;
1045 MonoMethodHeader *header;
1047 guint32 locals_stack_size, locals_stack_align;
1052 header = cfg->header;
1053 sig = mono_method_signature (cfg->method);
1055 cinfo = get_call_info (cfg->mempool, sig);
1057 cfg->frame_reg = X86_EBP;
1060 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1061 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1062 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1065 /* Reserve space to save LMF and caller saved registers */
1067 if (cfg->method->save_lmf) {
1068 /* The LMF var is allocated normally */
1070 if (cfg->used_int_regs & (1 << X86_EBX)) {
1074 if (cfg->used_int_regs & (1 << X86_EDI)) {
1078 if (cfg->used_int_regs & (1 << X86_ESI)) {
1083 switch (cinfo->ret.storage) {
1084 case ArgValuetypeInReg:
1085 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1087 cfg->ret->opcode = OP_REGOFFSET;
1088 cfg->ret->inst_basereg = X86_EBP;
1089 cfg->ret->inst_offset = - offset;
1095 /* Allocate locals */
1096 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1097 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1098 char *mname = mono_method_full_name (cfg->method, TRUE);
1099 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1103 if (locals_stack_align) {
1104 int prev_offset = offset;
1106 offset += (locals_stack_align - 1);
1107 offset &= ~(locals_stack_align - 1);
1109 while (prev_offset < offset) {
1111 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1114 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1115 cfg->locals_max_stack_offset = - offset;
1117 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1118 * have locals larger than 8 bytes we need to make sure that
1119 * they have the appropriate offset.
1121 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1122 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1123 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1124 if (offsets [i] != -1) {
1125 MonoInst *inst = cfg->varinfo [i];
1126 inst->opcode = OP_REGOFFSET;
1127 inst->inst_basereg = X86_EBP;
1128 inst->inst_offset = - (offset + offsets [i]);
1129 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1132 offset += locals_stack_size;
1136 * Allocate arguments+return value
1139 switch (cinfo->ret.storage) {
1141 if (cfg->vret_addr) {
1143 * In the new IR, the cfg->vret_addr variable represents the
1144 * vtype return value.
1146 cfg->vret_addr->opcode = OP_REGOFFSET;
1147 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1148 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1149 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1150 printf ("vret_addr =");
1151 mono_print_ins (cfg->vret_addr);
1154 cfg->ret->opcode = OP_REGOFFSET;
1155 cfg->ret->inst_basereg = X86_EBP;
1156 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1159 case ArgValuetypeInReg:
1162 cfg->ret->opcode = OP_REGVAR;
1163 cfg->ret->inst_c0 = cinfo->ret.reg;
1164 cfg->ret->dreg = cinfo->ret.reg;
1167 case ArgOnFloatFpStack:
1168 case ArgOnDoubleFpStack:
1171 g_assert_not_reached ();
1174 if (sig->call_convention == MONO_CALL_VARARG) {
1175 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1176 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1179 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1180 ArgInfo *ainfo = &cinfo->args [i];
1181 inst = cfg->args [i];
1182 if (inst->opcode != OP_REGVAR) {
1183 inst->opcode = OP_REGOFFSET;
1184 inst->inst_basereg = X86_EBP;
1186 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1189 cfg->stack_offset = offset;
1193 mono_arch_create_vars (MonoCompile *cfg)
1196 MonoMethodSignature *sig;
1199 sig = mono_method_signature (cfg->method);
1201 cinfo = get_call_info (cfg->mempool, sig);
1202 sig_ret = mini_get_underlying_type (sig->ret);
1204 if (cinfo->ret.storage == ArgValuetypeInReg)
1205 cfg->ret_var_is_local = TRUE;
1206 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (sig_ret))) {
1207 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1210 if (cfg->gen_sdb_seq_points) {
1213 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1214 ins->flags |= MONO_INST_VOLATILE;
1215 cfg->arch.ss_tramp_var = ins;
1217 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1218 ins->flags |= MONO_INST_VOLATILE;
1219 cfg->arch.bp_tramp_var = ins;
1222 if (cfg->method->save_lmf) {
1223 cfg->create_lmf_var = TRUE;
1226 cfg->lmf_ir_mono_lmf = TRUE;
1230 cfg->arch_eh_jit_info = 1;
1234 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1235 * so we try to do it just once when we have multiple fp arguments in a row.
1236 * We don't use this mechanism generally because for int arguments the generated code
1237 * is slightly bigger and new generation cpus optimize away the dependency chains
1238 * created by push instructions on the esp value.
1239 * fp_arg_setup is the first argument in the execution sequence where the esp register
1242 static G_GNUC_UNUSED int
1243 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1248 for (; start_arg < sig->param_count; ++start_arg) {
1249 t = mini_get_underlying_type (sig->params [start_arg]);
1250 if (!t->byref && t->type == MONO_TYPE_R8) {
1251 fp_space += sizeof (double);
1252 *fp_arg_setup = start_arg;
1261 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1263 MonoMethodSignature *tmp_sig;
1267 * mono_ArgIterator_Setup assumes the signature cookie is
1268 * passed first and all the arguments which were before it are
1269 * passed on the stack after the signature. So compensate by
1270 * passing a different signature.
1272 tmp_sig = mono_metadata_signature_dup (call->signature);
1273 tmp_sig->param_count -= call->signature->sentinelpos;
1274 tmp_sig->sentinelpos = 0;
1275 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1277 if (cfg->compile_aot) {
1278 sig_reg = mono_alloc_ireg (cfg);
1279 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1280 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1282 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1288 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1293 LLVMCallInfo *linfo;
1294 MonoType *t, *sig_ret;
1296 n = sig->param_count + sig->hasthis;
1298 cinfo = get_call_info (cfg->mempool, sig);
1301 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1304 * LLVM always uses the native ABI while we use our own ABI, the
1305 * only difference is the handling of vtypes:
1306 * - we only pass/receive them in registers in some cases, and only
1307 * in 1 or 2 integer registers.
1309 if (cinfo->ret.storage == ArgValuetypeInReg) {
1311 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1312 cfg->disable_llvm = TRUE;
1316 cfg->exception_message = g_strdup ("vtype ret in call");
1317 cfg->disable_llvm = TRUE;
1319 linfo->ret.storage = LLVMArgVtypeInReg;
1320 for (j = 0; j < 2; ++j)
1321 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1325 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage == ArgInIReg) {
1326 /* Vtype returned using a hidden argument */
1327 linfo->ret.storage = LLVMArgVtypeRetAddr;
1328 linfo->vret_arg_index = cinfo->vret_arg_index;
1331 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage != ArgInIReg) {
1333 cfg->exception_message = g_strdup ("vtype ret in call");
1334 cfg->disable_llvm = TRUE;
1337 for (i = 0; i < n; ++i) {
1338 ainfo = cinfo->args + i;
1340 if (i >= sig->hasthis)
1341 t = sig->params [i - sig->hasthis];
1343 t = &mono_defaults.int_class->byval_arg;
1345 linfo->args [i].storage = LLVMArgNone;
1347 switch (ainfo->storage) {
1349 linfo->args [i].storage = LLVMArgNormal;
1351 case ArgInDoubleSSEReg:
1352 case ArgInFloatSSEReg:
1353 linfo->args [i].storage = LLVMArgNormal;
1356 if (mini_type_is_vtype (t)) {
1357 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1358 /* LLVM seems to allocate argument space for empty structures too */
1359 linfo->args [i].storage = LLVMArgNone;
1361 linfo->args [i].storage = LLVMArgVtypeByVal;
1363 linfo->args [i].storage = LLVMArgNormal;
1366 case ArgValuetypeInReg:
1368 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1369 cfg->disable_llvm = TRUE;
1373 cfg->exception_message = g_strdup ("vtype arg");
1374 cfg->disable_llvm = TRUE;
1376 linfo->args [i].storage = LLVMArgVtypeInReg;
1377 for (j = 0; j < 2; ++j)
1378 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1382 linfo->args [i].storage = LLVMArgGSharedVt;
1385 cfg->exception_message = g_strdup ("ainfo->storage");
1386 cfg->disable_llvm = TRUE;
1396 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1398 if (cfg->compute_gc_maps) {
1401 /* Needs checking if the feature will be enabled again */
1402 g_assert_not_reached ();
1404 /* On x86, the offsets are from the sp value before the start of the call sequence */
1406 t = &mono_defaults.int_class->byval_arg;
1407 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1412 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1416 MonoMethodSignature *sig;
1419 int sentinelpos = 0, sp_offset = 0;
1421 sig = call->signature;
1422 n = sig->param_count + sig->hasthis;
1423 sig_ret = mini_get_underlying_type (sig->ret);
1425 cinfo = get_call_info (cfg->mempool, sig);
1426 call->call_info = cinfo;
1428 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1429 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1431 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1432 if (cinfo->ret.storage == ArgValuetypeInReg) {
1434 * Tell the JIT to use a more efficient calling convention: call using
1435 * OP_CALL, compute the result location after the call, and save the
1438 call->vret_in_reg = TRUE;
1439 #if defined(__APPLE__)
1440 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1441 call->vret_in_reg_fp = TRUE;
1444 NULLIFY_INS (call->vret_var);
1448 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1450 /* Handle the case where there are no implicit arguments */
1451 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1452 emit_sig_cookie (cfg, call, cinfo);
1453 sp_offset = cinfo->sig_cookie.offset;
1454 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1457 /* Arguments are pushed in the reverse order */
1458 for (i = n - 1; i >= 0; i --) {
1459 ArgInfo *ainfo = cinfo->args + i;
1460 MonoType *orig_type, *t;
1463 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1466 /* Push the vret arg before the first argument */
1467 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1468 vtarg->type = STACK_MP;
1469 vtarg->inst_destbasereg = X86_ESP;
1470 vtarg->sreg1 = call->vret_var->dreg;
1471 vtarg->inst_offset = cinfo->ret.offset;
1472 MONO_ADD_INS (cfg->cbb, vtarg);
1473 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1476 if (i >= sig->hasthis)
1477 t = sig->params [i - sig->hasthis];
1479 t = &mono_defaults.int_class->byval_arg;
1481 t = mini_get_underlying_type (t);
1483 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1485 in = call->args [i];
1486 arg->cil_code = in->cil_code;
1487 arg->sreg1 = in->dreg;
1488 arg->type = in->type;
1490 g_assert (in->dreg != -1);
1492 if (ainfo->storage == ArgGSharedVt) {
1493 arg->opcode = OP_OUTARG_VT;
1494 arg->sreg1 = in->dreg;
1495 arg->klass = in->klass;
1496 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1497 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1499 MONO_ADD_INS (cfg->cbb, arg);
1500 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1504 g_assert (in->klass);
1506 if (t->type == MONO_TYPE_TYPEDBYREF) {
1507 size = sizeof (MonoTypedRef);
1508 align = sizeof (gpointer);
1511 size = mini_type_stack_size_full (&in->klass->byval_arg, &align, sig->pinvoke);
1515 arg->opcode = OP_OUTARG_VT;
1516 arg->sreg1 = in->dreg;
1517 arg->klass = in->klass;
1518 arg->backend.size = size;
1519 arg->inst_p0 = call;
1520 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1521 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1523 MONO_ADD_INS (cfg->cbb, arg);
1524 if (ainfo->storage != ArgValuetypeInReg) {
1525 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1529 switch (ainfo->storage) {
1532 if (t->type == MONO_TYPE_R4) {
1533 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1535 } else if (t->type == MONO_TYPE_R8) {
1536 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1538 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1539 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, MONO_LVREG_MS (in->dreg));
1540 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, MONO_LVREG_LS (in->dreg));
1543 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1547 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1552 arg->opcode = OP_MOVE;
1553 arg->dreg = ainfo->reg;
1554 MONO_ADD_INS (cfg->cbb, arg);
1558 g_assert_not_reached ();
1561 if (cfg->compute_gc_maps) {
1563 /* FIXME: The == STACK_OBJ check might be fragile ? */
1564 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1566 if (call->need_unbox_trampoline)
1567 /* The unbox trampoline transforms this into a managed pointer */
1568 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.int_class->this_arg);
1570 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.object_class->byval_arg);
1572 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1576 for (j = 0; j < argsize; j += 4)
1577 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1582 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1583 /* Emit the signature cookie just before the implicit arguments */
1584 emit_sig_cookie (cfg, call, cinfo);
1585 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1589 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1592 if (cinfo->ret.storage == ArgValuetypeInReg) {
1595 else if (cinfo->ret.storage == ArgInIReg) {
1597 /* The return address is passed in a register */
1598 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1599 vtarg->sreg1 = call->inst.dreg;
1600 vtarg->dreg = mono_alloc_ireg (cfg);
1601 MONO_ADD_INS (cfg->cbb, vtarg);
1603 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1604 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1605 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1606 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1610 call->stack_usage = cinfo->stack_usage;
1611 call->stack_align_amount = cinfo->stack_align_amount;
1615 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1617 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1618 ArgInfo *ainfo = ins->inst_p1;
1619 int size = ins->backend.size;
1621 if (ainfo->storage == ArgValuetypeInReg) {
1622 int dreg = mono_alloc_ireg (cfg);
1625 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1628 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1631 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1635 g_assert_not_reached ();
1637 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1640 if (cfg->gsharedvt && mini_is_gsharedvt_klass (ins->klass)) {
1642 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1643 } else if (size <= 4) {
1644 int dreg = mono_alloc_ireg (cfg);
1645 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1646 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1647 } else if (size <= 20) {
1648 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1650 // FIXME: Code growth
1651 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1657 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1659 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
1662 if (ret->type == MONO_TYPE_R4) {
1663 if (COMPILE_LLVM (cfg))
1664 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1667 } else if (ret->type == MONO_TYPE_R8) {
1668 if (COMPILE_LLVM (cfg))
1669 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1672 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1673 if (COMPILE_LLVM (cfg))
1674 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1676 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, MONO_LVREG_LS (val->dreg));
1677 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, MONO_LVREG_MS (val->dreg));
1683 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1687 * Allow tracing to work with this interface (with an optional argument)
1690 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1694 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1695 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1697 /* if some args are passed in registers, we need to save them here */
1698 x86_push_reg (code, X86_EBP);
1700 if (cfg->compile_aot) {
1701 x86_push_imm (code, cfg->method);
1702 x86_mov_reg_imm (code, X86_EAX, func);
1703 x86_call_reg (code, X86_EAX);
1705 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1706 x86_push_imm (code, cfg->method);
1707 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1708 x86_call_code (code, 0);
1710 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1724 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1727 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1728 MonoMethod *method = cfg->method;
1729 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
1731 switch (ret_type->type) {
1732 case MONO_TYPE_VOID:
1733 /* special case string .ctor icall */
1734 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1735 save_mode = SAVE_EAX;
1736 stack_usage = enable_arguments ? 8 : 4;
1738 save_mode = SAVE_NONE;
1742 save_mode = SAVE_EAX_EDX;
1743 stack_usage = enable_arguments ? 16 : 8;
1747 save_mode = SAVE_FP;
1748 stack_usage = enable_arguments ? 16 : 8;
1750 case MONO_TYPE_GENERICINST:
1751 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1752 save_mode = SAVE_EAX;
1753 stack_usage = enable_arguments ? 8 : 4;
1757 case MONO_TYPE_VALUETYPE:
1758 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1759 save_mode = SAVE_STRUCT;
1760 stack_usage = enable_arguments ? 4 : 0;
1763 save_mode = SAVE_EAX;
1764 stack_usage = enable_arguments ? 8 : 4;
1768 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1770 switch (save_mode) {
1772 x86_push_reg (code, X86_EDX);
1773 x86_push_reg (code, X86_EAX);
1774 if (enable_arguments) {
1775 x86_push_reg (code, X86_EDX);
1776 x86_push_reg (code, X86_EAX);
1781 x86_push_reg (code, X86_EAX);
1782 if (enable_arguments) {
1783 x86_push_reg (code, X86_EAX);
1788 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1789 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1790 if (enable_arguments) {
1791 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1792 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1797 if (enable_arguments) {
1798 x86_push_membase (code, X86_EBP, 8);
1807 if (cfg->compile_aot) {
1808 x86_push_imm (code, method);
1809 x86_mov_reg_imm (code, X86_EAX, func);
1810 x86_call_reg (code, X86_EAX);
1812 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1813 x86_push_imm (code, method);
1814 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1815 x86_call_code (code, 0);
1818 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1820 switch (save_mode) {
1822 x86_pop_reg (code, X86_EAX);
1823 x86_pop_reg (code, X86_EDX);
1826 x86_pop_reg (code, X86_EAX);
1829 x86_fld_membase (code, X86_ESP, 0, TRUE);
1830 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1837 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1842 #define EMIT_COND_BRANCH(ins,cond,sign) \
1843 if (ins->inst_true_bb->native_offset) { \
1844 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1846 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1847 if ((cfg->opt & MONO_OPT_BRANCH) && \
1848 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1849 x86_branch8 (code, cond, 0, sign); \
1851 x86_branch32 (code, cond, 0, sign); \
1855 * Emit an exception if condition is fail and
1856 * if possible do a directly branch to target
1858 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1860 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1861 if (tins == NULL) { \
1862 mono_add_patch_info (cfg, code - cfg->native_code, \
1863 MONO_PATCH_INFO_EXC, exc_name); \
1864 x86_branch32 (code, cond, 0, signed); \
1866 EMIT_COND_BRANCH (tins, cond, signed); \
1870 #define EMIT_FPCOMPARE(code) do { \
1871 x86_fcompp (code); \
1872 x86_fnstsw (code); \
1877 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1879 gboolean needs_paddings = TRUE;
1881 MonoJumpInfo *jinfo = NULL;
1883 if (cfg->abs_patches) {
1884 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1885 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1886 needs_paddings = FALSE;
1889 if (cfg->compile_aot)
1890 needs_paddings = FALSE;
1891 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1892 This is required for code patching to be safe on SMP machines.
1894 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1895 #ifndef __native_client_codegen__
1896 if (needs_paddings && pad_size)
1897 x86_padding (code, 4 - pad_size);
1900 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1901 x86_call_code (code, 0);
1906 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1909 * mono_peephole_pass_1:
1911 * Perform peephole opts which should/can be performed before local regalloc
1914 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1918 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1919 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1921 switch (ins->opcode) {
1924 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1926 * X86_LEA is like ADD, but doesn't have the
1927 * sreg1==dreg restriction.
1929 ins->opcode = OP_X86_LEA_MEMBASE;
1930 ins->inst_basereg = ins->sreg1;
1931 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1932 ins->opcode = OP_X86_INC_REG;
1936 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1937 ins->opcode = OP_X86_LEA_MEMBASE;
1938 ins->inst_basereg = ins->sreg1;
1939 ins->inst_imm = -ins->inst_imm;
1940 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1941 ins->opcode = OP_X86_DEC_REG;
1943 case OP_COMPARE_IMM:
1944 case OP_ICOMPARE_IMM:
1945 /* OP_COMPARE_IMM (reg, 0)
1947 * OP_X86_TEST_NULL (reg)
1950 ins->opcode = OP_X86_TEST_NULL;
1952 case OP_X86_COMPARE_MEMBASE_IMM:
1954 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1955 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1957 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1958 * OP_COMPARE_IMM reg, imm
1960 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1962 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1963 ins->inst_basereg == last_ins->inst_destbasereg &&
1964 ins->inst_offset == last_ins->inst_offset) {
1965 ins->opcode = OP_COMPARE_IMM;
1966 ins->sreg1 = last_ins->sreg1;
1968 /* check if we can remove cmp reg,0 with test null */
1970 ins->opcode = OP_X86_TEST_NULL;
1974 case OP_X86_PUSH_MEMBASE:
1975 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1976 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1977 ins->inst_basereg == last_ins->inst_destbasereg &&
1978 ins->inst_offset == last_ins->inst_offset) {
1979 ins->opcode = OP_X86_PUSH;
1980 ins->sreg1 = last_ins->sreg1;
1985 mono_peephole_ins (bb, ins);
1990 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1994 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1995 switch (ins->opcode) {
1997 /* reg = 0 -> XOR (reg, reg) */
1998 /* XOR sets cflags on x86, so we cant do it always */
1999 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2002 ins->opcode = OP_IXOR;
2003 ins->sreg1 = ins->dreg;
2004 ins->sreg2 = ins->dreg;
2007 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2008 * since it takes 3 bytes instead of 7.
2010 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
2011 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2012 ins2->opcode = OP_STORE_MEMBASE_REG;
2013 ins2->sreg1 = ins->dreg;
2015 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2016 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2017 ins2->sreg1 = ins->dreg;
2019 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2020 /* Continue iteration */
2029 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2030 ins->opcode = OP_X86_INC_REG;
2034 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2035 ins->opcode = OP_X86_DEC_REG;
2039 mono_peephole_ins (bb, ins);
2044 * mono_arch_lowering_pass:
2046 * Converts complex opcodes into simpler ones so that each IR instruction
2047 * corresponds to one machine instruction.
2050 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2052 MonoInst *ins, *next;
2055 * FIXME: Need to add more instructions, but the current machine
2056 * description can't model some parts of the composite instructions like
2059 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2060 switch (ins->opcode) {
2063 case OP_IDIV_UN_IMM:
2064 case OP_IREM_UN_IMM:
2066 * Keep the cases where we could generated optimized code, otherwise convert
2067 * to the non-imm variant.
2069 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2071 mono_decompose_op_imm (cfg, bb, ins);
2078 bb->max_vreg = cfg->next_vreg;
2082 branch_cc_table [] = {
2083 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2084 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2085 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2088 /* Maps CMP_... constants to X86_CC_... constants */
2091 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2092 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2096 cc_signed_table [] = {
2097 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2098 FALSE, FALSE, FALSE, FALSE
2101 static unsigned char*
2102 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2104 #define XMM_TEMP_REG 0
2105 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2106 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2107 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2108 /* optimize by assigning a local var for this use so we avoid
2109 * the stack manipulations */
2110 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2111 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2112 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2113 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2114 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2116 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2118 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2121 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2122 x86_fnstcw_membase(code, X86_ESP, 0);
2123 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2124 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2125 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2126 x86_fldcw_membase (code, X86_ESP, 2);
2128 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2129 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2130 x86_pop_reg (code, dreg);
2131 /* FIXME: need the high register
2132 * x86_pop_reg (code, dreg_high);
2135 x86_push_reg (code, X86_EAX); // SP = SP - 4
2136 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2137 x86_pop_reg (code, dreg);
2139 x86_fldcw_membase (code, X86_ESP, 0);
2140 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2143 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2145 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2149 static unsigned char*
2150 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2152 int sreg = tree->sreg1;
2153 int need_touch = FALSE;
2155 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2164 * If requested stack size is larger than one page,
2165 * perform stack-touch operation
2168 * Generate stack probe code.
2169 * Under Windows, it is necessary to allocate one page at a time,
2170 * "touching" stack after each successful sub-allocation. This is
2171 * because of the way stack growth is implemented - there is a
2172 * guard page before the lowest stack page that is currently commited.
2173 * Stack normally grows sequentially so OS traps access to the
2174 * guard page and commits more pages when needed.
2176 x86_test_reg_imm (code, sreg, ~0xFFF);
2177 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2179 br[2] = code; /* loop */
2180 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2181 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2184 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2185 * that follows only initializes the last part of the area.
2187 /* Same as the init code below with size==0x1000 */
2188 if (tree->flags & MONO_INST_INIT) {
2189 x86_push_reg (code, X86_EAX);
2190 x86_push_reg (code, X86_ECX);
2191 x86_push_reg (code, X86_EDI);
2192 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2193 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2194 if (cfg->param_area)
2195 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2197 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2199 x86_prefix (code, X86_REP_PREFIX);
2201 x86_pop_reg (code, X86_EDI);
2202 x86_pop_reg (code, X86_ECX);
2203 x86_pop_reg (code, X86_EAX);
2206 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2207 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2208 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2209 x86_patch (br[3], br[2]);
2210 x86_test_reg_reg (code, sreg, sreg);
2211 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2212 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2214 br[1] = code; x86_jump8 (code, 0);
2216 x86_patch (br[0], code);
2217 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2218 x86_patch (br[1], code);
2219 x86_patch (br[4], code);
2222 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2224 if (tree->flags & MONO_INST_INIT) {
2226 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2227 x86_push_reg (code, X86_EAX);
2230 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2231 x86_push_reg (code, X86_ECX);
2234 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2235 x86_push_reg (code, X86_EDI);
2239 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2240 if (sreg != X86_ECX)
2241 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2242 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2244 if (cfg->param_area)
2245 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2247 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2249 x86_prefix (code, X86_REP_PREFIX);
2252 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2253 x86_pop_reg (code, X86_EDI);
2254 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2255 x86_pop_reg (code, X86_ECX);
2256 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2257 x86_pop_reg (code, X86_EAX);
2264 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2266 /* Move return value to the target register */
2267 switch (ins->opcode) {
2270 case OP_CALL_MEMBASE:
2271 if (ins->dreg != X86_EAX)
2272 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2282 static int tls_gs_offset;
2286 mono_x86_have_tls_get (void)
2289 static gboolean have_tls_get = FALSE;
2290 static gboolean inited = FALSE;
2293 return have_tls_get;
2295 #ifdef MONO_HAVE_FAST_TLS
2298 ins = (guint32*)pthread_getspecific;
2300 * We're looking for these two instructions:
2302 * mov 0x4(%esp),%eax
2303 * mov %gs:[offset](,%eax,4),%eax
2305 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2306 tls_gs_offset = ins [2];
2311 return have_tls_get;
2312 #elif defined(TARGET_ANDROID)
2320 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2322 #if defined(__APPLE__)
2323 x86_prefix (code, X86_GS_PREFIX);
2324 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2325 #elif defined(TARGET_WIN32)
2326 g_assert_not_reached ();
2328 x86_prefix (code, X86_GS_PREFIX);
2329 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2335 * mono_x86_emit_tls_get:
2336 * @code: buffer to store code to
2337 * @dreg: hard register where to place the result
2338 * @tls_offset: offset info
2340 * mono_x86_emit_tls_get emits in @code the native code that puts in
2341 * the dreg register the item in the thread local storage identified
2344 * Returns: a pointer to the end of the stored code
2347 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2349 #if defined(__APPLE__)
2350 x86_prefix (code, X86_GS_PREFIX);
2351 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2352 #elif defined(TARGET_WIN32)
2354 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2355 * Journal and/or a disassembly of the TlsGet () function.
2357 x86_prefix (code, X86_FS_PREFIX);
2358 x86_mov_reg_mem (code, dreg, 0x18, 4);
2359 if (tls_offset < 64) {
2360 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2364 g_assert (tls_offset < 0x440);
2365 /* Load TEB->TlsExpansionSlots */
2366 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2367 x86_test_reg_reg (code, dreg, dreg);
2369 x86_branch (code, X86_CC_EQ, code, TRUE);
2370 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2371 x86_patch (buf [0], code);
2374 if (optimize_for_xen) {
2375 x86_prefix (code, X86_GS_PREFIX);
2376 x86_mov_reg_mem (code, dreg, 0, 4);
2377 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2379 x86_prefix (code, X86_GS_PREFIX);
2380 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2387 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2389 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2390 #if defined(__APPLE__) || defined(__linux__)
2391 if (dreg != offset_reg)
2392 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2393 x86_prefix (code, X86_GS_PREFIX);
2394 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2396 g_assert_not_reached ();
2402 mono_x86_emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2404 return emit_tls_get_reg (code, dreg, offset_reg);
2408 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2410 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2412 g_assert_not_reached ();
2413 #elif defined(__APPLE__) || defined(__linux__)
2414 x86_prefix (code, X86_GS_PREFIX);
2415 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2417 g_assert_not_reached ();
2423 * mono_arch_translate_tls_offset:
2425 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2428 mono_arch_translate_tls_offset (int offset)
2431 return tls_gs_offset + (offset * 4);
2440 * Emit code to initialize an LMF structure at LMF_OFFSET.
2443 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2445 /* save all caller saved regs */
2446 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2447 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2448 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2449 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2450 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2451 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2452 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2454 /* save the current IP */
2455 if (cfg->compile_aot) {
2456 /* This pushes the current ip */
2457 x86_call_imm (code, 0);
2458 x86_pop_reg (code, X86_EAX);
2460 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2461 x86_mov_reg_imm (code, X86_EAX, 0);
2463 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2465 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2466 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2467 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2468 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2469 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2470 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2471 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2472 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2473 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2478 /* benchmark and set based on cpu */
2479 #define LOOP_ALIGNMENT 8
2480 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2484 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2489 guint8 *code = cfg->native_code + cfg->code_len;
2492 if (cfg->opt & MONO_OPT_LOOP) {
2493 int pad, align = LOOP_ALIGNMENT;
2494 /* set alignment depending on cpu */
2495 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2497 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2498 x86_padding (code, pad);
2499 cfg->code_len += pad;
2500 bb->native_offset = cfg->code_len;
2503 #ifdef __native_client_codegen__
2505 /* For Native Client, all indirect call/jump targets must be */
2506 /* 32-byte aligned. Exception handler blocks are jumped to */
2507 /* indirectly as well. */
2508 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2509 (bb->flags & BB_EXCEPTION_HANDLER);
2511 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2512 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2513 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2514 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2515 cfg->code_len += pad;
2516 bb->native_offset = cfg->code_len;
2519 #endif /* __native_client_codegen__ */
2520 if (cfg->verbose_level > 2)
2521 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2523 cpos = bb->max_offset;
2525 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
2526 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2527 g_assert (!cfg->compile_aot);
2530 cov->data [bb->dfn].cil_code = bb->cil_code;
2531 /* this is not thread save, but good enough */
2532 x86_inc_mem (code, &cov->data [bb->dfn].count);
2535 offset = code - cfg->native_code;
2537 mono_debug_open_block (cfg, bb, offset);
2539 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2540 x86_breakpoint (code);
2542 MONO_BB_FOR_EACH_INS (bb, ins) {
2543 offset = code - cfg->native_code;
2545 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2547 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2549 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2550 cfg->code_size *= 2;
2551 cfg->native_code = mono_realloc_native_code(cfg);
2552 code = cfg->native_code + offset;
2553 cfg->stat_code_reallocs++;
2556 if (cfg->debug_info)
2557 mono_debug_record_line_number (cfg, ins, offset);
2559 switch (ins->opcode) {
2561 x86_mul_reg (code, ins->sreg2, TRUE);
2564 x86_mul_reg (code, ins->sreg2, FALSE);
2566 case OP_X86_SETEQ_MEMBASE:
2567 case OP_X86_SETNE_MEMBASE:
2568 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2569 ins->inst_basereg, ins->inst_offset, TRUE);
2571 case OP_STOREI1_MEMBASE_IMM:
2572 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2574 case OP_STOREI2_MEMBASE_IMM:
2575 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2577 case OP_STORE_MEMBASE_IMM:
2578 case OP_STOREI4_MEMBASE_IMM:
2579 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2581 case OP_STOREI1_MEMBASE_REG:
2582 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2584 case OP_STOREI2_MEMBASE_REG:
2585 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2587 case OP_STORE_MEMBASE_REG:
2588 case OP_STOREI4_MEMBASE_REG:
2589 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2591 case OP_STORE_MEM_IMM:
2592 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2595 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2599 /* These are created by the cprop pass so they use inst_imm as the source */
2600 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2603 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2606 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2608 case OP_LOAD_MEMBASE:
2609 case OP_LOADI4_MEMBASE:
2610 case OP_LOADU4_MEMBASE:
2611 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2613 case OP_LOADU1_MEMBASE:
2614 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2616 case OP_LOADI1_MEMBASE:
2617 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2619 case OP_LOADU2_MEMBASE:
2620 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2622 case OP_LOADI2_MEMBASE:
2623 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2625 case OP_ICONV_TO_I1:
2627 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2629 case OP_ICONV_TO_I2:
2631 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2633 case OP_ICONV_TO_U1:
2634 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2636 case OP_ICONV_TO_U2:
2637 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2641 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2643 case OP_COMPARE_IMM:
2644 case OP_ICOMPARE_IMM:
2645 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2647 case OP_X86_COMPARE_MEMBASE_REG:
2648 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2650 case OP_X86_COMPARE_MEMBASE_IMM:
2651 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2653 case OP_X86_COMPARE_MEMBASE8_IMM:
2654 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2656 case OP_X86_COMPARE_REG_MEMBASE:
2657 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2659 case OP_X86_COMPARE_MEM_IMM:
2660 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2662 case OP_X86_TEST_NULL:
2663 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2665 case OP_X86_ADD_MEMBASE_IMM:
2666 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2668 case OP_X86_ADD_REG_MEMBASE:
2669 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2671 case OP_X86_SUB_MEMBASE_IMM:
2672 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2674 case OP_X86_SUB_REG_MEMBASE:
2675 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2677 case OP_X86_AND_MEMBASE_IMM:
2678 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2680 case OP_X86_OR_MEMBASE_IMM:
2681 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2683 case OP_X86_XOR_MEMBASE_IMM:
2684 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2686 case OP_X86_ADD_MEMBASE_REG:
2687 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2689 case OP_X86_SUB_MEMBASE_REG:
2690 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2692 case OP_X86_AND_MEMBASE_REG:
2693 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2695 case OP_X86_OR_MEMBASE_REG:
2696 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2698 case OP_X86_XOR_MEMBASE_REG:
2699 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2701 case OP_X86_INC_MEMBASE:
2702 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2704 case OP_X86_INC_REG:
2705 x86_inc_reg (code, ins->dreg);
2707 case OP_X86_DEC_MEMBASE:
2708 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2710 case OP_X86_DEC_REG:
2711 x86_dec_reg (code, ins->dreg);
2713 case OP_X86_MUL_REG_MEMBASE:
2714 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2716 case OP_X86_AND_REG_MEMBASE:
2717 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2719 case OP_X86_OR_REG_MEMBASE:
2720 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2722 case OP_X86_XOR_REG_MEMBASE:
2723 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2726 x86_breakpoint (code);
2728 case OP_RELAXED_NOP:
2729 x86_prefix (code, X86_REP_PREFIX);
2737 case OP_DUMMY_STORE:
2738 case OP_DUMMY_ICONST:
2739 case OP_DUMMY_R8CONST:
2740 case OP_NOT_REACHED:
2743 case OP_IL_SEQ_POINT:
2744 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2746 case OP_SEQ_POINT: {
2749 if (cfg->compile_aot)
2752 /* Have to use ecx as a temp reg since this can occur after OP_SETRET */
2755 * We do this _before_ the breakpoint, so single stepping after
2756 * a breakpoint is hit will step to the next IL offset.
2758 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
2759 MonoInst *var = cfg->arch.ss_tramp_var;
2763 g_assert (var->opcode == OP_REGOFFSET);
2764 /* Load ss_tramp_var */
2765 /* This is equal to &ss_trampoline */
2766 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, sizeof (mgreg_t));
2767 x86_alu_membase_imm (code, X86_CMP, X86_ECX, 0, 0);
2768 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2769 x86_call_membase (code, X86_ECX, 0);
2770 x86_patch (br [0], code);
2774 * Many parts of sdb depend on the ip after the single step trampoline call to be equal to the seq point offset.
2775 * This means we have to put the loading of bp_tramp_var after the offset.
2778 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2780 MonoInst *var = cfg->arch.bp_tramp_var;
2783 g_assert (var->opcode == OP_REGOFFSET);
2784 /* Load the address of the bp trampoline */
2785 /* This needs to be constant size */
2786 guint8 *start = code;
2787 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, 4);
2788 if (code < start + OP_SEQ_POINT_BP_OFFSET) {
2789 int size = start + OP_SEQ_POINT_BP_OFFSET - code;
2790 x86_padding (code, size);
2793 * A placeholder for a possible breakpoint inserted by
2794 * mono_arch_set_breakpoint ().
2796 for (i = 0; i < 2; ++i)
2799 * Add an additional nop so skipping the bp doesn't cause the ip to point
2800 * to another IL offset.
2808 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2812 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2817 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2821 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2826 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2830 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2835 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2839 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2842 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2846 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2850 #if defined( __native_client_codegen__ )
2851 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2852 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2855 * The code is the same for div/rem, the allocator will allocate dreg
2856 * to RAX/RDX as appropriate.
2858 if (ins->sreg2 == X86_EDX) {
2859 /* cdq clobbers this */
2860 x86_push_reg (code, ins->sreg2);
2862 x86_div_membase (code, X86_ESP, 0, TRUE);
2863 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2866 x86_div_reg (code, ins->sreg2, TRUE);
2871 #if defined( __native_client_codegen__ )
2872 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2873 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2875 if (ins->sreg2 == X86_EDX) {
2876 x86_push_reg (code, ins->sreg2);
2877 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2878 x86_div_membase (code, X86_ESP, 0, FALSE);
2879 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2881 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2882 x86_div_reg (code, ins->sreg2, FALSE);
2886 #if defined( __native_client_codegen__ )
2887 if (ins->inst_imm == 0) {
2888 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2889 x86_jump32 (code, 0);
2893 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2895 x86_div_reg (code, ins->sreg2, TRUE);
2898 int power = mono_is_power_of_two (ins->inst_imm);
2900 g_assert (ins->sreg1 == X86_EAX);
2901 g_assert (ins->dreg == X86_EAX);
2902 g_assert (power >= 0);
2905 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2907 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2909 * If the divident is >= 0, this does not nothing. If it is positive, it
2910 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2912 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2913 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2914 } else if (power == 0) {
2915 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2917 /* Based on gcc code */
2919 /* Add compensation for negative dividents */
2921 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2922 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2923 /* Compute remainder */
2924 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2925 /* Remove compensation */
2926 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2931 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2935 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2938 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2942 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2945 g_assert (ins->sreg2 == X86_ECX);
2946 x86_shift_reg (code, X86_SHL, ins->dreg);
2949 g_assert (ins->sreg2 == X86_ECX);
2950 x86_shift_reg (code, X86_SAR, ins->dreg);
2954 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2957 case OP_ISHR_UN_IMM:
2958 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2961 g_assert (ins->sreg2 == X86_ECX);
2962 x86_shift_reg (code, X86_SHR, ins->dreg);
2966 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2969 guint8 *jump_to_end;
2971 /* handle shifts below 32 bits */
2972 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2973 x86_shift_reg (code, X86_SHL, ins->sreg1);
2975 x86_test_reg_imm (code, X86_ECX, 32);
2976 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2978 /* handle shift over 32 bit */
2979 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2980 x86_clear_reg (code, ins->sreg1);
2982 x86_patch (jump_to_end, code);
2986 guint8 *jump_to_end;
2988 /* handle shifts below 32 bits */
2989 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2990 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2992 x86_test_reg_imm (code, X86_ECX, 32);
2993 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2995 /* handle shifts over 31 bits */
2996 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2997 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2999 x86_patch (jump_to_end, code);
3003 guint8 *jump_to_end;
3005 /* handle shifts below 32 bits */
3006 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3007 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
3009 x86_test_reg_imm (code, X86_ECX, 32);
3010 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3012 /* handle shifts over 31 bits */
3013 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3014 x86_clear_reg (code, ins->backend.reg3);
3016 x86_patch (jump_to_end, code);
3020 if (ins->inst_imm >= 32) {
3021 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3022 x86_clear_reg (code, ins->sreg1);
3023 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
3025 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
3026 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
3030 if (ins->inst_imm >= 32) {
3031 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3032 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
3033 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
3035 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3036 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3039 case OP_LSHR_UN_IMM:
3040 if (ins->inst_imm >= 32) {
3041 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3042 x86_clear_reg (code, ins->backend.reg3);
3043 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3045 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3046 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3050 x86_not_reg (code, ins->sreg1);
3053 x86_neg_reg (code, ins->sreg1);
3057 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3061 switch (ins->inst_imm) {
3065 if (ins->dreg != ins->sreg1)
3066 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3067 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3070 /* LEA r1, [r2 + r2*2] */
3071 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3074 /* LEA r1, [r2 + r2*4] */
3075 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3078 /* LEA r1, [r2 + r2*2] */
3080 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3081 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3084 /* LEA r1, [r2 + r2*8] */
3085 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3088 /* LEA r1, [r2 + r2*4] */
3090 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3091 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3094 /* LEA r1, [r2 + r2*2] */
3096 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3097 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3100 /* LEA r1, [r2 + r2*4] */
3101 /* LEA r1, [r1 + r1*4] */
3102 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3103 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3106 /* LEA r1, [r2 + r2*4] */
3108 /* LEA r1, [r1 + r1*4] */
3109 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3110 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3111 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3114 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3119 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3120 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3122 case OP_IMUL_OVF_UN: {
3123 /* the mul operation and the exception check should most likely be split */
3124 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3125 /*g_assert (ins->sreg2 == X86_EAX);
3126 g_assert (ins->dreg == X86_EAX);*/
3127 if (ins->sreg2 == X86_EAX) {
3128 non_eax_reg = ins->sreg1;
3129 } else if (ins->sreg1 == X86_EAX) {
3130 non_eax_reg = ins->sreg2;
3132 /* no need to save since we're going to store to it anyway */
3133 if (ins->dreg != X86_EAX) {
3135 x86_push_reg (code, X86_EAX);
3137 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3138 non_eax_reg = ins->sreg2;
3140 if (ins->dreg == X86_EDX) {
3143 x86_push_reg (code, X86_EAX);
3147 x86_push_reg (code, X86_EDX);
3149 x86_mul_reg (code, non_eax_reg, FALSE);
3150 /* save before the check since pop and mov don't change the flags */
3151 if (ins->dreg != X86_EAX)
3152 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3154 x86_pop_reg (code, X86_EDX);
3156 x86_pop_reg (code, X86_EAX);
3157 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3161 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3164 g_assert_not_reached ();
3165 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3166 x86_mov_reg_imm (code, ins->dreg, 0);
3169 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3170 x86_mov_reg_imm (code, ins->dreg, 0);
3172 case OP_LOAD_GOTADDR:
3173 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3174 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3177 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3178 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3180 case OP_X86_PUSH_GOT_ENTRY:
3181 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3182 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3185 if (ins->dreg != ins->sreg1)
3186 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3189 MonoCallInst *call = (MonoCallInst*)ins;
3192 ins->flags |= MONO_INST_GC_CALLSITE;
3193 ins->backend.pc_offset = code - cfg->native_code;
3195 /* reset offset to make max_len work */
3196 offset = code - cfg->native_code;
3198 g_assert (!cfg->method->save_lmf);
3200 /* restore callee saved registers */
3201 for (i = 0; i < X86_NREG; ++i)
3202 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3204 if (cfg->used_int_regs & (1 << X86_ESI)) {
3205 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3208 if (cfg->used_int_regs & (1 << X86_EDI)) {
3209 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3212 if (cfg->used_int_regs & (1 << X86_EBX)) {
3213 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3217 /* Copy arguments on the stack to our argument area */
3218 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3219 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3220 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3223 /* restore ESP/EBP */
3225 offset = code - cfg->native_code;
3226 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3227 x86_jump32 (code, 0);
3229 ins->flags |= MONO_INST_GC_CALLSITE;
3230 cfg->disable_aot = TRUE;
3234 /* ensure ins->sreg1 is not NULL
3235 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3236 * cmp DWORD PTR [eax], 0
3238 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3241 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3242 x86_push_reg (code, hreg);
3243 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3244 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3245 x86_pop_reg (code, hreg);
3258 case OP_VOIDCALL_REG:
3260 case OP_FCALL_MEMBASE:
3261 case OP_LCALL_MEMBASE:
3262 case OP_VCALL_MEMBASE:
3263 case OP_VCALL2_MEMBASE:
3264 case OP_VOIDCALL_MEMBASE:
3265 case OP_CALL_MEMBASE: {
3268 call = (MonoCallInst*)ins;
3269 cinfo = (CallInfo*)call->call_info;
3271 switch (ins->opcode) {
3278 if (ins->flags & MONO_INST_HAS_METHOD)
3279 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3281 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3287 case OP_VOIDCALL_REG:
3289 x86_call_reg (code, ins->sreg1);
3291 case OP_FCALL_MEMBASE:
3292 case OP_LCALL_MEMBASE:
3293 case OP_VCALL_MEMBASE:
3294 case OP_VCALL2_MEMBASE:
3295 case OP_VOIDCALL_MEMBASE:
3296 case OP_CALL_MEMBASE:
3297 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3300 g_assert_not_reached ();
3303 ins->flags |= MONO_INST_GC_CALLSITE;
3304 ins->backend.pc_offset = code - cfg->native_code;
3305 if (cinfo->callee_stack_pop) {
3306 /* Have to compensate for the stack space popped by the callee */
3307 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3309 code = emit_move_return_value (cfg, ins, code);
3313 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3315 case OP_X86_LEA_MEMBASE:
3316 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3319 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3322 /* keep alignment */
3323 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3324 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3325 code = mono_emit_stack_alloc (cfg, code, ins);
3326 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3327 if (cfg->param_area)
3328 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3330 case OP_LOCALLOC_IMM: {
3331 guint32 size = ins->inst_imm;
3332 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3334 if (ins->flags & MONO_INST_INIT) {
3335 /* FIXME: Optimize this */
3336 x86_mov_reg_imm (code, ins->dreg, size);
3337 ins->sreg1 = ins->dreg;
3339 code = mono_emit_stack_alloc (cfg, code, ins);
3340 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3342 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3343 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3345 if (cfg->param_area)
3346 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3350 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3351 x86_push_reg (code, ins->sreg1);
3352 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3353 (gpointer)"mono_arch_throw_exception");
3354 ins->flags |= MONO_INST_GC_CALLSITE;
3355 ins->backend.pc_offset = code - cfg->native_code;
3359 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3360 x86_push_reg (code, ins->sreg1);
3361 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3362 (gpointer)"mono_arch_rethrow_exception");
3363 ins->flags |= MONO_INST_GC_CALLSITE;
3364 ins->backend.pc_offset = code - cfg->native_code;
3367 case OP_CALL_HANDLER:
3368 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3369 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3370 x86_call_imm (code, 0);
3371 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3372 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3374 case OP_START_HANDLER: {
3375 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3376 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3377 if (cfg->param_area)
3378 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3381 case OP_ENDFINALLY: {
3382 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3383 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3387 case OP_ENDFILTER: {
3388 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3389 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3390 /* The local allocator will put the result into EAX */
3395 if (ins->dreg != X86_EAX)
3396 x86_mov_reg_reg (code, ins->dreg, X86_EAX, sizeof (gpointer));
3400 ins->inst_c0 = code - cfg->native_code;
3403 if (ins->inst_target_bb->native_offset) {
3404 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3406 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3407 if ((cfg->opt & MONO_OPT_BRANCH) &&
3408 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3409 x86_jump8 (code, 0);
3411 x86_jump32 (code, 0);
3415 x86_jump_reg (code, ins->sreg1);
3434 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3435 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3437 case OP_COND_EXC_EQ:
3438 case OP_COND_EXC_NE_UN:
3439 case OP_COND_EXC_LT:
3440 case OP_COND_EXC_LT_UN:
3441 case OP_COND_EXC_GT:
3442 case OP_COND_EXC_GT_UN:
3443 case OP_COND_EXC_GE:
3444 case OP_COND_EXC_GE_UN:
3445 case OP_COND_EXC_LE:
3446 case OP_COND_EXC_LE_UN:
3447 case OP_COND_EXC_IEQ:
3448 case OP_COND_EXC_INE_UN:
3449 case OP_COND_EXC_ILT:
3450 case OP_COND_EXC_ILT_UN:
3451 case OP_COND_EXC_IGT:
3452 case OP_COND_EXC_IGT_UN:
3453 case OP_COND_EXC_IGE:
3454 case OP_COND_EXC_IGE_UN:
3455 case OP_COND_EXC_ILE:
3456 case OP_COND_EXC_ILE_UN:
3457 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3459 case OP_COND_EXC_OV:
3460 case OP_COND_EXC_NO:
3462 case OP_COND_EXC_NC:
3463 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3465 case OP_COND_EXC_IOV:
3466 case OP_COND_EXC_INO:
3467 case OP_COND_EXC_IC:
3468 case OP_COND_EXC_INC:
3469 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3481 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3489 case OP_CMOV_INE_UN:
3490 case OP_CMOV_IGE_UN:
3491 case OP_CMOV_IGT_UN:
3492 case OP_CMOV_ILE_UN:
3493 case OP_CMOV_ILT_UN:
3494 g_assert (ins->dreg == ins->sreg1);
3495 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3498 /* floating point opcodes */
3500 double d = *(double *)ins->inst_p0;
3502 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3504 } else if (d == 1.0) {
3507 if (cfg->compile_aot) {
3508 guint32 *val = (guint32*)&d;
3509 x86_push_imm (code, val [1]);
3510 x86_push_imm (code, val [0]);
3511 x86_fld_membase (code, X86_ESP, 0, TRUE);
3512 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3515 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3516 x86_fld (code, NULL, TRUE);
3522 float f = *(float *)ins->inst_p0;
3524 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3526 } else if (f == 1.0) {
3529 if (cfg->compile_aot) {
3530 guint32 val = *(guint32*)&f;
3531 x86_push_imm (code, val);
3532 x86_fld_membase (code, X86_ESP, 0, FALSE);
3533 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3536 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3537 x86_fld (code, NULL, FALSE);
3542 case OP_STORER8_MEMBASE_REG:
3543 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3545 case OP_LOADR8_MEMBASE:
3546 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3548 case OP_STORER4_MEMBASE_REG:
3549 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3551 case OP_LOADR4_MEMBASE:
3552 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3554 case OP_ICONV_TO_R4:
3555 x86_push_reg (code, ins->sreg1);
3556 x86_fild_membase (code, X86_ESP, 0, FALSE);
3557 /* Change precision */
3558 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3559 x86_fld_membase (code, X86_ESP, 0, FALSE);
3560 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3562 case OP_ICONV_TO_R8:
3563 x86_push_reg (code, ins->sreg1);
3564 x86_fild_membase (code, X86_ESP, 0, FALSE);
3565 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3567 case OP_ICONV_TO_R_UN:
3568 x86_push_imm (code, 0);
3569 x86_push_reg (code, ins->sreg1);
3570 x86_fild_membase (code, X86_ESP, 0, TRUE);
3571 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3573 case OP_X86_FP_LOAD_I8:
3574 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3576 case OP_X86_FP_LOAD_I4:
3577 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3579 case OP_FCONV_TO_R4:
3580 /* Change precision */
3581 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3582 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3583 x86_fld_membase (code, X86_ESP, 0, FALSE);
3584 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3586 case OP_FCONV_TO_I1:
3587 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3589 case OP_FCONV_TO_U1:
3590 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3592 case OP_FCONV_TO_I2:
3593 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3595 case OP_FCONV_TO_U2:
3596 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3598 case OP_FCONV_TO_I4:
3600 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3602 case OP_FCONV_TO_I8:
3603 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3604 x86_fnstcw_membase(code, X86_ESP, 0);
3605 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3606 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3607 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3608 x86_fldcw_membase (code, X86_ESP, 2);
3609 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3610 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3611 x86_pop_reg (code, ins->dreg);
3612 x86_pop_reg (code, ins->backend.reg3);
3613 x86_fldcw_membase (code, X86_ESP, 0);
3614 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3616 case OP_LCONV_TO_R8_2:
3617 x86_push_reg (code, ins->sreg2);
3618 x86_push_reg (code, ins->sreg1);
3619 x86_fild_membase (code, X86_ESP, 0, TRUE);
3620 /* Change precision */
3621 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3622 x86_fld_membase (code, X86_ESP, 0, TRUE);
3623 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3625 case OP_LCONV_TO_R4_2:
3626 x86_push_reg (code, ins->sreg2);
3627 x86_push_reg (code, ins->sreg1);
3628 x86_fild_membase (code, X86_ESP, 0, TRUE);
3629 /* Change precision */
3630 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3631 x86_fld_membase (code, X86_ESP, 0, FALSE);
3632 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3634 case OP_LCONV_TO_R_UN_2: {
3635 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3638 /* load 64bit integer to FP stack */
3639 x86_push_reg (code, ins->sreg2);
3640 x86_push_reg (code, ins->sreg1);
3641 x86_fild_membase (code, X86_ESP, 0, TRUE);
3643 /* test if lreg is negative */
3644 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3645 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3647 /* add correction constant mn */
3648 if (cfg->compile_aot) {
3649 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3650 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3651 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3652 x86_fld80_membase (code, X86_ESP, 2);
3653 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3655 x86_fld80_mem (code, mn);
3657 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3659 x86_patch (br, code);
3661 /* Change precision */
3662 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3663 x86_fld_membase (code, X86_ESP, 0, TRUE);
3665 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3669 case OP_LCONV_TO_OVF_I:
3670 case OP_LCONV_TO_OVF_I4_2: {
3671 guint8 *br [3], *label [1];
3675 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3677 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3679 /* If the low word top bit is set, see if we are negative */
3680 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3681 /* We are not negative (no top bit set, check for our top word to be zero */
3682 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3683 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3686 /* throw exception */
3687 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3689 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3690 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3691 x86_jump8 (code, 0);
3693 x86_jump32 (code, 0);
3695 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3696 x86_jump32 (code, 0);
3700 x86_patch (br [0], code);
3701 /* our top bit is set, check that top word is 0xfffffff */
3702 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3704 x86_patch (br [1], code);
3705 /* nope, emit exception */
3706 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3707 x86_patch (br [2], label [0]);
3709 if (ins->dreg != ins->sreg1)
3710 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3714 /* Not needed on the fp stack */
3716 case OP_MOVE_F_TO_I4:
3717 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
3718 x86_mov_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, 4);
3720 case OP_MOVE_I4_TO_F:
3721 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
3722 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
3725 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3728 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3731 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3734 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3742 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3747 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3754 * it really doesn't make sense to inline all this code,
3755 * it's here just to show that things may not be as simple
3758 guchar *check_pos, *end_tan, *pop_jump;
3759 x86_push_reg (code, X86_EAX);
3762 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3764 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3765 x86_fstp (code, 0); /* pop the 1.0 */
3767 x86_jump8 (code, 0);
3769 x86_fp_op (code, X86_FADD, 0);
3773 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3775 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3778 x86_patch (pop_jump, code);
3779 x86_fstp (code, 0); /* pop the 1.0 */
3780 x86_patch (check_pos, code);
3781 x86_patch (end_tan, code);
3783 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3784 x86_pop_reg (code, X86_EAX);
3791 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3800 g_assert (cfg->opt & MONO_OPT_CMOV);
3801 g_assert (ins->dreg == ins->sreg1);
3802 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3803 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3806 g_assert (cfg->opt & MONO_OPT_CMOV);
3807 g_assert (ins->dreg == ins->sreg1);
3808 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3809 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3812 g_assert (cfg->opt & MONO_OPT_CMOV);
3813 g_assert (ins->dreg == ins->sreg1);
3814 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3815 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3818 g_assert (cfg->opt & MONO_OPT_CMOV);
3819 g_assert (ins->dreg == ins->sreg1);
3820 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3821 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3827 x86_fxch (code, ins->inst_imm);
3832 x86_push_reg (code, X86_EAX);
3833 /* we need to exchange ST(0) with ST(1) */
3836 /* this requires a loop, because fprem somtimes
3837 * returns a partial remainder */
3839 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3840 /* x86_fprem1 (code); */
3843 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3845 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3851 x86_pop_reg (code, X86_EAX);
3855 if (cfg->opt & MONO_OPT_FCMOV) {
3856 x86_fcomip (code, 1);
3860 /* this overwrites EAX */
3861 EMIT_FPCOMPARE(code);
3862 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3866 if (cfg->opt & MONO_OPT_FCMOV) {
3867 /* zeroing the register at the start results in
3868 * shorter and faster code (we can also remove the widening op)
3870 guchar *unordered_check;
3871 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3872 x86_fcomip (code, 1);
3874 unordered_check = code;
3875 x86_branch8 (code, X86_CC_P, 0, FALSE);
3876 if (ins->opcode == OP_FCEQ) {
3877 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3878 x86_patch (unordered_check, code);
3880 guchar *jump_to_end;
3881 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3883 x86_jump8 (code, 0);
3884 x86_patch (unordered_check, code);
3885 x86_inc_reg (code, ins->dreg);
3886 x86_patch (jump_to_end, code);
3891 if (ins->dreg != X86_EAX)
3892 x86_push_reg (code, X86_EAX);
3894 EMIT_FPCOMPARE(code);
3895 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3896 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3897 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3898 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3900 if (ins->dreg != X86_EAX)
3901 x86_pop_reg (code, X86_EAX);
3905 if (cfg->opt & MONO_OPT_FCMOV) {
3906 /* zeroing the register at the start results in
3907 * shorter and faster code (we can also remove the widening op)
3909 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3910 x86_fcomip (code, 1);
3912 if (ins->opcode == OP_FCLT_UN) {
3913 guchar *unordered_check = code;
3914 guchar *jump_to_end;
3915 x86_branch8 (code, X86_CC_P, 0, FALSE);
3916 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3918 x86_jump8 (code, 0);
3919 x86_patch (unordered_check, code);
3920 x86_inc_reg (code, ins->dreg);
3921 x86_patch (jump_to_end, code);
3923 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3927 if (ins->dreg != X86_EAX)
3928 x86_push_reg (code, X86_EAX);
3930 EMIT_FPCOMPARE(code);
3931 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3932 if (ins->opcode == OP_FCLT_UN) {
3933 guchar *is_not_zero_check, *end_jump;
3934 is_not_zero_check = code;
3935 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3937 x86_jump8 (code, 0);
3938 x86_patch (is_not_zero_check, code);
3939 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3941 x86_patch (end_jump, code);
3943 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3944 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3946 if (ins->dreg != X86_EAX)
3947 x86_pop_reg (code, X86_EAX);
3950 guchar *unordered_check;
3951 guchar *jump_to_end;
3952 if (cfg->opt & MONO_OPT_FCMOV) {
3953 /* zeroing the register at the start results in
3954 * shorter and faster code (we can also remove the widening op)
3956 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3957 x86_fcomip (code, 1);
3959 unordered_check = code;
3960 x86_branch8 (code, X86_CC_P, 0, FALSE);
3961 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3962 x86_patch (unordered_check, code);
3965 if (ins->dreg != X86_EAX)
3966 x86_push_reg (code, X86_EAX);
3968 EMIT_FPCOMPARE(code);
3969 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3970 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3971 unordered_check = code;
3972 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3974 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3975 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3976 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3978 x86_jump8 (code, 0);
3979 x86_patch (unordered_check, code);
3980 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3981 x86_patch (jump_to_end, code);
3983 if (ins->dreg != X86_EAX)
3984 x86_pop_reg (code, X86_EAX);
3989 if (cfg->opt & MONO_OPT_FCMOV) {
3990 /* zeroing the register at the start results in
3991 * shorter and faster code (we can also remove the widening op)
3993 guchar *unordered_check;
3994 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3995 x86_fcomip (code, 1);
3997 if (ins->opcode == OP_FCGT) {
3998 unordered_check = code;
3999 x86_branch8 (code, X86_CC_P, 0, FALSE);
4000 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4001 x86_patch (unordered_check, code);
4003 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4007 if (ins->dreg != X86_EAX)
4008 x86_push_reg (code, X86_EAX);
4010 EMIT_FPCOMPARE(code);
4011 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4012 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4013 if (ins->opcode == OP_FCGT_UN) {
4014 guchar *is_not_zero_check, *end_jump;
4015 is_not_zero_check = code;
4016 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4018 x86_jump8 (code, 0);
4019 x86_patch (is_not_zero_check, code);
4020 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4022 x86_patch (end_jump, code);
4024 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4025 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4027 if (ins->dreg != X86_EAX)
4028 x86_pop_reg (code, X86_EAX);
4031 guchar *unordered_check;
4032 guchar *jump_to_end;
4033 if (cfg->opt & MONO_OPT_FCMOV) {
4034 /* zeroing the register at the start results in
4035 * shorter and faster code (we can also remove the widening op)
4037 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4038 x86_fcomip (code, 1);
4040 unordered_check = code;
4041 x86_branch8 (code, X86_CC_P, 0, FALSE);
4042 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4043 x86_patch (unordered_check, code);
4046 if (ins->dreg != X86_EAX)
4047 x86_push_reg (code, X86_EAX);
4049 EMIT_FPCOMPARE(code);
4050 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4051 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4052 unordered_check = code;
4053 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4055 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4056 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4057 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4059 x86_jump8 (code, 0);
4060 x86_patch (unordered_check, code);
4061 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4062 x86_patch (jump_to_end, code);
4064 if (ins->dreg != X86_EAX)
4065 x86_pop_reg (code, X86_EAX);
4069 if (cfg->opt & MONO_OPT_FCMOV) {
4070 guchar *jump = code;
4071 x86_branch8 (code, X86_CC_P, 0, TRUE);
4072 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4073 x86_patch (jump, code);
4076 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4077 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4080 /* Branch if C013 != 100 */
4081 if (cfg->opt & MONO_OPT_FCMOV) {
4082 /* branch if !ZF or (PF|CF) */
4083 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4084 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4085 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4088 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4089 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4092 if (cfg->opt & MONO_OPT_FCMOV) {
4093 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4096 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4099 if (cfg->opt & MONO_OPT_FCMOV) {
4100 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4101 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4104 if (ins->opcode == OP_FBLT_UN) {
4105 guchar *is_not_zero_check, *end_jump;
4106 is_not_zero_check = code;
4107 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4109 x86_jump8 (code, 0);
4110 x86_patch (is_not_zero_check, code);
4111 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4113 x86_patch (end_jump, code);
4115 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4119 if (cfg->opt & MONO_OPT_FCMOV) {
4120 if (ins->opcode == OP_FBGT) {
4123 /* skip branch if C1=1 */
4125 x86_branch8 (code, X86_CC_P, 0, FALSE);
4126 /* branch if (C0 | C3) = 1 */
4127 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4128 x86_patch (br1, code);
4130 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4134 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4135 if (ins->opcode == OP_FBGT_UN) {
4136 guchar *is_not_zero_check, *end_jump;
4137 is_not_zero_check = code;
4138 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4140 x86_jump8 (code, 0);
4141 x86_patch (is_not_zero_check, code);
4142 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4144 x86_patch (end_jump, code);
4146 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4149 /* Branch if C013 == 100 or 001 */
4150 if (cfg->opt & MONO_OPT_FCMOV) {
4153 /* skip branch if C1=1 */
4155 x86_branch8 (code, X86_CC_P, 0, FALSE);
4156 /* branch if (C0 | C3) = 1 */
4157 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4158 x86_patch (br1, code);
4161 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4162 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4163 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4164 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4167 /* Branch if C013 == 000 */
4168 if (cfg->opt & MONO_OPT_FCMOV) {
4169 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4172 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4175 /* Branch if C013=000 or 100 */
4176 if (cfg->opt & MONO_OPT_FCMOV) {
4179 /* skip branch if C1=1 */
4181 x86_branch8 (code, X86_CC_P, 0, FALSE);
4182 /* branch if C0=0 */
4183 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4184 x86_patch (br1, code);
4187 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4188 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4189 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4192 /* Branch if C013 != 001 */
4193 if (cfg->opt & MONO_OPT_FCMOV) {
4194 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4195 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4198 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4199 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4203 x86_push_reg (code, X86_EAX);
4206 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4207 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4208 x86_pop_reg (code, X86_EAX);
4210 /* Have to clean up the fp stack before throwing the exception */
4212 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4215 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
4217 x86_patch (br1, code);
4221 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4224 case OP_TLS_GET_REG: {
4225 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4229 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4232 case OP_TLS_SET_REG: {
4233 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4236 case OP_MEMORY_BARRIER: {
4237 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4238 x86_prefix (code, X86_LOCK_PREFIX);
4239 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4243 case OP_ATOMIC_ADD_I4: {
4244 int dreg = ins->dreg;
4246 g_assert (cfg->has_atomic_add_i4);
4248 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4249 if (ins->sreg2 == dreg) {
4250 if (dreg == X86_EBX) {
4252 if (ins->inst_basereg == X86_EDI)
4256 if (ins->inst_basereg == X86_EBX)
4259 } else if (ins->inst_basereg == dreg) {
4260 if (dreg == X86_EBX) {
4262 if (ins->sreg2 == X86_EDI)
4266 if (ins->sreg2 == X86_EBX)
4271 if (dreg != ins->dreg) {
4272 x86_push_reg (code, dreg);
4275 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4276 x86_prefix (code, X86_LOCK_PREFIX);
4277 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4278 /* dreg contains the old value, add with sreg2 value */
4279 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4281 if (ins->dreg != dreg) {
4282 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4283 x86_pop_reg (code, dreg);
4288 case OP_ATOMIC_EXCHANGE_I4: {
4290 int sreg2 = ins->sreg2;
4291 int breg = ins->inst_basereg;
4293 g_assert (cfg->has_atomic_exchange_i4);
4295 /* cmpxchg uses eax as comperand, need to make sure we can use it
4296 * hack to overcome limits in x86 reg allocator
4297 * (req: dreg == eax and sreg2 != eax and breg != eax)
4299 g_assert (ins->dreg == X86_EAX);
4301 /* We need the EAX reg for the cmpxchg */
4302 if (ins->sreg2 == X86_EAX) {
4303 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4304 x86_push_reg (code, sreg2);
4305 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4308 if (breg == X86_EAX) {
4309 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4310 x86_push_reg (code, breg);
4311 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4314 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4316 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4317 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4318 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4319 x86_patch (br [1], br [0]);
4321 if (breg != ins->inst_basereg)
4322 x86_pop_reg (code, breg);
4324 if (ins->sreg2 != sreg2)
4325 x86_pop_reg (code, sreg2);
4329 case OP_ATOMIC_CAS_I4: {
4330 g_assert (ins->dreg == X86_EAX);
4331 g_assert (ins->sreg3 == X86_EAX);
4332 g_assert (ins->sreg1 != X86_EAX);
4333 g_assert (ins->sreg1 != ins->sreg2);
4335 x86_prefix (code, X86_LOCK_PREFIX);
4336 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4339 case OP_ATOMIC_LOAD_I1: {
4340 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4343 case OP_ATOMIC_LOAD_U1: {
4344 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4347 case OP_ATOMIC_LOAD_I2: {
4348 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4351 case OP_ATOMIC_LOAD_U2: {
4352 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4355 case OP_ATOMIC_LOAD_I4:
4356 case OP_ATOMIC_LOAD_U4: {
4357 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4360 case OP_ATOMIC_LOAD_R4:
4361 case OP_ATOMIC_LOAD_R8: {
4362 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4365 case OP_ATOMIC_STORE_I1:
4366 case OP_ATOMIC_STORE_U1:
4367 case OP_ATOMIC_STORE_I2:
4368 case OP_ATOMIC_STORE_U2:
4369 case OP_ATOMIC_STORE_I4:
4370 case OP_ATOMIC_STORE_U4: {
4373 switch (ins->opcode) {
4374 case OP_ATOMIC_STORE_I1:
4375 case OP_ATOMIC_STORE_U1:
4378 case OP_ATOMIC_STORE_I2:
4379 case OP_ATOMIC_STORE_U2:
4382 case OP_ATOMIC_STORE_I4:
4383 case OP_ATOMIC_STORE_U4:
4388 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4390 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4394 case OP_ATOMIC_STORE_R4:
4395 case OP_ATOMIC_STORE_R8: {
4396 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4398 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4402 case OP_CARD_TABLE_WBARRIER: {
4403 int ptr = ins->sreg1;
4404 int value = ins->sreg2;
4406 int nursery_shift, card_table_shift;
4407 gpointer card_table_mask;
4408 size_t nursery_size;
4409 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4410 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4411 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4414 * We need one register we can clobber, we choose EDX and make sreg1
4415 * fixed EAX to work around limitations in the local register allocator.
4416 * sreg2 might get allocated to EDX, but that is not a problem since
4417 * we use it before clobbering EDX.
4419 g_assert (ins->sreg1 == X86_EAX);
4422 * This is the code we produce:
4425 * edx >>= nursery_shift
4426 * cmp edx, (nursery_start >> nursery_shift)
4429 * edx >>= card_table_shift
4430 * card_table[edx] = 1
4434 if (card_table_nursery_check) {
4435 if (value != X86_EDX)
4436 x86_mov_reg_reg (code, X86_EDX, value, 4);
4437 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4438 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4439 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4441 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4442 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4443 if (card_table_mask)
4444 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4445 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4446 if (card_table_nursery_check)
4447 x86_patch (br, code);
4450 #ifdef MONO_ARCH_SIMD_INTRINSICS
4452 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4455 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4458 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4461 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4464 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4467 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4470 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4471 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4474 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4477 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4480 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4483 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4486 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4489 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4492 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4495 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4498 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4501 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4504 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4507 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4510 case OP_PSHUFLEW_HIGH:
4511 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4512 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4514 case OP_PSHUFLEW_LOW:
4515 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4516 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4519 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4520 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4523 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4524 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4527 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4528 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4532 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4535 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4538 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4541 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4544 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4547 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4550 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4551 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4554 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4557 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4560 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4563 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4566 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4569 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4572 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4575 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4578 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4581 case OP_EXTRACT_MASK:
4582 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4586 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4589 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4592 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4596 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4599 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4602 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4605 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4609 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4612 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4615 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4618 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4622 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4625 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4628 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4632 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4635 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4638 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4642 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4645 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4649 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4652 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4655 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4659 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4662 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4665 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4669 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4672 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4675 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4678 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4682 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4685 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4688 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4691 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4694 case OP_PSUM_ABS_DIFF:
4695 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4698 case OP_UNPACK_LOWB:
4699 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4701 case OP_UNPACK_LOWW:
4702 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4704 case OP_UNPACK_LOWD:
4705 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4707 case OP_UNPACK_LOWQ:
4708 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4710 case OP_UNPACK_LOWPS:
4711 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4713 case OP_UNPACK_LOWPD:
4714 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4717 case OP_UNPACK_HIGHB:
4718 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4720 case OP_UNPACK_HIGHW:
4721 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4723 case OP_UNPACK_HIGHD:
4724 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4726 case OP_UNPACK_HIGHQ:
4727 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4729 case OP_UNPACK_HIGHPS:
4730 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4732 case OP_UNPACK_HIGHPD:
4733 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4737 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4740 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4743 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4746 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4749 case OP_PADDB_SAT_UN:
4750 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4752 case OP_PSUBB_SAT_UN:
4753 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4755 case OP_PADDW_SAT_UN:
4756 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4758 case OP_PSUBW_SAT_UN:
4759 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4763 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4766 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4769 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4772 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4776 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4779 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4782 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4784 case OP_PMULW_HIGH_UN:
4785 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4788 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4792 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4795 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4799 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4802 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4806 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4809 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4813 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4816 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4820 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4823 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4827 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4830 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4834 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4837 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4841 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4844 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4848 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4851 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4855 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4857 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4858 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4862 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4864 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4865 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4869 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4871 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4872 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4876 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4878 case OP_EXTRACTX_U2:
4879 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4881 case OP_INSERTX_U1_SLOW:
4882 /*sreg1 is the extracted ireg (scratch)
4883 /sreg2 is the to be inserted ireg (scratch)
4884 /dreg is the xreg to receive the value*/
4886 /*clear the bits from the extracted word*/
4887 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4888 /*shift the value to insert if needed*/
4889 if (ins->inst_c0 & 1)
4890 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4891 /*join them together*/
4892 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4893 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4895 case OP_INSERTX_I4_SLOW:
4896 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4897 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4898 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4901 case OP_INSERTX_R4_SLOW:
4902 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4903 /*TODO if inst_c0 == 0 use movss*/
4904 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4905 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4907 case OP_INSERTX_R8_SLOW:
4908 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4909 if (cfg->verbose_level)
4910 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4912 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4914 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4917 case OP_STOREX_MEMBASE_REG:
4918 case OP_STOREX_MEMBASE:
4919 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4921 case OP_LOADX_MEMBASE:
4922 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4924 case OP_LOADX_ALIGNED_MEMBASE:
4925 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4927 case OP_STOREX_ALIGNED_MEMBASE_REG:
4928 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4930 case OP_STOREX_NTA_MEMBASE_REG:
4931 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4933 case OP_PREFETCH_MEMBASE:
4934 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4938 /*FIXME the peephole pass should have killed this*/
4939 if (ins->dreg != ins->sreg1)
4940 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4943 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4946 case OP_FCONV_TO_R8_X:
4947 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4948 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4951 case OP_XCONV_R8_TO_I4:
4952 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4953 switch (ins->backend.source_opcode) {
4954 case OP_FCONV_TO_I1:
4955 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4957 case OP_FCONV_TO_U1:
4958 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4960 case OP_FCONV_TO_I2:
4961 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4963 case OP_FCONV_TO_U2:
4964 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4970 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4971 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4972 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4973 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4974 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4975 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4978 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4979 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4980 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4983 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4984 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4987 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4988 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4989 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4992 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4993 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4994 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4998 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
5001 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
5004 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
5007 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
5010 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
5013 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
5016 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
5019 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
5023 case OP_LIVERANGE_START: {
5024 if (cfg->verbose_level > 1)
5025 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5026 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5029 case OP_LIVERANGE_END: {
5030 if (cfg->verbose_level > 1)
5031 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5032 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5035 case OP_GC_SAFE_POINT: {
5036 const char *polling_func = NULL;
5037 int compare_val = 0;
5040 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
5041 polling_func = "mono_nacl_gc";
5042 compare_val = 0xFFFFFFFF;
5044 g_assert (mono_threads_is_coop_enabled ());
5045 polling_func = "mono_threads_state_poll";
5049 x86_test_membase_imm (code, ins->sreg1, 0, compare_val);
5050 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
5051 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
5052 x86_patch (br [0], code);
5056 case OP_GC_LIVENESS_DEF:
5057 case OP_GC_LIVENESS_USE:
5058 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5059 ins->backend.pc_offset = code - cfg->native_code;
5061 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5062 ins->backend.pc_offset = code - cfg->native_code;
5063 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5066 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
5069 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
5072 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
5073 g_assert_not_reached ();
5076 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
5077 #ifndef __native_client_codegen__
5078 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5079 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5080 g_assert_not_reached ();
5081 #endif /* __native_client_codegen__ */
5087 cfg->code_len = code - cfg->native_code;
5090 #endif /* DISABLE_JIT */
5093 mono_arch_register_lowlevel_calls (void)
5098 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5100 unsigned char *ip = ji->ip.i + code;
5103 case MONO_PATCH_INFO_IP:
5104 *((gconstpointer *)(ip)) = target;
5106 case MONO_PATCH_INFO_ABS:
5107 case MONO_PATCH_INFO_METHOD:
5108 case MONO_PATCH_INFO_METHOD_JUMP:
5109 case MONO_PATCH_INFO_INTERNAL_METHOD:
5110 case MONO_PATCH_INFO_BB:
5111 case MONO_PATCH_INFO_LABEL:
5112 case MONO_PATCH_INFO_RGCTX_FETCH:
5113 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5114 #if defined(__native_client_codegen__) && defined(__native_client__)
5115 if (nacl_is_code_address (code)) {
5116 /* For tail calls, code is patched after being installed */
5117 /* but not through the normal "patch callsite" method. */
5118 unsigned char buf[kNaClAlignment];
5119 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5120 unsigned char *_target = target;
5122 /* All patch targets modified in x86_patch */
5123 /* are IP relative. */
5124 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5125 memcpy (buf, aligned_code, kNaClAlignment);
5126 /* Patch a temp buffer of bundle size, */
5127 /* then install to actual location. */
5128 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5129 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5130 g_assert (ret == 0);
5133 x86_patch (ip, (unsigned char*)target);
5136 x86_patch (ip, (unsigned char*)target);
5139 case MONO_PATCH_INFO_NONE:
5141 case MONO_PATCH_INFO_R4:
5142 case MONO_PATCH_INFO_R8: {
5143 guint32 offset = mono_arch_get_patch_offset (ip);
5144 *((gconstpointer *)(ip + offset)) = target;
5148 guint32 offset = mono_arch_get_patch_offset (ip);
5149 #if !defined(__native_client__)
5150 *((gconstpointer *)(ip + offset)) = target;
5152 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5159 static G_GNUC_UNUSED void
5160 stack_unaligned (MonoMethod *m, gpointer caller)
5162 printf ("%s\n", mono_method_full_name (m, TRUE));
5163 g_assert_not_reached ();
5167 mono_arch_emit_prolog (MonoCompile *cfg)
5169 MonoMethod *method = cfg->method;
5171 MonoMethodSignature *sig;
5173 int alloc_size, pos, max_offset, i, cfa_offset;
5175 gboolean need_stack_frame;
5176 #ifdef __native_client_codegen__
5177 guint alignment_check;
5180 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5182 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5183 cfg->code_size += 512;
5185 #if defined(__default_codegen__)
5186 code = cfg->native_code = g_malloc (cfg->code_size);
5187 #elif defined(__native_client_codegen__)
5188 /* native_code_alloc is not 32-byte aligned, native_code is. */
5189 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5190 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5192 /* Align native_code to next nearest kNaclAlignment byte. */
5193 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5194 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5196 code = cfg->native_code;
5198 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5199 g_assert(alignment_check == 0);
5206 /* Check that the stack is aligned on osx */
5207 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5208 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5209 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5211 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5212 x86_push_membase (code, X86_ESP, 0);
5213 x86_push_imm (code, cfg->method);
5214 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5215 x86_call_reg (code, X86_EAX);
5216 x86_patch (br [0], code);
5220 /* Offset between RSP and the CFA */
5224 cfa_offset = sizeof (gpointer);
5225 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5226 // IP saved at CFA - 4
5227 /* There is no IP reg on x86 */
5228 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5229 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5231 need_stack_frame = needs_stack_frame (cfg);
5233 if (need_stack_frame) {
5234 x86_push_reg (code, X86_EBP);
5235 cfa_offset += sizeof (gpointer);
5236 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5237 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5238 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5239 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5240 /* These are handled automatically by the stack marking code */
5241 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5243 cfg->frame_reg = X86_ESP;
5246 cfg->stack_offset += cfg->param_area;
5247 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5249 alloc_size = cfg->stack_offset;
5252 if (!method->save_lmf) {
5253 if (cfg->used_int_regs & (1 << X86_EBX)) {
5254 x86_push_reg (code, X86_EBX);
5256 cfa_offset += sizeof (gpointer);
5257 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5258 /* These are handled automatically by the stack marking code */
5259 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5262 if (cfg->used_int_regs & (1 << X86_EDI)) {
5263 x86_push_reg (code, X86_EDI);
5265 cfa_offset += sizeof (gpointer);
5266 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5267 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5270 if (cfg->used_int_regs & (1 << X86_ESI)) {
5271 x86_push_reg (code, X86_ESI);
5273 cfa_offset += sizeof (gpointer);
5274 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5275 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5281 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5282 if (mono_do_x86_stack_align && need_stack_frame) {
5283 int tot = alloc_size + pos + 4; /* ret ip */
5284 if (need_stack_frame)
5286 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5288 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5289 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5290 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5294 cfg->arch.sp_fp_offset = alloc_size + pos;
5297 /* See mono_emit_stack_alloc */
5298 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5299 guint32 remaining_size = alloc_size;
5300 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5301 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5302 guint32 offset = code - cfg->native_code;
5303 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5304 while (required_code_size >= (cfg->code_size - offset))
5305 cfg->code_size *= 2;
5306 cfg->native_code = mono_realloc_native_code(cfg);
5307 code = cfg->native_code + offset;
5308 cfg->stat_code_reallocs++;
5310 while (remaining_size >= 0x1000) {
5311 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5312 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5313 remaining_size -= 0x1000;
5316 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5318 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5321 g_assert (need_stack_frame);
5324 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5325 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5326 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5329 #if DEBUG_STACK_ALIGNMENT
5330 /* check the stack is aligned */
5331 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5332 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5333 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5334 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5335 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5336 x86_breakpoint (code);
5340 /* compute max_offset in order to use short forward jumps */
5342 if (cfg->opt & MONO_OPT_BRANCH) {
5343 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5345 bb->max_offset = max_offset;
5347 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5349 /* max alignment for loops */
5350 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5351 max_offset += LOOP_ALIGNMENT;
5352 #ifdef __native_client_codegen__
5353 /* max alignment for native client */
5354 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5355 max_offset += kNaClAlignment;
5357 MONO_BB_FOR_EACH_INS (bb, ins) {
5358 if (ins->opcode == OP_LABEL)
5359 ins->inst_c1 = max_offset;
5360 #ifdef __native_client_codegen__
5361 switch (ins->opcode)
5373 case OP_VOIDCALL_REG:
5375 case OP_FCALL_MEMBASE:
5376 case OP_LCALL_MEMBASE:
5377 case OP_VCALL_MEMBASE:
5378 case OP_VCALL2_MEMBASE:
5379 case OP_VOIDCALL_MEMBASE:
5380 case OP_CALL_MEMBASE:
5381 max_offset += kNaClAlignment;
5384 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5387 #endif /* __native_client_codegen__ */
5388 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5393 /* store runtime generic context */
5394 if (cfg->rgctx_var) {
5395 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5397 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5400 if (method->save_lmf)
5401 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5403 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5404 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5409 if (cfg->arch.ss_tramp_var) {
5410 /* Initialize ss_tramp_var */
5411 ins = cfg->arch.ss_tramp_var;
5412 g_assert (ins->opcode == OP_REGOFFSET);
5414 g_assert (!cfg->compile_aot);
5415 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&ss_trampoline, 4);
5418 if (cfg->arch.bp_tramp_var) {
5419 /* Initialize bp_tramp_var */
5420 ins = cfg->arch.bp_tramp_var;
5421 g_assert (ins->opcode == OP_REGOFFSET);
5423 g_assert (!cfg->compile_aot);
5424 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&bp_trampoline, 4);
5428 /* load arguments allocated to register from the stack */
5429 sig = mono_method_signature (method);
5432 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5433 inst = cfg->args [pos];
5434 if (inst->opcode == OP_REGVAR) {
5435 g_assert (need_stack_frame);
5436 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5437 if (cfg->verbose_level > 2)
5438 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5443 cfg->code_len = code - cfg->native_code;
5445 g_assert (cfg->code_len < cfg->code_size);
5451 mono_arch_emit_epilog (MonoCompile *cfg)
5453 MonoMethod *method = cfg->method;
5454 MonoMethodSignature *sig = mono_method_signature (method);
5456 guint32 stack_to_pop;
5458 int max_epilog_size = 16;
5460 gboolean need_stack_frame = needs_stack_frame (cfg);
5462 if (cfg->method->save_lmf)
5463 max_epilog_size += 128;
5465 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5466 cfg->code_size *= 2;
5467 cfg->native_code = mono_realloc_native_code(cfg);
5468 cfg->stat_code_reallocs++;
5471 code = cfg->native_code + cfg->code_len;
5473 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5474 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5476 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5479 if (method->save_lmf) {
5480 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5482 gboolean supported = FALSE;
5484 if (cfg->compile_aot) {
5485 #if defined(MONO_HAVE_FAST_TLS)
5488 } else if (mono_get_jit_tls_offset () != -1) {
5492 /* check if we need to restore protection of the stack after a stack overflow */
5494 if (cfg->compile_aot) {
5495 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5497 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5499 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5502 /* we load the value in a separate instruction: this mechanism may be
5503 * used later as a safer way to do thread interruption
5505 x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5506 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5508 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5509 /* note that the call trampoline will preserve eax/edx */
5510 x86_call_reg (code, X86_ECX);
5511 x86_patch (patch, code);
5513 /* FIXME: maybe save the jit tls in the prolog */
5516 /* restore caller saved regs */
5517 if (cfg->used_int_regs & (1 << X86_EBX)) {
5518 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5521 if (cfg->used_int_regs & (1 << X86_EDI)) {
5522 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5524 if (cfg->used_int_regs & (1 << X86_ESI)) {
5525 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5528 /* EBP is restored by LEAVE */
5530 for (i = 0; i < X86_NREG; ++i) {
5531 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5537 g_assert (need_stack_frame);
5538 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5542 g_assert (need_stack_frame);
5543 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5546 if (cfg->used_int_regs & (1 << X86_ESI)) {
5547 x86_pop_reg (code, X86_ESI);
5549 if (cfg->used_int_regs & (1 << X86_EDI)) {
5550 x86_pop_reg (code, X86_EDI);
5552 if (cfg->used_int_regs & (1 << X86_EBX)) {
5553 x86_pop_reg (code, X86_EBX);
5557 /* Load returned vtypes into registers if needed */
5558 cinfo = get_call_info (cfg->mempool, sig);
5559 if (cinfo->ret.storage == ArgValuetypeInReg) {
5560 for (quad = 0; quad < 2; quad ++) {
5561 switch (cinfo->ret.pair_storage [quad]) {
5563 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5565 case ArgOnFloatFpStack:
5566 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5568 case ArgOnDoubleFpStack:
5569 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5574 g_assert_not_reached ();
5579 if (need_stack_frame)
5582 if (CALLCONV_IS_STDCALL (sig)) {
5583 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5585 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
5586 } else if (cinfo->callee_stack_pop)
5587 stack_to_pop = cinfo->callee_stack_pop;
5592 g_assert (need_stack_frame);
5593 x86_ret_imm (code, stack_to_pop);
5598 cfg->code_len = code - cfg->native_code;
5600 g_assert (cfg->code_len < cfg->code_size);
5604 mono_arch_emit_exceptions (MonoCompile *cfg)
5606 MonoJumpInfo *patch_info;
5609 MonoClass *exc_classes [16];
5610 guint8 *exc_throw_start [16], *exc_throw_end [16];
5614 /* Compute needed space */
5615 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5616 if (patch_info->type == MONO_PATCH_INFO_EXC)
5621 * make sure we have enough space for exceptions
5622 * 16 is the size of two push_imm instructions and a call
5624 if (cfg->compile_aot)
5625 code_size = exc_count * 32;
5627 code_size = exc_count * 16;
5629 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5630 cfg->code_size *= 2;
5631 cfg->native_code = mono_realloc_native_code(cfg);
5632 cfg->stat_code_reallocs++;
5635 code = cfg->native_code + cfg->code_len;
5638 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5639 switch (patch_info->type) {
5640 case MONO_PATCH_INFO_EXC: {
5641 MonoClass *exc_class;
5645 x86_patch (patch_info->ip.i + cfg->native_code, code);
5647 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5648 throw_ip = patch_info->ip.i;
5650 /* Find a throw sequence for the same exception class */
5651 for (i = 0; i < nthrows; ++i)
5652 if (exc_classes [i] == exc_class)
5655 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5656 x86_jump_code (code, exc_throw_start [i]);
5657 patch_info->type = MONO_PATCH_INFO_NONE;
5662 /* Compute size of code following the push <OFFSET> */
5663 #if defined(__default_codegen__)
5665 #elif defined(__native_client_codegen__)
5666 code = mono_nacl_align (code);
5667 size = kNaClAlignment;
5669 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5671 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5672 /* Use the shorter form */
5674 x86_push_imm (code, 0);
5678 x86_push_imm (code, 0xf0f0f0f0);
5683 exc_classes [nthrows] = exc_class;
5684 exc_throw_start [nthrows] = code;
5687 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5688 patch_info->data.name = "mono_arch_throw_corlib_exception";
5689 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5690 patch_info->ip.i = code - cfg->native_code;
5691 x86_call_code (code, 0);
5692 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5697 exc_throw_end [nthrows] = code;
5709 cfg->code_len = code - cfg->native_code;
5711 g_assert (cfg->code_len < cfg->code_size);
5715 mono_arch_flush_icache (guint8 *code, gint size)
5721 mono_arch_flush_register_windows (void)
5726 mono_arch_is_inst_imm (gint64 imm)
5732 mono_arch_finish_init (void)
5734 if (!g_getenv ("MONO_NO_TLS")) {
5735 #ifndef TARGET_WIN32
5737 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5744 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5748 // Linear handler, the bsearch head compare is shorter
5749 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5750 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5751 // x86_patch(ins,target)
5752 //[1 + 5] x86_jump_mem(inst,mem)
5755 #if defined(__default_codegen__)
5756 #define BR_SMALL_SIZE 2
5757 #define BR_LARGE_SIZE 5
5758 #elif defined(__native_client_codegen__)
5759 /* I suspect the size calculation below is actually incorrect. */
5760 /* TODO: fix the calculation that uses these sizes. */
5761 #define BR_SMALL_SIZE 16
5762 #define BR_LARGE_SIZE 12
5763 #endif /*__native_client_codegen__*/
5764 #define JUMP_IMM_SIZE 6
5765 #define ENABLE_WRONG_METHOD_CHECK 0
5769 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5771 int i, distance = 0;
5772 for (i = start; i < target; ++i)
5773 distance += imt_entries [i]->chunk_size;
5778 * LOCKING: called with the domain lock held
5781 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5782 gpointer fail_tramp)
5786 guint8 *code, *start;
5789 for (i = 0; i < count; ++i) {
5790 MonoIMTCheckItem *item = imt_entries [i];
5791 if (item->is_equals) {
5792 if (item->check_target_idx) {
5793 if (!item->compare_done)
5794 item->chunk_size += CMP_SIZE;
5795 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5798 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5800 item->chunk_size += JUMP_IMM_SIZE;
5801 #if ENABLE_WRONG_METHOD_CHECK
5802 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5807 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5808 imt_entries [item->check_target_idx]->compare_done = TRUE;
5810 size += item->chunk_size;
5812 #if defined(__native_client__) && defined(__native_client_codegen__)
5813 /* In Native Client, we don't re-use thunks, allocate from the */
5814 /* normal code manager paths. */
5815 size = NACL_BUNDLE_ALIGN_UP (size);
5816 code = mono_domain_code_reserve (domain, size);
5819 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5821 code = mono_domain_code_reserve (domain, size);
5825 unwind_ops = mono_arch_get_cie_program ();
5827 for (i = 0; i < count; ++i) {
5828 MonoIMTCheckItem *item = imt_entries [i];
5829 item->code_target = code;
5830 if (item->is_equals) {
5831 if (item->check_target_idx) {
5832 if (!item->compare_done)
5833 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5834 item->jmp_code = code;
5835 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5836 if (item->has_target_code)
5837 x86_jump_code (code, item->value.target_code);
5839 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5842 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5843 item->jmp_code = code;
5844 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5845 if (item->has_target_code)
5846 x86_jump_code (code, item->value.target_code);
5848 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5849 x86_patch (item->jmp_code, code);
5850 x86_jump_code (code, fail_tramp);
5851 item->jmp_code = NULL;
5853 /* enable the commented code to assert on wrong method */
5854 #if ENABLE_WRONG_METHOD_CHECK
5855 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5856 item->jmp_code = code;
5857 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5859 if (item->has_target_code)
5860 x86_jump_code (code, item->value.target_code);
5862 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5863 #if ENABLE_WRONG_METHOD_CHECK
5864 x86_patch (item->jmp_code, code);
5865 x86_breakpoint (code);
5866 item->jmp_code = NULL;
5871 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5872 item->jmp_code = code;
5873 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5874 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5876 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5879 /* patch the branches to get to the target items */
5880 for (i = 0; i < count; ++i) {
5881 MonoIMTCheckItem *item = imt_entries [i];
5882 if (item->jmp_code) {
5883 if (item->check_target_idx) {
5884 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5890 mono_stats.imt_thunks_size += code - start;
5891 g_assert (code - start <= size);
5895 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5896 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5900 if (mono_jit_map_is_enabled ()) {
5903 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5905 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5906 mono_emit_jit_tramp (start, code - start, buff);
5910 nacl_domain_code_validate (domain, &start, size, &code);
5911 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
5913 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
5919 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5921 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5925 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5927 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5931 mono_arch_get_cie_program (void)
5935 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5936 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5942 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5944 MonoInst *ins = NULL;
5947 if (cmethod->klass == mono_defaults.math_class) {
5948 if (strcmp (cmethod->name, "Sin") == 0) {
5950 } else if (strcmp (cmethod->name, "Cos") == 0) {
5952 } else if (strcmp (cmethod->name, "Tan") == 0) {
5954 } else if (strcmp (cmethod->name, "Atan") == 0) {
5956 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5958 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5960 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5964 if (opcode && fsig->param_count == 1) {
5965 MONO_INST_NEW (cfg, ins, opcode);
5966 ins->type = STACK_R8;
5967 ins->dreg = mono_alloc_freg (cfg);
5968 ins->sreg1 = args [0]->dreg;
5969 MONO_ADD_INS (cfg->cbb, ins);
5972 if (cfg->opt & MONO_OPT_CMOV) {
5975 if (strcmp (cmethod->name, "Min") == 0) {
5976 if (fsig->params [0]->type == MONO_TYPE_I4)
5978 } else if (strcmp (cmethod->name, "Max") == 0) {
5979 if (fsig->params [0]->type == MONO_TYPE_I4)
5983 if (opcode && fsig->param_count == 2) {
5984 MONO_INST_NEW (cfg, ins, opcode);
5985 ins->type = STACK_I4;
5986 ins->dreg = mono_alloc_ireg (cfg);
5987 ins->sreg1 = args [0]->dreg;
5988 ins->sreg2 = args [1]->dreg;
5989 MONO_ADD_INS (cfg->cbb, ins);
5994 /* OP_FREM is not IEEE compatible */
5995 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
5996 MONO_INST_NEW (cfg, ins, OP_FREM);
5997 ins->inst_i0 = args [0];
5998 ins->inst_i1 = args [1];
6007 mono_arch_print_tree (MonoInst *tree, int arity)
6013 mono_arch_get_patch_offset (guint8 *code)
6015 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
6017 else if (code [0] == 0xba)
6019 else if (code [0] == 0x68)
6022 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
6023 /* push <OFFSET>(<REG>) */
6025 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
6026 /* call *<OFFSET>(<REG>) */
6028 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
6031 else if ((code [0] == 0x58) && (code [1] == 0x05))
6032 /* pop %eax; add <OFFSET>, %eax */
6034 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6035 /* pop <REG>; add <OFFSET>, <REG> */
6037 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6038 /* mov <REG>, imm */
6041 g_assert_not_reached ();
6047 * mono_breakpoint_clean_code:
6049 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6050 * breakpoints in the original code, they are removed in the copy.
6052 * Returns TRUE if no sw breakpoint was present.
6055 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6058 * If method_start is non-NULL we need to perform bound checks, since we access memory
6059 * at code - offset we could go before the start of the method and end up in a different
6060 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6063 if (!method_start || code - offset >= method_start) {
6064 memcpy (buf, code - offset, size);
6066 int diff = code - method_start;
6067 memset (buf, 0, size);
6068 memcpy (buf + offset - diff, method_start, diff + size - offset);
6074 * mono_x86_get_this_arg_offset:
6076 * Return the offset of the stack location where this is passed during a virtual
6080 mono_x86_get_this_arg_offset (MonoMethodSignature *sig)
6086 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6088 guint32 esp = regs [X86_ESP];
6095 * The stack looks like:
6099 res = ((MonoObject**)esp) [0];
6103 #define MAX_ARCH_DELEGATE_PARAMS 10
6106 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
6108 guint8 *code, *start;
6109 int code_reserve = 64;
6112 unwind_ops = mono_arch_get_cie_program ();
6115 * The stack contains:
6121 start = code = mono_global_codeman_reserve (code_reserve);
6123 /* Replace the this argument with the target */
6124 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6125 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6126 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6127 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6129 g_assert ((code - start) < code_reserve);
6132 /* 8 for mov_reg and jump, plus 8 for each parameter */
6133 #ifdef __native_client_codegen__
6134 /* TODO: calculate this size correctly */
6135 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6137 code_reserve = 8 + (param_count * 8);
6138 #endif /* __native_client_codegen__ */
6140 * The stack contains:
6141 * <args in reverse order>
6146 * <args in reverse order>
6149 * without unbalancing the stack.
6150 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6151 * and leaving original spot of first arg as placeholder in stack so
6152 * when callee pops stack everything works.
6155 start = code = mono_global_codeman_reserve (code_reserve);
6157 /* store delegate for access to method_ptr */
6158 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6161 for (i = 0; i < param_count; ++i) {
6162 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6163 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6166 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6168 g_assert ((code - start) < code_reserve);
6171 nacl_global_codeman_validate (&start, code_reserve, &code);
6174 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
6176 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
6177 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
6181 if (mono_jit_map_is_enabled ()) {
6184 buff = (char*)"delegate_invoke_has_target";
6186 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6187 mono_emit_jit_tramp (start, code - start, buff);
6191 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6196 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
6199 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
6201 guint8 *code, *start;
6206 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
6210 * The stack contains:
6214 start = code = mono_global_codeman_reserve (size);
6216 unwind_ops = mono_arch_get_cie_program ();
6218 /* Replace the this argument with the target */
6219 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6220 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6221 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6224 /* Load the IMT reg */
6225 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
6228 /* Load the vtable */
6229 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
6230 x86_jump_membase (code, X86_EAX, offset);
6231 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6234 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
6236 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
6237 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
6238 g_free (tramp_name);
6245 mono_arch_get_delegate_invoke_impls (void)
6248 MonoTrampInfo *info;
6251 get_delegate_invoke_impl (&info, TRUE, 0);
6252 res = g_slist_prepend (res, info);
6254 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
6255 get_delegate_invoke_impl (&info, FALSE, i);
6256 res = g_slist_prepend (res, info);
6259 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
6260 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
6261 res = g_slist_prepend (res, info);
6263 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
6264 res = g_slist_prepend (res, info);
6271 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6273 guint8 *code, *start;
6275 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6278 /* FIXME: Support more cases */
6279 if (MONO_TYPE_ISSTRUCT (sig->ret))
6283 * The stack contains:
6289 static guint8* cached = NULL;
6293 if (mono_aot_only) {
6294 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6296 MonoTrampInfo *info;
6297 start = get_delegate_invoke_impl (&info, TRUE, 0);
6298 mono_tramp_info_register (info, NULL);
6301 mono_memory_barrier ();
6305 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6308 for (i = 0; i < sig->param_count; ++i)
6309 if (!mono_is_regsize_var (sig->params [i]))
6312 code = cache [sig->param_count];
6316 if (mono_aot_only) {
6317 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6318 start = mono_aot_get_trampoline (name);
6321 MonoTrampInfo *info;
6322 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
6323 mono_tramp_info_register (info, NULL);
6326 mono_memory_barrier ();
6328 cache [sig->param_count] = start;
6335 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
6337 MonoTrampInfo *info;
6340 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
6342 mono_tramp_info_register (info, NULL);
6347 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6350 case X86_EAX: return ctx->eax;
6351 case X86_EBX: return ctx->ebx;
6352 case X86_ECX: return ctx->ecx;
6353 case X86_EDX: return ctx->edx;
6354 case X86_ESP: return ctx->esp;
6355 case X86_EBP: return ctx->ebp;
6356 case X86_ESI: return ctx->esi;
6357 case X86_EDI: return ctx->edi;
6359 g_assert_not_reached ();
6365 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6393 g_assert_not_reached ();
6397 #ifdef MONO_ARCH_SIMD_INTRINSICS
6400 get_float_to_x_spill_area (MonoCompile *cfg)
6402 if (!cfg->fconv_to_r8_x_var) {
6403 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6404 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6406 return cfg->fconv_to_r8_x_var;
6410 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6413 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6416 int dreg, src_opcode;
6418 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6421 switch (src_opcode = ins->opcode) {
6422 case OP_FCONV_TO_I1:
6423 case OP_FCONV_TO_U1:
6424 case OP_FCONV_TO_I2:
6425 case OP_FCONV_TO_U2:
6426 case OP_FCONV_TO_I4:
6433 /* dreg is the IREG and sreg1 is the FREG */
6434 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6435 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6436 fconv->sreg1 = ins->sreg1;
6437 fconv->dreg = mono_alloc_ireg (cfg);
6438 fconv->type = STACK_VTYPE;
6439 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6441 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6445 ins->opcode = OP_XCONV_R8_TO_I4;
6447 ins->klass = mono_defaults.int32_class;
6448 ins->sreg1 = fconv->dreg;
6450 ins->type = STACK_I4;
6451 ins->backend.source_opcode = src_opcode;
6454 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6457 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6462 if (long_ins->opcode == OP_LNEG) {
6464 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
6465 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
6466 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->dreg));
6471 #ifdef MONO_ARCH_SIMD_INTRINSICS
6473 if (!(cfg->opt & MONO_OPT_SIMD))
6476 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6477 switch (long_ins->opcode) {
6479 vreg = long_ins->sreg1;
6481 if (long_ins->inst_c0) {
6482 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6483 ins->klass = long_ins->klass;
6484 ins->sreg1 = long_ins->sreg1;
6486 ins->type = STACK_VTYPE;
6487 ins->dreg = vreg = alloc_ireg (cfg);
6488 MONO_ADD_INS (cfg->cbb, ins);
6491 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6492 ins->klass = mono_defaults.int32_class;
6494 ins->type = STACK_I4;
6495 ins->dreg = MONO_LVREG_LS (long_ins->dreg);
6496 MONO_ADD_INS (cfg->cbb, ins);
6498 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6499 ins->klass = long_ins->klass;
6500 ins->sreg1 = long_ins->sreg1;
6501 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6502 ins->type = STACK_VTYPE;
6503 ins->dreg = vreg = alloc_ireg (cfg);
6504 MONO_ADD_INS (cfg->cbb, ins);
6506 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6507 ins->klass = mono_defaults.int32_class;
6509 ins->type = STACK_I4;
6510 ins->dreg = MONO_LVREG_MS (long_ins->dreg);
6511 MONO_ADD_INS (cfg->cbb, ins);
6513 long_ins->opcode = OP_NOP;
6515 case OP_INSERTX_I8_SLOW:
6516 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6517 ins->dreg = long_ins->dreg;
6518 ins->sreg1 = long_ins->dreg;
6519 ins->sreg2 = MONO_LVREG_LS (long_ins->sreg2);
6520 ins->inst_c0 = long_ins->inst_c0 * 2;
6521 MONO_ADD_INS (cfg->cbb, ins);
6523 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6524 ins->dreg = long_ins->dreg;
6525 ins->sreg1 = long_ins->dreg;
6526 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg2);
6527 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6528 MONO_ADD_INS (cfg->cbb, ins);
6530 long_ins->opcode = OP_NOP;
6533 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6534 ins->dreg = long_ins->dreg;
6535 ins->sreg1 = MONO_LVREG_LS (long_ins->sreg1);
6536 ins->klass = long_ins->klass;
6537 ins->type = STACK_VTYPE;
6538 MONO_ADD_INS (cfg->cbb, ins);
6540 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6541 ins->dreg = long_ins->dreg;
6542 ins->sreg1 = long_ins->dreg;
6543 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg1);
6545 ins->klass = long_ins->klass;
6546 ins->type = STACK_VTYPE;
6547 MONO_ADD_INS (cfg->cbb, ins);
6549 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6550 ins->dreg = long_ins->dreg;
6551 ins->sreg1 = long_ins->dreg;;
6552 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6553 ins->klass = long_ins->klass;
6554 ins->type = STACK_VTYPE;
6555 MONO_ADD_INS (cfg->cbb, ins);
6557 long_ins->opcode = OP_NOP;
6560 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6563 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6565 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6568 gpointer *sp, old_value;
6571 offset = clause->exvar_offset;
6574 bp = MONO_CONTEXT_GET_BP (ctx);
6575 sp = *(gpointer*)(bp + offset);
6578 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6587 * mono_aot_emit_load_got_addr:
6589 * Emit code to load the got address.
6590 * On x86, the result is placed into EBX.
6593 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6595 x86_call_imm (code, 0);
6597 * The patch needs to point to the pop, since the GOT offset needs
6598 * to be added to that address.
6601 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6603 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6604 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6605 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6611 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6614 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6616 g_assert_not_reached ();
6617 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6622 * mono_arch_emit_load_aotconst:
6624 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6625 * TARGET from the mscorlib GOT in full-aot code.
6626 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6630 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
6632 /* Load the mscorlib got address */
6633 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6634 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6635 /* arch_emit_got_access () patches this */
6636 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6641 /* Can't put this into mini-x86.h */
6643 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6646 mono_arch_get_trampolines (gboolean aot)
6648 MonoTrampInfo *info;
6649 GSList *tramps = NULL;
6651 mono_x86_get_signal_exception_trampoline (&info, aot);
6653 tramps = g_slist_append (tramps, info);
6658 /* Soft Debug support */
6659 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6662 * mono_arch_set_breakpoint:
6664 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6665 * The location should contain code emitted by OP_SEQ_POINT.
6668 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6670 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6672 g_assert (code [0] == 0x90);
6673 x86_call_membase (code, X86_ECX, 0);
6677 * mono_arch_clear_breakpoint:
6679 * Clear the breakpoint at IP.
6682 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6684 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6687 for (i = 0; i < 2; ++i)
6692 * mono_arch_start_single_stepping:
6694 * Start single stepping.
6697 mono_arch_start_single_stepping (void)
6699 ss_trampoline = mini_get_single_step_trampoline ();
6703 * mono_arch_stop_single_stepping:
6705 * Stop single stepping.
6708 mono_arch_stop_single_stepping (void)
6710 ss_trampoline = NULL;
6714 * mono_arch_is_single_step_event:
6716 * Return whenever the machine state in SIGCTX corresponds to a single
6720 mono_arch_is_single_step_event (void *info, void *sigctx)
6722 /* We use soft breakpoints */
6727 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6729 /* We use soft breakpoints */
6733 #define BREAKPOINT_SIZE 2
6736 * mono_arch_skip_breakpoint:
6738 * See mini-amd64.c for docs.
6741 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6743 g_assert_not_reached ();
6747 * mono_arch_skip_single_step:
6749 * See mini-amd64.c for docs.
6752 mono_arch_skip_single_step (MonoContext *ctx)
6754 g_assert_not_reached ();
6758 * mono_arch_get_seq_point_info:
6760 * See mini-amd64.c for docs.
6763 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6770 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6772 ext->lmf.previous_lmf = (gsize)prev_lmf;
6773 /* Mark that this is a MonoLMFExt */
6774 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6775 ext->lmf.ebp = (gssize)ext;
6781 mono_arch_opcode_supported (int opcode)
6784 case OP_ATOMIC_ADD_I4:
6785 case OP_ATOMIC_EXCHANGE_I4:
6786 case OP_ATOMIC_CAS_I4:
6787 case OP_ATOMIC_LOAD_I1:
6788 case OP_ATOMIC_LOAD_I2:
6789 case OP_ATOMIC_LOAD_I4:
6790 case OP_ATOMIC_LOAD_U1:
6791 case OP_ATOMIC_LOAD_U2:
6792 case OP_ATOMIC_LOAD_U4:
6793 case OP_ATOMIC_LOAD_R4:
6794 case OP_ATOMIC_LOAD_R8:
6795 case OP_ATOMIC_STORE_I1:
6796 case OP_ATOMIC_STORE_I2:
6797 case OP_ATOMIC_STORE_I4:
6798 case OP_ATOMIC_STORE_U1:
6799 case OP_ATOMIC_STORE_U2:
6800 case OP_ATOMIC_STORE_U4:
6801 case OP_ATOMIC_STORE_R4:
6802 case OP_ATOMIC_STORE_R8:
6809 #if defined(ENABLE_GSHAREDVT)
6811 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6813 #endif /* !MONOTOUCH */