mono/mini/mini-x86.c

   1 /*
   2  * mini-x86.c: x86 backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Paolo Molaro (lupus@ximian.com)
   6  *   Dietmar Maurer (dietmar@ximian.com)
   7  *   Patrik Torstensson
   8  *
   9  * (C) 2003 Ximian, Inc.
  10  */
  11 #include "mini.h"
  12 #include <string.h>
  13 #include <math.h>
  14
  15 #include <mono/metadata/appdomain.h>
  16 #include <mono/metadata/debug-helpers.h>
  17 #include <mono/metadata/profiler-private.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "trace.h"
  21 #include "mini-x86.h"
  22 #include "inssel.h"
  23 #include "cpu-pentium.h"
  24
  25 static gint lmf_tls_offset = -1;
  26
  27 #ifdef PLATFORM_WIN32
  28 /* Under windows, the default pinvoke calling convention is stdcall */
  29 #define CALLCONV_IS_STDCALL(call_conv) (((call_conv) == MONO_CALL_STDCALL) || ((call_conv) == MONO_CALL_DEFAULT))
  30 #else
  31 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  32 #endif
  33
  34 #define SIGNAL_STACK_SIZE (64 * 1024)
  35
  36 static gpointer mono_arch_get_lmf_addr (void);
  37
  38 const char*
  39 mono_arch_regname (int reg) {
  40         switch (reg) {
  41         case X86_EAX: return "%eax";
  42         case X86_EBX: return "%ebx";
  43         case X86_ECX: return "%ecx";
  44         case X86_EDX: return "%edx";
  45         case X86_ESP: return "%esp";    case X86_EBP: return "%ebp";
  46         case X86_EDI: return "%edi";
  47         case X86_ESI: return "%esi";
  48         }
  49         return "unknown";
  50 }
  51
  52 /*
  53  * mono_arch_get_argument_info:
  54  * @csig:  a method signature
  55  * @param_count: the number of parameters to consider
  56  * @arg_info: an array to store the result infos
  57  *
  58  * Gathers information on parameters such as size, alignment and
  59  * padding. arg_info should be large enought to hold param_count + 1 entries.
  60  *
  61  * Returns the size of the activation frame.
  62  */
  63 int
  64 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
  65 {
  66         int k, frame_size = 0;
  67         int size, align, pad;
  68         int offset = 8;
  69
  70         if (MONO_TYPE_ISSTRUCT (csig->ret)) {
  71                 frame_size += sizeof (gpointer);
  72                 offset += 4;
  73         }
  74
  75         arg_info [0].offset = offset;
  76
  77         if (csig->hasthis) {
  78                 frame_size += sizeof (gpointer);
  79                 offset += 4;
  80         }
  81
  82         arg_info [0].size = frame_size;
  83
  84         for (k = 0; k < param_count; k++) {
  85
  86                 if (csig->pinvoke)
  87                         size = mono_type_native_stack_size (csig->params [k], &align);
  88                 else
  89                         size = mono_type_stack_size (csig->params [k], &align);
  90
  91                 /* ignore alignment for now */
  92                 align = 1;
  93
  94                 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
  95                 arg_info [k].pad = pad;
  96                 frame_size += size;
  97                 arg_info [k + 1].pad = 0;
  98                 arg_info [k + 1].size = size;
  99                 offset += pad;
 100                 arg_info [k + 1].offset = offset;
 101                 offset += size;
 102         }
 103
 104         align = MONO_ARCH_FRAME_ALIGNMENT;
 105         frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 106         arg_info [k].pad = pad;
 107
 108         return frame_size;
 109 }
 110
 111 static const guchar cpuid_impl [] = {
 112         0x55,                           /* push   %ebp */
 113         0x89, 0xe5,                     /* mov    %esp,%ebp */
 114         0x53,                           /* push   %ebx */
 115         0x8b, 0x45, 0x08,               /* mov    0x8(%ebp),%eax */
 116         0x0f, 0xa2,                     /* cpuid   */
 117         0x50,                           /* push   %eax */
 118         0x8b, 0x45, 0x10,               /* mov    0x10(%ebp),%eax */
 119         0x89, 0x18,                     /* mov    %ebx,(%eax) */
 120         0x8b, 0x45, 0x14,               /* mov    0x14(%ebp),%eax */
 121         0x89, 0x08,                     /* mov    %ecx,(%eax) */
 122         0x8b, 0x45, 0x18,               /* mov    0x18(%ebp),%eax */
 123         0x89, 0x10,                     /* mov    %edx,(%eax) */
 124         0x58,                           /* pop    %eax */
 125         0x8b, 0x55, 0x0c,               /* mov    0xc(%ebp),%edx */
 126         0x89, 0x02,                     /* mov    %eax,(%edx) */
 127         0x5b,                           /* pop    %ebx */
 128         0xc9,                           /* leave   */
 129         0xc3,                           /* ret     */
 130 };
 131
 132 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
 133
 134 static int
 135 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 136 {
 137         int have_cpuid = 0;
 138         __asm__  __volatile__ (
 139                 "pushfl\n"
 140                 "popl %%eax\n"
 141                 "movl %%eax, %%edx\n"
 142                 "xorl $0x200000, %%eax\n"
 143                 "pushl %%eax\n"
 144                 "popfl\n"
 145                 "pushfl\n"
 146                 "popl %%eax\n"
 147                 "xorl %%edx, %%eax\n"
 148                 "andl $0x200000, %%eax\n"
 149                 "movl %%eax, %0"
 150                 : "=r" (have_cpuid)
 151                 :
 152                 : "%eax", "%edx"
 153         );
 154
 155         if (have_cpuid) {
 156                 CpuidFunc func = (CpuidFunc)cpuid_impl;
 157                 func (id, p_eax, p_ebx, p_ecx, p_edx);
 158                 /*
 159                  * We use this approach because of issues with gcc and pic code, see:
 160                  * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
 161                 __asm__ __volatile__ ("cpuid"
 162                         : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 163                         : "a" (id));
 164                 */
 165                 return 1;
 166         }
 167         return 0;
 168 }
 169
 170 /*
 171  * Initialize the cpu to execute managed code.
 172  */
 173 void
 174 mono_arch_cpu_init (void)
 175 {
 176         guint16 fpcw;
 177
 178         /* spec compliance requires running with double precision */
 179         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 180         fpcw &= ~X86_FPCW_PRECC_MASK;
 181         fpcw |= X86_FPCW_PREC_DOUBLE;
 182         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 183         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 184
 185 }
 186
 187 /*
 188  * This function returns the optimizations supported on this cpu.
 189  */
 190 guint32
 191 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 192 {
 193         int eax, ebx, ecx, edx;
 194         guint32 opts = 0;
 195
 196         *exclude_mask = 0;
 197         /* Feature Flags function, flags returned in EDX. */
 198         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 199                 if (edx & (1 << 15)) {
 200                         opts |= MONO_OPT_CMOV;
 201                         if (edx & 1)
 202                                 opts |= MONO_OPT_FCMOV;
 203                         else
 204                                 *exclude_mask |= MONO_OPT_FCMOV;
 205                 } else
 206                         *exclude_mask |= MONO_OPT_CMOV;
 207         }
 208         return opts;
 209 }
 210
 211 static gboolean
 212 is_regsize_var (MonoType *t) {
 213         if (t->byref)
 214                 return TRUE;
 215         switch (t->type) {
 216         case MONO_TYPE_I4:
 217         case MONO_TYPE_U4:
 218         case MONO_TYPE_I:
 219         case MONO_TYPE_U:
 220         case MONO_TYPE_PTR:
 221                 return TRUE;
 222         case MONO_TYPE_OBJECT:
 223         case MONO_TYPE_STRING:
 224         case MONO_TYPE_CLASS:
 225         case MONO_TYPE_SZARRAY:
 226         case MONO_TYPE_ARRAY:
 227                 return TRUE;
 228         case MONO_TYPE_VALUETYPE:
 229                 if (t->data.klass->enumtype)
 230                         return is_regsize_var (t->data.klass->enum_basetype);
 231                 return FALSE;
 232         }
 233         return FALSE;
 234 }
 235
 236 GList *
 237 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 238 {
 239         GList *vars = NULL;
 240         int i;
 241
 242         for (i = 0; i < cfg->num_varinfo; i++) {
 243                 MonoInst *ins = cfg->varinfo [i];
 244                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 245
 246                 /* unused vars */
 247                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 248                         continue;
 249
 250                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 251                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 252                         continue;
 253
 254                 /* we dont allocate I1 to registers because there is no simply way to sign extend
 255                  * 8bit quantities in caller saved registers on x86 */
 256                 if (is_regsize_var (ins->inst_vtype) || (ins->inst_vtype->type == MONO_TYPE_BOOLEAN) ||
 257                     (ins->inst_vtype->type == MONO_TYPE_U1) || (ins->inst_vtype->type == MONO_TYPE_U2)||
 258                     (ins->inst_vtype->type == MONO_TYPE_I2) || (ins->inst_vtype->type == MONO_TYPE_CHAR)) {
 259                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 260                         g_assert (i == vmv->idx);
 261                         vars = g_list_prepend (vars, vmv);
 262                 }
 263         }
 264
 265         vars = mono_varlist_sort (cfg, vars, 0);
 266
 267         return vars;
 268 }
 269
 270 GList *
 271 mono_arch_get_global_int_regs (MonoCompile *cfg)
 272 {
 273         GList *regs = NULL;
 274
 275         /* we can use 3 registers for global allocation */
 276         regs = g_list_prepend (regs, (gpointer)X86_EBX);
 277         regs = g_list_prepend (regs, (gpointer)X86_ESI);
 278         regs = g_list_prepend (regs, (gpointer)X86_EDI);
 279
 280         return regs;
 281 }
 282
 283 /*
 284  * mono_arch_regalloc_cost:
 285  *
 286  *  Return the cost, in number of memory references, of the action of
 287  * allocating the variable VMV into a register during global register
 288  * allocation.
 289  */
 290 guint32
 291 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 292 {
 293         MonoInst *ins = cfg->varinfo [vmv->idx];
 294
 295         if (cfg->method->save_lmf)
 296                 /* The register is already saved */
 297                 return (ins->opcode == OP_ARG) ? 1 : 0;
 298         else
 299                 /* push+pop+possible load if it is an argument */
 300                 return (ins->opcode == OP_ARG) ? 3 : 2;
 301 }
 302
 303 /*
 304  * Set var information according to the calling convention. X86 version.
 305  * The locals var stuff should most likely be split in another method.
 306  */
 307 void
 308 mono_arch_allocate_vars (MonoCompile *m)
 309 {
 310         MonoMethodSignature *sig;
 311         MonoMethodHeader *header;
 312         MonoInst *inst;
 313         int i, offset, size, align, curinst;
 314
 315         header = ((MonoMethodNormal *)m->method)->header;
 316
 317         sig = m->method->signature;
 318
 319         offset = 8;
 320         curinst = 0;
 321         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
 322                 m->ret->opcode = OP_REGOFFSET;
 323                 m->ret->inst_basereg = X86_EBP;
 324                 m->ret->inst_offset = offset;
 325                 offset += sizeof (gpointer);
 326         } else {
 327                 /* FIXME: handle long and FP values */
 328                 switch (sig->ret->type) {
 329                 case MONO_TYPE_VOID:
 330                         break;
 331                 default:
 332                         m->ret->opcode = OP_REGVAR;
 333                         m->ret->inst_c0 = X86_EAX;
 334                         break;
 335                 }
 336         }
 337         if (sig->hasthis) {
 338                 inst = m->varinfo [curinst];
 339                 if (inst->opcode != OP_REGVAR) {
 340                         inst->opcode = OP_REGOFFSET;
 341                         inst->inst_basereg = X86_EBP;
 342                 }
 343                 inst->inst_offset = offset;
 344                 offset += sizeof (gpointer);
 345                 curinst++;
 346         }
 347
 348         if (sig->call_convention == MONO_CALL_VARARG) {
 349                 m->sig_cookie = offset;
 350                 offset += sizeof (gpointer);
 351         }
 352
 353         for (i = 0; i < sig->param_count; ++i) {
 354                 inst = m->varinfo [curinst];
 355                 if (inst->opcode != OP_REGVAR) {
 356                         inst->opcode = OP_REGOFFSET;
 357                         inst->inst_basereg = X86_EBP;
 358                 }
 359                 inst->inst_offset = offset;
 360                 size = mono_type_size (sig->params [i], &align);
 361                 size += 4 - 1;
 362                 size &= ~(4 - 1);
 363                 offset += size;
 364                 curinst++;
 365         }
 366
 367         offset = 0;
 368
 369         /* reserve space to save LMF and caller saved registers */
 370
 371         if (m->method->save_lmf) {
 372                 offset += sizeof (MonoLMF);
 373         } else {
 374                 if (m->used_int_regs & (1 << X86_EBX)) {
 375                         offset += 4;
 376                 }
 377
 378                 if (m->used_int_regs & (1 << X86_EDI)) {
 379                         offset += 4;
 380                 }
 381
 382                 if (m->used_int_regs & (1 << X86_ESI)) {
 383                         offset += 4;
 384                 }
 385         }
 386
 387         for (i = curinst; i < m->num_varinfo; ++i) {
 388                 inst = m->varinfo [i];
 389
 390                 if ((inst->flags & MONO_INST_IS_DEAD) || inst->opcode == OP_REGVAR)
 391                         continue;
 392
 393                 /* inst->unused indicates native sized value types, this is used by the
 394                 * pinvoke wrappers when they call functions returning structure */
 395                 if (inst->unused && MONO_TYPE_ISSTRUCT (inst->inst_vtype) && inst->inst_vtype->type != MONO_TYPE_TYPEDBYREF)
 396                         size = mono_class_native_size (inst->inst_vtype->data.klass, &align);
 397                 else
 398                         size = mono_type_size (inst->inst_vtype, &align);
 399
 400                 offset += size;
 401                 offset += align - 1;
 402                 offset &= ~(align - 1);
 403                 inst->opcode = OP_REGOFFSET;
 404                 inst->inst_basereg = X86_EBP;
 405                 inst->inst_offset = -offset;
 406                 //g_print ("allocating local %d to %d\n", i, -offset);
 407         }
 408         offset += (MONO_ARCH_FRAME_ALIGNMENT - 1);
 409         offset &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
 410
 411         /* change sign? */
 412         m->stack_offset = -offset;
 413 }
 414
 415 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
 416  * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
 417  */
 418
 419 /*
 420  * take the arguments and generate the arch-specific
 421  * instructions to properly call the function in call.
 422  * This includes pushing, moving arguments to the right register
 423  * etc.
 424  * Issue: who does the spilling if needed, and when?
 425  */
 426 MonoCallInst*
 427 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
 428         MonoInst *arg, *in;
 429         MonoMethodSignature *sig;
 430         int i, n, stack_size, type;
 431         MonoType *ptype;
 432
 433         stack_size = 0;
 434         /* add the vararg cookie before the non-implicit args */
 435         if (call->signature->call_convention == MONO_CALL_VARARG) {
 436                 MonoInst *sig_arg;
 437                 /* FIXME: Add support for signature tokens to AOT */
 438                 cfg->disable_aot = TRUE;
 439                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
 440                 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
 441                 sig_arg->inst_p0 = call->signature;
 442                 arg->inst_left = sig_arg;
 443                 arg->type = STACK_PTR;
 444                 /* prepend, so they get reversed */
 445                 arg->next = call->out_args;
 446                 call->out_args = arg;
 447                 stack_size += sizeof (gpointer);
 448         }
 449         sig = call->signature;
 450         n = sig->param_count + sig->hasthis;
 451
 452         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret))
 453                 stack_size += sizeof (gpointer);
 454         for (i = 0; i < n; ++i) {
 455                 if (is_virtual && i == 0) {
 456                         /* the argument will be attached to the call instrucion */
 457                         in = call->args [i];
 458                         stack_size += 4;
 459                 } else {
 460                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
 461                         in = call->args [i];
 462                         arg->cil_code = in->cil_code;
 463                         arg->inst_left = in;
 464                         arg->type = in->type;
 465                         /* prepend, so they get reversed */
 466                         arg->next = call->out_args;
 467                         call->out_args = arg;
 468                         if (i >= sig->hasthis) {
 469                                 ptype = sig->params [i - sig->hasthis];
 470                                 if (ptype->byref)
 471                                         type = MONO_TYPE_U;
 472                                 else
 473                                         type = ptype->type;
 474 handle_enum:
 475                                 /* FIXME: validate arguments... */
 476                                 switch (type) {
 477                                 case MONO_TYPE_I:
 478                                 case MONO_TYPE_U:
 479                                 case MONO_TYPE_BOOLEAN:
 480                                 case MONO_TYPE_CHAR:
 481                                 case MONO_TYPE_I1:
 482                                 case MONO_TYPE_U1:
 483                                 case MONO_TYPE_I2:
 484                                 case MONO_TYPE_U2:
 485                                 case MONO_TYPE_I4:
 486                                 case MONO_TYPE_U4:
 487                                 case MONO_TYPE_STRING:
 488                                 case MONO_TYPE_CLASS:
 489                                 case MONO_TYPE_OBJECT:
 490                                 case MONO_TYPE_PTR:
 491                                 case MONO_TYPE_FNPTR:
 492                                 case MONO_TYPE_ARRAY:
 493                                 case MONO_TYPE_SZARRAY:
 494                                         stack_size += 4;
 495                                         break;
 496                                 case MONO_TYPE_I8:
 497                                 case MONO_TYPE_U8:
 498                                         stack_size += 8;
 499                                         break;
 500                                 case MONO_TYPE_R4:
 501                                         stack_size += 4;
 502                                         arg->opcode = OP_OUTARG_R4;
 503                                         break;
 504                                 case MONO_TYPE_R8:
 505                                         stack_size += 8;
 506                                         arg->opcode = OP_OUTARG_R8;
 507                                         break;
 508                                 case MONO_TYPE_VALUETYPE:
 509                                         if (MONO_TYPE_ISSTRUCT (ptype)) {
 510                                                 int size;
 511                                                 if (sig->pinvoke)
 512                                                         size = mono_type_native_stack_size (&in->klass->byval_arg, NULL);
 513                                                 else
 514                                                         size = mono_type_stack_size (&in->klass->byval_arg, NULL);
 515
 516                                                 stack_size += size;
 517                                                 arg->opcode = OP_OUTARG_VT;
 518                                                 arg->klass = in->klass;
 519                                                 arg->unused = sig->pinvoke;
 520                                                 arg->inst_imm = size;
 521                                         } else {
 522                                                 type = ptype->data.klass->enum_basetype->type;
 523                                                 goto handle_enum;
 524                                         }
 525                                         break;
 526                                 case MONO_TYPE_TYPEDBYREF:
 527                                         stack_size += sizeof (MonoTypedRef);
 528                                         arg->opcode = OP_OUTARG_VT;
 529                                         arg->klass = in->klass;
 530                                         arg->unused = sig->pinvoke;
 531                                         arg->inst_imm = sizeof (MonoTypedRef);
 532                                         break;
 533                                 case MONO_TYPE_GENERICINST:
 534                                         type = ptype->data.generic_inst->generic_type->type;
 535                                         goto handle_enum;
 536
 537                                 default:
 538                                         g_error ("unknown type 0x%02x in mono_arch_call_opcode\n", type);
 539                                 }
 540                         } else {
 541                                 /* the this argument */
 542                                 stack_size += 4;
 543                         }
 544                 }
 545         }
 546         /* if the function returns a struct, the called method already does a ret $0x4 */
 547         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret))
 548                 stack_size -= 4;
 549         call->stack_usage = stack_size;
 550         /*
 551          * should set more info in call, such as the stack space
 552          * used by the args that needs to be added back to esp
 553          */
 554
 555         return call;
 556 }
 557
 558 /*
 559  * Allow tracing to work with this interface (with an optional argument)
 560  */
 561
 562 /*
 563  * This may be needed on some archs or for debugging support.
 564  */
 565 void
 566 mono_arch_instrument_mem_needs (MonoMethod *method, int *stack, int *code)
 567 {
 568         /* no stack room needed now (may be needed for FASTCALL-trace support) */
 569         *stack = 0;
 570         /* split prolog-epilog requirements? */
 571         *code = 50; /* max bytes needed: check this number */
 572 }
 573
 574 void*
 575 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
 576 {
 577         guchar *code = p;
 578
 579         /* if some args are passed in registers, we need to save them here */
 580         x86_push_reg (code, X86_EBP);
 581         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
 582         x86_push_imm (code, cfg->method);
 583         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
 584         x86_call_code (code, 0);
 585         x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
 586
 587         return code;
 588 }
 589
 590 enum {
 591         SAVE_NONE,
 592         SAVE_STRUCT,
 593         SAVE_EAX,
 594         SAVE_EAX_EDX,
 595         SAVE_FP
 596 };
 597
 598 void*
 599 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
 600 {
 601         guchar *code = p;
 602         int arg_size = 0, save_mode = SAVE_NONE;
 603         MonoMethod *method = cfg->method;
 604         int rtype = method->signature->ret->type;
 605
 606 handle_enum:
 607         switch (rtype) {
 608         case MONO_TYPE_VOID:
 609                 /* special case string .ctor icall */
 610                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
 611                         save_mode = SAVE_EAX;
 612                 else
 613                         save_mode = SAVE_NONE;
 614                 break;
 615         case MONO_TYPE_I8:
 616         case MONO_TYPE_U8:
 617                 save_mode = SAVE_EAX_EDX;
 618                 break;
 619         case MONO_TYPE_R4:
 620         case MONO_TYPE_R8:
 621                 save_mode = SAVE_FP;
 622                 break;
 623         case MONO_TYPE_VALUETYPE:
 624                 if (method->signature->ret->data.klass->enumtype) {
 625                         rtype = method->signature->ret->data.klass->enum_basetype->type;
 626                         goto handle_enum;
 627                 }
 628                 save_mode = SAVE_STRUCT;
 629                 break;
 630         default:
 631                 save_mode = SAVE_EAX;
 632                 break;
 633         }
 634
 635         switch (save_mode) {
 636         case SAVE_EAX_EDX:
 637                 x86_push_reg (code, X86_EDX);
 638                 x86_push_reg (code, X86_EAX);
 639                 if (enable_arguments) {
 640                         x86_push_reg (code, X86_EDX);
 641                         x86_push_reg (code, X86_EAX);
 642                         arg_size = 8;
 643                 }
 644                 break;
 645         case SAVE_EAX:
 646                 x86_push_reg (code, X86_EAX);
 647                 if (enable_arguments) {
 648                         x86_push_reg (code, X86_EAX);
 649                         arg_size = 4;
 650                 }
 651                 break;
 652         case SAVE_FP:
 653                 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
 654                 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
 655                 if (enable_arguments) {
 656                         x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
 657                         x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
 658                         arg_size = 8;
 659                 }
 660                 break;
 661         case SAVE_STRUCT:
 662                 if (enable_arguments) {
 663                         x86_push_membase (code, X86_EBP, 8);
 664                         arg_size = 4;
 665                 }
 666                 break;
 667         case SAVE_NONE:
 668         default:
 669                 break;
 670         }
 671
 672
 673         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
 674         x86_push_imm (code, method);
 675         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
 676         x86_call_code (code, 0);
 677         x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
 678
 679         switch (save_mode) {
 680         case SAVE_EAX_EDX:
 681                 x86_pop_reg (code, X86_EAX);
 682                 x86_pop_reg (code, X86_EDX);
 683                 break;
 684         case SAVE_EAX:
 685                 x86_pop_reg (code, X86_EAX);
 686                 break;
 687         case SAVE_FP:
 688                 x86_fld_membase (code, X86_ESP, 0, TRUE);
 689                 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
 690                 break;
 691         case SAVE_NONE:
 692         default:
 693                 break;
 694         }
 695
 696         return code;
 697 }
 698
 699 #define EMIT_COND_BRANCH(ins,cond,sign) \
 700 if (ins->flags & MONO_INST_BRLABEL) { \
 701         if (ins->inst_i0->inst_c0) { \
 702                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
 703         } else { \
 704                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
 705                 x86_branch32 (code, cond, 0, sign); \
 706         } \
 707 } else { \
 708         if (ins->inst_true_bb->native_offset) { \
 709                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
 710         } else { \
 711                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
 712                 if ((cfg->opt & MONO_OPT_BRANCH) && \
 713                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
 714                         x86_branch8 (code, cond, 0, sign); \
 715                 else \
 716                         x86_branch32 (code, cond, 0, sign); \
 717         } \
 718 }
 719
 720 /* emit an exception if condition is fail */
 721 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
 722         do {                                                        \
 723                 mono_add_patch_info (cfg, code - cfg->native_code,   \
 724                                     MONO_PATCH_INFO_EXC, exc_name);  \
 725                 x86_branch32 (code, cond, 0, signed);               \
 726         } while (0);
 727
 728 #define EMIT_FPCOMPARE(code) do { \
 729         x86_fcompp (code); \
 730         x86_fnstsw (code); \
 731 } while (0);
 732
 733 /* FIXME: Add more instructions */
 734 #define INST_IGNORES_CFLAGS(ins) (((ins)->opcode == CEE_BR) || ((ins)->opcode == OP_STORE_MEMBASE_IMM))
 735
 736 static void
 737 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
 738 {
 739         MonoInst *ins, *last_ins = NULL;
 740         ins = bb->code;
 741
 742         while (ins) {
 743
 744                 switch (ins->opcode) {
 745                 case OP_ICONST:
 746                         /* reg = 0 -> XOR (reg, reg) */
 747                         /* XOR sets cflags on x86, so we cant do it always */
 748                         if (ins->inst_c0 == 0 && ins->next && INST_IGNORES_CFLAGS (ins->next)) {
 749                                 ins->opcode = CEE_XOR;
 750                                 ins->sreg1 = ins->dreg;
 751                                 ins->sreg2 = ins->dreg;
 752                         }
 753                         break;
 754                 case OP_MUL_IMM:
 755                         /* remove unnecessary multiplication with 1 */
 756                         if (ins->inst_imm == 1) {
 757                                 if (ins->dreg != ins->sreg1) {
 758                                         ins->opcode = OP_MOVE;
 759                                 } else {
 760                                         last_ins->next = ins->next;
 761                                         ins = ins->next;
 762                                         continue;
 763                                 }
 764                         }
 765                         break;
 766                 case OP_COMPARE_IMM:
 767                         /* OP_COMPARE_IMM (reg, 0)
 768                          * -->
 769                          * OP_X86_TEST_NULL (reg)
 770                          */
 771                         if (ins->inst_imm == 0 && ins->next &&
 772                             (ins->next->opcode == CEE_BEQ || ins->next->opcode == CEE_BNE_UN ||
 773                              ins->next->opcode == OP_CEQ)) {
 774                                 ins->opcode = OP_X86_TEST_NULL;
 775                         }
 776                         break;
 777                 case OP_X86_COMPARE_MEMBASE_IMM:
 778                         /*
 779                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
 780                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
 781                          * -->
 782                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
 783                          * OP_COMPARE_IMM reg, imm
 784                          *
 785                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
 786                          */
 787                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
 788                             ins->inst_basereg == last_ins->inst_destbasereg &&
 789                             ins->inst_offset == last_ins->inst_offset) {
 790                                         ins->opcode = OP_COMPARE_IMM;
 791                                         ins->sreg1 = last_ins->sreg1;
 792
 793                                         /* check if we can remove cmp reg,0 with test null */
 794                                         if (ins->inst_imm == 0 && ins->next &&
 795                                                 (ins->next->opcode == CEE_BEQ || ins->next->opcode == CEE_BNE_UN ||
 796                                                 ins->next->opcode == OP_CEQ)) {
 797                                                 ins->opcode = OP_X86_TEST_NULL;
 798                                         }
 799                                 }
 800
 801                         break;
 802                 case OP_LOAD_MEMBASE:
 803                 case OP_LOADI4_MEMBASE:
 804                         /*
 805                          * Note: if reg1 = reg2 the load op is removed
 806                          *
 807                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
 808                          * OP_LOAD_MEMBASE offset(basereg), reg2
 809                          * -->
 810                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
 811                          * OP_MOVE reg1, reg2
 812                          */
 813                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
 814                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
 815                             ins->inst_basereg == last_ins->inst_destbasereg &&
 816                             ins->inst_offset == last_ins->inst_offset) {
 817                                 if (ins->dreg == last_ins->sreg1) {
 818                                         last_ins->next = ins->next;
 819                                         ins = ins->next;
 820                                         continue;
 821                                 } else {
 822                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
 823                                         ins->opcode = OP_MOVE;
 824                                         ins->sreg1 = last_ins->sreg1;
 825                                 }
 826
 827                         /*
 828                          * Note: reg1 must be different from the basereg in the second load
 829                          * Note: if reg1 = reg2 is equal then second load is removed
 830                          *
 831                          * OP_LOAD_MEMBASE offset(basereg), reg1
 832                          * OP_LOAD_MEMBASE offset(basereg), reg2
 833                          * -->
 834                          * OP_LOAD_MEMBASE offset(basereg), reg1
 835                          * OP_MOVE reg1, reg2
 836                          */
 837                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
 838                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
 839                               ins->inst_basereg != last_ins->dreg &&
 840                               ins->inst_basereg == last_ins->inst_basereg &&
 841                               ins->inst_offset == last_ins->inst_offset) {
 842
 843                                 if (ins->dreg == last_ins->dreg) {
 844                                         last_ins->next = ins->next;
 845                                         ins = ins->next;
 846                                         continue;
 847                                 } else {
 848                                         ins->opcode = OP_MOVE;
 849                                         ins->sreg1 = last_ins->dreg;
 850                                 }
 851
 852                                 //g_assert_not_reached ();
 853
 854 #if 0
 855                         /*
 856                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
 857                          * OP_LOAD_MEMBASE offset(basereg), reg
 858                          * -->
 859                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
 860                          * OP_ICONST reg, imm
 861                          */
 862                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
 863                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
 864                                    ins->inst_basereg == last_ins->inst_destbasereg &&
 865                                    ins->inst_offset == last_ins->inst_offset) {
 866                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
 867                                 ins->opcode = OP_ICONST;
 868                                 ins->inst_c0 = last_ins->inst_imm;
 869                                 g_assert_not_reached (); // check this rule
 870 #endif
 871                         }
 872                         break;
 873                 case OP_LOADU1_MEMBASE:
 874                 case OP_LOADI1_MEMBASE:
 875                         /*
 876                          * Note: if reg1 = reg2 the load op is removed
 877                          *
 878                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
 879                          * OP_LOAD_MEMBASE offset(basereg), reg2
 880                          * -->
 881                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
 882                          * OP_MOVE reg1, reg2
 883                          */
 884                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
 885                                         ins->inst_basereg == last_ins->inst_destbasereg &&
 886                                         ins->inst_offset == last_ins->inst_offset) {
 887                                 if (ins->dreg == last_ins->sreg1) {
 888                                         last_ins->next = ins->next;
 889                                         ins = ins->next;
 890                                         continue;
 891                                 } else {
 892                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
 893                                         ins->opcode = OP_MOVE;
 894                                         ins->sreg1 = last_ins->sreg1;
 895                                 }
 896                         }
 897                         break;
 898                 case OP_LOADU2_MEMBASE:
 899                 case OP_LOADI2_MEMBASE:
 900                         /*
 901                          * Note: if reg1 = reg2 the load op is removed
 902                          *
 903                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
 904                          * OP_LOAD_MEMBASE offset(basereg), reg2
 905                          * -->
 906                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
 907                          * OP_MOVE reg1, reg2
 908                          */
 909                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
 910                                         ins->inst_basereg == last_ins->inst_destbasereg &&
 911                                         ins->inst_offset == last_ins->inst_offset) {
 912                                 if (ins->dreg == last_ins->sreg1) {
 913                                         last_ins->next = ins->next;
 914                                         ins = ins->next;
 915                                         continue;
 916                                 } else {
 917                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
 918                                         ins->opcode = OP_MOVE;
 919                                         ins->sreg1 = last_ins->sreg1;
 920                                 }
 921                         }
 922                         break;
 923                 case CEE_CONV_I4:
 924                 case CEE_CONV_U4:
 925                 case OP_MOVE:
 926                         /*
 927                          * Removes:
 928                          *
 929                          * OP_MOVE reg, reg
 930                          */
 931                         if (ins->dreg == ins->sreg1) {
 932                                 if (last_ins)
 933                                         last_ins->next = ins->next;
 934                                 ins = ins->next;
 935                                 continue;
 936                         }
 937                         /*
 938                          * Removes:
 939                          *
 940                          * OP_MOVE sreg, dreg
 941                          * OP_MOVE dreg, sreg
 942                          */
 943                         if (last_ins && last_ins->opcode == OP_MOVE &&
 944                             ins->sreg1 == last_ins->dreg &&
 945                             ins->dreg == last_ins->sreg1) {
 946                                 last_ins->next = ins->next;
 947                                 ins = ins->next;
 948                                 continue;
 949                         }
 950                         break;
 951                 }
 952                 last_ins = ins;
 953                 ins = ins->next;
 954         }
 955         bb->last_ins = last_ins;
 956 }
 957
 958 static const int
 959 branch_cc_table [] = {
 960         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
 961         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
 962         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
 963 };
 964
 965 #define DEBUG(a) if (cfg->verbose_level > 1) a
 966 //#define DEBUG(a)
 967
 968 /*
 969  * returns the offset used by spillvar. It allocates a new
 970  * spill variable if necessary.
 971  */
 972 static int
 973 mono_spillvar_offset (MonoCompile *cfg, int spillvar)
 974 {
 975         MonoSpillInfo **si, *info;
 976         int i = 0;
 977
 978         si = &cfg->spill_info;
 979
 980         while (i <= spillvar) {
 981
 982                 if (!*si) {
 983                         *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
 984                         info->next = NULL;
 985                         cfg->stack_offset -= sizeof (gpointer);
 986                         info->offset = cfg->stack_offset;
 987                 }
 988
 989                 if (i == spillvar)
 990                         return (*si)->offset;
 991
 992                 i++;
 993                 si = &(*si)->next;
 994         }
 995
 996         g_assert_not_reached ();
 997         return 0;
 998 }
 999
1000 /*
1001  * returns the offset used by spillvar. It allocates a new
1002  * spill float variable if necessary.
1003  * (same as mono_spillvar_offset but for float)
1004  */
1005 static int
1006 mono_spillvar_offset_float (MonoCompile *cfg, int spillvar)
1007 {
1008         MonoSpillInfo **si, *info;
1009         int i = 0;
1010
1011         si = &cfg->spill_info_float;
1012
1013         while (i <= spillvar) {
1014
1015                 if (!*si) {
1016                         *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
1017                         info->next = NULL;
1018                         cfg->stack_offset -= sizeof (double);
1019                         info->offset = cfg->stack_offset;
1020                 }
1021
1022                 if (i == spillvar)
1023                         return (*si)->offset;
1024
1025                 i++;
1026                 si = &(*si)->next;
1027         }
1028
1029         g_assert_not_reached ();
1030         return 0;
1031 }
1032
1033 /*
1034  * Creates a store for spilled floating point items
1035  */
1036 static MonoInst*
1037 create_spilled_store_float (MonoCompile *cfg, int spill, int reg, MonoInst *ins)
1038 {
1039         MonoInst *store;
1040         MONO_INST_NEW (cfg, store, OP_STORER8_MEMBASE_REG);
1041         store->sreg1 = reg;
1042         store->inst_destbasereg = X86_EBP;
1043         store->inst_offset = mono_spillvar_offset_float (cfg, spill);
1044
1045         DEBUG (g_print ("SPILLED FLOAT STORE (%d at 0x%08x(%%sp)) (from %d)\n", spill, store->inst_offset, reg));
1046         return store;
1047 }
1048
1049 /*
1050  * Creates a load for spilled floating point items
1051  */
1052 static MonoInst*
1053 create_spilled_load_float (MonoCompile *cfg, int spill, int reg, MonoInst *ins)
1054 {
1055         MonoInst *load;
1056         MONO_INST_NEW (cfg, load, OP_LOADR8_SPILL_MEMBASE);
1057         load->dreg = reg;
1058         load->inst_basereg = X86_EBP;
1059         load->inst_offset = mono_spillvar_offset_float (cfg, spill);
1060
1061         DEBUG (g_print ("SPILLED FLOAT LOAD (%d at 0x%08x(%%sp)) (from %d)\n", spill, load->inst_offset, reg));
1062         return load;
1063 }
1064
1065 #define reg_is_freeable(r) ((r) >= 0 && (r) <= 7 && X86_IS_CALLEE ((r)))
1066
1067 typedef struct {
1068         int born_in;
1069         int killed_in;
1070         int last_use;
1071         int prev_use;
1072         int flags;              /* used to track fp spill/load */
1073 } RegTrack;
1074
1075 static const char*const * ins_spec = pentium_desc;
1076
1077 static void
1078 print_ins (int i, MonoInst *ins)
1079 {
1080         const char *spec = ins_spec [ins->opcode];
1081         g_print ("\t%-2d %s", i, mono_inst_name (ins->opcode));
1082         if (spec [MONO_INST_DEST]) {
1083                 if (ins->dreg >= MONO_MAX_IREGS)
1084                         g_print (" R%d <-", ins->dreg);
1085                 else
1086                         g_print (" %s <-", mono_arch_regname (ins->dreg));
1087         }
1088         if (spec [MONO_INST_SRC1]) {
1089                 if (ins->sreg1 >= MONO_MAX_IREGS)
1090                         g_print (" R%d", ins->sreg1);
1091                 else
1092                         g_print (" %s", mono_arch_regname (ins->sreg1));
1093         }
1094         if (spec [MONO_INST_SRC2]) {
1095                 if (ins->sreg2 >= MONO_MAX_IREGS)
1096                         g_print (" R%d", ins->sreg2);
1097                 else
1098                         g_print (" %s", mono_arch_regname (ins->sreg2));
1099         }
1100         if (spec [MONO_INST_CLOB])
1101                 g_print (" clobbers: %c", spec [MONO_INST_CLOB]);
1102         g_print ("\n");
1103 }
1104
1105 static void
1106 print_regtrack (RegTrack *t, int num)
1107 {
1108         int i;
1109         char buf [32];
1110         const char *r;
1111
1112         for (i = 0; i < num; ++i) {
1113                 if (!t [i].born_in)
1114                         continue;
1115                 if (i >= MONO_MAX_IREGS) {
1116                         g_snprintf (buf, sizeof(buf), "R%d", i);
1117                         r = buf;
1118                 } else
1119                         r = mono_arch_regname (i);
1120                 g_print ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].last_use);
1121         }
1122 }
1123
1124 typedef struct InstList InstList;
1125
1126 struct InstList {
1127         InstList *prev;
1128         InstList *next;
1129         MonoInst *data;
1130 };
1131
1132 static inline InstList*
1133 inst_list_prepend (MonoMemPool *pool, InstList *list, MonoInst *data)
1134 {
1135         InstList *item = mono_mempool_alloc (pool, sizeof (InstList));
1136         item->data = data;
1137         item->prev = NULL;
1138         item->next = list;
1139         if (list)
1140                 list->prev = item;
1141         return item;
1142 }
1143
1144 /*
1145  * Force the spilling of the variable in the symbolic register 'reg'.
1146  */
1147 static int
1148 get_register_force_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, int reg)
1149 {
1150         MonoInst *load;
1151         int i, sel, spill;
1152
1153         sel = cfg->rs->iassign [reg];
1154         /*i = cfg->rs->isymbolic [sel];
1155         g_assert (i == reg);*/
1156         i = reg;
1157         spill = ++cfg->spill_count;
1158         cfg->rs->iassign [i] = -spill - 1;
1159         mono_regstate_free_int (cfg->rs, sel);
1160         /* we need to create a spill var and insert a load to sel after the current instruction */
1161         MONO_INST_NEW (cfg, load, OP_LOAD_MEMBASE);
1162         load->dreg = sel;
1163         load->inst_basereg = X86_EBP;
1164         load->inst_offset = mono_spillvar_offset (cfg, spill);
1165         if (item->prev) {
1166                 while (ins->next != item->prev->data)
1167                         ins = ins->next;
1168         }
1169         load->next = ins->next;
1170         ins->next = load;
1171         DEBUG (g_print ("SPILLED LOAD (%d at 0x%08x(%%ebp)) R%d (freed %s)\n", spill, load->inst_offset, i, mono_arch_regname (sel)));
1172         i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
1173         g_assert (i == sel);
1174
1175         return sel;
1176 }
1177
1178 static int
1179 get_register_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, guint32 regmask, int reg)
1180 {
1181         MonoInst *load;
1182         int i, sel, spill;
1183
1184         DEBUG (g_print ("\tstart regmask to assign R%d: 0x%08x (R%d <- R%d R%d)\n", reg, regmask, ins->dreg, ins->sreg1, ins->sreg2));
1185         /* exclude the registers in the current instruction */
1186         if (reg != ins->sreg1 && (reg_is_freeable (ins->sreg1) || (ins->sreg1 >= MONO_MAX_IREGS && cfg->rs->iassign [ins->sreg1] >= 0))) {
1187                 if (ins->sreg1 >= MONO_MAX_IREGS)
1188                         regmask &= ~ (1 << cfg->rs->iassign [ins->sreg1]);
1189                 else
1190                         regmask &= ~ (1 << ins->sreg1);
1191                 DEBUG (g_print ("\t\texcluding sreg1 %s\n", mono_arch_regname (ins->sreg1)));
1192         }
1193         if (reg != ins->sreg2 && (reg_is_freeable (ins->sreg2) || (ins->sreg2 >= MONO_MAX_IREGS && cfg->rs->iassign [ins->sreg2] >= 0))) {
1194                 if (ins->sreg2 >= MONO_MAX_IREGS)
1195                         regmask &= ~ (1 << cfg->rs->iassign [ins->sreg2]);
1196                 else
1197                         regmask &= ~ (1 << ins->sreg2);
1198                 DEBUG (g_print ("\t\texcluding sreg2 %s %d\n", mono_arch_regname (ins->sreg2), ins->sreg2));
1199         }
1200         if (reg != ins->dreg && reg_is_freeable (ins->dreg)) {
1201                 regmask &= ~ (1 << ins->dreg);
1202                 DEBUG (g_print ("\t\texcluding dreg %s\n", mono_arch_regname (ins->dreg)));
1203         }
1204
1205         DEBUG (g_print ("\t\tavailable regmask: 0x%08x\n", regmask));
1206         g_assert (regmask); /* need at least a register we can free */
1207         sel = -1;
1208         /* we should track prev_use and spill the register that's farther */
1209         for (i = 0; i < MONO_MAX_IREGS; ++i) {
1210                 if (regmask & (1 << i)) {
1211                         sel = i;
1212                         DEBUG (g_print ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), cfg->rs->iassign [sel]));
1213                         break;
1214                 }
1215         }
1216         i = cfg->rs->isymbolic [sel];
1217         spill = ++cfg->spill_count;
1218         cfg->rs->iassign [i] = -spill - 1;
1219         mono_regstate_free_int (cfg->rs, sel);
1220         /* we need to create a spill var and insert a load to sel after the current instruction */
1221         MONO_INST_NEW (cfg, load, OP_LOAD_MEMBASE);
1222         load->dreg = sel;
1223         load->inst_basereg = X86_EBP;
1224         load->inst_offset = mono_spillvar_offset (cfg, spill);
1225         if (item->prev) {
1226                 while (ins->next != item->prev->data)
1227                         ins = ins->next;
1228         }
1229         load->next = ins->next;
1230         ins->next = load;
1231         DEBUG (g_print ("\tSPILLED LOAD (%d at 0x%08x(%%ebp)) R%d (freed %s)\n", spill, load->inst_offset, i, mono_arch_regname (sel)));
1232         i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
1233         g_assert (i == sel);
1234
1235         return sel;
1236 }
1237
1238 static MonoInst*
1239 create_copy_ins (MonoCompile *cfg, int dest, int src, MonoInst *ins)
1240 {
1241         MonoInst *copy;
1242         MONO_INST_NEW (cfg, copy, OP_MOVE);
1243         copy->dreg = dest;
1244         copy->sreg1 = src;
1245         if (ins) {
1246                 copy->next = ins->next;
1247                 ins->next = copy;
1248         }
1249         DEBUG (g_print ("\tforced copy from %s to %s\n", mono_arch_regname (src), mono_arch_regname (dest)));
1250         return copy;
1251 }
1252
1253 static MonoInst*
1254 create_spilled_store (MonoCompile *cfg, int spill, int reg, int prev_reg, MonoInst *ins)
1255 {
1256         MonoInst *store;
1257         MONO_INST_NEW (cfg, store, OP_STORE_MEMBASE_REG);
1258         store->sreg1 = reg;
1259         store->inst_destbasereg = X86_EBP;
1260         store->inst_offset = mono_spillvar_offset (cfg, spill);
1261         if (ins) {
1262                 store->next = ins->next;
1263                 ins->next = store;
1264         }
1265         DEBUG (g_print ("\tSPILLED STORE (%d at 0x%08x(%%ebp)) R%d (from %s)\n", spill, store->inst_offset, prev_reg, mono_arch_regname (reg)));
1266         return store;
1267 }
1268
1269 static void
1270 insert_before_ins (MonoInst *ins, InstList *item, MonoInst* to_insert)
1271 {
1272         MonoInst *prev;
1273         if (item->next) {
1274                 prev = item->next->data;
1275
1276                 while (prev->next != ins)
1277                         prev = prev->next;
1278                 to_insert->next = ins;
1279                 prev->next = to_insert;
1280         } else {
1281                 to_insert->next = ins;
1282         }
1283         /*
1284          * needed otherwise in the next instruction we can add an ins to the
1285          * end and that would get past this instruction.
1286          */
1287         item->data = to_insert;
1288 }
1289
1290
1291 #if  0
1292 static int
1293 alloc_int_reg (MonoCompile *cfg, InstList *curinst, MonoInst *ins, int sym_reg, guint32 allow_mask)
1294 {
1295         int val = cfg->rs->iassign [sym_reg];
1296         if (val < 0) {
1297                 int spill = 0;
1298                 if (val < -1) {
1299                         /* the register gets spilled after this inst */
1300                         spill = -val -1;
1301                 }
1302                 val = mono_regstate_alloc_int (cfg->rs, allow_mask);
1303                 if (val < 0)
1304                         val = get_register_spilling (cfg, curinst, ins, allow_mask, sym_reg);
1305                 cfg->rs->iassign [sym_reg] = val;
1306                 /* add option to store before the instruction for src registers */
1307                 if (spill)
1308                         create_spilled_store (cfg, spill, val, sym_reg, ins);
1309         }
1310         cfg->rs->isymbolic [val] = sym_reg;
1311         return val;
1312 }
1313 #endif
1314
1315 /* flags used in reginfo->flags */
1316 enum {
1317         MONO_X86_FP_NEEDS_LOAD_SPILL    = 1 << 0,
1318         MONO_X86_FP_NEEDS_SPILL                 = 1 << 1,
1319         MONO_X86_FP_NEEDS_LOAD                  = 1 << 2,
1320         MONO_X86_REG_NOT_ECX                    = 1 << 3,
1321         MONO_X86_REG_EAX                                = 1 << 4,
1322         MONO_X86_REG_EDX                                = 1 << 5,
1323         MONO_X86_REG_ECX                                = 1 << 6
1324 };
1325
1326 static int
1327 mono_x86_alloc_int_reg (MonoCompile *cfg, InstList *tmp, MonoInst *ins, guint32 dest_mask, int sym_reg, int flags)
1328 {
1329         int val;
1330         int test_mask = dest_mask;
1331
1332         if (flags & MONO_X86_REG_EAX)
1333                 test_mask &= (1 << X86_EAX);
1334         else if (flags & MONO_X86_REG_EDX)
1335                 test_mask &= (1 << X86_EDX);
1336         else if (flags & MONO_X86_REG_ECX)
1337                 test_mask &= (1 << X86_ECX);
1338         else if (flags & MONO_X86_REG_NOT_ECX)
1339                 test_mask &= ~ (1 << X86_ECX);
1340
1341         val = mono_regstate_alloc_int (cfg->rs, test_mask);
1342         if (val >= 0 && test_mask != dest_mask)
1343                 DEBUG(g_print ("\tUsed flag to allocate reg %s for R%u\n", mono_arch_regname (val), sym_reg));
1344
1345         if (val < 0 && (flags & MONO_X86_REG_NOT_ECX)) {
1346                 DEBUG(g_print ("\tFailed to allocate flag suggested mask (%u) but exluding ECX\n", test_mask));
1347                 val = mono_regstate_alloc_int (cfg->rs, (dest_mask & (~1 << X86_ECX)));
1348         }
1349
1350         if (val < 0) {
1351                 val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1352                 if (val < 0)
1353                         val = get_register_spilling (cfg, tmp, ins, dest_mask, sym_reg);
1354         }
1355
1356         return val;
1357 }
1358
1359
1360 /*#include "cprop.c"*/
1361
1362 /*
1363  * Local register allocation.
1364  * We first scan the list of instructions and we save the liveness info of
1365  * each register (when the register is first used, when it's value is set etc.).
1366  * We also reverse the list of instructions (in the InstList list) because assigning
1367  * registers backwards allows for more tricks to be used.
1368  */
1369 void
1370 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1371 {
1372         MonoInst *ins;
1373         MonoRegState *rs = cfg->rs;
1374         int i, val, fpcount;
1375         RegTrack *reginfo, *reginfof;
1376         RegTrack *reginfo1, *reginfo2, *reginfod;
1377         InstList *tmp, *reversed = NULL;
1378         const char *spec;
1379         guint32 src1_mask, src2_mask, dest_mask;
1380         GList *fspill_list = NULL;
1381         int fspill = 0;
1382
1383         if (!bb->code)
1384                 return;
1385         rs->next_vireg = bb->max_ireg;
1386         rs->next_vfreg = bb->max_freg;
1387         mono_regstate_assign (rs);
1388         reginfo = g_malloc0 (sizeof (RegTrack) * rs->next_vireg);
1389         reginfof = g_malloc0 (sizeof (RegTrack) * rs->next_vfreg);
1390         rs->ifree_mask = X86_CALLEE_REGS;
1391
1392         ins = bb->code;
1393
1394         /*if (cfg->opt & MONO_OPT_COPYPROP)
1395                 local_copy_prop (cfg, ins);*/
1396
1397         i = 1;
1398         fpcount = 0;
1399         DEBUG (g_print ("LOCAL regalloc: basic block: %d\n", bb->block_num));
1400         /* forward pass on the instructions to collect register liveness info */
1401         while (ins) {
1402                 spec = ins_spec [ins->opcode];
1403
1404                 DEBUG (print_ins (i, ins));
1405
1406                 if (spec [MONO_INST_SRC1]) {
1407                         if (spec [MONO_INST_SRC1] == 'f') {
1408                                 GList *spill;
1409                                 reginfo1 = reginfof;
1410
1411                                 spill = g_list_first (fspill_list);
1412                                 if (spill && fpcount < MONO_MAX_FREGS) {
1413                                         reginfo1 [ins->sreg1].flags |= MONO_X86_FP_NEEDS_LOAD;
1414                                         fspill_list = g_list_remove (fspill_list, spill->data);
1415                                 } else
1416                                         fpcount--;
1417                         }
1418                         else
1419                                 reginfo1 = reginfo;
1420                         reginfo1 [ins->sreg1].prev_use = reginfo1 [ins->sreg1].last_use;
1421                         reginfo1 [ins->sreg1].last_use = i;
1422                         if (spec [MONO_INST_SRC1] == 'L') {
1423                                 /* The virtual register is allocated sequentially */
1424                                 reginfo1 [ins->sreg1 + 1].prev_use = reginfo1 [ins->sreg1 + 1].last_use;
1425                                 reginfo1 [ins->sreg1 + 1].last_use = i;
1426                                 if (reginfo1 [ins->sreg1 + 1].born_in == 0 || reginfo1 [ins->sreg1 + 1].born_in > i)
1427                                         reginfo1 [ins->sreg1 + 1].born_in = i;
1428
1429                                 reginfo1 [ins->sreg1].flags |= MONO_X86_REG_EAX;
1430                                 reginfo1 [ins->sreg1 + 1].flags |= MONO_X86_REG_EDX;
1431                         }
1432                 } else {
1433                         ins->sreg1 = -1;
1434                 }
1435                 if (spec [MONO_INST_SRC2]) {
1436                         if (spec [MONO_INST_SRC2] == 'f') {
1437                                 GList *spill;
1438                                 reginfo2 = reginfof;
1439                                 spill = g_list_first (fspill_list);
1440                                 if (spill) {
1441                                         reginfo2 [ins->sreg2].flags |= MONO_X86_FP_NEEDS_LOAD;
1442                                         fspill_list = g_list_remove (fspill_list, spill->data);
1443                                         if (fpcount >= MONO_MAX_FREGS) {
1444                                                 fspill++;
1445                                                 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1446                                                 reginfo2 [ins->sreg2].flags |= MONO_X86_FP_NEEDS_LOAD_SPILL;
1447                                         }
1448                                 } else
1449                                         fpcount--;
1450                         }
1451                         else
1452                                 reginfo2 = reginfo;
1453                         reginfo2 [ins->sreg2].prev_use = reginfo2 [ins->sreg2].last_use;
1454                         reginfo2 [ins->sreg2].last_use = i;
1455                         if (spec [MONO_INST_SRC2] == 'L') {
1456                                 /* The virtual register is allocated sequentially */
1457                                 reginfo2 [ins->sreg2 + 1].prev_use = reginfo2 [ins->sreg2 + 1].last_use;
1458                                 reginfo2 [ins->sreg2 + 1].last_use = i;
1459                                 if (reginfo2 [ins->sreg2 + 1].born_in == 0 || reginfo2 [ins->sreg2 + 1].born_in > i)
1460                                         reginfo2 [ins->sreg2 + 1].born_in = i;
1461                         }
1462                         if (spec [MONO_INST_CLOB] == 's') {
1463                                 reginfo2 [ins->sreg1].flags |= MONO_X86_REG_NOT_ECX;
1464                                 reginfo2 [ins->sreg2].flags |= MONO_X86_REG_ECX;
1465                         }
1466                 } else {
1467                         ins->sreg2 = -1;
1468                 }
1469                 if (spec [MONO_INST_DEST]) {
1470                         if (spec [MONO_INST_DEST] == 'f') {
1471                                 reginfod = reginfof;
1472                                 if (fpcount >= MONO_MAX_FREGS) {
1473                                         reginfod [ins->dreg].flags |= MONO_X86_FP_NEEDS_SPILL;
1474                                         fspill++;
1475                                         fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1476                                         fpcount--;
1477                                 }
1478                                 fpcount++;
1479                         }
1480                         else
1481                                 reginfod = reginfo;
1482                         if (spec [MONO_INST_DEST] != 'b') /* it's not just a base register */
1483                                 reginfod [ins->dreg].killed_in = i;
1484                         reginfod [ins->dreg].prev_use = reginfod [ins->dreg].last_use;
1485                         reginfod [ins->dreg].last_use = i;
1486                         if (reginfod [ins->dreg].born_in == 0 || reginfod [ins->dreg].born_in > i)
1487                                 reginfod [ins->dreg].born_in = i;
1488                         if (spec [MONO_INST_DEST] == 'l' || spec [MONO_INST_DEST] == 'L') {
1489                                 /* The virtual register is allocated sequentially */
1490                                 reginfod [ins->dreg + 1].prev_use = reginfod [ins->dreg + 1].last_use;
1491                                 reginfod [ins->dreg + 1].last_use = i;
1492                                 if (reginfod [ins->dreg + 1].born_in == 0 || reginfod [ins->dreg + 1].born_in > i)
1493                                         reginfod [ins->dreg + 1].born_in = i;
1494
1495                                 reginfod [ins->dreg].flags |= MONO_X86_REG_EAX;
1496                                 reginfod [ins->dreg + 1].flags |= MONO_X86_REG_EDX;
1497                         }
1498                 } else {
1499                         ins->dreg = -1;
1500                 }
1501
1502                 reversed = inst_list_prepend (cfg->mempool, reversed, ins);
1503                 ++i;
1504                 ins = ins->next;
1505         }
1506
1507         // todo: check if we have anything left on fp stack, in verify mode?
1508         fspill = 0;
1509
1510         DEBUG (print_regtrack (reginfo, rs->next_vireg));
1511         DEBUG (print_regtrack (reginfof, rs->next_vfreg));
1512         tmp = reversed;
1513         while (tmp) {
1514                 int prev_dreg, prev_sreg1, prev_sreg2, clob_dreg;
1515                 dest_mask = src1_mask = src2_mask = X86_CALLEE_REGS;
1516                 --i;
1517                 ins = tmp->data;
1518                 spec = ins_spec [ins->opcode];
1519                 prev_dreg = -1;
1520                 clob_dreg = -1;
1521                 DEBUG (g_print ("processing:"));
1522                 DEBUG (print_ins (i, ins));
1523                 if (spec [MONO_INST_CLOB] == 's') {
1524                         if (rs->ifree_mask & (1 << X86_ECX)) {
1525                                 DEBUG (g_print ("\tshortcut assignment of R%d to ECX\n", ins->sreg2));
1526                                 rs->iassign [ins->sreg2] = X86_ECX;
1527                                 rs->isymbolic [X86_ECX] = ins->sreg2;
1528                                 ins->sreg2 = X86_ECX;
1529                                 rs->ifree_mask &= ~ (1 << X86_ECX);
1530                         } else {
1531                                 int need_ecx_spill = TRUE;
1532                                 /*
1533                                  * we first check if src1/dreg is already assigned a register
1534                                  * and then we force a spill of the var assigned to ECX.
1535                                  */
1536                                 /* the destination register can't be ECX */
1537                                 dest_mask &= ~ (1 << X86_ECX);
1538                                 src1_mask &= ~ (1 << X86_ECX);
1539                                 val = rs->iassign [ins->dreg];
1540                                 /*
1541                                  * the destination register is already assigned to ECX:
1542                                  * we need to allocate another register for it and then
1543                                  * copy from this to ECX.
1544                                  */
1545                                 if (val == X86_ECX && ins->dreg != ins->sreg2) {
1546                                         int new_dest;
1547                                         new_dest = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, ins->dreg, reginfo [ins->dreg].flags);
1548                                         g_assert (new_dest >= 0);
1549                                         DEBUG (g_print ("\tclob:s changing dreg R%d to %s from ECX\n", ins->dreg, mono_arch_regname (new_dest)));
1550
1551                                         rs->isymbolic [new_dest] = ins->dreg;
1552                                         rs->iassign [ins->dreg] = new_dest;
1553                                         clob_dreg = ins->dreg;
1554                                         ins->dreg = new_dest;
1555                                         create_copy_ins (cfg, X86_ECX, new_dest, ins);
1556                                         need_ecx_spill = FALSE;
1557                                         /*DEBUG (g_print ("\tforced spill of R%d\n", ins->dreg));
1558                                         val = get_register_force_spilling (cfg, tmp, ins, ins->dreg);
1559                                         rs->iassign [ins->dreg] = val;
1560                                         rs->isymbolic [val] = prev_dreg;
1561                                         ins->dreg = val;*/
1562                                 }
1563                                 val = rs->iassign [ins->sreg1];
1564                                 if (val == X86_ECX) {
1565                                         g_assert_not_reached ();
1566                                 } else if (val >= 0) {
1567                                         /*
1568                                          * the first src reg was already assigned to a register,
1569                                          * we need to copy it to the dest register because the
1570                                          * shift instruction clobbers the first operand.
1571                                          */
1572                                         MonoInst *copy = create_copy_ins (cfg, ins->dreg, val, NULL);
1573                                         DEBUG (g_print ("\tclob:s moved sreg1 from R%d to R%d\n", val, ins->dreg));
1574                                         insert_before_ins (ins, tmp, copy);
1575                                 }
1576                                 val = rs->iassign [ins->sreg2];
1577                                 if (val >= 0 && val != X86_ECX) {
1578                                         MonoInst *move = create_copy_ins (cfg, X86_ECX, val, NULL);
1579                                         DEBUG (g_print ("\tmoved arg from R%d (%d) to ECX\n", val, ins->sreg2));
1580                                         move->next = ins;
1581                                         g_assert_not_reached ();
1582                                         /* FIXME: where is move connected to the instruction list? */
1583                                         //tmp->prev->data->next = move;
1584                                 }
1585                                 if (need_ecx_spill && !(rs->ifree_mask & (1 << X86_ECX))) {
1586                                         DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [X86_ECX]));
1587                                         get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_ECX]);
1588                                         mono_regstate_free_int (rs, X86_ECX);
1589                                 }
1590                                 /* force-set sreg2 */
1591                                 rs->iassign [ins->sreg2] = X86_ECX;
1592                                 rs->isymbolic [X86_ECX] = ins->sreg2;
1593                                 ins->sreg2 = X86_ECX;
1594                                 rs->ifree_mask &= ~ (1 << X86_ECX);
1595                         }
1596                 } else if (spec [MONO_INST_CLOB] == 'd') { /* division */
1597                         int dest_reg = X86_EAX;
1598                         int clob_reg = X86_EDX;
1599                         if (spec [MONO_INST_DEST] == 'd') {
1600                                 dest_reg = X86_EDX; /* reminder */
1601                                 clob_reg = X86_EAX;
1602                         }
1603                         val = rs->iassign [ins->dreg];
1604                         if (0 && val >= 0 && val != dest_reg && !(rs->ifree_mask & (1 << dest_reg))) {
1605                                 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [dest_reg]));
1606                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [dest_reg]);
1607                                 mono_regstate_free_int (rs, dest_reg);
1608                         }
1609                         if (val < 0) {
1610                                 if (val < -1) {
1611                                         /* the register gets spilled after this inst */
1612                                         int spill = -val -1;
1613                                         dest_mask = 1 << clob_reg;
1614                                         prev_dreg = ins->dreg;
1615                                         val = mono_regstate_alloc_int (rs, dest_mask);
1616                                         if (val < 0)
1617                                                 val = get_register_spilling (cfg, tmp, ins, dest_mask, ins->dreg);
1618                                         rs->iassign [ins->dreg] = val;
1619                                         if (spill)
1620                                                 create_spilled_store (cfg, spill, val, prev_dreg, ins);
1621                                         DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_arch_regname (val), ins->dreg));
1622                                         rs->isymbolic [val] = prev_dreg;
1623                                         ins->dreg = val;
1624                                         if (val != dest_reg) { /* force a copy */
1625                                                 create_copy_ins (cfg, val, dest_reg, ins);
1626                                         }
1627                                 } else {
1628                                         DEBUG (g_print ("\tshortcut assignment of R%d to %s\n", ins->dreg, mono_arch_regname (dest_reg)));
1629                                         prev_dreg = ins->dreg;
1630                                         rs->iassign [ins->dreg] = dest_reg;
1631                                         rs->isymbolic [dest_reg] = ins->dreg;
1632                                         ins->dreg = dest_reg;
1633                                         rs->ifree_mask &= ~ (1 << dest_reg);
1634                                 }
1635                         } else {
1636                                 //DEBUG (g_print ("dest reg in div assigned: %s\n", mono_arch_regname (val)));
1637                                 if (val != dest_reg) { /* force a copy */
1638                                         create_copy_ins (cfg, val, dest_reg, ins);
1639                                         if (!(rs->ifree_mask & (1 << dest_reg)) && rs->isymbolic [dest_reg] >= MONO_MAX_IREGS) {
1640                                                 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [dest_reg]));
1641                                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [dest_reg]);
1642                                                 mono_regstate_free_int (rs, dest_reg);
1643                                         }
1644                                 }
1645                         }
1646                         if (!(rs->ifree_mask & (1 << clob_reg)) && (clob_reg != val) && (rs->isymbolic [clob_reg] >= 8)) {
1647                                 DEBUG (g_print ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1648                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [clob_reg]);
1649                                 mono_regstate_free_int (rs, clob_reg);
1650                         }
1651                         src1_mask = 1 << X86_EAX;
1652                         src2_mask = 1 << X86_ECX;
1653                 }
1654                 if (spec [MONO_INST_DEST] == 'l') {
1655                         int hreg;
1656                         val = rs->iassign [ins->dreg];
1657                         /* check special case when dreg have been moved from ecx (clob shift) */
1658                         if (spec [MONO_INST_CLOB] == 's' && clob_dreg != -1)
1659                                 hreg = clob_dreg + 1;
1660                         else
1661                                 hreg = ins->dreg + 1;
1662
1663                         /* base prev_dreg on fixed hreg, handle clob case */
1664                         val = hreg - 1;
1665
1666                         if (val != rs->isymbolic [X86_EAX] && !(rs->ifree_mask & (1 << X86_EAX))) {
1667                                 DEBUG (g_print ("\t(long-low) forced spill of R%d\n", rs->isymbolic [X86_EAX]));
1668                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_EAX]);
1669                                 mono_regstate_free_int (rs, X86_EAX);
1670                         }
1671                         if (hreg != rs->isymbolic [X86_EDX] && !(rs->ifree_mask & (1 << X86_EDX))) {
1672                                 DEBUG (g_print ("\t(long-high) forced spill of R%d\n", rs->isymbolic [X86_EDX]));
1673                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_EDX]);
1674                                 mono_regstate_free_int (rs, X86_EDX);
1675                         }
1676                 }
1677
1678                 /* Track dreg */
1679                 if (spec [MONO_INST_DEST] == 'f') {
1680                         if (reginfof [ins->dreg].flags & MONO_X86_FP_NEEDS_SPILL) {
1681                                 GList *spill_node;
1682                                 MonoInst *store;
1683                                 spill_node = g_list_first (fspill_list);
1684                                 g_assert (spill_node);
1685
1686                                 store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->dreg, ins);
1687                                 insert_before_ins (ins, tmp, store);
1688                                 fspill_list = g_list_remove (fspill_list, spill_node->data);
1689                                 fspill--;
1690                         }
1691                 } else if (spec [MONO_INST_DEST] == 'L') {
1692                         int hreg;
1693                         val = rs->iassign [ins->dreg];
1694                         /* check special case when dreg have been moved from ecx (clob shift) */
1695                         if (spec [MONO_INST_CLOB] == 's' && clob_dreg != -1)
1696                                 hreg = clob_dreg + 1;
1697                         else
1698                                 hreg = ins->dreg + 1;
1699
1700                         /* base prev_dreg on fixed hreg, handle clob case */
1701                         prev_dreg = hreg - 1;
1702
1703                         if (val < 0) {
1704                                 int spill = 0;
1705                                 if (val < -1) {
1706                                         /* the register gets spilled after this inst */
1707                                         spill = -val -1;
1708                                 }
1709                                 val = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, ins->dreg, reginfo [ins->dreg].flags);
1710                                 rs->iassign [ins->dreg] = val;
1711                                 if (spill)
1712                                         create_spilled_store (cfg, spill, val, prev_dreg, ins);
1713                         }
1714
1715                         DEBUG (g_print ("\tassigned dreg (long) %s to dest R%d\n", mono_arch_regname (val), hreg - 1));
1716
1717                         rs->isymbolic [val] = hreg - 1;
1718                         ins->dreg = val;
1719
1720                         val = rs->iassign [hreg];
1721                         if (val < 0) {
1722                                 int spill = 0;
1723                                 if (val < -1) {
1724                                         /* the register gets spilled after this inst */
1725                                         spill = -val -1;
1726                                 }
1727                                 val = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, hreg, reginfo [hreg].flags);
1728                                 rs->iassign [hreg] = val;
1729                                 if (spill)
1730                                         create_spilled_store (cfg, spill, val, hreg, ins);
1731                         }
1732
1733                         DEBUG (g_print ("\tassigned hreg (long-high) %s to dest R%d\n", mono_arch_regname (val), hreg));
1734                         rs->isymbolic [val] = hreg;
1735                         /* save reg allocating into unused */
1736                         ins->unused = val;
1737
1738                         /* check if we can free our long reg */
1739                         if (reg_is_freeable (val) && hreg >= 0 && reginfo [hreg].born_in >= i) {
1740                                 DEBUG (g_print ("\tfreeable %s (R%d) (born in %d)\n", mono_arch_regname (val), hreg, reginfo [hreg].born_in));
1741                                 mono_regstate_free_int (rs, val);
1742                         }
1743                 }
1744                 else if (ins->dreg >= MONO_MAX_IREGS) {
1745                         int hreg;
1746                         val = rs->iassign [ins->dreg];
1747                         if (spec [MONO_INST_DEST] == 'l') {
1748                                 /* check special case when dreg have been moved from ecx (clob shift) */
1749                                 if (spec [MONO_INST_CLOB] == 's' && clob_dreg != -1)
1750                                         hreg = clob_dreg + 1;
1751                                 else
1752                                         hreg = ins->dreg + 1;
1753
1754                                 /* base prev_dreg on fixed hreg, handle clob case */
1755                                 prev_dreg = hreg - 1;
1756                         } else
1757                                 prev_dreg = ins->dreg;
1758
1759                         if (val < 0) {
1760                                 int spill = 0;
1761                                 if (val < -1) {
1762                                         /* the register gets spilled after this inst */
1763                                         spill = -val -1;
1764                                 }
1765                                 val = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, ins->dreg, reginfo [ins->dreg].flags);
1766                                 rs->iassign [ins->dreg] = val;
1767                                 if (spill)
1768                                         create_spilled_store (cfg, spill, val, prev_dreg, ins);
1769                         }
1770                         DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_arch_regname (val), ins->dreg));
1771                         rs->isymbolic [val] = prev_dreg;
1772                         ins->dreg = val;
1773                         /* handle cases where lreg needs to be eax:edx */
1774                         if (spec [MONO_INST_DEST] == 'l') {
1775                                 /* check special case when dreg have been moved from ecx (clob shift) */
1776                                 int hreg = prev_dreg + 1;
1777                                 val = rs->iassign [hreg];
1778                                 if (val < 0) {
1779                                         int spill = 0;
1780                                         if (val < -1) {
1781                                                 /* the register gets spilled after this inst */
1782                                                 spill = -val -1;
1783                                         }
1784                                         val = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, hreg, reginfo [hreg].flags);
1785                                         rs->iassign [hreg] = val;
1786                                         if (spill)
1787                                                 create_spilled_store (cfg, spill, val, hreg, ins);
1788                                 }
1789                                 DEBUG (g_print ("\tassigned hreg %s to dest R%d\n", mono_arch_regname (val), hreg));
1790                                 rs->isymbolic [val] = hreg;
1791                                 if (ins->dreg == X86_EAX) {
1792                                         if (val != X86_EDX)
1793                                                 create_copy_ins (cfg, val, X86_EDX, ins);
1794                                 } else if (ins->dreg == X86_EDX) {
1795                                         if (val == X86_EAX) {
1796                                                 /* swap */
1797                                                 g_assert_not_reached ();
1798                                         } else {
1799                                                 /* two forced copies */
1800                                                 create_copy_ins (cfg, val, X86_EDX, ins);
1801                                                 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1802                                         }
1803                                 } else {
1804                                         if (val == X86_EDX) {
1805                                                 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1806                                         } else {
1807                                                 /* two forced copies */
1808                                                 create_copy_ins (cfg, val, X86_EDX, ins);
1809                                                 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1810                                         }
1811                                 }
1812                                 if (reg_is_freeable (val) && hreg >= 0 && reginfo [hreg].born_in >= i) {
1813                                         DEBUG (g_print ("\tfreeable %s (R%d)\n", mono_arch_regname (val), hreg));
1814                                         mono_regstate_free_int (rs, val);
1815                                 }
1816                         } else if (spec [MONO_INST_DEST] == 'a' && ins->dreg != X86_EAX && spec [MONO_INST_CLOB] != 'd') {
1817                                 /* this instruction only outputs to EAX, need to copy */
1818                                 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1819                         } else if (spec [MONO_INST_DEST] == 'd' && ins->dreg != X86_EDX && spec [MONO_INST_CLOB] != 'd') {
1820                                 create_copy_ins (cfg, ins->dreg, X86_EDX, ins);
1821                         }
1822                 }
1823                 if (spec [MONO_INST_DEST] != 'f' && reg_is_freeable (ins->dreg) && prev_dreg >= 0 && reginfo [prev_dreg].born_in >= i) {
1824                         DEBUG (g_print ("\tfreeable %s (R%d) (born in %d)\n", mono_arch_regname (ins->dreg), prev_dreg, reginfo [prev_dreg].born_in));
1825                         mono_regstate_free_int (rs, ins->dreg);
1826                 }
1827                 /* put src1 in EAX if it needs to be */
1828                 if (spec [MONO_INST_SRC1] == 'a') {
1829                         if (!(rs->ifree_mask & (1 << X86_EAX))) {
1830                                 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [X86_EAX]));
1831                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_EAX]);
1832                                 mono_regstate_free_int (rs, X86_EAX);
1833                         }
1834                         /* force-set sreg1 */
1835                         rs->iassign [ins->sreg1] = X86_EAX;
1836                         rs->isymbolic [X86_EAX] = ins->sreg1;
1837                         ins->sreg1 = X86_EAX;
1838                         rs->ifree_mask &= ~ (1 << X86_EAX);
1839                 }
1840
1841                 /* Track sreg1 */
1842                 if (spec [MONO_INST_SRC1] == 'f') {
1843                         if (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD) {
1844                                 MonoInst *load;
1845                                 MonoInst *store = NULL;
1846
1847                                 if (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD_SPILL) {
1848                                         GList *spill_node;
1849                                         spill_node = g_list_first (fspill_list);
1850                                         g_assert (spill_node);
1851
1852                                         store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->sreg1, ins);
1853                                         fspill_list = g_list_remove (fspill_list, spill_node->data);
1854                                 }
1855
1856                                 fspill++;
1857                                 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1858                                 load = create_spilled_load_float (cfg, fspill, ins->sreg1, ins);
1859                                 insert_before_ins (ins, tmp, load);
1860                                 if (store)
1861                                         insert_before_ins (load, tmp, store);
1862                         }
1863                 } else if ((spec [MONO_INST_DEST] == 'L') && (spec [MONO_INST_SRC1] == 'L')) {
1864                         /* force source to be same as dest */
1865                         rs->iassign [ins->sreg1] = ins->dreg;
1866                         rs->iassign [ins->sreg1 + 1] = ins->unused;
1867
1868                         DEBUG (g_print ("\tassigned sreg1 (long) %s to sreg1 R%d\n", mono_arch_regname (ins->dreg), ins->sreg1));
1869                         DEBUG (g_print ("\tassigned sreg1 (long-high) %s to sreg1 R%d\n", mono_arch_regname (ins->unused), ins->sreg1 + 1));
1870
1871                         ins->sreg1 = ins->dreg;
1872                         /*
1873                          * No need for saving the reg, we know that src1=dest in this cases
1874                          * ins->inst_c0 = ins->unused;
1875                          */
1876
1877                         /* make sure that we remove them from free mask */
1878                         rs->ifree_mask &= ~ (1 << ins->dreg);
1879                         rs->ifree_mask &= ~ (1 << ins->unused);
1880                 }
1881                 else if (ins->sreg1 >= MONO_MAX_IREGS) {
1882                         val = rs->iassign [ins->sreg1];
1883                         prev_sreg1 = ins->sreg1;
1884                         if (val < 0) {
1885                                 int spill = 0;
1886                                 if (val < -1) {
1887                                         /* the register gets spilled after this inst */
1888                                         spill = -val -1;
1889                                 }
1890                                 if (0 && ins->opcode == OP_MOVE) {
1891                                         /*
1892                                          * small optimization: the dest register is already allocated
1893                                          * but the src one is not: we can simply assign the same register
1894                                          * here and peephole will get rid of the instruction later.
1895                                          * This optimization may interfere with the clobbering handling:
1896                                          * it removes a mov operation that will be added again to handle clobbering.
1897                                          * There are also some other issues that should with make testjit.
1898                                          */
1899                                         mono_regstate_alloc_int (rs, 1 << ins->dreg);
1900                                         val = rs->iassign [ins->sreg1] = ins->dreg;
1901                                         //g_assert (val >= 0);
1902                                         DEBUG (g_print ("\tfast assigned sreg1 %s to R%d\n", mono_arch_regname (val), ins->sreg1));
1903                                 } else {
1904                                         //g_assert (val == -1); /* source cannot be spilled */
1905                                         val = mono_x86_alloc_int_reg (cfg, tmp, ins, src1_mask, ins->sreg1, reginfo [ins->sreg1].flags);
1906                                         rs->iassign [ins->sreg1] = val;
1907                                         DEBUG (g_print ("\tassigned sreg1 %s to R%d\n", mono_arch_regname (val), ins->sreg1));
1908                                 }
1909                                 if (spill) {
1910                                         MonoInst *store = create_spilled_store (cfg, spill, val, prev_sreg1, NULL);
1911                                         insert_before_ins (ins, tmp, store);
1912                                 }
1913                         }
1914                         rs->isymbolic [val] = prev_sreg1;
1915                         ins->sreg1 = val;
1916                 } else {
1917                         prev_sreg1 = -1;
1918                 }
1919                 /* handle clobbering of sreg1 */
1920                 if ((spec [MONO_INST_CLOB] == '1' || spec [MONO_INST_CLOB] == 's') && ins->dreg != ins->sreg1) {
1921                         MonoInst *copy = create_copy_ins (cfg, ins->dreg, ins->sreg1, NULL);
1922                         DEBUG (g_print ("\tneed to copy sreg1 %s to dreg %s\n", mono_arch_regname (ins->sreg1), mono_arch_regname (ins->dreg)));
1923                         if (ins->sreg2 == -1 || spec [MONO_INST_CLOB] == 's') {
1924                                 /* note: the copy is inserted before the current instruction! */
1925                                 insert_before_ins (ins, tmp, copy);
1926                                 /* we set sreg1 to dest as well */
1927                                 prev_sreg1 = ins->sreg1 = ins->dreg;
1928                         } else {
1929                                 /* inserted after the operation */
1930                                 copy->next = ins->next;
1931                                 ins->next = copy;
1932                         }
1933                 }
1934                 /* track sreg2 */
1935                 if (spec [MONO_INST_SRC2] == 'f') {
1936                         if (reginfof [ins->sreg2].flags & MONO_X86_FP_NEEDS_LOAD) {
1937                                 MonoInst *load;
1938                                 MonoInst *store = NULL;
1939
1940                                 if (reginfof [ins->sreg2].flags & MONO_X86_FP_NEEDS_LOAD_SPILL) {
1941                                         GList *spill_node;
1942
1943                                         spill_node = g_list_first (fspill_list);
1944                                         g_assert (spill_node);
1945                                         if (spec [MONO_INST_SRC1] == 'f' && (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD_SPILL))
1946                                                 spill_node = g_list_next (spill_node);
1947
1948                                         store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->sreg2, ins);
1949                                         fspill_list = g_list_remove (fspill_list, spill_node->data);
1950                                 }
1951
1952                                 fspill++;
1953                                 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1954                                 load = create_spilled_load_float (cfg, fspill, ins->sreg2, ins);
1955                                 insert_before_ins (ins, tmp, load);
1956                                 if (store)
1957                                         insert_before_ins (load, tmp, store);
1958                         }
1959                 }
1960                 else if (ins->sreg2 >= MONO_MAX_IREGS) {
1961                         val = rs->iassign [ins->sreg2];
1962                         prev_sreg2 = ins->sreg2;
1963                         if (val < 0) {
1964                                 int spill = 0;
1965                                 if (val < -1) {
1966                                         /* the register gets spilled after this inst */
1967                                         spill = -val -1;
1968                                 }
1969                                 val = mono_x86_alloc_int_reg (cfg, tmp, ins, src2_mask, ins->sreg2, reginfo [ins->sreg2].flags);
1970                                 rs->iassign [ins->sreg2] = val;
1971                                 DEBUG (g_print ("\tassigned sreg2 %s to R%d\n", mono_arch_regname (val), ins->sreg2));
1972                                 if (spill)
1973                                         create_spilled_store (cfg, spill, val, prev_sreg2, ins);
1974                         }
1975                         rs->isymbolic [val] = prev_sreg2;
1976                         ins->sreg2 = val;
1977                         if (spec [MONO_INST_CLOB] == 's' && ins->sreg2 != X86_ECX) {
1978                                 DEBUG (g_print ("\tassigned sreg2 %s to R%d, but ECX is needed (R%d)\n", mono_arch_regname (val), ins->sreg2, rs->iassign [X86_ECX]));
1979                         }
1980                 } else {
1981                         prev_sreg2 = -1;
1982                 }
1983
1984                 if (spec [MONO_INST_CLOB] == 'c') {
1985                         int j, s;
1986                         guint32 clob_mask = X86_CALLEE_REGS;
1987                         for (j = 0; j < MONO_MAX_IREGS; ++j) {
1988                                 s = 1 << j;
1989                                 if ((clob_mask & s) && !(rs->ifree_mask & s) && j != ins->sreg1) {
1990                                         //g_warning ("register %s busy at call site\n", mono_arch_regname (j));
1991                                 }
1992                         }
1993                 }
1994                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
1995                         DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg1)));
1996                         mono_regstate_free_int (rs, ins->sreg1);
1997                 }
1998                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
1999                         DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2000                         mono_regstate_free_int (rs, ins->sreg2);
2001                 }*/
2002
2003                 //DEBUG (print_ins (i, ins));
2004                 /* this may result from a insert_before call */
2005                 if (!tmp->next)
2006                         bb->code = tmp->data;
2007                 tmp = tmp->next;
2008         }
2009
2010         g_free (reginfo);
2011         g_free (reginfof);
2012         g_list_free (fspill_list);
2013 }
2014
2015 static unsigned char*
2016 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2017 {
2018         x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2019         x86_fnstcw_membase(code, X86_ESP, 0);
2020         x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2021         x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2022         x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2023         x86_fldcw_membase (code, X86_ESP, 2);
2024         if (size == 8) {
2025                 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2026                 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2027                 x86_pop_reg (code, dreg);
2028                 /* FIXME: need the high register
2029                  * x86_pop_reg (code, dreg_high);
2030                  */
2031         } else {
2032                 x86_push_reg (code, X86_EAX); // SP = SP - 4
2033                 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2034                 x86_pop_reg (code, dreg);
2035         }
2036         x86_fldcw_membase (code, X86_ESP, 0);
2037         x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2038
2039         if (size == 1)
2040                 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2041         else if (size == 2)
2042                 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2043         return code;
2044 }
2045
2046 static unsigned char*
2047 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2048 {
2049         int sreg = tree->sreg1;
2050 #ifdef PLATFORM_WIN32
2051         guint8* br[5];
2052
2053         /*
2054          * Under Windows:
2055          * If requested stack size is larger than one page,
2056          * perform stack-touch operation
2057          */
2058         /*
2059          * Generate stack probe code.
2060          * Under Windows, it is necessary to allocate one page at a time,
2061          * "touching" stack after each successful sub-allocation. This is
2062          * because of the way stack growth is implemented - there is a
2063          * guard page before the lowest stack page that is currently commited.
2064          * Stack normally grows sequentially so OS traps access to the
2065          * guard page and commits more pages when needed.
2066          */
2067         x86_test_reg_imm (code, sreg, ~0xFFF);
2068         br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2069
2070         br[2] = code; /* loop */
2071         x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2072         x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2073         x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2074         x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2075         br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2076         x86_patch (br[3], br[2]);
2077         x86_test_reg_reg (code, sreg, sreg);
2078         br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2079         x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2080
2081         br[1] = code; x86_jump8 (code, 0);
2082
2083         x86_patch (br[0], code);
2084         x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2085         x86_patch (br[1], code);
2086         x86_patch (br[4], code);
2087 #else /* PLATFORM_WIN32 */
2088         x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2089 #endif
2090         if (tree->flags & MONO_INST_INIT) {
2091                 int offset = 0;
2092                 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2093                         x86_push_reg (code, X86_EAX);
2094                         offset += 4;
2095                 }
2096                 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2097                         x86_push_reg (code, X86_ECX);
2098                         offset += 4;
2099                 }
2100                 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2101                         x86_push_reg (code, X86_EDI);
2102                         offset += 4;
2103                 }
2104
2105                 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2106                 if (sreg != X86_ECX)
2107                         x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2108                 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2109
2110                 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2111                 x86_cld (code);
2112                 x86_prefix (code, X86_REP_PREFIX);
2113                 x86_stosl (code);
2114
2115                 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2116                         x86_pop_reg (code, X86_EDI);
2117                 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2118                         x86_pop_reg (code, X86_ECX);
2119                 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2120                         x86_pop_reg (code, X86_EAX);
2121         }
2122         return code;
2123 }
2124
2125 #define REAL_PRINT_REG(text,reg) \
2126 mono_assert (reg >= 0); \
2127 x86_push_reg (code, X86_EAX); \
2128 x86_push_reg (code, X86_EDX); \
2129 x86_push_reg (code, X86_ECX); \
2130 x86_push_reg (code, reg); \
2131 x86_push_imm (code, reg); \
2132 x86_push_imm (code, text " %d %p\n"); \
2133 x86_mov_reg_imm (code, X86_EAX, printf); \
2134 x86_call_reg (code, X86_EAX); \
2135 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2136 x86_pop_reg (code, X86_ECX); \
2137 x86_pop_reg (code, X86_EDX); \
2138 x86_pop_reg (code, X86_EAX);
2139
2140 /* benchmark and set based on cpu */
2141 #define LOOP_ALIGNMENT 8
2142 #define bb_is_loop_start(bb) ((bb)->nesting && ((bb)->in_count == 1))
2143
2144 void
2145 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2146 {
2147         MonoInst *ins;
2148         MonoCallInst *call;
2149         guint offset;
2150         guint8 *code = cfg->native_code + cfg->code_len;
2151         MonoInst *last_ins = NULL;
2152         guint last_offset = 0;
2153         int max_len, cpos;
2154
2155         if (cfg->opt & MONO_OPT_PEEPHOLE)
2156                 peephole_pass (cfg, bb);
2157
2158         if (cfg->opt & MONO_OPT_LOOP) {
2159                 int pad, align = LOOP_ALIGNMENT;
2160                 /* set alignment depending on cpu */
2161                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2162                         pad = align - pad;
2163                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2164                         x86_padding (code, pad);
2165                         cfg->code_len += pad;
2166                         bb->native_offset = cfg->code_len;
2167                 }
2168         }
2169
2170         if (cfg->verbose_level > 2)
2171                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2172
2173         cpos = bb->max_offset;
2174
2175         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2176                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2177                 g_assert (!mono_compile_aot);
2178                 cpos += 6;
2179
2180                 cov->data [bb->dfn].cil_code = bb->cil_code;
2181                 /* this is not thread save, but good enough */
2182                 x86_inc_mem (code, &cov->data [bb->dfn].count);
2183         }
2184
2185         offset = code - cfg->native_code;
2186
2187         ins = bb->code;
2188         while (ins) {
2189                 offset = code - cfg->native_code;
2190
2191                 max_len = ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
2192
2193                 if (offset > (cfg->code_size - max_len - 16)) {
2194                         cfg->code_size *= 2;
2195                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2196                         code = cfg->native_code + offset;
2197                         mono_jit_stats.code_reallocs++;
2198                 }
2199
2200                 mono_debug_record_line_number (cfg, ins, offset);
2201
2202                 switch (ins->opcode) {
2203                 case OP_BIGMUL:
2204                         x86_mul_reg (code, ins->sreg2, TRUE);
2205                         break;
2206                 case OP_BIGMUL_UN:
2207                         x86_mul_reg (code, ins->sreg2, FALSE);
2208                         break;
2209                 case OP_X86_SETEQ_MEMBASE:
2210                         x86_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2211                         break;
2212                 case OP_STOREI1_MEMBASE_IMM:
2213                         x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2214                         break;
2215                 case OP_STOREI2_MEMBASE_IMM:
2216                         x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2217                         break;
2218                 case OP_STORE_MEMBASE_IMM:
2219                 case OP_STOREI4_MEMBASE_IMM:
2220                         x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2221                         break;
2222                 case OP_STOREI1_MEMBASE_REG:
2223                         x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2224                         break;
2225                 case OP_STOREI2_MEMBASE_REG:
2226                         x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2227                         break;
2228                 case OP_STORE_MEMBASE_REG:
2229                 case OP_STOREI4_MEMBASE_REG:
2230                         x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2231                         break;
2232                 case CEE_LDIND_I:
2233                 case CEE_LDIND_I4:
2234                 case CEE_LDIND_U4:
2235                         x86_mov_reg_mem (code, ins->dreg, ins->inst_p0, 4);
2236                         break;
2237                 case OP_LOADU4_MEM:
2238                         x86_mov_reg_imm (code, ins->dreg, ins->inst_p0);
2239                         x86_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2240                         break;
2241                 case OP_LOAD_MEMBASE:
2242                 case OP_LOADI4_MEMBASE:
2243                 case OP_LOADU4_MEMBASE:
2244                         x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2245                         break;
2246                 case OP_LOADU1_MEMBASE:
2247                         x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2248                         break;
2249                 case OP_LOADI1_MEMBASE:
2250                         x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2251                         break;
2252                 case OP_LOADU2_MEMBASE:
2253                         x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2254                         break;
2255                 case OP_LOADI2_MEMBASE:
2256                         x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2257                         break;
2258                 case CEE_CONV_I1:
2259                         x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2260                         break;
2261                 case CEE_CONV_I2:
2262                         x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2263                         break;
2264                 case CEE_CONV_U1:
2265                         x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2266                         break;
2267                 case CEE_CONV_U2:
2268                         x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2269                         break;
2270                 case OP_COMPARE:
2271                         x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2272                         break;
2273                 case OP_COMPARE_IMM:
2274                         x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2275                         break;
2276                 case OP_X86_COMPARE_MEMBASE_REG:
2277                         x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2278                         break;
2279                 case OP_X86_COMPARE_MEMBASE_IMM:
2280                         x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2281                         break;
2282                 case OP_X86_COMPARE_REG_MEMBASE:
2283                         x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2284                         break;
2285                 case OP_X86_TEST_NULL:
2286                         x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2287                         break;
2288                 case OP_X86_ADD_MEMBASE_IMM:
2289                         x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2290                         break;
2291                 case OP_X86_ADD_MEMBASE:
2292                         x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2293                         break;
2294                 case OP_X86_SUB_MEMBASE_IMM:
2295                         x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2296                         break;
2297                 case OP_X86_SUB_MEMBASE:
2298                         x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2299                         break;
2300                 case OP_X86_INC_MEMBASE:
2301                         x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2302                         break;
2303                 case OP_X86_INC_REG:
2304                         x86_inc_reg (code, ins->dreg);
2305                         break;
2306                 case OP_X86_DEC_MEMBASE:
2307                         x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2308                         break;
2309                 case OP_X86_DEC_REG:
2310                         x86_dec_reg (code, ins->dreg);
2311                         break;
2312                 case OP_X86_MUL_MEMBASE:
2313                         x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2314                         break;
2315                 case CEE_BREAK:
2316                         x86_breakpoint (code);
2317                         break;
2318                 case OP_ADDCC:
2319                 case CEE_ADD:
2320                         x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2321                         break;
2322                 case OP_ADC:
2323                         x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2324                         break;
2325                 case OP_ADD_IMM:
2326                         x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2327                         break;
2328                 case OP_ADC_IMM:
2329                         x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2330                         break;
2331                 case OP_SUBCC:
2332                 case CEE_SUB:
2333                         x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2334                         break;
2335                 case OP_SBB:
2336                         x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2337                         break;
2338                 case OP_SUB_IMM:
2339                         x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2340                         break;
2341                 case OP_SBB_IMM:
2342                         x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2343                         break;
2344                 case CEE_AND:
2345                         x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2346                         break;
2347                 case OP_AND_IMM:
2348                         x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2349                         break;
2350                 case CEE_DIV:
2351                         x86_cdq (code);
2352                         x86_div_reg (code, ins->sreg2, TRUE);
2353                         break;
2354                 case CEE_DIV_UN:
2355                         x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2356                         x86_div_reg (code, ins->sreg2, FALSE);
2357                         break;
2358                 case OP_DIV_IMM:
2359                         x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2360                         x86_cdq (code);
2361                         x86_div_reg (code, ins->sreg2, TRUE);
2362                         break;
2363                 case CEE_REM:
2364                         x86_cdq (code);
2365                         x86_div_reg (code, ins->sreg2, TRUE);
2366                         break;
2367                 case CEE_REM_UN:
2368                         x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2369                         x86_div_reg (code, ins->sreg2, FALSE);
2370                         break;
2371                 case OP_REM_IMM:
2372                         x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2373                         x86_cdq (code);
2374                         x86_div_reg (code, ins->sreg2, TRUE);
2375                         break;
2376                 case CEE_OR:
2377                         x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2378                         break;
2379                 case OP_OR_IMM:
2380                         x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2381                         break;
2382                 case CEE_XOR:
2383                         x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2384                         break;
2385                 case OP_XOR_IMM:
2386                         x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2387                         break;
2388                 case CEE_SHL:
2389                         g_assert (ins->sreg2 == X86_ECX);
2390                         x86_shift_reg (code, X86_SHL, ins->dreg);
2391                         break;
2392                 case CEE_SHR:
2393                         g_assert (ins->sreg2 == X86_ECX);
2394                         x86_shift_reg (code, X86_SAR, ins->dreg);
2395                         break;
2396                 case OP_SHR_IMM:
2397                         x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2398                         break;
2399                 case OP_SHR_UN_IMM:
2400                         x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2401                         break;
2402                 case CEE_SHR_UN:
2403                         g_assert (ins->sreg2 == X86_ECX);
2404                         x86_shift_reg (code, X86_SHR, ins->dreg);
2405                         break;
2406                 case OP_SHL_IMM:
2407                         x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2408                         break;
2409                 case OP_LSHL: {
2410                         guint8 *jump_to_end;
2411
2412                         /* handle shifts below 32 bits */
2413                         x86_shld_reg (code, ins->unused, ins->sreg1);
2414                         x86_shift_reg (code, X86_SHL, ins->sreg1);
2415
2416                         x86_test_reg_imm (code, X86_ECX, 32);
2417                         jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2418
2419                         /* handle shift over 32 bit */
2420                         x86_mov_reg_reg (code, ins->unused, ins->sreg1, 4);
2421                         x86_clear_reg (code, ins->sreg1);
2422
2423                         x86_patch (jump_to_end, code);
2424                         }
2425                         break;
2426                 case OP_LSHR: {
2427                         guint8 *jump_to_end;
2428
2429                         /* handle shifts below 32 bits */
2430                         x86_shrd_reg (code, ins->sreg1, ins->unused);
2431                         x86_shift_reg (code, X86_SAR, ins->unused);
2432
2433                         x86_test_reg_imm (code, X86_ECX, 32);
2434                         jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2435
2436                         /* handle shifts over 31 bits */
2437                         x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
2438                         x86_shift_reg_imm (code, X86_SAR, ins->unused, 31);
2439
2440                         x86_patch (jump_to_end, code);
2441                         }
2442                         break;
2443                 case OP_LSHR_UN: {
2444                         guint8 *jump_to_end;
2445
2446                         /* handle shifts below 32 bits */
2447                         x86_shrd_reg (code, ins->sreg1, ins->unused);
2448                         x86_shift_reg (code, X86_SHR, ins->unused);
2449
2450                         x86_test_reg_imm (code, X86_ECX, 32);
2451                         jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2452
2453                         /* handle shifts over 31 bits */
2454                         x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
2455                         x86_shift_reg_imm (code, X86_SHR, ins->unused, 31);
2456
2457                         x86_patch (jump_to_end, code);
2458                         }
2459                         break;
2460                 case OP_LSHL_IMM:
2461                         if (ins->inst_imm >= 32) {
2462                                 x86_mov_reg_reg (code, ins->unused, ins->sreg1, 4);
2463                                 x86_clear_reg (code, ins->sreg1);
2464                                 x86_shift_reg_imm (code, X86_SHL, ins->unused, ins->inst_imm - 32);
2465                         } else {
2466                                 x86_shld_reg_imm (code, ins->unused, ins->sreg1, ins->inst_imm);
2467                                 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2468                         }
2469                         break;
2470                 case OP_LSHR_IMM:
2471                         if (ins->inst_imm >= 32) {
2472                                 x86_mov_reg_reg (code, ins->sreg1, ins->unused,  4);
2473                                 x86_shift_reg_imm (code, X86_SAR, ins->unused, 0x1f);
2474                                 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2475                         } else {
2476                                 x86_shrd_reg_imm (code, ins->sreg1, ins->unused, ins->inst_imm);
2477                                 x86_shift_reg_imm (code, X86_SAR, ins->unused, ins->inst_imm);
2478                         }
2479                         break;
2480                 case OP_LSHR_UN_IMM:
2481                         if (ins->inst_imm >= 32) {
2482                                 x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
2483                                 x86_clear_reg (code, ins->unused);
2484                                 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2485                         } else {
2486                                 x86_shrd_reg_imm (code, ins->sreg1, ins->unused, ins->inst_imm);
2487                                 x86_shift_reg_imm (code, X86_SHR, ins->unused, ins->inst_imm);
2488                         }
2489                         break;
2490                 case CEE_NOT:
2491                         x86_not_reg (code, ins->sreg1);
2492                         break;
2493                 case CEE_NEG:
2494                         x86_neg_reg (code, ins->sreg1);
2495                         break;
2496                 case OP_SEXT_I1:
2497                         x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2498                         break;
2499                 case OP_SEXT_I2:
2500                         x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2501                         break;
2502                 case CEE_MUL:
2503                         x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2504                         break;
2505                 case OP_MUL_IMM:
2506                         x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2507                         break;
2508                 case CEE_MUL_OVF:
2509                         x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2510                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2511                         break;
2512                 case CEE_MUL_OVF_UN: {
2513                         /* the mul operation and the exception check should most likely be split */
2514                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2515                         /*g_assert (ins->sreg2 == X86_EAX);
2516                         g_assert (ins->dreg == X86_EAX);*/
2517                         if (ins->sreg2 == X86_EAX) {
2518                                 non_eax_reg = ins->sreg1;
2519                         } else if (ins->sreg1 == X86_EAX) {
2520                                 non_eax_reg = ins->sreg2;
2521                         } else {
2522                                 /* no need to save since we're going to store to it anyway */
2523                                 if (ins->dreg != X86_EAX) {
2524                                         saved_eax = TRUE;
2525                                         x86_push_reg (code, X86_EAX);
2526                                 }
2527                                 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
2528                                 non_eax_reg = ins->sreg2;
2529                         }
2530                         if (ins->dreg == X86_EDX) {
2531                                 if (!saved_eax) {
2532                                         saved_eax = TRUE;
2533                                         x86_push_reg (code, X86_EAX);
2534                                 }
2535                         } else if (ins->dreg != X86_EAX) {
2536                                 saved_edx = TRUE;
2537                                 x86_push_reg (code, X86_EDX);
2538                         }
2539                         x86_mul_reg (code, non_eax_reg, FALSE);
2540                         /* save before the check since pop and mov don't change the flags */
2541                         if (ins->dreg != X86_EAX)
2542                                 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2543                         if (saved_edx)
2544                                 x86_pop_reg (code, X86_EDX);
2545                         if (saved_eax)
2546                                 x86_pop_reg (code, X86_EAX);
2547                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2548                         break;
2549                 }
2550                 case OP_ICONST:
2551                         x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
2552                         break;
2553                 case OP_AOTCONST:
2554                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2555                         x86_mov_reg_imm (code, ins->dreg, 0);
2556                         break;
2557                 case CEE_CONV_I4:
2558                 case OP_MOVE:
2559                         x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2560                         break;
2561                 case CEE_CONV_U4:
2562                         g_assert_not_reached ();
2563                 case CEE_JMP: {
2564                         /*
2565                          * Note: this 'frame destruction' logic is useful for tail calls, too.
2566                          * Keep in sync with the code in emit_epilog.
2567                          */
2568                         int pos = 0;
2569
2570                         /* FIXME: no tracing support... */
2571                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2572                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2573                         /* reset offset to make max_len work */
2574                         offset = code - cfg->native_code;
2575
2576                         g_assert (!cfg->method->save_lmf);
2577
2578                         if (cfg->used_int_regs & (1 << X86_EBX))
2579                                 pos -= 4;
2580                         if (cfg->used_int_regs & (1 << X86_EDI))
2581                                 pos -= 4;
2582                         if (cfg->used_int_regs & (1 << X86_ESI))
2583                                 pos -= 4;
2584                         if (pos)
2585                                 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
2586
2587                         if (cfg->used_int_regs & (1 << X86_ESI))
2588                                 x86_pop_reg (code, X86_ESI);
2589                         if (cfg->used_int_regs & (1 << X86_EDI))
2590                                 x86_pop_reg (code, X86_EDI);
2591                         if (cfg->used_int_regs & (1 << X86_EBX))
2592                                 x86_pop_reg (code, X86_EBX);
2593
2594                         /* restore ESP/EBP */
2595                         x86_leave (code);
2596                         offset = code - cfg->native_code;
2597                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2598                         x86_jump32 (code, 0);
2599                         break;
2600                 }
2601                 case OP_CHECK_THIS:
2602                         /* ensure ins->sreg1 is not NULL */
2603                         x86_alu_membase_imm (code, X86_CMP, ins->sreg1, 0, 0);
2604                         break;
2605                 case OP_ARGLIST: {
2606                         int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
2607                         x86_push_reg (code, hreg);
2608                         x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
2609                         x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
2610                         x86_pop_reg (code, hreg);
2611                         break;
2612                 }
2613                 case OP_FCALL:
2614                 case OP_LCALL:
2615                 case OP_VCALL:
2616                 case OP_VOIDCALL:
2617                 case CEE_CALL:
2618                         call = (MonoCallInst*)ins;
2619                         if (ins->flags & MONO_INST_HAS_METHOD)
2620                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
2621                         else {
2622                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
2623                         }
2624                         x86_call_code (code, 0);
2625                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2626                                 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2627                         break;
2628                 case OP_FCALL_REG:
2629                 case OP_LCALL_REG:
2630                 case OP_VCALL_REG:
2631                 case OP_VOIDCALL_REG:
2632                 case OP_CALL_REG:
2633                         call = (MonoCallInst*)ins;
2634                         x86_call_reg (code, ins->sreg1);
2635                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2636                                 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2637                         break;
2638                 case OP_FCALL_MEMBASE:
2639                 case OP_LCALL_MEMBASE:
2640                 case OP_VCALL_MEMBASE:
2641                 case OP_VOIDCALL_MEMBASE:
2642                 case OP_CALL_MEMBASE:
2643                         call = (MonoCallInst*)ins;
2644                         x86_call_membase (code, ins->sreg1, ins->inst_offset);
2645                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2646                                 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2647                         break;
2648                 case OP_OUTARG:
2649                 case OP_X86_PUSH:
2650                         x86_push_reg (code, ins->sreg1);
2651                         break;
2652                 case OP_X86_PUSH_IMM:
2653                         x86_push_imm (code, ins->inst_imm);
2654                         break;
2655                 case OP_X86_PUSH_MEMBASE:
2656                         x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
2657                         break;
2658                 case OP_X86_PUSH_OBJ:
2659                         x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
2660                         x86_push_reg (code, X86_EDI);
2661                         x86_push_reg (code, X86_ESI);
2662                         x86_push_reg (code, X86_ECX);
2663                         if (ins->inst_offset)
2664                                 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
2665                         else
2666                                 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
2667                         x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2668                         x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
2669                         x86_cld (code);
2670                         x86_prefix (code, X86_REP_PREFIX);
2671                         x86_movsd (code);
2672                         x86_pop_reg (code, X86_ECX);
2673                         x86_pop_reg (code, X86_ESI);
2674                         x86_pop_reg (code, X86_EDI);
2675                         break;
2676                 case OP_X86_LEA:
2677                         x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->unused);
2678                         break;
2679                 case OP_X86_LEA_MEMBASE:
2680                         x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
2681                         break;
2682                 case OP_X86_XCHG:
2683                         x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
2684                         break;
2685                 case OP_LOCALLOC:
2686                         /* keep alignment */
2687                         x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
2688                         x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
2689                         code = mono_emit_stack_alloc (code, ins);
2690                         x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2691                         break;
2692                 case CEE_RET:
2693                         x86_ret (code);
2694                         break;
2695                 case CEE_THROW: {
2696                         x86_push_reg (code, ins->sreg1);
2697                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2698                                              (gpointer)"mono_arch_throw_exception");
2699                         x86_call_code (code, 0);
2700                         break;
2701                 }
2702                 case OP_CALL_HANDLER:
2703                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2704                         x86_call_imm (code, 0);
2705                         break;
2706                 case OP_LABEL:
2707                         ins->inst_c0 = code - cfg->native_code;
2708                         break;
2709                 case CEE_BR:
2710                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
2711                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
2712                         //break;
2713                         if (ins->flags & MONO_INST_BRLABEL) {
2714                                 if (ins->inst_i0->inst_c0) {
2715                                         x86_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
2716                                 } else {
2717                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
2718                                         x86_jump32 (code, 0);
2719                                 }
2720                         } else {
2721                                 if (ins->inst_target_bb->native_offset) {
2722                                         x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
2723                                 } else {
2724                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2725                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
2726                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
2727                                                 x86_jump8 (code, 0);
2728                                         else
2729                                                 x86_jump32 (code, 0);
2730                                 }
2731                         }
2732                         break;
2733                 case OP_BR_REG:
2734                         x86_jump_reg (code, ins->sreg1);
2735                         break;
2736                 case OP_CEQ:
2737                         x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
2738                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2739                         break;
2740                 case OP_CLT:
2741                         x86_set_reg (code, X86_CC_LT, ins->dreg, TRUE);
2742                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2743                         break;
2744                 case OP_CLT_UN:
2745                         x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
2746                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2747                         break;
2748                 case OP_CGT:
2749                         x86_set_reg (code, X86_CC_GT, ins->dreg, TRUE);
2750                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2751                         break;
2752                 case OP_CGT_UN:
2753                         x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
2754                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2755                         break;
2756                 case OP_COND_EXC_EQ:
2757                 case OP_COND_EXC_NE_UN:
2758                 case OP_COND_EXC_LT:
2759                 case OP_COND_EXC_LT_UN:
2760                 case OP_COND_EXC_GT:
2761                 case OP_COND_EXC_GT_UN:
2762                 case OP_COND_EXC_GE:
2763                 case OP_COND_EXC_GE_UN:
2764                 case OP_COND_EXC_LE:
2765                 case OP_COND_EXC_LE_UN:
2766                 case OP_COND_EXC_OV:
2767                 case OP_COND_EXC_NO:
2768                 case OP_COND_EXC_C:
2769                 case OP_COND_EXC_NC:
2770                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
2771                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
2772                         break;
2773                 case CEE_BEQ:
2774                 case CEE_BNE_UN:
2775                 case CEE_BLT:
2776                 case CEE_BLT_UN:
2777                 case CEE_BGT:
2778                 case CEE_BGT_UN:
2779                 case CEE_BGE:
2780                 case CEE_BGE_UN:
2781                 case CEE_BLE:
2782                 case CEE_BLE_UN:
2783                         EMIT_COND_BRANCH (ins, branch_cc_table [ins->opcode - CEE_BEQ], (ins->opcode < CEE_BNE_UN));
2784                         break;
2785
2786                 /* floating point opcodes */
2787                 case OP_R8CONST: {
2788                         double d = *(double *)ins->inst_p0;
2789
2790                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
2791                                 x86_fldz (code);
2792                         } else if (d == 1.0) {
2793                                 x86_fld1 (code);
2794                         } else {
2795                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
2796                                 x86_fld (code, NULL, TRUE);
2797                         }
2798                         break;
2799                 }
2800                 case OP_R4CONST: {
2801                         float f = *(float *)ins->inst_p0;
2802
2803                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
2804                                 x86_fldz (code);
2805                         } else if (f == 1.0) {
2806                                 x86_fld1 (code);
2807                         } else {
2808                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
2809                                 x86_fld (code, NULL, FALSE);
2810                         }
2811                         break;
2812                 }
2813                 case OP_STORER8_MEMBASE_REG:
2814                         x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
2815                         break;
2816                 case OP_LOADR8_SPILL_MEMBASE:
2817                         x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
2818                         x86_fxch (code, 1);
2819                         break;
2820                 case OP_LOADR8_MEMBASE:
2821                         x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
2822                         break;
2823                 case OP_STORER4_MEMBASE_REG:
2824                         x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
2825                         break;
2826                 case OP_LOADR4_MEMBASE:
2827                         x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
2828                         break;
2829                 case CEE_CONV_R4: /* FIXME: change precision */
2830                 case CEE_CONV_R8:
2831                         x86_push_reg (code, ins->sreg1);
2832                         x86_fild_membase (code, X86_ESP, 0, FALSE);
2833                         x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2834                         break;
2835                 case OP_X86_FP_LOAD_I8:
2836                         x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
2837                         break;
2838                 case OP_X86_FP_LOAD_I4:
2839                         x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
2840                         break;
2841                 case OP_FCONV_TO_I1:
2842                         code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
2843                         break;
2844                 case OP_FCONV_TO_U1:
2845                         code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
2846                         break;
2847                 case OP_FCONV_TO_I2:
2848                         code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
2849                         break;
2850                 case OP_FCONV_TO_U2:
2851                         code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
2852                         break;
2853                 case OP_FCONV_TO_I4:
2854                 case OP_FCONV_TO_I:
2855                         code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
2856                         break;
2857                 case OP_FCONV_TO_I8:
2858                         x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2859                         x86_fnstcw_membase(code, X86_ESP, 0);
2860                         x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
2861                         x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
2862                         x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
2863                         x86_fldcw_membase (code, X86_ESP, 2);
2864                         x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2865                         x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2866                         x86_pop_reg (code, ins->dreg);
2867                         x86_pop_reg (code, ins->unused);
2868                         x86_fldcw_membase (code, X86_ESP, 0);
2869                         x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2870                         break;
2871                 case OP_LCONV_TO_R_UN: {
2872                         static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
2873                         guint8 *br;
2874
2875                         /* load 64bit integer to FP stack */
2876                         x86_push_imm (code, 0);
2877                         x86_push_reg (code, ins->sreg2);
2878                         x86_push_reg (code, ins->sreg1);
2879                         x86_fild_membase (code, X86_ESP, 0, TRUE);
2880                         /* store as 80bit FP value */
2881                         x86_fst80_membase (code, X86_ESP, 0);
2882
2883                         /* test if lreg is negative */
2884                         x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
2885                         br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
2886
2887                         /* add correction constant mn */
2888                         x86_fld80_mem (code, mn);
2889                         x86_fld80_membase (code, X86_ESP, 0);
2890                         x86_fp_op_reg (code, X86_FADD, 1, TRUE);
2891                         x86_fst80_membase (code, X86_ESP, 0);
2892
2893                         x86_patch (br, code);
2894
2895                         x86_fld80_membase (code, X86_ESP, 0);
2896                         x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
2897
2898                         break;
2899                 }
2900                 case OP_LCONV_TO_OVF_I: {
2901                         guint8 *br [3], *label [1];
2902
2903                         /*
2904                          * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
2905                          */
2906                         x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2907
2908                         /* If the low word top bit is set, see if we are negative */
2909                         br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
2910                         /* We are not negative (no top bit set, check for our top word to be zero */
2911                         x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
2912                         br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2913                         label [0] = code;
2914
2915                         /* throw exception */
2916                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
2917                         x86_jump32 (code, 0);
2918
2919                         x86_patch (br [0], code);
2920                         /* our top bit is set, check that top word is 0xfffffff */
2921                         x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
2922
2923                         x86_patch (br [1], code);
2924                         /* nope, emit exception */
2925                         br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
2926                         x86_patch (br [2], label [0]);
2927
2928                         if (ins->dreg != ins->sreg1)
2929                                 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2930                         break;
2931                 }
2932                 case OP_FADD:
2933                         x86_fp_op_reg (code, X86_FADD, 1, TRUE);
2934                         break;
2935                 case OP_FSUB:
2936                         x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
2937                         break;
2938                 case OP_FMUL:
2939                         x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
2940                         break;
2941                 case OP_FDIV:
2942                         x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
2943                         break;
2944                 case OP_FNEG:
2945                         x86_fchs (code);
2946                         break;
2947                 case OP_SIN:
2948                         x86_fsin (code);
2949                         break;
2950                 case OP_COS:
2951                         x86_fcos (code);
2952                         break;
2953                 case OP_ABS:
2954                         x86_fabs (code);
2955                         break;
2956                 case OP_TAN: {
2957                         /*
2958                          * it really doesn't make sense to inline all this code,
2959                          * it's here just to show that things may not be as simple
2960                          * as they appear.
2961                          */
2962                         guchar *check_pos, *end_tan, *pop_jump;
2963                         x86_push_reg (code, X86_EAX);
2964                         x86_fptan (code);
2965                         x86_fnstsw (code);
2966                         x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
2967                         check_pos = code;
2968                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
2969                         x86_fstp (code, 0); /* pop the 1.0 */
2970                         end_tan = code;
2971                         x86_jump8 (code, 0);
2972                         x86_fldpi (code);
2973                         x86_fp_op (code, X86_FADD, 0);
2974                         x86_fxch (code, 1);
2975                         x86_fprem1 (code);
2976                         x86_fstsw (code);
2977                         x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
2978                         pop_jump = code;
2979                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
2980                         x86_fstp (code, 1);
2981                         x86_fptan (code);
2982                         x86_patch (pop_jump, code);
2983                         x86_fstp (code, 0); /* pop the 1.0 */
2984                         x86_patch (check_pos, code);
2985                         x86_patch (end_tan, code);
2986                         x86_pop_reg (code, X86_EAX);
2987                         break;
2988                 }
2989                 case OP_ATAN:
2990                         x86_fld1 (code);
2991                         x86_fpatan (code);
2992                         break;
2993                 case OP_SQRT:
2994                         x86_fsqrt (code);
2995                         break;
2996                 case OP_X86_FPOP:
2997                         x86_fstp (code, 0);
2998                         break;
2999                 case OP_FREM: {
3000                         guint8 *l1, *l2;
3001
3002                         x86_push_reg (code, X86_EAX);
3003                         /* we need to exchange ST(0) with ST(1) */
3004                         x86_fxch (code, 1);
3005
3006                         /* this requires a loop, because fprem somtimes
3007                          * returns a partial remainder */
3008                         l1 = code;
3009                         /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3010                         /* x86_fprem1 (code); */
3011                         x86_fprem (code);
3012                         x86_fnstsw (code);
3013                         x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3014                         l2 = code + 2;
3015                         x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3016
3017                         /* pop result */
3018                         x86_fstp (code, 1);
3019
3020                         x86_pop_reg (code, X86_EAX);
3021                         break;
3022                 }
3023                 case OP_FCOMPARE:
3024                         if (cfg->opt & MONO_OPT_FCMOV) {
3025                                 x86_fcomip (code, 1);
3026                                 x86_fstp (code, 0);
3027                                 break;
3028                         }
3029                         /* this overwrites EAX */
3030                         EMIT_FPCOMPARE(code);
3031                         x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3032                         break;
3033                 case OP_FCEQ:
3034                         if (cfg->opt & MONO_OPT_FCMOV) {
3035                                 /* zeroing the register at the start results in
3036                                  * shorter and faster code (we can also remove the widening op)
3037                                  */
3038                                 guchar *unordered_check;
3039                                 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3040                                 x86_fcomip (code, 1);
3041                                 x86_fstp (code, 0);
3042                                 unordered_check = code;
3043                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3044                                 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3045                                 x86_patch (unordered_check, code);
3046                                 break;
3047                         }
3048                         if (ins->dreg != X86_EAX)
3049                                 x86_push_reg (code, X86_EAX);
3050
3051                         EMIT_FPCOMPARE(code);
3052                         x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3053                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3054                         x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3055                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3056
3057                         if (ins->dreg != X86_EAX)
3058                                 x86_pop_reg (code, X86_EAX);
3059                         break;
3060                 case OP_FCLT:
3061                 case OP_FCLT_UN:
3062                         if (cfg->opt & MONO_OPT_FCMOV) {
3063                                 /* zeroing the register at the start results in
3064                                  * shorter and faster code (we can also remove the widening op)
3065                                  */
3066                                 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3067                                 x86_fcomip (code, 1);
3068                                 x86_fstp (code, 0);
3069                                 if (ins->opcode == OP_FCLT_UN) {
3070                                         guchar *unordered_check = code;
3071                                         guchar *jump_to_end;
3072                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3073                                         x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3074                                         jump_to_end = code;
3075                                         x86_jump8 (code, 0);
3076                                         x86_patch (unordered_check, code);
3077                                         x86_inc_reg (code, ins->dreg);
3078                                         x86_patch (jump_to_end, code);
3079                                 } else {
3080                                         x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3081                                 }
3082                                 break;
3083                         }
3084                         if (ins->dreg != X86_EAX)
3085                                 x86_push_reg (code, X86_EAX);
3086
3087                         EMIT_FPCOMPARE(code);
3088                         x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3089                         if (ins->opcode == OP_FCLT_UN) {
3090                                 guchar *is_not_zero_check, *end_jump;
3091                                 is_not_zero_check = code;
3092                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3093                                 end_jump = code;
3094                                 x86_jump8 (code, 0);
3095                                 x86_patch (is_not_zero_check, code);
3096                                 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3097
3098                                 x86_patch (end_jump, code);
3099                         }
3100                         x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3101                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3102
3103                         if (ins->dreg != X86_EAX)
3104                                 x86_pop_reg (code, X86_EAX);
3105                         break;
3106                 case OP_FCGT:
3107                 case OP_FCGT_UN:
3108                         if (cfg->opt & MONO_OPT_FCMOV) {
3109                                 /* zeroing the register at the start results in
3110                                  * shorter and faster code (we can also remove the widening op)
3111                                  */
3112                                 guchar *unordered_check;
3113                                 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3114                                 x86_fcomip (code, 1);
3115                                 x86_fstp (code, 0);
3116                                 if (ins->opcode == OP_FCGT) {
3117                                         unordered_check = code;
3118                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3119                                         x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3120                                         x86_patch (unordered_check, code);
3121                                 } else {
3122                                         x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3123                                 }
3124                                 break;
3125                         }
3126                         if (ins->dreg != X86_EAX)
3127                                 x86_push_reg (code, X86_EAX);
3128
3129                         EMIT_FPCOMPARE(code);
3130                         x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3131                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3132                         if (ins->opcode == OP_FCGT_UN) {
3133                                 guchar *is_not_zero_check, *end_jump;
3134                                 is_not_zero_check = code;
3135                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3136                                 end_jump = code;
3137                                 x86_jump8 (code, 0);
3138                                 x86_patch (is_not_zero_check, code);
3139                                 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3140
3141                                 x86_patch (end_jump, code);
3142                         }
3143                         x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3144                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3145
3146                         if (ins->dreg != X86_EAX)
3147                                 x86_pop_reg (code, X86_EAX);
3148                         break;
3149                 case OP_FBEQ:
3150                         if (cfg->opt & MONO_OPT_FCMOV) {
3151                                 guchar *jump = code;
3152                                 x86_branch8 (code, X86_CC_P, 0, TRUE);
3153                                 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3154                                 x86_patch (jump, code);
3155                                 break;
3156                         }
3157                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3158                         EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3159                         break;
3160                 case OP_FBNE_UN:
3161                         /* Branch if C013 != 100 */
3162                         if (cfg->opt & MONO_OPT_FCMOV) {
3163                                 /* branch if !ZF or (PF|CF) */
3164                                 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3165                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3166                                 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3167                                 break;
3168                         }
3169                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3170                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3171                         break;
3172                 case OP_FBLT:
3173                         if (cfg->opt & MONO_OPT_FCMOV) {
3174                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3175                                 break;
3176                         }
3177                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3178                         break;
3179                 case OP_FBLT_UN:
3180                         if (cfg->opt & MONO_OPT_FCMOV) {
3181                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3182                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3183                                 break;
3184                         }
3185                         if (ins->opcode == OP_FBLT_UN) {
3186                                 guchar *is_not_zero_check, *end_jump;
3187                                 is_not_zero_check = code;
3188                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3189                                 end_jump = code;
3190                                 x86_jump8 (code, 0);
3191                                 x86_patch (is_not_zero_check, code);
3192                                 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3193
3194                                 x86_patch (end_jump, code);
3195                         }
3196                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3197                         break;
3198                 case OP_FBGT:
3199                 case OP_FBGT_UN:
3200                         if (cfg->opt & MONO_OPT_FCMOV) {
3201                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3202                                 break;
3203                         }
3204                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3205                         if (ins->opcode == OP_FBGT_UN) {
3206                                 guchar *is_not_zero_check, *end_jump;
3207                                 is_not_zero_check = code;
3208                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3209                                 end_jump = code;
3210                                 x86_jump8 (code, 0);
3211                                 x86_patch (is_not_zero_check, code);
3212                                 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3213
3214                                 x86_patch (end_jump, code);
3215                         }
3216                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3217                         break;
3218                 case OP_FBGE:
3219                         /* Branch if C013 == 100 or 001 */
3220                         if (cfg->opt & MONO_OPT_FCMOV) {
3221                                 guchar *br1;
3222
3223                                 /* skip branch if C1=1 */
3224                                 br1 = code;
3225                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3226                                 /* branch if (C0 | C3) = 1 */
3227                                 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3228                                 x86_patch (br1, code);
3229                                 break;
3230                         }
3231                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3232                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3233                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3234                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3235                         break;
3236                 case OP_FBGE_UN:
3237                         /* Branch if C013 == 000 */
3238                         if (cfg->opt & MONO_OPT_FCMOV) {
3239                                 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3240                                 break;
3241                         }
3242                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3243                         break;
3244                 case OP_FBLE:
3245                         /* Branch if C013=000 or 100 */
3246                         if (cfg->opt & MONO_OPT_FCMOV) {
3247                                 guchar *br1;
3248
3249                                 /* skip branch if C1=1 */
3250                                 br1 = code;
3251                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3252                                 /* branch if C0=0 */
3253                                 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3254                                 x86_patch (br1, code);
3255                                 break;
3256                         }
3257                         x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
3258                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
3259                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3260                         break;
3261                 case OP_FBLE_UN:
3262                         /* Branch if C013 != 001 */
3263                         if (cfg->opt & MONO_OPT_FCMOV) {
3264                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3265                                 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3266                                 break;
3267                         }
3268                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3269                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3270                         break;
3271                 case CEE_CKFINITE: {
3272                         x86_push_reg (code, X86_EAX);
3273                         x86_fxam (code);
3274                         x86_fnstsw (code);
3275                         x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
3276                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3277                         x86_pop_reg (code, X86_EAX);
3278                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3279                         break;
3280                 }
3281                 default:
3282                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3283                         g_assert_not_reached ();
3284                 }
3285
3286                 if ((code - cfg->native_code - offset) > max_len) {
3287                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
3288                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
3289                         g_assert_not_reached ();
3290                 }
3291
3292                 cpos += max_len;
3293
3294                 last_ins = ins;
3295                 last_offset = offset;
3296
3297                 ins = ins->next;
3298         }
3299
3300         cfg->code_len = code - cfg->native_code;
3301 }
3302
3303 void
3304 mono_arch_register_lowlevel_calls (void)
3305 {
3306         mono_register_jit_icall (mono_arch_get_lmf_addr, "mono_arch_get_lmf_addr", NULL, TRUE);
3307 }
3308
3309 void
3310 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3311 {
3312         MonoJumpInfo *patch_info;
3313
3314         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3315                 unsigned char *ip = patch_info->ip.i + code;
3316                 const unsigned char *target;
3317
3318                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3319
3320                 switch (patch_info->type) {
3321                 case MONO_PATCH_INFO_IP:
3322                         *((gconstpointer *)(ip)) = target;
3323                         continue;
3324                 case MONO_PATCH_INFO_METHOD_REL:
3325                         *((gconstpointer *)(ip)) = target;
3326                         continue;
3327                 case MONO_PATCH_INFO_SWITCH: {
3328                         *((gconstpointer *)(ip + 2)) = target;
3329                         /* we put into the table the absolute address, no need for x86_patch in this case */
3330                         continue;
3331                 }
3332                 case MONO_PATCH_INFO_IID:
3333                         *((guint32 *)(ip + 1)) = (guint32)target;
3334                         continue;
3335                 case MONO_PATCH_INFO_CLASS_INIT: {
3336                         guint8 *code = ip;
3337                         /* Might already been changed to a nop */
3338                         x86_call_imm (code, 0);
3339                         break;
3340                 }
3341                 case MONO_PATCH_INFO_R4:
3342                 case MONO_PATCH_INFO_R8:
3343                         *((gconstpointer *)(ip + 2)) = target;
3344                         continue;
3345                 case MONO_PATCH_INFO_METHODCONST:
3346                 case MONO_PATCH_INFO_CLASS:
3347                 case MONO_PATCH_INFO_IMAGE:
3348                 case MONO_PATCH_INFO_FIELD:
3349                 case MONO_PATCH_INFO_VTABLE:
3350                 case MONO_PATCH_INFO_SFLDA:
3351                 case MONO_PATCH_INFO_EXC_NAME:
3352                 case MONO_PATCH_INFO_LDSTR:
3353                 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
3354                 case MONO_PATCH_INFO_LDTOKEN:
3355                         *((gconstpointer *)(ip + 1)) = target;
3356                         continue;
3357                 default:
3358                         break;
3359                 }
3360                 x86_patch (ip, target);
3361         }
3362 }
3363
3364 int
3365 mono_arch_max_epilog_size (MonoCompile *cfg)
3366 {
3367         int exc_count = 0, max_epilog_size = 16;
3368         MonoJumpInfo *patch_info;
3369
3370         if (cfg->method->save_lmf)
3371                 max_epilog_size += 128;
3372
3373         if (mono_jit_trace_calls != NULL)
3374                 max_epilog_size += 50;
3375
3376         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3377                 max_epilog_size += 50;
3378
3379         /* count the number of exception infos */
3380
3381         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
3382                 if (patch_info->type == MONO_PATCH_INFO_EXC)
3383                         exc_count++;
3384         }
3385
3386         /*
3387          * make sure we have enough space for exceptions
3388          * 16 is the size of two push_imm instructions and a call
3389          */
3390         max_epilog_size += exc_count*16;
3391
3392         return max_epilog_size;
3393 }
3394
3395 guint8 *
3396 mono_arch_emit_prolog (MonoCompile *cfg)
3397 {
3398         MonoMethod *method = cfg->method;
3399         MonoBasicBlock *bb;
3400         MonoMethodSignature *sig;
3401         MonoInst *inst;
3402         int alloc_size, pos, max_offset, i;
3403         guint8 *code;
3404
3405         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 256);
3406         code = cfg->native_code = g_malloc (cfg->code_size);
3407
3408         x86_push_reg (code, X86_EBP);
3409         x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
3410
3411         alloc_size = - cfg->stack_offset;
3412         pos = 0;
3413
3414         if (method->save_lmf) {
3415                 pos += sizeof (MonoLMF);
3416
3417                 /* save the current IP */
3418                 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
3419                 x86_push_imm (code, 0);
3420
3421                 /* save all caller saved regs */
3422                 x86_push_reg (code, X86_EBP);
3423                 x86_push_reg (code, X86_ESI);
3424                 x86_push_reg (code, X86_EDI);
3425                 x86_push_reg (code, X86_EBX);
3426
3427                 /* save method info */
3428                 x86_push_imm (code, method);
3429
3430                 /* get the address of lmf for the current thread */
3431                 /*
3432                  * This is performance critical so we try to use some tricks to make
3433                  * it fast.
3434                  */
3435                 if (lmf_tls_offset != -1) {
3436                         /* Load lmf quicky using the GS register */
3437                         x86_prefix (code, X86_GS_PREFIX);
3438                         x86_mov_reg_mem (code, X86_EAX, 0, 4);
3439                         x86_mov_reg_membase (code, X86_EAX, X86_EAX, lmf_tls_offset, 4);
3440                 }
3441                 else {
3442 #ifdef HAVE_KW_THREAD
3443                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3444                                                                  (gpointer)"mono_arch_get_lmf_addr");
3445 #else
3446                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3447                                                                  (gpointer)"mono_get_lmf_addr");
3448 #endif
3449                         x86_call_code (code, 0);
3450                 }
3451
3452                 /* push lmf */
3453                 x86_push_reg (code, X86_EAX);
3454                 /* push *lfm (previous_lmf) */
3455                 x86_push_membase (code, X86_EAX, 0);
3456                 /* *(lmf) = ESP */
3457                 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
3458         } else {
3459
3460                 if (cfg->used_int_regs & (1 << X86_EBX)) {
3461                         x86_push_reg (code, X86_EBX);
3462                         pos += 4;
3463                 }
3464
3465                 if (cfg->used_int_regs & (1 << X86_EDI)) {
3466                         x86_push_reg (code, X86_EDI);
3467                         pos += 4;
3468                 }
3469
3470                 if (cfg->used_int_regs & (1 << X86_ESI)) {
3471                         x86_push_reg (code, X86_ESI);
3472                         pos += 4;
3473                 }
3474         }
3475
3476         alloc_size -= pos;
3477
3478         if (alloc_size) {
3479                 /* See mono_emit_stack_alloc */
3480 #ifdef PLATFORM_WIN32
3481                 guint32 remaining_size = alloc_size;
3482                 while (remaining_size >= 0x1000) {
3483                         x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
3484                         x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
3485                         remaining_size -= 0x1000;
3486                 }
3487                 if (remaining_size)
3488                         x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
3489 #else
3490                 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
3491 #endif
3492         }
3493
3494         /* compute max_offset in order to use short forward jumps */
3495         max_offset = 0;
3496         if (cfg->opt & MONO_OPT_BRANCH) {
3497                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
3498                         MonoInst *ins = bb->code;
3499                         bb->max_offset = max_offset;
3500
3501                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
3502                                 max_offset += 6;
3503                         /* max alignment for loops */
3504                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
3505                                 max_offset += LOOP_ALIGNMENT;
3506
3507                         while (ins) {
3508                                 max_offset += ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
3509                                 ins = ins->next;
3510                         }
3511                 }
3512         }
3513
3514         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3515                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
3516
3517         /* load arguments allocated to register from the stack */
3518         sig = method->signature;
3519         pos = 0;
3520
3521         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3522                 inst = cfg->varinfo [pos];
3523                 if (inst->opcode == OP_REGVAR) {
3524                         x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
3525                         if (cfg->verbose_level > 2)
3526                                 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
3527                 }
3528                 pos++;
3529         }
3530
3531         cfg->code_len = code - cfg->native_code;
3532
3533         return code;
3534 }
3535
3536 void
3537 mono_arch_emit_epilog (MonoCompile *cfg)
3538 {
3539         MonoJumpInfo *patch_info;
3540         MonoMethod *method = cfg->method;
3541         MonoMethodSignature *sig = method->signature;
3542         int pos;
3543         guint32 stack_to_pop;
3544         guint8 *code;
3545
3546         code = cfg->native_code + cfg->code_len;
3547
3548         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3549                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
3550
3551         /* the code restoring the registers must be kept in sync with CEE_JMP */
3552         pos = 0;
3553
3554         if (method->save_lmf) {
3555                 gint32 prev_lmf_reg;
3556
3557                 /* Find a spare register */
3558                 switch (sig->ret->type) {
3559                 case MONO_TYPE_I8:
3560                 case MONO_TYPE_U8:
3561                         prev_lmf_reg = X86_EDI;
3562                         cfg->used_int_regs |= (1 << X86_EDI);
3563                         break;
3564                 default:
3565                         prev_lmf_reg = X86_EDX;
3566                         break;
3567                 }
3568
3569                 /* reg = previous_lmf */
3570                 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, -32, 4);
3571
3572                 /* ecx = lmf */
3573                 x86_mov_reg_membase (code, X86_ECX, X86_EBP, -28, 4);
3574
3575                 /* *(lmf) = previous_lmf */
3576                 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
3577
3578                 /* restore caller saved regs */
3579                 if (cfg->used_int_regs & (1 << X86_EBX)) {
3580                         x86_mov_reg_membase (code, X86_EBX, X86_EBP, -20, 4);
3581                 }
3582
3583                 if (cfg->used_int_regs & (1 << X86_EDI)) {
3584                         x86_mov_reg_membase (code, X86_EDI, X86_EBP, -16, 4);
3585                 }
3586                 if (cfg->used_int_regs & (1 << X86_ESI)) {
3587                         x86_mov_reg_membase (code, X86_ESI, X86_EBP, -12, 4);
3588                 }
3589
3590                 /* EBP is restored by LEAVE */
3591         } else {
3592                 if (cfg->used_int_regs & (1 << X86_EBX)) {
3593                         pos -= 4;
3594                 }
3595                 if (cfg->used_int_regs & (1 << X86_EDI)) {
3596                         pos -= 4;
3597                 }
3598                 if (cfg->used_int_regs & (1 << X86_ESI)) {
3599                         pos -= 4;
3600                 }
3601
3602                 if (pos)
3603                         x86_lea_membase (code, X86_ESP, X86_EBP, pos);
3604
3605                 if (cfg->used_int_regs & (1 << X86_ESI)) {
3606                         x86_pop_reg (code, X86_ESI);
3607                 }
3608                 if (cfg->used_int_regs & (1 << X86_EDI)) {
3609                         x86_pop_reg (code, X86_EDI);
3610                 }
3611                 if (cfg->used_int_regs & (1 << X86_EBX)) {
3612                         x86_pop_reg (code, X86_EBX);
3613                 }
3614         }
3615
3616         x86_leave (code);
3617
3618         if (CALLCONV_IS_STDCALL (sig->call_convention)) {
3619                 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
3620
3621                 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
3622         } else if (MONO_TYPE_ISSTRUCT (cfg->method->signature->ret))
3623                 stack_to_pop = 4;
3624         else
3625                 stack_to_pop = 0;
3626
3627         if (stack_to_pop)
3628                 x86_ret_imm (code, stack_to_pop);
3629         else
3630                 x86_ret (code);
3631
3632         /* add code to raise exceptions */
3633         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
3634                 switch (patch_info->type) {
3635                 case MONO_PATCH_INFO_EXC:
3636                         x86_patch (patch_info->ip.i + cfg->native_code, code);
3637                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC_NAME, patch_info->data.target);
3638                         x86_push_imm (code, patch_info->data.target);
3639                         mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_METHOD_REL, (gpointer)patch_info->ip.i);
3640                         x86_push_imm (code, patch_info->ip.i + cfg->native_code);
3641                         patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
3642                         patch_info->data.name = "mono_arch_throw_exception_by_name";
3643                         patch_info->ip.i = code - cfg->native_code;
3644                         x86_jump_code (code, 0);
3645                         break;
3646                 default:
3647                         /* do nothing */
3648                         break;
3649                 }
3650         }
3651
3652         cfg->code_len = code - cfg->native_code;
3653
3654         g_assert (cfg->code_len < cfg->code_size);
3655
3656 }
3657
3658 void
3659 mono_arch_flush_icache (guint8 *code, gint size)
3660 {
3661         /* not needed */
3662 }
3663
3664 void
3665 mono_arch_flush_register_windows (void)
3666 {
3667 }
3668
3669 /*
3670  * Support for fast access to the thread-local lmf structure using the GS
3671  * segment register on NPTL + kernel 2.6.x.
3672  */
3673
3674 static gboolean tls_offset_inited = FALSE;
3675
3676 #ifdef HAVE_KW_THREAD
3677 static __thread gpointer mono_lmf_addr;
3678 #endif
3679
3680 static gpointer
3681 mono_arch_get_lmf_addr (void)
3682 {
3683 #ifdef HAVE_KW_THREAD
3684         return mono_lmf_addr;
3685 #else
3686         g_assert_not_reached ();
3687         return NULL;
3688 #endif
3689 }
3690
3691 void
3692 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
3693 {
3694 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3695         pthread_t self = pthread_self();
3696         pthread_attr_t attr;
3697         void *staddr = NULL;
3698         size_t stsize = 0;
3699         struct sigaltstack sa;
3700 #endif
3701
3702         if (!tls_offset_inited) {
3703                 guint8 *code;
3704
3705                 tls_offset_inited = TRUE;
3706
3707                 if (getenv ("MONO_NPTL")) {
3708                         /*
3709                          * Determine the offset of mono_lfm_addr inside the TLS structures
3710                          * by disassembling the function above.
3711                          */
3712                         code = (guint8*)&mono_arch_get_lmf_addr;
3713
3714                         /* This is generated by gcc 3.3.2 */
3715                         if ((code [0] == 0x55) && (code [1] == 0x89) && (code [2] == 0xe5) &&
3716                                 (code [3] == 0x65) && (code [4] == 0xa1) && (code [5] == 0x00) &&
3717                                 (code [6] == 0x00) && (code [7] == 0x00) && (code [8] == 0x00) &&
3718                                 (code [9] == 0x8b) && (code [10] == 0x80)) {
3719                                 lmf_tls_offset = *(int*)&(code [11]);
3720                         }
3721                         else
3722                                 /* This is generated by gcc-3.4 */
3723                                 if ((code [0] == 0x55) && (code [1] == 0x89) && (code [2] == 0xe5) &&
3724                                         (code [3] == 0x65) && (code [4] == 0xa1)) {
3725                                         lmf_tls_offset = *(int*)&(code [5]);
3726                                 }
3727                 }
3728         }
3729
3730 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3731
3732         /* Determine stack boundaries */
3733         if (!mono_running_on_valgrind ()) {
3734 #ifdef HAVE_PTHREAD_GETATTR_NP
3735                 pthread_getattr_np( self, &attr );
3736 #else
3737 #ifdef HAVE_PTHREAD_ATTR_GET_NP
3738                 pthread_attr_get_np( self, &attr );
3739 #else
3740 #error "Not implemented"
3741 #endif
3742 #endif
3743                 pthread_attr_getstack( &attr, &staddr, &stsize );
3744         }
3745
3746         /*
3747          * staddr seems to be wrong for the main thread, so we keep the value in
3748          * tls->end_of_stack
3749          */
3750         tls->stack_size = stsize;
3751
3752         /* Setup an alternate signal stack */
3753         tls->signal_stack = g_malloc (SIGNAL_STACK_SIZE);
3754         tls->signal_stack_size = SIGNAL_STACK_SIZE;
3755
3756         sa.ss_sp = tls->signal_stack;
3757         sa.ss_size = SIGNAL_STACK_SIZE;
3758         sa.ss_flags = SS_ONSTACK;
3759         sigaltstack (&sa, NULL);
3760 #endif
3761
3762 #ifdef HAVE_KW_THREAD
3763         mono_lmf_addr = &tls->lmf;
3764 #endif
3765 }
3766
3767 void
3768 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
3769 {
3770 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3771         struct sigaltstack sa;
3772
3773         sa.ss_sp = tls->signal_stack;
3774         sa.ss_size = SIGNAL_STACK_SIZE;
3775         sa.ss_flags = SS_DISABLE;
3776         sigaltstack  (&sa, NULL);
3777
3778         if (tls->signal_stack)
3779                 g_free (tls->signal_stack);
3780 #endif
3781 }
3782
3783 void
3784 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
3785 {
3786
3787         /* add the this argument */
3788         if (this_reg != -1) {
3789                 MonoInst *this;
3790                 MONO_INST_NEW (cfg, this, OP_OUTARG);
3791                 this->type = this_type;
3792                 this->sreg1 = this_reg;
3793                 mono_bblock_add_inst (cfg->cbb, this);
3794         }
3795
3796         if (vt_reg != -1) {
3797                 MonoInst *vtarg;
3798                 MONO_INST_NEW (cfg, vtarg, OP_OUTARG);
3799                 vtarg->type = STACK_MP;
3800                 vtarg->sreg1 = vt_reg;
3801                 mono_bblock_add_inst (cfg->cbb, vtarg);
3802         }
3803 }
3804
3805
3806 gint
3807 mono_arch_get_opcode_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
3808 {
3809         if (cmethod->klass == mono_defaults.math_class) {
3810                 if (strcmp (cmethod->name, "Sin") == 0)
3811                         return OP_SIN;
3812                 else if (strcmp (cmethod->name, "Cos") == 0)
3813                         return OP_COS;
3814                 else if (strcmp (cmethod->name, "Tan") == 0)
3815                         return OP_TAN;
3816                 else if (strcmp (cmethod->name, "Atan") == 0)
3817                         return OP_ATAN;
3818                 else if (strcmp (cmethod->name, "Sqrt") == 0)
3819                         return OP_SQRT;
3820                 else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8)
3821                         return OP_ABS;
3822 #if 0
3823                 /* OP_FREM is not IEEE compatible */
3824                 else if (strcmp (cmethod->name, "IEEERemainder") == 0)
3825                         return OP_FREM;
3826 #endif
3827                 else
3828                         return -1;
3829         } else {
3830                 return -1;
3831         }
3832         return -1;
3833 }
3834
3835
3836 gboolean
3837 mono_arch_print_tree (MonoInst *tree, int arity)
3838 {
3839         return 0;
3840 }