2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * (C) 2003 Ximian, Inc.
18 #include <mono/metadata/appdomain.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/metadata/threads.h>
21 #include <mono/metadata/profiler-private.h>
22 #include <mono/metadata/mono-debug.h>
23 #include <mono/utils/mono-math.h>
24 #include <mono/utils/mono-counters.h>
31 /* On windows, these hold the key returned by TlsAlloc () */
32 static gint lmf_tls_offset = -1;
33 static gint lmf_addr_tls_offset = -1;
34 static gint appdomain_tls_offset = -1;
35 static gint thread_tls_offset = -1;
38 static gboolean optimize_for_xen = TRUE;
40 #define optimize_for_xen 0
44 static gboolean is_win32 = TRUE;
46 static gboolean is_win32 = FALSE;
49 /* This mutex protects architecture specific caches */
50 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
51 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
52 static CRITICAL_SECTION mini_arch_mutex;
54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
59 /* Under windows, the default pinvoke calling convention is stdcall */
60 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT))
62 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL)
66 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
69 mono_arch_regname (int reg)
72 case X86_EAX: return "%eax";
73 case X86_EBX: return "%ebx";
74 case X86_ECX: return "%ecx";
75 case X86_EDX: return "%edx";
76 case X86_ESP: return "%esp";
77 case X86_EBP: return "%ebp";
78 case X86_EDI: return "%edi";
79 case X86_ESI: return "%esi";
85 mono_arch_fregname (int reg)
110 mono_arch_xregname (int reg)
151 /* Only if storage == ArgValuetypeInReg */
152 ArgStorage pair_storage [2];
161 gboolean need_stack_align;
162 guint32 stack_align_amount;
170 #define FLOAT_PARAM_REGS 0
172 static X86_Reg_No param_regs [] = { 0 };
174 #if defined(PLATFORM_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
175 #define SMALL_STRUCTS_IN_REGS
176 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
180 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
182 ainfo->offset = *stack_size;
184 if (*gr >= PARAM_REGS) {
185 ainfo->storage = ArgOnStack;
186 (*stack_size) += sizeof (gpointer);
189 ainfo->storage = ArgInIReg;
190 ainfo->reg = param_regs [*gr];
196 add_general_pair (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
198 ainfo->offset = *stack_size;
200 g_assert (PARAM_REGS == 0);
202 ainfo->storage = ArgOnStack;
203 (*stack_size) += sizeof (gpointer) * 2;
207 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
209 ainfo->offset = *stack_size;
211 if (*gr >= FLOAT_PARAM_REGS) {
212 ainfo->storage = ArgOnStack;
213 (*stack_size) += is_double ? 8 : 4;
216 /* A double register */
218 ainfo->storage = ArgInDoubleSSEReg;
220 ainfo->storage = ArgInFloatSSEReg;
228 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
230 guint32 *gr, guint32 *fr, guint32 *stack_size)
235 klass = mono_class_from_mono_type (type);
236 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
238 #ifdef SMALL_STRUCTS_IN_REGS
239 if (sig->pinvoke && is_return) {
240 MonoMarshalType *info;
243 * the exact rules are not very well documented, the code below seems to work with the
244 * code generated by gcc 3.3.3 -mno-cygwin.
246 info = mono_marshal_load_type_info (klass);
249 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
251 /* Special case structs with only a float member */
252 if ((info->native_size == 8) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R8)) {
253 ainfo->storage = ArgValuetypeInReg;
254 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
257 if ((info->native_size == 4) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R4)) {
258 ainfo->storage = ArgValuetypeInReg;
259 ainfo->pair_storage [0] = ArgOnFloatFpStack;
262 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
263 ainfo->storage = ArgValuetypeInReg;
264 ainfo->pair_storage [0] = ArgInIReg;
265 ainfo->pair_regs [0] = return_regs [0];
266 if (info->native_size > 4) {
267 ainfo->pair_storage [1] = ArgInIReg;
268 ainfo->pair_regs [1] = return_regs [1];
275 ainfo->offset = *stack_size;
276 ainfo->storage = ArgOnStack;
277 *stack_size += ALIGN_TO (size, sizeof (gpointer));
283 * Obtain information about a call according to the calling convention.
284 * For x86 ELF, see the "System V Application Binary Interface Intel386
285 * Architecture Processor Supplment, Fourth Edition" document for more
287 * For x86 win32, see ???.
290 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
294 int n = sig->hasthis + sig->param_count;
295 guint32 stack_size = 0;
299 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
301 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
308 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
309 switch (ret_type->type) {
310 case MONO_TYPE_BOOLEAN:
321 case MONO_TYPE_FNPTR:
322 case MONO_TYPE_CLASS:
323 case MONO_TYPE_OBJECT:
324 case MONO_TYPE_SZARRAY:
325 case MONO_TYPE_ARRAY:
326 case MONO_TYPE_STRING:
327 cinfo->ret.storage = ArgInIReg;
328 cinfo->ret.reg = X86_EAX;
332 cinfo->ret.storage = ArgInIReg;
333 cinfo->ret.reg = X86_EAX;
336 cinfo->ret.storage = ArgOnFloatFpStack;
339 cinfo->ret.storage = ArgOnDoubleFpStack;
341 case MONO_TYPE_GENERICINST:
342 if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
343 cinfo->ret.storage = ArgInIReg;
344 cinfo->ret.reg = X86_EAX;
348 case MONO_TYPE_VALUETYPE: {
349 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
351 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
352 if (cinfo->ret.storage == ArgOnStack)
353 /* The caller passes the address where the value is stored */
354 add_general (&gr, &stack_size, &cinfo->ret);
357 case MONO_TYPE_TYPEDBYREF:
358 /* Same as a valuetype with size 24 */
359 add_general (&gr, &stack_size, &cinfo->ret);
363 cinfo->ret.storage = ArgNone;
366 g_error ("Can't handle as return value 0x%x", sig->ret->type);
372 add_general (&gr, &stack_size, cinfo->args + 0);
374 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
376 fr = FLOAT_PARAM_REGS;
378 /* Emit the signature cookie just before the implicit arguments */
379 add_general (&gr, &stack_size, &cinfo->sig_cookie);
382 for (i = 0; i < sig->param_count; ++i) {
383 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
386 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
387 /* We allways pass the sig cookie on the stack for simplicity */
389 * Prevent implicit arguments + the sig cookie from being passed
393 fr = FLOAT_PARAM_REGS;
395 /* Emit the signature cookie just before the implicit arguments */
396 add_general (&gr, &stack_size, &cinfo->sig_cookie);
399 if (sig->params [i]->byref) {
400 add_general (&gr, &stack_size, ainfo);
403 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
404 switch (ptype->type) {
405 case MONO_TYPE_BOOLEAN:
408 add_general (&gr, &stack_size, ainfo);
413 add_general (&gr, &stack_size, ainfo);
417 add_general (&gr, &stack_size, ainfo);
422 case MONO_TYPE_FNPTR:
423 case MONO_TYPE_CLASS:
424 case MONO_TYPE_OBJECT:
425 case MONO_TYPE_STRING:
426 case MONO_TYPE_SZARRAY:
427 case MONO_TYPE_ARRAY:
428 add_general (&gr, &stack_size, ainfo);
430 case MONO_TYPE_GENERICINST:
431 if (!mono_type_generic_inst_is_valuetype (sig->params [i])) {
432 add_general (&gr, &stack_size, ainfo);
436 case MONO_TYPE_VALUETYPE:
437 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
439 case MONO_TYPE_TYPEDBYREF:
440 stack_size += sizeof (MonoTypedRef);
441 ainfo->storage = ArgOnStack;
445 add_general_pair (&gr, &stack_size, ainfo);
448 add_float (&fr, &stack_size, ainfo, FALSE);
451 add_float (&fr, &stack_size, ainfo, TRUE);
454 g_error ("unexpected type 0x%x", ptype->type);
455 g_assert_not_reached ();
459 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
461 fr = FLOAT_PARAM_REGS;
463 /* Emit the signature cookie just before the implicit arguments */
464 add_general (&gr, &stack_size, &cinfo->sig_cookie);
467 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
468 cinfo->need_stack_align = TRUE;
469 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
470 stack_size += cinfo->stack_align_amount;
473 cinfo->stack_usage = stack_size;
474 cinfo->reg_usage = gr;
475 cinfo->freg_usage = fr;
480 * mono_arch_get_argument_info:
481 * @csig: a method signature
482 * @param_count: the number of parameters to consider
483 * @arg_info: an array to store the result infos
485 * Gathers information on parameters such as size, alignment and
486 * padding. arg_info should be large enought to hold param_count + 1 entries.
488 * Returns the size of the argument area on the stack.
491 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
493 int k, args_size = 0;
499 cinfo = get_call_info (NULL, NULL, csig, FALSE);
501 if (MONO_TYPE_ISSTRUCT (csig->ret) && (cinfo->ret.storage == ArgOnStack)) {
502 args_size += sizeof (gpointer);
506 arg_info [0].offset = offset;
509 args_size += sizeof (gpointer);
513 arg_info [0].size = args_size;
515 for (k = 0; k < param_count; k++) {
516 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
518 /* ignore alignment for now */
521 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
522 arg_info [k].pad = pad;
524 arg_info [k + 1].pad = 0;
525 arg_info [k + 1].size = size;
527 arg_info [k + 1].offset = offset;
531 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
532 align = MONO_ARCH_FRAME_ALIGNMENT;
535 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
536 arg_info [k].pad = pad;
543 static const guchar cpuid_impl [] = {
544 0x55, /* push %ebp */
545 0x89, 0xe5, /* mov %esp,%ebp */
546 0x53, /* push %ebx */
547 0x8b, 0x45, 0x08, /* mov 0x8(%ebp),%eax */
548 0x0f, 0xa2, /* cpuid */
549 0x50, /* push %eax */
550 0x8b, 0x45, 0x10, /* mov 0x10(%ebp),%eax */
551 0x89, 0x18, /* mov %ebx,(%eax) */
552 0x8b, 0x45, 0x14, /* mov 0x14(%ebp),%eax */
553 0x89, 0x08, /* mov %ecx,(%eax) */
554 0x8b, 0x45, 0x18, /* mov 0x18(%ebp),%eax */
555 0x89, 0x10, /* mov %edx,(%eax) */
557 0x8b, 0x55, 0x0c, /* mov 0xc(%ebp),%edx */
558 0x89, 0x02, /* mov %eax,(%edx) */
564 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
567 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
571 __asm__ __volatile__ (
574 "movl %%eax, %%edx\n"
575 "xorl $0x200000, %%eax\n"
580 "xorl %%edx, %%eax\n"
581 "andl $0x200000, %%eax\n"
603 /* Have to use the code manager to get around WinXP DEP */
604 static CpuidFunc func = NULL;
607 ptr = mono_global_codeman_reserve (sizeof (cpuid_impl));
608 memcpy (ptr, cpuid_impl, sizeof (cpuid_impl));
609 func = (CpuidFunc)ptr;
611 func (id, p_eax, p_ebx, p_ecx, p_edx);
614 * We use this approach because of issues with gcc and pic code, see:
615 * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
616 __asm__ __volatile__ ("cpuid"
617 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
626 * Initialize the cpu to execute managed code.
629 mono_arch_cpu_init (void)
631 /* spec compliance requires running with double precision */
635 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
636 fpcw &= ~X86_FPCW_PRECC_MASK;
637 fpcw |= X86_FPCW_PREC_DOUBLE;
638 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
639 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
641 _control87 (_PC_53, MCW_PC);
646 * Initialize architecture specific code.
649 mono_arch_init (void)
651 InitializeCriticalSection (&mini_arch_mutex);
655 * Cleanup architecture specific code.
658 mono_arch_cleanup (void)
660 DeleteCriticalSection (&mini_arch_mutex);
664 * This function returns the optimizations supported on this cpu.
667 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
669 int eax, ebx, ecx, edx;
673 /* Feature Flags function, flags returned in EDX. */
674 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
675 if (edx & (1 << 15)) {
676 opts |= MONO_OPT_CMOV;
678 opts |= MONO_OPT_FCMOV;
680 *exclude_mask |= MONO_OPT_FCMOV;
682 *exclude_mask |= MONO_OPT_CMOV;
684 opts |= MONO_OPT_SSE2;
686 *exclude_mask |= MONO_OPT_SSE2;
688 #ifdef MONO_ARCH_SIMD_INTRINSICS
689 /*SIMD intrinsics require at least SSE2.*/
690 if (!(opts & MONO_OPT_SSE2))
691 *exclude_mask |= MONO_OPT_SIMD;
698 * This function test for all SSE functions supported.
700 * Returns a bitmask corresponding to all supported versions.
702 * TODO detect other versions like SSE4a.
705 mono_arch_cpu_enumerate_simd_versions (void)
707 int eax, ebx, ecx, edx;
708 guint32 sse_opts = 0;
710 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
712 sse_opts |= 1 << SIMD_VERSION_SSE1;
714 sse_opts |= 1 << SIMD_VERSION_SSE2;
716 sse_opts |= 1 << SIMD_VERSION_SSE3;
718 sse_opts |= 1 << SIMD_VERSION_SSSE3;
720 sse_opts |= 1 << SIMD_VERSION_SSE41;
722 sse_opts |= 1 << SIMD_VERSION_SSE42;
728 * Determine whenever the trap whose info is in SIGINFO is caused by
732 mono_arch_is_int_overflow (void *sigctx, void *info)
737 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
739 ip = (guint8*)ctx.eip;
741 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
745 switch (x86_modrm_rm (ip [1])) {
765 g_assert_not_reached ();
777 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
782 for (i = 0; i < cfg->num_varinfo; i++) {
783 MonoInst *ins = cfg->varinfo [i];
784 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
787 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
790 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
791 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
794 /* we dont allocate I1 to registers because there is no simply way to sign extend
795 * 8bit quantities in caller saved registers on x86 */
796 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
797 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
798 g_assert (i == vmv->idx);
799 vars = g_list_prepend (vars, vmv);
803 vars = mono_varlist_sort (cfg, vars, 0);
809 mono_arch_get_global_int_regs (MonoCompile *cfg)
813 /* we can use 3 registers for global allocation */
814 regs = g_list_prepend (regs, (gpointer)X86_EBX);
815 regs = g_list_prepend (regs, (gpointer)X86_ESI);
816 regs = g_list_prepend (regs, (gpointer)X86_EDI);
822 * mono_arch_regalloc_cost:
824 * Return the cost, in number of memory references, of the action of
825 * allocating the variable VMV into a register during global register
829 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
831 MonoInst *ins = cfg->varinfo [vmv->idx];
833 if (cfg->method->save_lmf)
834 /* The register is already saved */
835 return (ins->opcode == OP_ARG) ? 1 : 0;
837 /* push+pop+possible load if it is an argument */
838 return (ins->opcode == OP_ARG) ? 3 : 2;
842 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
844 static int inited = FALSE;
845 static int count = 0;
847 if (cfg->arch.need_stack_frame_inited) {
848 g_assert (cfg->arch.need_stack_frame == flag);
852 cfg->arch.need_stack_frame = flag;
853 cfg->arch.need_stack_frame_inited = TRUE;
859 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
864 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
868 needs_stack_frame (MonoCompile *cfg)
870 MonoMethodSignature *sig;
871 MonoMethodHeader *header;
872 gboolean result = FALSE;
874 if (cfg->arch.need_stack_frame_inited)
875 return cfg->arch.need_stack_frame;
877 header = mono_method_get_header (cfg->method);
878 sig = mono_method_signature (cfg->method);
880 if (cfg->disable_omit_fp)
882 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
884 else if (cfg->method->save_lmf)
886 else if (cfg->stack_offset)
888 else if (cfg->param_area)
890 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
892 else if (header->num_clauses)
894 else if (sig->param_count + sig->hasthis)
896 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
898 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
899 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
902 set_needs_stack_frame (cfg, result);
904 return cfg->arch.need_stack_frame;
908 * Set var information according to the calling convention. X86 version.
909 * The locals var stuff should most likely be split in another method.
912 mono_arch_allocate_vars (MonoCompile *cfg)
914 MonoMethodSignature *sig;
915 MonoMethodHeader *header;
917 guint32 locals_stack_size, locals_stack_align;
922 header = mono_method_get_header (cfg->method);
923 sig = mono_method_signature (cfg->method);
925 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
927 cfg->frame_reg = X86_EBP;
930 /* Reserve space to save LMF and caller saved registers */
932 if (cfg->method->save_lmf) {
933 offset += sizeof (MonoLMF);
935 if (cfg->used_int_regs & (1 << X86_EBX)) {
939 if (cfg->used_int_regs & (1 << X86_EDI)) {
943 if (cfg->used_int_regs & (1 << X86_ESI)) {
948 switch (cinfo->ret.storage) {
949 case ArgValuetypeInReg:
950 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
952 cfg->ret->opcode = OP_REGOFFSET;
953 cfg->ret->inst_basereg = X86_EBP;
954 cfg->ret->inst_offset = - offset;
960 /* Allocate locals */
961 offsets = mono_allocate_stack_slots (cfg, &locals_stack_size, &locals_stack_align);
962 if (locals_stack_align) {
963 offset += (locals_stack_align - 1);
964 offset &= ~(locals_stack_align - 1);
967 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
968 * have locals larger than 8 bytes we need to make sure that
969 * they have the appropriate offset.
971 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
972 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
973 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
974 if (offsets [i] != -1) {
975 MonoInst *inst = cfg->varinfo [i];
976 inst->opcode = OP_REGOFFSET;
977 inst->inst_basereg = X86_EBP;
978 inst->inst_offset = - (offset + offsets [i]);
979 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
982 offset += locals_stack_size;
986 * Allocate arguments+return value
989 switch (cinfo->ret.storage) {
991 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
993 * In the new IR, the cfg->vret_addr variable represents the
994 * vtype return value.
996 cfg->vret_addr->opcode = OP_REGOFFSET;
997 cfg->vret_addr->inst_basereg = cfg->frame_reg;
998 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
999 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1000 printf ("vret_addr =");
1001 mono_print_ins (cfg->vret_addr);
1004 cfg->ret->opcode = OP_REGOFFSET;
1005 cfg->ret->inst_basereg = X86_EBP;
1006 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1009 case ArgValuetypeInReg:
1012 cfg->ret->opcode = OP_REGVAR;
1013 cfg->ret->inst_c0 = cinfo->ret.reg;
1014 cfg->ret->dreg = cinfo->ret.reg;
1017 case ArgOnFloatFpStack:
1018 case ArgOnDoubleFpStack:
1021 g_assert_not_reached ();
1024 if (sig->call_convention == MONO_CALL_VARARG) {
1025 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1026 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1029 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1030 ArgInfo *ainfo = &cinfo->args [i];
1031 inst = cfg->args [i];
1032 if (inst->opcode != OP_REGVAR) {
1033 inst->opcode = OP_REGOFFSET;
1034 inst->inst_basereg = X86_EBP;
1036 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1039 cfg->stack_offset = offset;
1043 mono_arch_create_vars (MonoCompile *cfg)
1045 MonoMethodSignature *sig;
1048 sig = mono_method_signature (cfg->method);
1050 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1052 if (cinfo->ret.storage == ArgValuetypeInReg)
1053 cfg->ret_var_is_local = TRUE;
1054 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1055 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1060 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1061 * so we try to do it just once when we have multiple fp arguments in a row.
1062 * We don't use this mechanism generally because for int arguments the generated code
1063 * is slightly bigger and new generation cpus optimize away the dependency chains
1064 * created by push instructions on the esp value.
1065 * fp_arg_setup is the first argument in the execution sequence where the esp register
1068 static G_GNUC_UNUSED int
1069 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1074 for (; start_arg < sig->param_count; ++start_arg) {
1075 t = mini_type_get_underlying_type (NULL, sig->params [start_arg]);
1076 if (!t->byref && t->type == MONO_TYPE_R8) {
1077 fp_space += sizeof (double);
1078 *fp_arg_setup = start_arg;
1087 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1089 MonoMethodSignature *tmp_sig;
1091 /* FIXME: Add support for signature tokens to AOT */
1092 cfg->disable_aot = TRUE;
1095 * mono_ArgIterator_Setup assumes the signature cookie is
1096 * passed first and all the arguments which were before it are
1097 * passed on the stack after the signature. So compensate by
1098 * passing a different signature.
1100 tmp_sig = mono_metadata_signature_dup (call->signature);
1101 tmp_sig->param_count -= call->signature->sentinelpos;
1102 tmp_sig->sentinelpos = 0;
1103 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1105 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1110 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1116 LLVMCallInfo *linfo;
1118 n = sig->param_count + sig->hasthis;
1120 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1122 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1125 * LLVM always uses the native ABI while we use our own ABI, the
1126 * only difference is the handling of vtypes:
1127 * - we only pass/receive them in registers in some cases, and only
1128 * in 1 or 2 integer registers.
1130 if (cinfo->ret.storage == ArgValuetypeInReg) {
1132 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1133 cfg->disable_llvm = TRUE;
1137 cfg->exception_message = g_strdup ("vtype ret in call");
1138 cfg->disable_llvm = TRUE;
1140 linfo->ret.storage = LLVMArgVtypeInReg;
1141 for (j = 0; j < 2; ++j)
1142 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1146 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1147 /* Vtype returned using a hidden argument */
1148 linfo->ret.storage = LLVMArgVtypeRetAddr;
1151 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != ArgInIReg) {
1153 cfg->exception_message = g_strdup ("vtype ret in call");
1154 cfg->disable_llvm = TRUE;
1157 for (i = 0; i < n; ++i) {
1158 ainfo = cinfo->args + i;
1160 linfo->args [i].storage = LLVMArgNone;
1162 switch (ainfo->storage) {
1164 linfo->args [i].storage = LLVMArgInIReg;
1166 case ArgInDoubleSSEReg:
1167 case ArgInFloatSSEReg:
1168 linfo->args [i].storage = LLVMArgInFPReg;
1171 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1172 linfo->args [i].storage = LLVMArgVtypeByVal;
1174 linfo->args [i].storage = LLVMArgInIReg;
1175 if (!sig->params [i - sig->hasthis]->byref) {
1176 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1177 linfo->args [i].storage = LLVMArgInFPReg;
1178 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1179 linfo->args [i].storage = LLVMArgInFPReg;
1184 case ArgValuetypeInReg:
1186 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1187 cfg->disable_llvm = TRUE;
1191 cfg->exception_message = g_strdup ("vtype arg");
1192 cfg->disable_llvm = TRUE;
1194 linfo->args [i].storage = LLVMArgVtypeInReg;
1195 for (j = 0; j < 2; ++j)
1196 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1200 cfg->exception_message = g_strdup ("ainfo->storage");
1201 cfg->disable_llvm = TRUE;
1211 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1214 MonoMethodSignature *sig;
1217 int sentinelpos = 0;
1219 sig = call->signature;
1220 n = sig->param_count + sig->hasthis;
1222 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1224 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1225 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1227 if (cinfo->need_stack_align) {
1228 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1229 arg->dreg = X86_ESP;
1230 arg->sreg1 = X86_ESP;
1231 arg->inst_imm = cinfo->stack_align_amount;
1232 MONO_ADD_INS (cfg->cbb, arg);
1235 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1236 if (cinfo->ret.storage == ArgValuetypeInReg) {
1238 * Tell the JIT to use a more efficient calling convention: call using
1239 * OP_CALL, compute the result location after the call, and save the
1242 call->vret_in_reg = TRUE;
1244 NULLIFY_INS (call->vret_var);
1248 /* Handle the case where there are no implicit arguments */
1249 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1250 emit_sig_cookie (cfg, call, cinfo);
1253 /* Arguments are pushed in the reverse order */
1254 for (i = n - 1; i >= 0; i --) {
1255 ArgInfo *ainfo = cinfo->args + i;
1258 if (i >= sig->hasthis)
1259 t = sig->params [i - sig->hasthis];
1261 t = &mono_defaults.int_class->byval_arg;
1262 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1264 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1266 in = call->args [i];
1267 arg->cil_code = in->cil_code;
1268 arg->sreg1 = in->dreg;
1269 arg->type = in->type;
1271 g_assert (in->dreg != -1);
1273 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1277 g_assert (in->klass);
1279 if (t->type == MONO_TYPE_TYPEDBYREF) {
1280 size = sizeof (MonoTypedRef);
1281 align = sizeof (gpointer);
1284 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1288 arg->opcode = OP_OUTARG_VT;
1289 arg->sreg1 = in->dreg;
1290 arg->klass = in->klass;
1291 arg->backend.size = size;
1293 MONO_ADD_INS (cfg->cbb, arg);
1297 switch (ainfo->storage) {
1299 arg->opcode = OP_X86_PUSH;
1301 if (t->type == MONO_TYPE_R4) {
1302 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1303 arg->opcode = OP_STORER4_MEMBASE_REG;
1304 arg->inst_destbasereg = X86_ESP;
1305 arg->inst_offset = 0;
1306 } else if (t->type == MONO_TYPE_R8) {
1307 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1308 arg->opcode = OP_STORER8_MEMBASE_REG;
1309 arg->inst_destbasereg = X86_ESP;
1310 arg->inst_offset = 0;
1311 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1313 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1318 g_assert_not_reached ();
1321 MONO_ADD_INS (cfg->cbb, arg);
1324 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1325 /* Emit the signature cookie just before the implicit arguments */
1326 emit_sig_cookie (cfg, call, cinfo);
1330 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1333 if (cinfo->ret.storage == ArgValuetypeInReg) {
1336 else if (cinfo->ret.storage == ArgInIReg) {
1338 /* The return address is passed in a register */
1339 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1340 vtarg->sreg1 = call->inst.dreg;
1341 vtarg->dreg = mono_alloc_ireg (cfg);
1342 MONO_ADD_INS (cfg->cbb, vtarg);
1344 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1347 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1348 vtarg->type = STACK_MP;
1349 vtarg->sreg1 = call->vret_var->dreg;
1350 MONO_ADD_INS (cfg->cbb, vtarg);
1353 /* if the function returns a struct, the called method already does a ret $0x4 */
1354 cinfo->stack_usage -= 4;
1357 call->stack_usage = cinfo->stack_usage;
1361 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1364 int size = ins->backend.size;
1367 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1368 arg->sreg1 = src->dreg;
1370 MONO_ADD_INS (cfg->cbb, arg);
1371 } else if (size <= 20) {
1372 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1373 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1375 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1376 arg->inst_basereg = src->dreg;
1377 arg->inst_offset = 0;
1378 arg->inst_imm = size;
1380 MONO_ADD_INS (cfg->cbb, arg);
1385 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1387 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1390 if (ret->type == MONO_TYPE_R4) {
1391 if (COMPILE_LLVM (cfg))
1392 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1395 } else if (ret->type == MONO_TYPE_R8) {
1396 if (COMPILE_LLVM (cfg))
1397 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1400 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1401 if (COMPILE_LLVM (cfg))
1402 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1404 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1405 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1411 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1415 * Allow tracing to work with this interface (with an optional argument)
1418 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1422 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1423 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1425 /* if some args are passed in registers, we need to save them here */
1426 x86_push_reg (code, X86_EBP);
1428 if (cfg->compile_aot) {
1429 x86_push_imm (code, cfg->method);
1430 x86_mov_reg_imm (code, X86_EAX, func);
1431 x86_call_reg (code, X86_EAX);
1433 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1434 x86_push_imm (code, cfg->method);
1435 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1436 x86_call_code (code, 0);
1438 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1452 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1455 int arg_size = 0, save_mode = SAVE_NONE;
1456 MonoMethod *method = cfg->method;
1458 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret)->type) {
1459 case MONO_TYPE_VOID:
1460 /* special case string .ctor icall */
1461 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
1462 save_mode = SAVE_EAX;
1464 save_mode = SAVE_NONE;
1468 save_mode = SAVE_EAX_EDX;
1472 save_mode = SAVE_FP;
1474 case MONO_TYPE_GENERICINST:
1475 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
1476 save_mode = SAVE_EAX;
1480 case MONO_TYPE_VALUETYPE:
1481 save_mode = SAVE_STRUCT;
1484 save_mode = SAVE_EAX;
1488 switch (save_mode) {
1490 x86_push_reg (code, X86_EDX);
1491 x86_push_reg (code, X86_EAX);
1492 if (enable_arguments) {
1493 x86_push_reg (code, X86_EDX);
1494 x86_push_reg (code, X86_EAX);
1499 x86_push_reg (code, X86_EAX);
1500 if (enable_arguments) {
1501 x86_push_reg (code, X86_EAX);
1506 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1507 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1508 if (enable_arguments) {
1509 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1510 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1515 if (enable_arguments) {
1516 x86_push_membase (code, X86_EBP, 8);
1525 if (cfg->compile_aot) {
1526 x86_push_imm (code, method);
1527 x86_mov_reg_imm (code, X86_EAX, func);
1528 x86_call_reg (code, X86_EAX);
1530 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1531 x86_push_imm (code, method);
1532 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1533 x86_call_code (code, 0);
1535 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1537 switch (save_mode) {
1539 x86_pop_reg (code, X86_EAX);
1540 x86_pop_reg (code, X86_EDX);
1543 x86_pop_reg (code, X86_EAX);
1546 x86_fld_membase (code, X86_ESP, 0, TRUE);
1547 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1557 #define EMIT_COND_BRANCH(ins,cond,sign) \
1558 if (ins->inst_true_bb->native_offset) { \
1559 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1561 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1562 if ((cfg->opt & MONO_OPT_BRANCH) && \
1563 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1564 x86_branch8 (code, cond, 0, sign); \
1566 x86_branch32 (code, cond, 0, sign); \
1570 * Emit an exception if condition is fail and
1571 * if possible do a directly branch to target
1573 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1575 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1576 if (tins == NULL) { \
1577 mono_add_patch_info (cfg, code - cfg->native_code, \
1578 MONO_PATCH_INFO_EXC, exc_name); \
1579 x86_branch32 (code, cond, 0, signed); \
1581 EMIT_COND_BRANCH (tins, cond, signed); \
1585 #define EMIT_FPCOMPARE(code) do { \
1586 x86_fcompp (code); \
1587 x86_fnstsw (code); \
1592 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1594 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1595 x86_call_code (code, 0);
1600 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1603 * mono_peephole_pass_1:
1605 * Perform peephole opts which should/can be performed before local regalloc
1608 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1612 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1613 MonoInst *last_ins = ins->prev;
1615 switch (ins->opcode) {
1618 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1620 * X86_LEA is like ADD, but doesn't have the
1621 * sreg1==dreg restriction.
1623 ins->opcode = OP_X86_LEA_MEMBASE;
1624 ins->inst_basereg = ins->sreg1;
1625 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1626 ins->opcode = OP_X86_INC_REG;
1630 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1631 ins->opcode = OP_X86_LEA_MEMBASE;
1632 ins->inst_basereg = ins->sreg1;
1633 ins->inst_imm = -ins->inst_imm;
1634 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1635 ins->opcode = OP_X86_DEC_REG;
1637 case OP_COMPARE_IMM:
1638 case OP_ICOMPARE_IMM:
1639 /* OP_COMPARE_IMM (reg, 0)
1641 * OP_X86_TEST_NULL (reg)
1644 ins->opcode = OP_X86_TEST_NULL;
1646 case OP_X86_COMPARE_MEMBASE_IMM:
1648 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1649 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1651 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1652 * OP_COMPARE_IMM reg, imm
1654 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1656 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1657 ins->inst_basereg == last_ins->inst_destbasereg &&
1658 ins->inst_offset == last_ins->inst_offset) {
1659 ins->opcode = OP_COMPARE_IMM;
1660 ins->sreg1 = last_ins->sreg1;
1662 /* check if we can remove cmp reg,0 with test null */
1664 ins->opcode = OP_X86_TEST_NULL;
1668 case OP_X86_PUSH_MEMBASE:
1669 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1670 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1671 ins->inst_basereg == last_ins->inst_destbasereg &&
1672 ins->inst_offset == last_ins->inst_offset) {
1673 ins->opcode = OP_X86_PUSH;
1674 ins->sreg1 = last_ins->sreg1;
1679 mono_peephole_ins (bb, ins);
1684 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1688 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1689 switch (ins->opcode) {
1691 /* reg = 0 -> XOR (reg, reg) */
1692 /* XOR sets cflags on x86, so we cant do it always */
1693 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1696 ins->opcode = OP_IXOR;
1697 ins->sreg1 = ins->dreg;
1698 ins->sreg2 = ins->dreg;
1701 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1702 * since it takes 3 bytes instead of 7.
1704 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
1705 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1706 ins2->opcode = OP_STORE_MEMBASE_REG;
1707 ins2->sreg1 = ins->dreg;
1709 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1710 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1711 ins2->sreg1 = ins->dreg;
1713 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1714 /* Continue iteration */
1723 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1724 ins->opcode = OP_X86_INC_REG;
1728 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1729 ins->opcode = OP_X86_DEC_REG;
1733 mono_peephole_ins (bb, ins);
1738 * mono_arch_lowering_pass:
1740 * Converts complex opcodes into simpler ones so that each IR instruction
1741 * corresponds to one machine instruction.
1744 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1746 MonoInst *ins, *next;
1749 * FIXME: Need to add more instructions, but the current machine
1750 * description can't model some parts of the composite instructions like
1753 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
1754 switch (ins->opcode) {
1757 case OP_IDIV_UN_IMM:
1758 case OP_IREM_UN_IMM:
1760 * Keep the cases where we could generated optimized code, otherwise convert
1761 * to the non-imm variant.
1763 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
1765 mono_decompose_op_imm (cfg, bb, ins);
1772 bb->max_vreg = cfg->next_vreg;
1776 branch_cc_table [] = {
1777 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1778 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1779 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1782 /* Maps CMP_... constants to X86_CC_... constants */
1785 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
1786 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
1790 cc_signed_table [] = {
1791 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
1792 FALSE, FALSE, FALSE, FALSE
1795 static unsigned char*
1796 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
1798 #define XMM_TEMP_REG 0
1799 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
1800 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
1801 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
1802 /* optimize by assigning a local var for this use so we avoid
1803 * the stack manipulations */
1804 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1805 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1806 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
1807 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
1808 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1810 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
1812 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
1815 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
1816 x86_fnstcw_membase(code, X86_ESP, 0);
1817 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
1818 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
1819 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
1820 x86_fldcw_membase (code, X86_ESP, 2);
1822 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1823 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
1824 x86_pop_reg (code, dreg);
1825 /* FIXME: need the high register
1826 * x86_pop_reg (code, dreg_high);
1829 x86_push_reg (code, X86_EAX); // SP = SP - 4
1830 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
1831 x86_pop_reg (code, dreg);
1833 x86_fldcw_membase (code, X86_ESP, 0);
1834 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
1837 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
1839 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
1843 static unsigned char*
1844 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
1846 int sreg = tree->sreg1;
1847 int need_touch = FALSE;
1849 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
1858 * If requested stack size is larger than one page,
1859 * perform stack-touch operation
1862 * Generate stack probe code.
1863 * Under Windows, it is necessary to allocate one page at a time,
1864 * "touching" stack after each successful sub-allocation. This is
1865 * because of the way stack growth is implemented - there is a
1866 * guard page before the lowest stack page that is currently commited.
1867 * Stack normally grows sequentially so OS traps access to the
1868 * guard page and commits more pages when needed.
1870 x86_test_reg_imm (code, sreg, ~0xFFF);
1871 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1873 br[2] = code; /* loop */
1874 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
1875 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
1878 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
1879 * that follows only initializes the last part of the area.
1881 /* Same as the init code below with size==0x1000 */
1882 if (tree->flags & MONO_INST_INIT) {
1883 x86_push_reg (code, X86_EAX);
1884 x86_push_reg (code, X86_ECX);
1885 x86_push_reg (code, X86_EDI);
1886 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
1887 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
1888 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
1890 x86_prefix (code, X86_REP_PREFIX);
1892 x86_pop_reg (code, X86_EDI);
1893 x86_pop_reg (code, X86_ECX);
1894 x86_pop_reg (code, X86_EAX);
1897 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
1898 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
1899 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
1900 x86_patch (br[3], br[2]);
1901 x86_test_reg_reg (code, sreg, sreg);
1902 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1903 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
1905 br[1] = code; x86_jump8 (code, 0);
1907 x86_patch (br[0], code);
1908 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
1909 x86_patch (br[1], code);
1910 x86_patch (br[4], code);
1913 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
1915 if (tree->flags & MONO_INST_INIT) {
1917 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
1918 x86_push_reg (code, X86_EAX);
1921 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
1922 x86_push_reg (code, X86_ECX);
1925 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
1926 x86_push_reg (code, X86_EDI);
1930 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
1931 if (sreg != X86_ECX)
1932 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
1933 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
1935 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
1937 x86_prefix (code, X86_REP_PREFIX);
1940 if (tree->dreg != X86_EDI && sreg != X86_EDI)
1941 x86_pop_reg (code, X86_EDI);
1942 if (tree->dreg != X86_ECX && sreg != X86_ECX)
1943 x86_pop_reg (code, X86_ECX);
1944 if (tree->dreg != X86_EAX && sreg != X86_EAX)
1945 x86_pop_reg (code, X86_EAX);
1952 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
1954 /* Move return value to the target register */
1955 switch (ins->opcode) {
1958 case OP_CALL_MEMBASE:
1959 if (ins->dreg != X86_EAX)
1960 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
1970 * mono_x86_emit_tls_get:
1971 * @code: buffer to store code to
1972 * @dreg: hard register where to place the result
1973 * @tls_offset: offset info
1975 * mono_x86_emit_tls_get emits in @code the native code that puts in
1976 * the dreg register the item in the thread local storage identified
1979 * Returns: a pointer to the end of the stored code
1982 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
1984 #ifdef PLATFORM_WIN32
1986 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
1987 * Journal and/or a disassembly of the TlsGet () function.
1989 g_assert (tls_offset < 64);
1990 x86_prefix (code, X86_FS_PREFIX);
1991 x86_mov_reg_mem (code, dreg, 0x18, 4);
1992 /* Dunno what this does but TlsGetValue () contains it */
1993 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
1994 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
1996 if (optimize_for_xen) {
1997 x86_prefix (code, X86_GS_PREFIX);
1998 x86_mov_reg_mem (code, dreg, 0, 4);
1999 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2001 x86_prefix (code, X86_GS_PREFIX);
2002 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2009 * emit_load_volatile_arguments:
2011 * Load volatile arguments from the stack to the original input registers.
2012 * Required before a tail call.
2015 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2017 MonoMethod *method = cfg->method;
2018 MonoMethodSignature *sig;
2023 /* FIXME: Generate intermediate code instead */
2025 sig = mono_method_signature (method);
2027 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
2029 /* This is the opposite of the code in emit_prolog */
2031 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2032 ArgInfo *ainfo = cinfo->args + i;
2034 inst = cfg->args [i];
2036 if (sig->hasthis && (i == 0))
2037 arg_type = &mono_defaults.object_class->byval_arg;
2039 arg_type = sig->params [i - sig->hasthis];
2042 * On x86, the arguments are either in their original stack locations, or in
2045 if (inst->opcode == OP_REGVAR) {
2046 g_assert (ainfo->storage == ArgOnStack);
2048 x86_mov_membase_reg (code, X86_EBP, inst->inst_offset, inst->dreg, 4);
2055 #define REAL_PRINT_REG(text,reg) \
2056 mono_assert (reg >= 0); \
2057 x86_push_reg (code, X86_EAX); \
2058 x86_push_reg (code, X86_EDX); \
2059 x86_push_reg (code, X86_ECX); \
2060 x86_push_reg (code, reg); \
2061 x86_push_imm (code, reg); \
2062 x86_push_imm (code, text " %d %p\n"); \
2063 x86_mov_reg_imm (code, X86_EAX, printf); \
2064 x86_call_reg (code, X86_EAX); \
2065 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2066 x86_pop_reg (code, X86_ECX); \
2067 x86_pop_reg (code, X86_EDX); \
2068 x86_pop_reg (code, X86_EAX);
2070 /* benchmark and set based on cpu */
2071 #define LOOP_ALIGNMENT 8
2072 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2077 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2082 guint8 *code = cfg->native_code + cfg->code_len;
2085 if (cfg->opt & MONO_OPT_LOOP) {
2086 int pad, align = LOOP_ALIGNMENT;
2087 /* set alignment depending on cpu */
2088 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2090 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2091 x86_padding (code, pad);
2092 cfg->code_len += pad;
2093 bb->native_offset = cfg->code_len;
2097 if (cfg->verbose_level > 2)
2098 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2100 cpos = bb->max_offset;
2102 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2103 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2104 g_assert (!cfg->compile_aot);
2107 cov->data [bb->dfn].cil_code = bb->cil_code;
2108 /* this is not thread save, but good enough */
2109 x86_inc_mem (code, &cov->data [bb->dfn].count);
2112 offset = code - cfg->native_code;
2114 mono_debug_open_block (cfg, bb, offset);
2116 MONO_BB_FOR_EACH_INS (bb, ins) {
2117 offset = code - cfg->native_code;
2119 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2121 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2122 cfg->code_size *= 2;
2123 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2124 code = cfg->native_code + offset;
2125 mono_jit_stats.code_reallocs++;
2128 if (cfg->debug_info)
2129 mono_debug_record_line_number (cfg, ins, offset);
2131 switch (ins->opcode) {
2133 x86_mul_reg (code, ins->sreg2, TRUE);
2136 x86_mul_reg (code, ins->sreg2, FALSE);
2138 case OP_X86_SETEQ_MEMBASE:
2139 case OP_X86_SETNE_MEMBASE:
2140 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2141 ins->inst_basereg, ins->inst_offset, TRUE);
2143 case OP_STOREI1_MEMBASE_IMM:
2144 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2146 case OP_STOREI2_MEMBASE_IMM:
2147 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2149 case OP_STORE_MEMBASE_IMM:
2150 case OP_STOREI4_MEMBASE_IMM:
2151 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2153 case OP_STOREI1_MEMBASE_REG:
2154 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2156 case OP_STOREI2_MEMBASE_REG:
2157 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2159 case OP_STORE_MEMBASE_REG:
2160 case OP_STOREI4_MEMBASE_REG:
2161 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2163 case OP_STORE_MEM_IMM:
2164 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2167 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2171 /* These are created by the cprop pass so they use inst_imm as the source */
2172 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2175 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2178 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2180 case OP_LOAD_MEMBASE:
2181 case OP_LOADI4_MEMBASE:
2182 case OP_LOADU4_MEMBASE:
2183 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2185 case OP_LOADU1_MEMBASE:
2186 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2188 case OP_LOADI1_MEMBASE:
2189 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2191 case OP_LOADU2_MEMBASE:
2192 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2194 case OP_LOADI2_MEMBASE:
2195 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2197 case OP_ICONV_TO_I1:
2199 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2201 case OP_ICONV_TO_I2:
2203 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2205 case OP_ICONV_TO_U1:
2206 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2208 case OP_ICONV_TO_U2:
2209 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2213 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2215 case OP_COMPARE_IMM:
2216 case OP_ICOMPARE_IMM:
2217 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2219 case OP_X86_COMPARE_MEMBASE_REG:
2220 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2222 case OP_X86_COMPARE_MEMBASE_IMM:
2223 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2225 case OP_X86_COMPARE_MEMBASE8_IMM:
2226 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2228 case OP_X86_COMPARE_REG_MEMBASE:
2229 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2231 case OP_X86_COMPARE_MEM_IMM:
2232 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2234 case OP_X86_TEST_NULL:
2235 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2237 case OP_X86_ADD_MEMBASE_IMM:
2238 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2240 case OP_X86_ADD_REG_MEMBASE:
2241 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2243 case OP_X86_SUB_MEMBASE_IMM:
2244 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2246 case OP_X86_SUB_REG_MEMBASE:
2247 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2249 case OP_X86_AND_MEMBASE_IMM:
2250 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2252 case OP_X86_OR_MEMBASE_IMM:
2253 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2255 case OP_X86_XOR_MEMBASE_IMM:
2256 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2258 case OP_X86_ADD_MEMBASE_REG:
2259 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2261 case OP_X86_SUB_MEMBASE_REG:
2262 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2264 case OP_X86_AND_MEMBASE_REG:
2265 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2267 case OP_X86_OR_MEMBASE_REG:
2268 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2270 case OP_X86_XOR_MEMBASE_REG:
2271 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2273 case OP_X86_INC_MEMBASE:
2274 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2276 case OP_X86_INC_REG:
2277 x86_inc_reg (code, ins->dreg);
2279 case OP_X86_DEC_MEMBASE:
2280 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2282 case OP_X86_DEC_REG:
2283 x86_dec_reg (code, ins->dreg);
2285 case OP_X86_MUL_REG_MEMBASE:
2286 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2288 case OP_X86_AND_REG_MEMBASE:
2289 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2291 case OP_X86_OR_REG_MEMBASE:
2292 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2294 case OP_X86_XOR_REG_MEMBASE:
2295 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2298 x86_breakpoint (code);
2300 case OP_RELAXED_NOP:
2301 x86_prefix (code, X86_REP_PREFIX);
2309 case OP_DUMMY_STORE:
2310 case OP_NOT_REACHED:
2316 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2320 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2325 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2329 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2334 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2338 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2343 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2347 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2350 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2354 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2359 * The code is the same for div/rem, the allocator will allocate dreg
2360 * to RAX/RDX as appropriate.
2362 if (ins->sreg2 == X86_EDX) {
2363 /* cdq clobbers this */
2364 x86_push_reg (code, ins->sreg2);
2366 x86_div_membase (code, X86_ESP, 0, TRUE);
2367 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2370 x86_div_reg (code, ins->sreg2, TRUE);
2375 if (ins->sreg2 == X86_EDX) {
2376 x86_push_reg (code, ins->sreg2);
2377 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2378 x86_div_membase (code, X86_ESP, 0, FALSE);
2379 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2381 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2382 x86_div_reg (code, ins->sreg2, FALSE);
2386 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2388 x86_div_reg (code, ins->sreg2, TRUE);
2391 int power = mono_is_power_of_two (ins->inst_imm);
2393 g_assert (ins->sreg1 == X86_EAX);
2394 g_assert (ins->dreg == X86_EAX);
2395 g_assert (power >= 0);
2398 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2400 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2402 * If the divident is >= 0, this does not nothing. If it is positive, it
2403 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2405 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2406 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2408 /* Based on gcc code */
2410 /* Add compensation for negative dividents */
2412 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2413 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2414 /* Compute remainder */
2415 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2416 /* Remove compensation */
2417 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2422 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2426 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2429 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2433 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2436 g_assert (ins->sreg2 == X86_ECX);
2437 x86_shift_reg (code, X86_SHL, ins->dreg);
2440 g_assert (ins->sreg2 == X86_ECX);
2441 x86_shift_reg (code, X86_SAR, ins->dreg);
2445 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2448 case OP_ISHR_UN_IMM:
2449 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2452 g_assert (ins->sreg2 == X86_ECX);
2453 x86_shift_reg (code, X86_SHR, ins->dreg);
2457 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2460 guint8 *jump_to_end;
2462 /* handle shifts below 32 bits */
2463 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2464 x86_shift_reg (code, X86_SHL, ins->sreg1);
2466 x86_test_reg_imm (code, X86_ECX, 32);
2467 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2469 /* handle shift over 32 bit */
2470 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2471 x86_clear_reg (code, ins->sreg1);
2473 x86_patch (jump_to_end, code);
2477 guint8 *jump_to_end;
2479 /* handle shifts below 32 bits */
2480 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2481 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2483 x86_test_reg_imm (code, X86_ECX, 32);
2484 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2486 /* handle shifts over 31 bits */
2487 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2488 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2490 x86_patch (jump_to_end, code);
2494 guint8 *jump_to_end;
2496 /* handle shifts below 32 bits */
2497 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2498 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2500 x86_test_reg_imm (code, X86_ECX, 32);
2501 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2503 /* handle shifts over 31 bits */
2504 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2505 x86_clear_reg (code, ins->backend.reg3);
2507 x86_patch (jump_to_end, code);
2511 if (ins->inst_imm >= 32) {
2512 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2513 x86_clear_reg (code, ins->sreg1);
2514 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2516 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2517 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2521 if (ins->inst_imm >= 32) {
2522 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2523 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2524 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2526 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2527 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2530 case OP_LSHR_UN_IMM:
2531 if (ins->inst_imm >= 32) {
2532 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2533 x86_clear_reg (code, ins->backend.reg3);
2534 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2536 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2537 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2541 x86_not_reg (code, ins->sreg1);
2544 x86_neg_reg (code, ins->sreg1);
2548 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2552 switch (ins->inst_imm) {
2556 if (ins->dreg != ins->sreg1)
2557 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2558 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2561 /* LEA r1, [r2 + r2*2] */
2562 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2565 /* LEA r1, [r2 + r2*4] */
2566 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2569 /* LEA r1, [r2 + r2*2] */
2571 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2572 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2575 /* LEA r1, [r2 + r2*8] */
2576 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2579 /* LEA r1, [r2 + r2*4] */
2581 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2582 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2585 /* LEA r1, [r2 + r2*2] */
2587 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2588 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2591 /* LEA r1, [r2 + r2*4] */
2592 /* LEA r1, [r1 + r1*4] */
2593 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2594 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2597 /* LEA r1, [r2 + r2*4] */
2599 /* LEA r1, [r1 + r1*4] */
2600 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2601 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2602 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2605 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2610 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2611 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2613 case OP_IMUL_OVF_UN: {
2614 /* the mul operation and the exception check should most likely be split */
2615 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2616 /*g_assert (ins->sreg2 == X86_EAX);
2617 g_assert (ins->dreg == X86_EAX);*/
2618 if (ins->sreg2 == X86_EAX) {
2619 non_eax_reg = ins->sreg1;
2620 } else if (ins->sreg1 == X86_EAX) {
2621 non_eax_reg = ins->sreg2;
2623 /* no need to save since we're going to store to it anyway */
2624 if (ins->dreg != X86_EAX) {
2626 x86_push_reg (code, X86_EAX);
2628 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
2629 non_eax_reg = ins->sreg2;
2631 if (ins->dreg == X86_EDX) {
2634 x86_push_reg (code, X86_EAX);
2636 } else if (ins->dreg != X86_EAX) {
2638 x86_push_reg (code, X86_EDX);
2640 x86_mul_reg (code, non_eax_reg, FALSE);
2641 /* save before the check since pop and mov don't change the flags */
2642 if (ins->dreg != X86_EAX)
2643 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2645 x86_pop_reg (code, X86_EDX);
2647 x86_pop_reg (code, X86_EAX);
2648 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2652 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
2655 g_assert_not_reached ();
2656 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2657 x86_mov_reg_imm (code, ins->dreg, 0);
2660 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2661 x86_mov_reg_imm (code, ins->dreg, 0);
2663 case OP_LOAD_GOTADDR:
2664 x86_call_imm (code, 0);
2666 * The patch needs to point to the pop, since the GOT offset needs
2667 * to be added to that address.
2669 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
2670 x86_pop_reg (code, ins->dreg);
2671 x86_alu_reg_imm (code, X86_ADD, ins->dreg, 0xf0f0f0f0);
2674 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2675 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
2677 case OP_X86_PUSH_GOT_ENTRY:
2678 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2679 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
2682 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2686 * Note: this 'frame destruction' logic is useful for tail calls, too.
2687 * Keep in sync with the code in emit_epilog.
2691 /* FIXME: no tracing support... */
2692 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2693 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2694 /* reset offset to make max_len work */
2695 offset = code - cfg->native_code;
2697 g_assert (!cfg->method->save_lmf);
2699 code = emit_load_volatile_arguments (cfg, code);
2701 if (cfg->used_int_regs & (1 << X86_EBX))
2703 if (cfg->used_int_regs & (1 << X86_EDI))
2705 if (cfg->used_int_regs & (1 << X86_ESI))
2708 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
2710 if (cfg->used_int_regs & (1 << X86_ESI))
2711 x86_pop_reg (code, X86_ESI);
2712 if (cfg->used_int_regs & (1 << X86_EDI))
2713 x86_pop_reg (code, X86_EDI);
2714 if (cfg->used_int_regs & (1 << X86_EBX))
2715 x86_pop_reg (code, X86_EBX);
2717 /* restore ESP/EBP */
2719 offset = code - cfg->native_code;
2720 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2721 x86_jump32 (code, 0);
2723 cfg->disable_aot = TRUE;
2727 /* ensure ins->sreg1 is not NULL
2728 * note that cmp DWORD PTR [eax], eax is one byte shorter than
2729 * cmp DWORD PTR [eax], 0
2731 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
2734 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
2735 x86_push_reg (code, hreg);
2736 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
2737 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
2738 x86_pop_reg (code, hreg);
2747 call = (MonoCallInst*)ins;
2748 if (ins->flags & MONO_INST_HAS_METHOD)
2749 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2751 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2752 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
2753 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
2754 * bytes to pop, we want to use pops. GCC does this (note it won't happen
2755 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
2756 * smart enough to do that optimization yet
2758 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
2759 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
2760 * (most likely from locality benefits). People with other processors should
2761 * check on theirs to see what happens.
2763 if (call->stack_usage == 4) {
2764 /* we want to use registers that won't get used soon, so use
2765 * ecx, as eax will get allocated first. edx is used by long calls,
2766 * so we can't use that.
2769 x86_pop_reg (code, X86_ECX);
2771 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2774 code = emit_move_return_value (cfg, ins, code);
2780 case OP_VOIDCALL_REG:
2782 call = (MonoCallInst*)ins;
2783 x86_call_reg (code, ins->sreg1);
2784 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
2785 if (call->stack_usage == 4)
2786 x86_pop_reg (code, X86_ECX);
2788 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2790 code = emit_move_return_value (cfg, ins, code);
2792 case OP_FCALL_MEMBASE:
2793 case OP_LCALL_MEMBASE:
2794 case OP_VCALL_MEMBASE:
2795 case OP_VCALL2_MEMBASE:
2796 case OP_VOIDCALL_MEMBASE:
2797 case OP_CALL_MEMBASE:
2798 call = (MonoCallInst*)ins;
2801 * Emit a few nops to simplify get_vcall_slot ().
2807 x86_call_membase (code, ins->sreg1, ins->inst_offset);
2808 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
2809 if (call->stack_usage == 4)
2810 x86_pop_reg (code, X86_ECX);
2812 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2814 code = emit_move_return_value (cfg, ins, code);
2817 x86_push_reg (code, ins->sreg1);
2819 case OP_X86_PUSH_IMM:
2820 x86_push_imm (code, ins->inst_imm);
2822 case OP_X86_PUSH_MEMBASE:
2823 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
2825 case OP_X86_PUSH_OBJ:
2826 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
2827 x86_push_reg (code, X86_EDI);
2828 x86_push_reg (code, X86_ESI);
2829 x86_push_reg (code, X86_ECX);
2830 if (ins->inst_offset)
2831 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
2833 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
2834 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2835 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
2837 x86_prefix (code, X86_REP_PREFIX);
2839 x86_pop_reg (code, X86_ECX);
2840 x86_pop_reg (code, X86_ESI);
2841 x86_pop_reg (code, X86_EDI);
2844 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
2846 case OP_X86_LEA_MEMBASE:
2847 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
2850 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
2853 /* keep alignment */
2854 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
2855 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
2856 code = mono_emit_stack_alloc (code, ins);
2857 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2859 case OP_LOCALLOC_IMM: {
2860 guint32 size = ins->inst_imm;
2861 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
2863 if (ins->flags & MONO_INST_INIT) {
2864 /* FIXME: Optimize this */
2865 x86_mov_reg_imm (code, ins->dreg, size);
2866 ins->sreg1 = ins->dreg;
2868 code = mono_emit_stack_alloc (code, ins);
2869 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2871 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
2872 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2877 x86_push_reg (code, ins->sreg1);
2878 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
2879 (gpointer)"mono_arch_throw_exception");
2883 x86_push_reg (code, ins->sreg1);
2884 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
2885 (gpointer)"mono_arch_rethrow_exception");
2888 case OP_CALL_HANDLER:
2889 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
2890 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2891 x86_call_imm (code, 0);
2892 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
2894 case OP_START_HANDLER: {
2895 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
2896 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
2899 case OP_ENDFINALLY: {
2900 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
2901 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
2905 case OP_ENDFILTER: {
2906 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
2907 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
2908 /* The local allocator will put the result into EAX */
2914 ins->inst_c0 = code - cfg->native_code;
2917 if (ins->inst_target_bb->native_offset) {
2918 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
2920 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2921 if ((cfg->opt & MONO_OPT_BRANCH) &&
2922 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
2923 x86_jump8 (code, 0);
2925 x86_jump32 (code, 0);
2929 x86_jump_reg (code, ins->sreg1);
2942 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
2943 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2945 case OP_COND_EXC_EQ:
2946 case OP_COND_EXC_NE_UN:
2947 case OP_COND_EXC_LT:
2948 case OP_COND_EXC_LT_UN:
2949 case OP_COND_EXC_GT:
2950 case OP_COND_EXC_GT_UN:
2951 case OP_COND_EXC_GE:
2952 case OP_COND_EXC_GE_UN:
2953 case OP_COND_EXC_LE:
2954 case OP_COND_EXC_LE_UN:
2955 case OP_COND_EXC_IEQ:
2956 case OP_COND_EXC_INE_UN:
2957 case OP_COND_EXC_ILT:
2958 case OP_COND_EXC_ILT_UN:
2959 case OP_COND_EXC_IGT:
2960 case OP_COND_EXC_IGT_UN:
2961 case OP_COND_EXC_IGE:
2962 case OP_COND_EXC_IGE_UN:
2963 case OP_COND_EXC_ILE:
2964 case OP_COND_EXC_ILE_UN:
2965 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
2967 case OP_COND_EXC_OV:
2968 case OP_COND_EXC_NO:
2970 case OP_COND_EXC_NC:
2971 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
2973 case OP_COND_EXC_IOV:
2974 case OP_COND_EXC_INO:
2975 case OP_COND_EXC_IC:
2976 case OP_COND_EXC_INC:
2977 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
2989 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
2997 case OP_CMOV_INE_UN:
2998 case OP_CMOV_IGE_UN:
2999 case OP_CMOV_IGT_UN:
3000 case OP_CMOV_ILE_UN:
3001 case OP_CMOV_ILT_UN:
3002 g_assert (ins->dreg == ins->sreg1);
3003 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3006 /* floating point opcodes */
3008 double d = *(double *)ins->inst_p0;
3010 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3012 } else if (d == 1.0) {
3015 if (cfg->compile_aot) {
3016 guint32 *val = (guint32*)&d;
3017 x86_push_imm (code, val [1]);
3018 x86_push_imm (code, val [0]);
3019 x86_fld_membase (code, X86_ESP, 0, TRUE);
3020 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3023 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3024 x86_fld (code, NULL, TRUE);
3030 float f = *(float *)ins->inst_p0;
3032 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3034 } else if (f == 1.0) {
3037 if (cfg->compile_aot) {
3038 guint32 val = *(guint32*)&f;
3039 x86_push_imm (code, val);
3040 x86_fld_membase (code, X86_ESP, 0, FALSE);
3041 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3044 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3045 x86_fld (code, NULL, FALSE);
3050 case OP_STORER8_MEMBASE_REG:
3051 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3053 case OP_LOADR8_SPILL_MEMBASE:
3054 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3057 case OP_LOADR8_MEMBASE:
3058 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3060 case OP_STORER4_MEMBASE_REG:
3061 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3063 case OP_LOADR4_MEMBASE:
3064 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3066 case OP_ICONV_TO_R4:
3067 x86_push_reg (code, ins->sreg1);
3068 x86_fild_membase (code, X86_ESP, 0, FALSE);
3069 /* Change precision */
3070 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3071 x86_fld_membase (code, X86_ESP, 0, FALSE);
3072 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3074 case OP_ICONV_TO_R8:
3075 x86_push_reg (code, ins->sreg1);
3076 x86_fild_membase (code, X86_ESP, 0, FALSE);
3077 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3079 case OP_ICONV_TO_R_UN:
3080 x86_push_imm (code, 0);
3081 x86_push_reg (code, ins->sreg1);
3082 x86_fild_membase (code, X86_ESP, 0, TRUE);
3083 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3085 case OP_X86_FP_LOAD_I8:
3086 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3088 case OP_X86_FP_LOAD_I4:
3089 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3091 case OP_FCONV_TO_R4:
3092 /* Change precision */
3093 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3094 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3095 x86_fld_membase (code, X86_ESP, 0, FALSE);
3096 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3098 case OP_FCONV_TO_I1:
3099 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3101 case OP_FCONV_TO_U1:
3102 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3104 case OP_FCONV_TO_I2:
3105 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3107 case OP_FCONV_TO_U2:
3108 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3110 case OP_FCONV_TO_I4:
3112 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3114 case OP_FCONV_TO_I8:
3115 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3116 x86_fnstcw_membase(code, X86_ESP, 0);
3117 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3118 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3119 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3120 x86_fldcw_membase (code, X86_ESP, 2);
3121 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3122 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3123 x86_pop_reg (code, ins->dreg);
3124 x86_pop_reg (code, ins->backend.reg3);
3125 x86_fldcw_membase (code, X86_ESP, 0);
3126 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3128 case OP_LCONV_TO_R8_2:
3129 x86_push_reg (code, ins->sreg2);
3130 x86_push_reg (code, ins->sreg1);
3131 x86_fild_membase (code, X86_ESP, 0, TRUE);
3132 /* Change precision */
3133 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3134 x86_fld_membase (code, X86_ESP, 0, TRUE);
3135 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3137 case OP_LCONV_TO_R4_2:
3138 x86_push_reg (code, ins->sreg2);
3139 x86_push_reg (code, ins->sreg1);
3140 x86_fild_membase (code, X86_ESP, 0, TRUE);
3141 /* Change precision */
3142 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3143 x86_fld_membase (code, X86_ESP, 0, FALSE);
3144 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3146 case OP_LCONV_TO_R_UN:
3147 case OP_LCONV_TO_R_UN_2: {
3148 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3151 /* load 64bit integer to FP stack */
3152 x86_push_reg (code, ins->sreg2);
3153 x86_push_reg (code, ins->sreg1);
3154 x86_fild_membase (code, X86_ESP, 0, TRUE);
3156 /* test if lreg is negative */
3157 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3158 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3160 /* add correction constant mn */
3161 x86_fld80_mem (code, mn);
3162 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3164 x86_patch (br, code);
3166 /* Change precision */
3167 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3168 x86_fld_membase (code, X86_ESP, 0, TRUE);
3170 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3174 case OP_LCONV_TO_OVF_I:
3175 case OP_LCONV_TO_OVF_I4_2: {
3176 guint8 *br [3], *label [1];
3180 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3182 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3184 /* If the low word top bit is set, see if we are negative */
3185 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3186 /* We are not negative (no top bit set, check for our top word to be zero */
3187 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3188 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3191 /* throw exception */
3192 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3194 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3195 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3196 x86_jump8 (code, 0);
3198 x86_jump32 (code, 0);
3200 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3201 x86_jump32 (code, 0);
3205 x86_patch (br [0], code);
3206 /* our top bit is set, check that top word is 0xfffffff */
3207 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3209 x86_patch (br [1], code);
3210 /* nope, emit exception */
3211 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3212 x86_patch (br [2], label [0]);
3214 if (ins->dreg != ins->sreg1)
3215 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3219 /* Not needed on the fp stack */
3222 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3225 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3228 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3231 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3239 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3244 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3251 * it really doesn't make sense to inline all this code,
3252 * it's here just to show that things may not be as simple
3255 guchar *check_pos, *end_tan, *pop_jump;
3256 x86_push_reg (code, X86_EAX);
3259 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3261 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3262 x86_fstp (code, 0); /* pop the 1.0 */
3264 x86_jump8 (code, 0);
3266 x86_fp_op (code, X86_FADD, 0);
3270 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3272 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3275 x86_patch (pop_jump, code);
3276 x86_fstp (code, 0); /* pop the 1.0 */
3277 x86_patch (check_pos, code);
3278 x86_patch (end_tan, code);
3280 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3281 x86_pop_reg (code, X86_EAX);
3288 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3297 g_assert (cfg->opt & MONO_OPT_CMOV);
3298 g_assert (ins->dreg == ins->sreg1);
3299 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3300 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3303 g_assert (cfg->opt & MONO_OPT_CMOV);
3304 g_assert (ins->dreg == ins->sreg1);
3305 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3306 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3309 g_assert (cfg->opt & MONO_OPT_CMOV);
3310 g_assert (ins->dreg == ins->sreg1);
3311 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3312 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3315 g_assert (cfg->opt & MONO_OPT_CMOV);
3316 g_assert (ins->dreg == ins->sreg1);
3317 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3318 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3324 x86_fxch (code, ins->inst_imm);
3329 x86_push_reg (code, X86_EAX);
3330 /* we need to exchange ST(0) with ST(1) */
3333 /* this requires a loop, because fprem somtimes
3334 * returns a partial remainder */
3336 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3337 /* x86_fprem1 (code); */
3340 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3342 x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3347 x86_pop_reg (code, X86_EAX);
3351 if (cfg->opt & MONO_OPT_FCMOV) {
3352 x86_fcomip (code, 1);
3356 /* this overwrites EAX */
3357 EMIT_FPCOMPARE(code);
3358 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3361 if (cfg->opt & MONO_OPT_FCMOV) {
3362 /* zeroing the register at the start results in
3363 * shorter and faster code (we can also remove the widening op)
3365 guchar *unordered_check;
3366 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3367 x86_fcomip (code, 1);
3369 unordered_check = code;
3370 x86_branch8 (code, X86_CC_P, 0, FALSE);
3371 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3372 x86_patch (unordered_check, code);
3375 if (ins->dreg != X86_EAX)
3376 x86_push_reg (code, X86_EAX);
3378 EMIT_FPCOMPARE(code);
3379 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3380 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3381 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3382 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3384 if (ins->dreg != X86_EAX)
3385 x86_pop_reg (code, X86_EAX);
3389 if (cfg->opt & MONO_OPT_FCMOV) {
3390 /* zeroing the register at the start results in
3391 * shorter and faster code (we can also remove the widening op)
3393 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3394 x86_fcomip (code, 1);
3396 if (ins->opcode == OP_FCLT_UN) {
3397 guchar *unordered_check = code;
3398 guchar *jump_to_end;
3399 x86_branch8 (code, X86_CC_P, 0, FALSE);
3400 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3402 x86_jump8 (code, 0);
3403 x86_patch (unordered_check, code);
3404 x86_inc_reg (code, ins->dreg);
3405 x86_patch (jump_to_end, code);
3407 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3411 if (ins->dreg != X86_EAX)
3412 x86_push_reg (code, X86_EAX);
3414 EMIT_FPCOMPARE(code);
3415 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3416 if (ins->opcode == OP_FCLT_UN) {
3417 guchar *is_not_zero_check, *end_jump;
3418 is_not_zero_check = code;
3419 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3421 x86_jump8 (code, 0);
3422 x86_patch (is_not_zero_check, code);
3423 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3425 x86_patch (end_jump, code);
3427 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3428 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3430 if (ins->dreg != X86_EAX)
3431 x86_pop_reg (code, X86_EAX);
3435 if (cfg->opt & MONO_OPT_FCMOV) {
3436 /* zeroing the register at the start results in
3437 * shorter and faster code (we can also remove the widening op)
3439 guchar *unordered_check;
3440 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3441 x86_fcomip (code, 1);
3443 if (ins->opcode == OP_FCGT) {
3444 unordered_check = code;
3445 x86_branch8 (code, X86_CC_P, 0, FALSE);
3446 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3447 x86_patch (unordered_check, code);
3449 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3453 if (ins->dreg != X86_EAX)
3454 x86_push_reg (code, X86_EAX);
3456 EMIT_FPCOMPARE(code);
3457 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3458 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3459 if (ins->opcode == OP_FCGT_UN) {
3460 guchar *is_not_zero_check, *end_jump;
3461 is_not_zero_check = code;
3462 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3464 x86_jump8 (code, 0);
3465 x86_patch (is_not_zero_check, code);
3466 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3468 x86_patch (end_jump, code);
3470 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3471 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3473 if (ins->dreg != X86_EAX)
3474 x86_pop_reg (code, X86_EAX);
3477 if (cfg->opt & MONO_OPT_FCMOV) {
3478 guchar *jump = code;
3479 x86_branch8 (code, X86_CC_P, 0, TRUE);
3480 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3481 x86_patch (jump, code);
3484 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3485 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3488 /* Branch if C013 != 100 */
3489 if (cfg->opt & MONO_OPT_FCMOV) {
3490 /* branch if !ZF or (PF|CF) */
3491 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3492 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3493 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3496 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3497 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3500 if (cfg->opt & MONO_OPT_FCMOV) {
3501 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3504 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3507 if (cfg->opt & MONO_OPT_FCMOV) {
3508 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3509 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3512 if (ins->opcode == OP_FBLT_UN) {
3513 guchar *is_not_zero_check, *end_jump;
3514 is_not_zero_check = code;
3515 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3517 x86_jump8 (code, 0);
3518 x86_patch (is_not_zero_check, code);
3519 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3521 x86_patch (end_jump, code);
3523 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3527 if (cfg->opt & MONO_OPT_FCMOV) {
3528 if (ins->opcode == OP_FBGT) {
3531 /* skip branch if C1=1 */
3533 x86_branch8 (code, X86_CC_P, 0, FALSE);
3534 /* branch if (C0 | C3) = 1 */
3535 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3536 x86_patch (br1, code);
3538 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3542 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3543 if (ins->opcode == OP_FBGT_UN) {
3544 guchar *is_not_zero_check, *end_jump;
3545 is_not_zero_check = code;
3546 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3548 x86_jump8 (code, 0);
3549 x86_patch (is_not_zero_check, code);
3550 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3552 x86_patch (end_jump, code);
3554 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3557 /* Branch if C013 == 100 or 001 */
3558 if (cfg->opt & MONO_OPT_FCMOV) {
3561 /* skip branch if C1=1 */
3563 x86_branch8 (code, X86_CC_P, 0, FALSE);
3564 /* branch if (C0 | C3) = 1 */
3565 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3566 x86_patch (br1, code);
3569 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3570 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3571 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3572 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3575 /* Branch if C013 == 000 */
3576 if (cfg->opt & MONO_OPT_FCMOV) {
3577 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3580 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3583 /* Branch if C013=000 or 100 */
3584 if (cfg->opt & MONO_OPT_FCMOV) {
3587 /* skip branch if C1=1 */
3589 x86_branch8 (code, X86_CC_P, 0, FALSE);
3590 /* branch if C0=0 */
3591 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3592 x86_patch (br1, code);
3595 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
3596 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
3597 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3600 /* Branch if C013 != 001 */
3601 if (cfg->opt & MONO_OPT_FCMOV) {
3602 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3603 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3606 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3607 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3611 x86_push_reg (code, X86_EAX);
3614 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
3615 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3616 x86_pop_reg (code, X86_EAX);
3618 /* Have to clean up the fp stack before throwing the exception */
3620 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3623 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3625 x86_patch (br1, code);
3629 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
3632 case OP_MEMORY_BARRIER: {
3633 /* Not needed on x86 */
3636 case OP_ATOMIC_ADD_I4: {
3637 int dreg = ins->dreg;
3639 if (dreg == ins->inst_basereg) {
3640 x86_push_reg (code, ins->sreg2);
3644 if (dreg != ins->sreg2)
3645 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
3647 x86_prefix (code, X86_LOCK_PREFIX);
3648 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
3650 if (dreg != ins->dreg) {
3651 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
3652 x86_pop_reg (code, dreg);
3657 case OP_ATOMIC_ADD_NEW_I4: {
3658 int dreg = ins->dreg;
3660 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
3661 if (ins->sreg2 == dreg) {
3662 if (dreg == X86_EBX) {
3664 if (ins->inst_basereg == X86_EDI)
3668 if (ins->inst_basereg == X86_EBX)
3671 } else if (ins->inst_basereg == dreg) {
3672 if (dreg == X86_EBX) {
3674 if (ins->sreg2 == X86_EDI)
3678 if (ins->sreg2 == X86_EBX)
3683 if (dreg != ins->dreg) {
3684 x86_push_reg (code, dreg);
3687 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
3688 x86_prefix (code, X86_LOCK_PREFIX);
3689 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
3690 /* dreg contains the old value, add with sreg2 value */
3691 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
3693 if (ins->dreg != dreg) {
3694 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
3695 x86_pop_reg (code, dreg);
3700 case OP_ATOMIC_EXCHANGE_I4: {
3702 int sreg2 = ins->sreg2;
3703 int breg = ins->inst_basereg;
3705 /* cmpxchg uses eax as comperand, need to make sure we can use it
3706 * hack to overcome limits in x86 reg allocator
3707 * (req: dreg == eax and sreg2 != eax and breg != eax)
3709 g_assert (ins->dreg == X86_EAX);
3711 /* We need the EAX reg for the cmpxchg */
3712 if (ins->sreg2 == X86_EAX) {
3713 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
3714 x86_push_reg (code, sreg2);
3715 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
3718 if (breg == X86_EAX) {
3719 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
3720 x86_push_reg (code, breg);
3721 x86_mov_reg_reg (code, breg, X86_EAX, 4);
3724 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
3726 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
3727 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
3728 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
3729 x86_patch (br [1], br [0]);
3731 if (breg != ins->inst_basereg)
3732 x86_pop_reg (code, breg);
3734 if (ins->sreg2 != sreg2)
3735 x86_pop_reg (code, sreg2);
3739 case OP_ATOMIC_CAS_I4: {
3740 g_assert (ins->sreg3 == X86_EAX);
3741 g_assert (ins->sreg1 != X86_EAX);
3742 g_assert (ins->sreg1 != ins->sreg2);
3744 x86_prefix (code, X86_LOCK_PREFIX);
3745 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
3747 if (ins->dreg != X86_EAX)
3748 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3751 #ifdef MONO_ARCH_SIMD_INTRINSICS
3753 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
3756 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
3759 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
3762 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
3765 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
3768 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
3771 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
3772 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
3775 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
3778 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
3781 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
3784 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
3787 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
3790 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
3793 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
3796 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
3799 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
3802 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
3805 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
3808 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
3811 case OP_PSHUFLEW_HIGH:
3812 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
3813 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
3815 case OP_PSHUFLEW_LOW:
3816 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
3817 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
3820 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
3821 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
3825 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
3828 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
3831 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
3834 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
3837 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
3840 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
3843 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
3844 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
3847 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
3850 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
3853 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
3856 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
3859 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
3862 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
3865 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
3868 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
3871 case OP_EXTRACT_MASK:
3872 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
3876 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
3879 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
3882 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
3886 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
3889 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
3892 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
3895 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
3899 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
3902 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
3905 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
3908 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
3912 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
3915 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
3918 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
3922 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
3925 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
3928 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
3932 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
3935 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
3939 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
3942 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
3945 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
3949 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
3952 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
3955 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
3959 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
3962 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
3965 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
3968 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
3972 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
3975 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
3978 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
3981 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
3984 case OP_PSUM_ABS_DIFF:
3985 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
3988 case OP_UNPACK_LOWB:
3989 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
3991 case OP_UNPACK_LOWW:
3992 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
3994 case OP_UNPACK_LOWD:
3995 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
3997 case OP_UNPACK_LOWQ:
3998 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4000 case OP_UNPACK_LOWPS:
4001 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4003 case OP_UNPACK_LOWPD:
4004 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4007 case OP_UNPACK_HIGHB:
4008 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4010 case OP_UNPACK_HIGHW:
4011 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4013 case OP_UNPACK_HIGHD:
4014 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4016 case OP_UNPACK_HIGHQ:
4017 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4019 case OP_UNPACK_HIGHPS:
4020 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4022 case OP_UNPACK_HIGHPD:
4023 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4027 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4030 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4033 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4036 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4039 case OP_PADDB_SAT_UN:
4040 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4042 case OP_PSUBB_SAT_UN:
4043 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4045 case OP_PADDW_SAT_UN:
4046 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4048 case OP_PSUBW_SAT_UN:
4049 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4053 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4056 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4059 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4062 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4066 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4069 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4072 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4074 case OP_PMULW_HIGH_UN:
4075 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4078 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4082 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4085 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4089 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4092 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4096 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4099 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4103 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4106 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4110 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4113 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4117 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4120 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4124 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4127 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4131 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4134 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4138 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4141 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4145 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4147 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4148 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4152 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4154 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4155 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4159 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4161 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4162 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4166 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4168 case OP_EXTRACTX_U2:
4169 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4171 case OP_INSERTX_U1_SLOW:
4172 /*sreg1 is the extracted ireg (scratch)
4173 /sreg2 is the to be inserted ireg (scratch)
4174 /dreg is the xreg to receive the value*/
4176 /*clear the bits from the extracted word*/
4177 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4178 /*shift the value to insert if needed*/
4179 if (ins->inst_c0 & 1)
4180 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4181 /*join them together*/
4182 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4183 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4185 case OP_INSERTX_I4_SLOW:
4186 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4187 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4188 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4191 case OP_INSERTX_R4_SLOW:
4192 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4193 /*TODO if inst_c0 == 0 use movss*/
4194 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4195 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4197 case OP_INSERTX_R8_SLOW:
4198 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4200 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4202 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVSD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4205 case OP_STOREX_MEMBASE_REG:
4206 case OP_STOREX_MEMBASE:
4207 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4209 case OP_LOADX_MEMBASE:
4210 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4212 case OP_LOADX_ALIGNED_MEMBASE:
4213 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4215 case OP_STOREX_ALIGNED_MEMBASE_REG:
4216 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4218 case OP_STOREX_NTA_MEMBASE_REG:
4219 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4221 case OP_PREFETCH_MEMBASE:
4222 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4226 /*FIXME the peephole pass should have killed this*/
4227 if (ins->dreg != ins->sreg1)
4228 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4231 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4233 case OP_ICONV_TO_R8_RAW:
4234 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4235 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4238 case OP_FCONV_TO_R8_X:
4239 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4240 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4243 case OP_XCONV_R8_TO_I4:
4244 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4245 switch (ins->backend.source_opcode) {
4246 case OP_FCONV_TO_I1:
4247 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4249 case OP_FCONV_TO_U1:
4250 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4252 case OP_FCONV_TO_I2:
4253 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4255 case OP_FCONV_TO_U2:
4256 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4262 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4263 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4264 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4265 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4266 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4267 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4270 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4271 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4272 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4275 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4276 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4279 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4280 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4281 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4284 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4285 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4286 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4289 case OP_LIVERANGE_START: {
4290 if (cfg->verbose_level > 1)
4291 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4292 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4295 case OP_LIVERANGE_END: {
4296 if (cfg->verbose_level > 1)
4297 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4298 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4302 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4303 g_assert_not_reached ();
4306 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4307 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4308 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4309 g_assert_not_reached ();
4315 cfg->code_len = code - cfg->native_code;
4318 #endif /* DISABLE_JIT */
4321 mono_arch_register_lowlevel_calls (void)
4326 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4328 MonoJumpInfo *patch_info;
4329 gboolean compile_aot = !run_cctors;
4331 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4332 unsigned char *ip = patch_info->ip.i + code;
4333 const unsigned char *target;
4335 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4338 switch (patch_info->type) {
4339 case MONO_PATCH_INFO_BB:
4340 case MONO_PATCH_INFO_LABEL:
4343 /* No need to patch these */
4348 switch (patch_info->type) {
4349 case MONO_PATCH_INFO_IP:
4350 *((gconstpointer *)(ip)) = target;
4352 case MONO_PATCH_INFO_CLASS_INIT: {
4354 /* Might already been changed to a nop */
4355 x86_call_code (code, 0);
4356 x86_patch (ip, target);
4359 case MONO_PATCH_INFO_ABS:
4360 case MONO_PATCH_INFO_METHOD:
4361 case MONO_PATCH_INFO_METHOD_JUMP:
4362 case MONO_PATCH_INFO_INTERNAL_METHOD:
4363 case MONO_PATCH_INFO_BB:
4364 case MONO_PATCH_INFO_LABEL:
4365 case MONO_PATCH_INFO_RGCTX_FETCH:
4366 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
4367 case MONO_PATCH_INFO_MONITOR_ENTER:
4368 case MONO_PATCH_INFO_MONITOR_EXIT:
4369 x86_patch (ip, target);
4371 case MONO_PATCH_INFO_NONE:
4374 guint32 offset = mono_arch_get_patch_offset (ip);
4375 *((gconstpointer *)(ip + offset)) = target;
4383 mono_arch_emit_prolog (MonoCompile *cfg)
4385 MonoMethod *method = cfg->method;
4387 MonoMethodSignature *sig;
4389 int alloc_size, pos, max_offset, i, cfa_offset;
4391 gboolean need_stack_frame;
4393 cfg->code_size = MAX (mono_method_get_header (method)->code_size * 4, 10240);
4395 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4396 cfg->code_size += 512;
4398 code = cfg->native_code = g_malloc (cfg->code_size);
4400 /* Offset between RSP and the CFA */
4404 cfa_offset = sizeof (gpointer);
4405 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
4406 // IP saved at CFA - 4
4407 /* There is no IP reg on x86 */
4408 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
4410 need_stack_frame = needs_stack_frame (cfg);
4412 if (need_stack_frame) {
4413 x86_push_reg (code, X86_EBP);
4414 cfa_offset += sizeof (gpointer);
4415 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4416 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
4417 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
4418 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
4421 alloc_size = cfg->stack_offset;
4424 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4425 /* Might need to attach the thread to the JIT or change the domain for the callback */
4426 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4427 guint8 *buf, *no_domain_branch;
4429 code = mono_x86_emit_tls_get (code, X86_EAX, appdomain_tls_offset);
4430 x86_alu_reg_imm (code, X86_CMP, X86_EAX, GPOINTER_TO_UINT (cfg->domain));
4431 no_domain_branch = code;
4432 x86_branch8 (code, X86_CC_NE, 0, 0);
4433 code = mono_x86_emit_tls_get ( code, X86_EAX, lmf_tls_offset);
4434 x86_test_reg_reg (code, X86_EAX, X86_EAX);
4436 x86_branch8 (code, X86_CC_NE, 0, 0);
4437 x86_patch (no_domain_branch, code);
4438 x86_push_imm (code, cfg->domain);
4439 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4440 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
4441 x86_patch (buf, code);
4442 #ifdef PLATFORM_WIN32
4443 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4444 /* FIXME: Add a separate key for LMF to avoid this */
4445 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4449 g_assert (!cfg->compile_aot);
4450 x86_push_imm (code, cfg->domain);
4451 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4452 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
4456 if (method->save_lmf) {
4457 pos += sizeof (MonoLMF);
4459 /* save the current IP */
4460 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
4461 x86_push_imm_template (code);
4462 cfa_offset += sizeof (gpointer);
4464 /* save all caller saved regs */
4465 x86_push_reg (code, X86_EBP);
4466 cfa_offset += sizeof (gpointer);
4467 x86_push_reg (code, X86_ESI);
4468 cfa_offset += sizeof (gpointer);
4469 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
4470 x86_push_reg (code, X86_EDI);
4471 cfa_offset += sizeof (gpointer);
4472 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
4473 x86_push_reg (code, X86_EBX);
4474 cfa_offset += sizeof (gpointer);
4475 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
4477 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
4479 * Optimized version which uses the mono_lmf TLS variable instead of indirection
4480 * through the mono_lmf_addr TLS variable.
4482 /* %eax = previous_lmf */
4483 x86_prefix (code, X86_GS_PREFIX);
4484 x86_mov_reg_mem (code, X86_EAX, lmf_tls_offset, 4);
4485 /* skip esp + method_info + lmf */
4486 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 12);
4487 /* push previous_lmf */
4488 x86_push_reg (code, X86_EAX);
4490 x86_prefix (code, X86_GS_PREFIX);
4491 x86_mov_mem_reg (code, lmf_tls_offset, X86_ESP, 4);
4493 /* get the address of lmf for the current thread */
4495 * This is performance critical so we try to use some tricks to make
4499 if (lmf_addr_tls_offset != -1) {
4500 /* Load lmf quicky using the GS register */
4501 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
4502 #ifdef PLATFORM_WIN32
4503 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4504 /* FIXME: Add a separate key for LMF to avoid this */
4505 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4508 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
4511 /* Skip esp + method info */
4512 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
4515 x86_push_reg (code, X86_EAX);
4516 /* push *lfm (previous_lmf) */
4517 x86_push_membase (code, X86_EAX, 0);
4519 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
4523 if (cfg->used_int_regs & (1 << X86_EBX)) {
4524 x86_push_reg (code, X86_EBX);
4526 cfa_offset += sizeof (gpointer);
4527 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
4530 if (cfg->used_int_regs & (1 << X86_EDI)) {
4531 x86_push_reg (code, X86_EDI);
4533 cfa_offset += sizeof (gpointer);
4534 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
4537 if (cfg->used_int_regs & (1 << X86_ESI)) {
4538 x86_push_reg (code, X86_ESI);
4540 cfa_offset += sizeof (gpointer);
4541 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
4547 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
4548 if (mono_do_x86_stack_align && need_stack_frame) {
4549 int tot = alloc_size + pos + 4; /* ret ip */
4550 if (need_stack_frame)
4552 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
4554 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
4558 /* See mono_emit_stack_alloc */
4559 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4560 guint32 remaining_size = alloc_size;
4561 while (remaining_size >= 0x1000) {
4562 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
4563 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
4564 remaining_size -= 0x1000;
4567 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
4569 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
4572 g_assert (need_stack_frame);
4575 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
4576 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
4577 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
4580 #if DEBUG_STACK_ALIGNMENT
4581 /* check the stack is aligned */
4582 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
4583 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
4584 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
4585 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
4586 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
4587 x86_breakpoint (code);
4591 /* compute max_offset in order to use short forward jumps */
4593 if (cfg->opt & MONO_OPT_BRANCH) {
4594 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4596 bb->max_offset = max_offset;
4598 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4600 /* max alignment for loops */
4601 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4602 max_offset += LOOP_ALIGNMENT;
4604 MONO_BB_FOR_EACH_INS (bb, ins) {
4605 if (ins->opcode == OP_LABEL)
4606 ins->inst_c1 = max_offset;
4608 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4613 /* store runtime generic context */
4614 if (cfg->rgctx_var) {
4615 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
4617 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
4620 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4621 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4623 /* load arguments allocated to register from the stack */
4624 sig = mono_method_signature (method);
4627 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4628 inst = cfg->args [pos];
4629 if (inst->opcode == OP_REGVAR) {
4630 g_assert (need_stack_frame);
4631 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
4632 if (cfg->verbose_level > 2)
4633 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
4638 cfg->code_len = code - cfg->native_code;
4640 g_assert (cfg->code_len < cfg->code_size);
4646 mono_arch_emit_epilog (MonoCompile *cfg)
4648 MonoMethod *method = cfg->method;
4649 MonoMethodSignature *sig = mono_method_signature (method);
4651 guint32 stack_to_pop;
4653 int max_epilog_size = 16;
4655 gboolean need_stack_frame = needs_stack_frame (cfg);
4657 if (cfg->method->save_lmf)
4658 max_epilog_size += 128;
4660 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4661 cfg->code_size *= 2;
4662 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4663 mono_jit_stats.code_reallocs++;
4666 code = cfg->native_code + cfg->code_len;
4668 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4669 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4671 /* the code restoring the registers must be kept in sync with OP_JMP */
4674 if (method->save_lmf) {
4675 gint32 prev_lmf_reg;
4676 gint32 lmf_offset = -sizeof (MonoLMF);
4678 /* check if we need to restore protection of the stack after a stack overflow */
4679 if (mono_get_jit_tls_offset () != -1) {
4681 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
4682 /* we load the value in a separate instruction: this mechanism may be
4683 * used later as a safer way to do thread interruption
4685 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
4686 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
4688 x86_branch8 (code, X86_CC_Z, 0, FALSE);
4689 /* note that the call trampoline will preserve eax/edx */
4690 x86_call_reg (code, X86_ECX);
4691 x86_patch (patch, code);
4693 /* FIXME: maybe save the jit tls in the prolog */
4695 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
4697 * Optimized version which uses the mono_lmf TLS variable instead of indirection
4698 * through the mono_lmf_addr TLS variable.
4700 /* reg = previous_lmf */
4701 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
4703 /* lmf = previous_lmf */
4704 x86_prefix (code, X86_GS_PREFIX);
4705 x86_mov_mem_reg (code, lmf_tls_offset, X86_ECX, 4);
4707 /* Find a spare register */
4708 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
4711 prev_lmf_reg = X86_EDI;
4712 cfg->used_int_regs |= (1 << X86_EDI);
4715 prev_lmf_reg = X86_EDX;
4719 /* reg = previous_lmf */
4720 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
4723 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
4725 /* *(lmf) = previous_lmf */
4726 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
4729 /* restore caller saved regs */
4730 if (cfg->used_int_regs & (1 << X86_EBX)) {
4731 x86_mov_reg_membase (code, X86_EBX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
4734 if (cfg->used_int_regs & (1 << X86_EDI)) {
4735 x86_mov_reg_membase (code, X86_EDI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
4737 if (cfg->used_int_regs & (1 << X86_ESI)) {
4738 x86_mov_reg_membase (code, X86_ESI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
4741 /* EBP is restored by LEAVE */
4743 if (cfg->used_int_regs & (1 << X86_EBX)) {
4746 if (cfg->used_int_regs & (1 << X86_EDI)) {
4749 if (cfg->used_int_regs & (1 << X86_ESI)) {
4754 g_assert (need_stack_frame);
4755 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
4758 if (cfg->used_int_regs & (1 << X86_ESI)) {
4759 x86_pop_reg (code, X86_ESI);
4761 if (cfg->used_int_regs & (1 << X86_EDI)) {
4762 x86_pop_reg (code, X86_EDI);
4764 if (cfg->used_int_regs & (1 << X86_EBX)) {
4765 x86_pop_reg (code, X86_EBX);
4769 /* Load returned vtypes into registers if needed */
4770 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
4771 if (cinfo->ret.storage == ArgValuetypeInReg) {
4772 for (quad = 0; quad < 2; quad ++) {
4773 switch (cinfo->ret.pair_storage [quad]) {
4775 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
4777 case ArgOnFloatFpStack:
4778 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
4780 case ArgOnDoubleFpStack:
4781 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
4786 g_assert_not_reached ();
4791 if (need_stack_frame)
4794 if (CALLCONV_IS_STDCALL (sig)) {
4795 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
4797 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
4798 } else if (MONO_TYPE_ISSTRUCT (mono_method_signature (cfg->method)->ret) && (cinfo->ret.storage == ArgOnStack))
4804 g_assert (need_stack_frame);
4805 x86_ret_imm (code, stack_to_pop);
4810 cfg->code_len = code - cfg->native_code;
4812 g_assert (cfg->code_len < cfg->code_size);
4816 mono_arch_emit_exceptions (MonoCompile *cfg)
4818 MonoJumpInfo *patch_info;
4821 MonoClass *exc_classes [16];
4822 guint8 *exc_throw_start [16], *exc_throw_end [16];
4826 /* Compute needed space */
4827 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4828 if (patch_info->type == MONO_PATCH_INFO_EXC)
4833 * make sure we have enough space for exceptions
4834 * 16 is the size of two push_imm instructions and a call
4836 if (cfg->compile_aot)
4837 code_size = exc_count * 32;
4839 code_size = exc_count * 16;
4841 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4842 cfg->code_size *= 2;
4843 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4844 mono_jit_stats.code_reallocs++;
4847 code = cfg->native_code + cfg->code_len;
4850 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4851 switch (patch_info->type) {
4852 case MONO_PATCH_INFO_EXC: {
4853 MonoClass *exc_class;
4857 x86_patch (patch_info->ip.i + cfg->native_code, code);
4859 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4860 g_assert (exc_class);
4861 throw_ip = patch_info->ip.i;
4863 /* Find a throw sequence for the same exception class */
4864 for (i = 0; i < nthrows; ++i)
4865 if (exc_classes [i] == exc_class)
4868 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
4869 x86_jump_code (code, exc_throw_start [i]);
4870 patch_info->type = MONO_PATCH_INFO_NONE;
4875 /* Compute size of code following the push <OFFSET> */
4878 if ((code - cfg->native_code) - throw_ip < 126 - size) {
4879 /* Use the shorter form */
4881 x86_push_imm (code, 0);
4885 x86_push_imm (code, 0xf0f0f0f0);
4890 exc_classes [nthrows] = exc_class;
4891 exc_throw_start [nthrows] = code;
4894 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
4895 patch_info->data.name = "mono_arch_throw_corlib_exception";
4896 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4897 patch_info->ip.i = code - cfg->native_code;
4898 x86_call_code (code, 0);
4899 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
4904 exc_throw_end [nthrows] = code;
4916 cfg->code_len = code - cfg->native_code;
4918 g_assert (cfg->code_len < cfg->code_size);
4922 mono_arch_flush_icache (guint8 *code, gint size)
4928 mono_arch_flush_register_windows (void)
4933 mono_arch_is_inst_imm (gint64 imm)
4939 * Support for fast access to the thread-local lmf structure using the GS
4940 * segment register on NPTL + kernel 2.6.x.
4943 static gboolean tls_offset_inited = FALSE;
4946 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
4948 if (!tls_offset_inited) {
4949 if (!getenv ("MONO_NO_TLS")) {
4950 #ifdef PLATFORM_WIN32
4952 * We need to init this multiple times, since when we are first called, the key might not
4953 * be initialized yet.
4955 appdomain_tls_offset = mono_domain_get_tls_key ();
4956 lmf_tls_offset = mono_get_jit_tls_key ();
4957 thread_tls_offset = mono_thread_get_tls_key ();
4959 /* Only 64 tls entries can be accessed using inline code */
4960 if (appdomain_tls_offset >= 64)
4961 appdomain_tls_offset = -1;
4962 if (lmf_tls_offset >= 64)
4963 lmf_tls_offset = -1;
4964 if (thread_tls_offset >= 64)
4965 thread_tls_offset = -1;
4968 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
4970 tls_offset_inited = TRUE;
4971 appdomain_tls_offset = mono_domain_get_tls_offset ();
4972 lmf_tls_offset = mono_get_lmf_tls_offset ();
4973 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
4974 thread_tls_offset = mono_thread_get_tls_offset ();
4981 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4985 #ifdef MONO_ARCH_HAVE_IMT
4987 // Linear handler, the bsearch head compare is shorter
4988 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4989 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
4990 // x86_patch(ins,target)
4991 //[1 + 5] x86_jump_mem(inst,mem)
4994 #define BR_SMALL_SIZE 2
4995 #define BR_LARGE_SIZE 5
4996 #define JUMP_IMM_SIZE 6
4997 #define ENABLE_WRONG_METHOD_CHECK 0
5000 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5002 int i, distance = 0;
5003 for (i = start; i < target; ++i)
5004 distance += imt_entries [i]->chunk_size;
5009 * LOCKING: called with the domain lock held
5012 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5013 gpointer fail_tramp)
5017 guint8 *code, *start;
5019 for (i = 0; i < count; ++i) {
5020 MonoIMTCheckItem *item = imt_entries [i];
5021 if (item->is_equals) {
5022 if (item->check_target_idx) {
5023 if (!item->compare_done)
5024 item->chunk_size += CMP_SIZE;
5025 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5028 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5030 item->chunk_size += JUMP_IMM_SIZE;
5031 #if ENABLE_WRONG_METHOD_CHECK
5032 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5037 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5038 imt_entries [item->check_target_idx]->compare_done = TRUE;
5040 size += item->chunk_size;
5043 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5045 code = mono_domain_code_reserve (domain, size);
5047 for (i = 0; i < count; ++i) {
5048 MonoIMTCheckItem *item = imt_entries [i];
5049 item->code_target = code;
5050 if (item->is_equals) {
5051 if (item->check_target_idx) {
5052 if (!item->compare_done)
5053 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5054 item->jmp_code = code;
5055 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5056 if (item->has_target_code)
5057 x86_jump_code (code, item->value.target_code);
5059 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5062 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5063 item->jmp_code = code;
5064 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5065 if (item->has_target_code)
5066 x86_jump_code (code, item->value.target_code);
5068 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5069 x86_patch (item->jmp_code, code);
5070 x86_jump_code (code, fail_tramp);
5071 item->jmp_code = NULL;
5073 /* enable the commented code to assert on wrong method */
5074 #if ENABLE_WRONG_METHOD_CHECK
5075 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5076 item->jmp_code = code;
5077 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5079 if (item->has_target_code)
5080 x86_jump_code (code, item->value.target_code);
5082 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5083 #if ENABLE_WRONG_METHOD_CHECK
5084 x86_patch (item->jmp_code, code);
5085 x86_breakpoint (code);
5086 item->jmp_code = NULL;
5091 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5092 item->jmp_code = code;
5093 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5094 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5096 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5099 /* patch the branches to get to the target items */
5100 for (i = 0; i < count; ++i) {
5101 MonoIMTCheckItem *item = imt_entries [i];
5102 if (item->jmp_code) {
5103 if (item->check_target_idx) {
5104 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5110 mono_stats.imt_thunks_size += code - start;
5111 g_assert (code - start <= size);
5116 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5118 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5122 mono_arch_find_this_argument (mgreg_t *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
5124 MonoMethodSignature *sig = mono_method_signature (method);
5125 CallInfo *cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5126 int this_argument_offset;
5127 MonoObject *this_argument;
5130 * this is the offset of the this arg from esp as saved at the start of
5131 * mono_arch_create_trampoline_code () in tramp-x86.c.
5133 this_argument_offset = 5;
5134 if (MONO_TYPE_ISSTRUCT (sig->ret) && (cinfo->ret.storage == ArgOnStack))
5135 this_argument_offset++;
5137 this_argument = * (MonoObject**) (((guint8*) regs [X86_ESP]) + this_argument_offset * sizeof (gpointer));
5140 return this_argument;
5145 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5147 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5151 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5153 MonoInst *ins = NULL;
5156 if (cmethod->klass == mono_defaults.math_class) {
5157 if (strcmp (cmethod->name, "Sin") == 0) {
5159 } else if (strcmp (cmethod->name, "Cos") == 0) {
5161 } else if (strcmp (cmethod->name, "Tan") == 0) {
5163 } else if (strcmp (cmethod->name, "Atan") == 0) {
5165 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5167 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5169 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5174 MONO_INST_NEW (cfg, ins, opcode);
5175 ins->type = STACK_R8;
5176 ins->dreg = mono_alloc_freg (cfg);
5177 ins->sreg1 = args [0]->dreg;
5178 MONO_ADD_INS (cfg->cbb, ins);
5181 if (cfg->opt & MONO_OPT_CMOV) {
5184 if (strcmp (cmethod->name, "Min") == 0) {
5185 if (fsig->params [0]->type == MONO_TYPE_I4)
5187 } else if (strcmp (cmethod->name, "Max") == 0) {
5188 if (fsig->params [0]->type == MONO_TYPE_I4)
5193 MONO_INST_NEW (cfg, ins, opcode);
5194 ins->type = STACK_I4;
5195 ins->dreg = mono_alloc_ireg (cfg);
5196 ins->sreg1 = args [0]->dreg;
5197 ins->sreg2 = args [1]->dreg;
5198 MONO_ADD_INS (cfg->cbb, ins);
5203 /* OP_FREM is not IEEE compatible */
5204 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5205 MONO_INST_NEW (cfg, ins, OP_FREM);
5206 ins->inst_i0 = args [0];
5207 ins->inst_i1 = args [1];
5216 mono_arch_print_tree (MonoInst *tree, int arity)
5221 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5227 if (appdomain_tls_offset == -1)
5230 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5231 ins->inst_offset = appdomain_tls_offset;
5235 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
5239 if (thread_tls_offset == -1)
5242 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5243 ins->inst_offset = thread_tls_offset;
5248 mono_arch_get_patch_offset (guint8 *code)
5250 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5252 else if ((code [0] == 0xba))
5254 else if ((code [0] == 0x68))
5257 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5258 /* push <OFFSET>(<REG>) */
5260 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5261 /* call *<OFFSET>(<REG>) */
5263 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5266 else if ((code [0] == 0x58) && (code [1] == 0x05))
5267 /* pop %eax; add <OFFSET>, %eax */
5269 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5270 /* pop <REG>; add <OFFSET>, <REG> */
5272 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5273 /* mov <REG>, imm */
5276 g_assert_not_reached ();
5282 * mono_breakpoint_clean_code:
5284 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5285 * breakpoints in the original code, they are removed in the copy.
5287 * Returns TRUE if no sw breakpoint was present.
5290 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5293 gboolean can_write = TRUE;
5295 * If method_start is non-NULL we need to perform bound checks, since we access memory
5296 * at code - offset we could go before the start of the method and end up in a different
5297 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5300 if (!method_start || code - offset >= method_start) {
5301 memcpy (buf, code - offset, size);
5303 int diff = code - method_start;
5304 memset (buf, 0, size);
5305 memcpy (buf + offset - diff, method_start, diff + size - offset);
5308 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5309 int idx = mono_breakpoint_info_index [i];
5313 ptr = mono_breakpoint_info [idx].address;
5314 if (ptr >= code && ptr < code + size) {
5315 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5317 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5318 buf [ptr - code] = saved_byte;
5325 mono_arch_get_vcall_slot (guint8 *code, mgreg_t *regs, int *displacement)
5331 mono_breakpoint_clean_code (NULL, code, 8, buf, sizeof (buf));
5339 * A given byte sequence can match more than case here, so we have to be
5340 * really careful about the ordering of the cases. Longer sequences
5342 * There are two types of calls:
5343 * - direct calls: 0xff address_byte 8/32 bits displacement
5344 * - indirect calls: nop nop nop <call>
5345 * The nops make sure we don't confuse the instruction preceeding an indirect
5346 * call with a direct call.
5348 if ((code [1] != 0xe8) && (code [3] == 0xff) && ((code [4] & 0x18) == 0x10) && ((code [4] >> 6) == 1)) {
5349 reg = code [4] & 0x07;
5350 disp = (signed char)code [5];
5351 } else if ((code [0] == 0xff) && ((code [1] & 0x18) == 0x10) && ((code [1] >> 6) == 2)) {
5352 reg = code [1] & 0x07;
5353 disp = *((gint32*)(code + 2));
5354 } else if ((code [1] == 0xe8)) {
5356 } else if ((code [4] == 0xff) && (((code [5] >> 6) & 0x3) == 0) && (((code [5] >> 3) & 0x7) == 2)) {
5358 * This is a interface call
5359 * 8b 40 30 mov 0x30(%eax),%eax
5360 * ff 10 call *(%eax)
5363 reg = code [5] & 0x07;
5368 *displacement = disp;
5369 return (gpointer)regs [reg];
5373 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig,
5374 mgreg_t *regs, guint8 *code)
5376 guint32 esp = regs [X86_ESP];
5377 CallInfo *cinfo = NULL;
5382 * Avoid expensive calls to get_generic_context_from_code () + get_call_info
5385 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5387 gsctx = mono_get_generic_context_from_code (code);
5388 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5390 offset = cinfo->args [0].offset;
5396 * The stack looks like:
5399 * <possible vtype return address>
5401 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
5403 res = (((MonoObject**)esp) [5 + (offset / 4)]);
5409 #define MAX_ARCH_DELEGATE_PARAMS 10
5412 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5414 guint8 *code, *start;
5416 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5419 /* FIXME: Support more cases */
5420 if (MONO_TYPE_ISSTRUCT (sig->ret))
5424 * The stack contains:
5430 static guint8* cached = NULL;
5434 start = code = mono_global_codeman_reserve (64);
5436 /* Replace the this argument with the target */
5437 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5438 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
5439 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5440 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5442 g_assert ((code - start) < 64);
5444 mono_debug_add_delegate_trampoline (start, code - start);
5446 mono_memory_barrier ();
5450 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5452 /* 8 for mov_reg and jump, plus 8 for each parameter */
5453 int code_reserve = 8 + (sig->param_count * 8);
5455 for (i = 0; i < sig->param_count; ++i)
5456 if (!mono_is_regsize_var (sig->params [i]))
5459 code = cache [sig->param_count];
5464 * The stack contains:
5465 * <args in reverse order>
5470 * <args in reverse order>
5473 * without unbalancing the stack.
5474 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
5475 * and leaving original spot of first arg as placeholder in stack so
5476 * when callee pops stack everything works.
5479 start = code = mono_global_codeman_reserve (code_reserve);
5481 /* store delegate for access to method_ptr */
5482 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
5485 for (i = 0; i < sig->param_count; ++i) {
5486 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
5487 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
5490 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5492 g_assert ((code - start) < code_reserve);
5494 mono_debug_add_delegate_trampoline (start, code - start);
5496 mono_memory_barrier ();
5498 cache [sig->param_count] = start;
5505 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5508 case X86_EAX: return (gpointer)ctx->eax;
5509 case X86_EBX: return (gpointer)ctx->ebx;
5510 case X86_ECX: return (gpointer)ctx->ecx;
5511 case X86_EDX: return (gpointer)ctx->edx;
5512 case X86_ESP: return (gpointer)ctx->esp;
5513 case X86_EBP: return (gpointer)ctx->ebp;
5514 case X86_ESI: return (gpointer)ctx->esi;
5515 case X86_EDI: return (gpointer)ctx->edi;
5516 default: g_assert_not_reached ();
5520 #ifdef MONO_ARCH_SIMD_INTRINSICS
5523 get_float_to_x_spill_area (MonoCompile *cfg)
5525 if (!cfg->fconv_to_r8_x_var) {
5526 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
5527 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
5529 return cfg->fconv_to_r8_x_var;
5533 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
5536 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
5539 int dreg, src_opcode;
5541 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
5544 switch (src_opcode = ins->opcode) {
5545 case OP_FCONV_TO_I1:
5546 case OP_FCONV_TO_U1:
5547 case OP_FCONV_TO_I2:
5548 case OP_FCONV_TO_U2:
5549 case OP_FCONV_TO_I4:
5556 /* dreg is the IREG and sreg1 is the FREG */
5557 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
5558 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
5559 fconv->sreg1 = ins->sreg1;
5560 fconv->dreg = mono_alloc_ireg (cfg);
5561 fconv->type = STACK_VTYPE;
5562 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
5564 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
5568 ins->opcode = OP_XCONV_R8_TO_I4;
5570 ins->klass = mono_defaults.int32_class;
5571 ins->sreg1 = fconv->dreg;
5573 ins->type = STACK_I4;
5574 ins->backend.source_opcode = src_opcode;
5577 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
5580 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
5585 if (long_ins->opcode == OP_LNEG) {
5587 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
5588 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
5589 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
5594 #ifdef MONO_ARCH_SIMD_INTRINSICS
5596 if (!(cfg->opt & MONO_OPT_SIMD))
5599 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
5600 switch (long_ins->opcode) {
5602 vreg = long_ins->sreg1;
5604 if (long_ins->inst_c0) {
5605 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
5606 ins->klass = long_ins->klass;
5607 ins->sreg1 = long_ins->sreg1;
5609 ins->type = STACK_VTYPE;
5610 ins->dreg = vreg = alloc_ireg (cfg);
5611 MONO_ADD_INS (cfg->cbb, ins);
5614 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
5615 ins->klass = mono_defaults.int32_class;
5617 ins->type = STACK_I4;
5618 ins->dreg = long_ins->dreg + 1;
5619 MONO_ADD_INS (cfg->cbb, ins);
5621 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
5622 ins->klass = long_ins->klass;
5623 ins->sreg1 = long_ins->sreg1;
5624 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
5625 ins->type = STACK_VTYPE;
5626 ins->dreg = vreg = alloc_ireg (cfg);
5627 MONO_ADD_INS (cfg->cbb, ins);
5629 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
5630 ins->klass = mono_defaults.int32_class;
5632 ins->type = STACK_I4;
5633 ins->dreg = long_ins->dreg + 2;
5634 MONO_ADD_INS (cfg->cbb, ins);
5636 long_ins->opcode = OP_NOP;
5638 case OP_INSERTX_I8_SLOW:
5639 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
5640 ins->dreg = long_ins->dreg;
5641 ins->sreg1 = long_ins->dreg;
5642 ins->sreg2 = long_ins->sreg2 + 1;
5643 ins->inst_c0 = long_ins->inst_c0 * 2;
5644 MONO_ADD_INS (cfg->cbb, ins);
5646 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
5647 ins->dreg = long_ins->dreg;
5648 ins->sreg1 = long_ins->dreg;
5649 ins->sreg2 = long_ins->sreg2 + 2;
5650 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
5651 MONO_ADD_INS (cfg->cbb, ins);
5653 long_ins->opcode = OP_NOP;
5656 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
5657 ins->dreg = long_ins->dreg;
5658 ins->sreg1 = long_ins->sreg1 + 1;
5659 ins->klass = long_ins->klass;
5660 ins->type = STACK_VTYPE;
5661 MONO_ADD_INS (cfg->cbb, ins);
5663 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
5664 ins->dreg = long_ins->dreg;
5665 ins->sreg1 = long_ins->dreg;
5666 ins->sreg2 = long_ins->sreg1 + 2;
5668 ins->klass = long_ins->klass;
5669 ins->type = STACK_VTYPE;
5670 MONO_ADD_INS (cfg->cbb, ins);
5672 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
5673 ins->dreg = long_ins->dreg;
5674 ins->sreg1 = long_ins->dreg;;
5675 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
5676 ins->klass = long_ins->klass;
5677 ins->type = STACK_VTYPE;
5678 MONO_ADD_INS (cfg->cbb, ins);
5680 long_ins->opcode = OP_NOP;
5683 #endif /* MONO_ARCH_SIMD_INTRINSICS */