2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
12 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
21 #include <mono/metadata/abi-details.h>
22 #include <mono/metadata/appdomain.h>
23 #include <mono/metadata/debug-helpers.h>
24 #include <mono/metadata/threads.h>
25 #include <mono/metadata/profiler-private.h>
26 #include <mono/metadata/mono-debug.h>
27 #include <mono/metadata/gc-internals.h>
28 #include <mono/utils/mono-math.h>
29 #include <mono/utils/mono-counters.h>
30 #include <mono/utils/mono-mmap.h>
31 #include <mono/utils/mono-memory-model.h>
32 #include <mono/utils/mono-hwcap.h>
33 #include <mono/utils/mono-threads.h>
43 static gboolean optimize_for_xen = TRUE;
45 #define optimize_for_xen 0
49 /* The single step trampoline */
50 static gpointer ss_trampoline;
52 /* The breakpoint trampoline */
53 static gpointer bp_trampoline;
55 /* This mutex protects architecture specific caches */
56 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
57 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
58 static mono_mutex_t mini_arch_mutex;
60 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
65 /* Under windows, the default pinvoke calling convention is stdcall */
66 #define CALLCONV_IS_STDCALL(sig) ((sig)->pinvoke && ((sig)->call_convention == MONO_CALL_STDCALL || (sig)->call_convention == MONO_CALL_DEFAULT || (sig)->call_convention == MONO_CALL_THISCALL))
68 #define CALLCONV_IS_STDCALL(sig) ((sig)->pinvoke && ((sig)->call_convention == MONO_CALL_STDCALL || (sig)->call_convention == MONO_CALL_THISCALL))
71 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
73 #define OP_SEQ_POINT_BP_OFFSET 7
76 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
79 mono_arch_regname (int reg)
82 case X86_EAX: return "%eax";
83 case X86_EBX: return "%ebx";
84 case X86_ECX: return "%ecx";
85 case X86_EDX: return "%edx";
86 case X86_ESP: return "%esp";
87 case X86_EBP: return "%ebp";
88 case X86_EDI: return "%edi";
89 case X86_ESI: return "%esi";
95 mono_arch_fregname (int reg)
120 mono_arch_xregname (int reg)
145 mono_x86_patch (unsigned char* code, gpointer target)
147 x86_patch (code, (unsigned char*)target);
150 #define FLOAT_PARAM_REGS 0
152 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
154 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
159 switch (sig->call_convention) {
160 case MONO_CALL_THISCALL:
161 return thiscall_param_regs;
167 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
168 #define SMALL_STRUCTS_IN_REGS
169 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
173 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
175 ainfo->offset = *stack_size;
177 if (!param_regs || param_regs [*gr] == X86_NREG) {
178 ainfo->storage = ArgOnStack;
180 (*stack_size) += sizeof (gpointer);
183 ainfo->storage = ArgInIReg;
184 ainfo->reg = param_regs [*gr];
190 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
192 ainfo->offset = *stack_size;
194 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
196 ainfo->storage = ArgOnStack;
197 (*stack_size) += sizeof (gpointer) * 2;
202 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
204 ainfo->offset = *stack_size;
206 if (*gr >= FLOAT_PARAM_REGS) {
207 ainfo->storage = ArgOnStack;
208 (*stack_size) += is_double ? 8 : 4;
209 ainfo->nslots = is_double ? 2 : 1;
212 /* A double register */
214 ainfo->storage = ArgInDoubleSSEReg;
216 ainfo->storage = ArgInFloatSSEReg;
224 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
226 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
231 klass = mono_class_from_mono_type (type);
232 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
234 #if defined(TARGET_WIN32)
236 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
237 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
238 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
239 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
240 * it must be represented in call and cannot be dropped.
242 if (size == 0 && MONO_TYPE_ISSTRUCT (type) && sig->pinvoke) {
243 /* Empty structs (1 byte size) needs to be represented in a stack slot */
244 ainfo->pass_empty_struct = TRUE;
249 #ifdef SMALL_STRUCTS_IN_REGS
250 if (sig->pinvoke && is_return) {
251 MonoMarshalType *info;
253 info = mono_marshal_load_type_info (klass);
256 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
258 /* Ignore empty struct return value, if used. */
259 if (info->num_fields == 0 && ainfo->pass_empty_struct) {
260 ainfo->storage = ArgValuetypeInReg;
265 * Windows x86 ABI for returning structs of size 4 or 8 bytes (regardless of type) dictates that
266 * values are passed in EDX:EAX register pairs, https://msdn.microsoft.com/en-us/library/984x0h58.aspx.
267 * This is different compared to for example float or double return types (not in struct) that will be returned
268 * in ST(0), https://msdn.microsoft.com/en-us/library/ha59cbfz.aspx.
270 * Apples OSX x86 ABI for returning structs of size 4 or 8 bytes uses a slightly different approach.
271 * If a struct includes only one scalar value, it will be handled with the same rules as scalar values.
272 * This means that structs with one float or double will be returned in ST(0). For more details,
273 * https://developer.apple.com/library/mac/documentation/DeveloperTools/Conceptual/LowLevelABI/130-IA-32_Function_Calling_Conventions/IA32.html.
275 #if !defined(TARGET_WIN32)
277 /* Special case structs with only a float member */
278 if (info->num_fields == 1) {
279 int ftype = mini_get_underlying_type (info->fields [0].field->type)->type;
280 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
281 ainfo->storage = ArgValuetypeInReg;
282 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
285 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
286 ainfo->storage = ArgValuetypeInReg;
287 ainfo->pair_storage [0] = ArgOnFloatFpStack;
293 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
294 ainfo->storage = ArgValuetypeInReg;
295 ainfo->pair_storage [0] = ArgInIReg;
296 ainfo->pair_regs [0] = return_regs [0];
297 if (info->native_size > 4) {
298 ainfo->pair_storage [1] = ArgInIReg;
299 ainfo->pair_regs [1] = return_regs [1];
306 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
307 g_assert (size <= 4);
308 ainfo->storage = ArgValuetypeInReg;
309 ainfo->reg = param_regs [*gr];
314 ainfo->offset = *stack_size;
315 ainfo->storage = ArgOnStack;
316 *stack_size += ALIGN_TO (size, sizeof (gpointer));
317 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
323 * Obtain information about a call according to the calling convention.
324 * For x86 ELF, see the "System V Application Binary Interface Intel386
325 * Architecture Processor Supplment, Fourth Edition" document for more
327 * For x86 win32, see https://msdn.microsoft.com/en-us/library/984x0h58.aspx.
330 get_call_info_internal (CallInfo *cinfo, MonoMethodSignature *sig)
332 guint32 i, gr, fr, pstart;
333 const guint32 *param_regs;
335 int n = sig->hasthis + sig->param_count;
336 guint32 stack_size = 0;
337 gboolean is_pinvoke = sig->pinvoke;
343 param_regs = callconv_param_regs(sig);
347 ret_type = mini_get_underlying_type (sig->ret);
348 switch (ret_type->type) {
358 case MONO_TYPE_FNPTR:
359 case MONO_TYPE_CLASS:
360 case MONO_TYPE_OBJECT:
361 case MONO_TYPE_SZARRAY:
362 case MONO_TYPE_ARRAY:
363 case MONO_TYPE_STRING:
364 cinfo->ret.storage = ArgInIReg;
365 cinfo->ret.reg = X86_EAX;
369 cinfo->ret.storage = ArgInIReg;
370 cinfo->ret.reg = X86_EAX;
371 cinfo->ret.is_pair = TRUE;
374 cinfo->ret.storage = ArgOnFloatFpStack;
377 cinfo->ret.storage = ArgOnDoubleFpStack;
379 case MONO_TYPE_GENERICINST:
380 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
381 cinfo->ret.storage = ArgInIReg;
382 cinfo->ret.reg = X86_EAX;
385 if (mini_is_gsharedvt_type (ret_type)) {
386 cinfo->ret.storage = ArgOnStack;
387 cinfo->vtype_retaddr = TRUE;
391 case MONO_TYPE_VALUETYPE:
392 case MONO_TYPE_TYPEDBYREF: {
393 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
395 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
396 if (cinfo->ret.storage == ArgOnStack) {
397 cinfo->vtype_retaddr = TRUE;
398 /* The caller passes the address where the value is stored */
404 g_assert (mini_is_gsharedvt_type (ret_type));
405 cinfo->ret.storage = ArgOnStack;
406 cinfo->vtype_retaddr = TRUE;
409 cinfo->ret.storage = ArgNone;
412 g_error ("Can't handle as return value 0x%x", ret_type->type);
418 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
419 * the first argument, allowing 'this' to be always passed in the first arg reg.
420 * Also do this if the first argument is a reference type, since virtual calls
421 * are sometimes made using calli without sig->hasthis set, like in the delegate
424 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
426 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
428 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
431 cinfo->vret_arg_offset = stack_size;
432 add_general (&gr, NULL, &stack_size, &cinfo->ret);
433 cinfo->vret_arg_index = 1;
437 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
439 if (cinfo->vtype_retaddr)
440 add_general (&gr, NULL, &stack_size, &cinfo->ret);
443 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
444 fr = FLOAT_PARAM_REGS;
446 /* Emit the signature cookie just before the implicit arguments */
447 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
450 for (i = pstart; i < sig->param_count; ++i) {
451 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
454 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
455 /* We allways pass the sig cookie on the stack for simplicity */
457 * Prevent implicit arguments + the sig cookie from being passed
460 fr = FLOAT_PARAM_REGS;
462 /* Emit the signature cookie just before the implicit arguments */
463 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
466 if (sig->params [i]->byref) {
467 add_general (&gr, param_regs, &stack_size, ainfo);
470 ptype = mini_get_underlying_type (sig->params [i]);
471 switch (ptype->type) {
474 add_general (&gr, param_regs, &stack_size, ainfo);
478 add_general (&gr, param_regs, &stack_size, ainfo);
482 add_general (&gr, param_regs, &stack_size, ainfo);
487 case MONO_TYPE_FNPTR:
488 case MONO_TYPE_CLASS:
489 case MONO_TYPE_OBJECT:
490 case MONO_TYPE_STRING:
491 case MONO_TYPE_SZARRAY:
492 case MONO_TYPE_ARRAY:
493 add_general (&gr, param_regs, &stack_size, ainfo);
495 case MONO_TYPE_GENERICINST:
496 if (!mono_type_generic_inst_is_valuetype (ptype)) {
497 add_general (&gr, param_regs, &stack_size, ainfo);
500 if (mini_is_gsharedvt_type (ptype)) {
501 /* gsharedvt arguments are passed by ref */
502 add_general (&gr, param_regs, &stack_size, ainfo);
503 g_assert (ainfo->storage == ArgOnStack);
504 ainfo->storage = ArgGSharedVt;
508 case MONO_TYPE_VALUETYPE:
509 case MONO_TYPE_TYPEDBYREF:
510 add_valuetype (sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
514 add_general_pair (&gr, param_regs, &stack_size, ainfo);
517 add_float (&fr, &stack_size, ainfo, FALSE);
520 add_float (&fr, &stack_size, ainfo, TRUE);
524 /* gsharedvt arguments are passed by ref */
525 g_assert (mini_is_gsharedvt_type (ptype));
526 add_general (&gr, param_regs, &stack_size, ainfo);
527 g_assert (ainfo->storage == ArgOnStack);
528 ainfo->storage = ArgGSharedVt;
531 g_error ("unexpected type 0x%x", ptype->type);
532 g_assert_not_reached ();
536 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
537 fr = FLOAT_PARAM_REGS;
539 /* Emit the signature cookie just before the implicit arguments */
540 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
543 if (cinfo->vtype_retaddr) {
544 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
545 cinfo->callee_stack_pop = 4;
546 } else if (CALLCONV_IS_STDCALL (sig)) {
547 /* Have to compensate for the stack space popped by the native callee */
548 cinfo->callee_stack_pop = stack_size;
551 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
552 cinfo->need_stack_align = TRUE;
553 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
554 stack_size += cinfo->stack_align_amount;
557 cinfo->stack_usage = stack_size;
558 cinfo->reg_usage = gr;
559 cinfo->freg_usage = fr;
564 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
566 int n = sig->hasthis + sig->param_count;
570 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
572 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
574 return get_call_info_internal (cinfo, sig);
578 * mono_arch_get_argument_info:
579 * @csig: a method signature
580 * @param_count: the number of parameters to consider
581 * @arg_info: an array to store the result infos
583 * Gathers information on parameters such as size, alignment and
584 * padding. arg_info should be large enought to hold param_count + 1 entries.
586 * Returns the size of the argument area on the stack.
587 * This should be signal safe, since it is called from
588 * mono_arch_unwind_frame ().
589 * FIXME: The metadata calls might not be signal safe.
592 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
594 int len, k, args_size = 0;
600 /* Avoid g_malloc as it is not signal safe */
601 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
602 cinfo = (CallInfo*)g_newa (guint8*, len);
603 memset (cinfo, 0, len);
605 cinfo = get_call_info_internal (cinfo, csig);
607 arg_info [0].offset = offset;
609 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
610 args_size += sizeof (gpointer);
615 args_size += sizeof (gpointer);
619 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
620 /* Emitted after this */
621 args_size += sizeof (gpointer);
625 arg_info [0].size = args_size;
627 for (k = 0; k < param_count; k++) {
628 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
630 /* ignore alignment for now */
633 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
634 arg_info [k].pad = pad;
636 arg_info [k + 1].pad = 0;
637 arg_info [k + 1].size = size;
639 arg_info [k + 1].offset = offset;
642 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
643 /* Emitted after the first arg */
644 args_size += sizeof (gpointer);
649 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
650 align = MONO_ARCH_FRAME_ALIGNMENT;
653 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
654 arg_info [k].pad = pad;
660 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
662 MonoType *callee_ret;
666 if (cfg->compile_aot && !cfg->full_aot)
667 /* OP_TAILCALL doesn't work with AOT */
670 c1 = get_call_info (NULL, caller_sig);
671 c2 = get_call_info (NULL, callee_sig);
673 * Tail calls with more callee stack usage than the caller cannot be supported, since
674 * the extra stack space would be left on the stack after the tail call.
676 res = c1->stack_usage >= c2->stack_usage;
677 callee_ret = mini_get_underlying_type (callee_sig->ret);
678 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
679 /* An address on the callee's stack is passed as the first argument */
689 * Initialize the cpu to execute managed code.
692 mono_arch_cpu_init (void)
694 /* spec compliance requires running with double precision */
698 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
699 fpcw &= ~X86_FPCW_PRECC_MASK;
700 fpcw |= X86_FPCW_PREC_DOUBLE;
701 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
702 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
704 _control87 (_PC_53, MCW_PC);
709 * Initialize architecture specific code.
712 mono_arch_init (void)
714 mono_os_mutex_init_recursive (&mini_arch_mutex);
717 bp_trampoline = mini_get_breakpoint_trampoline ();
719 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
720 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
721 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
722 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
727 * Cleanup architecture specific code.
730 mono_arch_cleanup (void)
732 mono_os_mutex_destroy (&mini_arch_mutex);
736 * This function returns the optimizations supported on this cpu.
739 mono_arch_cpu_optimizations (guint32 *exclude_mask)
745 if (mono_hwcap_x86_has_cmov) {
746 opts |= MONO_OPT_CMOV;
748 if (mono_hwcap_x86_has_fcmov)
749 opts |= MONO_OPT_FCMOV;
751 *exclude_mask |= MONO_OPT_FCMOV;
753 *exclude_mask |= MONO_OPT_CMOV;
756 if (mono_hwcap_x86_has_sse2)
757 opts |= MONO_OPT_SSE2;
759 *exclude_mask |= MONO_OPT_SSE2;
761 #ifdef MONO_ARCH_SIMD_INTRINSICS
762 /*SIMD intrinsics require at least SSE2.*/
763 if (!mono_hwcap_x86_has_sse2)
764 *exclude_mask |= MONO_OPT_SIMD;
771 * This function test for all SSE functions supported.
773 * Returns a bitmask corresponding to all supported versions.
777 mono_arch_cpu_enumerate_simd_versions (void)
779 guint32 sse_opts = 0;
781 if (mono_hwcap_x86_has_sse1)
782 sse_opts |= SIMD_VERSION_SSE1;
784 if (mono_hwcap_x86_has_sse2)
785 sse_opts |= SIMD_VERSION_SSE2;
787 if (mono_hwcap_x86_has_sse3)
788 sse_opts |= SIMD_VERSION_SSE3;
790 if (mono_hwcap_x86_has_ssse3)
791 sse_opts |= SIMD_VERSION_SSSE3;
793 if (mono_hwcap_x86_has_sse41)
794 sse_opts |= SIMD_VERSION_SSE41;
796 if (mono_hwcap_x86_has_sse42)
797 sse_opts |= SIMD_VERSION_SSE42;
799 if (mono_hwcap_x86_has_sse4a)
800 sse_opts |= SIMD_VERSION_SSE4a;
806 * Determine whenever the trap whose info is in SIGINFO is caused by
810 mono_arch_is_int_overflow (void *sigctx, void *info)
815 mono_sigctx_to_monoctx (sigctx, &ctx);
817 ip = (guint8*)ctx.eip;
819 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
823 switch (x86_modrm_rm (ip [1])) {
843 g_assert_not_reached ();
855 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
860 for (i = 0; i < cfg->num_varinfo; i++) {
861 MonoInst *ins = cfg->varinfo [i];
862 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
865 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
868 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
869 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
872 /* we dont allocate I1 to registers because there is no simply way to sign extend
873 * 8bit quantities in caller saved registers on x86 */
874 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
875 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
876 g_assert (i == vmv->idx);
877 vars = g_list_prepend (vars, vmv);
881 vars = mono_varlist_sort (cfg, vars, 0);
887 mono_arch_get_global_int_regs (MonoCompile *cfg)
891 /* we can use 3 registers for global allocation */
892 regs = g_list_prepend (regs, (gpointer)X86_EBX);
893 regs = g_list_prepend (regs, (gpointer)X86_ESI);
894 regs = g_list_prepend (regs, (gpointer)X86_EDI);
900 * mono_arch_regalloc_cost:
902 * Return the cost, in number of memory references, of the action of
903 * allocating the variable VMV into a register during global register
907 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
909 MonoInst *ins = cfg->varinfo [vmv->idx];
911 if (cfg->method->save_lmf)
912 /* The register is already saved */
913 return (ins->opcode == OP_ARG) ? 1 : 0;
915 /* push+pop+possible load if it is an argument */
916 return (ins->opcode == OP_ARG) ? 3 : 2;
920 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
922 static int inited = FALSE;
923 static int count = 0;
925 if (cfg->arch.need_stack_frame_inited) {
926 g_assert (cfg->arch.need_stack_frame == flag);
930 cfg->arch.need_stack_frame = flag;
931 cfg->arch.need_stack_frame_inited = TRUE;
937 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
942 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
946 needs_stack_frame (MonoCompile *cfg)
948 MonoMethodSignature *sig;
949 MonoMethodHeader *header;
950 gboolean result = FALSE;
952 #if defined(__APPLE__)
953 /*OSX requires stack frame code to have the correct alignment. */
957 if (cfg->arch.need_stack_frame_inited)
958 return cfg->arch.need_stack_frame;
960 header = cfg->header;
961 sig = mono_method_signature (cfg->method);
963 if (cfg->disable_omit_fp)
965 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
967 else if (cfg->method->save_lmf)
969 else if (cfg->stack_offset)
971 else if (cfg->param_area)
973 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
975 else if (header->num_clauses)
977 else if (sig->param_count + sig->hasthis)
979 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
981 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
982 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
985 set_needs_stack_frame (cfg, result);
987 return cfg->arch.need_stack_frame;
991 * Set var information according to the calling convention. X86 version.
992 * The locals var stuff should most likely be split in another method.
995 mono_arch_allocate_vars (MonoCompile *cfg)
997 MonoMethodSignature *sig;
998 MonoMethodHeader *header;
1000 guint32 locals_stack_size, locals_stack_align;
1005 header = cfg->header;
1006 sig = mono_method_signature (cfg->method);
1008 if (!cfg->arch.cinfo)
1009 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1010 cinfo = (CallInfo *)cfg->arch.cinfo;
1012 cfg->frame_reg = X86_EBP;
1015 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1016 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1017 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1020 /* Reserve space to save LMF and caller saved registers */
1022 if (cfg->method->save_lmf) {
1023 /* The LMF var is allocated normally */
1025 if (cfg->used_int_regs & (1 << X86_EBX)) {
1029 if (cfg->used_int_regs & (1 << X86_EDI)) {
1033 if (cfg->used_int_regs & (1 << X86_ESI)) {
1038 switch (cinfo->ret.storage) {
1039 case ArgValuetypeInReg:
1040 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1042 cfg->ret->opcode = OP_REGOFFSET;
1043 cfg->ret->inst_basereg = X86_EBP;
1044 cfg->ret->inst_offset = - offset;
1050 /* Allocate locals */
1051 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1052 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1053 char *mname = mono_method_full_name (cfg->method, TRUE);
1054 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1058 if (locals_stack_align) {
1059 int prev_offset = offset;
1061 offset += (locals_stack_align - 1);
1062 offset &= ~(locals_stack_align - 1);
1064 while (prev_offset < offset) {
1066 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1069 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1070 cfg->locals_max_stack_offset = - offset;
1072 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1073 * have locals larger than 8 bytes we need to make sure that
1074 * they have the appropriate offset.
1076 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1077 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1078 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1079 if (offsets [i] != -1) {
1080 MonoInst *inst = cfg->varinfo [i];
1081 inst->opcode = OP_REGOFFSET;
1082 inst->inst_basereg = X86_EBP;
1083 inst->inst_offset = - (offset + offsets [i]);
1084 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1087 offset += locals_stack_size;
1091 * Allocate arguments+return value
1094 switch (cinfo->ret.storage) {
1096 if (cfg->vret_addr) {
1098 * In the new IR, the cfg->vret_addr variable represents the
1099 * vtype return value.
1101 cfg->vret_addr->opcode = OP_REGOFFSET;
1102 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1103 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1104 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1105 printf ("vret_addr =");
1106 mono_print_ins (cfg->vret_addr);
1109 cfg->ret->opcode = OP_REGOFFSET;
1110 cfg->ret->inst_basereg = X86_EBP;
1111 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1114 case ArgValuetypeInReg:
1117 cfg->ret->opcode = OP_REGVAR;
1118 cfg->ret->inst_c0 = cinfo->ret.reg;
1119 cfg->ret->dreg = cinfo->ret.reg;
1122 case ArgOnFloatFpStack:
1123 case ArgOnDoubleFpStack:
1126 g_assert_not_reached ();
1129 if (sig->call_convention == MONO_CALL_VARARG) {
1130 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1131 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1134 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1135 ArgInfo *ainfo = &cinfo->args [i];
1136 inst = cfg->args [i];
1137 if (inst->opcode != OP_REGVAR) {
1138 inst->opcode = OP_REGOFFSET;
1139 inst->inst_basereg = X86_EBP;
1140 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1144 cfg->stack_offset = offset;
1148 mono_arch_create_vars (MonoCompile *cfg)
1151 MonoMethodSignature *sig;
1154 sig = mono_method_signature (cfg->method);
1156 if (!cfg->arch.cinfo)
1157 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1158 cinfo = (CallInfo *)cfg->arch.cinfo;
1160 sig_ret = mini_get_underlying_type (sig->ret);
1162 if (cinfo->ret.storage == ArgValuetypeInReg)
1163 cfg->ret_var_is_local = TRUE;
1164 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (sig_ret))) {
1165 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1168 if (cfg->gen_sdb_seq_points) {
1171 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1172 ins->flags |= MONO_INST_VOLATILE;
1173 cfg->arch.ss_tramp_var = ins;
1175 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1176 ins->flags |= MONO_INST_VOLATILE;
1177 cfg->arch.bp_tramp_var = ins;
1180 if (cfg->method->save_lmf) {
1181 cfg->create_lmf_var = TRUE;
1185 cfg->arch_eh_jit_info = 1;
1189 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1190 * so we try to do it just once when we have multiple fp arguments in a row.
1191 * We don't use this mechanism generally because for int arguments the generated code
1192 * is slightly bigger and new generation cpus optimize away the dependency chains
1193 * created by push instructions on the esp value.
1194 * fp_arg_setup is the first argument in the execution sequence where the esp register
1197 static G_GNUC_UNUSED int
1198 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1203 for (; start_arg < sig->param_count; ++start_arg) {
1204 t = mini_get_underlying_type (sig->params [start_arg]);
1205 if (!t->byref && t->type == MONO_TYPE_R8) {
1206 fp_space += sizeof (double);
1207 *fp_arg_setup = start_arg;
1216 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1218 MonoMethodSignature *tmp_sig;
1222 * mono_ArgIterator_Setup assumes the signature cookie is
1223 * passed first and all the arguments which were before it are
1224 * passed on the stack after the signature. So compensate by
1225 * passing a different signature.
1227 tmp_sig = mono_metadata_signature_dup (call->signature);
1228 tmp_sig->param_count -= call->signature->sentinelpos;
1229 tmp_sig->sentinelpos = 0;
1230 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1232 if (cfg->compile_aot) {
1233 sig_reg = mono_alloc_ireg (cfg);
1234 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1235 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1237 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1243 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1248 LLVMCallInfo *linfo;
1249 MonoType *t, *sig_ret;
1251 n = sig->param_count + sig->hasthis;
1253 cinfo = get_call_info (cfg->mempool, sig);
1256 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1259 * LLVM always uses the native ABI while we use our own ABI, the
1260 * only difference is the handling of vtypes:
1261 * - we only pass/receive them in registers in some cases, and only
1262 * in 1 or 2 integer registers.
1264 if (cinfo->ret.storage == ArgValuetypeInReg) {
1266 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1267 cfg->disable_llvm = TRUE;
1271 cfg->exception_message = g_strdup ("vtype ret in call");
1272 cfg->disable_llvm = TRUE;
1274 linfo->ret.storage = LLVMArgVtypeInReg;
1275 for (j = 0; j < 2; ++j)
1276 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1280 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage == ArgInIReg) {
1281 /* Vtype returned using a hidden argument */
1282 linfo->ret.storage = LLVMArgVtypeRetAddr;
1283 linfo->vret_arg_index = cinfo->vret_arg_index;
1286 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage != ArgInIReg) {
1288 cfg->exception_message = g_strdup ("vtype ret in call");
1289 cfg->disable_llvm = TRUE;
1292 for (i = 0; i < n; ++i) {
1293 ainfo = cinfo->args + i;
1295 if (i >= sig->hasthis)
1296 t = sig->params [i - sig->hasthis];
1298 t = &mono_defaults.int_class->byval_arg;
1300 linfo->args [i].storage = LLVMArgNone;
1302 switch (ainfo->storage) {
1304 linfo->args [i].storage = LLVMArgNormal;
1306 case ArgInDoubleSSEReg:
1307 case ArgInFloatSSEReg:
1308 linfo->args [i].storage = LLVMArgNormal;
1311 if (mini_type_is_vtype (t)) {
1312 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1313 /* LLVM seems to allocate argument space for empty structures too */
1314 linfo->args [i].storage = LLVMArgNone;
1316 linfo->args [i].storage = LLVMArgVtypeByVal;
1318 linfo->args [i].storage = LLVMArgNormal;
1321 case ArgValuetypeInReg:
1323 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1324 cfg->disable_llvm = TRUE;
1328 cfg->exception_message = g_strdup ("vtype arg");
1329 cfg->disable_llvm = TRUE;
1331 linfo->args [i].storage = LLVMArgVtypeInReg;
1332 for (j = 0; j < 2; ++j)
1333 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1337 linfo->args [i].storage = LLVMArgGSharedVt;
1340 cfg->exception_message = g_strdup ("ainfo->storage");
1341 cfg->disable_llvm = TRUE;
1351 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1353 if (cfg->compute_gc_maps) {
1356 /* Needs checking if the feature will be enabled again */
1357 g_assert_not_reached ();
1359 /* On x86, the offsets are from the sp value before the start of the call sequence */
1361 t = &mono_defaults.int_class->byval_arg;
1362 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1367 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1371 MonoMethodSignature *sig;
1374 int sentinelpos = 0, sp_offset = 0;
1376 sig = call->signature;
1377 n = sig->param_count + sig->hasthis;
1378 sig_ret = mini_get_underlying_type (sig->ret);
1380 cinfo = get_call_info (cfg->mempool, sig);
1381 call->call_info = cinfo;
1383 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1384 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1386 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1387 if (cinfo->ret.storage == ArgValuetypeInReg && cinfo->ret.pair_storage[0] != ArgNone ) {
1389 * Tell the JIT to use a more efficient calling convention: call using
1390 * OP_CALL, compute the result location after the call, and save the
1393 call->vret_in_reg = TRUE;
1394 #if defined(__APPLE__)
1395 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1396 call->vret_in_reg_fp = TRUE;
1399 NULLIFY_INS (call->vret_var);
1403 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1405 /* Handle the case where there are no implicit arguments */
1406 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1407 emit_sig_cookie (cfg, call, cinfo);
1408 sp_offset = cinfo->sig_cookie.offset;
1409 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1412 /* Arguments are pushed in the reverse order */
1413 for (i = n - 1; i >= 0; i --) {
1414 ArgInfo *ainfo = cinfo->args + i;
1415 MonoType *orig_type, *t;
1418 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1421 /* Push the vret arg before the first argument */
1422 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1423 vtarg->type = STACK_MP;
1424 vtarg->inst_destbasereg = X86_ESP;
1425 vtarg->sreg1 = call->vret_var->dreg;
1426 vtarg->inst_offset = cinfo->ret.offset;
1427 MONO_ADD_INS (cfg->cbb, vtarg);
1428 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1431 if (i >= sig->hasthis)
1432 t = sig->params [i - sig->hasthis];
1434 t = &mono_defaults.int_class->byval_arg;
1436 t = mini_get_underlying_type (t);
1438 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1440 in = call->args [i];
1441 arg->cil_code = in->cil_code;
1442 arg->sreg1 = in->dreg;
1443 arg->type = in->type;
1445 g_assert (in->dreg != -1);
1447 if (ainfo->storage == ArgGSharedVt) {
1448 arg->opcode = OP_OUTARG_VT;
1449 arg->sreg1 = in->dreg;
1450 arg->klass = in->klass;
1451 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1452 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1454 MONO_ADD_INS (cfg->cbb, arg);
1455 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1459 g_assert (in->klass);
1461 if (t->type == MONO_TYPE_TYPEDBYREF) {
1462 size = sizeof (MonoTypedRef);
1463 align = sizeof (gpointer);
1466 size = mini_type_stack_size_full (&in->klass->byval_arg, &align, sig->pinvoke);
1469 if (size > 0 || ainfo->pass_empty_struct) {
1470 arg->opcode = OP_OUTARG_VT;
1471 arg->sreg1 = in->dreg;
1472 arg->klass = in->klass;
1473 arg->backend.size = size;
1474 arg->inst_p0 = call;
1475 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1476 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1478 MONO_ADD_INS (cfg->cbb, arg);
1479 if (ainfo->storage != ArgValuetypeInReg) {
1480 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1484 switch (ainfo->storage) {
1487 if (t->type == MONO_TYPE_R4) {
1488 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1490 } else if (t->type == MONO_TYPE_R8) {
1491 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1493 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1494 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, MONO_LVREG_MS (in->dreg));
1495 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, MONO_LVREG_LS (in->dreg));
1498 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1502 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1507 arg->opcode = OP_MOVE;
1508 arg->dreg = ainfo->reg;
1509 MONO_ADD_INS (cfg->cbb, arg);
1513 g_assert_not_reached ();
1516 if (cfg->compute_gc_maps) {
1518 /* FIXME: The == STACK_OBJ check might be fragile ? */
1519 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1521 if (call->need_unbox_trampoline)
1522 /* The unbox trampoline transforms this into a managed pointer */
1523 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.int_class->this_arg);
1525 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.object_class->byval_arg);
1527 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1531 for (j = 0; j < argsize; j += 4)
1532 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1537 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1538 /* Emit the signature cookie just before the implicit arguments */
1539 emit_sig_cookie (cfg, call, cinfo);
1540 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1544 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1547 if (cinfo->ret.storage == ArgValuetypeInReg) {
1550 else if (cinfo->ret.storage == ArgInIReg) {
1552 /* The return address is passed in a register */
1553 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1554 vtarg->sreg1 = call->inst.dreg;
1555 vtarg->dreg = mono_alloc_ireg (cfg);
1556 MONO_ADD_INS (cfg->cbb, vtarg);
1558 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1559 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1560 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1561 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1565 call->stack_usage = cinfo->stack_usage;
1566 call->stack_align_amount = cinfo->stack_align_amount;
1570 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1572 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1573 ArgInfo *ainfo = ins->inst_p1;
1574 int size = ins->backend.size;
1576 if (ainfo->storage == ArgValuetypeInReg) {
1577 int dreg = mono_alloc_ireg (cfg);
1580 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1583 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1586 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1590 g_assert_not_reached ();
1592 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1595 if (cfg->gsharedvt && mini_is_gsharedvt_klass (ins->klass)) {
1597 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1598 } else if (size <= 4) {
1599 int dreg = mono_alloc_ireg (cfg);
1600 if (ainfo->pass_empty_struct) {
1601 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
1602 MONO_EMIT_NEW_ICONST (cfg, dreg, 0);
1604 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1606 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1607 } else if (size <= 20) {
1608 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1610 // FIXME: Code growth
1611 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1617 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1619 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
1622 if (ret->type == MONO_TYPE_R4) {
1623 if (COMPILE_LLVM (cfg))
1624 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1627 } else if (ret->type == MONO_TYPE_R8) {
1628 if (COMPILE_LLVM (cfg))
1629 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1632 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1633 if (COMPILE_LLVM (cfg))
1634 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1636 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, MONO_LVREG_LS (val->dreg));
1637 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, MONO_LVREG_MS (val->dreg));
1643 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1647 * Allow tracing to work with this interface (with an optional argument)
1650 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1654 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1655 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1657 /* if some args are passed in registers, we need to save them here */
1658 x86_push_reg (code, X86_EBP);
1660 if (cfg->compile_aot) {
1661 x86_push_imm (code, cfg->method);
1662 x86_mov_reg_imm (code, X86_EAX, func);
1663 x86_call_reg (code, X86_EAX);
1665 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1666 x86_push_imm (code, cfg->method);
1667 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1668 x86_call_code (code, 0);
1670 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1684 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1687 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1688 MonoMethod *method = cfg->method;
1689 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
1691 switch (ret_type->type) {
1692 case MONO_TYPE_VOID:
1693 /* special case string .ctor icall */
1694 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1695 save_mode = SAVE_EAX;
1696 stack_usage = enable_arguments ? 8 : 4;
1698 save_mode = SAVE_NONE;
1702 save_mode = SAVE_EAX_EDX;
1703 stack_usage = enable_arguments ? 16 : 8;
1707 save_mode = SAVE_FP;
1708 stack_usage = enable_arguments ? 16 : 8;
1710 case MONO_TYPE_GENERICINST:
1711 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1712 save_mode = SAVE_EAX;
1713 stack_usage = enable_arguments ? 8 : 4;
1717 case MONO_TYPE_VALUETYPE:
1718 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1719 save_mode = SAVE_STRUCT;
1720 stack_usage = enable_arguments ? 4 : 0;
1723 save_mode = SAVE_EAX;
1724 stack_usage = enable_arguments ? 8 : 4;
1728 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1730 switch (save_mode) {
1732 x86_push_reg (code, X86_EDX);
1733 x86_push_reg (code, X86_EAX);
1734 if (enable_arguments) {
1735 x86_push_reg (code, X86_EDX);
1736 x86_push_reg (code, X86_EAX);
1741 x86_push_reg (code, X86_EAX);
1742 if (enable_arguments) {
1743 x86_push_reg (code, X86_EAX);
1748 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1749 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1750 if (enable_arguments) {
1751 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1752 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1757 if (enable_arguments) {
1758 x86_push_membase (code, X86_EBP, 8);
1767 if (cfg->compile_aot) {
1768 x86_push_imm (code, method);
1769 x86_mov_reg_imm (code, X86_EAX, func);
1770 x86_call_reg (code, X86_EAX);
1772 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1773 x86_push_imm (code, method);
1774 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1775 x86_call_code (code, 0);
1778 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1780 switch (save_mode) {
1782 x86_pop_reg (code, X86_EAX);
1783 x86_pop_reg (code, X86_EDX);
1786 x86_pop_reg (code, X86_EAX);
1789 x86_fld_membase (code, X86_ESP, 0, TRUE);
1790 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1797 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1802 #define EMIT_COND_BRANCH(ins,cond,sign) \
1803 if (ins->inst_true_bb->native_offset) { \
1804 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1806 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1807 if ((cfg->opt & MONO_OPT_BRANCH) && \
1808 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1809 x86_branch8 (code, cond, 0, sign); \
1811 x86_branch32 (code, cond, 0, sign); \
1815 * Emit an exception if condition is fail and
1816 * if possible do a directly branch to target
1818 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1820 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1821 if (tins == NULL) { \
1822 mono_add_patch_info (cfg, code - cfg->native_code, \
1823 MONO_PATCH_INFO_EXC, exc_name); \
1824 x86_branch32 (code, cond, 0, signed); \
1826 EMIT_COND_BRANCH (tins, cond, signed); \
1830 #define EMIT_FPCOMPARE(code) do { \
1831 x86_fcompp (code); \
1832 x86_fnstsw (code); \
1837 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1839 gboolean needs_paddings = TRUE;
1841 MonoJumpInfo *jinfo = NULL;
1843 if (cfg->abs_patches) {
1844 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1845 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1846 needs_paddings = FALSE;
1849 if (cfg->compile_aot)
1850 needs_paddings = FALSE;
1851 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1852 This is required for code patching to be safe on SMP machines.
1854 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1855 if (needs_paddings && pad_size)
1856 x86_padding (code, 4 - pad_size);
1858 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1859 x86_call_code (code, 0);
1864 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1867 * mono_peephole_pass_1:
1869 * Perform peephole opts which should/can be performed before local regalloc
1872 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1876 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1877 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1879 switch (ins->opcode) {
1882 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1884 * X86_LEA is like ADD, but doesn't have the
1885 * sreg1==dreg restriction.
1887 ins->opcode = OP_X86_LEA_MEMBASE;
1888 ins->inst_basereg = ins->sreg1;
1889 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1890 ins->opcode = OP_X86_INC_REG;
1894 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1895 ins->opcode = OP_X86_LEA_MEMBASE;
1896 ins->inst_basereg = ins->sreg1;
1897 ins->inst_imm = -ins->inst_imm;
1898 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1899 ins->opcode = OP_X86_DEC_REG;
1901 case OP_COMPARE_IMM:
1902 case OP_ICOMPARE_IMM:
1903 /* OP_COMPARE_IMM (reg, 0)
1905 * OP_X86_TEST_NULL (reg)
1908 ins->opcode = OP_X86_TEST_NULL;
1910 case OP_X86_COMPARE_MEMBASE_IMM:
1912 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1913 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1915 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1916 * OP_COMPARE_IMM reg, imm
1918 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1920 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1921 ins->inst_basereg == last_ins->inst_destbasereg &&
1922 ins->inst_offset == last_ins->inst_offset) {
1923 ins->opcode = OP_COMPARE_IMM;
1924 ins->sreg1 = last_ins->sreg1;
1926 /* check if we can remove cmp reg,0 with test null */
1928 ins->opcode = OP_X86_TEST_NULL;
1932 case OP_X86_PUSH_MEMBASE:
1933 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1934 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1935 ins->inst_basereg == last_ins->inst_destbasereg &&
1936 ins->inst_offset == last_ins->inst_offset) {
1937 ins->opcode = OP_X86_PUSH;
1938 ins->sreg1 = last_ins->sreg1;
1943 mono_peephole_ins (bb, ins);
1948 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1952 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1953 switch (ins->opcode) {
1955 /* reg = 0 -> XOR (reg, reg) */
1956 /* XOR sets cflags on x86, so we cant do it always */
1957 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1960 ins->opcode = OP_IXOR;
1961 ins->sreg1 = ins->dreg;
1962 ins->sreg2 = ins->dreg;
1965 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1966 * since it takes 3 bytes instead of 7.
1968 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
1969 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1970 ins2->opcode = OP_STORE_MEMBASE_REG;
1971 ins2->sreg1 = ins->dreg;
1973 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1974 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1975 ins2->sreg1 = ins->dreg;
1977 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1978 /* Continue iteration */
1987 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1988 ins->opcode = OP_X86_INC_REG;
1992 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1993 ins->opcode = OP_X86_DEC_REG;
1997 mono_peephole_ins (bb, ins);
2002 * mono_arch_lowering_pass:
2004 * Converts complex opcodes into simpler ones so that each IR instruction
2005 * corresponds to one machine instruction.
2008 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2010 MonoInst *ins, *next;
2013 * FIXME: Need to add more instructions, but the current machine
2014 * description can't model some parts of the composite instructions like
2017 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2018 switch (ins->opcode) {
2021 case OP_IDIV_UN_IMM:
2022 case OP_IREM_UN_IMM:
2024 * Keep the cases where we could generated optimized code, otherwise convert
2025 * to the non-imm variant.
2027 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2029 mono_decompose_op_imm (cfg, bb, ins);
2036 bb->max_vreg = cfg->next_vreg;
2040 branch_cc_table [] = {
2041 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2042 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2043 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2046 /* Maps CMP_... constants to X86_CC_... constants */
2049 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2050 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2054 cc_signed_table [] = {
2055 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2056 FALSE, FALSE, FALSE, FALSE
2059 static unsigned char*
2060 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2062 #define XMM_TEMP_REG 0
2063 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2064 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2065 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2066 /* optimize by assigning a local var for this use so we avoid
2067 * the stack manipulations */
2068 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2069 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2070 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2071 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2072 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2074 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2076 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2079 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2080 x86_fnstcw_membase(code, X86_ESP, 0);
2081 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2082 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2083 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2084 x86_fldcw_membase (code, X86_ESP, 2);
2086 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2087 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2088 x86_pop_reg (code, dreg);
2089 /* FIXME: need the high register
2090 * x86_pop_reg (code, dreg_high);
2093 x86_push_reg (code, X86_EAX); // SP = SP - 4
2094 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2095 x86_pop_reg (code, dreg);
2097 x86_fldcw_membase (code, X86_ESP, 0);
2098 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2101 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2103 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2107 static unsigned char*
2108 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2110 int sreg = tree->sreg1;
2111 int need_touch = FALSE;
2113 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2122 * If requested stack size is larger than one page,
2123 * perform stack-touch operation
2126 * Generate stack probe code.
2127 * Under Windows, it is necessary to allocate one page at a time,
2128 * "touching" stack after each successful sub-allocation. This is
2129 * because of the way stack growth is implemented - there is a
2130 * guard page before the lowest stack page that is currently commited.
2131 * Stack normally grows sequentially so OS traps access to the
2132 * guard page and commits more pages when needed.
2134 x86_test_reg_imm (code, sreg, ~0xFFF);
2135 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2137 br[2] = code; /* loop */
2138 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2139 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2142 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2143 * that follows only initializes the last part of the area.
2145 /* Same as the init code below with size==0x1000 */
2146 if (tree->flags & MONO_INST_INIT) {
2147 x86_push_reg (code, X86_EAX);
2148 x86_push_reg (code, X86_ECX);
2149 x86_push_reg (code, X86_EDI);
2150 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2151 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2152 if (cfg->param_area)
2153 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2155 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2157 x86_prefix (code, X86_REP_PREFIX);
2159 x86_pop_reg (code, X86_EDI);
2160 x86_pop_reg (code, X86_ECX);
2161 x86_pop_reg (code, X86_EAX);
2164 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2165 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2166 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2167 x86_patch (br[3], br[2]);
2168 x86_test_reg_reg (code, sreg, sreg);
2169 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2170 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2172 br[1] = code; x86_jump8 (code, 0);
2174 x86_patch (br[0], code);
2175 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2176 x86_patch (br[1], code);
2177 x86_patch (br[4], code);
2180 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2182 if (tree->flags & MONO_INST_INIT) {
2184 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2185 x86_push_reg (code, X86_EAX);
2188 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2189 x86_push_reg (code, X86_ECX);
2192 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2193 x86_push_reg (code, X86_EDI);
2197 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2198 if (sreg != X86_ECX)
2199 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2200 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2202 if (cfg->param_area)
2203 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2205 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2207 x86_prefix (code, X86_REP_PREFIX);
2210 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2211 x86_pop_reg (code, X86_EDI);
2212 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2213 x86_pop_reg (code, X86_ECX);
2214 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2215 x86_pop_reg (code, X86_EAX);
2222 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2224 /* Move return value to the target register */
2225 switch (ins->opcode) {
2228 case OP_CALL_MEMBASE:
2229 if (ins->dreg != X86_EAX)
2230 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2240 static int tls_gs_offset;
2244 mono_arch_have_fast_tls (void)
2247 static gboolean have_fast_tls = FALSE;
2248 static gboolean inited = FALSE;
2251 if (mini_get_debug_options ()->use_fallback_tls)
2254 return have_fast_tls;
2256 ins = (guint32*)pthread_getspecific;
2258 * We're looking for these two instructions:
2260 * mov 0x4(%esp),%eax
2261 * mov %gs:[offset](,%eax,4),%eax
2263 have_fast_tls = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2264 tls_gs_offset = ins [2];
2267 return have_fast_tls;
2268 #elif defined(TARGET_ANDROID)
2271 if (mini_get_debug_options ()->use_fallback_tls)
2278 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2280 #if defined(TARGET_MACH)
2281 x86_prefix (code, X86_GS_PREFIX);
2282 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2283 #elif defined(TARGET_WIN32)
2285 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2286 * Journal and/or a disassembly of the TlsGet () function.
2288 x86_prefix (code, X86_FS_PREFIX);
2289 x86_mov_reg_mem (code, dreg, 0x18, 4);
2290 if (tls_offset < 64) {
2291 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2295 g_assert (tls_offset < 0x440);
2296 /* Load TEB->TlsExpansionSlots */
2297 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2298 x86_test_reg_reg (code, dreg, dreg);
2300 x86_branch (code, X86_CC_EQ, code, TRUE);
2301 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2302 x86_patch (buf [0], code);
2305 if (optimize_for_xen) {
2306 x86_prefix (code, X86_GS_PREFIX);
2307 x86_mov_reg_mem (code, dreg, 0, 4);
2308 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2310 x86_prefix (code, X86_GS_PREFIX);
2311 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2318 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2320 #if defined(TARGET_MACH)
2321 x86_prefix (code, X86_GS_PREFIX);
2322 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2323 #elif defined(TARGET_WIN32)
2324 g_assert_not_reached ();
2326 x86_prefix (code, X86_GS_PREFIX);
2327 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2335 * Emit code to initialize an LMF structure at LMF_OFFSET.
2338 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2340 /* save all caller saved regs */
2341 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2342 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2343 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2344 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2345 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2346 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2347 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2349 /* save the current IP */
2350 if (cfg->compile_aot) {
2351 /* This pushes the current ip */
2352 x86_call_imm (code, 0);
2353 x86_pop_reg (code, X86_EAX);
2355 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2356 x86_mov_reg_imm (code, X86_EAX, 0);
2358 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2360 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2361 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2362 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2363 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2364 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2365 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2366 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2367 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2368 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2373 /* benchmark and set based on cpu */
2374 #define LOOP_ALIGNMENT 8
2375 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2379 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2384 guint8 *code = cfg->native_code + cfg->code_len;
2387 if (cfg->opt & MONO_OPT_LOOP) {
2388 int pad, align = LOOP_ALIGNMENT;
2389 /* set alignment depending on cpu */
2390 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2392 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2393 x86_padding (code, pad);
2394 cfg->code_len += pad;
2395 bb->native_offset = cfg->code_len;
2399 if (cfg->verbose_level > 2)
2400 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2402 cpos = bb->max_offset;
2404 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
2405 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2406 g_assert (!cfg->compile_aot);
2409 cov->data [bb->dfn].cil_code = bb->cil_code;
2410 /* this is not thread save, but good enough */
2411 x86_inc_mem (code, &cov->data [bb->dfn].count);
2414 offset = code - cfg->native_code;
2416 mono_debug_open_block (cfg, bb, offset);
2418 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2419 x86_breakpoint (code);
2421 MONO_BB_FOR_EACH_INS (bb, ins) {
2422 offset = code - cfg->native_code;
2424 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2426 #define EXTRA_CODE_SPACE (16)
2428 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2429 cfg->code_size *= 2;
2430 cfg->native_code = mono_realloc_native_code(cfg);
2431 code = cfg->native_code + offset;
2432 cfg->stat_code_reallocs++;
2435 if (cfg->debug_info)
2436 mono_debug_record_line_number (cfg, ins, offset);
2438 switch (ins->opcode) {
2440 x86_mul_reg (code, ins->sreg2, TRUE);
2443 x86_mul_reg (code, ins->sreg2, FALSE);
2445 case OP_X86_SETEQ_MEMBASE:
2446 case OP_X86_SETNE_MEMBASE:
2447 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2448 ins->inst_basereg, ins->inst_offset, TRUE);
2450 case OP_STOREI1_MEMBASE_IMM:
2451 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2453 case OP_STOREI2_MEMBASE_IMM:
2454 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2456 case OP_STORE_MEMBASE_IMM:
2457 case OP_STOREI4_MEMBASE_IMM:
2458 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2460 case OP_STOREI1_MEMBASE_REG:
2461 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2463 case OP_STOREI2_MEMBASE_REG:
2464 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2466 case OP_STORE_MEMBASE_REG:
2467 case OP_STOREI4_MEMBASE_REG:
2468 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2470 case OP_STORE_MEM_IMM:
2471 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2474 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2478 /* These are created by the cprop pass so they use inst_imm as the source */
2479 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2482 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2485 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2487 case OP_LOAD_MEMBASE:
2488 case OP_LOADI4_MEMBASE:
2489 case OP_LOADU4_MEMBASE:
2490 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2492 case OP_LOADU1_MEMBASE:
2493 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2495 case OP_LOADI1_MEMBASE:
2496 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2498 case OP_LOADU2_MEMBASE:
2499 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2501 case OP_LOADI2_MEMBASE:
2502 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2504 case OP_ICONV_TO_I1:
2506 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2508 case OP_ICONV_TO_I2:
2510 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2512 case OP_ICONV_TO_U1:
2513 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2515 case OP_ICONV_TO_U2:
2516 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2520 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2522 case OP_COMPARE_IMM:
2523 case OP_ICOMPARE_IMM:
2524 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2526 case OP_X86_COMPARE_MEMBASE_REG:
2527 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2529 case OP_X86_COMPARE_MEMBASE_IMM:
2530 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2532 case OP_X86_COMPARE_MEMBASE8_IMM:
2533 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2535 case OP_X86_COMPARE_REG_MEMBASE:
2536 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2538 case OP_X86_COMPARE_MEM_IMM:
2539 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2541 case OP_X86_TEST_NULL:
2542 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2544 case OP_X86_ADD_MEMBASE_IMM:
2545 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2547 case OP_X86_ADD_REG_MEMBASE:
2548 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2550 case OP_X86_SUB_MEMBASE_IMM:
2551 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2553 case OP_X86_SUB_REG_MEMBASE:
2554 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2556 case OP_X86_AND_MEMBASE_IMM:
2557 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2559 case OP_X86_OR_MEMBASE_IMM:
2560 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2562 case OP_X86_XOR_MEMBASE_IMM:
2563 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2565 case OP_X86_ADD_MEMBASE_REG:
2566 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2568 case OP_X86_SUB_MEMBASE_REG:
2569 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2571 case OP_X86_AND_MEMBASE_REG:
2572 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2574 case OP_X86_OR_MEMBASE_REG:
2575 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2577 case OP_X86_XOR_MEMBASE_REG:
2578 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2580 case OP_X86_INC_MEMBASE:
2581 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2583 case OP_X86_INC_REG:
2584 x86_inc_reg (code, ins->dreg);
2586 case OP_X86_DEC_MEMBASE:
2587 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2589 case OP_X86_DEC_REG:
2590 x86_dec_reg (code, ins->dreg);
2592 case OP_X86_MUL_REG_MEMBASE:
2593 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2595 case OP_X86_AND_REG_MEMBASE:
2596 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2598 case OP_X86_OR_REG_MEMBASE:
2599 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2601 case OP_X86_XOR_REG_MEMBASE:
2602 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2605 x86_breakpoint (code);
2607 case OP_RELAXED_NOP:
2608 x86_prefix (code, X86_REP_PREFIX);
2616 case OP_DUMMY_STORE:
2617 case OP_DUMMY_ICONST:
2618 case OP_DUMMY_R8CONST:
2619 case OP_NOT_REACHED:
2622 case OP_IL_SEQ_POINT:
2623 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2625 case OP_SEQ_POINT: {
2628 if (cfg->compile_aot)
2631 /* Have to use ecx as a temp reg since this can occur after OP_SETRET */
2634 * We do this _before_ the breakpoint, so single stepping after
2635 * a breakpoint is hit will step to the next IL offset.
2637 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
2638 MonoInst *var = cfg->arch.ss_tramp_var;
2642 g_assert (var->opcode == OP_REGOFFSET);
2643 /* Load ss_tramp_var */
2644 /* This is equal to &ss_trampoline */
2645 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, sizeof (mgreg_t));
2646 x86_mov_reg_membase (code, X86_ECX, X86_ECX, 0, sizeof (mgreg_t));
2647 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
2648 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2649 x86_call_reg (code, X86_ECX);
2650 x86_patch (br [0], code);
2654 * Many parts of sdb depend on the ip after the single step trampoline call to be equal to the seq point offset.
2655 * This means we have to put the loading of bp_tramp_var after the offset.
2658 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2660 MonoInst *var = cfg->arch.bp_tramp_var;
2663 g_assert (var->opcode == OP_REGOFFSET);
2664 /* Load the address of the bp trampoline */
2665 /* This needs to be constant size */
2666 guint8 *start = code;
2667 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, 4);
2668 if (code < start + OP_SEQ_POINT_BP_OFFSET) {
2669 int size = start + OP_SEQ_POINT_BP_OFFSET - code;
2670 x86_padding (code, size);
2673 * A placeholder for a possible breakpoint inserted by
2674 * mono_arch_set_breakpoint ().
2676 for (i = 0; i < 2; ++i)
2679 * Add an additional nop so skipping the bp doesn't cause the ip to point
2680 * to another IL offset.
2688 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2692 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2697 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2701 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2706 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2710 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2715 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2719 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2722 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2726 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2731 * The code is the same for div/rem, the allocator will allocate dreg
2732 * to RAX/RDX as appropriate.
2734 if (ins->sreg2 == X86_EDX) {
2735 /* cdq clobbers this */
2736 x86_push_reg (code, ins->sreg2);
2738 x86_div_membase (code, X86_ESP, 0, TRUE);
2739 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2742 x86_div_reg (code, ins->sreg2, TRUE);
2747 if (ins->sreg2 == X86_EDX) {
2748 x86_push_reg (code, ins->sreg2);
2749 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2750 x86_div_membase (code, X86_ESP, 0, FALSE);
2751 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2753 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2754 x86_div_reg (code, ins->sreg2, FALSE);
2758 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2760 x86_div_reg (code, ins->sreg2, TRUE);
2763 int power = mono_is_power_of_two (ins->inst_imm);
2765 g_assert (ins->sreg1 == X86_EAX);
2766 g_assert (ins->dreg == X86_EAX);
2767 g_assert (power >= 0);
2770 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2772 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2774 * If the divident is >= 0, this does not nothing. If it is positive, it
2775 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2777 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2778 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2779 } else if (power == 0) {
2780 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2782 /* Based on gcc code */
2784 /* Add compensation for negative dividents */
2786 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2787 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2788 /* Compute remainder */
2789 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2790 /* Remove compensation */
2791 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2796 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2800 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2803 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2807 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2810 g_assert (ins->sreg2 == X86_ECX);
2811 x86_shift_reg (code, X86_SHL, ins->dreg);
2814 g_assert (ins->sreg2 == X86_ECX);
2815 x86_shift_reg (code, X86_SAR, ins->dreg);
2819 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2822 case OP_ISHR_UN_IMM:
2823 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2826 g_assert (ins->sreg2 == X86_ECX);
2827 x86_shift_reg (code, X86_SHR, ins->dreg);
2831 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2834 guint8 *jump_to_end;
2836 /* handle shifts below 32 bits */
2837 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2838 x86_shift_reg (code, X86_SHL, ins->sreg1);
2840 x86_test_reg_imm (code, X86_ECX, 32);
2841 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2843 /* handle shift over 32 bit */
2844 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2845 x86_clear_reg (code, ins->sreg1);
2847 x86_patch (jump_to_end, code);
2851 guint8 *jump_to_end;
2853 /* handle shifts below 32 bits */
2854 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2855 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2857 x86_test_reg_imm (code, X86_ECX, 32);
2858 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2860 /* handle shifts over 31 bits */
2861 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2862 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2864 x86_patch (jump_to_end, code);
2868 guint8 *jump_to_end;
2870 /* handle shifts below 32 bits */
2871 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2872 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2874 x86_test_reg_imm (code, X86_ECX, 32);
2875 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2877 /* handle shifts over 31 bits */
2878 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2879 x86_clear_reg (code, ins->backend.reg3);
2881 x86_patch (jump_to_end, code);
2885 if (ins->inst_imm >= 32) {
2886 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2887 x86_clear_reg (code, ins->sreg1);
2888 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2890 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2891 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2895 if (ins->inst_imm >= 32) {
2896 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2897 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2898 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2900 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2901 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2904 case OP_LSHR_UN_IMM:
2905 if (ins->inst_imm >= 32) {
2906 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2907 x86_clear_reg (code, ins->backend.reg3);
2908 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2910 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2911 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2915 x86_not_reg (code, ins->sreg1);
2918 x86_neg_reg (code, ins->sreg1);
2922 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2926 switch (ins->inst_imm) {
2930 if (ins->dreg != ins->sreg1)
2931 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2932 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2935 /* LEA r1, [r2 + r2*2] */
2936 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2939 /* LEA r1, [r2 + r2*4] */
2940 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2943 /* LEA r1, [r2 + r2*2] */
2945 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2946 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2949 /* LEA r1, [r2 + r2*8] */
2950 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2953 /* LEA r1, [r2 + r2*4] */
2955 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2956 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2959 /* LEA r1, [r2 + r2*2] */
2961 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2962 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2965 /* LEA r1, [r2 + r2*4] */
2966 /* LEA r1, [r1 + r1*4] */
2967 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2968 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2971 /* LEA r1, [r2 + r2*4] */
2973 /* LEA r1, [r1 + r1*4] */
2974 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2975 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2976 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2979 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2984 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2985 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2987 case OP_IMUL_OVF_UN: {
2988 /* the mul operation and the exception check should most likely be split */
2989 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2990 /*g_assert (ins->sreg2 == X86_EAX);
2991 g_assert (ins->dreg == X86_EAX);*/
2992 if (ins->sreg2 == X86_EAX) {
2993 non_eax_reg = ins->sreg1;
2994 } else if (ins->sreg1 == X86_EAX) {
2995 non_eax_reg = ins->sreg2;
2997 /* no need to save since we're going to store to it anyway */
2998 if (ins->dreg != X86_EAX) {
3000 x86_push_reg (code, X86_EAX);
3002 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3003 non_eax_reg = ins->sreg2;
3005 if (ins->dreg == X86_EDX) {
3008 x86_push_reg (code, X86_EAX);
3012 x86_push_reg (code, X86_EDX);
3014 x86_mul_reg (code, non_eax_reg, FALSE);
3015 /* save before the check since pop and mov don't change the flags */
3016 if (ins->dreg != X86_EAX)
3017 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3019 x86_pop_reg (code, X86_EDX);
3021 x86_pop_reg (code, X86_EAX);
3022 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3026 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3029 g_assert_not_reached ();
3030 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3031 x86_mov_reg_imm (code, ins->dreg, 0);
3034 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3035 x86_mov_reg_imm (code, ins->dreg, 0);
3037 case OP_LOAD_GOTADDR:
3038 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3039 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3042 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3043 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3045 case OP_X86_PUSH_GOT_ENTRY:
3046 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3047 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3050 if (ins->dreg != ins->sreg1)
3051 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3054 MonoCallInst *call = (MonoCallInst*)ins;
3057 ins->flags |= MONO_INST_GC_CALLSITE;
3058 ins->backend.pc_offset = code - cfg->native_code;
3060 /* reset offset to make max_len work */
3061 offset = code - cfg->native_code;
3063 g_assert (!cfg->method->save_lmf);
3065 /* restore callee saved registers */
3066 for (i = 0; i < X86_NREG; ++i)
3067 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3069 if (cfg->used_int_regs & (1 << X86_ESI)) {
3070 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3073 if (cfg->used_int_regs & (1 << X86_EDI)) {
3074 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3077 if (cfg->used_int_regs & (1 << X86_EBX)) {
3078 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3082 /* Copy arguments on the stack to our argument area */
3083 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3084 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3085 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3088 /* restore ESP/EBP */
3090 offset = code - cfg->native_code;
3091 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3092 x86_jump32 (code, 0);
3094 ins->flags |= MONO_INST_GC_CALLSITE;
3095 cfg->disable_aot = TRUE;
3099 /* ensure ins->sreg1 is not NULL
3100 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3101 * cmp DWORD PTR [eax], 0
3103 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3106 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3107 x86_push_reg (code, hreg);
3108 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3109 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3110 x86_pop_reg (code, hreg);
3123 case OP_VOIDCALL_REG:
3125 case OP_FCALL_MEMBASE:
3126 case OP_LCALL_MEMBASE:
3127 case OP_VCALL_MEMBASE:
3128 case OP_VCALL2_MEMBASE:
3129 case OP_VOIDCALL_MEMBASE:
3130 case OP_CALL_MEMBASE: {
3133 call = (MonoCallInst*)ins;
3134 cinfo = (CallInfo*)call->call_info;
3136 switch (ins->opcode) {
3143 if (ins->flags & MONO_INST_HAS_METHOD)
3144 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3146 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3152 case OP_VOIDCALL_REG:
3154 x86_call_reg (code, ins->sreg1);
3156 case OP_FCALL_MEMBASE:
3157 case OP_LCALL_MEMBASE:
3158 case OP_VCALL_MEMBASE:
3159 case OP_VCALL2_MEMBASE:
3160 case OP_VOIDCALL_MEMBASE:
3161 case OP_CALL_MEMBASE:
3162 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3165 g_assert_not_reached ();
3168 ins->flags |= MONO_INST_GC_CALLSITE;
3169 ins->backend.pc_offset = code - cfg->native_code;
3170 if (cinfo->callee_stack_pop) {
3171 /* Have to compensate for the stack space popped by the callee */
3172 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3174 code = emit_move_return_value (cfg, ins, code);
3178 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3180 case OP_X86_LEA_MEMBASE:
3181 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3184 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3187 /* keep alignment */
3188 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3189 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3190 code = mono_emit_stack_alloc (cfg, code, ins);
3191 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3192 if (cfg->param_area)
3193 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3195 case OP_LOCALLOC_IMM: {
3196 guint32 size = ins->inst_imm;
3197 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3199 if (ins->flags & MONO_INST_INIT) {
3200 /* FIXME: Optimize this */
3201 x86_mov_reg_imm (code, ins->dreg, size);
3202 ins->sreg1 = ins->dreg;
3204 code = mono_emit_stack_alloc (cfg, code, ins);
3205 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3207 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3208 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3210 if (cfg->param_area)
3211 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3215 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3216 x86_push_reg (code, ins->sreg1);
3217 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3218 (gpointer)"mono_arch_throw_exception");
3219 ins->flags |= MONO_INST_GC_CALLSITE;
3220 ins->backend.pc_offset = code - cfg->native_code;
3224 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3225 x86_push_reg (code, ins->sreg1);
3226 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3227 (gpointer)"mono_arch_rethrow_exception");
3228 ins->flags |= MONO_INST_GC_CALLSITE;
3229 ins->backend.pc_offset = code - cfg->native_code;
3232 case OP_CALL_HANDLER:
3233 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3234 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3235 x86_call_imm (code, 0);
3236 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3237 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3239 case OP_START_HANDLER: {
3240 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3241 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3242 if (cfg->param_area)
3243 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3246 case OP_ENDFINALLY: {
3247 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3248 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3252 case OP_ENDFILTER: {
3253 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3254 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3255 /* The local allocator will put the result into EAX */
3260 if (ins->dreg != X86_EAX)
3261 x86_mov_reg_reg (code, ins->dreg, X86_EAX, sizeof (gpointer));
3265 ins->inst_c0 = code - cfg->native_code;
3268 if (ins->inst_target_bb->native_offset) {
3269 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3271 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3272 if ((cfg->opt & MONO_OPT_BRANCH) &&
3273 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3274 x86_jump8 (code, 0);
3276 x86_jump32 (code, 0);
3280 x86_jump_reg (code, ins->sreg1);
3299 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3300 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3302 case OP_COND_EXC_EQ:
3303 case OP_COND_EXC_NE_UN:
3304 case OP_COND_EXC_LT:
3305 case OP_COND_EXC_LT_UN:
3306 case OP_COND_EXC_GT:
3307 case OP_COND_EXC_GT_UN:
3308 case OP_COND_EXC_GE:
3309 case OP_COND_EXC_GE_UN:
3310 case OP_COND_EXC_LE:
3311 case OP_COND_EXC_LE_UN:
3312 case OP_COND_EXC_IEQ:
3313 case OP_COND_EXC_INE_UN:
3314 case OP_COND_EXC_ILT:
3315 case OP_COND_EXC_ILT_UN:
3316 case OP_COND_EXC_IGT:
3317 case OP_COND_EXC_IGT_UN:
3318 case OP_COND_EXC_IGE:
3319 case OP_COND_EXC_IGE_UN:
3320 case OP_COND_EXC_ILE:
3321 case OP_COND_EXC_ILE_UN:
3322 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3324 case OP_COND_EXC_OV:
3325 case OP_COND_EXC_NO:
3327 case OP_COND_EXC_NC:
3328 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3330 case OP_COND_EXC_IOV:
3331 case OP_COND_EXC_INO:
3332 case OP_COND_EXC_IC:
3333 case OP_COND_EXC_INC:
3334 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3346 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3354 case OP_CMOV_INE_UN:
3355 case OP_CMOV_IGE_UN:
3356 case OP_CMOV_IGT_UN:
3357 case OP_CMOV_ILE_UN:
3358 case OP_CMOV_ILT_UN:
3359 g_assert (ins->dreg == ins->sreg1);
3360 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3363 /* floating point opcodes */
3365 double d = *(double *)ins->inst_p0;
3367 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3369 } else if (d == 1.0) {
3372 if (cfg->compile_aot) {
3373 guint32 *val = (guint32*)&d;
3374 x86_push_imm (code, val [1]);
3375 x86_push_imm (code, val [0]);
3376 x86_fld_membase (code, X86_ESP, 0, TRUE);
3377 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3380 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3381 x86_fld (code, NULL, TRUE);
3387 float f = *(float *)ins->inst_p0;
3389 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3391 } else if (f == 1.0) {
3394 if (cfg->compile_aot) {
3395 guint32 val = *(guint32*)&f;
3396 x86_push_imm (code, val);
3397 x86_fld_membase (code, X86_ESP, 0, FALSE);
3398 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3401 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3402 x86_fld (code, NULL, FALSE);
3407 case OP_STORER8_MEMBASE_REG:
3408 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3410 case OP_LOADR8_MEMBASE:
3411 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3413 case OP_STORER4_MEMBASE_REG:
3414 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3416 case OP_LOADR4_MEMBASE:
3417 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3419 case OP_ICONV_TO_R4:
3420 x86_push_reg (code, ins->sreg1);
3421 x86_fild_membase (code, X86_ESP, 0, FALSE);
3422 /* Change precision */
3423 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3424 x86_fld_membase (code, X86_ESP, 0, FALSE);
3425 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3427 case OP_ICONV_TO_R8:
3428 x86_push_reg (code, ins->sreg1);
3429 x86_fild_membase (code, X86_ESP, 0, FALSE);
3430 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3432 case OP_ICONV_TO_R_UN:
3433 x86_push_imm (code, 0);
3434 x86_push_reg (code, ins->sreg1);
3435 x86_fild_membase (code, X86_ESP, 0, TRUE);
3436 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3438 case OP_X86_FP_LOAD_I8:
3439 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3441 case OP_X86_FP_LOAD_I4:
3442 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3444 case OP_FCONV_TO_R4:
3445 /* Change precision */
3446 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3447 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3448 x86_fld_membase (code, X86_ESP, 0, FALSE);
3449 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3451 case OP_FCONV_TO_I1:
3452 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3454 case OP_FCONV_TO_U1:
3455 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3457 case OP_FCONV_TO_I2:
3458 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3460 case OP_FCONV_TO_U2:
3461 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3463 case OP_FCONV_TO_I4:
3465 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3467 case OP_FCONV_TO_I8:
3468 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3469 x86_fnstcw_membase(code, X86_ESP, 0);
3470 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3471 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3472 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3473 x86_fldcw_membase (code, X86_ESP, 2);
3474 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3475 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3476 x86_pop_reg (code, ins->dreg);
3477 x86_pop_reg (code, ins->backend.reg3);
3478 x86_fldcw_membase (code, X86_ESP, 0);
3479 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3481 case OP_LCONV_TO_R8_2:
3482 x86_push_reg (code, ins->sreg2);
3483 x86_push_reg (code, ins->sreg1);
3484 x86_fild_membase (code, X86_ESP, 0, TRUE);
3485 /* Change precision */
3486 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3487 x86_fld_membase (code, X86_ESP, 0, TRUE);
3488 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3490 case OP_LCONV_TO_R4_2:
3491 x86_push_reg (code, ins->sreg2);
3492 x86_push_reg (code, ins->sreg1);
3493 x86_fild_membase (code, X86_ESP, 0, TRUE);
3494 /* Change precision */
3495 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3496 x86_fld_membase (code, X86_ESP, 0, FALSE);
3497 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3499 case OP_LCONV_TO_R_UN_2: {
3500 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3503 /* load 64bit integer to FP stack */
3504 x86_push_reg (code, ins->sreg2);
3505 x86_push_reg (code, ins->sreg1);
3506 x86_fild_membase (code, X86_ESP, 0, TRUE);
3508 /* test if lreg is negative */
3509 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3510 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3512 /* add correction constant mn */
3513 if (cfg->compile_aot) {
3514 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3515 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3516 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3517 x86_fld80_membase (code, X86_ESP, 2);
3518 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3520 x86_fld80_mem (code, mn);
3522 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3524 x86_patch (br, code);
3526 /* Change precision */
3527 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3528 x86_fld_membase (code, X86_ESP, 0, TRUE);
3530 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3534 case OP_LCONV_TO_OVF_I:
3535 case OP_LCONV_TO_OVF_I4_2: {
3536 guint8 *br [3], *label [1];
3540 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3542 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3544 /* If the low word top bit is set, see if we are negative */
3545 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3546 /* We are not negative (no top bit set, check for our top word to be zero */
3547 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3548 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3551 /* throw exception */
3552 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3554 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3555 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3556 x86_jump8 (code, 0);
3558 x86_jump32 (code, 0);
3560 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3561 x86_jump32 (code, 0);
3565 x86_patch (br [0], code);
3566 /* our top bit is set, check that top word is 0xfffffff */
3567 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3569 x86_patch (br [1], code);
3570 /* nope, emit exception */
3571 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3572 x86_patch (br [2], label [0]);
3574 if (ins->dreg != ins->sreg1)
3575 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3579 /* Not needed on the fp stack */
3581 case OP_MOVE_F_TO_I4:
3582 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
3583 x86_mov_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, 4);
3585 case OP_MOVE_I4_TO_F:
3586 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
3587 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
3590 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3593 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3596 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3599 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3607 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3612 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3619 * it really doesn't make sense to inline all this code,
3620 * it's here just to show that things may not be as simple
3623 guchar *check_pos, *end_tan, *pop_jump;
3624 x86_push_reg (code, X86_EAX);
3627 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3629 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3630 x86_fstp (code, 0); /* pop the 1.0 */
3632 x86_jump8 (code, 0);
3634 x86_fp_op (code, X86_FADD, 0);
3638 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3640 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3643 x86_patch (pop_jump, code);
3644 x86_fstp (code, 0); /* pop the 1.0 */
3645 x86_patch (check_pos, code);
3646 x86_patch (end_tan, code);
3648 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3649 x86_pop_reg (code, X86_EAX);
3656 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3665 g_assert (cfg->opt & MONO_OPT_CMOV);
3666 g_assert (ins->dreg == ins->sreg1);
3667 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3668 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3671 g_assert (cfg->opt & MONO_OPT_CMOV);
3672 g_assert (ins->dreg == ins->sreg1);
3673 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3674 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3677 g_assert (cfg->opt & MONO_OPT_CMOV);
3678 g_assert (ins->dreg == ins->sreg1);
3679 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3680 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3683 g_assert (cfg->opt & MONO_OPT_CMOV);
3684 g_assert (ins->dreg == ins->sreg1);
3685 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3686 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3692 x86_fxch (code, ins->inst_imm);
3697 x86_push_reg (code, X86_EAX);
3698 /* we need to exchange ST(0) with ST(1) */
3701 /* this requires a loop, because fprem somtimes
3702 * returns a partial remainder */
3704 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3705 /* x86_fprem1 (code); */
3708 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3710 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3716 x86_pop_reg (code, X86_EAX);
3720 if (cfg->opt & MONO_OPT_FCMOV) {
3721 x86_fcomip (code, 1);
3725 /* this overwrites EAX */
3726 EMIT_FPCOMPARE(code);
3727 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3731 if (cfg->opt & MONO_OPT_FCMOV) {
3732 /* zeroing the register at the start results in
3733 * shorter and faster code (we can also remove the widening op)
3735 guchar *unordered_check;
3736 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3737 x86_fcomip (code, 1);
3739 unordered_check = code;
3740 x86_branch8 (code, X86_CC_P, 0, FALSE);
3741 if (ins->opcode == OP_FCEQ) {
3742 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3743 x86_patch (unordered_check, code);
3745 guchar *jump_to_end;
3746 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3748 x86_jump8 (code, 0);
3749 x86_patch (unordered_check, code);
3750 x86_inc_reg (code, ins->dreg);
3751 x86_patch (jump_to_end, code);
3756 if (ins->dreg != X86_EAX)
3757 x86_push_reg (code, X86_EAX);
3759 EMIT_FPCOMPARE(code);
3760 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3761 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3762 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3763 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3765 if (ins->dreg != X86_EAX)
3766 x86_pop_reg (code, X86_EAX);
3770 if (cfg->opt & MONO_OPT_FCMOV) {
3771 /* zeroing the register at the start results in
3772 * shorter and faster code (we can also remove the widening op)
3774 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3775 x86_fcomip (code, 1);
3777 if (ins->opcode == OP_FCLT_UN) {
3778 guchar *unordered_check = code;
3779 guchar *jump_to_end;
3780 x86_branch8 (code, X86_CC_P, 0, FALSE);
3781 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3783 x86_jump8 (code, 0);
3784 x86_patch (unordered_check, code);
3785 x86_inc_reg (code, ins->dreg);
3786 x86_patch (jump_to_end, code);
3788 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3792 if (ins->dreg != X86_EAX)
3793 x86_push_reg (code, X86_EAX);
3795 EMIT_FPCOMPARE(code);
3796 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3797 if (ins->opcode == OP_FCLT_UN) {
3798 guchar *is_not_zero_check, *end_jump;
3799 is_not_zero_check = code;
3800 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3802 x86_jump8 (code, 0);
3803 x86_patch (is_not_zero_check, code);
3804 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3806 x86_patch (end_jump, code);
3808 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3809 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3811 if (ins->dreg != X86_EAX)
3812 x86_pop_reg (code, X86_EAX);
3815 guchar *unordered_check;
3816 guchar *jump_to_end;
3817 if (cfg->opt & MONO_OPT_FCMOV) {
3818 /* zeroing the register at the start results in
3819 * shorter and faster code (we can also remove the widening op)
3821 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3822 x86_fcomip (code, 1);
3824 unordered_check = code;
3825 x86_branch8 (code, X86_CC_P, 0, FALSE);
3826 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3827 x86_patch (unordered_check, code);
3830 if (ins->dreg != X86_EAX)
3831 x86_push_reg (code, X86_EAX);
3833 EMIT_FPCOMPARE(code);
3834 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3835 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3836 unordered_check = code;
3837 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3839 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3840 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3841 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3843 x86_jump8 (code, 0);
3844 x86_patch (unordered_check, code);
3845 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3846 x86_patch (jump_to_end, code);
3848 if (ins->dreg != X86_EAX)
3849 x86_pop_reg (code, X86_EAX);
3854 if (cfg->opt & MONO_OPT_FCMOV) {
3855 /* zeroing the register at the start results in
3856 * shorter and faster code (we can also remove the widening op)
3858 guchar *unordered_check;
3859 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3860 x86_fcomip (code, 1);
3862 if (ins->opcode == OP_FCGT) {
3863 unordered_check = code;
3864 x86_branch8 (code, X86_CC_P, 0, FALSE);
3865 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3866 x86_patch (unordered_check, code);
3868 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3872 if (ins->dreg != X86_EAX)
3873 x86_push_reg (code, X86_EAX);
3875 EMIT_FPCOMPARE(code);
3876 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3877 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3878 if (ins->opcode == OP_FCGT_UN) {
3879 guchar *is_not_zero_check, *end_jump;
3880 is_not_zero_check = code;
3881 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3883 x86_jump8 (code, 0);
3884 x86_patch (is_not_zero_check, code);
3885 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3887 x86_patch (end_jump, code);
3889 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3890 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3892 if (ins->dreg != X86_EAX)
3893 x86_pop_reg (code, X86_EAX);
3896 guchar *unordered_check;
3897 guchar *jump_to_end;
3898 if (cfg->opt & MONO_OPT_FCMOV) {
3899 /* zeroing the register at the start results in
3900 * shorter and faster code (we can also remove the widening op)
3902 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3903 x86_fcomip (code, 1);
3905 unordered_check = code;
3906 x86_branch8 (code, X86_CC_P, 0, FALSE);
3907 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
3908 x86_patch (unordered_check, code);
3911 if (ins->dreg != X86_EAX)
3912 x86_push_reg (code, X86_EAX);
3914 EMIT_FPCOMPARE(code);
3915 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3916 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3917 unordered_check = code;
3918 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3920 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3921 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
3922 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3924 x86_jump8 (code, 0);
3925 x86_patch (unordered_check, code);
3926 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3927 x86_patch (jump_to_end, code);
3929 if (ins->dreg != X86_EAX)
3930 x86_pop_reg (code, X86_EAX);
3934 if (cfg->opt & MONO_OPT_FCMOV) {
3935 guchar *jump = code;
3936 x86_branch8 (code, X86_CC_P, 0, TRUE);
3937 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3938 x86_patch (jump, code);
3941 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3942 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3945 /* Branch if C013 != 100 */
3946 if (cfg->opt & MONO_OPT_FCMOV) {
3947 /* branch if !ZF or (PF|CF) */
3948 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3949 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3950 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3953 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3954 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3957 if (cfg->opt & MONO_OPT_FCMOV) {
3958 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3961 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3964 if (cfg->opt & MONO_OPT_FCMOV) {
3965 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3966 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3969 if (ins->opcode == OP_FBLT_UN) {
3970 guchar *is_not_zero_check, *end_jump;
3971 is_not_zero_check = code;
3972 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3974 x86_jump8 (code, 0);
3975 x86_patch (is_not_zero_check, code);
3976 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3978 x86_patch (end_jump, code);
3980 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3984 if (cfg->opt & MONO_OPT_FCMOV) {
3985 if (ins->opcode == OP_FBGT) {
3988 /* skip branch if C1=1 */
3990 x86_branch8 (code, X86_CC_P, 0, FALSE);
3991 /* branch if (C0 | C3) = 1 */
3992 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3993 x86_patch (br1, code);
3995 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3999 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4000 if (ins->opcode == OP_FBGT_UN) {
4001 guchar *is_not_zero_check, *end_jump;
4002 is_not_zero_check = code;
4003 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4005 x86_jump8 (code, 0);
4006 x86_patch (is_not_zero_check, code);
4007 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4009 x86_patch (end_jump, code);
4011 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4014 /* Branch if C013 == 100 or 001 */
4015 if (cfg->opt & MONO_OPT_FCMOV) {
4018 /* skip branch if C1=1 */
4020 x86_branch8 (code, X86_CC_P, 0, FALSE);
4021 /* branch if (C0 | C3) = 1 */
4022 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4023 x86_patch (br1, code);
4026 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4027 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4028 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4029 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4032 /* Branch if C013 == 000 */
4033 if (cfg->opt & MONO_OPT_FCMOV) {
4034 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4037 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4040 /* Branch if C013=000 or 100 */
4041 if (cfg->opt & MONO_OPT_FCMOV) {
4044 /* skip branch if C1=1 */
4046 x86_branch8 (code, X86_CC_P, 0, FALSE);
4047 /* branch if C0=0 */
4048 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4049 x86_patch (br1, code);
4052 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4053 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4054 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4057 /* Branch if C013 != 001 */
4058 if (cfg->opt & MONO_OPT_FCMOV) {
4059 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4060 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4063 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4064 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4068 x86_push_reg (code, X86_EAX);
4071 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4072 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4073 x86_pop_reg (code, X86_EAX);
4075 /* Have to clean up the fp stack before throwing the exception */
4077 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4080 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
4082 x86_patch (br1, code);
4086 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4090 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4093 case OP_MEMORY_BARRIER: {
4094 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4095 x86_prefix (code, X86_LOCK_PREFIX);
4096 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4100 case OP_ATOMIC_ADD_I4: {
4101 int dreg = ins->dreg;
4103 g_assert (cfg->has_atomic_add_i4);
4105 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4106 if (ins->sreg2 == dreg) {
4107 if (dreg == X86_EBX) {
4109 if (ins->inst_basereg == X86_EDI)
4113 if (ins->inst_basereg == X86_EBX)
4116 } else if (ins->inst_basereg == dreg) {
4117 if (dreg == X86_EBX) {
4119 if (ins->sreg2 == X86_EDI)
4123 if (ins->sreg2 == X86_EBX)
4128 if (dreg != ins->dreg) {
4129 x86_push_reg (code, dreg);
4132 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4133 x86_prefix (code, X86_LOCK_PREFIX);
4134 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4135 /* dreg contains the old value, add with sreg2 value */
4136 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4138 if (ins->dreg != dreg) {
4139 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4140 x86_pop_reg (code, dreg);
4145 case OP_ATOMIC_EXCHANGE_I4: {
4147 int sreg2 = ins->sreg2;
4148 int breg = ins->inst_basereg;
4150 g_assert (cfg->has_atomic_exchange_i4);
4152 /* cmpxchg uses eax as comperand, need to make sure we can use it
4153 * hack to overcome limits in x86 reg allocator
4154 * (req: dreg == eax and sreg2 != eax and breg != eax)
4156 g_assert (ins->dreg == X86_EAX);
4158 /* We need the EAX reg for the cmpxchg */
4159 if (ins->sreg2 == X86_EAX) {
4160 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4161 x86_push_reg (code, sreg2);
4162 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4165 if (breg == X86_EAX) {
4166 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4167 x86_push_reg (code, breg);
4168 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4171 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4173 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4174 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4175 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4176 x86_patch (br [1], br [0]);
4178 if (breg != ins->inst_basereg)
4179 x86_pop_reg (code, breg);
4181 if (ins->sreg2 != sreg2)
4182 x86_pop_reg (code, sreg2);
4186 case OP_ATOMIC_CAS_I4: {
4187 g_assert (ins->dreg == X86_EAX);
4188 g_assert (ins->sreg3 == X86_EAX);
4189 g_assert (ins->sreg1 != X86_EAX);
4190 g_assert (ins->sreg1 != ins->sreg2);
4192 x86_prefix (code, X86_LOCK_PREFIX);
4193 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4196 case OP_ATOMIC_LOAD_I1: {
4197 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4200 case OP_ATOMIC_LOAD_U1: {
4201 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4204 case OP_ATOMIC_LOAD_I2: {
4205 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4208 case OP_ATOMIC_LOAD_U2: {
4209 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4212 case OP_ATOMIC_LOAD_I4:
4213 case OP_ATOMIC_LOAD_U4: {
4214 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4217 case OP_ATOMIC_LOAD_R4:
4218 case OP_ATOMIC_LOAD_R8: {
4219 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4222 case OP_ATOMIC_STORE_I1:
4223 case OP_ATOMIC_STORE_U1:
4224 case OP_ATOMIC_STORE_I2:
4225 case OP_ATOMIC_STORE_U2:
4226 case OP_ATOMIC_STORE_I4:
4227 case OP_ATOMIC_STORE_U4: {
4230 switch (ins->opcode) {
4231 case OP_ATOMIC_STORE_I1:
4232 case OP_ATOMIC_STORE_U1:
4235 case OP_ATOMIC_STORE_I2:
4236 case OP_ATOMIC_STORE_U2:
4239 case OP_ATOMIC_STORE_I4:
4240 case OP_ATOMIC_STORE_U4:
4245 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4247 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4251 case OP_ATOMIC_STORE_R4:
4252 case OP_ATOMIC_STORE_R8: {
4253 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4255 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4259 case OP_CARD_TABLE_WBARRIER: {
4260 int ptr = ins->sreg1;
4261 int value = ins->sreg2;
4263 int nursery_shift, card_table_shift;
4264 gpointer card_table_mask;
4265 size_t nursery_size;
4266 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4267 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4268 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4271 * We need one register we can clobber, we choose EDX and make sreg1
4272 * fixed EAX to work around limitations in the local register allocator.
4273 * sreg2 might get allocated to EDX, but that is not a problem since
4274 * we use it before clobbering EDX.
4276 g_assert (ins->sreg1 == X86_EAX);
4279 * This is the code we produce:
4282 * edx >>= nursery_shift
4283 * cmp edx, (nursery_start >> nursery_shift)
4286 * edx >>= card_table_shift
4287 * card_table[edx] = 1
4291 if (card_table_nursery_check) {
4292 if (value != X86_EDX)
4293 x86_mov_reg_reg (code, X86_EDX, value, 4);
4294 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4295 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4296 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4298 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4299 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4300 if (card_table_mask)
4301 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4302 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4303 if (card_table_nursery_check)
4304 x86_patch (br, code);
4307 #ifdef MONO_ARCH_SIMD_INTRINSICS
4309 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4312 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4315 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4318 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4321 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4324 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4327 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4328 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4331 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4334 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4337 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4340 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4343 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4346 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4349 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4352 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4355 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4358 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4361 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4364 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4367 case OP_PSHUFLEW_HIGH:
4368 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4369 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4371 case OP_PSHUFLEW_LOW:
4372 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4373 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4376 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4377 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4380 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4381 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4384 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4385 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4389 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4392 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4395 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4398 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4401 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4404 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4407 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4408 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4411 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4414 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4417 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4420 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4423 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4426 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4429 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4432 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4435 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4438 case OP_EXTRACT_MASK:
4439 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4443 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4446 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4449 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4453 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4456 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4459 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4462 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4466 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4469 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4472 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4475 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4479 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4482 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4485 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4489 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4492 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4495 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4499 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4502 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4506 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4509 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4512 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4516 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4519 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4522 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4526 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4529 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4532 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4535 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4539 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4542 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4545 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4548 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4551 case OP_PSUM_ABS_DIFF:
4552 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4555 case OP_UNPACK_LOWB:
4556 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4558 case OP_UNPACK_LOWW:
4559 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4561 case OP_UNPACK_LOWD:
4562 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4564 case OP_UNPACK_LOWQ:
4565 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4567 case OP_UNPACK_LOWPS:
4568 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4570 case OP_UNPACK_LOWPD:
4571 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4574 case OP_UNPACK_HIGHB:
4575 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4577 case OP_UNPACK_HIGHW:
4578 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4580 case OP_UNPACK_HIGHD:
4581 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4583 case OP_UNPACK_HIGHQ:
4584 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4586 case OP_UNPACK_HIGHPS:
4587 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4589 case OP_UNPACK_HIGHPD:
4590 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4594 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4597 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4600 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4603 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4606 case OP_PADDB_SAT_UN:
4607 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4609 case OP_PSUBB_SAT_UN:
4610 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4612 case OP_PADDW_SAT_UN:
4613 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4615 case OP_PSUBW_SAT_UN:
4616 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4620 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4623 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4626 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4629 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4633 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4636 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4639 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4641 case OP_PMULW_HIGH_UN:
4642 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4645 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4649 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4652 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4656 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4659 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4663 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4666 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4670 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4673 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4677 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4680 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4684 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4687 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4691 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4694 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4698 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4701 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4705 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4708 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4712 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4714 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4715 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4719 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4721 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4722 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4726 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4728 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4729 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4733 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4735 case OP_EXTRACTX_U2:
4736 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4738 case OP_INSERTX_U1_SLOW:
4739 /*sreg1 is the extracted ireg (scratch)
4740 /sreg2 is the to be inserted ireg (scratch)
4741 /dreg is the xreg to receive the value*/
4743 /*clear the bits from the extracted word*/
4744 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4745 /*shift the value to insert if needed*/
4746 if (ins->inst_c0 & 1)
4747 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4748 /*join them together*/
4749 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4750 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4752 case OP_INSERTX_I4_SLOW:
4753 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4754 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4755 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4758 case OP_INSERTX_R4_SLOW:
4759 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4760 /*TODO if inst_c0 == 0 use movss*/
4761 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4762 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4764 case OP_INSERTX_R8_SLOW:
4765 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4766 if (cfg->verbose_level)
4767 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4769 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4771 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4774 case OP_STOREX_MEMBASE_REG:
4775 case OP_STOREX_MEMBASE:
4776 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4778 case OP_LOADX_MEMBASE:
4779 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4781 case OP_LOADX_ALIGNED_MEMBASE:
4782 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4784 case OP_STOREX_ALIGNED_MEMBASE_REG:
4785 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4787 case OP_STOREX_NTA_MEMBASE_REG:
4788 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4790 case OP_PREFETCH_MEMBASE:
4791 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4795 /*FIXME the peephole pass should have killed this*/
4796 if (ins->dreg != ins->sreg1)
4797 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4800 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4803 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->dreg, ins->dreg);
4806 case OP_FCONV_TO_R8_X:
4807 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4808 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4811 case OP_XCONV_R8_TO_I4:
4812 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4813 switch (ins->backend.source_opcode) {
4814 case OP_FCONV_TO_I1:
4815 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4817 case OP_FCONV_TO_U1:
4818 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4820 case OP_FCONV_TO_I2:
4821 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4823 case OP_FCONV_TO_U2:
4824 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4830 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4831 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4832 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4833 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4834 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4835 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4838 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4839 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4840 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4843 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4844 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4847 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4848 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4849 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4852 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4853 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4854 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4858 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4861 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4864 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4867 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4870 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4873 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4876 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4879 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4883 case OP_LIVERANGE_START: {
4884 if (cfg->verbose_level > 1)
4885 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4886 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4889 case OP_LIVERANGE_END: {
4890 if (cfg->verbose_level > 1)
4891 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4892 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4895 case OP_GC_SAFE_POINT: {
4898 g_assert (mono_threads_is_coop_enabled ());
4900 x86_test_membase_imm (code, ins->sreg1, 0, 1);
4901 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4902 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
4903 x86_patch (br [0], code);
4907 case OP_GC_LIVENESS_DEF:
4908 case OP_GC_LIVENESS_USE:
4909 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4910 ins->backend.pc_offset = code - cfg->native_code;
4912 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4913 ins->backend.pc_offset = code - cfg->native_code;
4914 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4917 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
4920 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
4923 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4924 g_assert_not_reached ();
4927 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4928 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4929 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4930 g_assert_not_reached ();
4936 cfg->code_len = code - cfg->native_code;
4939 #endif /* DISABLE_JIT */
4942 mono_arch_register_lowlevel_calls (void)
4947 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
4949 unsigned char *ip = ji->ip.i + code;
4952 case MONO_PATCH_INFO_IP:
4953 *((gconstpointer *)(ip)) = target;
4955 case MONO_PATCH_INFO_ABS:
4956 case MONO_PATCH_INFO_METHOD:
4957 case MONO_PATCH_INFO_METHOD_JUMP:
4958 case MONO_PATCH_INFO_INTERNAL_METHOD:
4959 case MONO_PATCH_INFO_BB:
4960 case MONO_PATCH_INFO_LABEL:
4961 case MONO_PATCH_INFO_RGCTX_FETCH:
4962 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
4963 x86_patch (ip, (unsigned char*)target);
4965 case MONO_PATCH_INFO_NONE:
4967 case MONO_PATCH_INFO_R4:
4968 case MONO_PATCH_INFO_R8: {
4969 guint32 offset = mono_arch_get_patch_offset (ip);
4970 *((gconstpointer *)(ip + offset)) = target;
4974 guint32 offset = mono_arch_get_patch_offset (ip);
4975 *((gconstpointer *)(ip + offset)) = target;
4981 static G_GNUC_UNUSED void
4982 stack_unaligned (MonoMethod *m, gpointer caller)
4984 printf ("%s\n", mono_method_full_name (m, TRUE));
4985 g_assert_not_reached ();
4989 mono_arch_emit_prolog (MonoCompile *cfg)
4991 MonoMethod *method = cfg->method;
4993 MonoMethodSignature *sig;
4997 int alloc_size, pos, max_offset, i, cfa_offset;
4999 gboolean need_stack_frame;
5001 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5003 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5004 cfg->code_size += 512;
5006 code = cfg->native_code = g_malloc (cfg->code_size);
5012 /* Check that the stack is aligned on osx */
5013 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5014 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5015 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5017 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5018 x86_push_membase (code, X86_ESP, 0);
5019 x86_push_imm (code, cfg->method);
5020 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5021 x86_call_reg (code, X86_EAX);
5022 x86_patch (br [0], code);
5026 /* Offset between RSP and the CFA */
5030 cfa_offset = sizeof (gpointer);
5031 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5032 // IP saved at CFA - 4
5033 /* There is no IP reg on x86 */
5034 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5035 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5037 need_stack_frame = needs_stack_frame (cfg);
5039 if (need_stack_frame) {
5040 x86_push_reg (code, X86_EBP);
5041 cfa_offset += sizeof (gpointer);
5042 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5043 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5044 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5045 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5046 /* These are handled automatically by the stack marking code */
5047 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5049 cfg->frame_reg = X86_ESP;
5052 cfg->stack_offset += cfg->param_area;
5053 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5055 alloc_size = cfg->stack_offset;
5058 if (!method->save_lmf) {
5059 if (cfg->used_int_regs & (1 << X86_EBX)) {
5060 x86_push_reg (code, X86_EBX);
5062 cfa_offset += sizeof (gpointer);
5063 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5064 /* These are handled automatically by the stack marking code */
5065 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5068 if (cfg->used_int_regs & (1 << X86_EDI)) {
5069 x86_push_reg (code, X86_EDI);
5071 cfa_offset += sizeof (gpointer);
5072 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5073 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5076 if (cfg->used_int_regs & (1 << X86_ESI)) {
5077 x86_push_reg (code, X86_ESI);
5079 cfa_offset += sizeof (gpointer);
5080 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5081 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5087 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5088 if (mono_do_x86_stack_align && need_stack_frame) {
5089 int tot = alloc_size + pos + 4; /* ret ip */
5090 if (need_stack_frame)
5092 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5094 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5095 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5096 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5100 cfg->arch.sp_fp_offset = alloc_size + pos;
5103 /* See mono_emit_stack_alloc */
5104 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5105 guint32 remaining_size = alloc_size;
5106 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5107 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5108 guint32 offset = code - cfg->native_code;
5109 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5110 while (required_code_size >= (cfg->code_size - offset))
5111 cfg->code_size *= 2;
5112 cfg->native_code = mono_realloc_native_code(cfg);
5113 code = cfg->native_code + offset;
5114 cfg->stat_code_reallocs++;
5116 while (remaining_size >= 0x1000) {
5117 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5118 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5119 remaining_size -= 0x1000;
5122 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5124 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5127 g_assert (need_stack_frame);
5130 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5131 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5132 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5135 #if DEBUG_STACK_ALIGNMENT
5136 /* check the stack is aligned */
5137 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5138 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5139 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5140 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5141 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5142 x86_breakpoint (code);
5146 /* compute max_offset in order to use short forward jumps */
5148 if (cfg->opt & MONO_OPT_BRANCH) {
5149 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5151 bb->max_offset = max_offset;
5153 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5155 /* max alignment for loops */
5156 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5157 max_offset += LOOP_ALIGNMENT;
5158 MONO_BB_FOR_EACH_INS (bb, ins) {
5159 if (ins->opcode == OP_LABEL)
5160 ins->inst_c1 = max_offset;
5161 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5166 /* store runtime generic context */
5167 if (cfg->rgctx_var) {
5168 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5170 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5173 if (method->save_lmf)
5174 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5176 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5177 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5182 if (cfg->arch.ss_tramp_var) {
5183 /* Initialize ss_tramp_var */
5184 ins = cfg->arch.ss_tramp_var;
5185 g_assert (ins->opcode == OP_REGOFFSET);
5187 g_assert (!cfg->compile_aot);
5188 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&ss_trampoline, 4);
5191 if (cfg->arch.bp_tramp_var) {
5192 /* Initialize bp_tramp_var */
5193 ins = cfg->arch.bp_tramp_var;
5194 g_assert (ins->opcode == OP_REGOFFSET);
5196 g_assert (!cfg->compile_aot);
5197 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&bp_trampoline, 4);
5201 /* load arguments allocated to register from the stack */
5202 sig = mono_method_signature (method);
5205 cinfo = (CallInfo *)cfg->arch.cinfo;
5207 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5208 inst = cfg->args [pos];
5209 ainfo = &cinfo->args [pos];
5210 if (inst->opcode == OP_REGVAR) {
5211 g_assert (need_stack_frame);
5212 x86_mov_reg_membase (code, inst->dreg, X86_EBP, ainfo->offset + ARGS_OFFSET, 4);
5213 if (cfg->verbose_level > 2)
5214 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5219 cfg->code_len = code - cfg->native_code;
5221 g_assert (cfg->code_len < cfg->code_size);
5227 mono_arch_emit_epilog (MonoCompile *cfg)
5229 MonoMethod *method = cfg->method;
5230 MonoMethodSignature *sig = mono_method_signature (method);
5232 guint32 stack_to_pop;
5234 int max_epilog_size = 16;
5236 gboolean need_stack_frame = needs_stack_frame (cfg);
5238 if (cfg->method->save_lmf)
5239 max_epilog_size += 128;
5241 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5242 cfg->code_size *= 2;
5243 cfg->native_code = mono_realloc_native_code(cfg);
5244 cfg->stat_code_reallocs++;
5247 code = cfg->native_code + cfg->code_len;
5249 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5250 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5252 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5255 if (method->save_lmf) {
5256 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5259 /* check if we need to restore protection of the stack after a stack overflow */
5260 if (!cfg->compile_aot && mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_JIT_TLS) != -1) {
5261 code = mono_x86_emit_tls_get (code, X86_ECX, mono_tls_get_tls_offset (TLS_KEY_JIT_TLS));
5263 /* we load the value in a separate instruction: this mechanism may be
5264 * used later as a safer way to do thread interruption
5266 x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5267 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5269 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5270 /* note that the call trampoline will preserve eax/edx */
5271 x86_call_reg (code, X86_ECX);
5272 x86_patch (patch, code);
5275 /* restore caller saved regs */
5276 if (cfg->used_int_regs & (1 << X86_EBX)) {
5277 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5280 if (cfg->used_int_regs & (1 << X86_EDI)) {
5281 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5283 if (cfg->used_int_regs & (1 << X86_ESI)) {
5284 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5287 /* EBP is restored by LEAVE */
5289 for (i = 0; i < X86_NREG; ++i) {
5290 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5296 g_assert (need_stack_frame);
5297 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5301 g_assert (need_stack_frame);
5302 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5305 if (cfg->used_int_regs & (1 << X86_ESI)) {
5306 x86_pop_reg (code, X86_ESI);
5308 if (cfg->used_int_regs & (1 << X86_EDI)) {
5309 x86_pop_reg (code, X86_EDI);
5311 if (cfg->used_int_regs & (1 << X86_EBX)) {
5312 x86_pop_reg (code, X86_EBX);
5316 /* Load returned vtypes into registers if needed */
5317 cinfo = (CallInfo *)cfg->arch.cinfo;
5318 if (cinfo->ret.storage == ArgValuetypeInReg) {
5319 for (quad = 0; quad < 2; quad ++) {
5320 switch (cinfo->ret.pair_storage [quad]) {
5322 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5324 case ArgOnFloatFpStack:
5325 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5327 case ArgOnDoubleFpStack:
5328 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5333 g_assert_not_reached ();
5338 if (need_stack_frame)
5341 if (CALLCONV_IS_STDCALL (sig)) {
5342 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5344 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
5345 } else if (cinfo->callee_stack_pop)
5346 stack_to_pop = cinfo->callee_stack_pop;
5351 g_assert (need_stack_frame);
5352 x86_ret_imm (code, stack_to_pop);
5357 cfg->code_len = code - cfg->native_code;
5359 g_assert (cfg->code_len < cfg->code_size);
5363 mono_arch_emit_exceptions (MonoCompile *cfg)
5365 MonoJumpInfo *patch_info;
5368 MonoClass *exc_classes [16];
5369 guint8 *exc_throw_start [16], *exc_throw_end [16];
5373 /* Compute needed space */
5374 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5375 if (patch_info->type == MONO_PATCH_INFO_EXC)
5380 * make sure we have enough space for exceptions
5381 * 16 is the size of two push_imm instructions and a call
5383 if (cfg->compile_aot)
5384 code_size = exc_count * 32;
5386 code_size = exc_count * 16;
5388 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5389 cfg->code_size *= 2;
5390 cfg->native_code = mono_realloc_native_code(cfg);
5391 cfg->stat_code_reallocs++;
5394 code = cfg->native_code + cfg->code_len;
5397 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5398 switch (patch_info->type) {
5399 case MONO_PATCH_INFO_EXC: {
5400 MonoClass *exc_class;
5404 x86_patch (patch_info->ip.i + cfg->native_code, code);
5406 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5407 throw_ip = patch_info->ip.i;
5409 /* Find a throw sequence for the same exception class */
5410 for (i = 0; i < nthrows; ++i)
5411 if (exc_classes [i] == exc_class)
5414 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5415 x86_jump_code (code, exc_throw_start [i]);
5416 patch_info->type = MONO_PATCH_INFO_NONE;
5421 /* Compute size of code following the push <OFFSET> */
5424 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5426 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5427 /* Use the shorter form */
5429 x86_push_imm (code, 0);
5433 x86_push_imm (code, 0xf0f0f0f0);
5438 exc_classes [nthrows] = exc_class;
5439 exc_throw_start [nthrows] = code;
5442 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5443 patch_info->data.name = "mono_arch_throw_corlib_exception";
5444 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5445 patch_info->ip.i = code - cfg->native_code;
5446 x86_call_code (code, 0);
5447 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5452 exc_throw_end [nthrows] = code;
5464 cfg->code_len = code - cfg->native_code;
5466 g_assert (cfg->code_len < cfg->code_size);
5470 mono_arch_flush_icache (guint8 *code, gint size)
5476 mono_arch_flush_register_windows (void)
5481 mono_arch_is_inst_imm (gint64 imm)
5487 mono_arch_finish_init (void)
5489 if (!g_getenv ("MONO_NO_TLS")) {
5490 #ifndef TARGET_WIN32
5492 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5499 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5503 // Linear handler, the bsearch head compare is shorter
5504 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5505 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5506 // x86_patch(ins,target)
5507 //[1 + 5] x86_jump_mem(inst,mem)
5510 #define BR_SMALL_SIZE 2
5511 #define BR_LARGE_SIZE 5
5512 #define JUMP_IMM_SIZE 6
5513 #define ENABLE_WRONG_METHOD_CHECK 0
5517 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5519 int i, distance = 0;
5520 for (i = start; i < target; ++i)
5521 distance += imt_entries [i]->chunk_size;
5526 * LOCKING: called with the domain lock held
5529 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5530 gpointer fail_tramp)
5534 guint8 *code, *start;
5537 for (i = 0; i < count; ++i) {
5538 MonoIMTCheckItem *item = imt_entries [i];
5539 if (item->is_equals) {
5540 if (item->check_target_idx) {
5541 if (!item->compare_done)
5542 item->chunk_size += CMP_SIZE;
5543 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5546 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5548 item->chunk_size += JUMP_IMM_SIZE;
5549 #if ENABLE_WRONG_METHOD_CHECK
5550 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5555 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5556 imt_entries [item->check_target_idx]->compare_done = TRUE;
5558 size += item->chunk_size;
5561 code = mono_method_alloc_generic_virtual_trampoline (domain, size);
5563 code = mono_domain_code_reserve (domain, size);
5566 unwind_ops = mono_arch_get_cie_program ();
5568 for (i = 0; i < count; ++i) {
5569 MonoIMTCheckItem *item = imt_entries [i];
5570 item->code_target = code;
5571 if (item->is_equals) {
5572 if (item->check_target_idx) {
5573 if (!item->compare_done)
5574 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5575 item->jmp_code = code;
5576 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5577 if (item->has_target_code)
5578 x86_jump_code (code, item->value.target_code);
5580 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5583 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5584 item->jmp_code = code;
5585 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5586 if (item->has_target_code)
5587 x86_jump_code (code, item->value.target_code);
5589 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5590 x86_patch (item->jmp_code, code);
5591 x86_jump_code (code, fail_tramp);
5592 item->jmp_code = NULL;
5594 /* enable the commented code to assert on wrong method */
5595 #if ENABLE_WRONG_METHOD_CHECK
5596 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5597 item->jmp_code = code;
5598 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5600 if (item->has_target_code)
5601 x86_jump_code (code, item->value.target_code);
5603 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5604 #if ENABLE_WRONG_METHOD_CHECK
5605 x86_patch (item->jmp_code, code);
5606 x86_breakpoint (code);
5607 item->jmp_code = NULL;
5612 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5613 item->jmp_code = code;
5614 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5615 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5617 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5620 /* patch the branches to get to the target items */
5621 for (i = 0; i < count; ++i) {
5622 MonoIMTCheckItem *item = imt_entries [i];
5623 if (item->jmp_code) {
5624 if (item->check_target_idx) {
5625 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5631 mono_stats.imt_trampolines_size += code - start;
5632 g_assert (code - start <= size);
5636 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5637 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5641 if (mono_jit_map_is_enabled ()) {
5644 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5646 buff = g_strdup_printf ("imt_trampoline_entries_%d", count);
5647 mono_emit_jit_tramp (start, code - start, buff);
5651 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
5653 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
5659 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5661 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5665 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5667 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5671 mono_arch_get_cie_program (void)
5675 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5676 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5682 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5684 MonoInst *ins = NULL;
5687 if (cmethod->klass == mono_defaults.math_class) {
5688 if (strcmp (cmethod->name, "Sin") == 0) {
5690 } else if (strcmp (cmethod->name, "Cos") == 0) {
5692 } else if (strcmp (cmethod->name, "Tan") == 0) {
5694 } else if (strcmp (cmethod->name, "Atan") == 0) {
5696 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5698 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5700 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5704 if (opcode && fsig->param_count == 1) {
5705 MONO_INST_NEW (cfg, ins, opcode);
5706 ins->type = STACK_R8;
5707 ins->dreg = mono_alloc_freg (cfg);
5708 ins->sreg1 = args [0]->dreg;
5709 MONO_ADD_INS (cfg->cbb, ins);
5712 if (cfg->opt & MONO_OPT_CMOV) {
5715 if (strcmp (cmethod->name, "Min") == 0) {
5716 if (fsig->params [0]->type == MONO_TYPE_I4)
5718 } else if (strcmp (cmethod->name, "Max") == 0) {
5719 if (fsig->params [0]->type == MONO_TYPE_I4)
5723 if (opcode && fsig->param_count == 2) {
5724 MONO_INST_NEW (cfg, ins, opcode);
5725 ins->type = STACK_I4;
5726 ins->dreg = mono_alloc_ireg (cfg);
5727 ins->sreg1 = args [0]->dreg;
5728 ins->sreg2 = args [1]->dreg;
5729 MONO_ADD_INS (cfg->cbb, ins);
5734 /* OP_FREM is not IEEE compatible */
5735 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
5736 MONO_INST_NEW (cfg, ins, OP_FREM);
5737 ins->inst_i0 = args [0];
5738 ins->inst_i1 = args [1];
5747 mono_arch_print_tree (MonoInst *tree, int arity)
5753 mono_arch_get_patch_offset (guint8 *code)
5755 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5757 else if (code [0] == 0xba)
5759 else if (code [0] == 0x68)
5762 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5763 /* push <OFFSET>(<REG>) */
5765 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5766 /* call *<OFFSET>(<REG>) */
5768 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5771 else if ((code [0] == 0x58) && (code [1] == 0x05))
5772 /* pop %eax; add <OFFSET>, %eax */
5774 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5775 /* pop <REG>; add <OFFSET>, <REG> */
5777 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5778 /* mov <REG>, imm */
5781 g_assert_not_reached ();
5787 * mono_breakpoint_clean_code:
5789 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5790 * breakpoints in the original code, they are removed in the copy.
5792 * Returns TRUE if no sw breakpoint was present.
5795 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5798 * If method_start is non-NULL we need to perform bound checks, since we access memory
5799 * at code - offset we could go before the start of the method and end up in a different
5800 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5803 if (!method_start || code - offset >= method_start) {
5804 memcpy (buf, code - offset, size);
5806 int diff = code - method_start;
5807 memset (buf, 0, size);
5808 memcpy (buf + offset - diff, method_start, diff + size - offset);
5814 * mono_x86_get_this_arg_offset:
5816 * Return the offset of the stack location where this is passed during a virtual
5820 mono_x86_get_this_arg_offset (MonoMethodSignature *sig)
5826 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
5828 guint32 esp = regs [X86_ESP];
5835 * The stack looks like:
5839 res = ((MonoObject**)esp) [0];
5843 #define MAX_ARCH_DELEGATE_PARAMS 10
5846 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
5848 guint8 *code, *start;
5849 int code_reserve = 64;
5852 unwind_ops = mono_arch_get_cie_program ();
5855 * The stack contains:
5861 start = code = mono_global_codeman_reserve (code_reserve);
5863 /* Replace the this argument with the target */
5864 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5865 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
5866 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5867 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
5869 g_assert ((code - start) < code_reserve);
5872 /* 8 for mov_reg and jump, plus 8 for each parameter */
5873 code_reserve = 8 + (param_count * 8);
5875 * The stack contains:
5876 * <args in reverse order>
5881 * <args in reverse order>
5884 * without unbalancing the stack.
5885 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
5886 * and leaving original spot of first arg as placeholder in stack so
5887 * when callee pops stack everything works.
5890 start = code = mono_global_codeman_reserve (code_reserve);
5892 /* store delegate for access to method_ptr */
5893 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
5896 for (i = 0; i < param_count; ++i) {
5897 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
5898 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
5901 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
5903 g_assert ((code - start) < code_reserve);
5907 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
5909 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
5910 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
5914 if (mono_jit_map_is_enabled ()) {
5917 buff = (char*)"delegate_invoke_has_target";
5919 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
5920 mono_emit_jit_tramp (start, code - start, buff);
5924 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
5929 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
5932 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
5934 guint8 *code, *start;
5939 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
5943 * The stack contains:
5947 start = code = mono_global_codeman_reserve (size);
5949 unwind_ops = mono_arch_get_cie_program ();
5951 /* Replace the this argument with the target */
5952 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5953 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
5954 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5957 /* Load the IMT reg */
5958 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
5961 /* Load the vtable */
5962 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
5963 x86_jump_membase (code, X86_EAX, offset);
5964 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
5966 tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
5967 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
5968 g_free (tramp_name);
5975 mono_arch_get_delegate_invoke_impls (void)
5978 MonoTrampInfo *info;
5981 get_delegate_invoke_impl (&info, TRUE, 0);
5982 res = g_slist_prepend (res, info);
5984 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
5985 get_delegate_invoke_impl (&info, FALSE, i);
5986 res = g_slist_prepend (res, info);
5989 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
5990 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
5991 res = g_slist_prepend (res, info);
5993 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
5994 res = g_slist_prepend (res, info);
6001 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6003 guint8 *code, *start;
6005 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6008 /* FIXME: Support more cases */
6009 if (MONO_TYPE_ISSTRUCT (sig->ret))
6013 * The stack contains:
6019 static guint8* cached = NULL;
6023 if (mono_aot_only) {
6024 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6026 MonoTrampInfo *info;
6027 start = get_delegate_invoke_impl (&info, TRUE, 0);
6028 mono_tramp_info_register (info, NULL);
6031 mono_memory_barrier ();
6035 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6038 for (i = 0; i < sig->param_count; ++i)
6039 if (!mono_is_regsize_var (sig->params [i]))
6042 code = cache [sig->param_count];
6046 if (mono_aot_only) {
6047 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6048 start = mono_aot_get_trampoline (name);
6051 MonoTrampInfo *info;
6052 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
6053 mono_tramp_info_register (info, NULL);
6056 mono_memory_barrier ();
6058 cache [sig->param_count] = start;
6065 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
6067 MonoTrampInfo *info;
6070 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
6072 mono_tramp_info_register (info, NULL);
6077 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6080 case X86_EAX: return ctx->eax;
6081 case X86_EBX: return ctx->ebx;
6082 case X86_ECX: return ctx->ecx;
6083 case X86_EDX: return ctx->edx;
6084 case X86_ESP: return ctx->esp;
6085 case X86_EBP: return ctx->ebp;
6086 case X86_ESI: return ctx->esi;
6087 case X86_EDI: return ctx->edi;
6089 g_assert_not_reached ();
6095 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6123 g_assert_not_reached ();
6127 #ifdef MONO_ARCH_SIMD_INTRINSICS
6130 get_float_to_x_spill_area (MonoCompile *cfg)
6132 if (!cfg->fconv_to_r8_x_var) {
6133 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6134 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6136 return cfg->fconv_to_r8_x_var;
6140 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6143 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6146 int dreg, src_opcode;
6148 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6151 switch (src_opcode = ins->opcode) {
6152 case OP_FCONV_TO_I1:
6153 case OP_FCONV_TO_U1:
6154 case OP_FCONV_TO_I2:
6155 case OP_FCONV_TO_U2:
6156 case OP_FCONV_TO_I4:
6163 /* dreg is the IREG and sreg1 is the FREG */
6164 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6165 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6166 fconv->sreg1 = ins->sreg1;
6167 fconv->dreg = mono_alloc_ireg (cfg);
6168 fconv->type = STACK_VTYPE;
6169 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6171 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6175 ins->opcode = OP_XCONV_R8_TO_I4;
6177 ins->klass = mono_defaults.int32_class;
6178 ins->sreg1 = fconv->dreg;
6180 ins->type = STACK_I4;
6181 ins->backend.source_opcode = src_opcode;
6184 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6187 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6192 if (long_ins->opcode == OP_LNEG) {
6194 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
6195 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
6196 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->dreg));
6201 #ifdef MONO_ARCH_SIMD_INTRINSICS
6203 if (!(cfg->opt & MONO_OPT_SIMD))
6206 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6207 switch (long_ins->opcode) {
6209 vreg = long_ins->sreg1;
6211 if (long_ins->inst_c0) {
6212 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6213 ins->klass = long_ins->klass;
6214 ins->sreg1 = long_ins->sreg1;
6216 ins->type = STACK_VTYPE;
6217 ins->dreg = vreg = alloc_ireg (cfg);
6218 MONO_ADD_INS (cfg->cbb, ins);
6221 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6222 ins->klass = mono_defaults.int32_class;
6224 ins->type = STACK_I4;
6225 ins->dreg = MONO_LVREG_LS (long_ins->dreg);
6226 MONO_ADD_INS (cfg->cbb, ins);
6228 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6229 ins->klass = long_ins->klass;
6230 ins->sreg1 = long_ins->sreg1;
6231 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6232 ins->type = STACK_VTYPE;
6233 ins->dreg = vreg = alloc_ireg (cfg);
6234 MONO_ADD_INS (cfg->cbb, ins);
6236 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6237 ins->klass = mono_defaults.int32_class;
6239 ins->type = STACK_I4;
6240 ins->dreg = MONO_LVREG_MS (long_ins->dreg);
6241 MONO_ADD_INS (cfg->cbb, ins);
6243 long_ins->opcode = OP_NOP;
6245 case OP_INSERTX_I8_SLOW:
6246 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6247 ins->dreg = long_ins->dreg;
6248 ins->sreg1 = long_ins->dreg;
6249 ins->sreg2 = MONO_LVREG_LS (long_ins->sreg2);
6250 ins->inst_c0 = long_ins->inst_c0 * 2;
6251 MONO_ADD_INS (cfg->cbb, ins);
6253 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6254 ins->dreg = long_ins->dreg;
6255 ins->sreg1 = long_ins->dreg;
6256 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg2);
6257 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6258 MONO_ADD_INS (cfg->cbb, ins);
6260 long_ins->opcode = OP_NOP;
6263 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6264 ins->dreg = long_ins->dreg;
6265 ins->sreg1 = MONO_LVREG_LS (long_ins->sreg1);
6266 ins->klass = long_ins->klass;
6267 ins->type = STACK_VTYPE;
6268 MONO_ADD_INS (cfg->cbb, ins);
6270 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6271 ins->dreg = long_ins->dreg;
6272 ins->sreg1 = long_ins->dreg;
6273 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg1);
6275 ins->klass = long_ins->klass;
6276 ins->type = STACK_VTYPE;
6277 MONO_ADD_INS (cfg->cbb, ins);
6279 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6280 ins->dreg = long_ins->dreg;
6281 ins->sreg1 = long_ins->dreg;;
6282 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6283 ins->klass = long_ins->klass;
6284 ins->type = STACK_VTYPE;
6285 MONO_ADD_INS (cfg->cbb, ins);
6287 long_ins->opcode = OP_NOP;
6290 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6293 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6295 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6298 gpointer *sp, old_value;
6301 offset = clause->exvar_offset;
6304 bp = MONO_CONTEXT_GET_BP (ctx);
6305 sp = *(gpointer*)(bp + offset);
6308 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6317 * mono_aot_emit_load_got_addr:
6319 * Emit code to load the got address.
6320 * On x86, the result is placed into EBX.
6323 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6325 x86_call_imm (code, 0);
6327 * The patch needs to point to the pop, since the GOT offset needs
6328 * to be added to that address.
6331 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6333 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6334 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6335 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6341 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6344 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6346 g_assert_not_reached ();
6347 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6352 * mono_arch_emit_load_aotconst:
6354 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6355 * TARGET from the mscorlib GOT in full-aot code.
6356 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6360 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
6362 /* Load the mscorlib got address */
6363 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6364 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6365 /* arch_emit_got_access () patches this */
6366 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6371 /* Can't put this into mini-x86.h */
6373 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6376 mono_arch_get_trampolines (gboolean aot)
6378 MonoTrampInfo *info;
6379 GSList *tramps = NULL;
6381 mono_x86_get_signal_exception_trampoline (&info, aot);
6383 tramps = g_slist_append (tramps, info);
6388 /* Soft Debug support */
6389 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6392 * mono_arch_set_breakpoint:
6394 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6395 * The location should contain code emitted by OP_SEQ_POINT.
6398 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6400 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6402 g_assert (code [0] == 0x90);
6403 x86_call_membase (code, X86_ECX, 0);
6407 * mono_arch_clear_breakpoint:
6409 * Clear the breakpoint at IP.
6412 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6414 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6417 for (i = 0; i < 2; ++i)
6422 * mono_arch_start_single_stepping:
6424 * Start single stepping.
6427 mono_arch_start_single_stepping (void)
6429 ss_trampoline = mini_get_single_step_trampoline ();
6433 * mono_arch_stop_single_stepping:
6435 * Stop single stepping.
6438 mono_arch_stop_single_stepping (void)
6440 ss_trampoline = NULL;
6444 * mono_arch_is_single_step_event:
6446 * Return whenever the machine state in SIGCTX corresponds to a single
6450 mono_arch_is_single_step_event (void *info, void *sigctx)
6452 /* We use soft breakpoints */
6457 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6459 /* We use soft breakpoints */
6463 #define BREAKPOINT_SIZE 2
6466 * mono_arch_skip_breakpoint:
6468 * See mini-amd64.c for docs.
6471 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6473 g_assert_not_reached ();
6477 * mono_arch_skip_single_step:
6479 * See mini-amd64.c for docs.
6482 mono_arch_skip_single_step (MonoContext *ctx)
6484 g_assert_not_reached ();
6488 * mono_arch_get_seq_point_info:
6490 * See mini-amd64.c for docs.
6493 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6500 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6502 ext->lmf.previous_lmf = (gsize)prev_lmf;
6503 /* Mark that this is a MonoLMFExt */
6504 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6505 ext->lmf.ebp = (gssize)ext;
6511 mono_arch_opcode_supported (int opcode)
6514 case OP_ATOMIC_ADD_I4:
6515 case OP_ATOMIC_EXCHANGE_I4:
6516 case OP_ATOMIC_CAS_I4:
6517 case OP_ATOMIC_LOAD_I1:
6518 case OP_ATOMIC_LOAD_I2:
6519 case OP_ATOMIC_LOAD_I4:
6520 case OP_ATOMIC_LOAD_U1:
6521 case OP_ATOMIC_LOAD_U2:
6522 case OP_ATOMIC_LOAD_U4:
6523 case OP_ATOMIC_LOAD_R4:
6524 case OP_ATOMIC_LOAD_R8:
6525 case OP_ATOMIC_STORE_I1:
6526 case OP_ATOMIC_STORE_I2:
6527 case OP_ATOMIC_STORE_I4:
6528 case OP_ATOMIC_STORE_U1:
6529 case OP_ATOMIC_STORE_U2:
6530 case OP_ATOMIC_STORE_U4:
6531 case OP_ATOMIC_STORE_R4:
6532 case OP_ATOMIC_STORE_R8:
6540 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
6542 return get_call_info (mp, sig);