2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/appdomain.h>
21 #include <mono/metadata/debug-helpers.h>
22 #include <mono/metadata/threads.h>
23 #include <mono/metadata/profiler-private.h>
24 #include <mono/metadata/mono-debug.h>
25 #include <mono/metadata/gc-internal.h>
26 #include <mono/utils/mono-math.h>
27 #include <mono/utils/mono-counters.h>
28 #include <mono/utils/mono-mmap.h>
29 #include <mono/utils/mono-memory-model.h>
30 #include <mono/utils/mono-hwcap-x86.h>
38 /* On windows, these hold the key returned by TlsAlloc () */
39 static gint lmf_tls_offset = -1;
40 static gint jit_tls_offset = -1;
42 static gint lmf_addr_tls_offset = -1;
44 static gint appdomain_tls_offset = -1;
47 static gboolean optimize_for_xen = TRUE;
49 #define optimize_for_xen 0
53 static gboolean is_win32 = TRUE;
55 static gboolean is_win32 = FALSE;
58 /* This mutex protects architecture specific caches */
59 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
60 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
61 static CRITICAL_SECTION mini_arch_mutex;
63 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
68 /* Under windows, the default pinvoke calling convention is stdcall */
69 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT))
71 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL)
74 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
77 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
80 #ifdef __native_client_codegen__
82 /* Default alignment for Native Client is 32-byte. */
83 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
85 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
86 /* Check that alignment doesn't cross an alignment boundary. */
88 mono_arch_nacl_pad (guint8 *code, int pad)
90 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
92 if (pad == 0) return code;
93 /* assertion: alignment cannot cross a block boundary */
94 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
95 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
96 while (pad >= kMaxPadding) {
97 x86_padding (code, kMaxPadding);
100 if (pad != 0) x86_padding (code, pad);
105 mono_arch_nacl_skip_nops (guint8 *code)
107 x86_skip_nops (code);
111 #endif /* __native_client_codegen__ */
114 * The code generated for sequence points reads from this location, which is
115 * made read-only when single stepping is enabled.
117 static gpointer ss_trigger_page;
119 /* Enabled breakpoints read from this trigger page */
120 static gpointer bp_trigger_page;
123 mono_arch_regname (int reg)
126 case X86_EAX: return "%eax";
127 case X86_EBX: return "%ebx";
128 case X86_ECX: return "%ecx";
129 case X86_EDX: return "%edx";
130 case X86_ESP: return "%esp";
131 case X86_EBP: return "%ebp";
132 case X86_EDI: return "%edi";
133 case X86_ESI: return "%esi";
139 mono_arch_fregname (int reg)
164 mono_arch_xregname (int reg)
189 mono_x86_patch (unsigned char* code, gpointer target)
191 x86_patch (code, (unsigned char*)target);
202 /* gsharedvt argument passed by addr */
214 /* Only if storage == ArgValuetypeInReg */
215 ArgStorage pair_storage [2];
224 gboolean need_stack_align;
225 guint32 stack_align_amount;
226 gboolean vtype_retaddr;
227 /* The index of the vret arg in the argument list */
237 #define FLOAT_PARAM_REGS 0
239 static X86_Reg_No param_regs [] = { 0 };
241 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
242 #define SMALL_STRUCTS_IN_REGS
243 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
247 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
249 ainfo->offset = *stack_size;
251 if (*gr >= PARAM_REGS) {
252 ainfo->storage = ArgOnStack;
254 (*stack_size) += sizeof (gpointer);
257 ainfo->storage = ArgInIReg;
258 ainfo->reg = param_regs [*gr];
264 add_general_pair (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
266 ainfo->offset = *stack_size;
268 g_assert (PARAM_REGS == 0);
270 ainfo->storage = ArgOnStack;
271 (*stack_size) += sizeof (gpointer) * 2;
276 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
278 ainfo->offset = *stack_size;
280 if (*gr >= FLOAT_PARAM_REGS) {
281 ainfo->storage = ArgOnStack;
282 (*stack_size) += is_double ? 8 : 4;
283 ainfo->nslots = is_double ? 2 : 1;
286 /* A double register */
288 ainfo->storage = ArgInDoubleSSEReg;
290 ainfo->storage = ArgInFloatSSEReg;
298 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
300 guint32 *gr, guint32 *fr, guint32 *stack_size)
305 klass = mono_class_from_mono_type (type);
306 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
308 #ifdef SMALL_STRUCTS_IN_REGS
309 if (sig->pinvoke && is_return) {
310 MonoMarshalType *info;
313 * the exact rules are not very well documented, the code below seems to work with the
314 * code generated by gcc 3.3.3 -mno-cygwin.
316 info = mono_marshal_load_type_info (klass);
319 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
321 /* Special case structs with only a float member */
322 if ((info->native_size == 8) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R8)) {
323 ainfo->storage = ArgValuetypeInReg;
324 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
327 if ((info->native_size == 4) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R4)) {
328 ainfo->storage = ArgValuetypeInReg;
329 ainfo->pair_storage [0] = ArgOnFloatFpStack;
332 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
333 ainfo->storage = ArgValuetypeInReg;
334 ainfo->pair_storage [0] = ArgInIReg;
335 ainfo->pair_regs [0] = return_regs [0];
336 if (info->native_size > 4) {
337 ainfo->pair_storage [1] = ArgInIReg;
338 ainfo->pair_regs [1] = return_regs [1];
345 ainfo->offset = *stack_size;
346 ainfo->storage = ArgOnStack;
347 *stack_size += ALIGN_TO (size, sizeof (gpointer));
348 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
354 * Obtain information about a call according to the calling convention.
355 * For x86 ELF, see the "System V Application Binary Interface Intel386
356 * Architecture Processor Supplment, Fourth Edition" document for more
358 * For x86 win32, see ???.
361 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
363 guint32 i, gr, fr, pstart;
365 int n = sig->hasthis + sig->param_count;
366 guint32 stack_size = 0;
367 gboolean is_pinvoke = sig->pinvoke;
375 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
376 switch (ret_type->type) {
377 case MONO_TYPE_BOOLEAN:
388 case MONO_TYPE_FNPTR:
389 case MONO_TYPE_CLASS:
390 case MONO_TYPE_OBJECT:
391 case MONO_TYPE_SZARRAY:
392 case MONO_TYPE_ARRAY:
393 case MONO_TYPE_STRING:
394 cinfo->ret.storage = ArgInIReg;
395 cinfo->ret.reg = X86_EAX;
399 cinfo->ret.storage = ArgInIReg;
400 cinfo->ret.reg = X86_EAX;
401 cinfo->ret.is_pair = TRUE;
404 cinfo->ret.storage = ArgOnFloatFpStack;
407 cinfo->ret.storage = ArgOnDoubleFpStack;
409 case MONO_TYPE_GENERICINST:
410 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
411 cinfo->ret.storage = ArgInIReg;
412 cinfo->ret.reg = X86_EAX;
415 if (mini_is_gsharedvt_type_gsctx (gsctx, ret_type)) {
416 cinfo->ret.storage = ArgOnStack;
417 cinfo->vtype_retaddr = TRUE;
421 case MONO_TYPE_VALUETYPE:
422 case MONO_TYPE_TYPEDBYREF: {
423 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
425 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
426 if (cinfo->ret.storage == ArgOnStack) {
427 cinfo->vtype_retaddr = TRUE;
428 /* The caller passes the address where the value is stored */
434 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ret_type));
435 cinfo->ret.storage = ArgOnStack;
436 cinfo->vtype_retaddr = TRUE;
439 cinfo->ret.storage = ArgNone;
442 g_error ("Can't handle as return value 0x%x", sig->ret->type);
448 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
449 * the first argument, allowing 'this' to be always passed in the first arg reg.
450 * Also do this if the first argument is a reference type, since virtual calls
451 * are sometimes made using calli without sig->hasthis set, like in the delegate
454 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
456 add_general (&gr, &stack_size, cinfo->args + 0);
458 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
461 cinfo->vret_arg_offset = stack_size;
462 add_general (&gr, &stack_size, &cinfo->ret);
463 cinfo->vret_arg_index = 1;
467 add_general (&gr, &stack_size, cinfo->args + 0);
469 if (cinfo->vtype_retaddr)
470 add_general (&gr, &stack_size, &cinfo->ret);
473 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
475 fr = FLOAT_PARAM_REGS;
477 /* Emit the signature cookie just before the implicit arguments */
478 add_general (&gr, &stack_size, &cinfo->sig_cookie);
481 for (i = pstart; i < sig->param_count; ++i) {
482 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
485 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
486 /* We allways pass the sig cookie on the stack for simplicity */
488 * Prevent implicit arguments + the sig cookie from being passed
492 fr = FLOAT_PARAM_REGS;
494 /* Emit the signature cookie just before the implicit arguments */
495 add_general (&gr, &stack_size, &cinfo->sig_cookie);
498 if (sig->params [i]->byref) {
499 add_general (&gr, &stack_size, ainfo);
502 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
503 switch (ptype->type) {
504 case MONO_TYPE_BOOLEAN:
507 add_general (&gr, &stack_size, ainfo);
512 add_general (&gr, &stack_size, ainfo);
516 add_general (&gr, &stack_size, ainfo);
521 case MONO_TYPE_FNPTR:
522 case MONO_TYPE_CLASS:
523 case MONO_TYPE_OBJECT:
524 case MONO_TYPE_STRING:
525 case MONO_TYPE_SZARRAY:
526 case MONO_TYPE_ARRAY:
527 add_general (&gr, &stack_size, ainfo);
529 case MONO_TYPE_GENERICINST:
530 if (!mono_type_generic_inst_is_valuetype (ptype)) {
531 add_general (&gr, &stack_size, ainfo);
534 if (mini_is_gsharedvt_type_gsctx (gsctx, ptype)) {
535 /* gsharedvt arguments are passed by ref */
536 add_general (&gr, &stack_size, ainfo);
537 g_assert (ainfo->storage == ArgOnStack);
538 ainfo->storage = ArgGSharedVt;
542 case MONO_TYPE_VALUETYPE:
543 case MONO_TYPE_TYPEDBYREF:
544 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
548 add_general_pair (&gr, &stack_size, ainfo);
551 add_float (&fr, &stack_size, ainfo, FALSE);
554 add_float (&fr, &stack_size, ainfo, TRUE);
558 /* gsharedvt arguments are passed by ref */
559 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ptype));
560 add_general (&gr, &stack_size, ainfo);
561 g_assert (ainfo->storage == ArgOnStack);
562 ainfo->storage = ArgGSharedVt;
565 g_error ("unexpected type 0x%x", ptype->type);
566 g_assert_not_reached ();
570 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
572 fr = FLOAT_PARAM_REGS;
574 /* Emit the signature cookie just before the implicit arguments */
575 add_general (&gr, &stack_size, &cinfo->sig_cookie);
578 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
579 cinfo->need_stack_align = TRUE;
580 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
581 stack_size += cinfo->stack_align_amount;
584 cinfo->stack_usage = stack_size;
585 cinfo->reg_usage = gr;
586 cinfo->freg_usage = fr;
591 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
593 int n = sig->hasthis + sig->param_count;
597 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
599 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
601 return get_call_info_internal (gsctx, cinfo, sig);
605 * mono_arch_get_argument_info:
606 * @csig: a method signature
607 * @param_count: the number of parameters to consider
608 * @arg_info: an array to store the result infos
610 * Gathers information on parameters such as size, alignment and
611 * padding. arg_info should be large enought to hold param_count + 1 entries.
613 * Returns the size of the argument area on the stack.
614 * This should be signal safe, since it is called from
615 * mono_arch_find_jit_info ().
616 * FIXME: The metadata calls might not be signal safe.
619 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
621 int len, k, args_size = 0;
627 /* Avoid g_malloc as it is not signal safe */
628 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
629 cinfo = (CallInfo*)g_newa (guint8*, len);
630 memset (cinfo, 0, len);
632 cinfo = get_call_info_internal (gsctx, cinfo, csig);
634 arg_info [0].offset = offset;
636 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
637 args_size += sizeof (gpointer);
642 args_size += sizeof (gpointer);
646 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
647 /* Emitted after this */
648 args_size += sizeof (gpointer);
652 arg_info [0].size = args_size;
654 for (k = 0; k < param_count; k++) {
655 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
657 /* ignore alignment for now */
660 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
661 arg_info [k].pad = pad;
663 arg_info [k + 1].pad = 0;
664 arg_info [k + 1].size = size;
666 arg_info [k + 1].offset = offset;
669 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
670 /* Emitted after the first arg */
671 args_size += sizeof (gpointer);
676 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
677 align = MONO_ARCH_FRAME_ALIGNMENT;
680 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
681 arg_info [k].pad = pad;
687 mono_x86_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
692 c1 = get_call_info (NULL, NULL, caller_sig);
693 c2 = get_call_info (NULL, NULL, callee_sig);
694 res = c1->stack_usage >= c2->stack_usage;
695 if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
696 /* An address on the callee's stack is passed as the first argument */
706 * Initialize the cpu to execute managed code.
709 mono_arch_cpu_init (void)
711 /* spec compliance requires running with double precision */
715 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
716 fpcw &= ~X86_FPCW_PRECC_MASK;
717 fpcw |= X86_FPCW_PREC_DOUBLE;
718 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
719 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
721 _control87 (_PC_53, MCW_PC);
726 * Initialize architecture specific code.
729 mono_arch_init (void)
731 InitializeCriticalSection (&mini_arch_mutex);
733 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
734 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
735 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
737 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
738 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
739 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
740 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
745 * Cleanup architecture specific code.
748 mono_arch_cleanup (void)
751 mono_vfree (ss_trigger_page, mono_pagesize ());
753 mono_vfree (bp_trigger_page, mono_pagesize ());
754 DeleteCriticalSection (&mini_arch_mutex);
758 * This function returns the optimizations supported on this cpu.
761 mono_arch_cpu_optimizations (guint32 *exclude_mask)
763 #if !defined(__native_client__)
768 if (mono_hwcap_x86_has_cmov) {
769 opts |= MONO_OPT_CMOV;
771 if (mono_hwcap_x86_has_fcmov)
772 opts |= MONO_OPT_FCMOV;
774 *exclude_mask |= MONO_OPT_FCMOV;
776 *exclude_mask |= MONO_OPT_CMOV;
779 if (mono_hwcap_x86_has_sse2)
780 opts |= MONO_OPT_SSE2;
782 *exclude_mask |= MONO_OPT_SSE2;
784 #ifdef MONO_ARCH_SIMD_INTRINSICS
785 /*SIMD intrinsics require at least SSE2.*/
786 if (!mono_hwcap_x86_has_sse2)
787 *exclude_mask |= MONO_OPT_SIMD;
792 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
797 * This function test for all SSE functions supported.
799 * Returns a bitmask corresponding to all supported versions.
803 mono_arch_cpu_enumerate_simd_versions (void)
805 guint32 sse_opts = 0;
807 if (mono_hwcap_x86_has_sse1)
808 sse_opts |= SIMD_VERSION_SSE1;
810 if (mono_hwcap_x86_has_sse2)
811 sse_opts |= SIMD_VERSION_SSE2;
813 if (mono_hwcap_x86_has_sse3)
814 sse_opts |= SIMD_VERSION_SSE3;
816 if (mono_hwcap_x86_has_ssse3)
817 sse_opts |= SIMD_VERSION_SSSE3;
819 if (mono_hwcap_x86_has_sse41)
820 sse_opts |= SIMD_VERSION_SSE41;
822 if (mono_hwcap_x86_has_sse42)
823 sse_opts |= SIMD_VERSION_SSE42;
825 if (mono_hwcap_x86_has_sse4a)
826 sse_opts |= SIMD_VERSION_SSE4a;
832 * Determine whenever the trap whose info is in SIGINFO is caused by
836 mono_arch_is_int_overflow (void *sigctx, void *info)
841 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
843 ip = (guint8*)ctx.eip;
845 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
849 switch (x86_modrm_rm (ip [1])) {
869 g_assert_not_reached ();
881 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
886 for (i = 0; i < cfg->num_varinfo; i++) {
887 MonoInst *ins = cfg->varinfo [i];
888 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
891 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
894 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
895 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
898 /* we dont allocate I1 to registers because there is no simply way to sign extend
899 * 8bit quantities in caller saved registers on x86 */
900 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
901 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
902 g_assert (i == vmv->idx);
903 vars = g_list_prepend (vars, vmv);
907 vars = mono_varlist_sort (cfg, vars, 0);
913 mono_arch_get_global_int_regs (MonoCompile *cfg)
917 /* we can use 3 registers for global allocation */
918 regs = g_list_prepend (regs, (gpointer)X86_EBX);
919 regs = g_list_prepend (regs, (gpointer)X86_ESI);
920 regs = g_list_prepend (regs, (gpointer)X86_EDI);
926 * mono_arch_regalloc_cost:
928 * Return the cost, in number of memory references, of the action of
929 * allocating the variable VMV into a register during global register
933 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
935 MonoInst *ins = cfg->varinfo [vmv->idx];
937 if (cfg->method->save_lmf)
938 /* The register is already saved */
939 return (ins->opcode == OP_ARG) ? 1 : 0;
941 /* push+pop+possible load if it is an argument */
942 return (ins->opcode == OP_ARG) ? 3 : 2;
946 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
948 static int inited = FALSE;
949 static int count = 0;
951 if (cfg->arch.need_stack_frame_inited) {
952 g_assert (cfg->arch.need_stack_frame == flag);
956 cfg->arch.need_stack_frame = flag;
957 cfg->arch.need_stack_frame_inited = TRUE;
963 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
968 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
972 needs_stack_frame (MonoCompile *cfg)
974 MonoMethodSignature *sig;
975 MonoMethodHeader *header;
976 gboolean result = FALSE;
978 #if defined(__APPLE__)
979 /*OSX requires stack frame code to have the correct alignment. */
983 if (cfg->arch.need_stack_frame_inited)
984 return cfg->arch.need_stack_frame;
986 header = cfg->header;
987 sig = mono_method_signature (cfg->method);
989 if (cfg->disable_omit_fp)
991 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
993 else if (cfg->method->save_lmf)
995 else if (cfg->stack_offset)
997 else if (cfg->param_area)
999 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1001 else if (header->num_clauses)
1003 else if (sig->param_count + sig->hasthis)
1005 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1007 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1008 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1011 set_needs_stack_frame (cfg, result);
1013 return cfg->arch.need_stack_frame;
1017 * Set var information according to the calling convention. X86 version.
1018 * The locals var stuff should most likely be split in another method.
1021 mono_arch_allocate_vars (MonoCompile *cfg)
1023 MonoMethodSignature *sig;
1024 MonoMethodHeader *header;
1026 guint32 locals_stack_size, locals_stack_align;
1031 header = cfg->header;
1032 sig = mono_method_signature (cfg->method);
1034 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1036 cfg->frame_reg = X86_EBP;
1039 /* Reserve space to save LMF and caller saved registers */
1041 if (cfg->method->save_lmf) {
1042 offset += sizeof (MonoLMF);
1044 if (cfg->used_int_regs & (1 << X86_EBX)) {
1048 if (cfg->used_int_regs & (1 << X86_EDI)) {
1052 if (cfg->used_int_regs & (1 << X86_ESI)) {
1057 switch (cinfo->ret.storage) {
1058 case ArgValuetypeInReg:
1059 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1061 cfg->ret->opcode = OP_REGOFFSET;
1062 cfg->ret->inst_basereg = X86_EBP;
1063 cfg->ret->inst_offset = - offset;
1069 /* Allocate locals */
1070 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1071 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1072 char *mname = mono_method_full_name (cfg->method, TRUE);
1073 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1074 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1078 if (locals_stack_align) {
1079 int prev_offset = offset;
1081 offset += (locals_stack_align - 1);
1082 offset &= ~(locals_stack_align - 1);
1084 while (prev_offset < offset) {
1086 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1089 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1090 cfg->locals_max_stack_offset = - offset;
1092 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1093 * have locals larger than 8 bytes we need to make sure that
1094 * they have the appropriate offset.
1096 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1097 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1098 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1099 if (offsets [i] != -1) {
1100 MonoInst *inst = cfg->varinfo [i];
1101 inst->opcode = OP_REGOFFSET;
1102 inst->inst_basereg = X86_EBP;
1103 inst->inst_offset = - (offset + offsets [i]);
1104 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1107 offset += locals_stack_size;
1111 * Allocate arguments+return value
1114 switch (cinfo->ret.storage) {
1116 if (cfg->vret_addr) {
1118 * In the new IR, the cfg->vret_addr variable represents the
1119 * vtype return value.
1121 cfg->vret_addr->opcode = OP_REGOFFSET;
1122 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1123 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1124 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1125 printf ("vret_addr =");
1126 mono_print_ins (cfg->vret_addr);
1129 cfg->ret->opcode = OP_REGOFFSET;
1130 cfg->ret->inst_basereg = X86_EBP;
1131 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1134 case ArgValuetypeInReg:
1137 cfg->ret->opcode = OP_REGVAR;
1138 cfg->ret->inst_c0 = cinfo->ret.reg;
1139 cfg->ret->dreg = cinfo->ret.reg;
1142 case ArgOnFloatFpStack:
1143 case ArgOnDoubleFpStack:
1146 g_assert_not_reached ();
1149 if (sig->call_convention == MONO_CALL_VARARG) {
1150 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1151 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1154 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1155 ArgInfo *ainfo = &cinfo->args [i];
1156 inst = cfg->args [i];
1157 if (inst->opcode != OP_REGVAR) {
1158 inst->opcode = OP_REGOFFSET;
1159 inst->inst_basereg = X86_EBP;
1161 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1164 cfg->stack_offset = offset;
1168 mono_arch_create_vars (MonoCompile *cfg)
1170 MonoMethodSignature *sig;
1173 sig = mono_method_signature (cfg->method);
1175 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1177 if (cinfo->ret.storage == ArgValuetypeInReg)
1178 cfg->ret_var_is_local = TRUE;
1179 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig->ret) || mini_is_gsharedvt_variable_type (cfg, sig->ret))) {
1180 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1183 cfg->arch_eh_jit_info = 1;
1187 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1188 * so we try to do it just once when we have multiple fp arguments in a row.
1189 * We don't use this mechanism generally because for int arguments the generated code
1190 * is slightly bigger and new generation cpus optimize away the dependency chains
1191 * created by push instructions on the esp value.
1192 * fp_arg_setup is the first argument in the execution sequence where the esp register
1195 static G_GNUC_UNUSED int
1196 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1201 for (; start_arg < sig->param_count; ++start_arg) {
1202 t = mini_type_get_underlying_type (NULL, sig->params [start_arg]);
1203 if (!t->byref && t->type == MONO_TYPE_R8) {
1204 fp_space += sizeof (double);
1205 *fp_arg_setup = start_arg;
1214 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1216 MonoMethodSignature *tmp_sig;
1220 * mono_ArgIterator_Setup assumes the signature cookie is
1221 * passed first and all the arguments which were before it are
1222 * passed on the stack after the signature. So compensate by
1223 * passing a different signature.
1225 tmp_sig = mono_metadata_signature_dup (call->signature);
1226 tmp_sig->param_count -= call->signature->sentinelpos;
1227 tmp_sig->sentinelpos = 0;
1228 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1230 if (cfg->compile_aot) {
1231 sig_reg = mono_alloc_ireg (cfg);
1232 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1233 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, sig_reg);
1235 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1241 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1246 LLVMCallInfo *linfo;
1249 n = sig->param_count + sig->hasthis;
1251 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1253 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1256 * LLVM always uses the native ABI while we use our own ABI, the
1257 * only difference is the handling of vtypes:
1258 * - we only pass/receive them in registers in some cases, and only
1259 * in 1 or 2 integer registers.
1261 if (cinfo->ret.storage == ArgValuetypeInReg) {
1263 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1264 cfg->disable_llvm = TRUE;
1268 cfg->exception_message = g_strdup ("vtype ret in call");
1269 cfg->disable_llvm = TRUE;
1271 linfo->ret.storage = LLVMArgVtypeInReg;
1272 for (j = 0; j < 2; ++j)
1273 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1277 if (mini_type_is_vtype (cfg, sig->ret) && cinfo->ret.storage == ArgInIReg) {
1278 /* Vtype returned using a hidden argument */
1279 linfo->ret.storage = LLVMArgVtypeRetAddr;
1280 linfo->vret_arg_index = cinfo->vret_arg_index;
1283 if (mini_type_is_vtype (cfg, sig->ret) && cinfo->ret.storage != ArgInIReg) {
1285 cfg->exception_message = g_strdup ("vtype ret in call");
1286 cfg->disable_llvm = TRUE;
1289 for (i = 0; i < n; ++i) {
1290 ainfo = cinfo->args + i;
1292 if (i >= sig->hasthis)
1293 t = sig->params [i - sig->hasthis];
1295 t = &mono_defaults.int_class->byval_arg;
1297 linfo->args [i].storage = LLVMArgNone;
1299 switch (ainfo->storage) {
1301 linfo->args [i].storage = LLVMArgInIReg;
1303 case ArgInDoubleSSEReg:
1304 case ArgInFloatSSEReg:
1305 linfo->args [i].storage = LLVMArgInFPReg;
1308 if (mini_type_is_vtype (cfg, t)) {
1309 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1310 /* LLVM seems to allocate argument space for empty structures too */
1311 linfo->args [i].storage = LLVMArgNone;
1313 linfo->args [i].storage = LLVMArgVtypeByVal;
1315 linfo->args [i].storage = LLVMArgInIReg;
1317 if (t->type == MONO_TYPE_R4)
1318 linfo->args [i].storage = LLVMArgInFPReg;
1319 else if (t->type == MONO_TYPE_R8)
1320 linfo->args [i].storage = LLVMArgInFPReg;
1324 case ArgValuetypeInReg:
1326 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1327 cfg->disable_llvm = TRUE;
1331 cfg->exception_message = g_strdup ("vtype arg");
1332 cfg->disable_llvm = TRUE;
1334 linfo->args [i].storage = LLVMArgVtypeInReg;
1335 for (j = 0; j < 2; ++j)
1336 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1340 linfo->args [i].storage = LLVMArgGSharedVt;
1343 cfg->exception_message = g_strdup ("ainfo->storage");
1344 cfg->disable_llvm = TRUE;
1354 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1356 if (cfg->compute_gc_maps) {
1359 /* On x86, the offsets are from the sp value before the start of the call sequence */
1361 t = &mono_defaults.int_class->byval_arg;
1362 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1367 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1370 MonoMethodSignature *sig;
1373 int sentinelpos = 0, sp_offset = 0;
1375 sig = call->signature;
1376 n = sig->param_count + sig->hasthis;
1378 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1380 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1381 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1383 if (cinfo->need_stack_align) {
1384 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1385 arg->dreg = X86_ESP;
1386 arg->sreg1 = X86_ESP;
1387 arg->inst_imm = cinfo->stack_align_amount;
1388 MONO_ADD_INS (cfg->cbb, arg);
1389 for (i = 0; i < cinfo->stack_align_amount; i += sizeof (mgreg_t)) {
1392 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1396 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1397 if (cinfo->ret.storage == ArgValuetypeInReg) {
1399 * Tell the JIT to use a more efficient calling convention: call using
1400 * OP_CALL, compute the result location after the call, and save the
1403 call->vret_in_reg = TRUE;
1405 NULLIFY_INS (call->vret_var);
1409 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1411 /* Handle the case where there are no implicit arguments */
1412 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1413 emit_sig_cookie (cfg, call, cinfo);
1415 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1418 /* Arguments are pushed in the reverse order */
1419 for (i = n - 1; i >= 0; i --) {
1420 ArgInfo *ainfo = cinfo->args + i;
1421 MonoType *orig_type, *t;
1424 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1425 /* Push the vret arg before the first argument */
1427 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1428 vtarg->type = STACK_MP;
1429 vtarg->sreg1 = call->vret_var->dreg;
1430 MONO_ADD_INS (cfg->cbb, vtarg);
1432 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1435 if (i >= sig->hasthis)
1436 t = sig->params [i - sig->hasthis];
1438 t = &mono_defaults.int_class->byval_arg;
1440 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1442 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1444 in = call->args [i];
1445 arg->cil_code = in->cil_code;
1446 arg->sreg1 = in->dreg;
1447 arg->type = in->type;
1449 g_assert (in->dreg != -1);
1451 if (ainfo->storage == ArgGSharedVt) {
1452 arg->opcode = OP_OUTARG_VT;
1453 arg->sreg1 = in->dreg;
1454 arg->klass = in->klass;
1456 MONO_ADD_INS (cfg->cbb, arg);
1457 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1461 g_assert (in->klass);
1463 if (t->type == MONO_TYPE_TYPEDBYREF) {
1464 size = sizeof (MonoTypedRef);
1465 align = sizeof (gpointer);
1468 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1472 arg->opcode = OP_OUTARG_VT;
1473 arg->sreg1 = in->dreg;
1474 arg->klass = in->klass;
1475 arg->backend.size = size;
1477 MONO_ADD_INS (cfg->cbb, arg);
1479 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1484 switch (ainfo->storage) {
1486 arg->opcode = OP_X86_PUSH;
1488 if (t->type == MONO_TYPE_R4) {
1489 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1490 arg->opcode = OP_STORER4_MEMBASE_REG;
1491 arg->inst_destbasereg = X86_ESP;
1492 arg->inst_offset = 0;
1494 } else if (t->type == MONO_TYPE_R8) {
1495 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1496 arg->opcode = OP_STORER8_MEMBASE_REG;
1497 arg->inst_destbasereg = X86_ESP;
1498 arg->inst_offset = 0;
1500 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1502 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1508 g_assert_not_reached ();
1511 MONO_ADD_INS (cfg->cbb, arg);
1513 sp_offset += argsize;
1515 if (cfg->compute_gc_maps) {
1517 /* FIXME: The == STACK_OBJ check might be fragile ? */
1518 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1520 if (call->need_unbox_trampoline)
1521 /* The unbox trampoline transforms this into a managed pointer */
1522 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.int_class->this_arg);
1524 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.object_class->byval_arg);
1526 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1530 for (j = 0; j < argsize; j += 4)
1531 emit_gc_param_slot_def (cfg, sp_offset - j, NULL);
1536 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1537 /* Emit the signature cookie just before the implicit arguments */
1538 emit_sig_cookie (cfg, call, cinfo);
1540 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1544 if (sig->ret && (MONO_TYPE_ISSTRUCT (sig->ret) || cinfo->vtype_retaddr)) {
1547 if (cinfo->ret.storage == ArgValuetypeInReg) {
1550 else if (cinfo->ret.storage == ArgInIReg) {
1552 /* The return address is passed in a register */
1553 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1554 vtarg->sreg1 = call->inst.dreg;
1555 vtarg->dreg = mono_alloc_ireg (cfg);
1556 MONO_ADD_INS (cfg->cbb, vtarg);
1558 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1559 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1561 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1562 vtarg->type = STACK_MP;
1563 vtarg->sreg1 = call->vret_var->dreg;
1564 MONO_ADD_INS (cfg->cbb, vtarg);
1566 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1569 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1570 if (cinfo->ret.storage != ArgValuetypeInReg)
1571 cinfo->stack_usage -= 4;
1574 call->stack_usage = cinfo->stack_usage;
1575 call->stack_align_amount = cinfo->stack_align_amount;
1576 cfg->arch.param_area_size = MAX (cfg->arch.param_area_size, sp_offset);
1580 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1583 int size = ins->backend.size;
1585 if (cfg->gsharedvt && mini_is_gsharedvt_klass (cfg, ins->klass)) {
1587 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1588 arg->sreg1 = src->dreg;
1589 MONO_ADD_INS (cfg->cbb, arg);
1590 } else if (size <= 4) {
1591 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1592 arg->sreg1 = src->dreg;
1594 MONO_ADD_INS (cfg->cbb, arg);
1595 } else if (size <= 20) {
1596 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1597 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1599 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1600 arg->inst_basereg = src->dreg;
1601 arg->inst_offset = 0;
1602 arg->inst_imm = size;
1604 MONO_ADD_INS (cfg->cbb, arg);
1609 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1611 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1614 if (ret->type == MONO_TYPE_R4) {
1615 if (COMPILE_LLVM (cfg))
1616 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1619 } else if (ret->type == MONO_TYPE_R8) {
1620 if (COMPILE_LLVM (cfg))
1621 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1624 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1625 if (COMPILE_LLVM (cfg))
1626 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1628 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1629 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1635 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1639 * Allow tracing to work with this interface (with an optional argument)
1642 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1646 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1647 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1649 /* if some args are passed in registers, we need to save them here */
1650 x86_push_reg (code, X86_EBP);
1652 if (cfg->compile_aot) {
1653 x86_push_imm (code, cfg->method);
1654 x86_mov_reg_imm (code, X86_EAX, func);
1655 x86_call_reg (code, X86_EAX);
1657 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1658 x86_push_imm (code, cfg->method);
1659 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1660 x86_call_code (code, 0);
1662 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1676 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1679 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1680 MonoMethod *method = cfg->method;
1681 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1683 switch (ret_type->type) {
1684 case MONO_TYPE_VOID:
1685 /* special case string .ctor icall */
1686 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1687 save_mode = SAVE_EAX;
1688 stack_usage = enable_arguments ? 8 : 4;
1690 save_mode = SAVE_NONE;
1694 save_mode = SAVE_EAX_EDX;
1695 stack_usage = enable_arguments ? 16 : 8;
1699 save_mode = SAVE_FP;
1700 stack_usage = enable_arguments ? 16 : 8;
1702 case MONO_TYPE_GENERICINST:
1703 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1704 save_mode = SAVE_EAX;
1705 stack_usage = enable_arguments ? 8 : 4;
1709 case MONO_TYPE_VALUETYPE:
1710 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1711 save_mode = SAVE_STRUCT;
1712 stack_usage = enable_arguments ? 4 : 0;
1715 save_mode = SAVE_EAX;
1716 stack_usage = enable_arguments ? 8 : 4;
1720 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1722 switch (save_mode) {
1724 x86_push_reg (code, X86_EDX);
1725 x86_push_reg (code, X86_EAX);
1726 if (enable_arguments) {
1727 x86_push_reg (code, X86_EDX);
1728 x86_push_reg (code, X86_EAX);
1733 x86_push_reg (code, X86_EAX);
1734 if (enable_arguments) {
1735 x86_push_reg (code, X86_EAX);
1740 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1741 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1742 if (enable_arguments) {
1743 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1744 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1749 if (enable_arguments) {
1750 x86_push_membase (code, X86_EBP, 8);
1759 if (cfg->compile_aot) {
1760 x86_push_imm (code, method);
1761 x86_mov_reg_imm (code, X86_EAX, func);
1762 x86_call_reg (code, X86_EAX);
1764 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1765 x86_push_imm (code, method);
1766 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1767 x86_call_code (code, 0);
1770 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1772 switch (save_mode) {
1774 x86_pop_reg (code, X86_EAX);
1775 x86_pop_reg (code, X86_EDX);
1778 x86_pop_reg (code, X86_EAX);
1781 x86_fld_membase (code, X86_ESP, 0, TRUE);
1782 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1789 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1794 #define EMIT_COND_BRANCH(ins,cond,sign) \
1795 if (ins->inst_true_bb->native_offset) { \
1796 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1798 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1799 if ((cfg->opt & MONO_OPT_BRANCH) && \
1800 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1801 x86_branch8 (code, cond, 0, sign); \
1803 x86_branch32 (code, cond, 0, sign); \
1807 * Emit an exception if condition is fail and
1808 * if possible do a directly branch to target
1810 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1812 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1813 if (tins == NULL) { \
1814 mono_add_patch_info (cfg, code - cfg->native_code, \
1815 MONO_PATCH_INFO_EXC, exc_name); \
1816 x86_branch32 (code, cond, 0, signed); \
1818 EMIT_COND_BRANCH (tins, cond, signed); \
1822 #define EMIT_FPCOMPARE(code) do { \
1823 x86_fcompp (code); \
1824 x86_fnstsw (code); \
1829 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1831 gboolean needs_paddings = TRUE;
1833 MonoJumpInfo *jinfo = NULL;
1835 if (cfg->abs_patches) {
1836 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1837 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1838 needs_paddings = FALSE;
1841 if (cfg->compile_aot)
1842 needs_paddings = FALSE;
1843 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1844 This is required for code patching to be safe on SMP machines.
1846 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1847 #ifndef __native_client_codegen__
1848 if (needs_paddings && pad_size)
1849 x86_padding (code, 4 - pad_size);
1852 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1853 x86_call_code (code, 0);
1858 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1861 * mono_peephole_pass_1:
1863 * Perform peephole opts which should/can be performed before local regalloc
1866 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1870 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1871 MonoInst *last_ins = ins->prev;
1873 switch (ins->opcode) {
1876 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1878 * X86_LEA is like ADD, but doesn't have the
1879 * sreg1==dreg restriction.
1881 ins->opcode = OP_X86_LEA_MEMBASE;
1882 ins->inst_basereg = ins->sreg1;
1883 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1884 ins->opcode = OP_X86_INC_REG;
1888 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1889 ins->opcode = OP_X86_LEA_MEMBASE;
1890 ins->inst_basereg = ins->sreg1;
1891 ins->inst_imm = -ins->inst_imm;
1892 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1893 ins->opcode = OP_X86_DEC_REG;
1895 case OP_COMPARE_IMM:
1896 case OP_ICOMPARE_IMM:
1897 /* OP_COMPARE_IMM (reg, 0)
1899 * OP_X86_TEST_NULL (reg)
1902 ins->opcode = OP_X86_TEST_NULL;
1904 case OP_X86_COMPARE_MEMBASE_IMM:
1906 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1907 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1909 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1910 * OP_COMPARE_IMM reg, imm
1912 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1914 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1915 ins->inst_basereg == last_ins->inst_destbasereg &&
1916 ins->inst_offset == last_ins->inst_offset) {
1917 ins->opcode = OP_COMPARE_IMM;
1918 ins->sreg1 = last_ins->sreg1;
1920 /* check if we can remove cmp reg,0 with test null */
1922 ins->opcode = OP_X86_TEST_NULL;
1926 case OP_X86_PUSH_MEMBASE:
1927 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1928 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1929 ins->inst_basereg == last_ins->inst_destbasereg &&
1930 ins->inst_offset == last_ins->inst_offset) {
1931 ins->opcode = OP_X86_PUSH;
1932 ins->sreg1 = last_ins->sreg1;
1937 mono_peephole_ins (bb, ins);
1942 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1946 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1947 switch (ins->opcode) {
1949 /* reg = 0 -> XOR (reg, reg) */
1950 /* XOR sets cflags on x86, so we cant do it always */
1951 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1954 ins->opcode = OP_IXOR;
1955 ins->sreg1 = ins->dreg;
1956 ins->sreg2 = ins->dreg;
1959 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1960 * since it takes 3 bytes instead of 7.
1962 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
1963 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1964 ins2->opcode = OP_STORE_MEMBASE_REG;
1965 ins2->sreg1 = ins->dreg;
1967 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1968 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1969 ins2->sreg1 = ins->dreg;
1971 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1972 /* Continue iteration */
1981 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1982 ins->opcode = OP_X86_INC_REG;
1986 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1987 ins->opcode = OP_X86_DEC_REG;
1991 mono_peephole_ins (bb, ins);
1996 * mono_arch_lowering_pass:
1998 * Converts complex opcodes into simpler ones so that each IR instruction
1999 * corresponds to one machine instruction.
2002 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2004 MonoInst *ins, *next;
2007 * FIXME: Need to add more instructions, but the current machine
2008 * description can't model some parts of the composite instructions like
2011 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2012 switch (ins->opcode) {
2015 case OP_IDIV_UN_IMM:
2016 case OP_IREM_UN_IMM:
2018 * Keep the cases where we could generated optimized code, otherwise convert
2019 * to the non-imm variant.
2021 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2023 mono_decompose_op_imm (cfg, bb, ins);
2030 bb->max_vreg = cfg->next_vreg;
2034 branch_cc_table [] = {
2035 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2036 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2037 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2040 /* Maps CMP_... constants to X86_CC_... constants */
2043 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2044 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2048 cc_signed_table [] = {
2049 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2050 FALSE, FALSE, FALSE, FALSE
2053 static unsigned char*
2054 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2056 #define XMM_TEMP_REG 0
2057 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2058 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2059 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2060 /* optimize by assigning a local var for this use so we avoid
2061 * the stack manipulations */
2062 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2063 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2064 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2065 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2066 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2068 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2070 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2073 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2074 x86_fnstcw_membase(code, X86_ESP, 0);
2075 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2076 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2077 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2078 x86_fldcw_membase (code, X86_ESP, 2);
2080 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2081 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2082 x86_pop_reg (code, dreg);
2083 /* FIXME: need the high register
2084 * x86_pop_reg (code, dreg_high);
2087 x86_push_reg (code, X86_EAX); // SP = SP - 4
2088 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2089 x86_pop_reg (code, dreg);
2091 x86_fldcw_membase (code, X86_ESP, 0);
2092 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2095 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2097 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2101 static unsigned char*
2102 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2104 int sreg = tree->sreg1;
2105 int need_touch = FALSE;
2107 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2116 * If requested stack size is larger than one page,
2117 * perform stack-touch operation
2120 * Generate stack probe code.
2121 * Under Windows, it is necessary to allocate one page at a time,
2122 * "touching" stack after each successful sub-allocation. This is
2123 * because of the way stack growth is implemented - there is a
2124 * guard page before the lowest stack page that is currently commited.
2125 * Stack normally grows sequentially so OS traps access to the
2126 * guard page and commits more pages when needed.
2128 x86_test_reg_imm (code, sreg, ~0xFFF);
2129 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2131 br[2] = code; /* loop */
2132 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2133 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2136 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2137 * that follows only initializes the last part of the area.
2139 /* Same as the init code below with size==0x1000 */
2140 if (tree->flags & MONO_INST_INIT) {
2141 x86_push_reg (code, X86_EAX);
2142 x86_push_reg (code, X86_ECX);
2143 x86_push_reg (code, X86_EDI);
2144 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2145 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2146 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2148 x86_prefix (code, X86_REP_PREFIX);
2150 x86_pop_reg (code, X86_EDI);
2151 x86_pop_reg (code, X86_ECX);
2152 x86_pop_reg (code, X86_EAX);
2155 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2156 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2157 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2158 x86_patch (br[3], br[2]);
2159 x86_test_reg_reg (code, sreg, sreg);
2160 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2161 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2163 br[1] = code; x86_jump8 (code, 0);
2165 x86_patch (br[0], code);
2166 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2167 x86_patch (br[1], code);
2168 x86_patch (br[4], code);
2171 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2173 if (tree->flags & MONO_INST_INIT) {
2175 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2176 x86_push_reg (code, X86_EAX);
2179 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2180 x86_push_reg (code, X86_ECX);
2183 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2184 x86_push_reg (code, X86_EDI);
2188 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2189 if (sreg != X86_ECX)
2190 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2191 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2193 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2195 x86_prefix (code, X86_REP_PREFIX);
2198 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2199 x86_pop_reg (code, X86_EDI);
2200 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2201 x86_pop_reg (code, X86_ECX);
2202 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2203 x86_pop_reg (code, X86_EAX);
2210 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2212 /* Move return value to the target register */
2213 switch (ins->opcode) {
2216 case OP_CALL_MEMBASE:
2217 if (ins->dreg != X86_EAX)
2218 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2228 static int tls_gs_offset;
2232 mono_x86_have_tls_get (void)
2235 static gboolean have_tls_get = FALSE;
2236 static gboolean inited = FALSE;
2240 return have_tls_get;
2242 ins = (guint32*)pthread_getspecific;
2244 * We're looking for these two instructions:
2246 * mov 0x4(%esp),%eax
2247 * mov %gs:[offset](,%eax,4),%eax
2249 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2250 tls_gs_offset = ins [2];
2254 return have_tls_get;
2255 #elif defined(TARGET_ANDROID)
2263 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2265 #if defined(__APPLE__)
2266 x86_prefix (code, X86_GS_PREFIX);
2267 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2268 #elif defined(TARGET_WIN32)
2269 g_assert_not_reached ();
2271 x86_prefix (code, X86_GS_PREFIX);
2272 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2278 * mono_x86_emit_tls_get:
2279 * @code: buffer to store code to
2280 * @dreg: hard register where to place the result
2281 * @tls_offset: offset info
2283 * mono_x86_emit_tls_get emits in @code the native code that puts in
2284 * the dreg register the item in the thread local storage identified
2287 * Returns: a pointer to the end of the stored code
2290 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2292 #if defined(__APPLE__)
2293 x86_prefix (code, X86_GS_PREFIX);
2294 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2295 #elif defined(TARGET_WIN32)
2297 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2298 * Journal and/or a disassembly of the TlsGet () function.
2300 g_assert (tls_offset < 64);
2301 x86_prefix (code, X86_FS_PREFIX);
2302 x86_mov_reg_mem (code, dreg, 0x18, 4);
2303 /* Dunno what this does but TlsGetValue () contains it */
2304 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2305 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2307 if (optimize_for_xen) {
2308 x86_prefix (code, X86_GS_PREFIX);
2309 x86_mov_reg_mem (code, dreg, 0, 4);
2310 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2312 x86_prefix (code, X86_GS_PREFIX);
2313 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2320 * emit_load_volatile_arguments:
2322 * Load volatile arguments from the stack to the original input registers.
2323 * Required before a tail call.
2326 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2328 MonoMethod *method = cfg->method;
2329 MonoMethodSignature *sig;
2334 /* FIXME: Generate intermediate code instead */
2336 sig = mono_method_signature (method);
2338 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2340 /* This is the opposite of the code in emit_prolog */
2342 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2343 ArgInfo *ainfo = cinfo->args + i;
2345 inst = cfg->args [i];
2347 if (sig->hasthis && (i == 0))
2348 arg_type = &mono_defaults.object_class->byval_arg;
2350 arg_type = sig->params [i - sig->hasthis];
2353 * On x86, the arguments are either in their original stack locations, or in
2356 if (inst->opcode == OP_REGVAR) {
2357 g_assert (ainfo->storage == ArgOnStack);
2359 x86_mov_membase_reg (code, X86_EBP, inst->inst_offset, inst->dreg, 4);
2366 #define REAL_PRINT_REG(text,reg) \
2367 mono_assert (reg >= 0); \
2368 x86_push_reg (code, X86_EAX); \
2369 x86_push_reg (code, X86_EDX); \
2370 x86_push_reg (code, X86_ECX); \
2371 x86_push_reg (code, reg); \
2372 x86_push_imm (code, reg); \
2373 x86_push_imm (code, text " %d %p\n"); \
2374 x86_mov_reg_imm (code, X86_EAX, printf); \
2375 x86_call_reg (code, X86_EAX); \
2376 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2377 x86_pop_reg (code, X86_ECX); \
2378 x86_pop_reg (code, X86_EDX); \
2379 x86_pop_reg (code, X86_EAX);
2381 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2382 #ifdef __native__client_codegen__
2383 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2386 /* benchmark and set based on cpu */
2387 #define LOOP_ALIGNMENT 8
2388 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2392 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2397 guint8 *code = cfg->native_code + cfg->code_len;
2400 if (cfg->opt & MONO_OPT_LOOP) {
2401 int pad, align = LOOP_ALIGNMENT;
2402 /* set alignment depending on cpu */
2403 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2405 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2406 x86_padding (code, pad);
2407 cfg->code_len += pad;
2408 bb->native_offset = cfg->code_len;
2411 #ifdef __native_client_codegen__
2413 /* For Native Client, all indirect call/jump targets must be */
2414 /* 32-byte aligned. Exception handler blocks are jumped to */
2415 /* indirectly as well. */
2416 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2417 (bb->flags & BB_EXCEPTION_HANDLER);
2419 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2420 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2421 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2422 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2423 cfg->code_len += pad;
2424 bb->native_offset = cfg->code_len;
2427 #endif /* __native_client_codegen__ */
2428 if (cfg->verbose_level > 2)
2429 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2431 cpos = bb->max_offset;
2433 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2434 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2435 g_assert (!cfg->compile_aot);
2438 cov->data [bb->dfn].cil_code = bb->cil_code;
2439 /* this is not thread save, but good enough */
2440 x86_inc_mem (code, &cov->data [bb->dfn].count);
2443 offset = code - cfg->native_code;
2445 mono_debug_open_block (cfg, bb, offset);
2447 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2448 x86_breakpoint (code);
2450 MONO_BB_FOR_EACH_INS (bb, ins) {
2451 offset = code - cfg->native_code;
2453 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2455 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2457 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2458 cfg->code_size *= 2;
2459 cfg->native_code = mono_realloc_native_code(cfg);
2460 code = cfg->native_code + offset;
2461 cfg->stat_code_reallocs++;
2464 if (cfg->debug_info)
2465 mono_debug_record_line_number (cfg, ins, offset);
2467 switch (ins->opcode) {
2469 x86_mul_reg (code, ins->sreg2, TRUE);
2472 x86_mul_reg (code, ins->sreg2, FALSE);
2474 case OP_X86_SETEQ_MEMBASE:
2475 case OP_X86_SETNE_MEMBASE:
2476 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2477 ins->inst_basereg, ins->inst_offset, TRUE);
2479 case OP_STOREI1_MEMBASE_IMM:
2480 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2482 case OP_STOREI2_MEMBASE_IMM:
2483 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2485 case OP_STORE_MEMBASE_IMM:
2486 case OP_STOREI4_MEMBASE_IMM:
2487 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2489 case OP_STOREI1_MEMBASE_REG:
2490 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2492 case OP_STOREI2_MEMBASE_REG:
2493 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2495 case OP_STORE_MEMBASE_REG:
2496 case OP_STOREI4_MEMBASE_REG:
2497 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2499 case OP_STORE_MEM_IMM:
2500 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2503 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2507 /* These are created by the cprop pass so they use inst_imm as the source */
2508 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2511 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2514 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2516 case OP_LOAD_MEMBASE:
2517 case OP_LOADI4_MEMBASE:
2518 case OP_LOADU4_MEMBASE:
2519 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2521 case OP_LOADU1_MEMBASE:
2522 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2524 case OP_LOADI1_MEMBASE:
2525 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2527 case OP_LOADU2_MEMBASE:
2528 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2530 case OP_LOADI2_MEMBASE:
2531 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2533 case OP_ICONV_TO_I1:
2535 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2537 case OP_ICONV_TO_I2:
2539 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2541 case OP_ICONV_TO_U1:
2542 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2544 case OP_ICONV_TO_U2:
2545 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2549 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2551 case OP_COMPARE_IMM:
2552 case OP_ICOMPARE_IMM:
2553 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2555 case OP_X86_COMPARE_MEMBASE_REG:
2556 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2558 case OP_X86_COMPARE_MEMBASE_IMM:
2559 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2561 case OP_X86_COMPARE_MEMBASE8_IMM:
2562 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2564 case OP_X86_COMPARE_REG_MEMBASE:
2565 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2567 case OP_X86_COMPARE_MEM_IMM:
2568 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2570 case OP_X86_TEST_NULL:
2571 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2573 case OP_X86_ADD_MEMBASE_IMM:
2574 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2576 case OP_X86_ADD_REG_MEMBASE:
2577 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2579 case OP_X86_SUB_MEMBASE_IMM:
2580 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2582 case OP_X86_SUB_REG_MEMBASE:
2583 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2585 case OP_X86_AND_MEMBASE_IMM:
2586 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2588 case OP_X86_OR_MEMBASE_IMM:
2589 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2591 case OP_X86_XOR_MEMBASE_IMM:
2592 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2594 case OP_X86_ADD_MEMBASE_REG:
2595 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2597 case OP_X86_SUB_MEMBASE_REG:
2598 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2600 case OP_X86_AND_MEMBASE_REG:
2601 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2603 case OP_X86_OR_MEMBASE_REG:
2604 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2606 case OP_X86_XOR_MEMBASE_REG:
2607 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2609 case OP_X86_INC_MEMBASE:
2610 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2612 case OP_X86_INC_REG:
2613 x86_inc_reg (code, ins->dreg);
2615 case OP_X86_DEC_MEMBASE:
2616 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2618 case OP_X86_DEC_REG:
2619 x86_dec_reg (code, ins->dreg);
2621 case OP_X86_MUL_REG_MEMBASE:
2622 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2624 case OP_X86_AND_REG_MEMBASE:
2625 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2627 case OP_X86_OR_REG_MEMBASE:
2628 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2630 case OP_X86_XOR_REG_MEMBASE:
2631 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2634 x86_breakpoint (code);
2636 case OP_RELAXED_NOP:
2637 x86_prefix (code, X86_REP_PREFIX);
2645 case OP_DUMMY_STORE:
2646 case OP_NOT_REACHED:
2649 case OP_SEQ_POINT: {
2652 if (cfg->compile_aot)
2656 * Read from the single stepping trigger page. This will cause a
2657 * SIGSEGV when single stepping is enabled.
2658 * We do this _before_ the breakpoint, so single stepping after
2659 * a breakpoint is hit will step to the next IL offset.
2661 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2662 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2664 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2667 * A placeholder for a possible breakpoint inserted by
2668 * mono_arch_set_breakpoint ().
2670 for (i = 0; i < 6; ++i)
2673 * Add an additional nop so skipping the bp doesn't cause the ip to point
2674 * to another IL offset.
2682 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2686 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2691 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2695 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2700 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2704 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2709 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2713 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2716 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2720 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2724 #if defined( __native_client_codegen__ )
2725 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2726 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2729 * The code is the same for div/rem, the allocator will allocate dreg
2730 * to RAX/RDX as appropriate.
2732 if (ins->sreg2 == X86_EDX) {
2733 /* cdq clobbers this */
2734 x86_push_reg (code, ins->sreg2);
2736 x86_div_membase (code, X86_ESP, 0, TRUE);
2737 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2740 x86_div_reg (code, ins->sreg2, TRUE);
2745 #if defined( __native_client_codegen__ )
2746 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2747 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2749 if (ins->sreg2 == X86_EDX) {
2750 x86_push_reg (code, ins->sreg2);
2751 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2752 x86_div_membase (code, X86_ESP, 0, FALSE);
2753 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2755 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2756 x86_div_reg (code, ins->sreg2, FALSE);
2760 #if defined( __native_client_codegen__ )
2761 if (ins->inst_imm == 0) {
2762 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2763 x86_jump32 (code, 0);
2767 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2769 x86_div_reg (code, ins->sreg2, TRUE);
2772 int power = mono_is_power_of_two (ins->inst_imm);
2774 g_assert (ins->sreg1 == X86_EAX);
2775 g_assert (ins->dreg == X86_EAX);
2776 g_assert (power >= 0);
2779 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2781 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2783 * If the divident is >= 0, this does not nothing. If it is positive, it
2784 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2786 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2787 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2788 } else if (power == 0) {
2789 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2791 /* Based on gcc code */
2793 /* Add compensation for negative dividents */
2795 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2796 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2797 /* Compute remainder */
2798 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2799 /* Remove compensation */
2800 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2805 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2809 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2812 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2816 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2819 g_assert (ins->sreg2 == X86_ECX);
2820 x86_shift_reg (code, X86_SHL, ins->dreg);
2823 g_assert (ins->sreg2 == X86_ECX);
2824 x86_shift_reg (code, X86_SAR, ins->dreg);
2828 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2831 case OP_ISHR_UN_IMM:
2832 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2835 g_assert (ins->sreg2 == X86_ECX);
2836 x86_shift_reg (code, X86_SHR, ins->dreg);
2840 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2843 guint8 *jump_to_end;
2845 /* handle shifts below 32 bits */
2846 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2847 x86_shift_reg (code, X86_SHL, ins->sreg1);
2849 x86_test_reg_imm (code, X86_ECX, 32);
2850 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2852 /* handle shift over 32 bit */
2853 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2854 x86_clear_reg (code, ins->sreg1);
2856 x86_patch (jump_to_end, code);
2860 guint8 *jump_to_end;
2862 /* handle shifts below 32 bits */
2863 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2864 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2866 x86_test_reg_imm (code, X86_ECX, 32);
2867 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2869 /* handle shifts over 31 bits */
2870 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2871 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2873 x86_patch (jump_to_end, code);
2877 guint8 *jump_to_end;
2879 /* handle shifts below 32 bits */
2880 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2881 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2883 x86_test_reg_imm (code, X86_ECX, 32);
2884 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2886 /* handle shifts over 31 bits */
2887 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2888 x86_clear_reg (code, ins->backend.reg3);
2890 x86_patch (jump_to_end, code);
2894 if (ins->inst_imm >= 32) {
2895 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2896 x86_clear_reg (code, ins->sreg1);
2897 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2899 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2900 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2904 if (ins->inst_imm >= 32) {
2905 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2906 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2907 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2909 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2910 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2913 case OP_LSHR_UN_IMM:
2914 if (ins->inst_imm >= 32) {
2915 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2916 x86_clear_reg (code, ins->backend.reg3);
2917 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2919 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2920 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2924 x86_not_reg (code, ins->sreg1);
2927 x86_neg_reg (code, ins->sreg1);
2931 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2935 switch (ins->inst_imm) {
2939 if (ins->dreg != ins->sreg1)
2940 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2941 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2944 /* LEA r1, [r2 + r2*2] */
2945 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2948 /* LEA r1, [r2 + r2*4] */
2949 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2952 /* LEA r1, [r2 + r2*2] */
2954 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2955 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2958 /* LEA r1, [r2 + r2*8] */
2959 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2962 /* LEA r1, [r2 + r2*4] */
2964 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2965 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2968 /* LEA r1, [r2 + r2*2] */
2970 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2971 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2974 /* LEA r1, [r2 + r2*4] */
2975 /* LEA r1, [r1 + r1*4] */
2976 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2977 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2980 /* LEA r1, [r2 + r2*4] */
2982 /* LEA r1, [r1 + r1*4] */
2983 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2984 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2985 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2988 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2993 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2994 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2996 case OP_IMUL_OVF_UN: {
2997 /* the mul operation and the exception check should most likely be split */
2998 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2999 /*g_assert (ins->sreg2 == X86_EAX);
3000 g_assert (ins->dreg == X86_EAX);*/
3001 if (ins->sreg2 == X86_EAX) {
3002 non_eax_reg = ins->sreg1;
3003 } else if (ins->sreg1 == X86_EAX) {
3004 non_eax_reg = ins->sreg2;
3006 /* no need to save since we're going to store to it anyway */
3007 if (ins->dreg != X86_EAX) {
3009 x86_push_reg (code, X86_EAX);
3011 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3012 non_eax_reg = ins->sreg2;
3014 if (ins->dreg == X86_EDX) {
3017 x86_push_reg (code, X86_EAX);
3019 } else if (ins->dreg != X86_EAX) {
3021 x86_push_reg (code, X86_EDX);
3023 x86_mul_reg (code, non_eax_reg, FALSE);
3024 /* save before the check since pop and mov don't change the flags */
3025 if (ins->dreg != X86_EAX)
3026 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3028 x86_pop_reg (code, X86_EDX);
3030 x86_pop_reg (code, X86_EAX);
3031 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3035 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3038 g_assert_not_reached ();
3039 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3040 x86_mov_reg_imm (code, ins->dreg, 0);
3043 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3044 x86_mov_reg_imm (code, ins->dreg, 0);
3046 case OP_LOAD_GOTADDR:
3047 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3048 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3051 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3052 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3054 case OP_X86_PUSH_GOT_ENTRY:
3055 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3056 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3059 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3063 * Note: this 'frame destruction' logic is useful for tail calls, too.
3064 * Keep in sync with the code in emit_epilog.
3068 /* FIXME: no tracing support... */
3069 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3070 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3071 /* reset offset to make max_len work */
3072 offset = code - cfg->native_code;
3074 g_assert (!cfg->method->save_lmf);
3076 code = emit_load_volatile_arguments (cfg, code);
3078 if (cfg->used_int_regs & (1 << X86_EBX))
3080 if (cfg->used_int_regs & (1 << X86_EDI))
3082 if (cfg->used_int_regs & (1 << X86_ESI))
3085 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
3087 if (cfg->used_int_regs & (1 << X86_ESI))
3088 x86_pop_reg (code, X86_ESI);
3089 if (cfg->used_int_regs & (1 << X86_EDI))
3090 x86_pop_reg (code, X86_EDI);
3091 if (cfg->used_int_regs & (1 << X86_EBX))
3092 x86_pop_reg (code, X86_EBX);
3094 /* restore ESP/EBP */
3096 offset = code - cfg->native_code;
3097 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3098 x86_jump32 (code, 0);
3100 cfg->disable_aot = TRUE;
3104 MonoCallInst *call = (MonoCallInst*)ins;
3107 ins->flags |= MONO_INST_GC_CALLSITE;
3108 ins->backend.pc_offset = code - cfg->native_code;
3110 /* FIXME: no tracing support... */
3111 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3112 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3113 /* reset offset to make max_len work */
3114 offset = code - cfg->native_code;
3116 g_assert (!cfg->method->save_lmf);
3118 //code = emit_load_volatile_arguments (cfg, code);
3120 /* restore callee saved registers */
3121 for (i = 0; i < X86_NREG; ++i)
3122 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3124 if (cfg->used_int_regs & (1 << X86_ESI)) {
3125 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3128 if (cfg->used_int_regs & (1 << X86_EDI)) {
3129 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3132 if (cfg->used_int_regs & (1 << X86_EBX)) {
3133 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3137 /* Copy arguments on the stack to our argument area */
3138 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3139 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3140 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3143 /* restore ESP/EBP */
3145 offset = code - cfg->native_code;
3146 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3147 x86_jump32 (code, 0);
3149 ins->flags |= MONO_INST_GC_CALLSITE;
3150 cfg->disable_aot = TRUE;
3154 /* ensure ins->sreg1 is not NULL
3155 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3156 * cmp DWORD PTR [eax], 0
3158 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3161 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3162 x86_push_reg (code, hreg);
3163 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3164 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3165 x86_pop_reg (code, hreg);
3174 call = (MonoCallInst*)ins;
3175 if (ins->flags & MONO_INST_HAS_METHOD)
3176 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3178 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3179 ins->flags |= MONO_INST_GC_CALLSITE;
3180 ins->backend.pc_offset = code - cfg->native_code;
3181 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3182 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
3183 * bytes to pop, we want to use pops. GCC does this (note it won't happen
3184 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
3185 * smart enough to do that optimization yet
3187 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
3188 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
3189 * (most likely from locality benefits). People with other processors should
3190 * check on theirs to see what happens.
3192 if (call->stack_usage == 4) {
3193 /* we want to use registers that won't get used soon, so use
3194 * ecx, as eax will get allocated first. edx is used by long calls,
3195 * so we can't use that.
3198 x86_pop_reg (code, X86_ECX);
3200 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3203 code = emit_move_return_value (cfg, ins, code);
3209 case OP_VOIDCALL_REG:
3211 call = (MonoCallInst*)ins;
3212 x86_call_reg (code, ins->sreg1);
3213 ins->flags |= MONO_INST_GC_CALLSITE;
3214 ins->backend.pc_offset = code - cfg->native_code;
3215 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3216 if (call->stack_usage == 4)
3217 x86_pop_reg (code, X86_ECX);
3219 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3221 code = emit_move_return_value (cfg, ins, code);
3223 case OP_FCALL_MEMBASE:
3224 case OP_LCALL_MEMBASE:
3225 case OP_VCALL_MEMBASE:
3226 case OP_VCALL2_MEMBASE:
3227 case OP_VOIDCALL_MEMBASE:
3228 case OP_CALL_MEMBASE:
3229 call = (MonoCallInst*)ins;
3231 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3232 ins->flags |= MONO_INST_GC_CALLSITE;
3233 ins->backend.pc_offset = code - cfg->native_code;
3234 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3235 if (call->stack_usage == 4)
3236 x86_pop_reg (code, X86_ECX);
3238 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3240 code = emit_move_return_value (cfg, ins, code);
3243 x86_push_reg (code, ins->sreg1);
3245 case OP_X86_PUSH_IMM:
3246 x86_push_imm (code, ins->inst_imm);
3248 case OP_X86_PUSH_MEMBASE:
3249 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
3251 case OP_X86_PUSH_OBJ:
3252 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
3253 x86_push_reg (code, X86_EDI);
3254 x86_push_reg (code, X86_ESI);
3255 x86_push_reg (code, X86_ECX);
3256 if (ins->inst_offset)
3257 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
3259 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
3260 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
3261 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
3263 x86_prefix (code, X86_REP_PREFIX);
3265 x86_pop_reg (code, X86_ECX);
3266 x86_pop_reg (code, X86_ESI);
3267 x86_pop_reg (code, X86_EDI);
3270 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3272 case OP_X86_LEA_MEMBASE:
3273 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3276 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3279 /* keep alignment */
3280 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3281 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3282 code = mono_emit_stack_alloc (code, ins);
3283 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3285 case OP_LOCALLOC_IMM: {
3286 guint32 size = ins->inst_imm;
3287 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3289 if (ins->flags & MONO_INST_INIT) {
3290 /* FIXME: Optimize this */
3291 x86_mov_reg_imm (code, ins->dreg, size);
3292 ins->sreg1 = ins->dreg;
3294 code = mono_emit_stack_alloc (code, ins);
3295 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3297 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3298 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3303 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3304 x86_push_reg (code, ins->sreg1);
3305 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3306 (gpointer)"mono_arch_throw_exception");
3307 ins->flags |= MONO_INST_GC_CALLSITE;
3308 ins->backend.pc_offset = code - cfg->native_code;
3312 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3313 x86_push_reg (code, ins->sreg1);
3314 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3315 (gpointer)"mono_arch_rethrow_exception");
3316 ins->flags |= MONO_INST_GC_CALLSITE;
3317 ins->backend.pc_offset = code - cfg->native_code;
3320 case OP_CALL_HANDLER:
3321 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3322 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3323 x86_call_imm (code, 0);
3324 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3325 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3327 case OP_START_HANDLER: {
3328 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3329 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3332 case OP_ENDFINALLY: {
3333 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3334 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3338 case OP_ENDFILTER: {
3339 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3340 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3341 /* The local allocator will put the result into EAX */
3347 ins->inst_c0 = code - cfg->native_code;
3350 if (ins->inst_target_bb->native_offset) {
3351 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3353 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3354 if ((cfg->opt & MONO_OPT_BRANCH) &&
3355 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3356 x86_jump8 (code, 0);
3358 x86_jump32 (code, 0);
3362 x86_jump_reg (code, ins->sreg1);
3375 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3376 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3378 case OP_COND_EXC_EQ:
3379 case OP_COND_EXC_NE_UN:
3380 case OP_COND_EXC_LT:
3381 case OP_COND_EXC_LT_UN:
3382 case OP_COND_EXC_GT:
3383 case OP_COND_EXC_GT_UN:
3384 case OP_COND_EXC_GE:
3385 case OP_COND_EXC_GE_UN:
3386 case OP_COND_EXC_LE:
3387 case OP_COND_EXC_LE_UN:
3388 case OP_COND_EXC_IEQ:
3389 case OP_COND_EXC_INE_UN:
3390 case OP_COND_EXC_ILT:
3391 case OP_COND_EXC_ILT_UN:
3392 case OP_COND_EXC_IGT:
3393 case OP_COND_EXC_IGT_UN:
3394 case OP_COND_EXC_IGE:
3395 case OP_COND_EXC_IGE_UN:
3396 case OP_COND_EXC_ILE:
3397 case OP_COND_EXC_ILE_UN:
3398 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3400 case OP_COND_EXC_OV:
3401 case OP_COND_EXC_NO:
3403 case OP_COND_EXC_NC:
3404 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3406 case OP_COND_EXC_IOV:
3407 case OP_COND_EXC_INO:
3408 case OP_COND_EXC_IC:
3409 case OP_COND_EXC_INC:
3410 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3422 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3430 case OP_CMOV_INE_UN:
3431 case OP_CMOV_IGE_UN:
3432 case OP_CMOV_IGT_UN:
3433 case OP_CMOV_ILE_UN:
3434 case OP_CMOV_ILT_UN:
3435 g_assert (ins->dreg == ins->sreg1);
3436 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3439 /* floating point opcodes */
3441 double d = *(double *)ins->inst_p0;
3443 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3445 } else if (d == 1.0) {
3448 if (cfg->compile_aot) {
3449 guint32 *val = (guint32*)&d;
3450 x86_push_imm (code, val [1]);
3451 x86_push_imm (code, val [0]);
3452 x86_fld_membase (code, X86_ESP, 0, TRUE);
3453 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3456 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3457 x86_fld (code, NULL, TRUE);
3463 float f = *(float *)ins->inst_p0;
3465 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3467 } else if (f == 1.0) {
3470 if (cfg->compile_aot) {
3471 guint32 val = *(guint32*)&f;
3472 x86_push_imm (code, val);
3473 x86_fld_membase (code, X86_ESP, 0, FALSE);
3474 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3477 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3478 x86_fld (code, NULL, FALSE);
3483 case OP_STORER8_MEMBASE_REG:
3484 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3486 case OP_LOADR8_MEMBASE:
3487 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3489 case OP_STORER4_MEMBASE_REG:
3490 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3492 case OP_LOADR4_MEMBASE:
3493 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3495 case OP_ICONV_TO_R4:
3496 x86_push_reg (code, ins->sreg1);
3497 x86_fild_membase (code, X86_ESP, 0, FALSE);
3498 /* Change precision */
3499 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3500 x86_fld_membase (code, X86_ESP, 0, FALSE);
3501 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3503 case OP_ICONV_TO_R8:
3504 x86_push_reg (code, ins->sreg1);
3505 x86_fild_membase (code, X86_ESP, 0, FALSE);
3506 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3508 case OP_ICONV_TO_R_UN:
3509 x86_push_imm (code, 0);
3510 x86_push_reg (code, ins->sreg1);
3511 x86_fild_membase (code, X86_ESP, 0, TRUE);
3512 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3514 case OP_X86_FP_LOAD_I8:
3515 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3517 case OP_X86_FP_LOAD_I4:
3518 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3520 case OP_FCONV_TO_R4:
3521 /* Change precision */
3522 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3523 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3524 x86_fld_membase (code, X86_ESP, 0, FALSE);
3525 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3527 case OP_FCONV_TO_I1:
3528 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3530 case OP_FCONV_TO_U1:
3531 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3533 case OP_FCONV_TO_I2:
3534 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3536 case OP_FCONV_TO_U2:
3537 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3539 case OP_FCONV_TO_I4:
3541 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3543 case OP_FCONV_TO_I8:
3544 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3545 x86_fnstcw_membase(code, X86_ESP, 0);
3546 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3547 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3548 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3549 x86_fldcw_membase (code, X86_ESP, 2);
3550 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3551 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3552 x86_pop_reg (code, ins->dreg);
3553 x86_pop_reg (code, ins->backend.reg3);
3554 x86_fldcw_membase (code, X86_ESP, 0);
3555 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3557 case OP_LCONV_TO_R8_2:
3558 x86_push_reg (code, ins->sreg2);
3559 x86_push_reg (code, ins->sreg1);
3560 x86_fild_membase (code, X86_ESP, 0, TRUE);
3561 /* Change precision */
3562 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3563 x86_fld_membase (code, X86_ESP, 0, TRUE);
3564 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3566 case OP_LCONV_TO_R4_2:
3567 x86_push_reg (code, ins->sreg2);
3568 x86_push_reg (code, ins->sreg1);
3569 x86_fild_membase (code, X86_ESP, 0, TRUE);
3570 /* Change precision */
3571 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3572 x86_fld_membase (code, X86_ESP, 0, FALSE);
3573 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3575 case OP_LCONV_TO_R_UN_2: {
3576 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3579 /* load 64bit integer to FP stack */
3580 x86_push_reg (code, ins->sreg2);
3581 x86_push_reg (code, ins->sreg1);
3582 x86_fild_membase (code, X86_ESP, 0, TRUE);
3584 /* test if lreg is negative */
3585 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3586 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3588 /* add correction constant mn */
3589 if (cfg->compile_aot) {
3590 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3591 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3592 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3593 x86_fld80_membase (code, X86_ESP, 2);
3594 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3596 x86_fld80_mem (code, mn);
3598 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3600 x86_patch (br, code);
3602 /* Change precision */
3603 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3604 x86_fld_membase (code, X86_ESP, 0, TRUE);
3606 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3610 case OP_LCONV_TO_OVF_I:
3611 case OP_LCONV_TO_OVF_I4_2: {
3612 guint8 *br [3], *label [1];
3616 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3618 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3620 /* If the low word top bit is set, see if we are negative */
3621 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3622 /* We are not negative (no top bit set, check for our top word to be zero */
3623 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3624 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3627 /* throw exception */
3628 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3630 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3631 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3632 x86_jump8 (code, 0);
3634 x86_jump32 (code, 0);
3636 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3637 x86_jump32 (code, 0);
3641 x86_patch (br [0], code);
3642 /* our top bit is set, check that top word is 0xfffffff */
3643 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3645 x86_patch (br [1], code);
3646 /* nope, emit exception */
3647 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3648 x86_patch (br [2], label [0]);
3650 if (ins->dreg != ins->sreg1)
3651 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3655 /* Not needed on the fp stack */
3658 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3661 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3664 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3667 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3675 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3680 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3687 * it really doesn't make sense to inline all this code,
3688 * it's here just to show that things may not be as simple
3691 guchar *check_pos, *end_tan, *pop_jump;
3692 x86_push_reg (code, X86_EAX);
3695 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3697 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3698 x86_fstp (code, 0); /* pop the 1.0 */
3700 x86_jump8 (code, 0);
3702 x86_fp_op (code, X86_FADD, 0);
3706 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3708 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3711 x86_patch (pop_jump, code);
3712 x86_fstp (code, 0); /* pop the 1.0 */
3713 x86_patch (check_pos, code);
3714 x86_patch (end_tan, code);
3716 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3717 x86_pop_reg (code, X86_EAX);
3724 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3733 g_assert (cfg->opt & MONO_OPT_CMOV);
3734 g_assert (ins->dreg == ins->sreg1);
3735 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3736 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3739 g_assert (cfg->opt & MONO_OPT_CMOV);
3740 g_assert (ins->dreg == ins->sreg1);
3741 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3742 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3745 g_assert (cfg->opt & MONO_OPT_CMOV);
3746 g_assert (ins->dreg == ins->sreg1);
3747 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3748 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3751 g_assert (cfg->opt & MONO_OPT_CMOV);
3752 g_assert (ins->dreg == ins->sreg1);
3753 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3754 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3760 x86_fxch (code, ins->inst_imm);
3765 x86_push_reg (code, X86_EAX);
3766 /* we need to exchange ST(0) with ST(1) */
3769 /* this requires a loop, because fprem somtimes
3770 * returns a partial remainder */
3772 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3773 /* x86_fprem1 (code); */
3776 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3778 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3784 x86_pop_reg (code, X86_EAX);
3788 if (cfg->opt & MONO_OPT_FCMOV) {
3789 x86_fcomip (code, 1);
3793 /* this overwrites EAX */
3794 EMIT_FPCOMPARE(code);
3795 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3798 if (cfg->opt & MONO_OPT_FCMOV) {
3799 /* zeroing the register at the start results in
3800 * shorter and faster code (we can also remove the widening op)
3802 guchar *unordered_check;
3803 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3804 x86_fcomip (code, 1);
3806 unordered_check = code;
3807 x86_branch8 (code, X86_CC_P, 0, FALSE);
3808 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3809 x86_patch (unordered_check, code);
3812 if (ins->dreg != X86_EAX)
3813 x86_push_reg (code, X86_EAX);
3815 EMIT_FPCOMPARE(code);
3816 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3817 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3818 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3819 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3821 if (ins->dreg != X86_EAX)
3822 x86_pop_reg (code, X86_EAX);
3826 if (cfg->opt & MONO_OPT_FCMOV) {
3827 /* zeroing the register at the start results in
3828 * shorter and faster code (we can also remove the widening op)
3830 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3831 x86_fcomip (code, 1);
3833 if (ins->opcode == OP_FCLT_UN) {
3834 guchar *unordered_check = code;
3835 guchar *jump_to_end;
3836 x86_branch8 (code, X86_CC_P, 0, FALSE);
3837 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3839 x86_jump8 (code, 0);
3840 x86_patch (unordered_check, code);
3841 x86_inc_reg (code, ins->dreg);
3842 x86_patch (jump_to_end, code);
3844 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3848 if (ins->dreg != X86_EAX)
3849 x86_push_reg (code, X86_EAX);
3851 EMIT_FPCOMPARE(code);
3852 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3853 if (ins->opcode == OP_FCLT_UN) {
3854 guchar *is_not_zero_check, *end_jump;
3855 is_not_zero_check = code;
3856 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3858 x86_jump8 (code, 0);
3859 x86_patch (is_not_zero_check, code);
3860 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3862 x86_patch (end_jump, code);
3864 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3865 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3867 if (ins->dreg != X86_EAX)
3868 x86_pop_reg (code, X86_EAX);
3872 if (cfg->opt & MONO_OPT_FCMOV) {
3873 /* zeroing the register at the start results in
3874 * shorter and faster code (we can also remove the widening op)
3876 guchar *unordered_check;
3877 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3878 x86_fcomip (code, 1);
3880 if (ins->opcode == OP_FCGT) {
3881 unordered_check = code;
3882 x86_branch8 (code, X86_CC_P, 0, FALSE);
3883 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3884 x86_patch (unordered_check, code);
3886 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3890 if (ins->dreg != X86_EAX)
3891 x86_push_reg (code, X86_EAX);
3893 EMIT_FPCOMPARE(code);
3894 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3895 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3896 if (ins->opcode == OP_FCGT_UN) {
3897 guchar *is_not_zero_check, *end_jump;
3898 is_not_zero_check = code;
3899 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3901 x86_jump8 (code, 0);
3902 x86_patch (is_not_zero_check, code);
3903 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3905 x86_patch (end_jump, code);
3907 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3908 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3910 if (ins->dreg != X86_EAX)
3911 x86_pop_reg (code, X86_EAX);
3914 if (cfg->opt & MONO_OPT_FCMOV) {
3915 guchar *jump = code;
3916 x86_branch8 (code, X86_CC_P, 0, TRUE);
3917 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3918 x86_patch (jump, code);
3921 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3922 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3925 /* Branch if C013 != 100 */
3926 if (cfg->opt & MONO_OPT_FCMOV) {
3927 /* branch if !ZF or (PF|CF) */
3928 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3929 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3930 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3933 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3934 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3937 if (cfg->opt & MONO_OPT_FCMOV) {
3938 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3941 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3944 if (cfg->opt & MONO_OPT_FCMOV) {
3945 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3946 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3949 if (ins->opcode == OP_FBLT_UN) {
3950 guchar *is_not_zero_check, *end_jump;
3951 is_not_zero_check = code;
3952 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3954 x86_jump8 (code, 0);
3955 x86_patch (is_not_zero_check, code);
3956 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3958 x86_patch (end_jump, code);
3960 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3964 if (cfg->opt & MONO_OPT_FCMOV) {
3965 if (ins->opcode == OP_FBGT) {
3968 /* skip branch if C1=1 */
3970 x86_branch8 (code, X86_CC_P, 0, FALSE);
3971 /* branch if (C0 | C3) = 1 */
3972 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3973 x86_patch (br1, code);
3975 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3979 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3980 if (ins->opcode == OP_FBGT_UN) {
3981 guchar *is_not_zero_check, *end_jump;
3982 is_not_zero_check = code;
3983 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3985 x86_jump8 (code, 0);
3986 x86_patch (is_not_zero_check, code);
3987 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3989 x86_patch (end_jump, code);
3991 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3994 /* Branch if C013 == 100 or 001 */
3995 if (cfg->opt & MONO_OPT_FCMOV) {
3998 /* skip branch if C1=1 */
4000 x86_branch8 (code, X86_CC_P, 0, FALSE);
4001 /* branch if (C0 | C3) = 1 */
4002 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4003 x86_patch (br1, code);
4006 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4007 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4008 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4009 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4012 /* Branch if C013 == 000 */
4013 if (cfg->opt & MONO_OPT_FCMOV) {
4014 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4017 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4020 /* Branch if C013=000 or 100 */
4021 if (cfg->opt & MONO_OPT_FCMOV) {
4024 /* skip branch if C1=1 */
4026 x86_branch8 (code, X86_CC_P, 0, FALSE);
4027 /* branch if C0=0 */
4028 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4029 x86_patch (br1, code);
4032 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4033 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4034 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4037 /* Branch if C013 != 001 */
4038 if (cfg->opt & MONO_OPT_FCMOV) {
4039 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4040 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4043 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4044 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4048 x86_push_reg (code, X86_EAX);
4051 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4052 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4053 x86_pop_reg (code, X86_EAX);
4055 /* Have to clean up the fp stack before throwing the exception */
4057 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4060 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4062 x86_patch (br1, code);
4066 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4069 case OP_TLS_GET_REG: {
4071 // FIXME: tls_gs_offset can change too, do these when calculating the tls offset
4072 if (ins->dreg != ins->sreg1)
4073 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
4074 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4076 x86_alu_reg_imm (code, X86_ADD, ins->dreg, tls_gs_offset);
4077 x86_prefix (code, X86_GS_PREFIX);
4078 x86_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof (gpointer));
4080 g_assert_not_reached ();
4084 case OP_MEMORY_BARRIER: {
4085 /* x86 only needs barrier for StoreLoad and FullBarrier */
4086 switch (ins->backend.memory_barrier_kind) {
4087 case StoreLoadBarrier:
4089 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4090 x86_prefix (code, X86_LOCK_PREFIX);
4091 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4096 case OP_ATOMIC_ADD_I4: {
4097 int dreg = ins->dreg;
4099 if (dreg == ins->inst_basereg) {
4100 x86_push_reg (code, ins->sreg2);
4104 if (dreg != ins->sreg2)
4105 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
4107 x86_prefix (code, X86_LOCK_PREFIX);
4108 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4110 if (dreg != ins->dreg) {
4111 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4112 x86_pop_reg (code, dreg);
4117 case OP_ATOMIC_ADD_NEW_I4: {
4118 int dreg = ins->dreg;
4120 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4121 if (ins->sreg2 == dreg) {
4122 if (dreg == X86_EBX) {
4124 if (ins->inst_basereg == X86_EDI)
4128 if (ins->inst_basereg == X86_EBX)
4131 } else if (ins->inst_basereg == dreg) {
4132 if (dreg == X86_EBX) {
4134 if (ins->sreg2 == X86_EDI)
4138 if (ins->sreg2 == X86_EBX)
4143 if (dreg != ins->dreg) {
4144 x86_push_reg (code, dreg);
4147 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4148 x86_prefix (code, X86_LOCK_PREFIX);
4149 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4150 /* dreg contains the old value, add with sreg2 value */
4151 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4153 if (ins->dreg != dreg) {
4154 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4155 x86_pop_reg (code, dreg);
4160 case OP_ATOMIC_EXCHANGE_I4: {
4162 int sreg2 = ins->sreg2;
4163 int breg = ins->inst_basereg;
4165 /* cmpxchg uses eax as comperand, need to make sure we can use it
4166 * hack to overcome limits in x86 reg allocator
4167 * (req: dreg == eax and sreg2 != eax and breg != eax)
4169 g_assert (ins->dreg == X86_EAX);
4171 /* We need the EAX reg for the cmpxchg */
4172 if (ins->sreg2 == X86_EAX) {
4173 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4174 x86_push_reg (code, sreg2);
4175 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4178 if (breg == X86_EAX) {
4179 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4180 x86_push_reg (code, breg);
4181 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4184 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4186 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4187 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4188 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4189 x86_patch (br [1], br [0]);
4191 if (breg != ins->inst_basereg)
4192 x86_pop_reg (code, breg);
4194 if (ins->sreg2 != sreg2)
4195 x86_pop_reg (code, sreg2);
4199 case OP_ATOMIC_CAS_I4: {
4200 g_assert (ins->dreg == X86_EAX);
4201 g_assert (ins->sreg3 == X86_EAX);
4202 g_assert (ins->sreg1 != X86_EAX);
4203 g_assert (ins->sreg1 != ins->sreg2);
4205 x86_prefix (code, X86_LOCK_PREFIX);
4206 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4209 case OP_CARD_TABLE_WBARRIER: {
4210 int ptr = ins->sreg1;
4211 int value = ins->sreg2;
4213 int nursery_shift, card_table_shift;
4214 gpointer card_table_mask;
4215 size_t nursery_size;
4216 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4217 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4218 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4221 * We need one register we can clobber, we choose EDX and make sreg1
4222 * fixed EAX to work around limitations in the local register allocator.
4223 * sreg2 might get allocated to EDX, but that is not a problem since
4224 * we use it before clobbering EDX.
4226 g_assert (ins->sreg1 == X86_EAX);
4229 * This is the code we produce:
4232 * edx >>= nursery_shift
4233 * cmp edx, (nursery_start >> nursery_shift)
4236 * edx >>= card_table_shift
4237 * card_table[edx] = 1
4241 if (card_table_nursery_check) {
4242 if (value != X86_EDX)
4243 x86_mov_reg_reg (code, X86_EDX, value, 4);
4244 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4245 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4246 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4248 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4249 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4250 if (card_table_mask)
4251 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4252 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4253 if (card_table_nursery_check)
4254 x86_patch (br, code);
4257 #ifdef MONO_ARCH_SIMD_INTRINSICS
4259 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4262 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4265 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4268 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4271 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4274 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4277 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4278 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4281 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4284 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4287 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4290 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4293 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4296 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4299 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4302 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4305 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4308 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4311 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4314 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4317 case OP_PSHUFLEW_HIGH:
4318 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4319 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4321 case OP_PSHUFLEW_LOW:
4322 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4323 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4326 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4327 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4330 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4331 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4334 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4335 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4339 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4342 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4345 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4348 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4351 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4354 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4357 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4358 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4361 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4364 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4367 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4370 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4373 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4376 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4379 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4382 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4385 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4388 case OP_EXTRACT_MASK:
4389 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4393 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4396 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4399 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4403 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4406 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4409 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4412 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4416 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4419 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4422 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4425 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4429 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4432 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4435 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4439 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4442 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4445 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4449 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4452 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4456 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4459 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4462 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4466 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4469 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4472 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4476 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4479 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4482 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4485 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4489 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4492 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4495 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4498 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4501 case OP_PSUM_ABS_DIFF:
4502 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4505 case OP_UNPACK_LOWB:
4506 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4508 case OP_UNPACK_LOWW:
4509 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4511 case OP_UNPACK_LOWD:
4512 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4514 case OP_UNPACK_LOWQ:
4515 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4517 case OP_UNPACK_LOWPS:
4518 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4520 case OP_UNPACK_LOWPD:
4521 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4524 case OP_UNPACK_HIGHB:
4525 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4527 case OP_UNPACK_HIGHW:
4528 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4530 case OP_UNPACK_HIGHD:
4531 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4533 case OP_UNPACK_HIGHQ:
4534 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4536 case OP_UNPACK_HIGHPS:
4537 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4539 case OP_UNPACK_HIGHPD:
4540 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4544 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4547 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4550 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4553 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4556 case OP_PADDB_SAT_UN:
4557 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4559 case OP_PSUBB_SAT_UN:
4560 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4562 case OP_PADDW_SAT_UN:
4563 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4565 case OP_PSUBW_SAT_UN:
4566 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4570 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4573 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4576 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4579 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4583 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4586 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4589 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4591 case OP_PMULW_HIGH_UN:
4592 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4595 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4599 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4602 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4606 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4609 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4613 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4616 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4620 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4623 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4627 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4630 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4634 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4637 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4641 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4644 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4648 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4651 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4655 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4658 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4662 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4664 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4665 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4669 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4671 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4672 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4676 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4678 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4679 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4683 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4685 case OP_EXTRACTX_U2:
4686 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4688 case OP_INSERTX_U1_SLOW:
4689 /*sreg1 is the extracted ireg (scratch)
4690 /sreg2 is the to be inserted ireg (scratch)
4691 /dreg is the xreg to receive the value*/
4693 /*clear the bits from the extracted word*/
4694 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4695 /*shift the value to insert if needed*/
4696 if (ins->inst_c0 & 1)
4697 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4698 /*join them together*/
4699 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4700 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4702 case OP_INSERTX_I4_SLOW:
4703 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4704 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4705 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4708 case OP_INSERTX_R4_SLOW:
4709 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4710 /*TODO if inst_c0 == 0 use movss*/
4711 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4712 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4714 case OP_INSERTX_R8_SLOW:
4715 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4716 if (cfg->verbose_level)
4717 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4719 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4721 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4724 case OP_STOREX_MEMBASE_REG:
4725 case OP_STOREX_MEMBASE:
4726 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4728 case OP_LOADX_MEMBASE:
4729 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4731 case OP_LOADX_ALIGNED_MEMBASE:
4732 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4734 case OP_STOREX_ALIGNED_MEMBASE_REG:
4735 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4737 case OP_STOREX_NTA_MEMBASE_REG:
4738 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4740 case OP_PREFETCH_MEMBASE:
4741 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4745 /*FIXME the peephole pass should have killed this*/
4746 if (ins->dreg != ins->sreg1)
4747 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4750 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4752 case OP_ICONV_TO_R8_RAW:
4753 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4754 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4757 case OP_FCONV_TO_R8_X:
4758 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4759 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4762 case OP_XCONV_R8_TO_I4:
4763 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4764 switch (ins->backend.source_opcode) {
4765 case OP_FCONV_TO_I1:
4766 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4768 case OP_FCONV_TO_U1:
4769 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4771 case OP_FCONV_TO_I2:
4772 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4774 case OP_FCONV_TO_U2:
4775 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4781 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4782 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4783 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4784 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4785 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4786 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4789 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4790 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4791 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4794 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4795 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4798 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4799 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4800 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4803 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4804 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4805 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4809 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4812 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4815 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4818 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4821 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4824 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4827 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4830 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4834 case OP_LIVERANGE_START: {
4835 if (cfg->verbose_level > 1)
4836 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4837 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4840 case OP_LIVERANGE_END: {
4841 if (cfg->verbose_level > 1)
4842 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4843 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4846 case OP_NACL_GC_SAFE_POINT: {
4847 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
4848 if (cfg->compile_aot)
4849 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
4853 x86_test_mem_imm8 (code, (gpointer)&__nacl_thread_suspension_needed, 0xFFFFFFFF);
4854 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4855 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
4856 x86_patch (br[0], code);
4861 case OP_GC_LIVENESS_DEF:
4862 case OP_GC_LIVENESS_USE:
4863 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4864 ins->backend.pc_offset = code - cfg->native_code;
4866 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4867 ins->backend.pc_offset = code - cfg->native_code;
4868 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4871 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4872 g_assert_not_reached ();
4875 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4876 #ifndef __native_client_codegen__
4877 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4878 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4879 g_assert_not_reached ();
4880 #endif /* __native_client_codegen__ */
4886 cfg->code_len = code - cfg->native_code;
4889 #endif /* DISABLE_JIT */
4892 mono_arch_register_lowlevel_calls (void)
4897 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4899 MonoJumpInfo *patch_info;
4900 gboolean compile_aot = !run_cctors;
4902 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4903 unsigned char *ip = patch_info->ip.i + code;
4904 const unsigned char *target;
4906 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4909 switch (patch_info->type) {
4910 case MONO_PATCH_INFO_BB:
4911 case MONO_PATCH_INFO_LABEL:
4914 /* No need to patch these */
4919 switch (patch_info->type) {
4920 case MONO_PATCH_INFO_IP:
4921 *((gconstpointer *)(ip)) = target;
4923 case MONO_PATCH_INFO_CLASS_INIT: {
4925 /* Might already been changed to a nop */
4926 x86_call_code (code, 0);
4927 x86_patch (ip, target);
4930 case MONO_PATCH_INFO_ABS:
4931 case MONO_PATCH_INFO_METHOD:
4932 case MONO_PATCH_INFO_METHOD_JUMP:
4933 case MONO_PATCH_INFO_INTERNAL_METHOD:
4934 case MONO_PATCH_INFO_BB:
4935 case MONO_PATCH_INFO_LABEL:
4936 case MONO_PATCH_INFO_RGCTX_FETCH:
4937 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
4938 case MONO_PATCH_INFO_MONITOR_ENTER:
4939 case MONO_PATCH_INFO_MONITOR_EXIT:
4940 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
4941 #if defined(__native_client_codegen__) && defined(__native_client__)
4942 if (nacl_is_code_address (code)) {
4943 /* For tail calls, code is patched after being installed */
4944 /* but not through the normal "patch callsite" method. */
4945 unsigned char buf[kNaClAlignment];
4946 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
4947 unsigned char *_target = target;
4949 /* All patch targets modified in x86_patch */
4950 /* are IP relative. */
4951 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
4952 memcpy (buf, aligned_code, kNaClAlignment);
4953 /* Patch a temp buffer of bundle size, */
4954 /* then install to actual location. */
4955 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
4956 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
4957 g_assert (ret == 0);
4960 x86_patch (ip, target);
4963 x86_patch (ip, target);
4966 case MONO_PATCH_INFO_NONE:
4968 case MONO_PATCH_INFO_R4:
4969 case MONO_PATCH_INFO_R8: {
4970 guint32 offset = mono_arch_get_patch_offset (ip);
4971 *((gconstpointer *)(ip + offset)) = target;
4975 guint32 offset = mono_arch_get_patch_offset (ip);
4976 #if !defined(__native_client__)
4977 *((gconstpointer *)(ip + offset)) = target;
4979 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
4987 static G_GNUC_UNUSED void
4988 stack_unaligned (MonoMethod *m, gpointer caller)
4990 printf ("%s\n", mono_method_full_name (m, TRUE));
4991 g_assert_not_reached ();
4995 mono_arch_emit_prolog (MonoCompile *cfg)
4997 MonoMethod *method = cfg->method;
4999 MonoMethodSignature *sig;
5001 int alloc_size, pos, max_offset, i, cfa_offset;
5003 gboolean need_stack_frame;
5004 #ifdef __native_client_codegen__
5005 guint alignment_check;
5008 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5010 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5011 cfg->code_size += 512;
5013 #if defined(__default_codegen__)
5014 code = cfg->native_code = g_malloc (cfg->code_size);
5015 #elif defined(__native_client_codegen__)
5016 /* native_code_alloc is not 32-byte aligned, native_code is. */
5017 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5018 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5020 /* Align native_code to next nearest kNaclAlignment byte. */
5021 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5022 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5024 code = cfg->native_code;
5026 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5027 g_assert(alignment_check == 0);
5034 /* Check that the stack is aligned on osx */
5035 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5036 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5037 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5039 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5040 x86_push_membase (code, X86_ESP, 0);
5041 x86_push_imm (code, cfg->method);
5042 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5043 x86_call_reg (code, X86_EAX);
5044 x86_patch (br [0], code);
5048 /* Offset between RSP and the CFA */
5052 cfa_offset = sizeof (gpointer);
5053 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5054 // IP saved at CFA - 4
5055 /* There is no IP reg on x86 */
5056 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5057 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5059 need_stack_frame = needs_stack_frame (cfg);
5061 if (need_stack_frame) {
5062 x86_push_reg (code, X86_EBP);
5063 cfa_offset += sizeof (gpointer);
5064 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5065 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5066 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5067 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5068 /* These are handled automatically by the stack marking code */
5069 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5071 cfg->frame_reg = X86_ESP;
5074 alloc_size = cfg->stack_offset;
5077 if (method->save_lmf) {
5078 pos += sizeof (MonoLMF);
5080 /* save the current IP */
5081 if (cfg->compile_aot) {
5082 /* This pushes the current ip */
5083 x86_call_imm (code, 0);
5085 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
5086 x86_push_imm_template (code);
5088 cfa_offset += sizeof (gpointer);
5089 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5091 /* save all caller saved regs */
5092 x86_push_reg (code, X86_EBP);
5093 cfa_offset += sizeof (gpointer);
5094 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5095 x86_push_reg (code, X86_ESI);
5096 cfa_offset += sizeof (gpointer);
5097 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5098 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5099 x86_push_reg (code, X86_EDI);
5100 cfa_offset += sizeof (gpointer);
5101 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5102 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5103 x86_push_reg (code, X86_EBX);
5104 cfa_offset += sizeof (gpointer);
5105 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5106 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5108 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5110 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5111 * through the mono_lmf_addr TLS variable.
5113 /* %eax = previous_lmf */
5114 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_tls_offset);
5115 /* skip esp + method_info + lmf */
5116 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 12);
5118 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5119 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + 4, SLOT_NOREF);
5120 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + 8, SLOT_NOREF);
5121 /* push previous_lmf */
5122 x86_push_reg (code, X86_EAX);
5124 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5126 code = mono_x86_emit_tls_set (code, X86_ESP, lmf_tls_offset);
5128 /* get the address of lmf for the current thread */
5130 * This is performance critical so we try to use some tricks to make
5133 gboolean have_fastpath = FALSE;
5136 if (jit_tls_offset != -1) {
5137 code = mono_x86_emit_tls_get (code, X86_EAX, jit_tls_offset);
5138 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5139 have_fastpath = TRUE;
5142 if (lmf_addr_tls_offset != -1) {
5143 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
5144 have_fastpath = TRUE;
5147 if (!have_fastpath) {
5148 if (cfg->compile_aot)
5149 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
5150 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
5153 /* Skip esp + method info */
5154 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
5157 x86_push_reg (code, X86_EAX);
5158 /* push *lfm (previous_lmf) */
5159 x86_push_membase (code, X86_EAX, 0);
5161 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
5165 if (cfg->used_int_regs & (1 << X86_EBX)) {
5166 x86_push_reg (code, X86_EBX);
5168 cfa_offset += sizeof (gpointer);
5169 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5170 /* These are handled automatically by the stack marking code */
5171 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5174 if (cfg->used_int_regs & (1 << X86_EDI)) {
5175 x86_push_reg (code, X86_EDI);
5177 cfa_offset += sizeof (gpointer);
5178 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5179 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5182 if (cfg->used_int_regs & (1 << X86_ESI)) {
5183 x86_push_reg (code, X86_ESI);
5185 cfa_offset += sizeof (gpointer);
5186 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5187 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5193 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5194 if (mono_do_x86_stack_align && need_stack_frame) {
5195 int tot = alloc_size + pos + 4; /* ret ip */
5196 if (need_stack_frame)
5198 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5200 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5201 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5202 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5206 cfg->arch.sp_fp_offset = alloc_size + pos;
5209 /* See mono_emit_stack_alloc */
5210 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5211 guint32 remaining_size = alloc_size;
5212 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5213 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5214 guint32 offset = code - cfg->native_code;
5215 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5216 while (required_code_size >= (cfg->code_size - offset))
5217 cfg->code_size *= 2;
5218 cfg->native_code = mono_realloc_native_code(cfg);
5219 code = cfg->native_code + offset;
5220 cfg->stat_code_reallocs++;
5222 while (remaining_size >= 0x1000) {
5223 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5224 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5225 remaining_size -= 0x1000;
5228 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5230 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5233 g_assert (need_stack_frame);
5236 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5237 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5238 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5241 #if DEBUG_STACK_ALIGNMENT
5242 /* check the stack is aligned */
5243 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5244 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5245 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5246 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5247 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5248 x86_breakpoint (code);
5252 /* compute max_offset in order to use short forward jumps */
5254 if (cfg->opt & MONO_OPT_BRANCH) {
5255 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5257 bb->max_offset = max_offset;
5259 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5261 /* max alignment for loops */
5262 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5263 max_offset += LOOP_ALIGNMENT;
5264 #ifdef __native_client_codegen__
5265 /* max alignment for native client */
5266 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5267 max_offset += kNaClAlignment;
5269 MONO_BB_FOR_EACH_INS (bb, ins) {
5270 if (ins->opcode == OP_LABEL)
5271 ins->inst_c1 = max_offset;
5272 #ifdef __native_client_codegen__
5273 switch (ins->opcode)
5285 case OP_VOIDCALL_REG:
5287 case OP_FCALL_MEMBASE:
5288 case OP_LCALL_MEMBASE:
5289 case OP_VCALL_MEMBASE:
5290 case OP_VCALL2_MEMBASE:
5291 case OP_VOIDCALL_MEMBASE:
5292 case OP_CALL_MEMBASE:
5293 max_offset += kNaClAlignment;
5296 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5299 #endif /* __native_client_codegen__ */
5300 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5305 /* store runtime generic context */
5306 if (cfg->rgctx_var) {
5307 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5309 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5312 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5313 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5315 /* load arguments allocated to register from the stack */
5316 sig = mono_method_signature (method);
5319 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5320 inst = cfg->args [pos];
5321 if (inst->opcode == OP_REGVAR) {
5322 g_assert (need_stack_frame);
5323 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5324 if (cfg->verbose_level > 2)
5325 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5330 cfg->code_len = code - cfg->native_code;
5332 g_assert (cfg->code_len < cfg->code_size);
5338 mono_arch_emit_epilog (MonoCompile *cfg)
5340 MonoMethod *method = cfg->method;
5341 MonoMethodSignature *sig = mono_method_signature (method);
5343 guint32 stack_to_pop;
5345 int max_epilog_size = 16;
5347 gboolean need_stack_frame = needs_stack_frame (cfg);
5349 if (cfg->method->save_lmf)
5350 max_epilog_size += 128;
5352 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5353 cfg->code_size *= 2;
5354 cfg->native_code = mono_realloc_native_code(cfg);
5355 cfg->stat_code_reallocs++;
5358 code = cfg->native_code + cfg->code_len;
5360 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5361 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5363 /* the code restoring the registers must be kept in sync with OP_JMP */
5366 if (method->save_lmf) {
5367 gint32 prev_lmf_reg;
5368 gint32 lmf_offset = -sizeof (MonoLMF);
5370 /* check if we need to restore protection of the stack after a stack overflow */
5371 if (mono_get_jit_tls_offset () != -1) {
5373 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5374 /* we load the value in a separate instruction: this mechanism may be
5375 * used later as a safer way to do thread interruption
5377 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5378 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5380 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5381 /* note that the call trampoline will preserve eax/edx */
5382 x86_call_reg (code, X86_ECX);
5383 x86_patch (patch, code);
5385 /* FIXME: maybe save the jit tls in the prolog */
5387 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5389 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5390 * through the mono_lmf_addr TLS variable.
5392 /* reg = previous_lmf */
5393 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5395 /* lmf = previous_lmf */
5396 code = mono_x86_emit_tls_set (code, X86_ECX, lmf_tls_offset);
5398 /* Find a spare register */
5399 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
5402 prev_lmf_reg = X86_EDI;
5403 cfg->used_int_regs |= (1 << X86_EDI);
5406 prev_lmf_reg = X86_EDX;
5410 /* reg = previous_lmf */
5411 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5414 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
5416 /* *(lmf) = previous_lmf */
5417 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
5420 /* restore caller saved regs */
5421 if (cfg->used_int_regs & (1 << X86_EBX)) {
5422 x86_mov_reg_membase (code, X86_EBX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
5425 if (cfg->used_int_regs & (1 << X86_EDI)) {
5426 x86_mov_reg_membase (code, X86_EDI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
5428 if (cfg->used_int_regs & (1 << X86_ESI)) {
5429 x86_mov_reg_membase (code, X86_ESI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
5432 /* EBP is restored by LEAVE */
5434 if (cfg->used_int_regs & (1 << X86_EBX)) {
5437 if (cfg->used_int_regs & (1 << X86_EDI)) {
5440 if (cfg->used_int_regs & (1 << X86_ESI)) {
5445 g_assert (need_stack_frame);
5446 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5449 if (cfg->used_int_regs & (1 << X86_ESI)) {
5450 x86_pop_reg (code, X86_ESI);
5452 if (cfg->used_int_regs & (1 << X86_EDI)) {
5453 x86_pop_reg (code, X86_EDI);
5455 if (cfg->used_int_regs & (1 << X86_EBX)) {
5456 x86_pop_reg (code, X86_EBX);
5460 /* Load returned vtypes into registers if needed */
5461 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5462 if (cinfo->ret.storage == ArgValuetypeInReg) {
5463 for (quad = 0; quad < 2; quad ++) {
5464 switch (cinfo->ret.pair_storage [quad]) {
5466 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5468 case ArgOnFloatFpStack:
5469 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5471 case ArgOnDoubleFpStack:
5472 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5477 g_assert_not_reached ();
5482 if (need_stack_frame)
5485 if (CALLCONV_IS_STDCALL (sig)) {
5486 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5488 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5489 } else if (cinfo->vtype_retaddr)
5495 g_assert (need_stack_frame);
5496 x86_ret_imm (code, stack_to_pop);
5501 cfg->code_len = code - cfg->native_code;
5503 g_assert (cfg->code_len < cfg->code_size);
5507 mono_arch_emit_exceptions (MonoCompile *cfg)
5509 MonoJumpInfo *patch_info;
5512 MonoClass *exc_classes [16];
5513 guint8 *exc_throw_start [16], *exc_throw_end [16];
5517 /* Compute needed space */
5518 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5519 if (patch_info->type == MONO_PATCH_INFO_EXC)
5524 * make sure we have enough space for exceptions
5525 * 16 is the size of two push_imm instructions and a call
5527 if (cfg->compile_aot)
5528 code_size = exc_count * 32;
5530 code_size = exc_count * 16;
5532 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5533 cfg->code_size *= 2;
5534 cfg->native_code = mono_realloc_native_code(cfg);
5535 cfg->stat_code_reallocs++;
5538 code = cfg->native_code + cfg->code_len;
5541 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5542 switch (patch_info->type) {
5543 case MONO_PATCH_INFO_EXC: {
5544 MonoClass *exc_class;
5548 x86_patch (patch_info->ip.i + cfg->native_code, code);
5550 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5551 g_assert (exc_class);
5552 throw_ip = patch_info->ip.i;
5554 /* Find a throw sequence for the same exception class */
5555 for (i = 0; i < nthrows; ++i)
5556 if (exc_classes [i] == exc_class)
5559 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5560 x86_jump_code (code, exc_throw_start [i]);
5561 patch_info->type = MONO_PATCH_INFO_NONE;
5566 /* Compute size of code following the push <OFFSET> */
5567 #if defined(__default_codegen__)
5569 #elif defined(__native_client_codegen__)
5570 code = mono_nacl_align (code);
5571 size = kNaClAlignment;
5573 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5575 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5576 /* Use the shorter form */
5578 x86_push_imm (code, 0);
5582 x86_push_imm (code, 0xf0f0f0f0);
5587 exc_classes [nthrows] = exc_class;
5588 exc_throw_start [nthrows] = code;
5591 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5592 patch_info->data.name = "mono_arch_throw_corlib_exception";
5593 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5594 patch_info->ip.i = code - cfg->native_code;
5595 x86_call_code (code, 0);
5596 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5601 exc_throw_end [nthrows] = code;
5613 cfg->code_len = code - cfg->native_code;
5615 g_assert (cfg->code_len < cfg->code_size);
5619 mono_arch_flush_icache (guint8 *code, gint size)
5625 mono_arch_flush_register_windows (void)
5630 mono_arch_is_inst_imm (gint64 imm)
5636 mono_arch_finish_init (void)
5638 if (!getenv ("MONO_NO_TLS")) {
5641 * We need to init this multiple times, since when we are first called, the key might not
5642 * be initialized yet.
5644 appdomain_tls_offset = mono_domain_get_tls_key ();
5645 jit_tls_offset = mono_get_jit_tls_key ();
5647 /* Only 64 tls entries can be accessed using inline code */
5648 if (appdomain_tls_offset >= 64)
5649 appdomain_tls_offset = -1;
5650 if (jit_tls_offset >= 64)
5651 jit_tls_offset = -1;
5654 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5656 appdomain_tls_offset = mono_domain_get_tls_offset ();
5657 lmf_tls_offset = mono_get_lmf_tls_offset ();
5658 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5664 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5668 #ifdef MONO_ARCH_HAVE_IMT
5670 // Linear handler, the bsearch head compare is shorter
5671 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5672 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5673 // x86_patch(ins,target)
5674 //[1 + 5] x86_jump_mem(inst,mem)
5677 #if defined(__default_codegen__)
5678 #define BR_SMALL_SIZE 2
5679 #define BR_LARGE_SIZE 5
5680 #elif defined(__native_client_codegen__)
5681 /* I suspect the size calculation below is actually incorrect. */
5682 /* TODO: fix the calculation that uses these sizes. */
5683 #define BR_SMALL_SIZE 16
5684 #define BR_LARGE_SIZE 12
5685 #endif /*__native_client_codegen__*/
5686 #define JUMP_IMM_SIZE 6
5687 #define ENABLE_WRONG_METHOD_CHECK 0
5691 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5693 int i, distance = 0;
5694 for (i = start; i < target; ++i)
5695 distance += imt_entries [i]->chunk_size;
5700 * LOCKING: called with the domain lock held
5703 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5704 gpointer fail_tramp)
5708 guint8 *code, *start;
5710 for (i = 0; i < count; ++i) {
5711 MonoIMTCheckItem *item = imt_entries [i];
5712 if (item->is_equals) {
5713 if (item->check_target_idx) {
5714 if (!item->compare_done)
5715 item->chunk_size += CMP_SIZE;
5716 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5719 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5721 item->chunk_size += JUMP_IMM_SIZE;
5722 #if ENABLE_WRONG_METHOD_CHECK
5723 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5728 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5729 imt_entries [item->check_target_idx]->compare_done = TRUE;
5731 size += item->chunk_size;
5733 #if defined(__native_client__) && defined(__native_client_codegen__)
5734 /* In Native Client, we don't re-use thunks, allocate from the */
5735 /* normal code manager paths. */
5736 size = NACL_BUNDLE_ALIGN_UP (size);
5737 code = mono_domain_code_reserve (domain, size);
5740 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5742 code = mono_domain_code_reserve (domain, size);
5745 for (i = 0; i < count; ++i) {
5746 MonoIMTCheckItem *item = imt_entries [i];
5747 item->code_target = code;
5748 if (item->is_equals) {
5749 if (item->check_target_idx) {
5750 if (!item->compare_done)
5751 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5752 item->jmp_code = code;
5753 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5754 if (item->has_target_code)
5755 x86_jump_code (code, item->value.target_code);
5757 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5760 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5761 item->jmp_code = code;
5762 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5763 if (item->has_target_code)
5764 x86_jump_code (code, item->value.target_code);
5766 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5767 x86_patch (item->jmp_code, code);
5768 x86_jump_code (code, fail_tramp);
5769 item->jmp_code = NULL;
5771 /* enable the commented code to assert on wrong method */
5772 #if ENABLE_WRONG_METHOD_CHECK
5773 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5774 item->jmp_code = code;
5775 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5777 if (item->has_target_code)
5778 x86_jump_code (code, item->value.target_code);
5780 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5781 #if ENABLE_WRONG_METHOD_CHECK
5782 x86_patch (item->jmp_code, code);
5783 x86_breakpoint (code);
5784 item->jmp_code = NULL;
5789 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5790 item->jmp_code = code;
5791 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5792 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5794 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5797 /* patch the branches to get to the target items */
5798 for (i = 0; i < count; ++i) {
5799 MonoIMTCheckItem *item = imt_entries [i];
5800 if (item->jmp_code) {
5801 if (item->check_target_idx) {
5802 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5808 mono_stats.imt_thunks_size += code - start;
5809 g_assert (code - start <= size);
5813 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5814 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5818 if (mono_jit_map_is_enabled ()) {
5821 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5823 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5824 mono_emit_jit_tramp (start, code - start, buff);
5828 nacl_domain_code_validate (domain, &start, size, &code);
5834 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5836 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5841 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5843 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5847 mono_arch_get_cie_program (void)
5851 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5852 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5858 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5860 MonoInst *ins = NULL;
5863 if (cmethod->klass == mono_defaults.math_class) {
5864 if (strcmp (cmethod->name, "Sin") == 0) {
5866 } else if (strcmp (cmethod->name, "Cos") == 0) {
5868 } else if (strcmp (cmethod->name, "Tan") == 0) {
5870 } else if (strcmp (cmethod->name, "Atan") == 0) {
5872 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5874 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5876 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5881 MONO_INST_NEW (cfg, ins, opcode);
5882 ins->type = STACK_R8;
5883 ins->dreg = mono_alloc_freg (cfg);
5884 ins->sreg1 = args [0]->dreg;
5885 MONO_ADD_INS (cfg->cbb, ins);
5888 if (cfg->opt & MONO_OPT_CMOV) {
5891 if (strcmp (cmethod->name, "Min") == 0) {
5892 if (fsig->params [0]->type == MONO_TYPE_I4)
5894 } else if (strcmp (cmethod->name, "Max") == 0) {
5895 if (fsig->params [0]->type == MONO_TYPE_I4)
5900 MONO_INST_NEW (cfg, ins, opcode);
5901 ins->type = STACK_I4;
5902 ins->dreg = mono_alloc_ireg (cfg);
5903 ins->sreg1 = args [0]->dreg;
5904 ins->sreg2 = args [1]->dreg;
5905 MONO_ADD_INS (cfg->cbb, ins);
5910 /* OP_FREM is not IEEE compatible */
5911 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5912 MONO_INST_NEW (cfg, ins, OP_FREM);
5913 ins->inst_i0 = args [0];
5914 ins->inst_i1 = args [1];
5923 mono_arch_print_tree (MonoInst *tree, int arity)
5928 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5934 if (appdomain_tls_offset == -1)
5937 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5938 ins->inst_offset = appdomain_tls_offset;
5943 mono_arch_get_patch_offset (guint8 *code)
5945 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5947 else if (code [0] == 0xba)
5949 else if (code [0] == 0x68)
5952 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5953 /* push <OFFSET>(<REG>) */
5955 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5956 /* call *<OFFSET>(<REG>) */
5958 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5961 else if ((code [0] == 0x58) && (code [1] == 0x05))
5962 /* pop %eax; add <OFFSET>, %eax */
5964 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5965 /* pop <REG>; add <OFFSET>, <REG> */
5967 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5968 /* mov <REG>, imm */
5971 g_assert_not_reached ();
5977 * mono_breakpoint_clean_code:
5979 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5980 * breakpoints in the original code, they are removed in the copy.
5982 * Returns TRUE if no sw breakpoint was present.
5985 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5988 gboolean can_write = TRUE;
5990 * If method_start is non-NULL we need to perform bound checks, since we access memory
5991 * at code - offset we could go before the start of the method and end up in a different
5992 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5995 if (!method_start || code - offset >= method_start) {
5996 memcpy (buf, code - offset, size);
5998 int diff = code - method_start;
5999 memset (buf, 0, size);
6000 memcpy (buf + offset - diff, method_start, diff + size - offset);
6003 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6004 int idx = mono_breakpoint_info_index [i];
6008 ptr = mono_breakpoint_info [idx].address;
6009 if (ptr >= code && ptr < code + size) {
6010 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6012 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6013 buf [ptr - code] = saved_byte;
6020 * mono_x86_get_this_arg_offset:
6022 * Return the offset of the stack location where this is passed during a virtual
6026 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6032 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6034 guint32 esp = regs [X86_ESP];
6035 CallInfo *cinfo = NULL;
6042 * The stack looks like:
6046 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
6048 res = (((MonoObject**)esp) [5 + (offset / 4)]);
6054 #define MAX_ARCH_DELEGATE_PARAMS 10
6057 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6059 guint8 *code, *start;
6060 int code_reserve = 64;
6063 * The stack contains:
6069 start = code = mono_global_codeman_reserve (code_reserve);
6071 /* Replace the this argument with the target */
6072 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6073 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
6074 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6075 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6077 g_assert ((code - start) < code_reserve);
6080 /* 8 for mov_reg and jump, plus 8 for each parameter */
6081 #ifdef __native_client_codegen__
6082 /* TODO: calculate this size correctly */
6083 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6085 code_reserve = 8 + (param_count * 8);
6086 #endif /* __native_client_codegen__ */
6088 * The stack contains:
6089 * <args in reverse order>
6094 * <args in reverse order>
6097 * without unbalancing the stack.
6098 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6099 * and leaving original spot of first arg as placeholder in stack so
6100 * when callee pops stack everything works.
6103 start = code = mono_global_codeman_reserve (code_reserve);
6105 /* store delegate for access to method_ptr */
6106 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6109 for (i = 0; i < param_count; ++i) {
6110 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6111 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6114 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6116 g_assert ((code - start) < code_reserve);
6119 nacl_global_codeman_validate(&start, code_reserve, &code);
6120 mono_debug_add_delegate_trampoline (start, code - start);
6123 *code_len = code - start;
6125 if (mono_jit_map_is_enabled ()) {
6128 buff = (char*)"delegate_invoke_has_target";
6130 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6131 mono_emit_jit_tramp (start, code - start, buff);
6140 mono_arch_get_delegate_invoke_impls (void)
6148 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6149 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
6151 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6152 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6153 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
6154 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
6155 g_free (tramp_name);
6162 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6164 guint8 *code, *start;
6166 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6169 /* FIXME: Support more cases */
6170 if (MONO_TYPE_ISSTRUCT (sig->ret))
6174 * The stack contains:
6180 static guint8* cached = NULL;
6185 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6187 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6189 mono_memory_barrier ();
6193 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6196 for (i = 0; i < sig->param_count; ++i)
6197 if (!mono_is_regsize_var (sig->params [i]))
6200 code = cache [sig->param_count];
6204 if (mono_aot_only) {
6205 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6206 start = mono_aot_get_trampoline (name);
6209 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6212 mono_memory_barrier ();
6214 cache [sig->param_count] = start;
6221 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6224 case X86_EAX: return ctx->eax;
6225 case X86_EBX: return ctx->ebx;
6226 case X86_ECX: return ctx->ecx;
6227 case X86_EDX: return ctx->edx;
6228 case X86_ESP: return ctx->esp;
6229 case X86_EBP: return ctx->ebp;
6230 case X86_ESI: return ctx->esi;
6231 case X86_EDI: return ctx->edi;
6233 g_assert_not_reached ();
6239 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6267 g_assert_not_reached ();
6271 #ifdef MONO_ARCH_SIMD_INTRINSICS
6274 get_float_to_x_spill_area (MonoCompile *cfg)
6276 if (!cfg->fconv_to_r8_x_var) {
6277 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6278 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6280 return cfg->fconv_to_r8_x_var;
6284 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6287 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6290 int dreg, src_opcode;
6292 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6295 switch (src_opcode = ins->opcode) {
6296 case OP_FCONV_TO_I1:
6297 case OP_FCONV_TO_U1:
6298 case OP_FCONV_TO_I2:
6299 case OP_FCONV_TO_U2:
6300 case OP_FCONV_TO_I4:
6307 /* dreg is the IREG and sreg1 is the FREG */
6308 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6309 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6310 fconv->sreg1 = ins->sreg1;
6311 fconv->dreg = mono_alloc_ireg (cfg);
6312 fconv->type = STACK_VTYPE;
6313 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6315 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6319 ins->opcode = OP_XCONV_R8_TO_I4;
6321 ins->klass = mono_defaults.int32_class;
6322 ins->sreg1 = fconv->dreg;
6324 ins->type = STACK_I4;
6325 ins->backend.source_opcode = src_opcode;
6328 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6331 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6336 if (long_ins->opcode == OP_LNEG) {
6338 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6339 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6340 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6345 #ifdef MONO_ARCH_SIMD_INTRINSICS
6347 if (!(cfg->opt & MONO_OPT_SIMD))
6350 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6351 switch (long_ins->opcode) {
6353 vreg = long_ins->sreg1;
6355 if (long_ins->inst_c0) {
6356 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6357 ins->klass = long_ins->klass;
6358 ins->sreg1 = long_ins->sreg1;
6360 ins->type = STACK_VTYPE;
6361 ins->dreg = vreg = alloc_ireg (cfg);
6362 MONO_ADD_INS (cfg->cbb, ins);
6365 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6366 ins->klass = mono_defaults.int32_class;
6368 ins->type = STACK_I4;
6369 ins->dreg = long_ins->dreg + 1;
6370 MONO_ADD_INS (cfg->cbb, ins);
6372 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6373 ins->klass = long_ins->klass;
6374 ins->sreg1 = long_ins->sreg1;
6375 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6376 ins->type = STACK_VTYPE;
6377 ins->dreg = vreg = alloc_ireg (cfg);
6378 MONO_ADD_INS (cfg->cbb, ins);
6380 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6381 ins->klass = mono_defaults.int32_class;
6383 ins->type = STACK_I4;
6384 ins->dreg = long_ins->dreg + 2;
6385 MONO_ADD_INS (cfg->cbb, ins);
6387 long_ins->opcode = OP_NOP;
6389 case OP_INSERTX_I8_SLOW:
6390 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6391 ins->dreg = long_ins->dreg;
6392 ins->sreg1 = long_ins->dreg;
6393 ins->sreg2 = long_ins->sreg2 + 1;
6394 ins->inst_c0 = long_ins->inst_c0 * 2;
6395 MONO_ADD_INS (cfg->cbb, ins);
6397 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6398 ins->dreg = long_ins->dreg;
6399 ins->sreg1 = long_ins->dreg;
6400 ins->sreg2 = long_ins->sreg2 + 2;
6401 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6402 MONO_ADD_INS (cfg->cbb, ins);
6404 long_ins->opcode = OP_NOP;
6407 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6408 ins->dreg = long_ins->dreg;
6409 ins->sreg1 = long_ins->sreg1 + 1;
6410 ins->klass = long_ins->klass;
6411 ins->type = STACK_VTYPE;
6412 MONO_ADD_INS (cfg->cbb, ins);
6414 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6415 ins->dreg = long_ins->dreg;
6416 ins->sreg1 = long_ins->dreg;
6417 ins->sreg2 = long_ins->sreg1 + 2;
6419 ins->klass = long_ins->klass;
6420 ins->type = STACK_VTYPE;
6421 MONO_ADD_INS (cfg->cbb, ins);
6423 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6424 ins->dreg = long_ins->dreg;
6425 ins->sreg1 = long_ins->dreg;;
6426 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6427 ins->klass = long_ins->klass;
6428 ins->type = STACK_VTYPE;
6429 MONO_ADD_INS (cfg->cbb, ins);
6431 long_ins->opcode = OP_NOP;
6434 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6437 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6439 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6442 gpointer *sp, old_value;
6444 const unsigned char *handler;
6446 /*Decode the first instruction to figure out where did we store the spvar*/
6447 /*Our jit MUST generate the following:
6449 Which is encoded as: 0x89 mod_rm.
6450 mod_rm (esp, ebp, imm) which can be: (imm will never be zero)
6451 mod (reg + imm8): 01 reg(esp): 100 rm(ebp): 101 -> 01100101 (0x65)
6452 mod (reg + imm32): 10 reg(esp): 100 rm(ebp): 101 -> 10100101 (0xA5)
6454 handler = clause->handler_start;
6456 if (*handler != 0x89)
6461 if (*handler == 0x65)
6462 offset = *(signed char*)(handler + 1);
6463 else if (*handler == 0xA5)
6464 offset = *(int*)(handler + 1);
6469 bp = MONO_CONTEXT_GET_BP (ctx);
6470 sp = *(gpointer*)(bp + offset);
6473 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6482 * mono_aot_emit_load_got_addr:
6484 * Emit code to load the got address.
6485 * On x86, the result is placed into EBX.
6488 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6490 x86_call_imm (code, 0);
6492 * The patch needs to point to the pop, since the GOT offset needs
6493 * to be added to that address.
6496 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6498 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6499 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6500 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6506 * mono_ppc_emit_load_aotconst:
6508 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6509 * TARGET from the mscorlib GOT in full-aot code.
6510 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6514 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6516 /* Load the mscorlib got address */
6517 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6518 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6519 /* arch_emit_got_access () patches this */
6520 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6525 /* Can't put this into mini-x86.h */
6527 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6530 mono_arch_get_trampolines (gboolean aot)
6532 MonoTrampInfo *info;
6533 GSList *tramps = NULL;
6535 mono_x86_get_signal_exception_trampoline (&info, aot);
6537 tramps = g_slist_append (tramps, info);
6544 #define DBG_SIGNAL SIGBUS
6546 #define DBG_SIGNAL SIGSEGV
6549 /* Soft Debug support */
6550 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6553 * mono_arch_set_breakpoint:
6555 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6556 * The location should contain code emitted by OP_SEQ_POINT.
6559 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6564 * In production, we will use int3 (has to fix the size in the md
6565 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6568 g_assert (code [0] == 0x90);
6569 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6573 * mono_arch_clear_breakpoint:
6575 * Clear the breakpoint at IP.
6578 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6583 for (i = 0; i < 6; ++i)
6588 * mono_arch_start_single_stepping:
6590 * Start single stepping.
6593 mono_arch_start_single_stepping (void)
6595 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6599 * mono_arch_stop_single_stepping:
6601 * Stop single stepping.
6604 mono_arch_stop_single_stepping (void)
6606 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6610 * mono_arch_is_single_step_event:
6612 * Return whenever the machine state in SIGCTX corresponds to a single
6616 mono_arch_is_single_step_event (void *info, void *sigctx)
6619 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6621 if (((gpointer)einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6626 siginfo_t* sinfo = (siginfo_t*) info;
6627 /* Sometimes the address is off by 4 */
6628 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6636 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6639 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6640 if (((gpointer)einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6645 siginfo_t* sinfo = (siginfo_t*)info;
6646 /* Sometimes the address is off by 4 */
6647 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6654 #define BREAKPOINT_SIZE 6
6657 * mono_arch_skip_breakpoint:
6659 * See mini-amd64.c for docs.
6662 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6664 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6668 * mono_arch_skip_single_step:
6670 * See mini-amd64.c for docs.
6673 mono_arch_skip_single_step (MonoContext *ctx)
6675 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6679 * mono_arch_get_seq_point_info:
6681 * See mini-amd64.c for docs.
6684 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6692 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
6694 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6696 #endif /* !MONOTOUCH */