3 * x86 backend for the Mono code generator
6 * Paolo Molaro (lupus@ximian.com)
7 * Dietmar Maurer (dietmar@ximian.com)
10 * Copyright 2003 Ximian, Inc.
11 * Copyright 2003-2011 Novell Inc.
12 * Copyright 2011 Xamarin Inc.
13 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
22 #include <mono/metadata/abi-details.h>
23 #include <mono/metadata/appdomain.h>
24 #include <mono/metadata/debug-helpers.h>
25 #include <mono/metadata/threads.h>
26 #include <mono/metadata/profiler-private.h>
27 #include <mono/metadata/mono-debug.h>
28 #include <mono/metadata/gc-internals.h>
29 #include <mono/utils/mono-math.h>
30 #include <mono/utils/mono-counters.h>
31 #include <mono/utils/mono-mmap.h>
32 #include <mono/utils/mono-memory-model.h>
33 #include <mono/utils/mono-hwcap.h>
34 #include <mono/utils/mono-threads.h>
35 #include <mono/utils/unlocked.h>
45 static gboolean optimize_for_xen = TRUE;
47 #define optimize_for_xen 0
51 /* The single step trampoline */
52 static gpointer ss_trampoline;
54 /* The breakpoint trampoline */
55 static gpointer bp_trampoline;
57 /* This mutex protects architecture specific caches */
58 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
59 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
60 static mono_mutex_t mini_arch_mutex;
62 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
67 /* Under windows, the default pinvoke calling convention is stdcall */
68 #define CALLCONV_IS_STDCALL(sig) ((sig)->pinvoke && ((sig)->call_convention == MONO_CALL_STDCALL || (sig)->call_convention == MONO_CALL_DEFAULT || (sig)->call_convention == MONO_CALL_THISCALL))
70 #define CALLCONV_IS_STDCALL(sig) ((sig)->pinvoke && ((sig)->call_convention == MONO_CALL_STDCALL || (sig)->call_convention == MONO_CALL_THISCALL))
73 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
75 #define OP_SEQ_POINT_BP_OFFSET 7
78 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
81 mono_arch_regname (int reg)
84 case X86_EAX: return "%eax";
85 case X86_EBX: return "%ebx";
86 case X86_ECX: return "%ecx";
87 case X86_EDX: return "%edx";
88 case X86_ESP: return "%esp";
89 case X86_EBP: return "%ebp";
90 case X86_EDI: return "%edi";
91 case X86_ESI: return "%esi";
97 mono_arch_fregname (int reg)
122 mono_arch_xregname (int reg)
147 mono_x86_patch (unsigned char* code, gpointer target)
149 x86_patch (code, (unsigned char*)target);
152 #define FLOAT_PARAM_REGS 0
154 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
156 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
161 switch (sig->call_convention) {
162 case MONO_CALL_THISCALL:
163 return thiscall_param_regs;
169 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
170 #define SMALL_STRUCTS_IN_REGS
171 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
175 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
177 ainfo->offset = *stack_size;
179 if (!param_regs || param_regs [*gr] == X86_NREG) {
180 ainfo->storage = ArgOnStack;
182 (*stack_size) += sizeof (gpointer);
185 ainfo->storage = ArgInIReg;
186 ainfo->reg = param_regs [*gr];
192 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
194 ainfo->offset = *stack_size;
196 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
198 ainfo->storage = ArgOnStack;
199 (*stack_size) += sizeof (gpointer) * 2;
204 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
206 ainfo->offset = *stack_size;
208 if (*gr >= FLOAT_PARAM_REGS) {
209 ainfo->storage = ArgOnStack;
210 (*stack_size) += is_double ? 8 : 4;
211 ainfo->nslots = is_double ? 2 : 1;
214 /* A double register */
216 ainfo->storage = ArgInDoubleSSEReg;
218 ainfo->storage = ArgInFloatSSEReg;
226 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
228 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
233 klass = mono_class_from_mono_type (type);
234 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
236 #if defined(TARGET_WIN32)
238 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
239 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
240 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
241 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
242 * it must be represented in call and cannot be dropped.
244 if (size == 0 && MONO_TYPE_ISSTRUCT (type) && sig->pinvoke) {
245 /* Empty structs (1 byte size) needs to be represented in a stack slot */
246 ainfo->pass_empty_struct = TRUE;
251 #ifdef SMALL_STRUCTS_IN_REGS
252 if (sig->pinvoke && is_return) {
253 MonoMarshalType *info;
255 info = mono_marshal_load_type_info (klass);
258 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
260 /* Ignore empty struct return value, if used. */
261 if (info->num_fields == 0 && ainfo->pass_empty_struct) {
262 ainfo->storage = ArgValuetypeInReg;
267 * Windows x86 ABI for returning structs of size 4 or 8 bytes (regardless of type) dictates that
268 * values are passed in EDX:EAX register pairs, https://msdn.microsoft.com/en-us/library/984x0h58.aspx.
269 * This is different compared to for example float or double return types (not in struct) that will be returned
270 * in ST(0), https://msdn.microsoft.com/en-us/library/ha59cbfz.aspx.
272 * Apples OSX x86 ABI for returning structs of size 4 or 8 bytes uses a slightly different approach.
273 * If a struct includes only one scalar value, it will be handled with the same rules as scalar values.
274 * This means that structs with one float or double will be returned in ST(0). For more details,
275 * https://developer.apple.com/library/mac/documentation/DeveloperTools/Conceptual/LowLevelABI/130-IA-32_Function_Calling_Conventions/IA32.html.
277 #if !defined(TARGET_WIN32)
279 /* Special case structs with only a float member */
280 if (info->num_fields == 1) {
281 int ftype = mini_get_underlying_type (info->fields [0].field->type)->type;
282 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
283 ainfo->storage = ArgValuetypeInReg;
284 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
287 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
288 ainfo->storage = ArgValuetypeInReg;
289 ainfo->pair_storage [0] = ArgOnFloatFpStack;
295 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
296 ainfo->storage = ArgValuetypeInReg;
297 ainfo->pair_storage [0] = ArgInIReg;
298 ainfo->pair_regs [0] = return_regs [0];
299 if (info->native_size > 4) {
300 ainfo->pair_storage [1] = ArgInIReg;
301 ainfo->pair_regs [1] = return_regs [1];
308 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
309 g_assert (size <= 4);
310 ainfo->storage = ArgValuetypeInReg;
311 ainfo->reg = param_regs [*gr];
316 ainfo->offset = *stack_size;
317 ainfo->storage = ArgOnStack;
318 *stack_size += ALIGN_TO (size, sizeof (gpointer));
319 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
325 * Obtain information about a call according to the calling convention.
326 * For x86 ELF, see the "System V Application Binary Interface Intel386
327 * Architecture Processor Supplment, Fourth Edition" document for more
329 * For x86 win32, see https://msdn.microsoft.com/en-us/library/984x0h58.aspx.
332 get_call_info_internal (CallInfo *cinfo, MonoMethodSignature *sig)
334 guint32 i, gr, fr, pstart;
335 const guint32 *param_regs;
337 int n = sig->hasthis + sig->param_count;
338 guint32 stack_size = 0;
339 gboolean is_pinvoke = sig->pinvoke;
345 param_regs = callconv_param_regs(sig);
349 ret_type = mini_get_underlying_type (sig->ret);
350 switch (ret_type->type) {
360 case MONO_TYPE_FNPTR:
361 case MONO_TYPE_OBJECT:
362 cinfo->ret.storage = ArgInIReg;
363 cinfo->ret.reg = X86_EAX;
367 cinfo->ret.storage = ArgInIReg;
368 cinfo->ret.reg = X86_EAX;
369 cinfo->ret.is_pair = TRUE;
372 cinfo->ret.storage = ArgOnFloatFpStack;
375 cinfo->ret.storage = ArgOnDoubleFpStack;
377 case MONO_TYPE_GENERICINST:
378 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
379 cinfo->ret.storage = ArgInIReg;
380 cinfo->ret.reg = X86_EAX;
383 if (mini_is_gsharedvt_type (ret_type)) {
384 cinfo->ret.storage = ArgOnStack;
385 cinfo->vtype_retaddr = TRUE;
389 case MONO_TYPE_VALUETYPE:
390 case MONO_TYPE_TYPEDBYREF: {
391 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
393 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
394 if (cinfo->ret.storage == ArgOnStack) {
395 cinfo->vtype_retaddr = TRUE;
396 /* The caller passes the address where the value is stored */
402 g_assert (mini_is_gsharedvt_type (ret_type));
403 cinfo->ret.storage = ArgOnStack;
404 cinfo->vtype_retaddr = TRUE;
407 cinfo->ret.storage = ArgNone;
410 g_error ("Can't handle as return value 0x%x", ret_type->type);
416 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
417 * the first argument, allowing 'this' to be always passed in the first arg reg.
418 * Also do this if the first argument is a reference type, since virtual calls
419 * are sometimes made using calli without sig->hasthis set, like in the delegate
422 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
424 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
426 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
429 cinfo->vret_arg_offset = stack_size;
430 add_general (&gr, NULL, &stack_size, &cinfo->ret);
431 cinfo->vret_arg_index = 1;
435 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
437 if (cinfo->vtype_retaddr)
438 add_general (&gr, NULL, &stack_size, &cinfo->ret);
441 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
442 fr = FLOAT_PARAM_REGS;
444 /* Emit the signature cookie just before the implicit arguments */
445 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
448 for (i = pstart; i < sig->param_count; ++i) {
449 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
452 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
453 /* We allways pass the sig cookie on the stack for simplicity */
455 * Prevent implicit arguments + the sig cookie from being passed
458 fr = FLOAT_PARAM_REGS;
460 /* Emit the signature cookie just before the implicit arguments */
461 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
464 if (sig->params [i]->byref) {
465 add_general (&gr, param_regs, &stack_size, ainfo);
468 ptype = mini_get_underlying_type (sig->params [i]);
469 switch (ptype->type) {
472 add_general (&gr, param_regs, &stack_size, ainfo);
476 add_general (&gr, param_regs, &stack_size, ainfo);
480 add_general (&gr, param_regs, &stack_size, ainfo);
485 case MONO_TYPE_FNPTR:
486 case MONO_TYPE_OBJECT:
487 add_general (&gr, param_regs, &stack_size, ainfo);
489 case MONO_TYPE_GENERICINST:
490 if (!mono_type_generic_inst_is_valuetype (ptype)) {
491 add_general (&gr, param_regs, &stack_size, ainfo);
494 if (mini_is_gsharedvt_type (ptype)) {
495 /* gsharedvt arguments are passed by ref */
496 add_general (&gr, param_regs, &stack_size, ainfo);
497 g_assert (ainfo->storage == ArgOnStack);
498 ainfo->storage = ArgGSharedVt;
502 case MONO_TYPE_VALUETYPE:
503 case MONO_TYPE_TYPEDBYREF:
504 add_valuetype (sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
508 add_general_pair (&gr, param_regs, &stack_size, ainfo);
511 add_float (&fr, &stack_size, ainfo, FALSE);
514 add_float (&fr, &stack_size, ainfo, TRUE);
518 /* gsharedvt arguments are passed by ref */
519 g_assert (mini_is_gsharedvt_type (ptype));
520 add_general (&gr, param_regs, &stack_size, ainfo);
521 g_assert (ainfo->storage == ArgOnStack);
522 ainfo->storage = ArgGSharedVt;
525 g_error ("unexpected type 0x%x", ptype->type);
526 g_assert_not_reached ();
530 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
531 fr = FLOAT_PARAM_REGS;
533 /* Emit the signature cookie just before the implicit arguments */
534 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
537 if (cinfo->vtype_retaddr) {
538 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
539 cinfo->callee_stack_pop = 4;
540 } else if (CALLCONV_IS_STDCALL (sig)) {
541 /* Have to compensate for the stack space popped by the native callee */
542 cinfo->callee_stack_pop = stack_size;
545 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
546 cinfo->need_stack_align = TRUE;
547 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
548 stack_size += cinfo->stack_align_amount;
551 cinfo->stack_usage = stack_size;
552 cinfo->reg_usage = gr;
553 cinfo->freg_usage = fr;
558 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
560 int n = sig->hasthis + sig->param_count;
564 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
566 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
568 return get_call_info_internal (cinfo, sig);
572 * mono_arch_get_argument_info:
573 * @csig: a method signature
574 * @param_count: the number of parameters to consider
575 * @arg_info: an array to store the result infos
577 * Gathers information on parameters such as size, alignment and
578 * padding. arg_info should be large enought to hold param_count + 1 entries.
580 * Returns the size of the argument area on the stack.
581 * This should be signal safe, since it is called from
582 * mono_arch_unwind_frame ().
583 * FIXME: The metadata calls might not be signal safe.
586 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
588 int len, k, args_size = 0;
594 /* Avoid g_malloc as it is not signal safe */
595 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
596 cinfo = (CallInfo*)g_newa (guint8*, len);
597 memset (cinfo, 0, len);
599 cinfo = get_call_info_internal (cinfo, csig);
601 arg_info [0].offset = offset;
603 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
604 args_size += sizeof (gpointer);
609 args_size += sizeof (gpointer);
613 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
614 /* Emitted after this */
615 args_size += sizeof (gpointer);
619 arg_info [0].size = args_size;
621 for (k = 0; k < param_count; k++) {
622 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
624 /* ignore alignment for now */
627 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
628 arg_info [k].pad = pad;
630 arg_info [k + 1].pad = 0;
631 arg_info [k + 1].size = size;
633 arg_info [k + 1].offset = offset;
636 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
637 /* Emitted after the first arg */
638 args_size += sizeof (gpointer);
643 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
644 align = MONO_ARCH_FRAME_ALIGNMENT;
647 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
648 arg_info [k].pad = pad;
654 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
656 MonoType *callee_ret;
660 if (cfg->compile_aot && !cfg->full_aot)
661 /* OP_TAILCALL doesn't work with AOT */
664 c1 = get_call_info (NULL, caller_sig);
665 c2 = get_call_info (NULL, callee_sig);
667 * Tail calls with more callee stack usage than the caller cannot be supported, since
668 * the extra stack space would be left on the stack after the tail call.
670 res = c1->stack_usage >= c2->stack_usage;
671 callee_ret = mini_get_underlying_type (callee_sig->ret);
672 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
673 /* An address on the callee's stack is passed as the first argument */
683 * Initialize the cpu to execute managed code.
686 mono_arch_cpu_init (void)
688 /* spec compliance requires running with double precision */
692 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
693 fpcw &= ~X86_FPCW_PRECC_MASK;
694 fpcw |= X86_FPCW_PREC_DOUBLE;
695 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
696 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
698 _control87 (_PC_53, MCW_PC);
703 * Initialize architecture specific code.
706 mono_arch_init (void)
708 mono_os_mutex_init_recursive (&mini_arch_mutex);
711 bp_trampoline = mini_get_breakpoint_trampoline ();
713 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
714 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
715 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
716 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
721 * Cleanup architecture specific code.
724 mono_arch_cleanup (void)
726 mono_os_mutex_destroy (&mini_arch_mutex);
730 * This function returns the optimizations supported on this cpu.
733 mono_arch_cpu_optimizations (guint32 *exclude_mask)
739 if (mono_hwcap_x86_has_cmov) {
740 opts |= MONO_OPT_CMOV;
742 if (mono_hwcap_x86_has_fcmov)
743 opts |= MONO_OPT_FCMOV;
745 *exclude_mask |= MONO_OPT_FCMOV;
747 *exclude_mask |= MONO_OPT_CMOV;
750 if (mono_hwcap_x86_has_sse2)
751 opts |= MONO_OPT_SSE2;
753 *exclude_mask |= MONO_OPT_SSE2;
755 #ifdef MONO_ARCH_SIMD_INTRINSICS
756 /*SIMD intrinsics require at least SSE2.*/
757 if (!mono_hwcap_x86_has_sse2)
758 *exclude_mask |= MONO_OPT_SIMD;
765 * This function test for all SSE functions supported.
767 * Returns a bitmask corresponding to all supported versions.
771 mono_arch_cpu_enumerate_simd_versions (void)
773 guint32 sse_opts = 0;
775 if (mono_hwcap_x86_has_sse1)
776 sse_opts |= SIMD_VERSION_SSE1;
778 if (mono_hwcap_x86_has_sse2)
779 sse_opts |= SIMD_VERSION_SSE2;
781 if (mono_hwcap_x86_has_sse3)
782 sse_opts |= SIMD_VERSION_SSE3;
784 if (mono_hwcap_x86_has_ssse3)
785 sse_opts |= SIMD_VERSION_SSSE3;
787 if (mono_hwcap_x86_has_sse41)
788 sse_opts |= SIMD_VERSION_SSE41;
790 if (mono_hwcap_x86_has_sse42)
791 sse_opts |= SIMD_VERSION_SSE42;
793 if (mono_hwcap_x86_has_sse4a)
794 sse_opts |= SIMD_VERSION_SSE4a;
800 * Determine whenever the trap whose info is in SIGINFO is caused by
804 mono_arch_is_int_overflow (void *sigctx, void *info)
809 mono_sigctx_to_monoctx (sigctx, &ctx);
811 ip = (guint8*)ctx.eip;
813 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
817 switch (x86_modrm_rm (ip [1])) {
837 g_assert_not_reached ();
849 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
854 for (i = 0; i < cfg->num_varinfo; i++) {
855 MonoInst *ins = cfg->varinfo [i];
856 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
859 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
862 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
863 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
866 /* we dont allocate I1 to registers because there is no simply way to sign extend
867 * 8bit quantities in caller saved registers on x86 */
868 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
869 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
870 g_assert (i == vmv->idx);
871 vars = g_list_prepend (vars, vmv);
875 vars = mono_varlist_sort (cfg, vars, 0);
881 mono_arch_get_global_int_regs (MonoCompile *cfg)
885 /* we can use 3 registers for global allocation */
886 regs = g_list_prepend (regs, (gpointer)X86_EBX);
887 regs = g_list_prepend (regs, (gpointer)X86_ESI);
888 regs = g_list_prepend (regs, (gpointer)X86_EDI);
894 * mono_arch_regalloc_cost:
896 * Return the cost, in number of memory references, of the action of
897 * allocating the variable VMV into a register during global register
901 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
903 MonoInst *ins = cfg->varinfo [vmv->idx];
905 if (cfg->method->save_lmf)
906 /* The register is already saved */
907 return (ins->opcode == OP_ARG) ? 1 : 0;
909 /* push+pop+possible load if it is an argument */
910 return (ins->opcode == OP_ARG) ? 3 : 2;
914 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
916 static int inited = FALSE;
917 static int count = 0;
919 if (cfg->arch.need_stack_frame_inited) {
920 g_assert (cfg->arch.need_stack_frame == flag);
924 cfg->arch.need_stack_frame = flag;
925 cfg->arch.need_stack_frame_inited = TRUE;
931 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
936 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
940 needs_stack_frame (MonoCompile *cfg)
942 MonoMethodSignature *sig;
943 MonoMethodHeader *header;
944 gboolean result = FALSE;
946 #if defined(__APPLE__)
947 /*OSX requires stack frame code to have the correct alignment. */
951 if (cfg->arch.need_stack_frame_inited)
952 return cfg->arch.need_stack_frame;
954 header = cfg->header;
955 sig = mono_method_signature (cfg->method);
957 if (cfg->disable_omit_fp)
959 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
961 else if (cfg->method->save_lmf)
963 else if (cfg->stack_offset)
965 else if (cfg->param_area)
967 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
969 else if (header->num_clauses)
971 else if (sig->param_count + sig->hasthis)
973 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
975 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)))
978 set_needs_stack_frame (cfg, result);
980 return cfg->arch.need_stack_frame;
984 * Set var information according to the calling convention. X86 version.
985 * The locals var stuff should most likely be split in another method.
988 mono_arch_allocate_vars (MonoCompile *cfg)
990 MonoMethodSignature *sig;
991 MonoMethodHeader *header;
993 guint32 locals_stack_size, locals_stack_align;
998 header = cfg->header;
999 sig = mono_method_signature (cfg->method);
1001 if (!cfg->arch.cinfo)
1002 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1003 cinfo = (CallInfo *)cfg->arch.cinfo;
1005 cfg->frame_reg = X86_EBP;
1008 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1009 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1010 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1013 /* Reserve space to save LMF and caller saved registers */
1015 if (cfg->method->save_lmf) {
1016 /* The LMF var is allocated normally */
1018 if (cfg->used_int_regs & (1 << X86_EBX)) {
1022 if (cfg->used_int_regs & (1 << X86_EDI)) {
1026 if (cfg->used_int_regs & (1 << X86_ESI)) {
1031 switch (cinfo->ret.storage) {
1032 case ArgValuetypeInReg:
1033 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1035 cfg->ret->opcode = OP_REGOFFSET;
1036 cfg->ret->inst_basereg = X86_EBP;
1037 cfg->ret->inst_offset = - offset;
1043 /* Allocate locals */
1044 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1045 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1046 char *mname = mono_method_full_name (cfg->method, TRUE);
1047 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1051 if (locals_stack_align) {
1052 int prev_offset = offset;
1054 offset += (locals_stack_align - 1);
1055 offset &= ~(locals_stack_align - 1);
1057 while (prev_offset < offset) {
1059 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1062 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1063 cfg->locals_max_stack_offset = - offset;
1065 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1066 * have locals larger than 8 bytes we need to make sure that
1067 * they have the appropriate offset.
1069 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8) {
1070 int extra_size = MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1071 offset += extra_size;
1072 locals_stack_size += extra_size;
1074 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1075 if (offsets [i] != -1) {
1076 MonoInst *inst = cfg->varinfo [i];
1077 inst->opcode = OP_REGOFFSET;
1078 inst->inst_basereg = X86_EBP;
1079 inst->inst_offset = - (offset + offsets [i]);
1080 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1083 offset += locals_stack_size;
1087 * Allocate arguments+return value
1090 switch (cinfo->ret.storage) {
1092 if (cfg->vret_addr) {
1094 * In the new IR, the cfg->vret_addr variable represents the
1095 * vtype return value.
1097 cfg->vret_addr->opcode = OP_REGOFFSET;
1098 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1099 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1100 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1101 printf ("vret_addr =");
1102 mono_print_ins (cfg->vret_addr);
1105 cfg->ret->opcode = OP_REGOFFSET;
1106 cfg->ret->inst_basereg = X86_EBP;
1107 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1110 case ArgValuetypeInReg:
1113 cfg->ret->opcode = OP_REGVAR;
1114 cfg->ret->inst_c0 = cinfo->ret.reg;
1115 cfg->ret->dreg = cinfo->ret.reg;
1118 case ArgOnFloatFpStack:
1119 case ArgOnDoubleFpStack:
1122 g_assert_not_reached ();
1125 if (sig->call_convention == MONO_CALL_VARARG) {
1126 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1127 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1130 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1131 ArgInfo *ainfo = &cinfo->args [i];
1132 inst = cfg->args [i];
1133 if (inst->opcode != OP_REGVAR) {
1134 inst->opcode = OP_REGOFFSET;
1135 inst->inst_basereg = X86_EBP;
1136 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1140 cfg->stack_offset = offset;
1144 mono_arch_create_vars (MonoCompile *cfg)
1147 MonoMethodSignature *sig;
1150 sig = mono_method_signature (cfg->method);
1152 if (!cfg->arch.cinfo)
1153 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1154 cinfo = (CallInfo *)cfg->arch.cinfo;
1156 sig_ret = mini_get_underlying_type (sig->ret);
1158 if (cinfo->ret.storage == ArgValuetypeInReg)
1159 cfg->ret_var_is_local = TRUE;
1160 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (sig_ret))) {
1161 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1164 if (cfg->gen_sdb_seq_points) {
1167 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1168 ins->flags |= MONO_INST_VOLATILE;
1169 cfg->arch.ss_tramp_var = ins;
1171 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1172 ins->flags |= MONO_INST_VOLATILE;
1173 cfg->arch.bp_tramp_var = ins;
1176 if (cfg->method->save_lmf) {
1177 cfg->create_lmf_var = TRUE;
1181 cfg->arch_eh_jit_info = 1;
1185 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1186 * so we try to do it just once when we have multiple fp arguments in a row.
1187 * We don't use this mechanism generally because for int arguments the generated code
1188 * is slightly bigger and new generation cpus optimize away the dependency chains
1189 * created by push instructions on the esp value.
1190 * fp_arg_setup is the first argument in the execution sequence where the esp register
1193 static G_GNUC_UNUSED int
1194 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1199 for (; start_arg < sig->param_count; ++start_arg) {
1200 t = mini_get_underlying_type (sig->params [start_arg]);
1201 if (!t->byref && t->type == MONO_TYPE_R8) {
1202 fp_space += sizeof (double);
1203 *fp_arg_setup = start_arg;
1212 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1214 MonoMethodSignature *tmp_sig;
1218 * mono_ArgIterator_Setup assumes the signature cookie is
1219 * passed first and all the arguments which were before it are
1220 * passed on the stack after the signature. So compensate by
1221 * passing a different signature.
1223 tmp_sig = mono_metadata_signature_dup (call->signature);
1224 tmp_sig->param_count -= call->signature->sentinelpos;
1225 tmp_sig->sentinelpos = 0;
1226 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1228 if (cfg->compile_aot) {
1229 sig_reg = mono_alloc_ireg (cfg);
1230 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1231 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1233 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1239 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1244 LLVMCallInfo *linfo;
1245 MonoType *t, *sig_ret;
1247 n = sig->param_count + sig->hasthis;
1249 cinfo = get_call_info (cfg->mempool, sig);
1252 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1255 * LLVM always uses the native ABI while we use our own ABI, the
1256 * only difference is the handling of vtypes:
1257 * - we only pass/receive them in registers in some cases, and only
1258 * in 1 or 2 integer registers.
1260 if (cinfo->ret.storage == ArgValuetypeInReg) {
1262 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1263 cfg->disable_llvm = TRUE;
1267 cfg->exception_message = g_strdup ("vtype ret in call");
1268 cfg->disable_llvm = TRUE;
1270 linfo->ret.storage = LLVMArgVtypeInReg;
1271 for (j = 0; j < 2; ++j)
1272 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1276 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage == ArgInIReg) {
1277 /* Vtype returned using a hidden argument */
1278 linfo->ret.storage = LLVMArgVtypeRetAddr;
1279 linfo->vret_arg_index = cinfo->vret_arg_index;
1282 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage != ArgInIReg) {
1284 cfg->exception_message = g_strdup ("vtype ret in call");
1285 cfg->disable_llvm = TRUE;
1288 for (i = 0; i < n; ++i) {
1289 ainfo = cinfo->args + i;
1291 if (i >= sig->hasthis)
1292 t = sig->params [i - sig->hasthis];
1294 t = &mono_defaults.int_class->byval_arg;
1296 linfo->args [i].storage = LLVMArgNone;
1298 switch (ainfo->storage) {
1300 linfo->args [i].storage = LLVMArgNormal;
1302 case ArgInDoubleSSEReg:
1303 case ArgInFloatSSEReg:
1304 linfo->args [i].storage = LLVMArgNormal;
1307 if (mini_type_is_vtype (t)) {
1308 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1309 /* LLVM seems to allocate argument space for empty structures too */
1310 linfo->args [i].storage = LLVMArgNone;
1312 linfo->args [i].storage = LLVMArgVtypeByVal;
1314 linfo->args [i].storage = LLVMArgNormal;
1317 case ArgValuetypeInReg:
1319 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1320 cfg->disable_llvm = TRUE;
1324 cfg->exception_message = g_strdup ("vtype arg");
1325 cfg->disable_llvm = TRUE;
1327 linfo->args [i].storage = LLVMArgVtypeInReg;
1328 for (j = 0; j < 2; ++j)
1329 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1333 linfo->args [i].storage = LLVMArgGSharedVt;
1336 cfg->exception_message = g_strdup ("ainfo->storage");
1337 cfg->disable_llvm = TRUE;
1347 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1349 if (cfg->compute_gc_maps) {
1352 /* Needs checking if the feature will be enabled again */
1353 g_assert_not_reached ();
1355 /* On x86, the offsets are from the sp value before the start of the call sequence */
1357 t = &mono_defaults.int_class->byval_arg;
1358 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1363 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1367 MonoMethodSignature *sig;
1370 int sentinelpos = 0, sp_offset = 0;
1372 sig = call->signature;
1373 n = sig->param_count + sig->hasthis;
1374 sig_ret = mini_get_underlying_type (sig->ret);
1376 cinfo = get_call_info (cfg->mempool, sig);
1377 call->call_info = cinfo;
1379 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1380 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1382 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1383 if (cinfo->ret.storage == ArgValuetypeInReg && cinfo->ret.pair_storage[0] != ArgNone ) {
1385 * Tell the JIT to use a more efficient calling convention: call using
1386 * OP_CALL, compute the result location after the call, and save the
1389 call->vret_in_reg = TRUE;
1390 #if defined(__APPLE__)
1391 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1392 call->vret_in_reg_fp = TRUE;
1395 NULLIFY_INS (call->vret_var);
1399 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1401 /* Handle the case where there are no implicit arguments */
1402 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1403 emit_sig_cookie (cfg, call, cinfo);
1404 sp_offset = cinfo->sig_cookie.offset;
1405 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1408 /* Arguments are pushed in the reverse order */
1409 for (i = n - 1; i >= 0; i --) {
1410 ArgInfo *ainfo = cinfo->args + i;
1411 MonoType *orig_type, *t;
1414 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1417 /* Push the vret arg before the first argument */
1418 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1419 vtarg->type = STACK_MP;
1420 vtarg->inst_destbasereg = X86_ESP;
1421 vtarg->sreg1 = call->vret_var->dreg;
1422 vtarg->inst_offset = cinfo->ret.offset;
1423 MONO_ADD_INS (cfg->cbb, vtarg);
1424 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1427 if (i >= sig->hasthis)
1428 t = sig->params [i - sig->hasthis];
1430 t = &mono_defaults.int_class->byval_arg;
1432 t = mini_get_underlying_type (t);
1434 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1436 in = call->args [i];
1437 arg->cil_code = in->cil_code;
1438 arg->sreg1 = in->dreg;
1439 arg->type = in->type;
1441 g_assert (in->dreg != -1);
1443 if (ainfo->storage == ArgGSharedVt) {
1444 arg->opcode = OP_OUTARG_VT;
1445 arg->sreg1 = in->dreg;
1446 arg->klass = in->klass;
1447 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1448 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1450 MONO_ADD_INS (cfg->cbb, arg);
1451 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1455 g_assert (in->klass);
1457 if (t->type == MONO_TYPE_TYPEDBYREF) {
1458 size = sizeof (MonoTypedRef);
1459 align = sizeof (gpointer);
1462 size = mini_type_stack_size_full (&in->klass->byval_arg, &align, sig->pinvoke);
1465 if (size > 0 || ainfo->pass_empty_struct) {
1466 arg->opcode = OP_OUTARG_VT;
1467 arg->sreg1 = in->dreg;
1468 arg->klass = in->klass;
1469 arg->backend.size = size;
1470 arg->inst_p0 = call;
1471 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1472 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1474 MONO_ADD_INS (cfg->cbb, arg);
1475 if (ainfo->storage != ArgValuetypeInReg) {
1476 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1480 switch (ainfo->storage) {
1483 if (t->type == MONO_TYPE_R4) {
1484 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1486 } else if (t->type == MONO_TYPE_R8) {
1487 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1489 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1490 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, MONO_LVREG_MS (in->dreg));
1491 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, MONO_LVREG_LS (in->dreg));
1494 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1498 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1503 arg->opcode = OP_MOVE;
1504 arg->dreg = ainfo->reg;
1505 MONO_ADD_INS (cfg->cbb, arg);
1509 g_assert_not_reached ();
1512 if (cfg->compute_gc_maps) {
1514 /* FIXME: The == STACK_OBJ check might be fragile ? */
1515 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1517 if (call->need_unbox_trampoline)
1518 /* The unbox trampoline transforms this into a managed pointer */
1519 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.int_class->this_arg);
1521 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.object_class->byval_arg);
1523 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1527 for (j = 0; j < argsize; j += 4)
1528 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1533 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1534 /* Emit the signature cookie just before the implicit arguments */
1535 emit_sig_cookie (cfg, call, cinfo);
1536 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1540 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1543 if (cinfo->ret.storage == ArgValuetypeInReg) {
1546 else if (cinfo->ret.storage == ArgInIReg) {
1548 /* The return address is passed in a register */
1549 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1550 vtarg->sreg1 = call->inst.dreg;
1551 vtarg->dreg = mono_alloc_ireg (cfg);
1552 MONO_ADD_INS (cfg->cbb, vtarg);
1554 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1555 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1556 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1557 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1561 call->stack_usage = cinfo->stack_usage;
1562 call->stack_align_amount = cinfo->stack_align_amount;
1566 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1568 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1569 ArgInfo *ainfo = ins->inst_p1;
1570 int size = ins->backend.size;
1572 if (ainfo->storage == ArgValuetypeInReg) {
1573 int dreg = mono_alloc_ireg (cfg);
1576 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1579 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1582 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1586 g_assert_not_reached ();
1588 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1591 if (cfg->gsharedvt && mini_is_gsharedvt_klass (ins->klass)) {
1593 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1594 } else if (size <= 4) {
1595 int dreg = mono_alloc_ireg (cfg);
1596 if (ainfo->pass_empty_struct) {
1597 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
1598 MONO_EMIT_NEW_ICONST (cfg, dreg, 0);
1600 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1602 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1603 } else if (size <= 20) {
1604 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1606 // FIXME: Code growth
1607 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1613 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1615 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
1618 if (ret->type == MONO_TYPE_R4) {
1619 if (COMPILE_LLVM (cfg))
1620 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1623 } else if (ret->type == MONO_TYPE_R8) {
1624 if (COMPILE_LLVM (cfg))
1625 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1628 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1629 if (COMPILE_LLVM (cfg))
1630 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1632 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, MONO_LVREG_LS (val->dreg));
1633 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, MONO_LVREG_MS (val->dreg));
1639 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1643 * Allow tracing to work with this interface (with an optional argument)
1646 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1650 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1651 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1653 /* if some args are passed in registers, we need to save them here */
1654 x86_push_reg (code, X86_EBP);
1656 if (cfg->compile_aot) {
1657 x86_push_imm (code, cfg->method);
1658 x86_mov_reg_imm (code, X86_EAX, func);
1659 x86_call_reg (code, X86_EAX);
1661 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1662 x86_push_imm (code, cfg->method);
1663 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1664 x86_call_code (code, 0);
1666 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1680 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1683 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1684 MonoMethod *method = cfg->method;
1685 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
1687 switch (ret_type->type) {
1688 case MONO_TYPE_VOID:
1689 /* special case string .ctor icall */
1690 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1691 save_mode = SAVE_EAX;
1692 stack_usage = enable_arguments ? 8 : 4;
1694 save_mode = SAVE_NONE;
1698 save_mode = SAVE_EAX_EDX;
1699 stack_usage = enable_arguments ? 16 : 8;
1703 save_mode = SAVE_FP;
1704 stack_usage = enable_arguments ? 16 : 8;
1706 case MONO_TYPE_GENERICINST:
1707 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1708 save_mode = SAVE_EAX;
1709 stack_usage = enable_arguments ? 8 : 4;
1713 case MONO_TYPE_VALUETYPE:
1714 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1715 save_mode = SAVE_STRUCT;
1716 stack_usage = enable_arguments ? 4 : 0;
1719 save_mode = SAVE_EAX;
1720 stack_usage = enable_arguments ? 8 : 4;
1724 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1726 switch (save_mode) {
1728 x86_push_reg (code, X86_EDX);
1729 x86_push_reg (code, X86_EAX);
1730 if (enable_arguments) {
1731 x86_push_reg (code, X86_EDX);
1732 x86_push_reg (code, X86_EAX);
1737 x86_push_reg (code, X86_EAX);
1738 if (enable_arguments) {
1739 x86_push_reg (code, X86_EAX);
1744 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1745 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1746 if (enable_arguments) {
1747 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1748 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1753 if (enable_arguments) {
1754 x86_push_membase (code, X86_EBP, 8);
1763 if (cfg->compile_aot) {
1764 x86_push_imm (code, method);
1765 x86_mov_reg_imm (code, X86_EAX, func);
1766 x86_call_reg (code, X86_EAX);
1768 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1769 x86_push_imm (code, method);
1770 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1771 x86_call_code (code, 0);
1774 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1776 switch (save_mode) {
1778 x86_pop_reg (code, X86_EAX);
1779 x86_pop_reg (code, X86_EDX);
1782 x86_pop_reg (code, X86_EAX);
1785 x86_fld_membase (code, X86_ESP, 0, TRUE);
1786 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1793 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1798 #define EMIT_COND_BRANCH(ins,cond,sign) \
1799 if (ins->inst_true_bb->native_offset) { \
1800 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1802 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1803 if ((cfg->opt & MONO_OPT_BRANCH) && \
1804 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1805 x86_branch8 (code, cond, 0, sign); \
1807 x86_branch32 (code, cond, 0, sign); \
1811 * Emit an exception if condition is fail and
1812 * if possible do a directly branch to target
1814 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1816 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1817 if (tins == NULL) { \
1818 mono_add_patch_info (cfg, code - cfg->native_code, \
1819 MONO_PATCH_INFO_EXC, exc_name); \
1820 x86_branch32 (code, cond, 0, signed); \
1822 EMIT_COND_BRANCH (tins, cond, signed); \
1826 #define EMIT_FPCOMPARE(code) do { \
1827 x86_fcompp (code); \
1828 x86_fnstsw (code); \
1833 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1835 gboolean needs_paddings = TRUE;
1837 MonoJumpInfo *jinfo = NULL;
1839 if (cfg->abs_patches) {
1840 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1841 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1842 needs_paddings = FALSE;
1845 if (cfg->compile_aot)
1846 needs_paddings = FALSE;
1847 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1848 This is required for code patching to be safe on SMP machines.
1850 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1851 if (needs_paddings && pad_size)
1852 x86_padding (code, 4 - pad_size);
1854 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1855 x86_call_code (code, 0);
1860 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1863 * mono_peephole_pass_1:
1865 * Perform peephole opts which should/can be performed before local regalloc
1868 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1872 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1873 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1875 switch (ins->opcode) {
1878 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1880 * X86_LEA is like ADD, but doesn't have the
1881 * sreg1==dreg restriction.
1883 ins->opcode = OP_X86_LEA_MEMBASE;
1884 ins->inst_basereg = ins->sreg1;
1885 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1886 ins->opcode = OP_X86_INC_REG;
1890 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1891 ins->opcode = OP_X86_LEA_MEMBASE;
1892 ins->inst_basereg = ins->sreg1;
1893 ins->inst_imm = -ins->inst_imm;
1894 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1895 ins->opcode = OP_X86_DEC_REG;
1897 case OP_COMPARE_IMM:
1898 case OP_ICOMPARE_IMM:
1899 /* OP_COMPARE_IMM (reg, 0)
1901 * OP_X86_TEST_NULL (reg)
1904 ins->opcode = OP_X86_TEST_NULL;
1906 case OP_X86_COMPARE_MEMBASE_IMM:
1908 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1909 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1911 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1912 * OP_COMPARE_IMM reg, imm
1914 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1916 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1917 ins->inst_basereg == last_ins->inst_destbasereg &&
1918 ins->inst_offset == last_ins->inst_offset) {
1919 ins->opcode = OP_COMPARE_IMM;
1920 ins->sreg1 = last_ins->sreg1;
1922 /* check if we can remove cmp reg,0 with test null */
1924 ins->opcode = OP_X86_TEST_NULL;
1928 case OP_X86_PUSH_MEMBASE:
1929 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1930 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1931 ins->inst_basereg == last_ins->inst_destbasereg &&
1932 ins->inst_offset == last_ins->inst_offset) {
1933 ins->opcode = OP_X86_PUSH;
1934 ins->sreg1 = last_ins->sreg1;
1939 mono_peephole_ins (bb, ins);
1944 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1948 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1949 switch (ins->opcode) {
1951 /* reg = 0 -> XOR (reg, reg) */
1952 /* XOR sets cflags on x86, so we cant do it always */
1953 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1956 ins->opcode = OP_IXOR;
1957 ins->sreg1 = ins->dreg;
1958 ins->sreg2 = ins->dreg;
1961 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1962 * since it takes 3 bytes instead of 7.
1964 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
1965 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1966 ins2->opcode = OP_STORE_MEMBASE_REG;
1967 ins2->sreg1 = ins->dreg;
1969 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1970 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1971 ins2->sreg1 = ins->dreg;
1973 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1974 /* Continue iteration */
1983 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1984 ins->opcode = OP_X86_INC_REG;
1988 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1989 ins->opcode = OP_X86_DEC_REG;
1993 mono_peephole_ins (bb, ins);
1997 #define NEW_INS(cfg,ins,dest,op) do { \
1998 MONO_INST_NEW ((cfg), (dest), (op)); \
1999 (dest)->cil_code = (ins)->cil_code; \
2000 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2004 * mono_arch_lowering_pass:
2006 * Converts complex opcodes into simpler ones so that each IR instruction
2007 * corresponds to one machine instruction.
2010 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2012 MonoInst *ins, *next;
2015 * FIXME: Need to add more instructions, but the current machine
2016 * description can't model some parts of the composite instructions like
2019 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2020 switch (ins->opcode) {
2023 case OP_IDIV_UN_IMM:
2024 case OP_IREM_UN_IMM:
2026 * Keep the cases where we could generated optimized code, otherwise convert
2027 * to the non-imm variant.
2029 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2031 mono_decompose_op_imm (cfg, bb, ins);
2033 #ifdef MONO_ARCH_SIMD_INTRINSICS
2034 case OP_EXPAND_I1: {
2036 int temp_reg1 = mono_alloc_ireg (cfg);
2037 int temp_reg2 = mono_alloc_ireg (cfg);
2038 int original_reg = ins->sreg1;
2040 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2041 temp->sreg1 = original_reg;
2042 temp->dreg = temp_reg1;
2044 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2045 temp->sreg1 = temp_reg1;
2046 temp->dreg = temp_reg2;
2049 NEW_INS (cfg, ins, temp, OP_IOR);
2050 temp->sreg1 = temp->dreg = temp_reg2;
2051 temp->sreg2 = temp_reg1;
2053 ins->opcode = OP_EXPAND_I2;
2054 ins->sreg1 = temp_reg2;
2063 bb->max_vreg = cfg->next_vreg;
2067 branch_cc_table [] = {
2068 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2069 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2070 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2073 /* Maps CMP_... constants to X86_CC_... constants */
2076 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2077 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2081 cc_signed_table [] = {
2082 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2083 FALSE, FALSE, FALSE, FALSE
2086 static unsigned char*
2087 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2089 #define XMM_TEMP_REG 0
2090 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2091 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2092 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2093 /* optimize by assigning a local var for this use so we avoid
2094 * the stack manipulations */
2095 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2096 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2097 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2098 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2099 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2101 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2103 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2106 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2107 x86_fnstcw_membase(code, X86_ESP, 0);
2108 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2109 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2110 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2111 x86_fldcw_membase (code, X86_ESP, 2);
2113 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2114 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2115 x86_pop_reg (code, dreg);
2116 /* FIXME: need the high register
2117 * x86_pop_reg (code, dreg_high);
2120 x86_push_reg (code, X86_EAX); // SP = SP - 4
2121 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2122 x86_pop_reg (code, dreg);
2124 x86_fldcw_membase (code, X86_ESP, 0);
2125 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2128 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2130 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2134 static unsigned char*
2135 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2137 int sreg = tree->sreg1;
2138 int need_touch = FALSE;
2140 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2149 * If requested stack size is larger than one page,
2150 * perform stack-touch operation
2153 * Generate stack probe code.
2154 * Under Windows, it is necessary to allocate one page at a time,
2155 * "touching" stack after each successful sub-allocation. This is
2156 * because of the way stack growth is implemented - there is a
2157 * guard page before the lowest stack page that is currently commited.
2158 * Stack normally grows sequentially so OS traps access to the
2159 * guard page and commits more pages when needed.
2161 x86_test_reg_imm (code, sreg, ~0xFFF);
2162 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2164 br[2] = code; /* loop */
2165 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2166 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2169 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2170 * that follows only initializes the last part of the area.
2172 /* Same as the init code below with size==0x1000 */
2173 if (tree->flags & MONO_INST_INIT) {
2174 x86_push_reg (code, X86_EAX);
2175 x86_push_reg (code, X86_ECX);
2176 x86_push_reg (code, X86_EDI);
2177 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2178 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2179 if (cfg->param_area)
2180 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2182 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2184 x86_prefix (code, X86_REP_PREFIX);
2186 x86_pop_reg (code, X86_EDI);
2187 x86_pop_reg (code, X86_ECX);
2188 x86_pop_reg (code, X86_EAX);
2191 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2192 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2193 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2194 x86_patch (br[3], br[2]);
2195 x86_test_reg_reg (code, sreg, sreg);
2196 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2197 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2199 br[1] = code; x86_jump8 (code, 0);
2201 x86_patch (br[0], code);
2202 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2203 x86_patch (br[1], code);
2204 x86_patch (br[4], code);
2207 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2209 if (tree->flags & MONO_INST_INIT) {
2211 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2212 x86_push_reg (code, X86_EAX);
2215 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2216 x86_push_reg (code, X86_ECX);
2219 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2220 x86_push_reg (code, X86_EDI);
2224 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2225 if (sreg != X86_ECX)
2226 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2227 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2229 if (cfg->param_area)
2230 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2232 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2234 x86_prefix (code, X86_REP_PREFIX);
2237 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2238 x86_pop_reg (code, X86_EDI);
2239 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2240 x86_pop_reg (code, X86_ECX);
2241 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2242 x86_pop_reg (code, X86_EAX);
2249 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2251 /* Move return value to the target register */
2252 switch (ins->opcode) {
2255 case OP_CALL_MEMBASE:
2256 if (ins->dreg != X86_EAX)
2257 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2267 static int tls_gs_offset;
2271 mono_arch_have_fast_tls (void)
2274 static gboolean have_fast_tls = FALSE;
2275 static gboolean inited = FALSE;
2278 if (mini_get_debug_options ()->use_fallback_tls)
2281 return have_fast_tls;
2283 ins = (guint32*)pthread_getspecific;
2285 * We're looking for these two instructions:
2287 * mov 0x4(%esp),%eax
2288 * mov %gs:[offset](,%eax,4),%eax
2290 have_fast_tls = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2291 tls_gs_offset = ins [2];
2294 return have_fast_tls;
2295 #elif defined(TARGET_ANDROID)
2298 if (mini_get_debug_options ()->use_fallback_tls)
2305 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2307 #if defined(TARGET_MACH)
2308 x86_prefix (code, X86_GS_PREFIX);
2309 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2310 #elif defined(TARGET_WIN32)
2312 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2313 * Journal and/or a disassembly of the TlsGet () function.
2315 x86_prefix (code, X86_FS_PREFIX);
2316 x86_mov_reg_mem (code, dreg, 0x18, 4);
2317 if (tls_offset < 64) {
2318 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2322 g_assert (tls_offset < 0x440);
2323 /* Load TEB->TlsExpansionSlots */
2324 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2325 x86_test_reg_reg (code, dreg, dreg);
2327 x86_branch (code, X86_CC_EQ, code, TRUE);
2328 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2329 x86_patch (buf [0], code);
2332 if (optimize_for_xen) {
2333 x86_prefix (code, X86_GS_PREFIX);
2334 x86_mov_reg_mem (code, dreg, 0, 4);
2335 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2337 x86_prefix (code, X86_GS_PREFIX);
2338 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2345 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2347 #if defined(TARGET_MACH)
2348 x86_prefix (code, X86_GS_PREFIX);
2349 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2350 #elif defined(TARGET_WIN32)
2351 g_assert_not_reached ();
2353 x86_prefix (code, X86_GS_PREFIX);
2354 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2362 * Emit code to initialize an LMF structure at LMF_OFFSET.
2365 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2367 /* save all caller saved regs */
2368 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2369 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2370 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2371 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2372 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2373 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2374 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2376 /* save the current IP */
2377 if (cfg->compile_aot) {
2378 /* This pushes the current ip */
2379 x86_call_imm (code, 0);
2380 x86_pop_reg (code, X86_EAX);
2382 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2383 x86_mov_reg_imm (code, X86_EAX, 0);
2385 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2387 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2388 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2389 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2390 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2391 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2392 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2393 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2394 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2395 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2400 /* benchmark and set based on cpu */
2401 #define LOOP_ALIGNMENT 8
2402 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2406 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2411 guint8 *code = cfg->native_code + cfg->code_len;
2414 if (cfg->opt & MONO_OPT_LOOP) {
2415 int pad, align = LOOP_ALIGNMENT;
2416 /* set alignment depending on cpu */
2417 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2419 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2420 x86_padding (code, pad);
2421 cfg->code_len += pad;
2422 bb->native_offset = cfg->code_len;
2426 if (cfg->verbose_level > 2)
2427 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2429 cpos = bb->max_offset;
2431 offset = code - cfg->native_code;
2433 mono_debug_open_block (cfg, bb, offset);
2435 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2436 x86_breakpoint (code);
2438 MONO_BB_FOR_EACH_INS (bb, ins) {
2439 offset = code - cfg->native_code;
2441 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2443 #define EXTRA_CODE_SPACE (16)
2445 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2446 cfg->code_size *= 2;
2447 cfg->native_code = mono_realloc_native_code(cfg);
2448 code = cfg->native_code + offset;
2449 cfg->stat_code_reallocs++;
2452 if (cfg->debug_info)
2453 mono_debug_record_line_number (cfg, ins, offset);
2455 switch (ins->opcode) {
2457 x86_mul_reg (code, ins->sreg2, TRUE);
2460 x86_mul_reg (code, ins->sreg2, FALSE);
2462 case OP_X86_SETEQ_MEMBASE:
2463 case OP_X86_SETNE_MEMBASE:
2464 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2465 ins->inst_basereg, ins->inst_offset, TRUE);
2467 case OP_STOREI1_MEMBASE_IMM:
2468 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2470 case OP_STOREI2_MEMBASE_IMM:
2471 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2473 case OP_STORE_MEMBASE_IMM:
2474 case OP_STOREI4_MEMBASE_IMM:
2475 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2477 case OP_STOREI1_MEMBASE_REG:
2478 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2480 case OP_STOREI2_MEMBASE_REG:
2481 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2483 case OP_STORE_MEMBASE_REG:
2484 case OP_STOREI4_MEMBASE_REG:
2485 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2487 case OP_STORE_MEM_IMM:
2488 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2491 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2495 /* These are created by the cprop pass so they use inst_imm as the source */
2496 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2499 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2502 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2504 case OP_LOAD_MEMBASE:
2505 case OP_LOADI4_MEMBASE:
2506 case OP_LOADU4_MEMBASE:
2507 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2509 case OP_LOADU1_MEMBASE:
2510 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2512 case OP_LOADI1_MEMBASE:
2513 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2515 case OP_LOADU2_MEMBASE:
2516 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2518 case OP_LOADI2_MEMBASE:
2519 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2521 case OP_ICONV_TO_I1:
2523 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2525 case OP_ICONV_TO_I2:
2527 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2529 case OP_ICONV_TO_U1:
2530 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2532 case OP_ICONV_TO_U2:
2533 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2537 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2539 case OP_COMPARE_IMM:
2540 case OP_ICOMPARE_IMM:
2541 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2543 case OP_X86_COMPARE_MEMBASE_REG:
2544 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2546 case OP_X86_COMPARE_MEMBASE_IMM:
2547 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2549 case OP_X86_COMPARE_MEMBASE8_IMM:
2550 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2552 case OP_X86_COMPARE_REG_MEMBASE:
2553 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2555 case OP_X86_COMPARE_MEM_IMM:
2556 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2558 case OP_X86_TEST_NULL:
2559 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2561 case OP_X86_ADD_MEMBASE_IMM:
2562 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2564 case OP_X86_ADD_REG_MEMBASE:
2565 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2567 case OP_X86_SUB_MEMBASE_IMM:
2568 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2570 case OP_X86_SUB_REG_MEMBASE:
2571 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2573 case OP_X86_AND_MEMBASE_IMM:
2574 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2576 case OP_X86_OR_MEMBASE_IMM:
2577 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2579 case OP_X86_XOR_MEMBASE_IMM:
2580 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2582 case OP_X86_ADD_MEMBASE_REG:
2583 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2585 case OP_X86_SUB_MEMBASE_REG:
2586 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2588 case OP_X86_AND_MEMBASE_REG:
2589 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2591 case OP_X86_OR_MEMBASE_REG:
2592 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2594 case OP_X86_XOR_MEMBASE_REG:
2595 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2597 case OP_X86_INC_MEMBASE:
2598 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2600 case OP_X86_INC_REG:
2601 x86_inc_reg (code, ins->dreg);
2603 case OP_X86_DEC_MEMBASE:
2604 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2606 case OP_X86_DEC_REG:
2607 x86_dec_reg (code, ins->dreg);
2609 case OP_X86_MUL_REG_MEMBASE:
2610 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2612 case OP_X86_AND_REG_MEMBASE:
2613 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2615 case OP_X86_OR_REG_MEMBASE:
2616 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2618 case OP_X86_XOR_REG_MEMBASE:
2619 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2622 x86_breakpoint (code);
2624 case OP_RELAXED_NOP:
2625 x86_prefix (code, X86_REP_PREFIX);
2633 case OP_DUMMY_STORE:
2634 case OP_DUMMY_ICONST:
2635 case OP_DUMMY_R8CONST:
2636 case OP_NOT_REACHED:
2639 case OP_IL_SEQ_POINT:
2640 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2642 case OP_SEQ_POINT: {
2645 if (cfg->compile_aot)
2648 /* Have to use ecx as a temp reg since this can occur after OP_SETRET */
2651 * We do this _before_ the breakpoint, so single stepping after
2652 * a breakpoint is hit will step to the next IL offset.
2654 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
2655 MonoInst *var = cfg->arch.ss_tramp_var;
2659 g_assert (var->opcode == OP_REGOFFSET);
2660 /* Load ss_tramp_var */
2661 /* This is equal to &ss_trampoline */
2662 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, sizeof (mgreg_t));
2663 x86_mov_reg_membase (code, X86_ECX, X86_ECX, 0, sizeof (mgreg_t));
2664 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
2665 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2666 x86_call_reg (code, X86_ECX);
2667 x86_patch (br [0], code);
2671 * Many parts of sdb depend on the ip after the single step trampoline call to be equal to the seq point offset.
2672 * This means we have to put the loading of bp_tramp_var after the offset.
2675 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2677 MonoInst *var = cfg->arch.bp_tramp_var;
2680 g_assert (var->opcode == OP_REGOFFSET);
2681 /* Load the address of the bp trampoline */
2682 /* This needs to be constant size */
2683 guint8 *start = code;
2684 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, 4);
2685 if (code < start + OP_SEQ_POINT_BP_OFFSET) {
2686 int size = start + OP_SEQ_POINT_BP_OFFSET - code;
2687 x86_padding (code, size);
2690 * A placeholder for a possible breakpoint inserted by
2691 * mono_arch_set_breakpoint ().
2693 for (i = 0; i < 2; ++i)
2696 * Add an additional nop so skipping the bp doesn't cause the ip to point
2697 * to another IL offset.
2705 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2709 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2714 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2718 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2723 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2727 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2732 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2736 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2739 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2743 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2748 * The code is the same for div/rem, the allocator will allocate dreg
2749 * to RAX/RDX as appropriate.
2751 if (ins->sreg2 == X86_EDX) {
2752 /* cdq clobbers this */
2753 x86_push_reg (code, ins->sreg2);
2755 x86_div_membase (code, X86_ESP, 0, TRUE);
2756 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2759 x86_div_reg (code, ins->sreg2, TRUE);
2764 if (ins->sreg2 == X86_EDX) {
2765 x86_push_reg (code, ins->sreg2);
2766 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2767 x86_div_membase (code, X86_ESP, 0, FALSE);
2768 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2770 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2771 x86_div_reg (code, ins->sreg2, FALSE);
2775 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2777 x86_div_reg (code, ins->sreg2, TRUE);
2780 int power = mono_is_power_of_two (ins->inst_imm);
2782 g_assert (ins->sreg1 == X86_EAX);
2783 g_assert (ins->dreg == X86_EAX);
2784 g_assert (power >= 0);
2787 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2789 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2791 * If the divident is >= 0, this does not nothing. If it is positive, it
2792 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2794 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2795 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2796 } else if (power == 0) {
2797 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2799 /* Based on gcc code */
2801 /* Add compensation for negative dividents */
2803 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2804 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2805 /* Compute remainder */
2806 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2807 /* Remove compensation */
2808 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2813 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2817 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2820 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2824 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2827 g_assert (ins->sreg2 == X86_ECX);
2828 x86_shift_reg (code, X86_SHL, ins->dreg);
2831 g_assert (ins->sreg2 == X86_ECX);
2832 x86_shift_reg (code, X86_SAR, ins->dreg);
2836 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2839 case OP_ISHR_UN_IMM:
2840 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2843 g_assert (ins->sreg2 == X86_ECX);
2844 x86_shift_reg (code, X86_SHR, ins->dreg);
2848 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2851 guint8 *jump_to_end;
2853 /* handle shifts below 32 bits */
2854 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2855 x86_shift_reg (code, X86_SHL, ins->sreg1);
2857 x86_test_reg_imm (code, X86_ECX, 32);
2858 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2860 /* handle shift over 32 bit */
2861 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2862 x86_clear_reg (code, ins->sreg1);
2864 x86_patch (jump_to_end, code);
2868 guint8 *jump_to_end;
2870 /* handle shifts below 32 bits */
2871 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2872 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2874 x86_test_reg_imm (code, X86_ECX, 32);
2875 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2877 /* handle shifts over 31 bits */
2878 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2879 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2881 x86_patch (jump_to_end, code);
2885 guint8 *jump_to_end;
2887 /* handle shifts below 32 bits */
2888 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2889 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2891 x86_test_reg_imm (code, X86_ECX, 32);
2892 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2894 /* handle shifts over 31 bits */
2895 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2896 x86_clear_reg (code, ins->backend.reg3);
2898 x86_patch (jump_to_end, code);
2902 if (ins->inst_imm >= 32) {
2903 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2904 x86_clear_reg (code, ins->sreg1);
2905 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2907 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2908 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2912 if (ins->inst_imm >= 32) {
2913 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2914 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2915 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2917 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2918 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2921 case OP_LSHR_UN_IMM:
2922 if (ins->inst_imm >= 32) {
2923 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2924 x86_clear_reg (code, ins->backend.reg3);
2925 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2927 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2928 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2932 x86_not_reg (code, ins->sreg1);
2935 x86_neg_reg (code, ins->sreg1);
2939 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2943 switch (ins->inst_imm) {
2947 if (ins->dreg != ins->sreg1)
2948 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2949 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2952 /* LEA r1, [r2 + r2*2] */
2953 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2956 /* LEA r1, [r2 + r2*4] */
2957 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2960 /* LEA r1, [r2 + r2*2] */
2962 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2963 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2966 /* LEA r1, [r2 + r2*8] */
2967 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2970 /* LEA r1, [r2 + r2*4] */
2972 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2973 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2976 /* LEA r1, [r2 + r2*2] */
2978 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2979 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2982 /* LEA r1, [r2 + r2*4] */
2983 /* LEA r1, [r1 + r1*4] */
2984 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2985 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2988 /* LEA r1, [r2 + r2*4] */
2990 /* LEA r1, [r1 + r1*4] */
2991 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2992 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2993 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2996 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3001 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3002 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3004 case OP_IMUL_OVF_UN: {
3005 /* the mul operation and the exception check should most likely be split */
3006 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3007 /*g_assert (ins->sreg2 == X86_EAX);
3008 g_assert (ins->dreg == X86_EAX);*/
3009 if (ins->sreg2 == X86_EAX) {
3010 non_eax_reg = ins->sreg1;
3011 } else if (ins->sreg1 == X86_EAX) {
3012 non_eax_reg = ins->sreg2;
3014 /* no need to save since we're going to store to it anyway */
3015 if (ins->dreg != X86_EAX) {
3017 x86_push_reg (code, X86_EAX);
3019 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3020 non_eax_reg = ins->sreg2;
3022 if (ins->dreg == X86_EDX) {
3025 x86_push_reg (code, X86_EAX);
3029 x86_push_reg (code, X86_EDX);
3031 x86_mul_reg (code, non_eax_reg, FALSE);
3032 /* save before the check since pop and mov don't change the flags */
3033 if (ins->dreg != X86_EAX)
3034 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3036 x86_pop_reg (code, X86_EDX);
3038 x86_pop_reg (code, X86_EAX);
3039 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3043 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3046 g_assert_not_reached ();
3047 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3048 x86_mov_reg_imm (code, ins->dreg, 0);
3051 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3052 x86_mov_reg_imm (code, ins->dreg, 0);
3054 case OP_LOAD_GOTADDR:
3055 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3056 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3059 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3060 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3062 case OP_X86_PUSH_GOT_ENTRY:
3063 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3064 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3067 if (ins->dreg != ins->sreg1)
3068 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3071 MonoCallInst *call = (MonoCallInst*)ins;
3074 ins->flags |= MONO_INST_GC_CALLSITE;
3075 ins->backend.pc_offset = code - cfg->native_code;
3077 /* reset offset to make max_len work */
3078 offset = code - cfg->native_code;
3080 g_assert (!cfg->method->save_lmf);
3082 /* restore callee saved registers */
3083 for (i = 0; i < X86_NREG; ++i)
3084 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3086 if (cfg->used_int_regs & (1 << X86_ESI)) {
3087 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3090 if (cfg->used_int_regs & (1 << X86_EDI)) {
3091 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3094 if (cfg->used_int_regs & (1 << X86_EBX)) {
3095 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3099 /* Copy arguments on the stack to our argument area */
3100 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3101 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3102 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3105 /* restore ESP/EBP */
3107 offset = code - cfg->native_code;
3108 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3109 x86_jump32 (code, 0);
3111 ins->flags |= MONO_INST_GC_CALLSITE;
3112 cfg->disable_aot = TRUE;
3116 /* ensure ins->sreg1 is not NULL
3117 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3118 * cmp DWORD PTR [eax], 0
3120 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3123 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3124 x86_push_reg (code, hreg);
3125 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3126 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3127 x86_pop_reg (code, hreg);
3140 case OP_VOIDCALL_REG:
3142 case OP_FCALL_MEMBASE:
3143 case OP_LCALL_MEMBASE:
3144 case OP_VCALL_MEMBASE:
3145 case OP_VCALL2_MEMBASE:
3146 case OP_VOIDCALL_MEMBASE:
3147 case OP_CALL_MEMBASE: {
3150 call = (MonoCallInst*)ins;
3151 cinfo = (CallInfo*)call->call_info;
3153 switch (ins->opcode) {
3160 if (ins->flags & MONO_INST_HAS_METHOD)
3161 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3163 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3169 case OP_VOIDCALL_REG:
3171 x86_call_reg (code, ins->sreg1);
3173 case OP_FCALL_MEMBASE:
3174 case OP_LCALL_MEMBASE:
3175 case OP_VCALL_MEMBASE:
3176 case OP_VCALL2_MEMBASE:
3177 case OP_VOIDCALL_MEMBASE:
3178 case OP_CALL_MEMBASE:
3179 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3182 g_assert_not_reached ();
3185 ins->flags |= MONO_INST_GC_CALLSITE;
3186 ins->backend.pc_offset = code - cfg->native_code;
3187 if (cinfo->callee_stack_pop) {
3188 /* Have to compensate for the stack space popped by the callee */
3189 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3191 code = emit_move_return_value (cfg, ins, code);
3195 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3197 case OP_X86_LEA_MEMBASE:
3198 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3201 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3204 /* keep alignment */
3205 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3206 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3207 code = mono_emit_stack_alloc (cfg, code, ins);
3208 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3209 if (cfg->param_area)
3210 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3212 case OP_LOCALLOC_IMM: {
3213 guint32 size = ins->inst_imm;
3214 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3216 if (ins->flags & MONO_INST_INIT) {
3217 /* FIXME: Optimize this */
3218 x86_mov_reg_imm (code, ins->dreg, size);
3219 ins->sreg1 = ins->dreg;
3221 code = mono_emit_stack_alloc (cfg, code, ins);
3222 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3224 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3225 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3227 if (cfg->param_area)
3228 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3232 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3233 x86_push_reg (code, ins->sreg1);
3234 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3235 (gpointer)"mono_arch_throw_exception");
3236 ins->flags |= MONO_INST_GC_CALLSITE;
3237 ins->backend.pc_offset = code - cfg->native_code;
3241 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3242 x86_push_reg (code, ins->sreg1);
3243 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3244 (gpointer)"mono_arch_rethrow_exception");
3245 ins->flags |= MONO_INST_GC_CALLSITE;
3246 ins->backend.pc_offset = code - cfg->native_code;
3249 case OP_CALL_HANDLER:
3250 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3251 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3252 x86_call_imm (code, 0);
3253 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3254 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3256 case OP_START_HANDLER: {
3257 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3258 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3259 if (cfg->param_area)
3260 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3263 case OP_ENDFINALLY: {
3264 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3265 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3269 case OP_ENDFILTER: {
3270 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3271 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3272 /* The local allocator will put the result into EAX */
3277 if (ins->dreg != X86_EAX)
3278 x86_mov_reg_reg (code, ins->dreg, X86_EAX, sizeof (gpointer));
3282 ins->inst_c0 = code - cfg->native_code;
3285 if (ins->inst_target_bb->native_offset) {
3286 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3288 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3289 if ((cfg->opt & MONO_OPT_BRANCH) &&
3290 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3291 x86_jump8 (code, 0);
3293 x86_jump32 (code, 0);
3297 x86_jump_reg (code, ins->sreg1);
3316 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3317 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3319 case OP_COND_EXC_EQ:
3320 case OP_COND_EXC_NE_UN:
3321 case OP_COND_EXC_LT:
3322 case OP_COND_EXC_LT_UN:
3323 case OP_COND_EXC_GT:
3324 case OP_COND_EXC_GT_UN:
3325 case OP_COND_EXC_GE:
3326 case OP_COND_EXC_GE_UN:
3327 case OP_COND_EXC_LE:
3328 case OP_COND_EXC_LE_UN:
3329 case OP_COND_EXC_IEQ:
3330 case OP_COND_EXC_INE_UN:
3331 case OP_COND_EXC_ILT:
3332 case OP_COND_EXC_ILT_UN:
3333 case OP_COND_EXC_IGT:
3334 case OP_COND_EXC_IGT_UN:
3335 case OP_COND_EXC_IGE:
3336 case OP_COND_EXC_IGE_UN:
3337 case OP_COND_EXC_ILE:
3338 case OP_COND_EXC_ILE_UN:
3339 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3341 case OP_COND_EXC_OV:
3342 case OP_COND_EXC_NO:
3344 case OP_COND_EXC_NC:
3345 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3347 case OP_COND_EXC_IOV:
3348 case OP_COND_EXC_INO:
3349 case OP_COND_EXC_IC:
3350 case OP_COND_EXC_INC:
3351 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3363 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3371 case OP_CMOV_INE_UN:
3372 case OP_CMOV_IGE_UN:
3373 case OP_CMOV_IGT_UN:
3374 case OP_CMOV_ILE_UN:
3375 case OP_CMOV_ILT_UN:
3376 g_assert (ins->dreg == ins->sreg1);
3377 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3380 /* floating point opcodes */
3382 double d = *(double *)ins->inst_p0;
3384 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3386 } else if (d == 1.0) {
3389 if (cfg->compile_aot) {
3390 guint32 *val = (guint32*)&d;
3391 x86_push_imm (code, val [1]);
3392 x86_push_imm (code, val [0]);
3393 x86_fld_membase (code, X86_ESP, 0, TRUE);
3394 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3397 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3398 x86_fld (code, NULL, TRUE);
3404 float f = *(float *)ins->inst_p0;
3406 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3408 } else if (f == 1.0) {
3411 if (cfg->compile_aot) {
3412 guint32 val = *(guint32*)&f;
3413 x86_push_imm (code, val);
3414 x86_fld_membase (code, X86_ESP, 0, FALSE);
3415 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3418 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3419 x86_fld (code, NULL, FALSE);
3424 case OP_STORER8_MEMBASE_REG:
3425 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3427 case OP_LOADR8_MEMBASE:
3428 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3430 case OP_STORER4_MEMBASE_REG:
3431 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3433 case OP_LOADR4_MEMBASE:
3434 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3436 case OP_ICONV_TO_R4:
3437 x86_push_reg (code, ins->sreg1);
3438 x86_fild_membase (code, X86_ESP, 0, FALSE);
3439 /* Change precision */
3440 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3441 x86_fld_membase (code, X86_ESP, 0, FALSE);
3442 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3444 case OP_ICONV_TO_R8:
3445 x86_push_reg (code, ins->sreg1);
3446 x86_fild_membase (code, X86_ESP, 0, FALSE);
3447 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3449 case OP_ICONV_TO_R_UN:
3450 x86_push_imm (code, 0);
3451 x86_push_reg (code, ins->sreg1);
3452 x86_fild_membase (code, X86_ESP, 0, TRUE);
3453 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3455 case OP_X86_FP_LOAD_I8:
3456 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3458 case OP_X86_FP_LOAD_I4:
3459 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3461 case OP_FCONV_TO_R4:
3462 /* Change precision */
3463 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3464 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3465 x86_fld_membase (code, X86_ESP, 0, FALSE);
3466 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3468 case OP_FCONV_TO_I1:
3469 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3471 case OP_FCONV_TO_U1:
3472 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3474 case OP_FCONV_TO_I2:
3475 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3477 case OP_FCONV_TO_U2:
3478 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3480 case OP_FCONV_TO_I4:
3482 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3484 case OP_FCONV_TO_I8:
3485 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3486 x86_fnstcw_membase(code, X86_ESP, 0);
3487 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3488 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3489 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3490 x86_fldcw_membase (code, X86_ESP, 2);
3491 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3492 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3493 x86_pop_reg (code, ins->dreg);
3494 x86_pop_reg (code, ins->backend.reg3);
3495 x86_fldcw_membase (code, X86_ESP, 0);
3496 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3498 case OP_LCONV_TO_R8_2:
3499 x86_push_reg (code, ins->sreg2);
3500 x86_push_reg (code, ins->sreg1);
3501 x86_fild_membase (code, X86_ESP, 0, TRUE);
3502 /* Change precision */
3503 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3504 x86_fld_membase (code, X86_ESP, 0, TRUE);
3505 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3507 case OP_LCONV_TO_R4_2:
3508 x86_push_reg (code, ins->sreg2);
3509 x86_push_reg (code, ins->sreg1);
3510 x86_fild_membase (code, X86_ESP, 0, TRUE);
3511 /* Change precision */
3512 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3513 x86_fld_membase (code, X86_ESP, 0, FALSE);
3514 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3516 case OP_LCONV_TO_R_UN_2: {
3517 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3520 /* load 64bit integer to FP stack */
3521 x86_push_reg (code, ins->sreg2);
3522 x86_push_reg (code, ins->sreg1);
3523 x86_fild_membase (code, X86_ESP, 0, TRUE);
3525 /* test if lreg is negative */
3526 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3527 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3529 /* add correction constant mn */
3530 if (cfg->compile_aot) {
3531 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3532 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3533 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3534 x86_fld80_membase (code, X86_ESP, 2);
3535 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3537 x86_fld80_mem (code, mn);
3539 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3541 x86_patch (br, code);
3543 /* Change precision */
3544 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3545 x86_fld_membase (code, X86_ESP, 0, TRUE);
3547 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3551 case OP_LCONV_TO_OVF_I:
3552 case OP_LCONV_TO_OVF_I4_2: {
3553 guint8 *br [3], *label [1];
3557 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3559 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3561 /* If the low word top bit is set, see if we are negative */
3562 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3563 /* We are not negative (no top bit set, check for our top word to be zero */
3564 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3565 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3568 /* throw exception */
3569 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3571 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3572 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3573 x86_jump8 (code, 0);
3575 x86_jump32 (code, 0);
3577 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3578 x86_jump32 (code, 0);
3582 x86_patch (br [0], code);
3583 /* our top bit is set, check that top word is 0xfffffff */
3584 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3586 x86_patch (br [1], code);
3587 /* nope, emit exception */
3588 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3589 x86_patch (br [2], label [0]);
3591 if (ins->dreg != ins->sreg1)
3592 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3596 /* Not needed on the fp stack */
3598 case OP_MOVE_F_TO_I4:
3599 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
3600 x86_mov_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, 4);
3602 case OP_MOVE_I4_TO_F:
3603 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
3604 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
3607 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3610 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3613 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3616 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3624 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3629 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3636 * it really doesn't make sense to inline all this code,
3637 * it's here just to show that things may not be as simple
3640 guchar *check_pos, *end_tan, *pop_jump;
3641 x86_push_reg (code, X86_EAX);
3644 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3646 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3647 x86_fstp (code, 0); /* pop the 1.0 */
3649 x86_jump8 (code, 0);
3651 x86_fp_op (code, X86_FADD, 0);
3655 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3657 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3660 x86_patch (pop_jump, code);
3661 x86_fstp (code, 0); /* pop the 1.0 */
3662 x86_patch (check_pos, code);
3663 x86_patch (end_tan, code);
3665 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3666 x86_pop_reg (code, X86_EAX);
3673 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3682 g_assert (cfg->opt & MONO_OPT_CMOV);
3683 g_assert (ins->dreg == ins->sreg1);
3684 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3685 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3688 g_assert (cfg->opt & MONO_OPT_CMOV);
3689 g_assert (ins->dreg == ins->sreg1);
3690 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3691 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3694 g_assert (cfg->opt & MONO_OPT_CMOV);
3695 g_assert (ins->dreg == ins->sreg1);
3696 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3697 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3700 g_assert (cfg->opt & MONO_OPT_CMOV);
3701 g_assert (ins->dreg == ins->sreg1);
3702 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3703 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3709 x86_fxch (code, ins->inst_imm);
3714 x86_push_reg (code, X86_EAX);
3715 /* we need to exchange ST(0) with ST(1) */
3718 /* this requires a loop, because fprem somtimes
3719 * returns a partial remainder */
3721 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3722 /* x86_fprem1 (code); */
3725 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3727 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3733 x86_pop_reg (code, X86_EAX);
3737 if (cfg->opt & MONO_OPT_FCMOV) {
3738 x86_fcomip (code, 1);
3742 /* this overwrites EAX */
3743 EMIT_FPCOMPARE(code);
3744 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3748 if (cfg->opt & MONO_OPT_FCMOV) {
3749 /* zeroing the register at the start results in
3750 * shorter and faster code (we can also remove the widening op)
3752 guchar *unordered_check;
3753 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3754 x86_fcomip (code, 1);
3756 unordered_check = code;
3757 x86_branch8 (code, X86_CC_P, 0, FALSE);
3758 if (ins->opcode == OP_FCEQ) {
3759 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3760 x86_patch (unordered_check, code);
3762 guchar *jump_to_end;
3763 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3765 x86_jump8 (code, 0);
3766 x86_patch (unordered_check, code);
3767 x86_inc_reg (code, ins->dreg);
3768 x86_patch (jump_to_end, code);
3773 if (ins->dreg != X86_EAX)
3774 x86_push_reg (code, X86_EAX);
3776 EMIT_FPCOMPARE(code);
3777 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3778 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3779 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3780 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3782 if (ins->dreg != X86_EAX)
3783 x86_pop_reg (code, X86_EAX);
3787 if (cfg->opt & MONO_OPT_FCMOV) {
3788 /* zeroing the register at the start results in
3789 * shorter and faster code (we can also remove the widening op)
3791 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3792 x86_fcomip (code, 1);
3794 if (ins->opcode == OP_FCLT_UN) {
3795 guchar *unordered_check = code;
3796 guchar *jump_to_end;
3797 x86_branch8 (code, X86_CC_P, 0, FALSE);
3798 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3800 x86_jump8 (code, 0);
3801 x86_patch (unordered_check, code);
3802 x86_inc_reg (code, ins->dreg);
3803 x86_patch (jump_to_end, code);
3805 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3809 if (ins->dreg != X86_EAX)
3810 x86_push_reg (code, X86_EAX);
3812 EMIT_FPCOMPARE(code);
3813 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3814 if (ins->opcode == OP_FCLT_UN) {
3815 guchar *is_not_zero_check, *end_jump;
3816 is_not_zero_check = code;
3817 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3819 x86_jump8 (code, 0);
3820 x86_patch (is_not_zero_check, code);
3821 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3823 x86_patch (end_jump, code);
3825 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3826 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3828 if (ins->dreg != X86_EAX)
3829 x86_pop_reg (code, X86_EAX);
3832 guchar *unordered_check;
3833 guchar *jump_to_end;
3834 if (cfg->opt & MONO_OPT_FCMOV) {
3835 /* zeroing the register at the start results in
3836 * shorter and faster code (we can also remove the widening op)
3838 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3839 x86_fcomip (code, 1);
3841 unordered_check = code;
3842 x86_branch8 (code, X86_CC_P, 0, FALSE);
3843 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3844 x86_patch (unordered_check, code);
3847 if (ins->dreg != X86_EAX)
3848 x86_push_reg (code, X86_EAX);
3850 EMIT_FPCOMPARE(code);
3851 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3852 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3853 unordered_check = code;
3854 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3856 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3857 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3858 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3860 x86_jump8 (code, 0);
3861 x86_patch (unordered_check, code);
3862 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3863 x86_patch (jump_to_end, code);
3865 if (ins->dreg != X86_EAX)
3866 x86_pop_reg (code, X86_EAX);
3871 if (cfg->opt & MONO_OPT_FCMOV) {
3872 /* zeroing the register at the start results in
3873 * shorter and faster code (we can also remove the widening op)
3875 guchar *unordered_check;
3876 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3877 x86_fcomip (code, 1);
3879 if (ins->opcode == OP_FCGT) {
3880 unordered_check = code;
3881 x86_branch8 (code, X86_CC_P, 0, FALSE);
3882 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3883 x86_patch (unordered_check, code);
3885 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3889 if (ins->dreg != X86_EAX)
3890 x86_push_reg (code, X86_EAX);
3892 EMIT_FPCOMPARE(code);
3893 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3894 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3895 if (ins->opcode == OP_FCGT_UN) {
3896 guchar *is_not_zero_check, *end_jump;
3897 is_not_zero_check = code;
3898 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3900 x86_jump8 (code, 0);
3901 x86_patch (is_not_zero_check, code);
3902 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3904 x86_patch (end_jump, code);
3906 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3907 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3909 if (ins->dreg != X86_EAX)
3910 x86_pop_reg (code, X86_EAX);
3913 guchar *unordered_check;
3914 guchar *jump_to_end;
3915 if (cfg->opt & MONO_OPT_FCMOV) {
3916 /* zeroing the register at the start results in
3917 * shorter and faster code (we can also remove the widening op)
3919 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3920 x86_fcomip (code, 1);
3922 unordered_check = code;
3923 x86_branch8 (code, X86_CC_P, 0, FALSE);
3924 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
3925 x86_patch (unordered_check, code);
3928 if (ins->dreg != X86_EAX)
3929 x86_push_reg (code, X86_EAX);
3931 EMIT_FPCOMPARE(code);
3932 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3933 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3934 unordered_check = code;
3935 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3937 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3938 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
3939 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3941 x86_jump8 (code, 0);
3942 x86_patch (unordered_check, code);
3943 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3944 x86_patch (jump_to_end, code);
3946 if (ins->dreg != X86_EAX)
3947 x86_pop_reg (code, X86_EAX);
3951 if (cfg->opt & MONO_OPT_FCMOV) {
3952 guchar *jump = code;
3953 x86_branch8 (code, X86_CC_P, 0, TRUE);
3954 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3955 x86_patch (jump, code);
3958 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3959 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3962 /* Branch if C013 != 100 */
3963 if (cfg->opt & MONO_OPT_FCMOV) {
3964 /* branch if !ZF or (PF|CF) */
3965 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3966 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3967 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3970 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3971 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3974 if (cfg->opt & MONO_OPT_FCMOV) {
3975 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3978 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3981 if (cfg->opt & MONO_OPT_FCMOV) {
3982 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3983 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3986 if (ins->opcode == OP_FBLT_UN) {
3987 guchar *is_not_zero_check, *end_jump;
3988 is_not_zero_check = code;
3989 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3991 x86_jump8 (code, 0);
3992 x86_patch (is_not_zero_check, code);
3993 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3995 x86_patch (end_jump, code);
3997 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4001 if (cfg->opt & MONO_OPT_FCMOV) {
4002 if (ins->opcode == OP_FBGT) {
4005 /* skip branch if C1=1 */
4007 x86_branch8 (code, X86_CC_P, 0, FALSE);
4008 /* branch if (C0 | C3) = 1 */
4009 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4010 x86_patch (br1, code);
4012 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4016 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4017 if (ins->opcode == OP_FBGT_UN) {
4018 guchar *is_not_zero_check, *end_jump;
4019 is_not_zero_check = code;
4020 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4022 x86_jump8 (code, 0);
4023 x86_patch (is_not_zero_check, code);
4024 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4026 x86_patch (end_jump, code);
4028 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4031 /* Branch if C013 == 100 or 001 */
4032 if (cfg->opt & MONO_OPT_FCMOV) {
4035 /* skip branch if C1=1 */
4037 x86_branch8 (code, X86_CC_P, 0, FALSE);
4038 /* branch if (C0 | C3) = 1 */
4039 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4040 x86_patch (br1, code);
4043 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4044 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4045 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4046 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4049 /* Branch if C013 == 000 */
4050 if (cfg->opt & MONO_OPT_FCMOV) {
4051 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4054 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4057 /* Branch if C013=000 or 100 */
4058 if (cfg->opt & MONO_OPT_FCMOV) {
4061 /* skip branch if C1=1 */
4063 x86_branch8 (code, X86_CC_P, 0, FALSE);
4064 /* branch if C0=0 */
4065 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4066 x86_patch (br1, code);
4069 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4070 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4071 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4074 /* Branch if C013 != 001 */
4075 if (cfg->opt & MONO_OPT_FCMOV) {
4076 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4077 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4080 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4081 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4085 x86_push_reg (code, X86_EAX);
4088 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4089 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4090 x86_pop_reg (code, X86_EAX);
4092 /* Have to clean up the fp stack before throwing the exception */
4094 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4097 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
4099 x86_patch (br1, code);
4103 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4107 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4110 case OP_MEMORY_BARRIER: {
4111 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4112 x86_prefix (code, X86_LOCK_PREFIX);
4113 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4117 case OP_ATOMIC_ADD_I4: {
4118 int dreg = ins->dreg;
4120 g_assert (cfg->has_atomic_add_i4);
4122 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4123 if (ins->sreg2 == dreg) {
4124 if (dreg == X86_EBX) {
4126 if (ins->inst_basereg == X86_EDI)
4130 if (ins->inst_basereg == X86_EBX)
4133 } else if (ins->inst_basereg == dreg) {
4134 if (dreg == X86_EBX) {
4136 if (ins->sreg2 == X86_EDI)
4140 if (ins->sreg2 == X86_EBX)
4145 if (dreg != ins->dreg) {
4146 x86_push_reg (code, dreg);
4149 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4150 x86_prefix (code, X86_LOCK_PREFIX);
4151 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4152 /* dreg contains the old value, add with sreg2 value */
4153 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4155 if (ins->dreg != dreg) {
4156 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4157 x86_pop_reg (code, dreg);
4162 case OP_ATOMIC_EXCHANGE_I4: {
4164 int sreg2 = ins->sreg2;
4165 int breg = ins->inst_basereg;
4167 g_assert (cfg->has_atomic_exchange_i4);
4169 /* cmpxchg uses eax as comperand, need to make sure we can use it
4170 * hack to overcome limits in x86 reg allocator
4171 * (req: dreg == eax and sreg2 != eax and breg != eax)
4173 g_assert (ins->dreg == X86_EAX);
4175 /* We need the EAX reg for the cmpxchg */
4176 if (ins->sreg2 == X86_EAX) {
4177 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4178 x86_push_reg (code, sreg2);
4179 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4182 if (breg == X86_EAX) {
4183 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4184 x86_push_reg (code, breg);
4185 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4188 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4190 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4191 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4192 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4193 x86_patch (br [1], br [0]);
4195 if (breg != ins->inst_basereg)
4196 x86_pop_reg (code, breg);
4198 if (ins->sreg2 != sreg2)
4199 x86_pop_reg (code, sreg2);
4203 case OP_ATOMIC_CAS_I4: {
4204 g_assert (ins->dreg == X86_EAX);
4205 g_assert (ins->sreg3 == X86_EAX);
4206 g_assert (ins->sreg1 != X86_EAX);
4207 g_assert (ins->sreg1 != ins->sreg2);
4209 x86_prefix (code, X86_LOCK_PREFIX);
4210 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4213 case OP_ATOMIC_LOAD_I1: {
4214 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4217 case OP_ATOMIC_LOAD_U1: {
4218 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4221 case OP_ATOMIC_LOAD_I2: {
4222 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4225 case OP_ATOMIC_LOAD_U2: {
4226 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4229 case OP_ATOMIC_LOAD_I4:
4230 case OP_ATOMIC_LOAD_U4: {
4231 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4234 case OP_ATOMIC_LOAD_R4:
4235 case OP_ATOMIC_LOAD_R8: {
4236 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4239 case OP_ATOMIC_STORE_I1:
4240 case OP_ATOMIC_STORE_U1:
4241 case OP_ATOMIC_STORE_I2:
4242 case OP_ATOMIC_STORE_U2:
4243 case OP_ATOMIC_STORE_I4:
4244 case OP_ATOMIC_STORE_U4: {
4247 switch (ins->opcode) {
4248 case OP_ATOMIC_STORE_I1:
4249 case OP_ATOMIC_STORE_U1:
4252 case OP_ATOMIC_STORE_I2:
4253 case OP_ATOMIC_STORE_U2:
4256 case OP_ATOMIC_STORE_I4:
4257 case OP_ATOMIC_STORE_U4:
4262 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4264 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4268 case OP_ATOMIC_STORE_R4:
4269 case OP_ATOMIC_STORE_R8: {
4270 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4272 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4276 case OP_CARD_TABLE_WBARRIER: {
4277 int ptr = ins->sreg1;
4278 int value = ins->sreg2;
4280 int nursery_shift, card_table_shift;
4281 gpointer card_table_mask;
4282 size_t nursery_size;
4283 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4284 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4285 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4288 * We need one register we can clobber, we choose EDX and make sreg1
4289 * fixed EAX to work around limitations in the local register allocator.
4290 * sreg2 might get allocated to EDX, but that is not a problem since
4291 * we use it before clobbering EDX.
4293 g_assert (ins->sreg1 == X86_EAX);
4296 * This is the code we produce:
4299 * edx >>= nursery_shift
4300 * cmp edx, (nursery_start >> nursery_shift)
4303 * edx >>= card_table_shift
4304 * card_table[edx] = 1
4308 if (card_table_nursery_check) {
4309 if (value != X86_EDX)
4310 x86_mov_reg_reg (code, X86_EDX, value, 4);
4311 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4312 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4313 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4315 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4316 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4317 if (card_table_mask)
4318 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4319 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4320 if (card_table_nursery_check)
4321 x86_patch (br, code);
4324 #ifdef MONO_ARCH_SIMD_INTRINSICS
4326 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4329 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4332 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4335 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4338 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4341 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4344 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4345 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4348 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4351 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4354 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4357 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4360 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4363 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4366 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4369 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4372 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4375 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4378 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4381 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4384 case OP_PSHUFLEW_HIGH:
4385 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4386 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4388 case OP_PSHUFLEW_LOW:
4389 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4390 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4393 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4394 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4397 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4398 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4401 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4402 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4406 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4409 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4412 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4415 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4418 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4421 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4424 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4425 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4428 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4431 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4434 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4437 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4440 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4443 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4446 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4449 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4452 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4455 case OP_EXTRACT_MASK:
4456 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4460 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4463 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4466 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4470 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4473 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4476 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4479 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4483 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4486 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4489 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4492 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4496 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4499 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4502 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4506 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4509 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4512 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4516 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4519 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4523 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4526 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4529 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4533 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4536 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4539 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4543 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4546 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4549 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4552 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4556 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4559 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4562 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4565 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4568 case OP_PSUM_ABS_DIFF:
4569 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4572 case OP_UNPACK_LOWB:
4573 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4575 case OP_UNPACK_LOWW:
4576 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4578 case OP_UNPACK_LOWD:
4579 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4581 case OP_UNPACK_LOWQ:
4582 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4584 case OP_UNPACK_LOWPS:
4585 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4587 case OP_UNPACK_LOWPD:
4588 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4591 case OP_UNPACK_HIGHB:
4592 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4594 case OP_UNPACK_HIGHW:
4595 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4597 case OP_UNPACK_HIGHD:
4598 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4600 case OP_UNPACK_HIGHQ:
4601 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4603 case OP_UNPACK_HIGHPS:
4604 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4606 case OP_UNPACK_HIGHPD:
4607 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4611 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4614 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4617 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4620 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4623 case OP_PADDB_SAT_UN:
4624 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4626 case OP_PSUBB_SAT_UN:
4627 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4629 case OP_PADDW_SAT_UN:
4630 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4632 case OP_PSUBW_SAT_UN:
4633 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4637 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4640 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4643 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4646 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4650 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4653 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4656 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4658 case OP_PMULW_HIGH_UN:
4659 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4662 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4666 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4669 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4673 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4676 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4680 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4683 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4687 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4690 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4694 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4697 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4701 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4704 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4708 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4711 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4715 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4718 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4722 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4725 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4729 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4731 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4732 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4736 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4738 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4739 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4743 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4745 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4746 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4750 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4752 case OP_EXTRACTX_U2:
4753 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4755 case OP_INSERTX_U1_SLOW:
4756 /*sreg1 is the extracted ireg (scratch)
4757 /sreg2 is the to be inserted ireg (scratch)
4758 /dreg is the xreg to receive the value*/
4760 /*clear the bits from the extracted word*/
4761 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4762 /*shift the value to insert if needed*/
4763 if (ins->inst_c0 & 1)
4764 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4765 /*join them together*/
4766 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4767 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4769 case OP_INSERTX_I4_SLOW:
4770 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4771 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4772 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4775 case OP_INSERTX_R4_SLOW:
4776 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4777 /*TODO if inst_c0 == 0 use movss*/
4778 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4779 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4781 case OP_INSERTX_R8_SLOW:
4782 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4783 if (cfg->verbose_level)
4784 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4786 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4788 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4791 case OP_STOREX_MEMBASE_REG:
4792 case OP_STOREX_MEMBASE:
4793 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4795 case OP_LOADX_MEMBASE:
4796 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4798 case OP_LOADX_ALIGNED_MEMBASE:
4799 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4801 case OP_STOREX_ALIGNED_MEMBASE_REG:
4802 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4804 case OP_STOREX_NTA_MEMBASE_REG:
4805 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4807 case OP_PREFETCH_MEMBASE:
4808 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4812 /*FIXME the peephole pass should have killed this*/
4813 if (ins->dreg != ins->sreg1)
4814 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4817 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4820 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->dreg, ins->dreg);
4823 case OP_FCONV_TO_R8_X:
4824 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4825 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4828 case OP_XCONV_R8_TO_I4:
4829 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4830 switch (ins->backend.source_opcode) {
4831 case OP_FCONV_TO_I1:
4832 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4834 case OP_FCONV_TO_U1:
4835 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4837 case OP_FCONV_TO_I2:
4838 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4840 case OP_FCONV_TO_U2:
4841 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4847 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4848 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4849 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4852 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4853 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4856 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4857 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4858 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4861 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4862 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4863 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4867 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4870 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4873 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4876 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4879 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4882 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4885 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4888 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4892 case OP_LIVERANGE_START: {
4893 if (cfg->verbose_level > 1)
4894 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4895 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4898 case OP_LIVERANGE_END: {
4899 if (cfg->verbose_level > 1)
4900 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4901 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4904 case OP_GC_SAFE_POINT: {
4907 g_assert (mono_threads_is_coop_enabled ());
4909 x86_test_membase_imm (code, ins->sreg1, 0, 1);
4910 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4911 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll");
4912 x86_patch (br [0], code);
4916 case OP_GC_LIVENESS_DEF:
4917 case OP_GC_LIVENESS_USE:
4918 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4919 ins->backend.pc_offset = code - cfg->native_code;
4921 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4922 ins->backend.pc_offset = code - cfg->native_code;
4923 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4926 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
4929 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
4931 case OP_FILL_PROF_CALL_CTX:
4932 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, esp), X86_ESP, sizeof (mgreg_t));
4933 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, ebp), X86_EBP, sizeof (mgreg_t));
4934 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, ebx), X86_EBX, sizeof (mgreg_t));
4935 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, esi), X86_ESI, sizeof (mgreg_t));
4936 x86_mov_membase_reg (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoContext, edi), X86_EDI, sizeof (mgreg_t));
4939 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4940 g_assert_not_reached ();
4943 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4944 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4945 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4946 g_assert_not_reached ();
4952 cfg->code_len = code - cfg->native_code;
4955 #endif /* DISABLE_JIT */
4958 mono_arch_register_lowlevel_calls (void)
4963 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
4965 unsigned char *ip = ji->ip.i + code;
4968 case MONO_PATCH_INFO_IP:
4969 *((gconstpointer *)(ip)) = target;
4971 case MONO_PATCH_INFO_ABS:
4972 case MONO_PATCH_INFO_METHOD:
4973 case MONO_PATCH_INFO_METHOD_JUMP:
4974 case MONO_PATCH_INFO_INTERNAL_METHOD:
4975 case MONO_PATCH_INFO_BB:
4976 case MONO_PATCH_INFO_LABEL:
4977 case MONO_PATCH_INFO_RGCTX_FETCH:
4978 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
4979 x86_patch (ip, (unsigned char*)target);
4981 case MONO_PATCH_INFO_NONE:
4983 case MONO_PATCH_INFO_R4:
4984 case MONO_PATCH_INFO_R8: {
4985 guint32 offset = mono_arch_get_patch_offset (ip);
4986 *((gconstpointer *)(ip + offset)) = target;
4990 guint32 offset = mono_arch_get_patch_offset (ip);
4991 *((gconstpointer *)(ip + offset)) = target;
4997 static G_GNUC_UNUSED void
4998 stack_unaligned (MonoMethod *m, gpointer caller)
5000 printf ("%s\n", mono_method_full_name (m, TRUE));
5001 g_assert_not_reached ();
5005 mono_arch_emit_prolog (MonoCompile *cfg)
5007 MonoMethod *method = cfg->method;
5009 MonoMethodSignature *sig;
5013 int alloc_size, pos, max_offset, i, cfa_offset;
5015 gboolean need_stack_frame;
5017 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5019 code = cfg->native_code = g_malloc (cfg->code_size);
5025 /* Check that the stack is aligned on osx */
5026 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5027 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5028 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5030 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5031 x86_push_membase (code, X86_ESP, 0);
5032 x86_push_imm (code, cfg->method);
5033 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5034 x86_call_reg (code, X86_EAX);
5035 x86_patch (br [0], code);
5039 /* Offset between RSP and the CFA */
5043 cfa_offset = sizeof (gpointer);
5044 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5045 // IP saved at CFA - 4
5046 /* There is no IP reg on x86 */
5047 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5048 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5050 need_stack_frame = needs_stack_frame (cfg);
5052 if (need_stack_frame) {
5053 x86_push_reg (code, X86_EBP);
5054 cfa_offset += sizeof (gpointer);
5055 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5056 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5057 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5058 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5059 /* These are handled automatically by the stack marking code */
5060 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5062 cfg->frame_reg = X86_ESP;
5065 cfg->stack_offset += cfg->param_area;
5066 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5068 alloc_size = cfg->stack_offset;
5071 if (!method->save_lmf) {
5072 if (cfg->used_int_regs & (1 << X86_EBX)) {
5073 x86_push_reg (code, X86_EBX);
5075 cfa_offset += sizeof (gpointer);
5076 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5077 /* These are handled automatically by the stack marking code */
5078 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5081 if (cfg->used_int_regs & (1 << X86_EDI)) {
5082 x86_push_reg (code, X86_EDI);
5084 cfa_offset += sizeof (gpointer);
5085 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5086 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5089 if (cfg->used_int_regs & (1 << X86_ESI)) {
5090 x86_push_reg (code, X86_ESI);
5092 cfa_offset += sizeof (gpointer);
5093 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5094 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5100 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5101 if (mono_do_x86_stack_align && need_stack_frame) {
5102 int tot = alloc_size + pos + 4; /* ret ip */
5103 if (need_stack_frame)
5105 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5107 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5108 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5109 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5113 cfg->arch.sp_fp_offset = alloc_size + pos;
5116 /* See mono_emit_stack_alloc */
5117 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5118 guint32 remaining_size = alloc_size;
5119 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5120 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5121 guint32 offset = code - cfg->native_code;
5122 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5123 while (required_code_size >= (cfg->code_size - offset))
5124 cfg->code_size *= 2;
5125 cfg->native_code = mono_realloc_native_code(cfg);
5126 code = cfg->native_code + offset;
5127 cfg->stat_code_reallocs++;
5129 while (remaining_size >= 0x1000) {
5130 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5131 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5132 remaining_size -= 0x1000;
5135 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5137 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5140 g_assert (need_stack_frame);
5143 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5144 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5145 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5148 #if DEBUG_STACK_ALIGNMENT
5149 /* check the stack is aligned */
5150 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5151 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5152 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5153 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5154 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5155 x86_breakpoint (code);
5159 /* compute max_offset in order to use short forward jumps */
5161 if (cfg->opt & MONO_OPT_BRANCH) {
5162 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5164 bb->max_offset = max_offset;
5166 /* max alignment for loops */
5167 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5168 max_offset += LOOP_ALIGNMENT;
5169 MONO_BB_FOR_EACH_INS (bb, ins) {
5170 if (ins->opcode == OP_LABEL)
5171 ins->inst_c1 = max_offset;
5172 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5177 /* store runtime generic context */
5178 if (cfg->rgctx_var) {
5179 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5181 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5184 if (method->save_lmf)
5185 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5187 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5188 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5193 if (cfg->arch.ss_tramp_var) {
5194 /* Initialize ss_tramp_var */
5195 ins = cfg->arch.ss_tramp_var;
5196 g_assert (ins->opcode == OP_REGOFFSET);
5198 g_assert (!cfg->compile_aot);
5199 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&ss_trampoline, 4);
5202 if (cfg->arch.bp_tramp_var) {
5203 /* Initialize bp_tramp_var */
5204 ins = cfg->arch.bp_tramp_var;
5205 g_assert (ins->opcode == OP_REGOFFSET);
5207 g_assert (!cfg->compile_aot);
5208 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&bp_trampoline, 4);
5212 /* load arguments allocated to register from the stack */
5213 sig = mono_method_signature (method);
5216 cinfo = (CallInfo *)cfg->arch.cinfo;
5218 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5219 inst = cfg->args [pos];
5220 ainfo = &cinfo->args [pos];
5221 if (inst->opcode == OP_REGVAR) {
5222 g_assert (need_stack_frame);
5223 x86_mov_reg_membase (code, inst->dreg, X86_EBP, ainfo->offset + ARGS_OFFSET, 4);
5224 if (cfg->verbose_level > 2)
5225 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5230 cfg->code_len = code - cfg->native_code;
5232 g_assert (cfg->code_len < cfg->code_size);
5238 mono_arch_emit_epilog (MonoCompile *cfg)
5240 MonoMethod *method = cfg->method;
5241 MonoMethodSignature *sig = mono_method_signature (method);
5243 guint32 stack_to_pop;
5245 int max_epilog_size = 16;
5247 gboolean need_stack_frame = needs_stack_frame (cfg);
5249 if (cfg->method->save_lmf)
5250 max_epilog_size += 128;
5252 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5253 cfg->code_size *= 2;
5254 cfg->native_code = mono_realloc_native_code(cfg);
5255 cfg->stat_code_reallocs++;
5258 code = cfg->native_code + cfg->code_len;
5260 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5261 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5263 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5266 if (method->save_lmf) {
5267 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5270 /* check if we need to restore protection of the stack after a stack overflow */
5271 if (!cfg->compile_aot && mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_JIT_TLS) != -1) {
5272 code = mono_x86_emit_tls_get (code, X86_ECX, mono_tls_get_tls_offset (TLS_KEY_JIT_TLS));
5274 /* we load the value in a separate instruction: this mechanism may be
5275 * used later as a safer way to do thread interruption
5277 x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5278 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5280 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5281 /* note that the call trampoline will preserve eax/edx */
5282 x86_call_reg (code, X86_ECX);
5283 x86_patch (patch, code);
5286 /* restore caller saved regs */
5287 if (cfg->used_int_regs & (1 << X86_EBX)) {
5288 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5291 if (cfg->used_int_regs & (1 << X86_EDI)) {
5292 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5294 if (cfg->used_int_regs & (1 << X86_ESI)) {
5295 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5298 /* EBP is restored by LEAVE */
5300 for (i = 0; i < X86_NREG; ++i) {
5301 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5307 g_assert (need_stack_frame);
5308 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5312 g_assert (need_stack_frame);
5313 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5316 if (cfg->used_int_regs & (1 << X86_ESI)) {
5317 x86_pop_reg (code, X86_ESI);
5319 if (cfg->used_int_regs & (1 << X86_EDI)) {
5320 x86_pop_reg (code, X86_EDI);
5322 if (cfg->used_int_regs & (1 << X86_EBX)) {
5323 x86_pop_reg (code, X86_EBX);
5327 /* Load returned vtypes into registers if needed */
5328 cinfo = (CallInfo *)cfg->arch.cinfo;
5329 if (cinfo->ret.storage == ArgValuetypeInReg) {
5330 for (quad = 0; quad < 2; quad ++) {
5331 switch (cinfo->ret.pair_storage [quad]) {
5333 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5335 case ArgOnFloatFpStack:
5336 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5338 case ArgOnDoubleFpStack:
5339 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5344 g_assert_not_reached ();
5349 if (need_stack_frame)
5352 if (CALLCONV_IS_STDCALL (sig)) {
5353 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5355 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
5356 } else if (cinfo->callee_stack_pop)
5357 stack_to_pop = cinfo->callee_stack_pop;
5362 g_assert (need_stack_frame);
5363 x86_ret_imm (code, stack_to_pop);
5368 cfg->code_len = code - cfg->native_code;
5370 g_assert (cfg->code_len < cfg->code_size);
5374 mono_arch_emit_exceptions (MonoCompile *cfg)
5376 MonoJumpInfo *patch_info;
5379 MonoClass *exc_classes [16];
5380 guint8 *exc_throw_start [16], *exc_throw_end [16];
5384 /* Compute needed space */
5385 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5386 if (patch_info->type == MONO_PATCH_INFO_EXC)
5391 * make sure we have enough space for exceptions
5392 * 16 is the size of two push_imm instructions and a call
5394 if (cfg->compile_aot)
5395 code_size = exc_count * 32;
5397 code_size = exc_count * 16;
5399 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5400 cfg->code_size *= 2;
5401 cfg->native_code = mono_realloc_native_code(cfg);
5402 cfg->stat_code_reallocs++;
5405 code = cfg->native_code + cfg->code_len;
5408 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5409 switch (patch_info->type) {
5410 case MONO_PATCH_INFO_EXC: {
5411 MonoClass *exc_class;
5415 x86_patch (patch_info->ip.i + cfg->native_code, code);
5417 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5418 throw_ip = patch_info->ip.i;
5420 /* Find a throw sequence for the same exception class */
5421 for (i = 0; i < nthrows; ++i)
5422 if (exc_classes [i] == exc_class)
5425 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5426 x86_jump_code (code, exc_throw_start [i]);
5427 patch_info->type = MONO_PATCH_INFO_NONE;
5432 /* Compute size of code following the push <OFFSET> */
5435 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5437 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5438 /* Use the shorter form */
5440 x86_push_imm (code, 0);
5444 x86_push_imm (code, 0xf0f0f0f0);
5449 exc_classes [nthrows] = exc_class;
5450 exc_throw_start [nthrows] = code;
5453 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5454 patch_info->data.name = "mono_arch_throw_corlib_exception";
5455 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5456 patch_info->ip.i = code - cfg->native_code;
5457 x86_call_code (code, 0);
5458 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5463 exc_throw_end [nthrows] = code;
5475 cfg->code_len = code - cfg->native_code;
5477 g_assert (cfg->code_len < cfg->code_size);
5481 mono_arch_flush_icache (guint8 *code, gint size)
5487 mono_arch_flush_register_windows (void)
5492 mono_arch_is_inst_imm (gint64 imm)
5498 mono_arch_finish_init (void)
5500 char *mono_no_tls = g_getenv ("MONO_NO_TLS");
5502 #ifndef TARGET_WIN32
5504 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5508 g_free (mono_no_tls);
5513 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5517 // Linear handler, the bsearch head compare is shorter
5518 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5519 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5520 // x86_patch(ins,target)
5521 //[1 + 5] x86_jump_mem(inst,mem)
5524 #define BR_SMALL_SIZE 2
5525 #define BR_LARGE_SIZE 5
5526 #define JUMP_IMM_SIZE 6
5527 #define ENABLE_WRONG_METHOD_CHECK 0
5531 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5533 int i, distance = 0;
5534 for (i = start; i < target; ++i)
5535 distance += imt_entries [i]->chunk_size;
5540 * LOCKING: called with the domain lock held
5543 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5544 gpointer fail_tramp)
5548 guint8 *code, *start;
5551 for (i = 0; i < count; ++i) {
5552 MonoIMTCheckItem *item = imt_entries [i];
5553 if (item->is_equals) {
5554 if (item->check_target_idx) {
5555 if (!item->compare_done)
5556 item->chunk_size += CMP_SIZE;
5557 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5560 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5562 item->chunk_size += JUMP_IMM_SIZE;
5563 #if ENABLE_WRONG_METHOD_CHECK
5564 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5569 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5570 imt_entries [item->check_target_idx]->compare_done = TRUE;
5572 size += item->chunk_size;
5575 code = mono_method_alloc_generic_virtual_trampoline (domain, size);
5577 code = mono_domain_code_reserve (domain, size);
5580 unwind_ops = mono_arch_get_cie_program ();
5582 for (i = 0; i < count; ++i) {
5583 MonoIMTCheckItem *item = imt_entries [i];
5584 item->code_target = code;
5585 if (item->is_equals) {
5586 if (item->check_target_idx) {
5587 if (!item->compare_done)
5588 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5589 item->jmp_code = code;
5590 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5591 if (item->has_target_code)
5592 x86_jump_code (code, item->value.target_code);
5594 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5597 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5598 item->jmp_code = code;
5599 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5600 if (item->has_target_code)
5601 x86_jump_code (code, item->value.target_code);
5603 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5604 x86_patch (item->jmp_code, code);
5605 x86_jump_code (code, fail_tramp);
5606 item->jmp_code = NULL;
5608 /* enable the commented code to assert on wrong method */
5609 #if ENABLE_WRONG_METHOD_CHECK
5610 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5611 item->jmp_code = code;
5612 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5614 if (item->has_target_code)
5615 x86_jump_code (code, item->value.target_code);
5617 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5618 #if ENABLE_WRONG_METHOD_CHECK
5619 x86_patch (item->jmp_code, code);
5620 x86_breakpoint (code);
5621 item->jmp_code = NULL;
5626 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5627 item->jmp_code = code;
5628 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5629 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5631 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5634 /* patch the branches to get to the target items */
5635 for (i = 0; i < count; ++i) {
5636 MonoIMTCheckItem *item = imt_entries [i];
5637 if (item->jmp_code) {
5638 if (item->check_target_idx) {
5639 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5645 UnlockedAdd (&mono_stats.imt_trampolines_size, code - start);
5646 g_assert (code - start <= size);
5650 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5651 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5655 if (mono_jit_map_is_enabled ()) {
5658 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5660 buff = g_strdup_printf ("imt_trampoline_entries_%d", count);
5661 mono_emit_jit_tramp (start, code - start, buff);
5665 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL));
5667 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
5673 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5675 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5679 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5681 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5685 mono_arch_get_cie_program (void)
5689 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5690 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5696 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5698 MonoInst *ins = NULL;
5701 if (cmethod->klass == mono_defaults.math_class) {
5702 if (strcmp (cmethod->name, "Sin") == 0) {
5704 } else if (strcmp (cmethod->name, "Cos") == 0) {
5706 } else if (strcmp (cmethod->name, "Tan") == 0) {
5708 } else if (strcmp (cmethod->name, "Atan") == 0) {
5710 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5712 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5714 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5718 if (opcode && fsig->param_count == 1) {
5719 MONO_INST_NEW (cfg, ins, opcode);
5720 ins->type = STACK_R8;
5721 ins->dreg = mono_alloc_freg (cfg);
5722 ins->sreg1 = args [0]->dreg;
5723 MONO_ADD_INS (cfg->cbb, ins);
5726 if (cfg->opt & MONO_OPT_CMOV) {
5729 if (strcmp (cmethod->name, "Min") == 0) {
5730 if (fsig->params [0]->type == MONO_TYPE_I4)
5732 } else if (strcmp (cmethod->name, "Max") == 0) {
5733 if (fsig->params [0]->type == MONO_TYPE_I4)
5737 if (opcode && fsig->param_count == 2) {
5738 MONO_INST_NEW (cfg, ins, opcode);
5739 ins->type = STACK_I4;
5740 ins->dreg = mono_alloc_ireg (cfg);
5741 ins->sreg1 = args [0]->dreg;
5742 ins->sreg2 = args [1]->dreg;
5743 MONO_ADD_INS (cfg->cbb, ins);
5748 /* OP_FREM is not IEEE compatible */
5749 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
5750 MONO_INST_NEW (cfg, ins, OP_FREM);
5751 ins->inst_i0 = args [0];
5752 ins->inst_i1 = args [1];
5761 mono_arch_get_patch_offset (guint8 *code)
5763 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5765 else if (code [0] == 0xba)
5767 else if (code [0] == 0x68)
5770 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5771 /* push <OFFSET>(<REG>) */
5773 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5774 /* call *<OFFSET>(<REG>) */
5776 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5779 else if ((code [0] == 0x58) && (code [1] == 0x05))
5780 /* pop %eax; add <OFFSET>, %eax */
5782 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5783 /* pop <REG>; add <OFFSET>, <REG> */
5785 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5786 /* mov <REG>, imm */
5789 g_assert_not_reached ();
5795 * \return TRUE if no sw breakpoint was present.
5797 * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
5798 * breakpoints in the original code, they are removed in the copy.
5801 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5804 * If method_start is non-NULL we need to perform bound checks, since we access memory
5805 * at code - offset we could go before the start of the method and end up in a different
5806 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5809 if (!method_start || code - offset >= method_start) {
5810 memcpy (buf, code - offset, size);
5812 int diff = code - method_start;
5813 memset (buf, 0, size);
5814 memcpy (buf + offset - diff, method_start, diff + size - offset);
5820 * mono_x86_get_this_arg_offset:
5822 * Return the offset of the stack location where this is passed during a virtual
5826 mono_x86_get_this_arg_offset (MonoMethodSignature *sig)
5832 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
5834 guint32 esp = regs [X86_ESP];
5841 * The stack looks like:
5845 res = ((MonoObject**)esp) [0];
5849 #define MAX_ARCH_DELEGATE_PARAMS 10
5852 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
5854 guint8 *code, *start;
5855 int code_reserve = 64;
5858 unwind_ops = mono_arch_get_cie_program ();
5861 * The stack contains:
5867 start = code = mono_global_codeman_reserve (code_reserve);
5869 /* Replace the this argument with the target */
5870 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5871 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
5872 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5873 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
5875 g_assert ((code - start) < code_reserve);
5878 /* 8 for mov_reg and jump, plus 8 for each parameter */
5879 code_reserve = 8 + (param_count * 8);
5881 * The stack contains:
5882 * <args in reverse order>
5887 * <args in reverse order>
5890 * without unbalancing the stack.
5891 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
5892 * and leaving original spot of first arg as placeholder in stack so
5893 * when callee pops stack everything works.
5896 start = code = mono_global_codeman_reserve (code_reserve);
5898 /* store delegate for access to method_ptr */
5899 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
5902 for (i = 0; i < param_count; ++i) {
5903 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
5904 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
5907 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
5909 g_assert ((code - start) < code_reserve);
5913 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
5915 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
5916 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
5920 if (mono_jit_map_is_enabled ()) {
5923 buff = (char*)"delegate_invoke_has_target";
5925 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
5926 mono_emit_jit_tramp (start, code - start, buff);
5930 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
5935 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
5938 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
5940 guint8 *code, *start;
5945 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
5949 * The stack contains:
5953 start = code = mono_global_codeman_reserve (size);
5955 unwind_ops = mono_arch_get_cie_program ();
5957 /* Replace the this argument with the target */
5958 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5959 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
5960 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5963 /* Load the IMT reg */
5964 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
5967 /* Load the vtable */
5968 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
5969 x86_jump_membase (code, X86_EAX, offset);
5970 MONO_PROFILER_RAISE (jit_code_buffer, (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL));
5972 tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
5973 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
5974 g_free (tramp_name);
5981 mono_arch_get_delegate_invoke_impls (void)
5984 MonoTrampInfo *info;
5987 get_delegate_invoke_impl (&info, TRUE, 0);
5988 res = g_slist_prepend (res, info);
5990 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
5991 get_delegate_invoke_impl (&info, FALSE, i);
5992 res = g_slist_prepend (res, info);
5995 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
5996 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
5997 res = g_slist_prepend (res, info);
5999 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
6000 res = g_slist_prepend (res, info);
6007 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6009 guint8 *code, *start;
6011 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6014 /* FIXME: Support more cases */
6015 if (MONO_TYPE_ISSTRUCT (sig->ret))
6019 * The stack contains:
6025 static guint8* cached = NULL;
6029 if (mono_aot_only) {
6030 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6032 MonoTrampInfo *info;
6033 start = get_delegate_invoke_impl (&info, TRUE, 0);
6034 mono_tramp_info_register (info, NULL);
6037 mono_memory_barrier ();
6041 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6044 for (i = 0; i < sig->param_count; ++i)
6045 if (!mono_is_regsize_var (sig->params [i]))
6048 code = cache [sig->param_count];
6052 if (mono_aot_only) {
6053 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6054 start = mono_aot_get_trampoline (name);
6057 MonoTrampInfo *info;
6058 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
6059 mono_tramp_info_register (info, NULL);
6062 mono_memory_barrier ();
6064 cache [sig->param_count] = start;
6071 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
6073 MonoTrampInfo *info;
6076 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
6078 mono_tramp_info_register (info, NULL);
6083 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6086 case X86_EAX: return ctx->eax;
6087 case X86_EBX: return ctx->ebx;
6088 case X86_ECX: return ctx->ecx;
6089 case X86_EDX: return ctx->edx;
6090 case X86_ESP: return ctx->esp;
6091 case X86_EBP: return ctx->ebp;
6092 case X86_ESI: return ctx->esi;
6093 case X86_EDI: return ctx->edi;
6095 g_assert_not_reached ();
6101 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6129 g_assert_not_reached ();
6133 #ifdef MONO_ARCH_SIMD_INTRINSICS
6136 get_float_to_x_spill_area (MonoCompile *cfg)
6138 if (!cfg->fconv_to_r8_x_var) {
6139 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6140 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6142 return cfg->fconv_to_r8_x_var;
6146 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6149 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6152 int dreg, src_opcode;
6154 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6157 switch (src_opcode = ins->opcode) {
6158 case OP_FCONV_TO_I1:
6159 case OP_FCONV_TO_U1:
6160 case OP_FCONV_TO_I2:
6161 case OP_FCONV_TO_U2:
6162 case OP_FCONV_TO_I4:
6169 /* dreg is the IREG and sreg1 is the FREG */
6170 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6171 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6172 fconv->sreg1 = ins->sreg1;
6173 fconv->dreg = mono_alloc_ireg (cfg);
6174 fconv->type = STACK_VTYPE;
6175 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6177 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6181 ins->opcode = OP_XCONV_R8_TO_I4;
6183 ins->klass = mono_defaults.int32_class;
6184 ins->sreg1 = fconv->dreg;
6186 ins->type = STACK_I4;
6187 ins->backend.source_opcode = src_opcode;
6190 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6193 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6198 if (long_ins->opcode == OP_LNEG) {
6200 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
6201 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
6202 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->dreg));
6207 #ifdef MONO_ARCH_SIMD_INTRINSICS
6209 if (!(cfg->opt & MONO_OPT_SIMD))
6212 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6213 switch (long_ins->opcode) {
6215 vreg = long_ins->sreg1;
6217 if (long_ins->inst_c0) {
6218 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6219 ins->klass = long_ins->klass;
6220 ins->sreg1 = long_ins->sreg1;
6222 ins->type = STACK_VTYPE;
6223 ins->dreg = vreg = alloc_ireg (cfg);
6224 MONO_ADD_INS (cfg->cbb, ins);
6227 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6228 ins->klass = mono_defaults.int32_class;
6230 ins->type = STACK_I4;
6231 ins->dreg = MONO_LVREG_LS (long_ins->dreg);
6232 MONO_ADD_INS (cfg->cbb, ins);
6234 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6235 ins->klass = long_ins->klass;
6236 ins->sreg1 = long_ins->sreg1;
6237 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6238 ins->type = STACK_VTYPE;
6239 ins->dreg = vreg = alloc_ireg (cfg);
6240 MONO_ADD_INS (cfg->cbb, ins);
6242 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6243 ins->klass = mono_defaults.int32_class;
6245 ins->type = STACK_I4;
6246 ins->dreg = MONO_LVREG_MS (long_ins->dreg);
6247 MONO_ADD_INS (cfg->cbb, ins);
6249 long_ins->opcode = OP_NOP;
6251 case OP_INSERTX_I8_SLOW:
6252 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6253 ins->dreg = long_ins->dreg;
6254 ins->sreg1 = long_ins->dreg;
6255 ins->sreg2 = MONO_LVREG_LS (long_ins->sreg2);
6256 ins->inst_c0 = long_ins->inst_c0 * 2;
6257 MONO_ADD_INS (cfg->cbb, ins);
6259 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6260 ins->dreg = long_ins->dreg;
6261 ins->sreg1 = long_ins->dreg;
6262 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg2);
6263 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6264 MONO_ADD_INS (cfg->cbb, ins);
6266 long_ins->opcode = OP_NOP;
6269 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6270 ins->dreg = long_ins->dreg;
6271 ins->sreg1 = MONO_LVREG_LS (long_ins->sreg1);
6272 ins->klass = long_ins->klass;
6273 ins->type = STACK_VTYPE;
6274 MONO_ADD_INS (cfg->cbb, ins);
6276 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6277 ins->dreg = long_ins->dreg;
6278 ins->sreg1 = long_ins->dreg;
6279 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg1);
6281 ins->klass = long_ins->klass;
6282 ins->type = STACK_VTYPE;
6283 MONO_ADD_INS (cfg->cbb, ins);
6285 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6286 ins->dreg = long_ins->dreg;
6287 ins->sreg1 = long_ins->dreg;;
6288 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6289 ins->klass = long_ins->klass;
6290 ins->type = STACK_VTYPE;
6291 MONO_ADD_INS (cfg->cbb, ins);
6293 long_ins->opcode = OP_NOP;
6296 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6300 * mono_aot_emit_load_got_addr:
6302 * Emit code to load the got address.
6303 * On x86, the result is placed into EBX.
6306 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6308 x86_call_imm (code, 0);
6310 * The patch needs to point to the pop, since the GOT offset needs
6311 * to be added to that address.
6314 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6316 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6317 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6318 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6324 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6327 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6329 g_assert_not_reached ();
6330 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6335 * mono_arch_emit_load_aotconst:
6337 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6338 * TARGET from the mscorlib GOT in full-aot code.
6339 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6343 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
6345 /* Load the mscorlib got address */
6346 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6347 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6348 /* arch_emit_got_access () patches this */
6349 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6354 /* Can't put this into mini-x86.h */
6356 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6359 mono_arch_get_trampolines (gboolean aot)
6361 MonoTrampInfo *info;
6362 GSList *tramps = NULL;
6364 mono_x86_get_signal_exception_trampoline (&info, aot);
6366 tramps = g_slist_append (tramps, info);
6371 /* Soft Debug support */
6372 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6375 * mono_arch_set_breakpoint:
6377 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6378 * The location should contain code emitted by OP_SEQ_POINT.
6381 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6383 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6385 g_assert (code [0] == 0x90);
6386 x86_call_membase (code, X86_ECX, 0);
6390 * mono_arch_clear_breakpoint:
6392 * Clear the breakpoint at IP.
6395 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6397 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6400 for (i = 0; i < 2; ++i)
6405 * mono_arch_start_single_stepping:
6407 * Start single stepping.
6410 mono_arch_start_single_stepping (void)
6412 ss_trampoline = mini_get_single_step_trampoline ();
6416 * mono_arch_stop_single_stepping:
6418 * Stop single stepping.
6421 mono_arch_stop_single_stepping (void)
6423 ss_trampoline = NULL;
6427 * mono_arch_is_single_step_event:
6429 * Return whenever the machine state in SIGCTX corresponds to a single
6433 mono_arch_is_single_step_event (void *info, void *sigctx)
6435 /* We use soft breakpoints */
6440 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6442 /* We use soft breakpoints */
6446 #define BREAKPOINT_SIZE 2
6449 * mono_arch_skip_breakpoint:
6451 * See mini-amd64.c for docs.
6454 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6456 g_assert_not_reached ();
6460 * mono_arch_skip_single_step:
6462 * See mini-amd64.c for docs.
6465 mono_arch_skip_single_step (MonoContext *ctx)
6467 g_assert_not_reached ();
6471 * mono_arch_get_seq_point_info:
6473 * See mini-amd64.c for docs.
6476 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6483 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6485 ext->lmf.previous_lmf = (gsize)prev_lmf;
6486 /* Mark that this is a MonoLMFExt */
6487 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6488 ext->lmf.ebp = (gssize)ext;
6494 mono_arch_opcode_supported (int opcode)
6497 case OP_ATOMIC_ADD_I4:
6498 case OP_ATOMIC_EXCHANGE_I4:
6499 case OP_ATOMIC_CAS_I4:
6500 case OP_ATOMIC_LOAD_I1:
6501 case OP_ATOMIC_LOAD_I2:
6502 case OP_ATOMIC_LOAD_I4:
6503 case OP_ATOMIC_LOAD_U1:
6504 case OP_ATOMIC_LOAD_U2:
6505 case OP_ATOMIC_LOAD_U4:
6506 case OP_ATOMIC_LOAD_R4:
6507 case OP_ATOMIC_LOAD_R8:
6508 case OP_ATOMIC_STORE_I1:
6509 case OP_ATOMIC_STORE_I2:
6510 case OP_ATOMIC_STORE_I4:
6511 case OP_ATOMIC_STORE_U1:
6512 case OP_ATOMIC_STORE_U2:
6513 case OP_ATOMIC_STORE_U4:
6514 case OP_ATOMIC_STORE_R4:
6515 case OP_ATOMIC_STORE_R8:
6523 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
6525 return get_call_info (mp, sig);