2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/abi-details.h>
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/metadata/gc-internal.h>
27 #include <mono/utils/mono-math.h>
28 #include <mono/utils/mono-counters.h>
29 #include <mono/utils/mono-mmap.h>
30 #include <mono/utils/mono-memory-model.h>
31 #include <mono/utils/mono-hwcap-x86.h>
32 #include <mono/utils/mono-threads.h>
42 static gboolean optimize_for_xen = TRUE;
44 #define optimize_for_xen 0
48 /* The single step trampoline */
49 static gpointer ss_trampoline;
51 /* The breakpoint trampoline */
52 static gpointer bp_trampoline;
54 /* This mutex protects architecture specific caches */
55 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
56 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
57 static mono_mutex_t mini_arch_mutex;
59 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
64 /* Under windows, the default pinvoke calling convention is stdcall */
65 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
67 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
70 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
72 #define OP_SEQ_POINT_BP_OFFSET 7
75 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
77 #ifdef __native_client_codegen__
79 /* Default alignment for Native Client is 32-byte. */
80 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
82 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
83 /* Check that alignment doesn't cross an alignment boundary. */
85 mono_arch_nacl_pad (guint8 *code, int pad)
87 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
89 if (pad == 0) return code;
90 /* assertion: alignment cannot cross a block boundary */
91 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
92 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
93 while (pad >= kMaxPadding) {
94 x86_padding (code, kMaxPadding);
97 if (pad != 0) x86_padding (code, pad);
102 mono_arch_nacl_skip_nops (guint8 *code)
104 x86_skip_nops (code);
108 #endif /* __native_client_codegen__ */
111 mono_arch_regname (int reg)
114 case X86_EAX: return "%eax";
115 case X86_EBX: return "%ebx";
116 case X86_ECX: return "%ecx";
117 case X86_EDX: return "%edx";
118 case X86_ESP: return "%esp";
119 case X86_EBP: return "%ebp";
120 case X86_EDI: return "%edi";
121 case X86_ESI: return "%esi";
127 mono_arch_fregname (int reg)
152 mono_arch_xregname (int reg)
177 mono_x86_patch (unsigned char* code, gpointer target)
179 x86_patch (code, (unsigned char*)target);
190 /* gsharedvt argument passed by addr */
202 /* Only if storage == ArgValuetypeInReg */
203 ArgStorage pair_storage [2];
212 gboolean need_stack_align;
213 guint32 stack_align_amount;
214 gboolean vtype_retaddr;
215 /* The index of the vret arg in the argument list */
218 /* Argument space popped by the callee */
219 int callee_stack_pop;
225 #define FLOAT_PARAM_REGS 0
227 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
229 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
234 switch (sig->call_convention) {
235 case MONO_CALL_THISCALL:
236 return thiscall_param_regs;
242 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
243 #define SMALL_STRUCTS_IN_REGS
244 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
248 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
250 ainfo->offset = *stack_size;
252 if (!param_regs || param_regs [*gr] == X86_NREG) {
253 ainfo->storage = ArgOnStack;
255 (*stack_size) += sizeof (gpointer);
258 ainfo->storage = ArgInIReg;
259 ainfo->reg = param_regs [*gr];
265 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
267 ainfo->offset = *stack_size;
269 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
271 ainfo->storage = ArgOnStack;
272 (*stack_size) += sizeof (gpointer) * 2;
277 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
279 ainfo->offset = *stack_size;
281 if (*gr >= FLOAT_PARAM_REGS) {
282 ainfo->storage = ArgOnStack;
283 (*stack_size) += is_double ? 8 : 4;
284 ainfo->nslots = is_double ? 2 : 1;
287 /* A double register */
289 ainfo->storage = ArgInDoubleSSEReg;
291 ainfo->storage = ArgInFloatSSEReg;
299 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
301 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
306 klass = mono_class_from_mono_type (type);
307 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
309 #ifdef SMALL_STRUCTS_IN_REGS
310 if (sig->pinvoke && is_return) {
311 MonoMarshalType *info;
314 * the exact rules are not very well documented, the code below seems to work with the
315 * code generated by gcc 3.3.3 -mno-cygwin.
317 info = mono_marshal_load_type_info (klass);
320 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
322 /* Special case structs with only a float member */
323 if (info->num_fields == 1) {
324 int ftype = mini_get_underlying_type (info->fields [0].field->type)->type;
325 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
326 ainfo->storage = ArgValuetypeInReg;
327 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
330 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
331 ainfo->storage = ArgValuetypeInReg;
332 ainfo->pair_storage [0] = ArgOnFloatFpStack;
336 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
337 ainfo->storage = ArgValuetypeInReg;
338 ainfo->pair_storage [0] = ArgInIReg;
339 ainfo->pair_regs [0] = return_regs [0];
340 if (info->native_size > 4) {
341 ainfo->pair_storage [1] = ArgInIReg;
342 ainfo->pair_regs [1] = return_regs [1];
349 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
350 g_assert (size <= 4);
351 ainfo->storage = ArgValuetypeInReg;
352 ainfo->reg = param_regs [*gr];
357 ainfo->offset = *stack_size;
358 ainfo->storage = ArgOnStack;
359 *stack_size += ALIGN_TO (size, sizeof (gpointer));
360 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
366 * Obtain information about a call according to the calling convention.
367 * For x86 ELF, see the "System V Application Binary Interface Intel386
368 * Architecture Processor Supplment, Fourth Edition" document for more
370 * For x86 win32, see ???.
373 get_call_info_internal (CallInfo *cinfo, MonoMethodSignature *sig)
375 guint32 i, gr, fr, pstart;
376 const guint32 *param_regs;
378 int n = sig->hasthis + sig->param_count;
379 guint32 stack_size = 0;
380 gboolean is_pinvoke = sig->pinvoke;
386 param_regs = callconv_param_regs(sig);
390 ret_type = mini_get_underlying_type (sig->ret);
391 switch (ret_type->type) {
401 case MONO_TYPE_FNPTR:
402 case MONO_TYPE_CLASS:
403 case MONO_TYPE_OBJECT:
404 case MONO_TYPE_SZARRAY:
405 case MONO_TYPE_ARRAY:
406 case MONO_TYPE_STRING:
407 cinfo->ret.storage = ArgInIReg;
408 cinfo->ret.reg = X86_EAX;
412 cinfo->ret.storage = ArgInIReg;
413 cinfo->ret.reg = X86_EAX;
414 cinfo->ret.is_pair = TRUE;
417 cinfo->ret.storage = ArgOnFloatFpStack;
420 cinfo->ret.storage = ArgOnDoubleFpStack;
422 case MONO_TYPE_GENERICINST:
423 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
424 cinfo->ret.storage = ArgInIReg;
425 cinfo->ret.reg = X86_EAX;
428 if (mini_is_gsharedvt_type (ret_type)) {
429 cinfo->ret.storage = ArgOnStack;
430 cinfo->vtype_retaddr = TRUE;
434 case MONO_TYPE_VALUETYPE:
435 case MONO_TYPE_TYPEDBYREF: {
436 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
438 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
439 if (cinfo->ret.storage == ArgOnStack) {
440 cinfo->vtype_retaddr = TRUE;
441 /* The caller passes the address where the value is stored */
447 g_assert (mini_is_gsharedvt_type (ret_type));
448 cinfo->ret.storage = ArgOnStack;
449 cinfo->vtype_retaddr = TRUE;
452 cinfo->ret.storage = ArgNone;
455 g_error ("Can't handle as return value 0x%x", ret_type->type);
461 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
462 * the first argument, allowing 'this' to be always passed in the first arg reg.
463 * Also do this if the first argument is a reference type, since virtual calls
464 * are sometimes made using calli without sig->hasthis set, like in the delegate
467 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
469 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
471 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
474 cinfo->vret_arg_offset = stack_size;
475 add_general (&gr, NULL, &stack_size, &cinfo->ret);
476 cinfo->vret_arg_index = 1;
480 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
482 if (cinfo->vtype_retaddr)
483 add_general (&gr, NULL, &stack_size, &cinfo->ret);
486 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
487 fr = FLOAT_PARAM_REGS;
489 /* Emit the signature cookie just before the implicit arguments */
490 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
493 for (i = pstart; i < sig->param_count; ++i) {
494 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
497 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
498 /* We allways pass the sig cookie on the stack for simplicity */
500 * Prevent implicit arguments + the sig cookie from being passed
503 fr = FLOAT_PARAM_REGS;
505 /* Emit the signature cookie just before the implicit arguments */
506 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
509 if (sig->params [i]->byref) {
510 add_general (&gr, param_regs, &stack_size, ainfo);
513 ptype = mini_get_underlying_type (sig->params [i]);
514 switch (ptype->type) {
517 add_general (&gr, param_regs, &stack_size, ainfo);
521 add_general (&gr, param_regs, &stack_size, ainfo);
525 add_general (&gr, param_regs, &stack_size, ainfo);
530 case MONO_TYPE_FNPTR:
531 case MONO_TYPE_CLASS:
532 case MONO_TYPE_OBJECT:
533 case MONO_TYPE_STRING:
534 case MONO_TYPE_SZARRAY:
535 case MONO_TYPE_ARRAY:
536 add_general (&gr, param_regs, &stack_size, ainfo);
538 case MONO_TYPE_GENERICINST:
539 if (!mono_type_generic_inst_is_valuetype (ptype)) {
540 add_general (&gr, param_regs, &stack_size, ainfo);
543 if (mini_is_gsharedvt_type (ptype)) {
544 /* gsharedvt arguments are passed by ref */
545 add_general (&gr, param_regs, &stack_size, ainfo);
546 g_assert (ainfo->storage == ArgOnStack);
547 ainfo->storage = ArgGSharedVt;
551 case MONO_TYPE_VALUETYPE:
552 case MONO_TYPE_TYPEDBYREF:
553 add_valuetype (sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
557 add_general_pair (&gr, param_regs, &stack_size, ainfo);
560 add_float (&fr, &stack_size, ainfo, FALSE);
563 add_float (&fr, &stack_size, ainfo, TRUE);
567 /* gsharedvt arguments are passed by ref */
568 g_assert (mini_is_gsharedvt_type (ptype));
569 add_general (&gr, param_regs, &stack_size, ainfo);
570 g_assert (ainfo->storage == ArgOnStack);
571 ainfo->storage = ArgGSharedVt;
574 g_error ("unexpected type 0x%x", ptype->type);
575 g_assert_not_reached ();
579 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
580 fr = FLOAT_PARAM_REGS;
582 /* Emit the signature cookie just before the implicit arguments */
583 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
586 if (cinfo->vtype_retaddr) {
587 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
588 cinfo->callee_stack_pop = 4;
589 } else if (CALLCONV_IS_STDCALL (sig) && sig->pinvoke) {
590 /* Have to compensate for the stack space popped by the native callee */
591 cinfo->callee_stack_pop = stack_size;
594 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
595 cinfo->need_stack_align = TRUE;
596 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
597 stack_size += cinfo->stack_align_amount;
600 cinfo->stack_usage = stack_size;
601 cinfo->reg_usage = gr;
602 cinfo->freg_usage = fr;
607 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
609 int n = sig->hasthis + sig->param_count;
613 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
615 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
617 return get_call_info_internal (cinfo, sig);
621 * mono_arch_get_argument_info:
622 * @csig: a method signature
623 * @param_count: the number of parameters to consider
624 * @arg_info: an array to store the result infos
626 * Gathers information on parameters such as size, alignment and
627 * padding. arg_info should be large enought to hold param_count + 1 entries.
629 * Returns the size of the argument area on the stack.
630 * This should be signal safe, since it is called from
631 * mono_arch_unwind_frame ().
632 * FIXME: The metadata calls might not be signal safe.
635 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
637 int len, k, args_size = 0;
643 /* Avoid g_malloc as it is not signal safe */
644 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
645 cinfo = (CallInfo*)g_newa (guint8*, len);
646 memset (cinfo, 0, len);
648 cinfo = get_call_info_internal (cinfo, csig);
650 arg_info [0].offset = offset;
652 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
653 args_size += sizeof (gpointer);
658 args_size += sizeof (gpointer);
662 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
663 /* Emitted after this */
664 args_size += sizeof (gpointer);
668 arg_info [0].size = args_size;
670 for (k = 0; k < param_count; k++) {
671 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
673 /* ignore alignment for now */
676 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
677 arg_info [k].pad = pad;
679 arg_info [k + 1].pad = 0;
680 arg_info [k + 1].size = size;
682 arg_info [k + 1].offset = offset;
685 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
686 /* Emitted after the first arg */
687 args_size += sizeof (gpointer);
692 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
693 align = MONO_ARCH_FRAME_ALIGNMENT;
696 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
697 arg_info [k].pad = pad;
703 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
705 MonoType *callee_ret;
709 if (cfg->compile_aot && !cfg->full_aot)
710 /* OP_TAILCALL doesn't work with AOT */
713 c1 = get_call_info (NULL, caller_sig);
714 c2 = get_call_info (NULL, callee_sig);
716 * Tail calls with more callee stack usage than the caller cannot be supported, since
717 * the extra stack space would be left on the stack after the tail call.
719 res = c1->stack_usage >= c2->stack_usage;
720 callee_ret = mini_get_underlying_type (callee_sig->ret);
721 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
722 /* An address on the callee's stack is passed as the first argument */
732 * Initialize the cpu to execute managed code.
735 mono_arch_cpu_init (void)
737 /* spec compliance requires running with double precision */
741 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
742 fpcw &= ~X86_FPCW_PRECC_MASK;
743 fpcw |= X86_FPCW_PREC_DOUBLE;
744 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
745 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
747 _control87 (_PC_53, MCW_PC);
752 * Initialize architecture specific code.
755 mono_arch_init (void)
757 mono_mutex_init_recursive (&mini_arch_mutex);
760 bp_trampoline = mini_get_breakpoint_trampoline ();
762 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
763 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
764 #if defined(ENABLE_GSHAREDVT)
765 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
770 * Cleanup architecture specific code.
773 mono_arch_cleanup (void)
775 mono_mutex_destroy (&mini_arch_mutex);
779 * This function returns the optimizations supported on this cpu.
782 mono_arch_cpu_optimizations (guint32 *exclude_mask)
784 #if !defined(__native_client__)
789 if (mono_hwcap_x86_has_cmov) {
790 opts |= MONO_OPT_CMOV;
792 if (mono_hwcap_x86_has_fcmov)
793 opts |= MONO_OPT_FCMOV;
795 *exclude_mask |= MONO_OPT_FCMOV;
797 *exclude_mask |= MONO_OPT_CMOV;
800 if (mono_hwcap_x86_has_sse2)
801 opts |= MONO_OPT_SSE2;
803 *exclude_mask |= MONO_OPT_SSE2;
805 #ifdef MONO_ARCH_SIMD_INTRINSICS
806 /*SIMD intrinsics require at least SSE2.*/
807 if (!mono_hwcap_x86_has_sse2)
808 *exclude_mask |= MONO_OPT_SIMD;
813 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
818 * This function test for all SSE functions supported.
820 * Returns a bitmask corresponding to all supported versions.
824 mono_arch_cpu_enumerate_simd_versions (void)
826 guint32 sse_opts = 0;
828 if (mono_hwcap_x86_has_sse1)
829 sse_opts |= SIMD_VERSION_SSE1;
831 if (mono_hwcap_x86_has_sse2)
832 sse_opts |= SIMD_VERSION_SSE2;
834 if (mono_hwcap_x86_has_sse3)
835 sse_opts |= SIMD_VERSION_SSE3;
837 if (mono_hwcap_x86_has_ssse3)
838 sse_opts |= SIMD_VERSION_SSSE3;
840 if (mono_hwcap_x86_has_sse41)
841 sse_opts |= SIMD_VERSION_SSE41;
843 if (mono_hwcap_x86_has_sse42)
844 sse_opts |= SIMD_VERSION_SSE42;
846 if (mono_hwcap_x86_has_sse4a)
847 sse_opts |= SIMD_VERSION_SSE4a;
853 * Determine whenever the trap whose info is in SIGINFO is caused by
857 mono_arch_is_int_overflow (void *sigctx, void *info)
862 mono_sigctx_to_monoctx (sigctx, &ctx);
864 ip = (guint8*)ctx.eip;
866 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
870 switch (x86_modrm_rm (ip [1])) {
890 g_assert_not_reached ();
902 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
907 for (i = 0; i < cfg->num_varinfo; i++) {
908 MonoInst *ins = cfg->varinfo [i];
909 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
912 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
915 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
916 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
919 /* we dont allocate I1 to registers because there is no simply way to sign extend
920 * 8bit quantities in caller saved registers on x86 */
921 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
922 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
923 g_assert (i == vmv->idx);
924 vars = g_list_prepend (vars, vmv);
928 vars = mono_varlist_sort (cfg, vars, 0);
934 mono_arch_get_global_int_regs (MonoCompile *cfg)
938 /* we can use 3 registers for global allocation */
939 regs = g_list_prepend (regs, (gpointer)X86_EBX);
940 regs = g_list_prepend (regs, (gpointer)X86_ESI);
941 regs = g_list_prepend (regs, (gpointer)X86_EDI);
947 * mono_arch_regalloc_cost:
949 * Return the cost, in number of memory references, of the action of
950 * allocating the variable VMV into a register during global register
954 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
956 MonoInst *ins = cfg->varinfo [vmv->idx];
958 if (cfg->method->save_lmf)
959 /* The register is already saved */
960 return (ins->opcode == OP_ARG) ? 1 : 0;
962 /* push+pop+possible load if it is an argument */
963 return (ins->opcode == OP_ARG) ? 3 : 2;
967 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
969 static int inited = FALSE;
970 static int count = 0;
972 if (cfg->arch.need_stack_frame_inited) {
973 g_assert (cfg->arch.need_stack_frame == flag);
977 cfg->arch.need_stack_frame = flag;
978 cfg->arch.need_stack_frame_inited = TRUE;
984 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
989 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
993 needs_stack_frame (MonoCompile *cfg)
995 MonoMethodSignature *sig;
996 MonoMethodHeader *header;
997 gboolean result = FALSE;
999 #if defined(__APPLE__)
1000 /*OSX requires stack frame code to have the correct alignment. */
1004 if (cfg->arch.need_stack_frame_inited)
1005 return cfg->arch.need_stack_frame;
1007 header = cfg->header;
1008 sig = mono_method_signature (cfg->method);
1010 if (cfg->disable_omit_fp)
1012 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1014 else if (cfg->method->save_lmf)
1016 else if (cfg->stack_offset)
1018 else if (cfg->param_area)
1020 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1022 else if (header->num_clauses)
1024 else if (sig->param_count + sig->hasthis)
1026 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1028 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1029 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1032 set_needs_stack_frame (cfg, result);
1034 return cfg->arch.need_stack_frame;
1038 * Set var information according to the calling convention. X86 version.
1039 * The locals var stuff should most likely be split in another method.
1042 mono_arch_allocate_vars (MonoCompile *cfg)
1044 MonoMethodSignature *sig;
1045 MonoMethodHeader *header;
1047 guint32 locals_stack_size, locals_stack_align;
1052 header = cfg->header;
1053 sig = mono_method_signature (cfg->method);
1055 cinfo = get_call_info (cfg->mempool, sig);
1057 cfg->frame_reg = X86_EBP;
1060 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1061 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1062 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1065 /* Reserve space to save LMF and caller saved registers */
1067 if (cfg->method->save_lmf) {
1068 /* The LMF var is allocated normally */
1070 if (cfg->used_int_regs & (1 << X86_EBX)) {
1074 if (cfg->used_int_regs & (1 << X86_EDI)) {
1078 if (cfg->used_int_regs & (1 << X86_ESI)) {
1083 switch (cinfo->ret.storage) {
1084 case ArgValuetypeInReg:
1085 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1087 cfg->ret->opcode = OP_REGOFFSET;
1088 cfg->ret->inst_basereg = X86_EBP;
1089 cfg->ret->inst_offset = - offset;
1095 /* Allocate locals */
1096 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1097 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1098 char *mname = mono_method_full_name (cfg->method, TRUE);
1099 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1100 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1104 if (locals_stack_align) {
1105 int prev_offset = offset;
1107 offset += (locals_stack_align - 1);
1108 offset &= ~(locals_stack_align - 1);
1110 while (prev_offset < offset) {
1112 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1115 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1116 cfg->locals_max_stack_offset = - offset;
1118 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1119 * have locals larger than 8 bytes we need to make sure that
1120 * they have the appropriate offset.
1122 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1123 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1124 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1125 if (offsets [i] != -1) {
1126 MonoInst *inst = cfg->varinfo [i];
1127 inst->opcode = OP_REGOFFSET;
1128 inst->inst_basereg = X86_EBP;
1129 inst->inst_offset = - (offset + offsets [i]);
1130 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1133 offset += locals_stack_size;
1137 * Allocate arguments+return value
1140 switch (cinfo->ret.storage) {
1142 if (cfg->vret_addr) {
1144 * In the new IR, the cfg->vret_addr variable represents the
1145 * vtype return value.
1147 cfg->vret_addr->opcode = OP_REGOFFSET;
1148 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1149 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1150 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1151 printf ("vret_addr =");
1152 mono_print_ins (cfg->vret_addr);
1155 cfg->ret->opcode = OP_REGOFFSET;
1156 cfg->ret->inst_basereg = X86_EBP;
1157 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1160 case ArgValuetypeInReg:
1163 cfg->ret->opcode = OP_REGVAR;
1164 cfg->ret->inst_c0 = cinfo->ret.reg;
1165 cfg->ret->dreg = cinfo->ret.reg;
1168 case ArgOnFloatFpStack:
1169 case ArgOnDoubleFpStack:
1172 g_assert_not_reached ();
1175 if (sig->call_convention == MONO_CALL_VARARG) {
1176 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1177 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1180 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1181 ArgInfo *ainfo = &cinfo->args [i];
1182 inst = cfg->args [i];
1183 if (inst->opcode != OP_REGVAR) {
1184 inst->opcode = OP_REGOFFSET;
1185 inst->inst_basereg = X86_EBP;
1187 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1190 cfg->stack_offset = offset;
1194 mono_arch_create_vars (MonoCompile *cfg)
1197 MonoMethodSignature *sig;
1200 sig = mono_method_signature (cfg->method);
1202 cinfo = get_call_info (cfg->mempool, sig);
1203 sig_ret = mini_get_underlying_type (sig->ret);
1205 if (cinfo->ret.storage == ArgValuetypeInReg)
1206 cfg->ret_var_is_local = TRUE;
1207 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (sig_ret))) {
1208 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1211 if (cfg->gen_sdb_seq_points) {
1214 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1215 ins->flags |= MONO_INST_VOLATILE;
1216 cfg->arch.ss_tramp_var = ins;
1218 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1219 ins->flags |= MONO_INST_VOLATILE;
1220 cfg->arch.bp_tramp_var = ins;
1223 if (cfg->method->save_lmf) {
1224 cfg->create_lmf_var = TRUE;
1227 cfg->lmf_ir_mono_lmf = TRUE;
1231 cfg->arch_eh_jit_info = 1;
1235 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1236 * so we try to do it just once when we have multiple fp arguments in a row.
1237 * We don't use this mechanism generally because for int arguments the generated code
1238 * is slightly bigger and new generation cpus optimize away the dependency chains
1239 * created by push instructions on the esp value.
1240 * fp_arg_setup is the first argument in the execution sequence where the esp register
1243 static G_GNUC_UNUSED int
1244 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1249 for (; start_arg < sig->param_count; ++start_arg) {
1250 t = mini_get_underlying_type (sig->params [start_arg]);
1251 if (!t->byref && t->type == MONO_TYPE_R8) {
1252 fp_space += sizeof (double);
1253 *fp_arg_setup = start_arg;
1262 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1264 MonoMethodSignature *tmp_sig;
1268 * mono_ArgIterator_Setup assumes the signature cookie is
1269 * passed first and all the arguments which were before it are
1270 * passed on the stack after the signature. So compensate by
1271 * passing a different signature.
1273 tmp_sig = mono_metadata_signature_dup (call->signature);
1274 tmp_sig->param_count -= call->signature->sentinelpos;
1275 tmp_sig->sentinelpos = 0;
1276 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1278 if (cfg->compile_aot) {
1279 sig_reg = mono_alloc_ireg (cfg);
1280 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1281 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1283 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1289 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1294 LLVMCallInfo *linfo;
1295 MonoType *t, *sig_ret;
1297 n = sig->param_count + sig->hasthis;
1299 cinfo = get_call_info (cfg->mempool, sig);
1302 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1305 * LLVM always uses the native ABI while we use our own ABI, the
1306 * only difference is the handling of vtypes:
1307 * - we only pass/receive them in registers in some cases, and only
1308 * in 1 or 2 integer registers.
1310 if (cinfo->ret.storage == ArgValuetypeInReg) {
1312 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1313 cfg->disable_llvm = TRUE;
1317 cfg->exception_message = g_strdup ("vtype ret in call");
1318 cfg->disable_llvm = TRUE;
1320 linfo->ret.storage = LLVMArgVtypeInReg;
1321 for (j = 0; j < 2; ++j)
1322 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1326 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage == ArgInIReg) {
1327 /* Vtype returned using a hidden argument */
1328 linfo->ret.storage = LLVMArgVtypeRetAddr;
1329 linfo->vret_arg_index = cinfo->vret_arg_index;
1332 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage != ArgInIReg) {
1334 cfg->exception_message = g_strdup ("vtype ret in call");
1335 cfg->disable_llvm = TRUE;
1338 for (i = 0; i < n; ++i) {
1339 ainfo = cinfo->args + i;
1341 if (i >= sig->hasthis)
1342 t = sig->params [i - sig->hasthis];
1344 t = &mono_defaults.int_class->byval_arg;
1346 linfo->args [i].storage = LLVMArgNone;
1348 switch (ainfo->storage) {
1350 linfo->args [i].storage = LLVMArgNormal;
1352 case ArgInDoubleSSEReg:
1353 case ArgInFloatSSEReg:
1354 linfo->args [i].storage = LLVMArgNormal;
1357 if (mini_type_is_vtype (t)) {
1358 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1359 /* LLVM seems to allocate argument space for empty structures too */
1360 linfo->args [i].storage = LLVMArgNone;
1362 linfo->args [i].storage = LLVMArgVtypeByVal;
1364 linfo->args [i].storage = LLVMArgNormal;
1367 case ArgValuetypeInReg:
1369 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1370 cfg->disable_llvm = TRUE;
1374 cfg->exception_message = g_strdup ("vtype arg");
1375 cfg->disable_llvm = TRUE;
1377 linfo->args [i].storage = LLVMArgVtypeInReg;
1378 for (j = 0; j < 2; ++j)
1379 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1383 linfo->args [i].storage = LLVMArgGSharedVt;
1386 cfg->exception_message = g_strdup ("ainfo->storage");
1387 cfg->disable_llvm = TRUE;
1397 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1399 if (cfg->compute_gc_maps) {
1402 /* Needs checking if the feature will be enabled again */
1403 g_assert_not_reached ();
1405 /* On x86, the offsets are from the sp value before the start of the call sequence */
1407 t = &mono_defaults.int_class->byval_arg;
1408 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1413 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1417 MonoMethodSignature *sig;
1420 int sentinelpos = 0, sp_offset = 0;
1422 sig = call->signature;
1423 n = sig->param_count + sig->hasthis;
1424 sig_ret = mini_get_underlying_type (sig->ret);
1426 cinfo = get_call_info (cfg->mempool, sig);
1427 call->call_info = cinfo;
1429 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1430 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1432 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1433 if (cinfo->ret.storage == ArgValuetypeInReg) {
1435 * Tell the JIT to use a more efficient calling convention: call using
1436 * OP_CALL, compute the result location after the call, and save the
1439 call->vret_in_reg = TRUE;
1440 #if defined(__APPLE__)
1441 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1442 call->vret_in_reg_fp = TRUE;
1445 NULLIFY_INS (call->vret_var);
1449 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1451 /* Handle the case where there are no implicit arguments */
1452 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1453 emit_sig_cookie (cfg, call, cinfo);
1454 sp_offset = cinfo->sig_cookie.offset;
1455 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1458 /* Arguments are pushed in the reverse order */
1459 for (i = n - 1; i >= 0; i --) {
1460 ArgInfo *ainfo = cinfo->args + i;
1461 MonoType *orig_type, *t;
1464 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1467 /* Push the vret arg before the first argument */
1468 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1469 vtarg->type = STACK_MP;
1470 vtarg->inst_destbasereg = X86_ESP;
1471 vtarg->sreg1 = call->vret_var->dreg;
1472 vtarg->inst_offset = cinfo->ret.offset;
1473 MONO_ADD_INS (cfg->cbb, vtarg);
1474 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1477 if (i >= sig->hasthis)
1478 t = sig->params [i - sig->hasthis];
1480 t = &mono_defaults.int_class->byval_arg;
1482 t = mini_get_underlying_type (t);
1484 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1486 in = call->args [i];
1487 arg->cil_code = in->cil_code;
1488 arg->sreg1 = in->dreg;
1489 arg->type = in->type;
1491 g_assert (in->dreg != -1);
1493 if (ainfo->storage == ArgGSharedVt) {
1494 arg->opcode = OP_OUTARG_VT;
1495 arg->sreg1 = in->dreg;
1496 arg->klass = in->klass;
1497 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1498 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1500 MONO_ADD_INS (cfg->cbb, arg);
1501 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1505 g_assert (in->klass);
1507 if (t->type == MONO_TYPE_TYPEDBYREF) {
1508 size = sizeof (MonoTypedRef);
1509 align = sizeof (gpointer);
1512 size = mini_type_stack_size_full (&in->klass->byval_arg, &align, sig->pinvoke);
1516 arg->opcode = OP_OUTARG_VT;
1517 arg->sreg1 = in->dreg;
1518 arg->klass = in->klass;
1519 arg->backend.size = size;
1520 arg->inst_p0 = call;
1521 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1522 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1524 MONO_ADD_INS (cfg->cbb, arg);
1525 if (ainfo->storage != ArgValuetypeInReg) {
1526 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1530 switch (ainfo->storage) {
1533 if (t->type == MONO_TYPE_R4) {
1534 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1536 } else if (t->type == MONO_TYPE_R8) {
1537 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1539 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1540 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, in->dreg + 2);
1541 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg + 1);
1544 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1548 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1553 arg->opcode = OP_MOVE;
1554 arg->dreg = ainfo->reg;
1555 MONO_ADD_INS (cfg->cbb, arg);
1559 g_assert_not_reached ();
1562 if (cfg->compute_gc_maps) {
1564 /* FIXME: The == STACK_OBJ check might be fragile ? */
1565 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1567 if (call->need_unbox_trampoline)
1568 /* The unbox trampoline transforms this into a managed pointer */
1569 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.int_class->this_arg);
1571 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.object_class->byval_arg);
1573 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1577 for (j = 0; j < argsize; j += 4)
1578 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1583 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1584 /* Emit the signature cookie just before the implicit arguments */
1585 emit_sig_cookie (cfg, call, cinfo);
1586 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1590 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1593 if (cinfo->ret.storage == ArgValuetypeInReg) {
1596 else if (cinfo->ret.storage == ArgInIReg) {
1598 /* The return address is passed in a register */
1599 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1600 vtarg->sreg1 = call->inst.dreg;
1601 vtarg->dreg = mono_alloc_ireg (cfg);
1602 MONO_ADD_INS (cfg->cbb, vtarg);
1604 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1605 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1606 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1607 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1611 call->stack_usage = cinfo->stack_usage;
1612 call->stack_align_amount = cinfo->stack_align_amount;
1616 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1618 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1619 ArgInfo *ainfo = ins->inst_p1;
1620 int size = ins->backend.size;
1622 if (ainfo->storage == ArgValuetypeInReg) {
1623 int dreg = mono_alloc_ireg (cfg);
1626 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1629 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1632 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1636 g_assert_not_reached ();
1638 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1641 if (cfg->gsharedvt && mini_is_gsharedvt_klass (ins->klass)) {
1643 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1644 } else if (size <= 4) {
1645 int dreg = mono_alloc_ireg (cfg);
1646 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1647 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1648 } else if (size <= 20) {
1649 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1651 // FIXME: Code growth
1652 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1658 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1660 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
1663 if (ret->type == MONO_TYPE_R4) {
1664 if (COMPILE_LLVM (cfg))
1665 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1668 } else if (ret->type == MONO_TYPE_R8) {
1669 if (COMPILE_LLVM (cfg))
1670 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1673 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1674 if (COMPILE_LLVM (cfg))
1675 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1677 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1678 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1684 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1688 * Allow tracing to work with this interface (with an optional argument)
1691 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1695 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1696 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1698 /* if some args are passed in registers, we need to save them here */
1699 x86_push_reg (code, X86_EBP);
1701 if (cfg->compile_aot) {
1702 x86_push_imm (code, cfg->method);
1703 x86_mov_reg_imm (code, X86_EAX, func);
1704 x86_call_reg (code, X86_EAX);
1706 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1707 x86_push_imm (code, cfg->method);
1708 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1709 x86_call_code (code, 0);
1711 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1725 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1728 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1729 MonoMethod *method = cfg->method;
1730 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
1732 switch (ret_type->type) {
1733 case MONO_TYPE_VOID:
1734 /* special case string .ctor icall */
1735 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1736 save_mode = SAVE_EAX;
1737 stack_usage = enable_arguments ? 8 : 4;
1739 save_mode = SAVE_NONE;
1743 save_mode = SAVE_EAX_EDX;
1744 stack_usage = enable_arguments ? 16 : 8;
1748 save_mode = SAVE_FP;
1749 stack_usage = enable_arguments ? 16 : 8;
1751 case MONO_TYPE_GENERICINST:
1752 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1753 save_mode = SAVE_EAX;
1754 stack_usage = enable_arguments ? 8 : 4;
1758 case MONO_TYPE_VALUETYPE:
1759 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1760 save_mode = SAVE_STRUCT;
1761 stack_usage = enable_arguments ? 4 : 0;
1764 save_mode = SAVE_EAX;
1765 stack_usage = enable_arguments ? 8 : 4;
1769 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1771 switch (save_mode) {
1773 x86_push_reg (code, X86_EDX);
1774 x86_push_reg (code, X86_EAX);
1775 if (enable_arguments) {
1776 x86_push_reg (code, X86_EDX);
1777 x86_push_reg (code, X86_EAX);
1782 x86_push_reg (code, X86_EAX);
1783 if (enable_arguments) {
1784 x86_push_reg (code, X86_EAX);
1789 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1790 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1791 if (enable_arguments) {
1792 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1793 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1798 if (enable_arguments) {
1799 x86_push_membase (code, X86_EBP, 8);
1808 if (cfg->compile_aot) {
1809 x86_push_imm (code, method);
1810 x86_mov_reg_imm (code, X86_EAX, func);
1811 x86_call_reg (code, X86_EAX);
1813 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1814 x86_push_imm (code, method);
1815 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1816 x86_call_code (code, 0);
1819 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1821 switch (save_mode) {
1823 x86_pop_reg (code, X86_EAX);
1824 x86_pop_reg (code, X86_EDX);
1827 x86_pop_reg (code, X86_EAX);
1830 x86_fld_membase (code, X86_ESP, 0, TRUE);
1831 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1838 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1843 #define EMIT_COND_BRANCH(ins,cond,sign) \
1844 if (ins->inst_true_bb->native_offset) { \
1845 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1847 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1848 if ((cfg->opt & MONO_OPT_BRANCH) && \
1849 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1850 x86_branch8 (code, cond, 0, sign); \
1852 x86_branch32 (code, cond, 0, sign); \
1856 * Emit an exception if condition is fail and
1857 * if possible do a directly branch to target
1859 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1861 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1862 if (tins == NULL) { \
1863 mono_add_patch_info (cfg, code - cfg->native_code, \
1864 MONO_PATCH_INFO_EXC, exc_name); \
1865 x86_branch32 (code, cond, 0, signed); \
1867 EMIT_COND_BRANCH (tins, cond, signed); \
1871 #define EMIT_FPCOMPARE(code) do { \
1872 x86_fcompp (code); \
1873 x86_fnstsw (code); \
1878 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1880 gboolean needs_paddings = TRUE;
1882 MonoJumpInfo *jinfo = NULL;
1884 if (cfg->abs_patches) {
1885 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1886 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1887 needs_paddings = FALSE;
1890 if (cfg->compile_aot)
1891 needs_paddings = FALSE;
1892 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1893 This is required for code patching to be safe on SMP machines.
1895 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1896 #ifndef __native_client_codegen__
1897 if (needs_paddings && pad_size)
1898 x86_padding (code, 4 - pad_size);
1901 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1902 x86_call_code (code, 0);
1907 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1910 * mono_peephole_pass_1:
1912 * Perform peephole opts which should/can be performed before local regalloc
1915 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1919 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1920 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1922 switch (ins->opcode) {
1925 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1927 * X86_LEA is like ADD, but doesn't have the
1928 * sreg1==dreg restriction.
1930 ins->opcode = OP_X86_LEA_MEMBASE;
1931 ins->inst_basereg = ins->sreg1;
1932 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1933 ins->opcode = OP_X86_INC_REG;
1937 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1938 ins->opcode = OP_X86_LEA_MEMBASE;
1939 ins->inst_basereg = ins->sreg1;
1940 ins->inst_imm = -ins->inst_imm;
1941 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1942 ins->opcode = OP_X86_DEC_REG;
1944 case OP_COMPARE_IMM:
1945 case OP_ICOMPARE_IMM:
1946 /* OP_COMPARE_IMM (reg, 0)
1948 * OP_X86_TEST_NULL (reg)
1951 ins->opcode = OP_X86_TEST_NULL;
1953 case OP_X86_COMPARE_MEMBASE_IMM:
1955 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1956 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1958 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1959 * OP_COMPARE_IMM reg, imm
1961 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1963 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1964 ins->inst_basereg == last_ins->inst_destbasereg &&
1965 ins->inst_offset == last_ins->inst_offset) {
1966 ins->opcode = OP_COMPARE_IMM;
1967 ins->sreg1 = last_ins->sreg1;
1969 /* check if we can remove cmp reg,0 with test null */
1971 ins->opcode = OP_X86_TEST_NULL;
1975 case OP_X86_PUSH_MEMBASE:
1976 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1977 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1978 ins->inst_basereg == last_ins->inst_destbasereg &&
1979 ins->inst_offset == last_ins->inst_offset) {
1980 ins->opcode = OP_X86_PUSH;
1981 ins->sreg1 = last_ins->sreg1;
1986 mono_peephole_ins (bb, ins);
1991 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1995 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1996 switch (ins->opcode) {
1998 /* reg = 0 -> XOR (reg, reg) */
1999 /* XOR sets cflags on x86, so we cant do it always */
2000 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2003 ins->opcode = OP_IXOR;
2004 ins->sreg1 = ins->dreg;
2005 ins->sreg2 = ins->dreg;
2008 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2009 * since it takes 3 bytes instead of 7.
2011 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
2012 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2013 ins2->opcode = OP_STORE_MEMBASE_REG;
2014 ins2->sreg1 = ins->dreg;
2016 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2017 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2018 ins2->sreg1 = ins->dreg;
2020 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2021 /* Continue iteration */
2030 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2031 ins->opcode = OP_X86_INC_REG;
2035 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2036 ins->opcode = OP_X86_DEC_REG;
2040 mono_peephole_ins (bb, ins);
2045 * mono_arch_lowering_pass:
2047 * Converts complex opcodes into simpler ones so that each IR instruction
2048 * corresponds to one machine instruction.
2051 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2053 MonoInst *ins, *next;
2056 * FIXME: Need to add more instructions, but the current machine
2057 * description can't model some parts of the composite instructions like
2060 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2061 switch (ins->opcode) {
2064 case OP_IDIV_UN_IMM:
2065 case OP_IREM_UN_IMM:
2067 * Keep the cases where we could generated optimized code, otherwise convert
2068 * to the non-imm variant.
2070 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2072 mono_decompose_op_imm (cfg, bb, ins);
2079 bb->max_vreg = cfg->next_vreg;
2083 branch_cc_table [] = {
2084 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2085 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2086 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2089 /* Maps CMP_... constants to X86_CC_... constants */
2092 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2093 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2097 cc_signed_table [] = {
2098 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2099 FALSE, FALSE, FALSE, FALSE
2102 static unsigned char*
2103 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2105 #define XMM_TEMP_REG 0
2106 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2107 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2108 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2109 /* optimize by assigning a local var for this use so we avoid
2110 * the stack manipulations */
2111 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2112 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2113 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2114 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2115 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2117 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2119 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2122 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2123 x86_fnstcw_membase(code, X86_ESP, 0);
2124 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2125 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2126 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2127 x86_fldcw_membase (code, X86_ESP, 2);
2129 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2130 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2131 x86_pop_reg (code, dreg);
2132 /* FIXME: need the high register
2133 * x86_pop_reg (code, dreg_high);
2136 x86_push_reg (code, X86_EAX); // SP = SP - 4
2137 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2138 x86_pop_reg (code, dreg);
2140 x86_fldcw_membase (code, X86_ESP, 0);
2141 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2144 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2146 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2150 static unsigned char*
2151 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2153 int sreg = tree->sreg1;
2154 int need_touch = FALSE;
2156 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2165 * If requested stack size is larger than one page,
2166 * perform stack-touch operation
2169 * Generate stack probe code.
2170 * Under Windows, it is necessary to allocate one page at a time,
2171 * "touching" stack after each successful sub-allocation. This is
2172 * because of the way stack growth is implemented - there is a
2173 * guard page before the lowest stack page that is currently commited.
2174 * Stack normally grows sequentially so OS traps access to the
2175 * guard page and commits more pages when needed.
2177 x86_test_reg_imm (code, sreg, ~0xFFF);
2178 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2180 br[2] = code; /* loop */
2181 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2182 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2185 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2186 * that follows only initializes the last part of the area.
2188 /* Same as the init code below with size==0x1000 */
2189 if (tree->flags & MONO_INST_INIT) {
2190 x86_push_reg (code, X86_EAX);
2191 x86_push_reg (code, X86_ECX);
2192 x86_push_reg (code, X86_EDI);
2193 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2194 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2195 if (cfg->param_area)
2196 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2198 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2200 x86_prefix (code, X86_REP_PREFIX);
2202 x86_pop_reg (code, X86_EDI);
2203 x86_pop_reg (code, X86_ECX);
2204 x86_pop_reg (code, X86_EAX);
2207 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2208 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2209 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2210 x86_patch (br[3], br[2]);
2211 x86_test_reg_reg (code, sreg, sreg);
2212 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2213 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2215 br[1] = code; x86_jump8 (code, 0);
2217 x86_patch (br[0], code);
2218 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2219 x86_patch (br[1], code);
2220 x86_patch (br[4], code);
2223 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2225 if (tree->flags & MONO_INST_INIT) {
2227 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2228 x86_push_reg (code, X86_EAX);
2231 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2232 x86_push_reg (code, X86_ECX);
2235 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2236 x86_push_reg (code, X86_EDI);
2240 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2241 if (sreg != X86_ECX)
2242 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2243 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2245 if (cfg->param_area)
2246 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2248 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2250 x86_prefix (code, X86_REP_PREFIX);
2253 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2254 x86_pop_reg (code, X86_EDI);
2255 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2256 x86_pop_reg (code, X86_ECX);
2257 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2258 x86_pop_reg (code, X86_EAX);
2265 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2267 /* Move return value to the target register */
2268 switch (ins->opcode) {
2271 case OP_CALL_MEMBASE:
2272 if (ins->dreg != X86_EAX)
2273 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2283 static int tls_gs_offset;
2287 mono_x86_have_tls_get (void)
2290 static gboolean have_tls_get = FALSE;
2291 static gboolean inited = FALSE;
2294 return have_tls_get;
2296 #ifdef MONO_HAVE_FAST_TLS
2299 ins = (guint32*)pthread_getspecific;
2301 * We're looking for these two instructions:
2303 * mov 0x4(%esp),%eax
2304 * mov %gs:[offset](,%eax,4),%eax
2306 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2307 tls_gs_offset = ins [2];
2312 return have_tls_get;
2313 #elif defined(TARGET_ANDROID)
2321 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2323 #if defined(__APPLE__)
2324 x86_prefix (code, X86_GS_PREFIX);
2325 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2326 #elif defined(TARGET_WIN32)
2327 g_assert_not_reached ();
2329 x86_prefix (code, X86_GS_PREFIX);
2330 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2336 * mono_x86_emit_tls_get:
2337 * @code: buffer to store code to
2338 * @dreg: hard register where to place the result
2339 * @tls_offset: offset info
2341 * mono_x86_emit_tls_get emits in @code the native code that puts in
2342 * the dreg register the item in the thread local storage identified
2345 * Returns: a pointer to the end of the stored code
2348 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2350 #if defined(__APPLE__)
2351 x86_prefix (code, X86_GS_PREFIX);
2352 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2353 #elif defined(TARGET_WIN32)
2355 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2356 * Journal and/or a disassembly of the TlsGet () function.
2358 x86_prefix (code, X86_FS_PREFIX);
2359 x86_mov_reg_mem (code, dreg, 0x18, 4);
2360 if (tls_offset < 64) {
2361 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2365 g_assert (tls_offset < 0x440);
2366 /* Load TEB->TlsExpansionSlots */
2367 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2368 x86_test_reg_reg (code, dreg, dreg);
2370 x86_branch (code, X86_CC_EQ, code, TRUE);
2371 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2372 x86_patch (buf [0], code);
2375 if (optimize_for_xen) {
2376 x86_prefix (code, X86_GS_PREFIX);
2377 x86_mov_reg_mem (code, dreg, 0, 4);
2378 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2380 x86_prefix (code, X86_GS_PREFIX);
2381 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2388 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2390 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2391 #if defined(__APPLE__) || defined(__linux__)
2392 if (dreg != offset_reg)
2393 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2394 x86_prefix (code, X86_GS_PREFIX);
2395 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2397 g_assert_not_reached ();
2403 mono_x86_emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2405 return emit_tls_get_reg (code, dreg, offset_reg);
2409 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2411 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2413 g_assert_not_reached ();
2414 #elif defined(__APPLE__) || defined(__linux__)
2415 x86_prefix (code, X86_GS_PREFIX);
2416 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2418 g_assert_not_reached ();
2424 * mono_arch_translate_tls_offset:
2426 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2429 mono_arch_translate_tls_offset (int offset)
2432 return tls_gs_offset + (offset * 4);
2441 * Emit code to initialize an LMF structure at LMF_OFFSET.
2444 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2446 /* save all caller saved regs */
2447 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2448 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2449 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2450 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2451 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2452 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2453 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2455 /* save the current IP */
2456 if (cfg->compile_aot) {
2457 /* This pushes the current ip */
2458 x86_call_imm (code, 0);
2459 x86_pop_reg (code, X86_EAX);
2461 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2462 x86_mov_reg_imm (code, X86_EAX, 0);
2464 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2466 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2467 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2468 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2469 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2470 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2471 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2472 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2473 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2474 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2479 #define REAL_PRINT_REG(text,reg) \
2480 mono_assert (reg >= 0); \
2481 x86_push_reg (code, X86_EAX); \
2482 x86_push_reg (code, X86_EDX); \
2483 x86_push_reg (code, X86_ECX); \
2484 x86_push_reg (code, reg); \
2485 x86_push_imm (code, reg); \
2486 x86_push_imm (code, text " %d %p\n"); \
2487 x86_mov_reg_imm (code, X86_EAX, printf); \
2488 x86_call_reg (code, X86_EAX); \
2489 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2490 x86_pop_reg (code, X86_ECX); \
2491 x86_pop_reg (code, X86_EDX); \
2492 x86_pop_reg (code, X86_EAX);
2494 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2495 #ifdef __native__client_codegen__
2496 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2499 /* benchmark and set based on cpu */
2500 #define LOOP_ALIGNMENT 8
2501 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2505 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2510 guint8 *code = cfg->native_code + cfg->code_len;
2513 if (cfg->opt & MONO_OPT_LOOP) {
2514 int pad, align = LOOP_ALIGNMENT;
2515 /* set alignment depending on cpu */
2516 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2518 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2519 x86_padding (code, pad);
2520 cfg->code_len += pad;
2521 bb->native_offset = cfg->code_len;
2524 #ifdef __native_client_codegen__
2526 /* For Native Client, all indirect call/jump targets must be */
2527 /* 32-byte aligned. Exception handler blocks are jumped to */
2528 /* indirectly as well. */
2529 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2530 (bb->flags & BB_EXCEPTION_HANDLER);
2532 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2533 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2534 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2535 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2536 cfg->code_len += pad;
2537 bb->native_offset = cfg->code_len;
2540 #endif /* __native_client_codegen__ */
2541 if (cfg->verbose_level > 2)
2542 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2544 cpos = bb->max_offset;
2546 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
2547 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2548 g_assert (!cfg->compile_aot);
2551 cov->data [bb->dfn].cil_code = bb->cil_code;
2552 /* this is not thread save, but good enough */
2553 x86_inc_mem (code, &cov->data [bb->dfn].count);
2556 offset = code - cfg->native_code;
2558 mono_debug_open_block (cfg, bb, offset);
2560 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2561 x86_breakpoint (code);
2563 MONO_BB_FOR_EACH_INS (bb, ins) {
2564 offset = code - cfg->native_code;
2566 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2568 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2570 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2571 cfg->code_size *= 2;
2572 cfg->native_code = mono_realloc_native_code(cfg);
2573 code = cfg->native_code + offset;
2574 cfg->stat_code_reallocs++;
2577 if (cfg->debug_info)
2578 mono_debug_record_line_number (cfg, ins, offset);
2580 switch (ins->opcode) {
2582 x86_mul_reg (code, ins->sreg2, TRUE);
2585 x86_mul_reg (code, ins->sreg2, FALSE);
2587 case OP_X86_SETEQ_MEMBASE:
2588 case OP_X86_SETNE_MEMBASE:
2589 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2590 ins->inst_basereg, ins->inst_offset, TRUE);
2592 case OP_STOREI1_MEMBASE_IMM:
2593 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2595 case OP_STOREI2_MEMBASE_IMM:
2596 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2598 case OP_STORE_MEMBASE_IMM:
2599 case OP_STOREI4_MEMBASE_IMM:
2600 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2602 case OP_STOREI1_MEMBASE_REG:
2603 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2605 case OP_STOREI2_MEMBASE_REG:
2606 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2608 case OP_STORE_MEMBASE_REG:
2609 case OP_STOREI4_MEMBASE_REG:
2610 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2612 case OP_STORE_MEM_IMM:
2613 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2616 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2620 /* These are created by the cprop pass so they use inst_imm as the source */
2621 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2624 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2627 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2629 case OP_LOAD_MEMBASE:
2630 case OP_LOADI4_MEMBASE:
2631 case OP_LOADU4_MEMBASE:
2632 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2634 case OP_LOADU1_MEMBASE:
2635 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2637 case OP_LOADI1_MEMBASE:
2638 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2640 case OP_LOADU2_MEMBASE:
2641 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2643 case OP_LOADI2_MEMBASE:
2644 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2646 case OP_ICONV_TO_I1:
2648 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2650 case OP_ICONV_TO_I2:
2652 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2654 case OP_ICONV_TO_U1:
2655 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2657 case OP_ICONV_TO_U2:
2658 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2662 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2664 case OP_COMPARE_IMM:
2665 case OP_ICOMPARE_IMM:
2666 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2668 case OP_X86_COMPARE_MEMBASE_REG:
2669 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2671 case OP_X86_COMPARE_MEMBASE_IMM:
2672 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2674 case OP_X86_COMPARE_MEMBASE8_IMM:
2675 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2677 case OP_X86_COMPARE_REG_MEMBASE:
2678 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2680 case OP_X86_COMPARE_MEM_IMM:
2681 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2683 case OP_X86_TEST_NULL:
2684 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2686 case OP_X86_ADD_MEMBASE_IMM:
2687 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2689 case OP_X86_ADD_REG_MEMBASE:
2690 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2692 case OP_X86_SUB_MEMBASE_IMM:
2693 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2695 case OP_X86_SUB_REG_MEMBASE:
2696 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2698 case OP_X86_AND_MEMBASE_IMM:
2699 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2701 case OP_X86_OR_MEMBASE_IMM:
2702 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2704 case OP_X86_XOR_MEMBASE_IMM:
2705 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2707 case OP_X86_ADD_MEMBASE_REG:
2708 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2710 case OP_X86_SUB_MEMBASE_REG:
2711 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2713 case OP_X86_AND_MEMBASE_REG:
2714 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2716 case OP_X86_OR_MEMBASE_REG:
2717 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2719 case OP_X86_XOR_MEMBASE_REG:
2720 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2722 case OP_X86_INC_MEMBASE:
2723 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2725 case OP_X86_INC_REG:
2726 x86_inc_reg (code, ins->dreg);
2728 case OP_X86_DEC_MEMBASE:
2729 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2731 case OP_X86_DEC_REG:
2732 x86_dec_reg (code, ins->dreg);
2734 case OP_X86_MUL_REG_MEMBASE:
2735 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2737 case OP_X86_AND_REG_MEMBASE:
2738 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2740 case OP_X86_OR_REG_MEMBASE:
2741 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2743 case OP_X86_XOR_REG_MEMBASE:
2744 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2747 x86_breakpoint (code);
2749 case OP_RELAXED_NOP:
2750 x86_prefix (code, X86_REP_PREFIX);
2758 case OP_DUMMY_STORE:
2759 case OP_DUMMY_ICONST:
2760 case OP_DUMMY_R8CONST:
2761 case OP_NOT_REACHED:
2764 case OP_IL_SEQ_POINT:
2765 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2767 case OP_SEQ_POINT: {
2770 if (cfg->compile_aot)
2773 /* Have to use ecx as a temp reg since this can occur after OP_SETRET */
2776 * We do this _before_ the breakpoint, so single stepping after
2777 * a breakpoint is hit will step to the next IL offset.
2779 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
2780 MonoInst *var = cfg->arch.ss_tramp_var;
2784 g_assert (var->opcode == OP_REGOFFSET);
2785 /* Load ss_tramp_var */
2786 /* This is equal to &ss_trampoline */
2787 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, sizeof (mgreg_t));
2788 x86_alu_membase_imm (code, X86_CMP, X86_ECX, 0, 0);
2789 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2790 x86_call_membase (code, X86_ECX, 0);
2791 x86_patch (br [0], code);
2795 * Many parts of sdb depend on the ip after the single step trampoline call to be equal to the seq point offset.
2796 * This means we have to put the loading of bp_tramp_var after the offset.
2799 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2801 MonoInst *var = cfg->arch.bp_tramp_var;
2804 g_assert (var->opcode == OP_REGOFFSET);
2805 /* Load the address of the bp trampoline */
2806 /* This needs to be constant size */
2807 guint8 *start = code;
2808 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, 4);
2809 if (code < start + OP_SEQ_POINT_BP_OFFSET) {
2810 int size = start + OP_SEQ_POINT_BP_OFFSET - code;
2811 x86_padding (code, size);
2814 * A placeholder for a possible breakpoint inserted by
2815 * mono_arch_set_breakpoint ().
2817 for (i = 0; i < 2; ++i)
2820 * Add an additional nop so skipping the bp doesn't cause the ip to point
2821 * to another IL offset.
2829 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2833 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2838 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2842 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2847 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2851 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2856 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2860 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2863 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2867 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2871 #if defined( __native_client_codegen__ )
2872 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2873 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2876 * The code is the same for div/rem, the allocator will allocate dreg
2877 * to RAX/RDX as appropriate.
2879 if (ins->sreg2 == X86_EDX) {
2880 /* cdq clobbers this */
2881 x86_push_reg (code, ins->sreg2);
2883 x86_div_membase (code, X86_ESP, 0, TRUE);
2884 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2887 x86_div_reg (code, ins->sreg2, TRUE);
2892 #if defined( __native_client_codegen__ )
2893 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2894 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2896 if (ins->sreg2 == X86_EDX) {
2897 x86_push_reg (code, ins->sreg2);
2898 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2899 x86_div_membase (code, X86_ESP, 0, FALSE);
2900 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2902 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2903 x86_div_reg (code, ins->sreg2, FALSE);
2907 #if defined( __native_client_codegen__ )
2908 if (ins->inst_imm == 0) {
2909 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2910 x86_jump32 (code, 0);
2914 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2916 x86_div_reg (code, ins->sreg2, TRUE);
2919 int power = mono_is_power_of_two (ins->inst_imm);
2921 g_assert (ins->sreg1 == X86_EAX);
2922 g_assert (ins->dreg == X86_EAX);
2923 g_assert (power >= 0);
2926 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2928 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2930 * If the divident is >= 0, this does not nothing. If it is positive, it
2931 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2933 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2934 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2935 } else if (power == 0) {
2936 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2938 /* Based on gcc code */
2940 /* Add compensation for negative dividents */
2942 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2943 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2944 /* Compute remainder */
2945 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2946 /* Remove compensation */
2947 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2952 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2956 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2959 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2963 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2966 g_assert (ins->sreg2 == X86_ECX);
2967 x86_shift_reg (code, X86_SHL, ins->dreg);
2970 g_assert (ins->sreg2 == X86_ECX);
2971 x86_shift_reg (code, X86_SAR, ins->dreg);
2975 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2978 case OP_ISHR_UN_IMM:
2979 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2982 g_assert (ins->sreg2 == X86_ECX);
2983 x86_shift_reg (code, X86_SHR, ins->dreg);
2987 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2990 guint8 *jump_to_end;
2992 /* handle shifts below 32 bits */
2993 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2994 x86_shift_reg (code, X86_SHL, ins->sreg1);
2996 x86_test_reg_imm (code, X86_ECX, 32);
2997 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2999 /* handle shift over 32 bit */
3000 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3001 x86_clear_reg (code, ins->sreg1);
3003 x86_patch (jump_to_end, code);
3007 guint8 *jump_to_end;
3009 /* handle shifts below 32 bits */
3010 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3011 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
3013 x86_test_reg_imm (code, X86_ECX, 32);
3014 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3016 /* handle shifts over 31 bits */
3017 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3018 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
3020 x86_patch (jump_to_end, code);
3024 guint8 *jump_to_end;
3026 /* handle shifts below 32 bits */
3027 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3028 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
3030 x86_test_reg_imm (code, X86_ECX, 32);
3031 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3033 /* handle shifts over 31 bits */
3034 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3035 x86_clear_reg (code, ins->backend.reg3);
3037 x86_patch (jump_to_end, code);
3041 if (ins->inst_imm >= 32) {
3042 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3043 x86_clear_reg (code, ins->sreg1);
3044 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
3046 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
3047 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
3051 if (ins->inst_imm >= 32) {
3052 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3053 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
3054 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
3056 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3057 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3060 case OP_LSHR_UN_IMM:
3061 if (ins->inst_imm >= 32) {
3062 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3063 x86_clear_reg (code, ins->backend.reg3);
3064 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3066 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3067 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3071 x86_not_reg (code, ins->sreg1);
3074 x86_neg_reg (code, ins->sreg1);
3078 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3082 switch (ins->inst_imm) {
3086 if (ins->dreg != ins->sreg1)
3087 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3088 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3091 /* LEA r1, [r2 + r2*2] */
3092 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3095 /* LEA r1, [r2 + r2*4] */
3096 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3099 /* LEA r1, [r2 + r2*2] */
3101 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3102 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3105 /* LEA r1, [r2 + r2*8] */
3106 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3109 /* LEA r1, [r2 + r2*4] */
3111 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3112 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3115 /* LEA r1, [r2 + r2*2] */
3117 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3118 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3121 /* LEA r1, [r2 + r2*4] */
3122 /* LEA r1, [r1 + r1*4] */
3123 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3124 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3127 /* LEA r1, [r2 + r2*4] */
3129 /* LEA r1, [r1 + r1*4] */
3130 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3131 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3132 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3135 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3140 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3141 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3143 case OP_IMUL_OVF_UN: {
3144 /* the mul operation and the exception check should most likely be split */
3145 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3146 /*g_assert (ins->sreg2 == X86_EAX);
3147 g_assert (ins->dreg == X86_EAX);*/
3148 if (ins->sreg2 == X86_EAX) {
3149 non_eax_reg = ins->sreg1;
3150 } else if (ins->sreg1 == X86_EAX) {
3151 non_eax_reg = ins->sreg2;
3153 /* no need to save since we're going to store to it anyway */
3154 if (ins->dreg != X86_EAX) {
3156 x86_push_reg (code, X86_EAX);
3158 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3159 non_eax_reg = ins->sreg2;
3161 if (ins->dreg == X86_EDX) {
3164 x86_push_reg (code, X86_EAX);
3166 } else if (ins->dreg != X86_EAX) {
3168 x86_push_reg (code, X86_EDX);
3170 x86_mul_reg (code, non_eax_reg, FALSE);
3171 /* save before the check since pop and mov don't change the flags */
3172 if (ins->dreg != X86_EAX)
3173 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3175 x86_pop_reg (code, X86_EDX);
3177 x86_pop_reg (code, X86_EAX);
3178 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3182 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3185 g_assert_not_reached ();
3186 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3187 x86_mov_reg_imm (code, ins->dreg, 0);
3190 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3191 x86_mov_reg_imm (code, ins->dreg, 0);
3193 case OP_LOAD_GOTADDR:
3194 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3195 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3198 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3199 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3201 case OP_X86_PUSH_GOT_ENTRY:
3202 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3203 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3206 if (ins->dreg != ins->sreg1)
3207 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3210 MonoCallInst *call = (MonoCallInst*)ins;
3213 ins->flags |= MONO_INST_GC_CALLSITE;
3214 ins->backend.pc_offset = code - cfg->native_code;
3216 /* reset offset to make max_len work */
3217 offset = code - cfg->native_code;
3219 g_assert (!cfg->method->save_lmf);
3221 /* restore callee saved registers */
3222 for (i = 0; i < X86_NREG; ++i)
3223 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3225 if (cfg->used_int_regs & (1 << X86_ESI)) {
3226 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3229 if (cfg->used_int_regs & (1 << X86_EDI)) {
3230 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3233 if (cfg->used_int_regs & (1 << X86_EBX)) {
3234 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3238 /* Copy arguments on the stack to our argument area */
3239 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3240 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3241 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3244 /* restore ESP/EBP */
3246 offset = code - cfg->native_code;
3247 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3248 x86_jump32 (code, 0);
3250 ins->flags |= MONO_INST_GC_CALLSITE;
3251 cfg->disable_aot = TRUE;
3255 /* ensure ins->sreg1 is not NULL
3256 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3257 * cmp DWORD PTR [eax], 0
3259 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3262 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3263 x86_push_reg (code, hreg);
3264 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3265 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3266 x86_pop_reg (code, hreg);
3279 case OP_VOIDCALL_REG:
3281 case OP_FCALL_MEMBASE:
3282 case OP_LCALL_MEMBASE:
3283 case OP_VCALL_MEMBASE:
3284 case OP_VCALL2_MEMBASE:
3285 case OP_VOIDCALL_MEMBASE:
3286 case OP_CALL_MEMBASE: {
3289 call = (MonoCallInst*)ins;
3290 cinfo = (CallInfo*)call->call_info;
3292 switch (ins->opcode) {
3299 if (ins->flags & MONO_INST_HAS_METHOD)
3300 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3302 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3308 case OP_VOIDCALL_REG:
3310 x86_call_reg (code, ins->sreg1);
3312 case OP_FCALL_MEMBASE:
3313 case OP_LCALL_MEMBASE:
3314 case OP_VCALL_MEMBASE:
3315 case OP_VCALL2_MEMBASE:
3316 case OP_VOIDCALL_MEMBASE:
3317 case OP_CALL_MEMBASE:
3318 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3321 g_assert_not_reached ();
3324 ins->flags |= MONO_INST_GC_CALLSITE;
3325 ins->backend.pc_offset = code - cfg->native_code;
3326 if (cinfo->callee_stack_pop) {
3327 /* Have to compensate for the stack space popped by the callee */
3328 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3330 code = emit_move_return_value (cfg, ins, code);
3334 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3336 case OP_X86_LEA_MEMBASE:
3337 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3340 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3343 /* keep alignment */
3344 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3345 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3346 code = mono_emit_stack_alloc (cfg, code, ins);
3347 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3348 if (cfg->param_area)
3349 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3351 case OP_LOCALLOC_IMM: {
3352 guint32 size = ins->inst_imm;
3353 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3355 if (ins->flags & MONO_INST_INIT) {
3356 /* FIXME: Optimize this */
3357 x86_mov_reg_imm (code, ins->dreg, size);
3358 ins->sreg1 = ins->dreg;
3360 code = mono_emit_stack_alloc (cfg, code, ins);
3361 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3363 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3364 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3366 if (cfg->param_area)
3367 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3371 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3372 x86_push_reg (code, ins->sreg1);
3373 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3374 (gpointer)"mono_arch_throw_exception");
3375 ins->flags |= MONO_INST_GC_CALLSITE;
3376 ins->backend.pc_offset = code - cfg->native_code;
3380 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3381 x86_push_reg (code, ins->sreg1);
3382 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3383 (gpointer)"mono_arch_rethrow_exception");
3384 ins->flags |= MONO_INST_GC_CALLSITE;
3385 ins->backend.pc_offset = code - cfg->native_code;
3388 case OP_CALL_HANDLER:
3389 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3390 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3391 x86_call_imm (code, 0);
3392 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3393 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3395 case OP_START_HANDLER: {
3396 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3397 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3398 if (cfg->param_area)
3399 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3402 case OP_ENDFINALLY: {
3403 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3404 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3408 case OP_ENDFILTER: {
3409 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3410 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3411 /* The local allocator will put the result into EAX */
3416 if (ins->dreg != X86_EAX)
3417 x86_mov_reg_reg (code, ins->dreg, X86_EAX, sizeof (gpointer));
3421 ins->inst_c0 = code - cfg->native_code;
3424 if (ins->inst_target_bb->native_offset) {
3425 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3427 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3428 if ((cfg->opt & MONO_OPT_BRANCH) &&
3429 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3430 x86_jump8 (code, 0);
3432 x86_jump32 (code, 0);
3436 x86_jump_reg (code, ins->sreg1);
3455 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3456 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3458 case OP_COND_EXC_EQ:
3459 case OP_COND_EXC_NE_UN:
3460 case OP_COND_EXC_LT:
3461 case OP_COND_EXC_LT_UN:
3462 case OP_COND_EXC_GT:
3463 case OP_COND_EXC_GT_UN:
3464 case OP_COND_EXC_GE:
3465 case OP_COND_EXC_GE_UN:
3466 case OP_COND_EXC_LE:
3467 case OP_COND_EXC_LE_UN:
3468 case OP_COND_EXC_IEQ:
3469 case OP_COND_EXC_INE_UN:
3470 case OP_COND_EXC_ILT:
3471 case OP_COND_EXC_ILT_UN:
3472 case OP_COND_EXC_IGT:
3473 case OP_COND_EXC_IGT_UN:
3474 case OP_COND_EXC_IGE:
3475 case OP_COND_EXC_IGE_UN:
3476 case OP_COND_EXC_ILE:
3477 case OP_COND_EXC_ILE_UN:
3478 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3480 case OP_COND_EXC_OV:
3481 case OP_COND_EXC_NO:
3483 case OP_COND_EXC_NC:
3484 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3486 case OP_COND_EXC_IOV:
3487 case OP_COND_EXC_INO:
3488 case OP_COND_EXC_IC:
3489 case OP_COND_EXC_INC:
3490 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3502 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3510 case OP_CMOV_INE_UN:
3511 case OP_CMOV_IGE_UN:
3512 case OP_CMOV_IGT_UN:
3513 case OP_CMOV_ILE_UN:
3514 case OP_CMOV_ILT_UN:
3515 g_assert (ins->dreg == ins->sreg1);
3516 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3519 /* floating point opcodes */
3521 double d = *(double *)ins->inst_p0;
3523 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3525 } else if (d == 1.0) {
3528 if (cfg->compile_aot) {
3529 guint32 *val = (guint32*)&d;
3530 x86_push_imm (code, val [1]);
3531 x86_push_imm (code, val [0]);
3532 x86_fld_membase (code, X86_ESP, 0, TRUE);
3533 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3536 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3537 x86_fld (code, NULL, TRUE);
3543 float f = *(float *)ins->inst_p0;
3545 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3547 } else if (f == 1.0) {
3550 if (cfg->compile_aot) {
3551 guint32 val = *(guint32*)&f;
3552 x86_push_imm (code, val);
3553 x86_fld_membase (code, X86_ESP, 0, FALSE);
3554 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3557 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3558 x86_fld (code, NULL, FALSE);
3563 case OP_STORER8_MEMBASE_REG:
3564 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3566 case OP_LOADR8_MEMBASE:
3567 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3569 case OP_STORER4_MEMBASE_REG:
3570 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3572 case OP_LOADR4_MEMBASE:
3573 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3575 case OP_ICONV_TO_R4:
3576 x86_push_reg (code, ins->sreg1);
3577 x86_fild_membase (code, X86_ESP, 0, FALSE);
3578 /* Change precision */
3579 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3580 x86_fld_membase (code, X86_ESP, 0, FALSE);
3581 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3583 case OP_ICONV_TO_R8:
3584 x86_push_reg (code, ins->sreg1);
3585 x86_fild_membase (code, X86_ESP, 0, FALSE);
3586 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3588 case OP_ICONV_TO_R_UN:
3589 x86_push_imm (code, 0);
3590 x86_push_reg (code, ins->sreg1);
3591 x86_fild_membase (code, X86_ESP, 0, TRUE);
3592 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3594 case OP_X86_FP_LOAD_I8:
3595 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3597 case OP_X86_FP_LOAD_I4:
3598 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3600 case OP_FCONV_TO_R4:
3601 /* Change precision */
3602 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3603 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3604 x86_fld_membase (code, X86_ESP, 0, FALSE);
3605 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3607 case OP_FCONV_TO_I1:
3608 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3610 case OP_FCONV_TO_U1:
3611 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3613 case OP_FCONV_TO_I2:
3614 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3616 case OP_FCONV_TO_U2:
3617 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3619 case OP_FCONV_TO_I4:
3621 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3623 case OP_FCONV_TO_I8:
3624 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3625 x86_fnstcw_membase(code, X86_ESP, 0);
3626 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3627 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3628 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3629 x86_fldcw_membase (code, X86_ESP, 2);
3630 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3631 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3632 x86_pop_reg (code, ins->dreg);
3633 x86_pop_reg (code, ins->backend.reg3);
3634 x86_fldcw_membase (code, X86_ESP, 0);
3635 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3637 case OP_LCONV_TO_R8_2:
3638 x86_push_reg (code, ins->sreg2);
3639 x86_push_reg (code, ins->sreg1);
3640 x86_fild_membase (code, X86_ESP, 0, TRUE);
3641 /* Change precision */
3642 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3643 x86_fld_membase (code, X86_ESP, 0, TRUE);
3644 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3646 case OP_LCONV_TO_R4_2:
3647 x86_push_reg (code, ins->sreg2);
3648 x86_push_reg (code, ins->sreg1);
3649 x86_fild_membase (code, X86_ESP, 0, TRUE);
3650 /* Change precision */
3651 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3652 x86_fld_membase (code, X86_ESP, 0, FALSE);
3653 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3655 case OP_LCONV_TO_R_UN_2: {
3656 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3659 /* load 64bit integer to FP stack */
3660 x86_push_reg (code, ins->sreg2);
3661 x86_push_reg (code, ins->sreg1);
3662 x86_fild_membase (code, X86_ESP, 0, TRUE);
3664 /* test if lreg is negative */
3665 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3666 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3668 /* add correction constant mn */
3669 if (cfg->compile_aot) {
3670 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3671 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3672 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3673 x86_fld80_membase (code, X86_ESP, 2);
3674 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3676 x86_fld80_mem (code, mn);
3678 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3680 x86_patch (br, code);
3682 /* Change precision */
3683 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3684 x86_fld_membase (code, X86_ESP, 0, TRUE);
3686 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3690 case OP_LCONV_TO_OVF_I:
3691 case OP_LCONV_TO_OVF_I4_2: {
3692 guint8 *br [3], *label [1];
3696 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3698 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3700 /* If the low word top bit is set, see if we are negative */
3701 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3702 /* We are not negative (no top bit set, check for our top word to be zero */
3703 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3704 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3707 /* throw exception */
3708 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3710 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3711 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3712 x86_jump8 (code, 0);
3714 x86_jump32 (code, 0);
3716 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3717 x86_jump32 (code, 0);
3721 x86_patch (br [0], code);
3722 /* our top bit is set, check that top word is 0xfffffff */
3723 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3725 x86_patch (br [1], code);
3726 /* nope, emit exception */
3727 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3728 x86_patch (br [2], label [0]);
3730 if (ins->dreg != ins->sreg1)
3731 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3735 /* Not needed on the fp stack */
3737 case OP_MOVE_F_TO_I4:
3738 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
3739 x86_mov_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, 4);
3741 case OP_MOVE_I4_TO_F:
3742 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
3743 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
3746 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3749 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3752 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3755 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3763 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3768 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3775 * it really doesn't make sense to inline all this code,
3776 * it's here just to show that things may not be as simple
3779 guchar *check_pos, *end_tan, *pop_jump;
3780 x86_push_reg (code, X86_EAX);
3783 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3785 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3786 x86_fstp (code, 0); /* pop the 1.0 */
3788 x86_jump8 (code, 0);
3790 x86_fp_op (code, X86_FADD, 0);
3794 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3796 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3799 x86_patch (pop_jump, code);
3800 x86_fstp (code, 0); /* pop the 1.0 */
3801 x86_patch (check_pos, code);
3802 x86_patch (end_tan, code);
3804 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3805 x86_pop_reg (code, X86_EAX);
3812 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3821 g_assert (cfg->opt & MONO_OPT_CMOV);
3822 g_assert (ins->dreg == ins->sreg1);
3823 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3824 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3827 g_assert (cfg->opt & MONO_OPT_CMOV);
3828 g_assert (ins->dreg == ins->sreg1);
3829 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3830 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3833 g_assert (cfg->opt & MONO_OPT_CMOV);
3834 g_assert (ins->dreg == ins->sreg1);
3835 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3836 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3839 g_assert (cfg->opt & MONO_OPT_CMOV);
3840 g_assert (ins->dreg == ins->sreg1);
3841 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3842 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3848 x86_fxch (code, ins->inst_imm);
3853 x86_push_reg (code, X86_EAX);
3854 /* we need to exchange ST(0) with ST(1) */
3857 /* this requires a loop, because fprem somtimes
3858 * returns a partial remainder */
3860 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3861 /* x86_fprem1 (code); */
3864 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3866 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3872 x86_pop_reg (code, X86_EAX);
3876 if (cfg->opt & MONO_OPT_FCMOV) {
3877 x86_fcomip (code, 1);
3881 /* this overwrites EAX */
3882 EMIT_FPCOMPARE(code);
3883 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3887 if (cfg->opt & MONO_OPT_FCMOV) {
3888 /* zeroing the register at the start results in
3889 * shorter and faster code (we can also remove the widening op)
3891 guchar *unordered_check;
3892 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3893 x86_fcomip (code, 1);
3895 unordered_check = code;
3896 x86_branch8 (code, X86_CC_P, 0, FALSE);
3897 if (ins->opcode == OP_FCEQ) {
3898 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3899 x86_patch (unordered_check, code);
3901 guchar *jump_to_end;
3902 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3904 x86_jump8 (code, 0);
3905 x86_patch (unordered_check, code);
3906 x86_inc_reg (code, ins->dreg);
3907 x86_patch (jump_to_end, code);
3912 if (ins->dreg != X86_EAX)
3913 x86_push_reg (code, X86_EAX);
3915 EMIT_FPCOMPARE(code);
3916 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3917 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3918 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3919 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3921 if (ins->dreg != X86_EAX)
3922 x86_pop_reg (code, X86_EAX);
3926 if (cfg->opt & MONO_OPT_FCMOV) {
3927 /* zeroing the register at the start results in
3928 * shorter and faster code (we can also remove the widening op)
3930 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3931 x86_fcomip (code, 1);
3933 if (ins->opcode == OP_FCLT_UN) {
3934 guchar *unordered_check = code;
3935 guchar *jump_to_end;
3936 x86_branch8 (code, X86_CC_P, 0, FALSE);
3937 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3939 x86_jump8 (code, 0);
3940 x86_patch (unordered_check, code);
3941 x86_inc_reg (code, ins->dreg);
3942 x86_patch (jump_to_end, code);
3944 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3948 if (ins->dreg != X86_EAX)
3949 x86_push_reg (code, X86_EAX);
3951 EMIT_FPCOMPARE(code);
3952 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3953 if (ins->opcode == OP_FCLT_UN) {
3954 guchar *is_not_zero_check, *end_jump;
3955 is_not_zero_check = code;
3956 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3958 x86_jump8 (code, 0);
3959 x86_patch (is_not_zero_check, code);
3960 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3962 x86_patch (end_jump, code);
3964 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3965 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3967 if (ins->dreg != X86_EAX)
3968 x86_pop_reg (code, X86_EAX);
3971 guchar *unordered_check;
3972 guchar *jump_to_end;
3973 if (cfg->opt & MONO_OPT_FCMOV) {
3974 /* zeroing the register at the start results in
3975 * shorter and faster code (we can also remove the widening op)
3977 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3978 x86_fcomip (code, 1);
3980 unordered_check = code;
3981 x86_branch8 (code, X86_CC_P, 0, FALSE);
3982 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3983 x86_patch (unordered_check, code);
3986 if (ins->dreg != X86_EAX)
3987 x86_push_reg (code, X86_EAX);
3989 EMIT_FPCOMPARE(code);
3990 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3991 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3992 unordered_check = code;
3993 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3995 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3996 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3997 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3999 x86_jump8 (code, 0);
4000 x86_patch (unordered_check, code);
4001 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4002 x86_patch (jump_to_end, code);
4004 if (ins->dreg != X86_EAX)
4005 x86_pop_reg (code, X86_EAX);
4010 if (cfg->opt & MONO_OPT_FCMOV) {
4011 /* zeroing the register at the start results in
4012 * shorter and faster code (we can also remove the widening op)
4014 guchar *unordered_check;
4015 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4016 x86_fcomip (code, 1);
4018 if (ins->opcode == OP_FCGT) {
4019 unordered_check = code;
4020 x86_branch8 (code, X86_CC_P, 0, FALSE);
4021 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4022 x86_patch (unordered_check, code);
4024 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4028 if (ins->dreg != X86_EAX)
4029 x86_push_reg (code, X86_EAX);
4031 EMIT_FPCOMPARE(code);
4032 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4033 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4034 if (ins->opcode == OP_FCGT_UN) {
4035 guchar *is_not_zero_check, *end_jump;
4036 is_not_zero_check = code;
4037 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4039 x86_jump8 (code, 0);
4040 x86_patch (is_not_zero_check, code);
4041 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4043 x86_patch (end_jump, code);
4045 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4046 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4048 if (ins->dreg != X86_EAX)
4049 x86_pop_reg (code, X86_EAX);
4052 guchar *unordered_check;
4053 guchar *jump_to_end;
4054 if (cfg->opt & MONO_OPT_FCMOV) {
4055 /* zeroing the register at the start results in
4056 * shorter and faster code (we can also remove the widening op)
4058 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4059 x86_fcomip (code, 1);
4061 unordered_check = code;
4062 x86_branch8 (code, X86_CC_P, 0, FALSE);
4063 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4064 x86_patch (unordered_check, code);
4067 if (ins->dreg != X86_EAX)
4068 x86_push_reg (code, X86_EAX);
4070 EMIT_FPCOMPARE(code);
4071 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4072 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4073 unordered_check = code;
4074 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4076 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4077 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4078 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4080 x86_jump8 (code, 0);
4081 x86_patch (unordered_check, code);
4082 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4083 x86_patch (jump_to_end, code);
4085 if (ins->dreg != X86_EAX)
4086 x86_pop_reg (code, X86_EAX);
4090 if (cfg->opt & MONO_OPT_FCMOV) {
4091 guchar *jump = code;
4092 x86_branch8 (code, X86_CC_P, 0, TRUE);
4093 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4094 x86_patch (jump, code);
4097 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4098 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4101 /* Branch if C013 != 100 */
4102 if (cfg->opt & MONO_OPT_FCMOV) {
4103 /* branch if !ZF or (PF|CF) */
4104 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4105 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4106 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4109 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4110 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4113 if (cfg->opt & MONO_OPT_FCMOV) {
4114 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4117 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4120 if (cfg->opt & MONO_OPT_FCMOV) {
4121 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4122 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4125 if (ins->opcode == OP_FBLT_UN) {
4126 guchar *is_not_zero_check, *end_jump;
4127 is_not_zero_check = code;
4128 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4130 x86_jump8 (code, 0);
4131 x86_patch (is_not_zero_check, code);
4132 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4134 x86_patch (end_jump, code);
4136 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4140 if (cfg->opt & MONO_OPT_FCMOV) {
4141 if (ins->opcode == OP_FBGT) {
4144 /* skip branch if C1=1 */
4146 x86_branch8 (code, X86_CC_P, 0, FALSE);
4147 /* branch if (C0 | C3) = 1 */
4148 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4149 x86_patch (br1, code);
4151 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4155 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4156 if (ins->opcode == OP_FBGT_UN) {
4157 guchar *is_not_zero_check, *end_jump;
4158 is_not_zero_check = code;
4159 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4161 x86_jump8 (code, 0);
4162 x86_patch (is_not_zero_check, code);
4163 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4165 x86_patch (end_jump, code);
4167 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4170 /* Branch if C013 == 100 or 001 */
4171 if (cfg->opt & MONO_OPT_FCMOV) {
4174 /* skip branch if C1=1 */
4176 x86_branch8 (code, X86_CC_P, 0, FALSE);
4177 /* branch if (C0 | C3) = 1 */
4178 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4179 x86_patch (br1, code);
4182 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4183 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4184 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4185 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4188 /* Branch if C013 == 000 */
4189 if (cfg->opt & MONO_OPT_FCMOV) {
4190 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4193 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4196 /* Branch if C013=000 or 100 */
4197 if (cfg->opt & MONO_OPT_FCMOV) {
4200 /* skip branch if C1=1 */
4202 x86_branch8 (code, X86_CC_P, 0, FALSE);
4203 /* branch if C0=0 */
4204 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4205 x86_patch (br1, code);
4208 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4209 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4210 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4213 /* Branch if C013 != 001 */
4214 if (cfg->opt & MONO_OPT_FCMOV) {
4215 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4216 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4219 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4220 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4224 x86_push_reg (code, X86_EAX);
4227 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4228 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4229 x86_pop_reg (code, X86_EAX);
4231 /* Have to clean up the fp stack before throwing the exception */
4233 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4236 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4238 x86_patch (br1, code);
4242 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4245 case OP_TLS_GET_REG: {
4246 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4250 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4253 case OP_TLS_SET_REG: {
4254 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4257 case OP_MEMORY_BARRIER: {
4258 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4259 x86_prefix (code, X86_LOCK_PREFIX);
4260 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4264 case OP_ATOMIC_ADD_I4: {
4265 int dreg = ins->dreg;
4267 g_assert (cfg->has_atomic_add_i4);
4269 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4270 if (ins->sreg2 == dreg) {
4271 if (dreg == X86_EBX) {
4273 if (ins->inst_basereg == X86_EDI)
4277 if (ins->inst_basereg == X86_EBX)
4280 } else if (ins->inst_basereg == dreg) {
4281 if (dreg == X86_EBX) {
4283 if (ins->sreg2 == X86_EDI)
4287 if (ins->sreg2 == X86_EBX)
4292 if (dreg != ins->dreg) {
4293 x86_push_reg (code, dreg);
4296 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4297 x86_prefix (code, X86_LOCK_PREFIX);
4298 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4299 /* dreg contains the old value, add with sreg2 value */
4300 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4302 if (ins->dreg != dreg) {
4303 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4304 x86_pop_reg (code, dreg);
4309 case OP_ATOMIC_EXCHANGE_I4: {
4311 int sreg2 = ins->sreg2;
4312 int breg = ins->inst_basereg;
4314 g_assert (cfg->has_atomic_exchange_i4);
4316 /* cmpxchg uses eax as comperand, need to make sure we can use it
4317 * hack to overcome limits in x86 reg allocator
4318 * (req: dreg == eax and sreg2 != eax and breg != eax)
4320 g_assert (ins->dreg == X86_EAX);
4322 /* We need the EAX reg for the cmpxchg */
4323 if (ins->sreg2 == X86_EAX) {
4324 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4325 x86_push_reg (code, sreg2);
4326 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4329 if (breg == X86_EAX) {
4330 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4331 x86_push_reg (code, breg);
4332 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4335 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4337 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4338 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4339 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4340 x86_patch (br [1], br [0]);
4342 if (breg != ins->inst_basereg)
4343 x86_pop_reg (code, breg);
4345 if (ins->sreg2 != sreg2)
4346 x86_pop_reg (code, sreg2);
4350 case OP_ATOMIC_CAS_I4: {
4351 g_assert (ins->dreg == X86_EAX);
4352 g_assert (ins->sreg3 == X86_EAX);
4353 g_assert (ins->sreg1 != X86_EAX);
4354 g_assert (ins->sreg1 != ins->sreg2);
4356 x86_prefix (code, X86_LOCK_PREFIX);
4357 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4360 case OP_ATOMIC_LOAD_I1: {
4361 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4364 case OP_ATOMIC_LOAD_U1: {
4365 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4368 case OP_ATOMIC_LOAD_I2: {
4369 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4372 case OP_ATOMIC_LOAD_U2: {
4373 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4376 case OP_ATOMIC_LOAD_I4:
4377 case OP_ATOMIC_LOAD_U4: {
4378 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4381 case OP_ATOMIC_LOAD_R4:
4382 case OP_ATOMIC_LOAD_R8: {
4383 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4386 case OP_ATOMIC_STORE_I1:
4387 case OP_ATOMIC_STORE_U1:
4388 case OP_ATOMIC_STORE_I2:
4389 case OP_ATOMIC_STORE_U2:
4390 case OP_ATOMIC_STORE_I4:
4391 case OP_ATOMIC_STORE_U4: {
4394 switch (ins->opcode) {
4395 case OP_ATOMIC_STORE_I1:
4396 case OP_ATOMIC_STORE_U1:
4399 case OP_ATOMIC_STORE_I2:
4400 case OP_ATOMIC_STORE_U2:
4403 case OP_ATOMIC_STORE_I4:
4404 case OP_ATOMIC_STORE_U4:
4409 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4411 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4415 case OP_ATOMIC_STORE_R4:
4416 case OP_ATOMIC_STORE_R8: {
4417 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4419 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4423 case OP_CARD_TABLE_WBARRIER: {
4424 int ptr = ins->sreg1;
4425 int value = ins->sreg2;
4427 int nursery_shift, card_table_shift;
4428 gpointer card_table_mask;
4429 size_t nursery_size;
4430 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4431 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4432 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4435 * We need one register we can clobber, we choose EDX and make sreg1
4436 * fixed EAX to work around limitations in the local register allocator.
4437 * sreg2 might get allocated to EDX, but that is not a problem since
4438 * we use it before clobbering EDX.
4440 g_assert (ins->sreg1 == X86_EAX);
4443 * This is the code we produce:
4446 * edx >>= nursery_shift
4447 * cmp edx, (nursery_start >> nursery_shift)
4450 * edx >>= card_table_shift
4451 * card_table[edx] = 1
4455 if (card_table_nursery_check) {
4456 if (value != X86_EDX)
4457 x86_mov_reg_reg (code, X86_EDX, value, 4);
4458 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4459 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4460 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4462 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4463 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4464 if (card_table_mask)
4465 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4466 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4467 if (card_table_nursery_check)
4468 x86_patch (br, code);
4471 #ifdef MONO_ARCH_SIMD_INTRINSICS
4473 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4476 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4479 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4482 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4485 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4488 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4491 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4492 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4495 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4498 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4501 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4504 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4507 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4510 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4513 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4516 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4519 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4522 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4525 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4528 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4531 case OP_PSHUFLEW_HIGH:
4532 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4533 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4535 case OP_PSHUFLEW_LOW:
4536 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4537 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4540 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4541 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4544 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4545 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4548 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4549 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4553 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4556 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4559 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4562 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4565 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4568 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4571 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4572 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4575 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4578 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4581 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4584 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4587 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4590 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4593 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4596 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4599 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4602 case OP_EXTRACT_MASK:
4603 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4607 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4610 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4613 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4617 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4620 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4623 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4626 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4630 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4633 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4636 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4639 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4643 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4646 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4649 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4653 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4656 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4659 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4663 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4666 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4670 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4673 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4676 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4680 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4683 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4686 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4690 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4693 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4696 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4699 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4703 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4706 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4709 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4712 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4715 case OP_PSUM_ABS_DIFF:
4716 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4719 case OP_UNPACK_LOWB:
4720 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4722 case OP_UNPACK_LOWW:
4723 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4725 case OP_UNPACK_LOWD:
4726 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4728 case OP_UNPACK_LOWQ:
4729 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4731 case OP_UNPACK_LOWPS:
4732 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4734 case OP_UNPACK_LOWPD:
4735 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4738 case OP_UNPACK_HIGHB:
4739 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4741 case OP_UNPACK_HIGHW:
4742 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4744 case OP_UNPACK_HIGHD:
4745 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4747 case OP_UNPACK_HIGHQ:
4748 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4750 case OP_UNPACK_HIGHPS:
4751 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4753 case OP_UNPACK_HIGHPD:
4754 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4758 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4761 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4764 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4767 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4770 case OP_PADDB_SAT_UN:
4771 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4773 case OP_PSUBB_SAT_UN:
4774 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4776 case OP_PADDW_SAT_UN:
4777 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4779 case OP_PSUBW_SAT_UN:
4780 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4784 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4787 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4790 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4793 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4797 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4800 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4803 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4805 case OP_PMULW_HIGH_UN:
4806 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4809 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4813 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4816 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4820 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4823 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4827 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4830 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4834 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4837 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4841 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4844 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4848 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4851 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4855 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4858 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4862 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4865 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4869 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4872 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4876 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4878 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4879 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4883 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4885 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4886 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4890 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4892 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4893 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4897 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4899 case OP_EXTRACTX_U2:
4900 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4902 case OP_INSERTX_U1_SLOW:
4903 /*sreg1 is the extracted ireg (scratch)
4904 /sreg2 is the to be inserted ireg (scratch)
4905 /dreg is the xreg to receive the value*/
4907 /*clear the bits from the extracted word*/
4908 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4909 /*shift the value to insert if needed*/
4910 if (ins->inst_c0 & 1)
4911 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4912 /*join them together*/
4913 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4914 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4916 case OP_INSERTX_I4_SLOW:
4917 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4918 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4919 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4922 case OP_INSERTX_R4_SLOW:
4923 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4924 /*TODO if inst_c0 == 0 use movss*/
4925 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4926 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4928 case OP_INSERTX_R8_SLOW:
4929 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4930 if (cfg->verbose_level)
4931 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4933 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4935 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4938 case OP_STOREX_MEMBASE_REG:
4939 case OP_STOREX_MEMBASE:
4940 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4942 case OP_LOADX_MEMBASE:
4943 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4945 case OP_LOADX_ALIGNED_MEMBASE:
4946 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4948 case OP_STOREX_ALIGNED_MEMBASE_REG:
4949 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4951 case OP_STOREX_NTA_MEMBASE_REG:
4952 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4954 case OP_PREFETCH_MEMBASE:
4955 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4959 /*FIXME the peephole pass should have killed this*/
4960 if (ins->dreg != ins->sreg1)
4961 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4964 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4967 case OP_FCONV_TO_R8_X:
4968 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4969 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4972 case OP_XCONV_R8_TO_I4:
4973 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4974 switch (ins->backend.source_opcode) {
4975 case OP_FCONV_TO_I1:
4976 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4978 case OP_FCONV_TO_U1:
4979 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4981 case OP_FCONV_TO_I2:
4982 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4984 case OP_FCONV_TO_U2:
4985 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4991 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4992 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4993 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4994 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4995 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4996 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4999 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
5000 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
5001 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5004 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
5005 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5008 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
5009 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5010 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5013 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
5014 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5015 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
5019 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
5022 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
5025 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
5028 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
5031 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
5034 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
5037 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
5040 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
5044 case OP_LIVERANGE_START: {
5045 if (cfg->verbose_level > 1)
5046 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5047 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5050 case OP_LIVERANGE_END: {
5051 if (cfg->verbose_level > 1)
5052 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5053 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5056 case OP_GC_SAFE_POINT: {
5057 const char *polling_func = NULL;
5058 int compare_val = 0;
5061 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
5062 polling_func = "mono_nacl_gc";
5063 compare_val = 0xFFFFFFFF;
5065 g_assert (mono_threads_is_coop_enabled ());
5066 polling_func = "mono_threads_state_poll";
5070 x86_test_membase_imm (code, ins->sreg1, 0, compare_val);
5071 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
5072 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
5073 x86_patch (br [0], code);
5077 case OP_GC_LIVENESS_DEF:
5078 case OP_GC_LIVENESS_USE:
5079 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5080 ins->backend.pc_offset = code - cfg->native_code;
5082 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5083 ins->backend.pc_offset = code - cfg->native_code;
5084 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5087 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
5090 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
5093 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
5094 g_assert_not_reached ();
5097 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
5098 #ifndef __native_client_codegen__
5099 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5100 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5101 g_assert_not_reached ();
5102 #endif /* __native_client_codegen__ */
5108 cfg->code_len = code - cfg->native_code;
5111 #endif /* DISABLE_JIT */
5114 mono_arch_register_lowlevel_calls (void)
5119 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5121 unsigned char *ip = ji->ip.i + code;
5124 case MONO_PATCH_INFO_IP:
5125 *((gconstpointer *)(ip)) = target;
5127 case MONO_PATCH_INFO_ABS:
5128 case MONO_PATCH_INFO_METHOD:
5129 case MONO_PATCH_INFO_METHOD_JUMP:
5130 case MONO_PATCH_INFO_INTERNAL_METHOD:
5131 case MONO_PATCH_INFO_BB:
5132 case MONO_PATCH_INFO_LABEL:
5133 case MONO_PATCH_INFO_RGCTX_FETCH:
5134 case MONO_PATCH_INFO_MONITOR_ENTER:
5135 case MONO_PATCH_INFO_MONITOR_ENTER_V4:
5136 case MONO_PATCH_INFO_MONITOR_EXIT:
5137 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5138 #if defined(__native_client_codegen__) && defined(__native_client__)
5139 if (nacl_is_code_address (code)) {
5140 /* For tail calls, code is patched after being installed */
5141 /* but not through the normal "patch callsite" method. */
5142 unsigned char buf[kNaClAlignment];
5143 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5144 unsigned char *_target = target;
5146 /* All patch targets modified in x86_patch */
5147 /* are IP relative. */
5148 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5149 memcpy (buf, aligned_code, kNaClAlignment);
5150 /* Patch a temp buffer of bundle size, */
5151 /* then install to actual location. */
5152 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5153 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5154 g_assert (ret == 0);
5157 x86_patch (ip, (unsigned char*)target);
5160 x86_patch (ip, (unsigned char*)target);
5163 case MONO_PATCH_INFO_NONE:
5165 case MONO_PATCH_INFO_R4:
5166 case MONO_PATCH_INFO_R8: {
5167 guint32 offset = mono_arch_get_patch_offset (ip);
5168 *((gconstpointer *)(ip + offset)) = target;
5172 guint32 offset = mono_arch_get_patch_offset (ip);
5173 #if !defined(__native_client__)
5174 *((gconstpointer *)(ip + offset)) = target;
5176 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5183 static G_GNUC_UNUSED void
5184 stack_unaligned (MonoMethod *m, gpointer caller)
5186 printf ("%s\n", mono_method_full_name (m, TRUE));
5187 g_assert_not_reached ();
5191 mono_arch_emit_prolog (MonoCompile *cfg)
5193 MonoMethod *method = cfg->method;
5195 MonoMethodSignature *sig;
5197 int alloc_size, pos, max_offset, i, cfa_offset;
5199 gboolean need_stack_frame;
5200 #ifdef __native_client_codegen__
5201 guint alignment_check;
5204 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5206 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5207 cfg->code_size += 512;
5209 #if defined(__default_codegen__)
5210 code = cfg->native_code = g_malloc (cfg->code_size);
5211 #elif defined(__native_client_codegen__)
5212 /* native_code_alloc is not 32-byte aligned, native_code is. */
5213 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5214 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5216 /* Align native_code to next nearest kNaclAlignment byte. */
5217 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5218 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5220 code = cfg->native_code;
5222 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5223 g_assert(alignment_check == 0);
5230 /* Check that the stack is aligned on osx */
5231 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5232 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5233 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5235 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5236 x86_push_membase (code, X86_ESP, 0);
5237 x86_push_imm (code, cfg->method);
5238 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5239 x86_call_reg (code, X86_EAX);
5240 x86_patch (br [0], code);
5244 /* Offset between RSP and the CFA */
5248 cfa_offset = sizeof (gpointer);
5249 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5250 // IP saved at CFA - 4
5251 /* There is no IP reg on x86 */
5252 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5253 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5255 need_stack_frame = needs_stack_frame (cfg);
5257 if (need_stack_frame) {
5258 x86_push_reg (code, X86_EBP);
5259 cfa_offset += sizeof (gpointer);
5260 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5261 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5262 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5263 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5264 /* These are handled automatically by the stack marking code */
5265 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5267 cfg->frame_reg = X86_ESP;
5270 cfg->stack_offset += cfg->param_area;
5271 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5273 alloc_size = cfg->stack_offset;
5276 if (!method->save_lmf) {
5277 if (cfg->used_int_regs & (1 << X86_EBX)) {
5278 x86_push_reg (code, X86_EBX);
5280 cfa_offset += sizeof (gpointer);
5281 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5282 /* These are handled automatically by the stack marking code */
5283 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5286 if (cfg->used_int_regs & (1 << X86_EDI)) {
5287 x86_push_reg (code, X86_EDI);
5289 cfa_offset += sizeof (gpointer);
5290 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5291 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5294 if (cfg->used_int_regs & (1 << X86_ESI)) {
5295 x86_push_reg (code, X86_ESI);
5297 cfa_offset += sizeof (gpointer);
5298 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5299 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5305 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5306 if (mono_do_x86_stack_align && need_stack_frame) {
5307 int tot = alloc_size + pos + 4; /* ret ip */
5308 if (need_stack_frame)
5310 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5312 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5313 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5314 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5318 cfg->arch.sp_fp_offset = alloc_size + pos;
5321 /* See mono_emit_stack_alloc */
5322 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5323 guint32 remaining_size = alloc_size;
5324 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5325 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5326 guint32 offset = code - cfg->native_code;
5327 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5328 while (required_code_size >= (cfg->code_size - offset))
5329 cfg->code_size *= 2;
5330 cfg->native_code = mono_realloc_native_code(cfg);
5331 code = cfg->native_code + offset;
5332 cfg->stat_code_reallocs++;
5334 while (remaining_size >= 0x1000) {
5335 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5336 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5337 remaining_size -= 0x1000;
5340 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5342 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5345 g_assert (need_stack_frame);
5348 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5349 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5350 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5353 #if DEBUG_STACK_ALIGNMENT
5354 /* check the stack is aligned */
5355 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5356 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5357 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5358 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5359 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5360 x86_breakpoint (code);
5364 /* compute max_offset in order to use short forward jumps */
5366 if (cfg->opt & MONO_OPT_BRANCH) {
5367 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5369 bb->max_offset = max_offset;
5371 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5373 /* max alignment for loops */
5374 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5375 max_offset += LOOP_ALIGNMENT;
5376 #ifdef __native_client_codegen__
5377 /* max alignment for native client */
5378 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5379 max_offset += kNaClAlignment;
5381 MONO_BB_FOR_EACH_INS (bb, ins) {
5382 if (ins->opcode == OP_LABEL)
5383 ins->inst_c1 = max_offset;
5384 #ifdef __native_client_codegen__
5385 switch (ins->opcode)
5397 case OP_VOIDCALL_REG:
5399 case OP_FCALL_MEMBASE:
5400 case OP_LCALL_MEMBASE:
5401 case OP_VCALL_MEMBASE:
5402 case OP_VCALL2_MEMBASE:
5403 case OP_VOIDCALL_MEMBASE:
5404 case OP_CALL_MEMBASE:
5405 max_offset += kNaClAlignment;
5408 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5411 #endif /* __native_client_codegen__ */
5412 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5417 /* store runtime generic context */
5418 if (cfg->rgctx_var) {
5419 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5421 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5424 if (method->save_lmf)
5425 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5427 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5428 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5433 if (cfg->arch.ss_tramp_var) {
5434 /* Initialize ss_tramp_var */
5435 ins = cfg->arch.ss_tramp_var;
5436 g_assert (ins->opcode == OP_REGOFFSET);
5438 g_assert (!cfg->compile_aot);
5439 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&ss_trampoline, 4);
5442 if (cfg->arch.bp_tramp_var) {
5443 /* Initialize bp_tramp_var */
5444 ins = cfg->arch.bp_tramp_var;
5445 g_assert (ins->opcode == OP_REGOFFSET);
5447 g_assert (!cfg->compile_aot);
5448 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&bp_trampoline, 4);
5452 /* load arguments allocated to register from the stack */
5453 sig = mono_method_signature (method);
5456 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5457 inst = cfg->args [pos];
5458 if (inst->opcode == OP_REGVAR) {
5459 g_assert (need_stack_frame);
5460 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5461 if (cfg->verbose_level > 2)
5462 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5467 cfg->code_len = code - cfg->native_code;
5469 g_assert (cfg->code_len < cfg->code_size);
5475 mono_arch_emit_epilog (MonoCompile *cfg)
5477 MonoMethod *method = cfg->method;
5478 MonoMethodSignature *sig = mono_method_signature (method);
5480 guint32 stack_to_pop;
5482 int max_epilog_size = 16;
5484 gboolean need_stack_frame = needs_stack_frame (cfg);
5486 if (cfg->method->save_lmf)
5487 max_epilog_size += 128;
5489 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5490 cfg->code_size *= 2;
5491 cfg->native_code = mono_realloc_native_code(cfg);
5492 cfg->stat_code_reallocs++;
5495 code = cfg->native_code + cfg->code_len;
5497 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5498 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5500 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5503 if (method->save_lmf) {
5504 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5506 gboolean supported = FALSE;
5508 if (cfg->compile_aot) {
5509 #if defined(MONO_HAVE_FAST_TLS)
5512 } else if (mono_get_jit_tls_offset () != -1) {
5516 /* check if we need to restore protection of the stack after a stack overflow */
5518 if (cfg->compile_aot) {
5519 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5521 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5523 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5526 /* we load the value in a separate instruction: this mechanism may be
5527 * used later as a safer way to do thread interruption
5529 x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5530 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5532 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5533 /* note that the call trampoline will preserve eax/edx */
5534 x86_call_reg (code, X86_ECX);
5535 x86_patch (patch, code);
5537 /* FIXME: maybe save the jit tls in the prolog */
5540 /* restore caller saved regs */
5541 if (cfg->used_int_regs & (1 << X86_EBX)) {
5542 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5545 if (cfg->used_int_regs & (1 << X86_EDI)) {
5546 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5548 if (cfg->used_int_regs & (1 << X86_ESI)) {
5549 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5552 /* EBP is restored by LEAVE */
5554 for (i = 0; i < X86_NREG; ++i) {
5555 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5561 g_assert (need_stack_frame);
5562 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5566 g_assert (need_stack_frame);
5567 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5570 if (cfg->used_int_regs & (1 << X86_ESI)) {
5571 x86_pop_reg (code, X86_ESI);
5573 if (cfg->used_int_regs & (1 << X86_EDI)) {
5574 x86_pop_reg (code, X86_EDI);
5576 if (cfg->used_int_regs & (1 << X86_EBX)) {
5577 x86_pop_reg (code, X86_EBX);
5581 /* Load returned vtypes into registers if needed */
5582 cinfo = get_call_info (cfg->mempool, sig);
5583 if (cinfo->ret.storage == ArgValuetypeInReg) {
5584 for (quad = 0; quad < 2; quad ++) {
5585 switch (cinfo->ret.pair_storage [quad]) {
5587 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5589 case ArgOnFloatFpStack:
5590 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5592 case ArgOnDoubleFpStack:
5593 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5598 g_assert_not_reached ();
5603 if (need_stack_frame)
5606 if (CALLCONV_IS_STDCALL (sig)) {
5607 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5609 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
5610 } else if (cinfo->callee_stack_pop)
5611 stack_to_pop = cinfo->callee_stack_pop;
5616 g_assert (need_stack_frame);
5617 x86_ret_imm (code, stack_to_pop);
5622 cfg->code_len = code - cfg->native_code;
5624 g_assert (cfg->code_len < cfg->code_size);
5628 mono_arch_emit_exceptions (MonoCompile *cfg)
5630 MonoJumpInfo *patch_info;
5633 MonoClass *exc_classes [16];
5634 guint8 *exc_throw_start [16], *exc_throw_end [16];
5638 /* Compute needed space */
5639 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5640 if (patch_info->type == MONO_PATCH_INFO_EXC)
5645 * make sure we have enough space for exceptions
5646 * 16 is the size of two push_imm instructions and a call
5648 if (cfg->compile_aot)
5649 code_size = exc_count * 32;
5651 code_size = exc_count * 16;
5653 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5654 cfg->code_size *= 2;
5655 cfg->native_code = mono_realloc_native_code(cfg);
5656 cfg->stat_code_reallocs++;
5659 code = cfg->native_code + cfg->code_len;
5662 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5663 switch (patch_info->type) {
5664 case MONO_PATCH_INFO_EXC: {
5665 MonoClass *exc_class;
5669 x86_patch (patch_info->ip.i + cfg->native_code, code);
5671 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5672 g_assert (exc_class);
5673 throw_ip = patch_info->ip.i;
5675 /* Find a throw sequence for the same exception class */
5676 for (i = 0; i < nthrows; ++i)
5677 if (exc_classes [i] == exc_class)
5680 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5681 x86_jump_code (code, exc_throw_start [i]);
5682 patch_info->type = MONO_PATCH_INFO_NONE;
5687 /* Compute size of code following the push <OFFSET> */
5688 #if defined(__default_codegen__)
5690 #elif defined(__native_client_codegen__)
5691 code = mono_nacl_align (code);
5692 size = kNaClAlignment;
5694 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5696 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5697 /* Use the shorter form */
5699 x86_push_imm (code, 0);
5703 x86_push_imm (code, 0xf0f0f0f0);
5708 exc_classes [nthrows] = exc_class;
5709 exc_throw_start [nthrows] = code;
5712 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5713 patch_info->data.name = "mono_arch_throw_corlib_exception";
5714 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5715 patch_info->ip.i = code - cfg->native_code;
5716 x86_call_code (code, 0);
5717 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5722 exc_throw_end [nthrows] = code;
5734 cfg->code_len = code - cfg->native_code;
5736 g_assert (cfg->code_len < cfg->code_size);
5740 mono_arch_flush_icache (guint8 *code, gint size)
5746 mono_arch_flush_register_windows (void)
5751 mono_arch_is_inst_imm (gint64 imm)
5757 mono_arch_finish_init (void)
5759 if (!g_getenv ("MONO_NO_TLS")) {
5760 #ifndef TARGET_WIN32
5762 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5769 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5773 // Linear handler, the bsearch head compare is shorter
5774 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5775 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5776 // x86_patch(ins,target)
5777 //[1 + 5] x86_jump_mem(inst,mem)
5780 #if defined(__default_codegen__)
5781 #define BR_SMALL_SIZE 2
5782 #define BR_LARGE_SIZE 5
5783 #elif defined(__native_client_codegen__)
5784 /* I suspect the size calculation below is actually incorrect. */
5785 /* TODO: fix the calculation that uses these sizes. */
5786 #define BR_SMALL_SIZE 16
5787 #define BR_LARGE_SIZE 12
5788 #endif /*__native_client_codegen__*/
5789 #define JUMP_IMM_SIZE 6
5790 #define ENABLE_WRONG_METHOD_CHECK 0
5794 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5796 int i, distance = 0;
5797 for (i = start; i < target; ++i)
5798 distance += imt_entries [i]->chunk_size;
5803 * LOCKING: called with the domain lock held
5806 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5807 gpointer fail_tramp)
5811 guint8 *code, *start;
5814 for (i = 0; i < count; ++i) {
5815 MonoIMTCheckItem *item = imt_entries [i];
5816 if (item->is_equals) {
5817 if (item->check_target_idx) {
5818 if (!item->compare_done)
5819 item->chunk_size += CMP_SIZE;
5820 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5823 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5825 item->chunk_size += JUMP_IMM_SIZE;
5826 #if ENABLE_WRONG_METHOD_CHECK
5827 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5832 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5833 imt_entries [item->check_target_idx]->compare_done = TRUE;
5835 size += item->chunk_size;
5837 #if defined(__native_client__) && defined(__native_client_codegen__)
5838 /* In Native Client, we don't re-use thunks, allocate from the */
5839 /* normal code manager paths. */
5840 size = NACL_BUNDLE_ALIGN_UP (size);
5841 code = mono_domain_code_reserve (domain, size);
5844 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5846 code = mono_domain_code_reserve (domain, size);
5850 unwind_ops = mono_arch_get_cie_program ();
5852 for (i = 0; i < count; ++i) {
5853 MonoIMTCheckItem *item = imt_entries [i];
5854 item->code_target = code;
5855 if (item->is_equals) {
5856 if (item->check_target_idx) {
5857 if (!item->compare_done)
5858 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5859 item->jmp_code = code;
5860 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5861 if (item->has_target_code)
5862 x86_jump_code (code, item->value.target_code);
5864 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5867 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5868 item->jmp_code = code;
5869 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5870 if (item->has_target_code)
5871 x86_jump_code (code, item->value.target_code);
5873 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5874 x86_patch (item->jmp_code, code);
5875 x86_jump_code (code, fail_tramp);
5876 item->jmp_code = NULL;
5878 /* enable the commented code to assert on wrong method */
5879 #if ENABLE_WRONG_METHOD_CHECK
5880 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5881 item->jmp_code = code;
5882 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5884 if (item->has_target_code)
5885 x86_jump_code (code, item->value.target_code);
5887 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5888 #if ENABLE_WRONG_METHOD_CHECK
5889 x86_patch (item->jmp_code, code);
5890 x86_breakpoint (code);
5891 item->jmp_code = NULL;
5896 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5897 item->jmp_code = code;
5898 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5899 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5901 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5904 /* patch the branches to get to the target items */
5905 for (i = 0; i < count; ++i) {
5906 MonoIMTCheckItem *item = imt_entries [i];
5907 if (item->jmp_code) {
5908 if (item->check_target_idx) {
5909 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5915 mono_stats.imt_thunks_size += code - start;
5916 g_assert (code - start <= size);
5920 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5921 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5925 if (mono_jit_map_is_enabled ()) {
5928 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5930 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5931 mono_emit_jit_tramp (start, code - start, buff);
5935 nacl_domain_code_validate (domain, &start, size, &code);
5936 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
5938 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
5944 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5946 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5950 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5952 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5956 mono_arch_get_cie_program (void)
5960 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5961 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5967 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5969 MonoInst *ins = NULL;
5972 if (cmethod->klass == mono_defaults.math_class) {
5973 if (strcmp (cmethod->name, "Sin") == 0) {
5975 } else if (strcmp (cmethod->name, "Cos") == 0) {
5977 } else if (strcmp (cmethod->name, "Tan") == 0) {
5979 } else if (strcmp (cmethod->name, "Atan") == 0) {
5981 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5983 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5985 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5989 if (opcode && fsig->param_count == 1) {
5990 MONO_INST_NEW (cfg, ins, opcode);
5991 ins->type = STACK_R8;
5992 ins->dreg = mono_alloc_freg (cfg);
5993 ins->sreg1 = args [0]->dreg;
5994 MONO_ADD_INS (cfg->cbb, ins);
5997 if (cfg->opt & MONO_OPT_CMOV) {
6000 if (strcmp (cmethod->name, "Min") == 0) {
6001 if (fsig->params [0]->type == MONO_TYPE_I4)
6003 } else if (strcmp (cmethod->name, "Max") == 0) {
6004 if (fsig->params [0]->type == MONO_TYPE_I4)
6008 if (opcode && fsig->param_count == 2) {
6009 MONO_INST_NEW (cfg, ins, opcode);
6010 ins->type = STACK_I4;
6011 ins->dreg = mono_alloc_ireg (cfg);
6012 ins->sreg1 = args [0]->dreg;
6013 ins->sreg2 = args [1]->dreg;
6014 MONO_ADD_INS (cfg->cbb, ins);
6019 /* OP_FREM is not IEEE compatible */
6020 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
6021 MONO_INST_NEW (cfg, ins, OP_FREM);
6022 ins->inst_i0 = args [0];
6023 ins->inst_i1 = args [1];
6032 mono_arch_print_tree (MonoInst *tree, int arity)
6038 mono_arch_get_patch_offset (guint8 *code)
6040 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
6042 else if (code [0] == 0xba)
6044 else if (code [0] == 0x68)
6047 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
6048 /* push <OFFSET>(<REG>) */
6050 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
6051 /* call *<OFFSET>(<REG>) */
6053 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
6056 else if ((code [0] == 0x58) && (code [1] == 0x05))
6057 /* pop %eax; add <OFFSET>, %eax */
6059 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6060 /* pop <REG>; add <OFFSET>, <REG> */
6062 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6063 /* mov <REG>, imm */
6066 g_assert_not_reached ();
6072 * mono_breakpoint_clean_code:
6074 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6075 * breakpoints in the original code, they are removed in the copy.
6077 * Returns TRUE if no sw breakpoint was present.
6080 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6083 * If method_start is non-NULL we need to perform bound checks, since we access memory
6084 * at code - offset we could go before the start of the method and end up in a different
6085 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6088 if (!method_start || code - offset >= method_start) {
6089 memcpy (buf, code - offset, size);
6091 int diff = code - method_start;
6092 memset (buf, 0, size);
6093 memcpy (buf + offset - diff, method_start, diff + size - offset);
6099 * mono_x86_get_this_arg_offset:
6101 * Return the offset of the stack location where this is passed during a virtual
6105 mono_x86_get_this_arg_offset (MonoMethodSignature *sig)
6111 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6113 guint32 esp = regs [X86_ESP];
6120 * The stack looks like:
6124 res = ((MonoObject**)esp) [0];
6128 #define MAX_ARCH_DELEGATE_PARAMS 10
6131 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
6133 guint8 *code, *start;
6134 int code_reserve = 64;
6137 unwind_ops = mono_arch_get_cie_program ();
6140 * The stack contains:
6146 start = code = mono_global_codeman_reserve (code_reserve);
6148 /* Replace the this argument with the target */
6149 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6150 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6151 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6152 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6154 g_assert ((code - start) < code_reserve);
6157 /* 8 for mov_reg and jump, plus 8 for each parameter */
6158 #ifdef __native_client_codegen__
6159 /* TODO: calculate this size correctly */
6160 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6162 code_reserve = 8 + (param_count * 8);
6163 #endif /* __native_client_codegen__ */
6165 * The stack contains:
6166 * <args in reverse order>
6171 * <args in reverse order>
6174 * without unbalancing the stack.
6175 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6176 * and leaving original spot of first arg as placeholder in stack so
6177 * when callee pops stack everything works.
6180 start = code = mono_global_codeman_reserve (code_reserve);
6182 /* store delegate for access to method_ptr */
6183 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6186 for (i = 0; i < param_count; ++i) {
6187 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6188 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6191 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6193 g_assert ((code - start) < code_reserve);
6196 nacl_global_codeman_validate (&start, code_reserve, &code);
6199 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
6201 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
6202 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
6206 if (mono_jit_map_is_enabled ()) {
6209 buff = (char*)"delegate_invoke_has_target";
6211 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6212 mono_emit_jit_tramp (start, code - start, buff);
6216 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6221 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
6224 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
6226 guint8 *code, *start;
6231 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
6235 * The stack contains:
6239 start = code = mono_global_codeman_reserve (size);
6241 unwind_ops = mono_arch_get_cie_program ();
6243 /* Replace the this argument with the target */
6244 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6245 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6246 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6249 /* Load the IMT reg */
6250 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
6253 /* Load the vtable */
6254 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
6255 x86_jump_membase (code, X86_EAX, offset);
6256 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6259 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
6261 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
6262 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
6263 g_free (tramp_name);
6270 mono_arch_get_delegate_invoke_impls (void)
6273 MonoTrampInfo *info;
6276 get_delegate_invoke_impl (&info, TRUE, 0);
6277 res = g_slist_prepend (res, info);
6279 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
6280 get_delegate_invoke_impl (&info, FALSE, i);
6281 res = g_slist_prepend (res, info);
6284 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
6285 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
6286 res = g_slist_prepend (res, info);
6288 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
6289 res = g_slist_prepend (res, info);
6296 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6298 guint8 *code, *start;
6300 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6303 /* FIXME: Support more cases */
6304 if (MONO_TYPE_ISSTRUCT (sig->ret))
6308 * The stack contains:
6314 static guint8* cached = NULL;
6318 if (mono_aot_only) {
6319 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6321 MonoTrampInfo *info;
6322 start = get_delegate_invoke_impl (&info, TRUE, 0);
6323 mono_tramp_info_register (info, NULL);
6326 mono_memory_barrier ();
6330 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6333 for (i = 0; i < sig->param_count; ++i)
6334 if (!mono_is_regsize_var (sig->params [i]))
6337 code = cache [sig->param_count];
6341 if (mono_aot_only) {
6342 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6343 start = mono_aot_get_trampoline (name);
6346 MonoTrampInfo *info;
6347 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
6348 mono_tramp_info_register (info, NULL);
6351 mono_memory_barrier ();
6353 cache [sig->param_count] = start;
6360 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
6362 MonoTrampInfo *info;
6365 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
6367 mono_tramp_info_register (info, NULL);
6372 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6375 case X86_EAX: return ctx->eax;
6376 case X86_EBX: return ctx->ebx;
6377 case X86_ECX: return ctx->ecx;
6378 case X86_EDX: return ctx->edx;
6379 case X86_ESP: return ctx->esp;
6380 case X86_EBP: return ctx->ebp;
6381 case X86_ESI: return ctx->esi;
6382 case X86_EDI: return ctx->edi;
6384 g_assert_not_reached ();
6390 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6418 g_assert_not_reached ();
6422 #ifdef MONO_ARCH_SIMD_INTRINSICS
6425 get_float_to_x_spill_area (MonoCompile *cfg)
6427 if (!cfg->fconv_to_r8_x_var) {
6428 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6429 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6431 return cfg->fconv_to_r8_x_var;
6435 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6438 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6441 int dreg, src_opcode;
6443 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6446 switch (src_opcode = ins->opcode) {
6447 case OP_FCONV_TO_I1:
6448 case OP_FCONV_TO_U1:
6449 case OP_FCONV_TO_I2:
6450 case OP_FCONV_TO_U2:
6451 case OP_FCONV_TO_I4:
6458 /* dreg is the IREG and sreg1 is the FREG */
6459 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6460 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6461 fconv->sreg1 = ins->sreg1;
6462 fconv->dreg = mono_alloc_ireg (cfg);
6463 fconv->type = STACK_VTYPE;
6464 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6466 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6470 ins->opcode = OP_XCONV_R8_TO_I4;
6472 ins->klass = mono_defaults.int32_class;
6473 ins->sreg1 = fconv->dreg;
6475 ins->type = STACK_I4;
6476 ins->backend.source_opcode = src_opcode;
6479 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6482 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6487 if (long_ins->opcode == OP_LNEG) {
6489 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6490 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6491 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6496 #ifdef MONO_ARCH_SIMD_INTRINSICS
6498 if (!(cfg->opt & MONO_OPT_SIMD))
6501 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6502 switch (long_ins->opcode) {
6504 vreg = long_ins->sreg1;
6506 if (long_ins->inst_c0) {
6507 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6508 ins->klass = long_ins->klass;
6509 ins->sreg1 = long_ins->sreg1;
6511 ins->type = STACK_VTYPE;
6512 ins->dreg = vreg = alloc_ireg (cfg);
6513 MONO_ADD_INS (cfg->cbb, ins);
6516 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6517 ins->klass = mono_defaults.int32_class;
6519 ins->type = STACK_I4;
6520 ins->dreg = long_ins->dreg + 1;
6521 MONO_ADD_INS (cfg->cbb, ins);
6523 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6524 ins->klass = long_ins->klass;
6525 ins->sreg1 = long_ins->sreg1;
6526 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6527 ins->type = STACK_VTYPE;
6528 ins->dreg = vreg = alloc_ireg (cfg);
6529 MONO_ADD_INS (cfg->cbb, ins);
6531 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6532 ins->klass = mono_defaults.int32_class;
6534 ins->type = STACK_I4;
6535 ins->dreg = long_ins->dreg + 2;
6536 MONO_ADD_INS (cfg->cbb, ins);
6538 long_ins->opcode = OP_NOP;
6540 case OP_INSERTX_I8_SLOW:
6541 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6542 ins->dreg = long_ins->dreg;
6543 ins->sreg1 = long_ins->dreg;
6544 ins->sreg2 = long_ins->sreg2 + 1;
6545 ins->inst_c0 = long_ins->inst_c0 * 2;
6546 MONO_ADD_INS (cfg->cbb, ins);
6548 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6549 ins->dreg = long_ins->dreg;
6550 ins->sreg1 = long_ins->dreg;
6551 ins->sreg2 = long_ins->sreg2 + 2;
6552 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6553 MONO_ADD_INS (cfg->cbb, ins);
6555 long_ins->opcode = OP_NOP;
6558 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6559 ins->dreg = long_ins->dreg;
6560 ins->sreg1 = long_ins->sreg1 + 1;
6561 ins->klass = long_ins->klass;
6562 ins->type = STACK_VTYPE;
6563 MONO_ADD_INS (cfg->cbb, ins);
6565 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6566 ins->dreg = long_ins->dreg;
6567 ins->sreg1 = long_ins->dreg;
6568 ins->sreg2 = long_ins->sreg1 + 2;
6570 ins->klass = long_ins->klass;
6571 ins->type = STACK_VTYPE;
6572 MONO_ADD_INS (cfg->cbb, ins);
6574 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6575 ins->dreg = long_ins->dreg;
6576 ins->sreg1 = long_ins->dreg;;
6577 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6578 ins->klass = long_ins->klass;
6579 ins->type = STACK_VTYPE;
6580 MONO_ADD_INS (cfg->cbb, ins);
6582 long_ins->opcode = OP_NOP;
6585 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6588 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6590 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6593 gpointer *sp, old_value;
6596 offset = clause->exvar_offset;
6599 bp = MONO_CONTEXT_GET_BP (ctx);
6600 sp = *(gpointer*)(bp + offset);
6603 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6612 * mono_aot_emit_load_got_addr:
6614 * Emit code to load the got address.
6615 * On x86, the result is placed into EBX.
6618 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6620 x86_call_imm (code, 0);
6622 * The patch needs to point to the pop, since the GOT offset needs
6623 * to be added to that address.
6626 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6628 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6629 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6630 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6636 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6639 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6641 g_assert_not_reached ();
6642 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6647 * mono_arch_emit_load_aotconst:
6649 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6650 * TARGET from the mscorlib GOT in full-aot code.
6651 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6655 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6657 /* Load the mscorlib got address */
6658 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6659 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6660 /* arch_emit_got_access () patches this */
6661 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6666 /* Can't put this into mini-x86.h */
6668 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6671 mono_arch_get_trampolines (gboolean aot)
6673 MonoTrampInfo *info;
6674 GSList *tramps = NULL;
6676 mono_x86_get_signal_exception_trampoline (&info, aot);
6678 tramps = g_slist_append (tramps, info);
6683 /* Soft Debug support */
6684 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6687 * mono_arch_set_breakpoint:
6689 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6690 * The location should contain code emitted by OP_SEQ_POINT.
6693 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6695 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6697 g_assert (code [0] == 0x90);
6698 x86_call_membase (code, X86_ECX, 0);
6702 * mono_arch_clear_breakpoint:
6704 * Clear the breakpoint at IP.
6707 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6709 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6712 for (i = 0; i < 2; ++i)
6717 * mono_arch_start_single_stepping:
6719 * Start single stepping.
6722 mono_arch_start_single_stepping (void)
6724 ss_trampoline = mini_get_single_step_trampoline ();
6728 * mono_arch_stop_single_stepping:
6730 * Stop single stepping.
6733 mono_arch_stop_single_stepping (void)
6735 ss_trampoline = NULL;
6739 * mono_arch_is_single_step_event:
6741 * Return whenever the machine state in SIGCTX corresponds to a single
6745 mono_arch_is_single_step_event (void *info, void *sigctx)
6747 /* We use soft breakpoints */
6752 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6754 /* We use soft breakpoints */
6758 #define BREAKPOINT_SIZE 2
6761 * mono_arch_skip_breakpoint:
6763 * See mini-amd64.c for docs.
6766 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6768 g_assert_not_reached ();
6772 * mono_arch_skip_single_step:
6774 * See mini-amd64.c for docs.
6777 mono_arch_skip_single_step (MonoContext *ctx)
6779 g_assert_not_reached ();
6783 * mono_arch_get_seq_point_info:
6785 * See mini-amd64.c for docs.
6788 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6795 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6797 ext->lmf.previous_lmf = (gsize)prev_lmf;
6798 /* Mark that this is a MonoLMFExt */
6799 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6800 ext->lmf.ebp = (gssize)ext;
6806 mono_arch_opcode_supported (int opcode)
6809 case OP_ATOMIC_ADD_I4:
6810 case OP_ATOMIC_EXCHANGE_I4:
6811 case OP_ATOMIC_CAS_I4:
6812 case OP_ATOMIC_LOAD_I1:
6813 case OP_ATOMIC_LOAD_I2:
6814 case OP_ATOMIC_LOAD_I4:
6815 case OP_ATOMIC_LOAD_U1:
6816 case OP_ATOMIC_LOAD_U2:
6817 case OP_ATOMIC_LOAD_U4:
6818 case OP_ATOMIC_LOAD_R4:
6819 case OP_ATOMIC_LOAD_R8:
6820 case OP_ATOMIC_STORE_I1:
6821 case OP_ATOMIC_STORE_I2:
6822 case OP_ATOMIC_STORE_I4:
6823 case OP_ATOMIC_STORE_U1:
6824 case OP_ATOMIC_STORE_U2:
6825 case OP_ATOMIC_STORE_U4:
6826 case OP_ATOMIC_STORE_R4:
6827 case OP_ATOMIC_STORE_R8:
6834 #if defined(ENABLE_GSHAREDVT)
6836 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6838 #endif /* !MONOTOUCH */