2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/abi-details.h>
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/metadata/gc-internals.h>
27 #include <mono/utils/mono-math.h>
28 #include <mono/utils/mono-counters.h>
29 #include <mono/utils/mono-mmap.h>
30 #include <mono/utils/mono-memory-model.h>
31 #include <mono/utils/mono-hwcap-x86.h>
32 #include <mono/utils/mono-threads.h>
42 static gboolean optimize_for_xen = TRUE;
44 #define optimize_for_xen 0
48 /* The single step trampoline */
49 static gpointer ss_trampoline;
51 /* The breakpoint trampoline */
52 static gpointer bp_trampoline;
54 /* This mutex protects architecture specific caches */
55 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
56 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
57 static mono_mutex_t mini_arch_mutex;
59 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
64 /* Under windows, the default pinvoke calling convention is stdcall */
65 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
67 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
70 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
72 #define OP_SEQ_POINT_BP_OFFSET 7
75 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
77 #ifdef __native_client_codegen__
79 /* Default alignment for Native Client is 32-byte. */
80 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
82 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
83 /* Check that alignment doesn't cross an alignment boundary. */
85 mono_arch_nacl_pad (guint8 *code, int pad)
87 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
89 if (pad == 0) return code;
90 /* assertion: alignment cannot cross a block boundary */
91 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
92 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
93 while (pad >= kMaxPadding) {
94 x86_padding (code, kMaxPadding);
97 if (pad != 0) x86_padding (code, pad);
102 mono_arch_nacl_skip_nops (guint8 *code)
104 x86_skip_nops (code);
108 #endif /* __native_client_codegen__ */
111 mono_arch_regname (int reg)
114 case X86_EAX: return "%eax";
115 case X86_EBX: return "%ebx";
116 case X86_ECX: return "%ecx";
117 case X86_EDX: return "%edx";
118 case X86_ESP: return "%esp";
119 case X86_EBP: return "%ebp";
120 case X86_EDI: return "%edi";
121 case X86_ESI: return "%esi";
127 mono_arch_fregname (int reg)
152 mono_arch_xregname (int reg)
177 mono_x86_patch (unsigned char* code, gpointer target)
179 x86_patch (code, (unsigned char*)target);
182 #define FLOAT_PARAM_REGS 0
184 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
186 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
191 switch (sig->call_convention) {
192 case MONO_CALL_THISCALL:
193 return thiscall_param_regs;
199 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
200 #define SMALL_STRUCTS_IN_REGS
201 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
205 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
207 ainfo->offset = *stack_size;
209 if (!param_regs || param_regs [*gr] == X86_NREG) {
210 ainfo->storage = ArgOnStack;
212 (*stack_size) += sizeof (gpointer);
215 ainfo->storage = ArgInIReg;
216 ainfo->reg = param_regs [*gr];
222 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
224 ainfo->offset = *stack_size;
226 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
228 ainfo->storage = ArgOnStack;
229 (*stack_size) += sizeof (gpointer) * 2;
234 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
236 ainfo->offset = *stack_size;
238 if (*gr >= FLOAT_PARAM_REGS) {
239 ainfo->storage = ArgOnStack;
240 (*stack_size) += is_double ? 8 : 4;
241 ainfo->nslots = is_double ? 2 : 1;
244 /* A double register */
246 ainfo->storage = ArgInDoubleSSEReg;
248 ainfo->storage = ArgInFloatSSEReg;
256 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
258 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
263 klass = mono_class_from_mono_type (type);
264 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
266 #ifdef SMALL_STRUCTS_IN_REGS
267 if (sig->pinvoke && is_return) {
268 MonoMarshalType *info;
271 * the exact rules are not very well documented, the code below seems to work with the
272 * code generated by gcc 3.3.3 -mno-cygwin.
274 info = mono_marshal_load_type_info (klass);
277 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
279 /* Special case structs with only a float member */
280 if (info->num_fields == 1) {
281 int ftype = mini_get_underlying_type (info->fields [0].field->type)->type;
282 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
283 ainfo->storage = ArgValuetypeInReg;
284 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
287 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
288 ainfo->storage = ArgValuetypeInReg;
289 ainfo->pair_storage [0] = ArgOnFloatFpStack;
293 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
294 ainfo->storage = ArgValuetypeInReg;
295 ainfo->pair_storage [0] = ArgInIReg;
296 ainfo->pair_regs [0] = return_regs [0];
297 if (info->native_size > 4) {
298 ainfo->pair_storage [1] = ArgInIReg;
299 ainfo->pair_regs [1] = return_regs [1];
306 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
307 g_assert (size <= 4);
308 ainfo->storage = ArgValuetypeInReg;
309 ainfo->reg = param_regs [*gr];
314 ainfo->offset = *stack_size;
315 ainfo->storage = ArgOnStack;
316 *stack_size += ALIGN_TO (size, sizeof (gpointer));
317 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
323 * Obtain information about a call according to the calling convention.
324 * For x86 ELF, see the "System V Application Binary Interface Intel386
325 * Architecture Processor Supplment, Fourth Edition" document for more
327 * For x86 win32, see ???.
330 get_call_info_internal (CallInfo *cinfo, MonoMethodSignature *sig)
332 guint32 i, gr, fr, pstart;
333 const guint32 *param_regs;
335 int n = sig->hasthis + sig->param_count;
336 guint32 stack_size = 0;
337 gboolean is_pinvoke = sig->pinvoke;
343 param_regs = callconv_param_regs(sig);
347 ret_type = mini_get_underlying_type (sig->ret);
348 switch (ret_type->type) {
358 case MONO_TYPE_FNPTR:
359 case MONO_TYPE_CLASS:
360 case MONO_TYPE_OBJECT:
361 case MONO_TYPE_SZARRAY:
362 case MONO_TYPE_ARRAY:
363 case MONO_TYPE_STRING:
364 cinfo->ret.storage = ArgInIReg;
365 cinfo->ret.reg = X86_EAX;
369 cinfo->ret.storage = ArgInIReg;
370 cinfo->ret.reg = X86_EAX;
371 cinfo->ret.is_pair = TRUE;
374 cinfo->ret.storage = ArgOnFloatFpStack;
377 cinfo->ret.storage = ArgOnDoubleFpStack;
379 case MONO_TYPE_GENERICINST:
380 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
381 cinfo->ret.storage = ArgInIReg;
382 cinfo->ret.reg = X86_EAX;
385 if (mini_is_gsharedvt_type (ret_type)) {
386 cinfo->ret.storage = ArgOnStack;
387 cinfo->vtype_retaddr = TRUE;
391 case MONO_TYPE_VALUETYPE:
392 case MONO_TYPE_TYPEDBYREF: {
393 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
395 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
396 if (cinfo->ret.storage == ArgOnStack) {
397 cinfo->vtype_retaddr = TRUE;
398 /* The caller passes the address where the value is stored */
404 g_assert (mini_is_gsharedvt_type (ret_type));
405 cinfo->ret.storage = ArgOnStack;
406 cinfo->vtype_retaddr = TRUE;
409 cinfo->ret.storage = ArgNone;
412 g_error ("Can't handle as return value 0x%x", ret_type->type);
418 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
419 * the first argument, allowing 'this' to be always passed in the first arg reg.
420 * Also do this if the first argument is a reference type, since virtual calls
421 * are sometimes made using calli without sig->hasthis set, like in the delegate
424 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
426 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
428 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
431 cinfo->vret_arg_offset = stack_size;
432 add_general (&gr, NULL, &stack_size, &cinfo->ret);
433 cinfo->vret_arg_index = 1;
437 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
439 if (cinfo->vtype_retaddr)
440 add_general (&gr, NULL, &stack_size, &cinfo->ret);
443 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
444 fr = FLOAT_PARAM_REGS;
446 /* Emit the signature cookie just before the implicit arguments */
447 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
450 for (i = pstart; i < sig->param_count; ++i) {
451 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
454 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
455 /* We allways pass the sig cookie on the stack for simplicity */
457 * Prevent implicit arguments + the sig cookie from being passed
460 fr = FLOAT_PARAM_REGS;
462 /* Emit the signature cookie just before the implicit arguments */
463 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
466 if (sig->params [i]->byref) {
467 add_general (&gr, param_regs, &stack_size, ainfo);
470 ptype = mini_get_underlying_type (sig->params [i]);
471 switch (ptype->type) {
474 add_general (&gr, param_regs, &stack_size, ainfo);
478 add_general (&gr, param_regs, &stack_size, ainfo);
482 add_general (&gr, param_regs, &stack_size, ainfo);
487 case MONO_TYPE_FNPTR:
488 case MONO_TYPE_CLASS:
489 case MONO_TYPE_OBJECT:
490 case MONO_TYPE_STRING:
491 case MONO_TYPE_SZARRAY:
492 case MONO_TYPE_ARRAY:
493 add_general (&gr, param_regs, &stack_size, ainfo);
495 case MONO_TYPE_GENERICINST:
496 if (!mono_type_generic_inst_is_valuetype (ptype)) {
497 add_general (&gr, param_regs, &stack_size, ainfo);
500 if (mini_is_gsharedvt_type (ptype)) {
501 /* gsharedvt arguments are passed by ref */
502 add_general (&gr, param_regs, &stack_size, ainfo);
503 g_assert (ainfo->storage == ArgOnStack);
504 ainfo->storage = ArgGSharedVt;
508 case MONO_TYPE_VALUETYPE:
509 case MONO_TYPE_TYPEDBYREF:
510 add_valuetype (sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
514 add_general_pair (&gr, param_regs, &stack_size, ainfo);
517 add_float (&fr, &stack_size, ainfo, FALSE);
520 add_float (&fr, &stack_size, ainfo, TRUE);
524 /* gsharedvt arguments are passed by ref */
525 g_assert (mini_is_gsharedvt_type (ptype));
526 add_general (&gr, param_regs, &stack_size, ainfo);
527 g_assert (ainfo->storage == ArgOnStack);
528 ainfo->storage = ArgGSharedVt;
531 g_error ("unexpected type 0x%x", ptype->type);
532 g_assert_not_reached ();
536 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
537 fr = FLOAT_PARAM_REGS;
539 /* Emit the signature cookie just before the implicit arguments */
540 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
543 if (cinfo->vtype_retaddr) {
544 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
545 cinfo->callee_stack_pop = 4;
546 } else if (CALLCONV_IS_STDCALL (sig) && sig->pinvoke) {
547 /* Have to compensate for the stack space popped by the native callee */
548 cinfo->callee_stack_pop = stack_size;
551 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
552 cinfo->need_stack_align = TRUE;
553 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
554 stack_size += cinfo->stack_align_amount;
557 cinfo->stack_usage = stack_size;
558 cinfo->reg_usage = gr;
559 cinfo->freg_usage = fr;
564 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
566 int n = sig->hasthis + sig->param_count;
570 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
572 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
574 return get_call_info_internal (cinfo, sig);
578 * mono_arch_get_argument_info:
579 * @csig: a method signature
580 * @param_count: the number of parameters to consider
581 * @arg_info: an array to store the result infos
583 * Gathers information on parameters such as size, alignment and
584 * padding. arg_info should be large enought to hold param_count + 1 entries.
586 * Returns the size of the argument area on the stack.
587 * This should be signal safe, since it is called from
588 * mono_arch_unwind_frame ().
589 * FIXME: The metadata calls might not be signal safe.
592 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
594 int len, k, args_size = 0;
600 /* Avoid g_malloc as it is not signal safe */
601 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
602 cinfo = (CallInfo*)g_newa (guint8*, len);
603 memset (cinfo, 0, len);
605 cinfo = get_call_info_internal (cinfo, csig);
607 arg_info [0].offset = offset;
609 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
610 args_size += sizeof (gpointer);
615 args_size += sizeof (gpointer);
619 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
620 /* Emitted after this */
621 args_size += sizeof (gpointer);
625 arg_info [0].size = args_size;
627 for (k = 0; k < param_count; k++) {
628 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
630 /* ignore alignment for now */
633 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
634 arg_info [k].pad = pad;
636 arg_info [k + 1].pad = 0;
637 arg_info [k + 1].size = size;
639 arg_info [k + 1].offset = offset;
642 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
643 /* Emitted after the first arg */
644 args_size += sizeof (gpointer);
649 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
650 align = MONO_ARCH_FRAME_ALIGNMENT;
653 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
654 arg_info [k].pad = pad;
660 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
662 MonoType *callee_ret;
666 if (cfg->compile_aot && !cfg->full_aot)
667 /* OP_TAILCALL doesn't work with AOT */
670 c1 = get_call_info (NULL, caller_sig);
671 c2 = get_call_info (NULL, callee_sig);
673 * Tail calls with more callee stack usage than the caller cannot be supported, since
674 * the extra stack space would be left on the stack after the tail call.
676 res = c1->stack_usage >= c2->stack_usage;
677 callee_ret = mini_get_underlying_type (callee_sig->ret);
678 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
679 /* An address on the callee's stack is passed as the first argument */
689 * Initialize the cpu to execute managed code.
692 mono_arch_cpu_init (void)
694 /* spec compliance requires running with double precision */
698 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
699 fpcw &= ~X86_FPCW_PRECC_MASK;
700 fpcw |= X86_FPCW_PREC_DOUBLE;
701 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
702 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
704 _control87 (_PC_53, MCW_PC);
709 * Initialize architecture specific code.
712 mono_arch_init (void)
714 mono_os_mutex_init_recursive (&mini_arch_mutex);
717 bp_trampoline = mini_get_breakpoint_trampoline ();
719 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
720 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
721 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
722 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
727 * Cleanup architecture specific code.
730 mono_arch_cleanup (void)
732 mono_os_mutex_destroy (&mini_arch_mutex);
736 * This function returns the optimizations supported on this cpu.
739 mono_arch_cpu_optimizations (guint32 *exclude_mask)
741 #if !defined(__native_client__)
746 if (mono_hwcap_x86_has_cmov) {
747 opts |= MONO_OPT_CMOV;
749 if (mono_hwcap_x86_has_fcmov)
750 opts |= MONO_OPT_FCMOV;
752 *exclude_mask |= MONO_OPT_FCMOV;
754 *exclude_mask |= MONO_OPT_CMOV;
757 if (mono_hwcap_x86_has_sse2)
758 opts |= MONO_OPT_SSE2;
760 *exclude_mask |= MONO_OPT_SSE2;
762 #ifdef MONO_ARCH_SIMD_INTRINSICS
763 /*SIMD intrinsics require at least SSE2.*/
764 if (!mono_hwcap_x86_has_sse2)
765 *exclude_mask |= MONO_OPT_SIMD;
770 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
775 * This function test for all SSE functions supported.
777 * Returns a bitmask corresponding to all supported versions.
781 mono_arch_cpu_enumerate_simd_versions (void)
783 guint32 sse_opts = 0;
785 if (mono_hwcap_x86_has_sse1)
786 sse_opts |= SIMD_VERSION_SSE1;
788 if (mono_hwcap_x86_has_sse2)
789 sse_opts |= SIMD_VERSION_SSE2;
791 if (mono_hwcap_x86_has_sse3)
792 sse_opts |= SIMD_VERSION_SSE3;
794 if (mono_hwcap_x86_has_ssse3)
795 sse_opts |= SIMD_VERSION_SSSE3;
797 if (mono_hwcap_x86_has_sse41)
798 sse_opts |= SIMD_VERSION_SSE41;
800 if (mono_hwcap_x86_has_sse42)
801 sse_opts |= SIMD_VERSION_SSE42;
803 if (mono_hwcap_x86_has_sse4a)
804 sse_opts |= SIMD_VERSION_SSE4a;
810 * Determine whenever the trap whose info is in SIGINFO is caused by
814 mono_arch_is_int_overflow (void *sigctx, void *info)
819 mono_sigctx_to_monoctx (sigctx, &ctx);
821 ip = (guint8*)ctx.eip;
823 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
827 switch (x86_modrm_rm (ip [1])) {
847 g_assert_not_reached ();
859 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
864 for (i = 0; i < cfg->num_varinfo; i++) {
865 MonoInst *ins = cfg->varinfo [i];
866 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
869 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
872 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
873 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
876 /* we dont allocate I1 to registers because there is no simply way to sign extend
877 * 8bit quantities in caller saved registers on x86 */
878 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
879 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
880 g_assert (i == vmv->idx);
881 vars = g_list_prepend (vars, vmv);
885 vars = mono_varlist_sort (cfg, vars, 0);
891 mono_arch_get_global_int_regs (MonoCompile *cfg)
895 /* we can use 3 registers for global allocation */
896 regs = g_list_prepend (regs, (gpointer)X86_EBX);
897 regs = g_list_prepend (regs, (gpointer)X86_ESI);
898 regs = g_list_prepend (regs, (gpointer)X86_EDI);
904 * mono_arch_regalloc_cost:
906 * Return the cost, in number of memory references, of the action of
907 * allocating the variable VMV into a register during global register
911 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
913 MonoInst *ins = cfg->varinfo [vmv->idx];
915 if (cfg->method->save_lmf)
916 /* The register is already saved */
917 return (ins->opcode == OP_ARG) ? 1 : 0;
919 /* push+pop+possible load if it is an argument */
920 return (ins->opcode == OP_ARG) ? 3 : 2;
924 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
926 static int inited = FALSE;
927 static int count = 0;
929 if (cfg->arch.need_stack_frame_inited) {
930 g_assert (cfg->arch.need_stack_frame == flag);
934 cfg->arch.need_stack_frame = flag;
935 cfg->arch.need_stack_frame_inited = TRUE;
941 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
946 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
950 needs_stack_frame (MonoCompile *cfg)
952 MonoMethodSignature *sig;
953 MonoMethodHeader *header;
954 gboolean result = FALSE;
956 #if defined(__APPLE__)
957 /*OSX requires stack frame code to have the correct alignment. */
961 if (cfg->arch.need_stack_frame_inited)
962 return cfg->arch.need_stack_frame;
964 header = cfg->header;
965 sig = mono_method_signature (cfg->method);
967 if (cfg->disable_omit_fp)
969 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
971 else if (cfg->method->save_lmf)
973 else if (cfg->stack_offset)
975 else if (cfg->param_area)
977 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
979 else if (header->num_clauses)
981 else if (sig->param_count + sig->hasthis)
983 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
985 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
986 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
989 set_needs_stack_frame (cfg, result);
991 return cfg->arch.need_stack_frame;
995 * Set var information according to the calling convention. X86 version.
996 * The locals var stuff should most likely be split in another method.
999 mono_arch_allocate_vars (MonoCompile *cfg)
1001 MonoMethodSignature *sig;
1002 MonoMethodHeader *header;
1004 guint32 locals_stack_size, locals_stack_align;
1009 header = cfg->header;
1010 sig = mono_method_signature (cfg->method);
1012 cinfo = get_call_info (cfg->mempool, sig);
1014 cfg->frame_reg = X86_EBP;
1017 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1018 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1019 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1022 /* Reserve space to save LMF and caller saved registers */
1024 if (cfg->method->save_lmf) {
1025 /* The LMF var is allocated normally */
1027 if (cfg->used_int_regs & (1 << X86_EBX)) {
1031 if (cfg->used_int_regs & (1 << X86_EDI)) {
1035 if (cfg->used_int_regs & (1 << X86_ESI)) {
1040 switch (cinfo->ret.storage) {
1041 case ArgValuetypeInReg:
1042 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1044 cfg->ret->opcode = OP_REGOFFSET;
1045 cfg->ret->inst_basereg = X86_EBP;
1046 cfg->ret->inst_offset = - offset;
1052 /* Allocate locals */
1053 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1054 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1055 char *mname = mono_method_full_name (cfg->method, TRUE);
1056 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1060 if (locals_stack_align) {
1061 int prev_offset = offset;
1063 offset += (locals_stack_align - 1);
1064 offset &= ~(locals_stack_align - 1);
1066 while (prev_offset < offset) {
1068 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1071 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1072 cfg->locals_max_stack_offset = - offset;
1074 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1075 * have locals larger than 8 bytes we need to make sure that
1076 * they have the appropriate offset.
1078 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1079 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1080 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1081 if (offsets [i] != -1) {
1082 MonoInst *inst = cfg->varinfo [i];
1083 inst->opcode = OP_REGOFFSET;
1084 inst->inst_basereg = X86_EBP;
1085 inst->inst_offset = - (offset + offsets [i]);
1086 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1089 offset += locals_stack_size;
1093 * Allocate arguments+return value
1096 switch (cinfo->ret.storage) {
1098 if (cfg->vret_addr) {
1100 * In the new IR, the cfg->vret_addr variable represents the
1101 * vtype return value.
1103 cfg->vret_addr->opcode = OP_REGOFFSET;
1104 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1105 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1106 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1107 printf ("vret_addr =");
1108 mono_print_ins (cfg->vret_addr);
1111 cfg->ret->opcode = OP_REGOFFSET;
1112 cfg->ret->inst_basereg = X86_EBP;
1113 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1116 case ArgValuetypeInReg:
1119 cfg->ret->opcode = OP_REGVAR;
1120 cfg->ret->inst_c0 = cinfo->ret.reg;
1121 cfg->ret->dreg = cinfo->ret.reg;
1124 case ArgOnFloatFpStack:
1125 case ArgOnDoubleFpStack:
1128 g_assert_not_reached ();
1131 if (sig->call_convention == MONO_CALL_VARARG) {
1132 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1133 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1136 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1137 ArgInfo *ainfo = &cinfo->args [i];
1138 inst = cfg->args [i];
1139 if (inst->opcode != OP_REGVAR) {
1140 inst->opcode = OP_REGOFFSET;
1141 inst->inst_basereg = X86_EBP;
1143 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1146 cfg->stack_offset = offset;
1150 mono_arch_create_vars (MonoCompile *cfg)
1153 MonoMethodSignature *sig;
1156 sig = mono_method_signature (cfg->method);
1158 cinfo = get_call_info (cfg->mempool, sig);
1159 sig_ret = mini_get_underlying_type (sig->ret);
1161 if (cinfo->ret.storage == ArgValuetypeInReg)
1162 cfg->ret_var_is_local = TRUE;
1163 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (sig_ret))) {
1164 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1167 if (cfg->gen_sdb_seq_points) {
1170 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1171 ins->flags |= MONO_INST_VOLATILE;
1172 cfg->arch.ss_tramp_var = ins;
1174 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1175 ins->flags |= MONO_INST_VOLATILE;
1176 cfg->arch.bp_tramp_var = ins;
1179 if (cfg->method->save_lmf) {
1180 cfg->create_lmf_var = TRUE;
1183 cfg->lmf_ir_mono_lmf = TRUE;
1187 cfg->arch_eh_jit_info = 1;
1191 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1192 * so we try to do it just once when we have multiple fp arguments in a row.
1193 * We don't use this mechanism generally because for int arguments the generated code
1194 * is slightly bigger and new generation cpus optimize away the dependency chains
1195 * created by push instructions on the esp value.
1196 * fp_arg_setup is the first argument in the execution sequence where the esp register
1199 static G_GNUC_UNUSED int
1200 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1205 for (; start_arg < sig->param_count; ++start_arg) {
1206 t = mini_get_underlying_type (sig->params [start_arg]);
1207 if (!t->byref && t->type == MONO_TYPE_R8) {
1208 fp_space += sizeof (double);
1209 *fp_arg_setup = start_arg;
1218 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1220 MonoMethodSignature *tmp_sig;
1224 * mono_ArgIterator_Setup assumes the signature cookie is
1225 * passed first and all the arguments which were before it are
1226 * passed on the stack after the signature. So compensate by
1227 * passing a different signature.
1229 tmp_sig = mono_metadata_signature_dup (call->signature);
1230 tmp_sig->param_count -= call->signature->sentinelpos;
1231 tmp_sig->sentinelpos = 0;
1232 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1234 if (cfg->compile_aot) {
1235 sig_reg = mono_alloc_ireg (cfg);
1236 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1237 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1239 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1245 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1250 LLVMCallInfo *linfo;
1251 MonoType *t, *sig_ret;
1253 n = sig->param_count + sig->hasthis;
1255 cinfo = get_call_info (cfg->mempool, sig);
1258 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1261 * LLVM always uses the native ABI while we use our own ABI, the
1262 * only difference is the handling of vtypes:
1263 * - we only pass/receive them in registers in some cases, and only
1264 * in 1 or 2 integer registers.
1266 if (cinfo->ret.storage == ArgValuetypeInReg) {
1268 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1269 cfg->disable_llvm = TRUE;
1273 cfg->exception_message = g_strdup ("vtype ret in call");
1274 cfg->disable_llvm = TRUE;
1276 linfo->ret.storage = LLVMArgVtypeInReg;
1277 for (j = 0; j < 2; ++j)
1278 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1282 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage == ArgInIReg) {
1283 /* Vtype returned using a hidden argument */
1284 linfo->ret.storage = LLVMArgVtypeRetAddr;
1285 linfo->vret_arg_index = cinfo->vret_arg_index;
1288 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage != ArgInIReg) {
1290 cfg->exception_message = g_strdup ("vtype ret in call");
1291 cfg->disable_llvm = TRUE;
1294 for (i = 0; i < n; ++i) {
1295 ainfo = cinfo->args + i;
1297 if (i >= sig->hasthis)
1298 t = sig->params [i - sig->hasthis];
1300 t = &mono_defaults.int_class->byval_arg;
1302 linfo->args [i].storage = LLVMArgNone;
1304 switch (ainfo->storage) {
1306 linfo->args [i].storage = LLVMArgNormal;
1308 case ArgInDoubleSSEReg:
1309 case ArgInFloatSSEReg:
1310 linfo->args [i].storage = LLVMArgNormal;
1313 if (mini_type_is_vtype (t)) {
1314 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1315 /* LLVM seems to allocate argument space for empty structures too */
1316 linfo->args [i].storage = LLVMArgNone;
1318 linfo->args [i].storage = LLVMArgVtypeByVal;
1320 linfo->args [i].storage = LLVMArgNormal;
1323 case ArgValuetypeInReg:
1325 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1326 cfg->disable_llvm = TRUE;
1330 cfg->exception_message = g_strdup ("vtype arg");
1331 cfg->disable_llvm = TRUE;
1333 linfo->args [i].storage = LLVMArgVtypeInReg;
1334 for (j = 0; j < 2; ++j)
1335 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1339 linfo->args [i].storage = LLVMArgGSharedVt;
1342 cfg->exception_message = g_strdup ("ainfo->storage");
1343 cfg->disable_llvm = TRUE;
1353 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1355 if (cfg->compute_gc_maps) {
1358 /* Needs checking if the feature will be enabled again */
1359 g_assert_not_reached ();
1361 /* On x86, the offsets are from the sp value before the start of the call sequence */
1363 t = &mono_defaults.int_class->byval_arg;
1364 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1369 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1373 MonoMethodSignature *sig;
1376 int sentinelpos = 0, sp_offset = 0;
1378 sig = call->signature;
1379 n = sig->param_count + sig->hasthis;
1380 sig_ret = mini_get_underlying_type (sig->ret);
1382 cinfo = get_call_info (cfg->mempool, sig);
1383 call->call_info = cinfo;
1385 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1386 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1388 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1389 if (cinfo->ret.storage == ArgValuetypeInReg) {
1391 * Tell the JIT to use a more efficient calling convention: call using
1392 * OP_CALL, compute the result location after the call, and save the
1395 call->vret_in_reg = TRUE;
1396 #if defined(__APPLE__)
1397 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1398 call->vret_in_reg_fp = TRUE;
1401 NULLIFY_INS (call->vret_var);
1405 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1407 /* Handle the case where there are no implicit arguments */
1408 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1409 emit_sig_cookie (cfg, call, cinfo);
1410 sp_offset = cinfo->sig_cookie.offset;
1411 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1414 /* Arguments are pushed in the reverse order */
1415 for (i = n - 1; i >= 0; i --) {
1416 ArgInfo *ainfo = cinfo->args + i;
1417 MonoType *orig_type, *t;
1420 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1423 /* Push the vret arg before the first argument */
1424 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1425 vtarg->type = STACK_MP;
1426 vtarg->inst_destbasereg = X86_ESP;
1427 vtarg->sreg1 = call->vret_var->dreg;
1428 vtarg->inst_offset = cinfo->ret.offset;
1429 MONO_ADD_INS (cfg->cbb, vtarg);
1430 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1433 if (i >= sig->hasthis)
1434 t = sig->params [i - sig->hasthis];
1436 t = &mono_defaults.int_class->byval_arg;
1438 t = mini_get_underlying_type (t);
1440 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1442 in = call->args [i];
1443 arg->cil_code = in->cil_code;
1444 arg->sreg1 = in->dreg;
1445 arg->type = in->type;
1447 g_assert (in->dreg != -1);
1449 if (ainfo->storage == ArgGSharedVt) {
1450 arg->opcode = OP_OUTARG_VT;
1451 arg->sreg1 = in->dreg;
1452 arg->klass = in->klass;
1453 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1454 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1456 MONO_ADD_INS (cfg->cbb, arg);
1457 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1461 g_assert (in->klass);
1463 if (t->type == MONO_TYPE_TYPEDBYREF) {
1464 size = sizeof (MonoTypedRef);
1465 align = sizeof (gpointer);
1468 size = mini_type_stack_size_full (&in->klass->byval_arg, &align, sig->pinvoke);
1472 arg->opcode = OP_OUTARG_VT;
1473 arg->sreg1 = in->dreg;
1474 arg->klass = in->klass;
1475 arg->backend.size = size;
1476 arg->inst_p0 = call;
1477 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1478 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1480 MONO_ADD_INS (cfg->cbb, arg);
1481 if (ainfo->storage != ArgValuetypeInReg) {
1482 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1486 switch (ainfo->storage) {
1489 if (t->type == MONO_TYPE_R4) {
1490 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1492 } else if (t->type == MONO_TYPE_R8) {
1493 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1495 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1496 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, MONO_LVREG_MS (in->dreg));
1497 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, MONO_LVREG_LS (in->dreg));
1500 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1504 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1509 arg->opcode = OP_MOVE;
1510 arg->dreg = ainfo->reg;
1511 MONO_ADD_INS (cfg->cbb, arg);
1515 g_assert_not_reached ();
1518 if (cfg->compute_gc_maps) {
1520 /* FIXME: The == STACK_OBJ check might be fragile ? */
1521 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1523 if (call->need_unbox_trampoline)
1524 /* The unbox trampoline transforms this into a managed pointer */
1525 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.int_class->this_arg);
1527 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.object_class->byval_arg);
1529 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1533 for (j = 0; j < argsize; j += 4)
1534 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1539 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1540 /* Emit the signature cookie just before the implicit arguments */
1541 emit_sig_cookie (cfg, call, cinfo);
1542 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1546 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1549 if (cinfo->ret.storage == ArgValuetypeInReg) {
1552 else if (cinfo->ret.storage == ArgInIReg) {
1554 /* The return address is passed in a register */
1555 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1556 vtarg->sreg1 = call->inst.dreg;
1557 vtarg->dreg = mono_alloc_ireg (cfg);
1558 MONO_ADD_INS (cfg->cbb, vtarg);
1560 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1561 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1562 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1563 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1567 call->stack_usage = cinfo->stack_usage;
1568 call->stack_align_amount = cinfo->stack_align_amount;
1572 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1574 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1575 ArgInfo *ainfo = ins->inst_p1;
1576 int size = ins->backend.size;
1578 if (ainfo->storage == ArgValuetypeInReg) {
1579 int dreg = mono_alloc_ireg (cfg);
1582 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1585 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1588 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1592 g_assert_not_reached ();
1594 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1597 if (cfg->gsharedvt && mini_is_gsharedvt_klass (ins->klass)) {
1599 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1600 } else if (size <= 4) {
1601 int dreg = mono_alloc_ireg (cfg);
1602 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1603 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1604 } else if (size <= 20) {
1605 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1607 // FIXME: Code growth
1608 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1614 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1616 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
1619 if (ret->type == MONO_TYPE_R4) {
1620 if (COMPILE_LLVM (cfg))
1621 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1624 } else if (ret->type == MONO_TYPE_R8) {
1625 if (COMPILE_LLVM (cfg))
1626 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1629 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1630 if (COMPILE_LLVM (cfg))
1631 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1633 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, MONO_LVREG_LS (val->dreg));
1634 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, MONO_LVREG_MS (val->dreg));
1640 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1644 * Allow tracing to work with this interface (with an optional argument)
1647 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1651 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1652 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1654 /* if some args are passed in registers, we need to save them here */
1655 x86_push_reg (code, X86_EBP);
1657 if (cfg->compile_aot) {
1658 x86_push_imm (code, cfg->method);
1659 x86_mov_reg_imm (code, X86_EAX, func);
1660 x86_call_reg (code, X86_EAX);
1662 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1663 x86_push_imm (code, cfg->method);
1664 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1665 x86_call_code (code, 0);
1667 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1681 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1684 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1685 MonoMethod *method = cfg->method;
1686 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
1688 switch (ret_type->type) {
1689 case MONO_TYPE_VOID:
1690 /* special case string .ctor icall */
1691 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1692 save_mode = SAVE_EAX;
1693 stack_usage = enable_arguments ? 8 : 4;
1695 save_mode = SAVE_NONE;
1699 save_mode = SAVE_EAX_EDX;
1700 stack_usage = enable_arguments ? 16 : 8;
1704 save_mode = SAVE_FP;
1705 stack_usage = enable_arguments ? 16 : 8;
1707 case MONO_TYPE_GENERICINST:
1708 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1709 save_mode = SAVE_EAX;
1710 stack_usage = enable_arguments ? 8 : 4;
1714 case MONO_TYPE_VALUETYPE:
1715 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1716 save_mode = SAVE_STRUCT;
1717 stack_usage = enable_arguments ? 4 : 0;
1720 save_mode = SAVE_EAX;
1721 stack_usage = enable_arguments ? 8 : 4;
1725 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1727 switch (save_mode) {
1729 x86_push_reg (code, X86_EDX);
1730 x86_push_reg (code, X86_EAX);
1731 if (enable_arguments) {
1732 x86_push_reg (code, X86_EDX);
1733 x86_push_reg (code, X86_EAX);
1738 x86_push_reg (code, X86_EAX);
1739 if (enable_arguments) {
1740 x86_push_reg (code, X86_EAX);
1745 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1746 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1747 if (enable_arguments) {
1748 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1749 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1754 if (enable_arguments) {
1755 x86_push_membase (code, X86_EBP, 8);
1764 if (cfg->compile_aot) {
1765 x86_push_imm (code, method);
1766 x86_mov_reg_imm (code, X86_EAX, func);
1767 x86_call_reg (code, X86_EAX);
1769 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1770 x86_push_imm (code, method);
1771 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1772 x86_call_code (code, 0);
1775 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1777 switch (save_mode) {
1779 x86_pop_reg (code, X86_EAX);
1780 x86_pop_reg (code, X86_EDX);
1783 x86_pop_reg (code, X86_EAX);
1786 x86_fld_membase (code, X86_ESP, 0, TRUE);
1787 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1794 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1799 #define EMIT_COND_BRANCH(ins,cond,sign) \
1800 if (ins->inst_true_bb->native_offset) { \
1801 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1803 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1804 if ((cfg->opt & MONO_OPT_BRANCH) && \
1805 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1806 x86_branch8 (code, cond, 0, sign); \
1808 x86_branch32 (code, cond, 0, sign); \
1812 * Emit an exception if condition is fail and
1813 * if possible do a directly branch to target
1815 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1817 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1818 if (tins == NULL) { \
1819 mono_add_patch_info (cfg, code - cfg->native_code, \
1820 MONO_PATCH_INFO_EXC, exc_name); \
1821 x86_branch32 (code, cond, 0, signed); \
1823 EMIT_COND_BRANCH (tins, cond, signed); \
1827 #define EMIT_FPCOMPARE(code) do { \
1828 x86_fcompp (code); \
1829 x86_fnstsw (code); \
1834 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1836 gboolean needs_paddings = TRUE;
1838 MonoJumpInfo *jinfo = NULL;
1840 if (cfg->abs_patches) {
1841 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1842 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1843 needs_paddings = FALSE;
1846 if (cfg->compile_aot)
1847 needs_paddings = FALSE;
1848 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1849 This is required for code patching to be safe on SMP machines.
1851 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1852 #ifndef __native_client_codegen__
1853 if (needs_paddings && pad_size)
1854 x86_padding (code, 4 - pad_size);
1857 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1858 x86_call_code (code, 0);
1863 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1866 * mono_peephole_pass_1:
1868 * Perform peephole opts which should/can be performed before local regalloc
1871 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1875 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1876 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1878 switch (ins->opcode) {
1881 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1883 * X86_LEA is like ADD, but doesn't have the
1884 * sreg1==dreg restriction.
1886 ins->opcode = OP_X86_LEA_MEMBASE;
1887 ins->inst_basereg = ins->sreg1;
1888 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1889 ins->opcode = OP_X86_INC_REG;
1893 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1894 ins->opcode = OP_X86_LEA_MEMBASE;
1895 ins->inst_basereg = ins->sreg1;
1896 ins->inst_imm = -ins->inst_imm;
1897 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1898 ins->opcode = OP_X86_DEC_REG;
1900 case OP_COMPARE_IMM:
1901 case OP_ICOMPARE_IMM:
1902 /* OP_COMPARE_IMM (reg, 0)
1904 * OP_X86_TEST_NULL (reg)
1907 ins->opcode = OP_X86_TEST_NULL;
1909 case OP_X86_COMPARE_MEMBASE_IMM:
1911 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1912 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1914 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1915 * OP_COMPARE_IMM reg, imm
1917 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1919 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1920 ins->inst_basereg == last_ins->inst_destbasereg &&
1921 ins->inst_offset == last_ins->inst_offset) {
1922 ins->opcode = OP_COMPARE_IMM;
1923 ins->sreg1 = last_ins->sreg1;
1925 /* check if we can remove cmp reg,0 with test null */
1927 ins->opcode = OP_X86_TEST_NULL;
1931 case OP_X86_PUSH_MEMBASE:
1932 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1933 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1934 ins->inst_basereg == last_ins->inst_destbasereg &&
1935 ins->inst_offset == last_ins->inst_offset) {
1936 ins->opcode = OP_X86_PUSH;
1937 ins->sreg1 = last_ins->sreg1;
1942 mono_peephole_ins (bb, ins);
1947 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1951 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1952 switch (ins->opcode) {
1954 /* reg = 0 -> XOR (reg, reg) */
1955 /* XOR sets cflags on x86, so we cant do it always */
1956 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1959 ins->opcode = OP_IXOR;
1960 ins->sreg1 = ins->dreg;
1961 ins->sreg2 = ins->dreg;
1964 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1965 * since it takes 3 bytes instead of 7.
1967 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
1968 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1969 ins2->opcode = OP_STORE_MEMBASE_REG;
1970 ins2->sreg1 = ins->dreg;
1972 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1973 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1974 ins2->sreg1 = ins->dreg;
1976 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1977 /* Continue iteration */
1986 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1987 ins->opcode = OP_X86_INC_REG;
1991 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1992 ins->opcode = OP_X86_DEC_REG;
1996 mono_peephole_ins (bb, ins);
2001 * mono_arch_lowering_pass:
2003 * Converts complex opcodes into simpler ones so that each IR instruction
2004 * corresponds to one machine instruction.
2007 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2009 MonoInst *ins, *next;
2012 * FIXME: Need to add more instructions, but the current machine
2013 * description can't model some parts of the composite instructions like
2016 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2017 switch (ins->opcode) {
2020 case OP_IDIV_UN_IMM:
2021 case OP_IREM_UN_IMM:
2023 * Keep the cases where we could generated optimized code, otherwise convert
2024 * to the non-imm variant.
2026 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2028 mono_decompose_op_imm (cfg, bb, ins);
2035 bb->max_vreg = cfg->next_vreg;
2039 branch_cc_table [] = {
2040 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2041 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2042 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2045 /* Maps CMP_... constants to X86_CC_... constants */
2048 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2049 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2053 cc_signed_table [] = {
2054 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2055 FALSE, FALSE, FALSE, FALSE
2058 static unsigned char*
2059 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2061 #define XMM_TEMP_REG 0
2062 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2063 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2064 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2065 /* optimize by assigning a local var for this use so we avoid
2066 * the stack manipulations */
2067 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2068 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2069 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2070 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2071 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2073 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2075 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2078 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2079 x86_fnstcw_membase(code, X86_ESP, 0);
2080 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2081 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2082 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2083 x86_fldcw_membase (code, X86_ESP, 2);
2085 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2086 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2087 x86_pop_reg (code, dreg);
2088 /* FIXME: need the high register
2089 * x86_pop_reg (code, dreg_high);
2092 x86_push_reg (code, X86_EAX); // SP = SP - 4
2093 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2094 x86_pop_reg (code, dreg);
2096 x86_fldcw_membase (code, X86_ESP, 0);
2097 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2100 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2102 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2106 static unsigned char*
2107 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2109 int sreg = tree->sreg1;
2110 int need_touch = FALSE;
2112 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2121 * If requested stack size is larger than one page,
2122 * perform stack-touch operation
2125 * Generate stack probe code.
2126 * Under Windows, it is necessary to allocate one page at a time,
2127 * "touching" stack after each successful sub-allocation. This is
2128 * because of the way stack growth is implemented - there is a
2129 * guard page before the lowest stack page that is currently commited.
2130 * Stack normally grows sequentially so OS traps access to the
2131 * guard page and commits more pages when needed.
2133 x86_test_reg_imm (code, sreg, ~0xFFF);
2134 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2136 br[2] = code; /* loop */
2137 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2138 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2141 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2142 * that follows only initializes the last part of the area.
2144 /* Same as the init code below with size==0x1000 */
2145 if (tree->flags & MONO_INST_INIT) {
2146 x86_push_reg (code, X86_EAX);
2147 x86_push_reg (code, X86_ECX);
2148 x86_push_reg (code, X86_EDI);
2149 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2150 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2151 if (cfg->param_area)
2152 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2154 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2156 x86_prefix (code, X86_REP_PREFIX);
2158 x86_pop_reg (code, X86_EDI);
2159 x86_pop_reg (code, X86_ECX);
2160 x86_pop_reg (code, X86_EAX);
2163 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2164 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2165 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2166 x86_patch (br[3], br[2]);
2167 x86_test_reg_reg (code, sreg, sreg);
2168 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2169 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2171 br[1] = code; x86_jump8 (code, 0);
2173 x86_patch (br[0], code);
2174 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2175 x86_patch (br[1], code);
2176 x86_patch (br[4], code);
2179 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2181 if (tree->flags & MONO_INST_INIT) {
2183 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2184 x86_push_reg (code, X86_EAX);
2187 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2188 x86_push_reg (code, X86_ECX);
2191 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2192 x86_push_reg (code, X86_EDI);
2196 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2197 if (sreg != X86_ECX)
2198 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2199 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2201 if (cfg->param_area)
2202 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2204 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2206 x86_prefix (code, X86_REP_PREFIX);
2209 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2210 x86_pop_reg (code, X86_EDI);
2211 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2212 x86_pop_reg (code, X86_ECX);
2213 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2214 x86_pop_reg (code, X86_EAX);
2221 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2223 /* Move return value to the target register */
2224 switch (ins->opcode) {
2227 case OP_CALL_MEMBASE:
2228 if (ins->dreg != X86_EAX)
2229 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2239 static int tls_gs_offset;
2243 mono_x86_have_tls_get (void)
2246 static gboolean have_tls_get = FALSE;
2247 static gboolean inited = FALSE;
2250 return have_tls_get;
2252 #ifdef MONO_HAVE_FAST_TLS
2255 ins = (guint32*)pthread_getspecific;
2257 * We're looking for these two instructions:
2259 * mov 0x4(%esp),%eax
2260 * mov %gs:[offset](,%eax,4),%eax
2262 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2263 tls_gs_offset = ins [2];
2268 return have_tls_get;
2269 #elif defined(TARGET_ANDROID)
2277 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2279 #if defined(__APPLE__)
2280 x86_prefix (code, X86_GS_PREFIX);
2281 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2282 #elif defined(TARGET_WIN32)
2283 g_assert_not_reached ();
2285 x86_prefix (code, X86_GS_PREFIX);
2286 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2292 * mono_x86_emit_tls_get:
2293 * @code: buffer to store code to
2294 * @dreg: hard register where to place the result
2295 * @tls_offset: offset info
2297 * mono_x86_emit_tls_get emits in @code the native code that puts in
2298 * the dreg register the item in the thread local storage identified
2301 * Returns: a pointer to the end of the stored code
2304 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2306 #if defined(__APPLE__)
2307 x86_prefix (code, X86_GS_PREFIX);
2308 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2309 #elif defined(TARGET_WIN32)
2311 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2312 * Journal and/or a disassembly of the TlsGet () function.
2314 x86_prefix (code, X86_FS_PREFIX);
2315 x86_mov_reg_mem (code, dreg, 0x18, 4);
2316 if (tls_offset < 64) {
2317 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2321 g_assert (tls_offset < 0x440);
2322 /* Load TEB->TlsExpansionSlots */
2323 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2324 x86_test_reg_reg (code, dreg, dreg);
2326 x86_branch (code, X86_CC_EQ, code, TRUE);
2327 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2328 x86_patch (buf [0], code);
2331 if (optimize_for_xen) {
2332 x86_prefix (code, X86_GS_PREFIX);
2333 x86_mov_reg_mem (code, dreg, 0, 4);
2334 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2336 x86_prefix (code, X86_GS_PREFIX);
2337 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2344 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2346 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2347 #if defined(__APPLE__) || defined(__linux__)
2348 if (dreg != offset_reg)
2349 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2350 x86_prefix (code, X86_GS_PREFIX);
2351 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2353 g_assert_not_reached ();
2359 mono_x86_emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2361 return emit_tls_get_reg (code, dreg, offset_reg);
2365 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2367 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2369 g_assert_not_reached ();
2370 #elif defined(__APPLE__) || defined(__linux__)
2371 x86_prefix (code, X86_GS_PREFIX);
2372 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2374 g_assert_not_reached ();
2380 * mono_arch_translate_tls_offset:
2382 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2385 mono_arch_translate_tls_offset (int offset)
2388 return tls_gs_offset + (offset * 4);
2397 * Emit code to initialize an LMF structure at LMF_OFFSET.
2400 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2402 /* save all caller saved regs */
2403 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2404 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2405 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2406 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2407 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2408 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2409 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2411 /* save the current IP */
2412 if (cfg->compile_aot) {
2413 /* This pushes the current ip */
2414 x86_call_imm (code, 0);
2415 x86_pop_reg (code, X86_EAX);
2417 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2418 x86_mov_reg_imm (code, X86_EAX, 0);
2420 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2422 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2423 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2424 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2425 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2426 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2427 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2428 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2429 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2430 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2435 /* benchmark and set based on cpu */
2436 #define LOOP_ALIGNMENT 8
2437 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2441 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2446 guint8 *code = cfg->native_code + cfg->code_len;
2449 if (cfg->opt & MONO_OPT_LOOP) {
2450 int pad, align = LOOP_ALIGNMENT;
2451 /* set alignment depending on cpu */
2452 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2454 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2455 x86_padding (code, pad);
2456 cfg->code_len += pad;
2457 bb->native_offset = cfg->code_len;
2460 #ifdef __native_client_codegen__
2462 /* For Native Client, all indirect call/jump targets must be */
2463 /* 32-byte aligned. Exception handler blocks are jumped to */
2464 /* indirectly as well. */
2465 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2466 (bb->flags & BB_EXCEPTION_HANDLER);
2468 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2469 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2470 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2471 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2472 cfg->code_len += pad;
2473 bb->native_offset = cfg->code_len;
2476 #endif /* __native_client_codegen__ */
2477 if (cfg->verbose_level > 2)
2478 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2480 cpos = bb->max_offset;
2482 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
2483 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2484 g_assert (!cfg->compile_aot);
2487 cov->data [bb->dfn].cil_code = bb->cil_code;
2488 /* this is not thread save, but good enough */
2489 x86_inc_mem (code, &cov->data [bb->dfn].count);
2492 offset = code - cfg->native_code;
2494 mono_debug_open_block (cfg, bb, offset);
2496 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2497 x86_breakpoint (code);
2499 MONO_BB_FOR_EACH_INS (bb, ins) {
2500 offset = code - cfg->native_code;
2502 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2504 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2506 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2507 cfg->code_size *= 2;
2508 cfg->native_code = mono_realloc_native_code(cfg);
2509 code = cfg->native_code + offset;
2510 cfg->stat_code_reallocs++;
2513 if (cfg->debug_info)
2514 mono_debug_record_line_number (cfg, ins, offset);
2516 switch (ins->opcode) {
2518 x86_mul_reg (code, ins->sreg2, TRUE);
2521 x86_mul_reg (code, ins->sreg2, FALSE);
2523 case OP_X86_SETEQ_MEMBASE:
2524 case OP_X86_SETNE_MEMBASE:
2525 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2526 ins->inst_basereg, ins->inst_offset, TRUE);
2528 case OP_STOREI1_MEMBASE_IMM:
2529 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2531 case OP_STOREI2_MEMBASE_IMM:
2532 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2534 case OP_STORE_MEMBASE_IMM:
2535 case OP_STOREI4_MEMBASE_IMM:
2536 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2538 case OP_STOREI1_MEMBASE_REG:
2539 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2541 case OP_STOREI2_MEMBASE_REG:
2542 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2544 case OP_STORE_MEMBASE_REG:
2545 case OP_STOREI4_MEMBASE_REG:
2546 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2548 case OP_STORE_MEM_IMM:
2549 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2552 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2556 /* These are created by the cprop pass so they use inst_imm as the source */
2557 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2560 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2563 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2565 case OP_LOAD_MEMBASE:
2566 case OP_LOADI4_MEMBASE:
2567 case OP_LOADU4_MEMBASE:
2568 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2570 case OP_LOADU1_MEMBASE:
2571 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2573 case OP_LOADI1_MEMBASE:
2574 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2576 case OP_LOADU2_MEMBASE:
2577 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2579 case OP_LOADI2_MEMBASE:
2580 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2582 case OP_ICONV_TO_I1:
2584 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2586 case OP_ICONV_TO_I2:
2588 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2590 case OP_ICONV_TO_U1:
2591 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2593 case OP_ICONV_TO_U2:
2594 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2598 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2600 case OP_COMPARE_IMM:
2601 case OP_ICOMPARE_IMM:
2602 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2604 case OP_X86_COMPARE_MEMBASE_REG:
2605 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2607 case OP_X86_COMPARE_MEMBASE_IMM:
2608 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2610 case OP_X86_COMPARE_MEMBASE8_IMM:
2611 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2613 case OP_X86_COMPARE_REG_MEMBASE:
2614 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2616 case OP_X86_COMPARE_MEM_IMM:
2617 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2619 case OP_X86_TEST_NULL:
2620 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2622 case OP_X86_ADD_MEMBASE_IMM:
2623 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2625 case OP_X86_ADD_REG_MEMBASE:
2626 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2628 case OP_X86_SUB_MEMBASE_IMM:
2629 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2631 case OP_X86_SUB_REG_MEMBASE:
2632 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2634 case OP_X86_AND_MEMBASE_IMM:
2635 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2637 case OP_X86_OR_MEMBASE_IMM:
2638 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2640 case OP_X86_XOR_MEMBASE_IMM:
2641 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2643 case OP_X86_ADD_MEMBASE_REG:
2644 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2646 case OP_X86_SUB_MEMBASE_REG:
2647 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2649 case OP_X86_AND_MEMBASE_REG:
2650 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2652 case OP_X86_OR_MEMBASE_REG:
2653 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2655 case OP_X86_XOR_MEMBASE_REG:
2656 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2658 case OP_X86_INC_MEMBASE:
2659 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2661 case OP_X86_INC_REG:
2662 x86_inc_reg (code, ins->dreg);
2664 case OP_X86_DEC_MEMBASE:
2665 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2667 case OP_X86_DEC_REG:
2668 x86_dec_reg (code, ins->dreg);
2670 case OP_X86_MUL_REG_MEMBASE:
2671 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2673 case OP_X86_AND_REG_MEMBASE:
2674 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2676 case OP_X86_OR_REG_MEMBASE:
2677 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2679 case OP_X86_XOR_REG_MEMBASE:
2680 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2683 x86_breakpoint (code);
2685 case OP_RELAXED_NOP:
2686 x86_prefix (code, X86_REP_PREFIX);
2694 case OP_DUMMY_STORE:
2695 case OP_DUMMY_ICONST:
2696 case OP_DUMMY_R8CONST:
2697 case OP_NOT_REACHED:
2700 case OP_IL_SEQ_POINT:
2701 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2703 case OP_SEQ_POINT: {
2706 if (cfg->compile_aot)
2709 /* Have to use ecx as a temp reg since this can occur after OP_SETRET */
2712 * We do this _before_ the breakpoint, so single stepping after
2713 * a breakpoint is hit will step to the next IL offset.
2715 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
2716 MonoInst *var = cfg->arch.ss_tramp_var;
2720 g_assert (var->opcode == OP_REGOFFSET);
2721 /* Load ss_tramp_var */
2722 /* This is equal to &ss_trampoline */
2723 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, sizeof (mgreg_t));
2724 x86_alu_membase_imm (code, X86_CMP, X86_ECX, 0, 0);
2725 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2726 x86_call_membase (code, X86_ECX, 0);
2727 x86_patch (br [0], code);
2731 * Many parts of sdb depend on the ip after the single step trampoline call to be equal to the seq point offset.
2732 * This means we have to put the loading of bp_tramp_var after the offset.
2735 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2737 MonoInst *var = cfg->arch.bp_tramp_var;
2740 g_assert (var->opcode == OP_REGOFFSET);
2741 /* Load the address of the bp trampoline */
2742 /* This needs to be constant size */
2743 guint8 *start = code;
2744 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, 4);
2745 if (code < start + OP_SEQ_POINT_BP_OFFSET) {
2746 int size = start + OP_SEQ_POINT_BP_OFFSET - code;
2747 x86_padding (code, size);
2750 * A placeholder for a possible breakpoint inserted by
2751 * mono_arch_set_breakpoint ().
2753 for (i = 0; i < 2; ++i)
2756 * Add an additional nop so skipping the bp doesn't cause the ip to point
2757 * to another IL offset.
2765 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2769 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2774 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2778 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2783 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2787 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2792 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2796 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2799 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2803 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2807 #if defined( __native_client_codegen__ )
2808 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2809 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2812 * The code is the same for div/rem, the allocator will allocate dreg
2813 * to RAX/RDX as appropriate.
2815 if (ins->sreg2 == X86_EDX) {
2816 /* cdq clobbers this */
2817 x86_push_reg (code, ins->sreg2);
2819 x86_div_membase (code, X86_ESP, 0, TRUE);
2820 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2823 x86_div_reg (code, ins->sreg2, TRUE);
2828 #if defined( __native_client_codegen__ )
2829 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2830 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2832 if (ins->sreg2 == X86_EDX) {
2833 x86_push_reg (code, ins->sreg2);
2834 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2835 x86_div_membase (code, X86_ESP, 0, FALSE);
2836 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2838 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2839 x86_div_reg (code, ins->sreg2, FALSE);
2843 #if defined( __native_client_codegen__ )
2844 if (ins->inst_imm == 0) {
2845 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2846 x86_jump32 (code, 0);
2850 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2852 x86_div_reg (code, ins->sreg2, TRUE);
2855 int power = mono_is_power_of_two (ins->inst_imm);
2857 g_assert (ins->sreg1 == X86_EAX);
2858 g_assert (ins->dreg == X86_EAX);
2859 g_assert (power >= 0);
2862 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2864 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2866 * If the divident is >= 0, this does not nothing. If it is positive, it
2867 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2869 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2870 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2871 } else if (power == 0) {
2872 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2874 /* Based on gcc code */
2876 /* Add compensation for negative dividents */
2878 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2879 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2880 /* Compute remainder */
2881 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2882 /* Remove compensation */
2883 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2888 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2892 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2895 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2899 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2902 g_assert (ins->sreg2 == X86_ECX);
2903 x86_shift_reg (code, X86_SHL, ins->dreg);
2906 g_assert (ins->sreg2 == X86_ECX);
2907 x86_shift_reg (code, X86_SAR, ins->dreg);
2911 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2914 case OP_ISHR_UN_IMM:
2915 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2918 g_assert (ins->sreg2 == X86_ECX);
2919 x86_shift_reg (code, X86_SHR, ins->dreg);
2923 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2926 guint8 *jump_to_end;
2928 /* handle shifts below 32 bits */
2929 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2930 x86_shift_reg (code, X86_SHL, ins->sreg1);
2932 x86_test_reg_imm (code, X86_ECX, 32);
2933 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2935 /* handle shift over 32 bit */
2936 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2937 x86_clear_reg (code, ins->sreg1);
2939 x86_patch (jump_to_end, code);
2943 guint8 *jump_to_end;
2945 /* handle shifts below 32 bits */
2946 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2947 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2949 x86_test_reg_imm (code, X86_ECX, 32);
2950 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2952 /* handle shifts over 31 bits */
2953 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2954 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2956 x86_patch (jump_to_end, code);
2960 guint8 *jump_to_end;
2962 /* handle shifts below 32 bits */
2963 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2964 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2966 x86_test_reg_imm (code, X86_ECX, 32);
2967 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2969 /* handle shifts over 31 bits */
2970 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2971 x86_clear_reg (code, ins->backend.reg3);
2973 x86_patch (jump_to_end, code);
2977 if (ins->inst_imm >= 32) {
2978 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2979 x86_clear_reg (code, ins->sreg1);
2980 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2982 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2983 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2987 if (ins->inst_imm >= 32) {
2988 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2989 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2990 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2992 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2993 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2996 case OP_LSHR_UN_IMM:
2997 if (ins->inst_imm >= 32) {
2998 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2999 x86_clear_reg (code, ins->backend.reg3);
3000 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3002 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3003 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3007 x86_not_reg (code, ins->sreg1);
3010 x86_neg_reg (code, ins->sreg1);
3014 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3018 switch (ins->inst_imm) {
3022 if (ins->dreg != ins->sreg1)
3023 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3024 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3027 /* LEA r1, [r2 + r2*2] */
3028 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3031 /* LEA r1, [r2 + r2*4] */
3032 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3035 /* LEA r1, [r2 + r2*2] */
3037 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3038 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3041 /* LEA r1, [r2 + r2*8] */
3042 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3045 /* LEA r1, [r2 + r2*4] */
3047 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3048 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3051 /* LEA r1, [r2 + r2*2] */
3053 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3054 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3057 /* LEA r1, [r2 + r2*4] */
3058 /* LEA r1, [r1 + r1*4] */
3059 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3060 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3063 /* LEA r1, [r2 + r2*4] */
3065 /* LEA r1, [r1 + r1*4] */
3066 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3067 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3068 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3071 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3076 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3077 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3079 case OP_IMUL_OVF_UN: {
3080 /* the mul operation and the exception check should most likely be split */
3081 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3082 /*g_assert (ins->sreg2 == X86_EAX);
3083 g_assert (ins->dreg == X86_EAX);*/
3084 if (ins->sreg2 == X86_EAX) {
3085 non_eax_reg = ins->sreg1;
3086 } else if (ins->sreg1 == X86_EAX) {
3087 non_eax_reg = ins->sreg2;
3089 /* no need to save since we're going to store to it anyway */
3090 if (ins->dreg != X86_EAX) {
3092 x86_push_reg (code, X86_EAX);
3094 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3095 non_eax_reg = ins->sreg2;
3097 if (ins->dreg == X86_EDX) {
3100 x86_push_reg (code, X86_EAX);
3104 x86_push_reg (code, X86_EDX);
3106 x86_mul_reg (code, non_eax_reg, FALSE);
3107 /* save before the check since pop and mov don't change the flags */
3108 if (ins->dreg != X86_EAX)
3109 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3111 x86_pop_reg (code, X86_EDX);
3113 x86_pop_reg (code, X86_EAX);
3114 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3118 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3121 g_assert_not_reached ();
3122 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3123 x86_mov_reg_imm (code, ins->dreg, 0);
3126 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3127 x86_mov_reg_imm (code, ins->dreg, 0);
3129 case OP_LOAD_GOTADDR:
3130 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3131 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3134 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3135 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3137 case OP_X86_PUSH_GOT_ENTRY:
3138 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3139 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3142 if (ins->dreg != ins->sreg1)
3143 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3146 MonoCallInst *call = (MonoCallInst*)ins;
3149 ins->flags |= MONO_INST_GC_CALLSITE;
3150 ins->backend.pc_offset = code - cfg->native_code;
3152 /* reset offset to make max_len work */
3153 offset = code - cfg->native_code;
3155 g_assert (!cfg->method->save_lmf);
3157 /* restore callee saved registers */
3158 for (i = 0; i < X86_NREG; ++i)
3159 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3161 if (cfg->used_int_regs & (1 << X86_ESI)) {
3162 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3165 if (cfg->used_int_regs & (1 << X86_EDI)) {
3166 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3169 if (cfg->used_int_regs & (1 << X86_EBX)) {
3170 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3174 /* Copy arguments on the stack to our argument area */
3175 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3176 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3177 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3180 /* restore ESP/EBP */
3182 offset = code - cfg->native_code;
3183 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3184 x86_jump32 (code, 0);
3186 ins->flags |= MONO_INST_GC_CALLSITE;
3187 cfg->disable_aot = TRUE;
3191 /* ensure ins->sreg1 is not NULL
3192 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3193 * cmp DWORD PTR [eax], 0
3195 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3198 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3199 x86_push_reg (code, hreg);
3200 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3201 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3202 x86_pop_reg (code, hreg);
3215 case OP_VOIDCALL_REG:
3217 case OP_FCALL_MEMBASE:
3218 case OP_LCALL_MEMBASE:
3219 case OP_VCALL_MEMBASE:
3220 case OP_VCALL2_MEMBASE:
3221 case OP_VOIDCALL_MEMBASE:
3222 case OP_CALL_MEMBASE: {
3225 call = (MonoCallInst*)ins;
3226 cinfo = (CallInfo*)call->call_info;
3228 switch (ins->opcode) {
3235 if (ins->flags & MONO_INST_HAS_METHOD)
3236 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3238 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3244 case OP_VOIDCALL_REG:
3246 x86_call_reg (code, ins->sreg1);
3248 case OP_FCALL_MEMBASE:
3249 case OP_LCALL_MEMBASE:
3250 case OP_VCALL_MEMBASE:
3251 case OP_VCALL2_MEMBASE:
3252 case OP_VOIDCALL_MEMBASE:
3253 case OP_CALL_MEMBASE:
3254 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3257 g_assert_not_reached ();
3260 ins->flags |= MONO_INST_GC_CALLSITE;
3261 ins->backend.pc_offset = code - cfg->native_code;
3262 if (cinfo->callee_stack_pop) {
3263 /* Have to compensate for the stack space popped by the callee */
3264 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3266 code = emit_move_return_value (cfg, ins, code);
3270 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3272 case OP_X86_LEA_MEMBASE:
3273 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3276 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3279 /* keep alignment */
3280 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3281 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3282 code = mono_emit_stack_alloc (cfg, code, ins);
3283 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3284 if (cfg->param_area)
3285 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3287 case OP_LOCALLOC_IMM: {
3288 guint32 size = ins->inst_imm;
3289 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3291 if (ins->flags & MONO_INST_INIT) {
3292 /* FIXME: Optimize this */
3293 x86_mov_reg_imm (code, ins->dreg, size);
3294 ins->sreg1 = ins->dreg;
3296 code = mono_emit_stack_alloc (cfg, code, ins);
3297 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3299 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3300 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3302 if (cfg->param_area)
3303 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3307 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3308 x86_push_reg (code, ins->sreg1);
3309 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3310 (gpointer)"mono_arch_throw_exception");
3311 ins->flags |= MONO_INST_GC_CALLSITE;
3312 ins->backend.pc_offset = code - cfg->native_code;
3316 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3317 x86_push_reg (code, ins->sreg1);
3318 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3319 (gpointer)"mono_arch_rethrow_exception");
3320 ins->flags |= MONO_INST_GC_CALLSITE;
3321 ins->backend.pc_offset = code - cfg->native_code;
3324 case OP_CALL_HANDLER:
3325 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3326 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3327 x86_call_imm (code, 0);
3328 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3329 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3331 case OP_START_HANDLER: {
3332 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3333 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3334 if (cfg->param_area)
3335 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3338 case OP_ENDFINALLY: {
3339 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3340 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3344 case OP_ENDFILTER: {
3345 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3346 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3347 /* The local allocator will put the result into EAX */
3352 if (ins->dreg != X86_EAX)
3353 x86_mov_reg_reg (code, ins->dreg, X86_EAX, sizeof (gpointer));
3357 ins->inst_c0 = code - cfg->native_code;
3360 if (ins->inst_target_bb->native_offset) {
3361 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3363 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3364 if ((cfg->opt & MONO_OPT_BRANCH) &&
3365 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3366 x86_jump8 (code, 0);
3368 x86_jump32 (code, 0);
3372 x86_jump_reg (code, ins->sreg1);
3391 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3392 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3394 case OP_COND_EXC_EQ:
3395 case OP_COND_EXC_NE_UN:
3396 case OP_COND_EXC_LT:
3397 case OP_COND_EXC_LT_UN:
3398 case OP_COND_EXC_GT:
3399 case OP_COND_EXC_GT_UN:
3400 case OP_COND_EXC_GE:
3401 case OP_COND_EXC_GE_UN:
3402 case OP_COND_EXC_LE:
3403 case OP_COND_EXC_LE_UN:
3404 case OP_COND_EXC_IEQ:
3405 case OP_COND_EXC_INE_UN:
3406 case OP_COND_EXC_ILT:
3407 case OP_COND_EXC_ILT_UN:
3408 case OP_COND_EXC_IGT:
3409 case OP_COND_EXC_IGT_UN:
3410 case OP_COND_EXC_IGE:
3411 case OP_COND_EXC_IGE_UN:
3412 case OP_COND_EXC_ILE:
3413 case OP_COND_EXC_ILE_UN:
3414 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3416 case OP_COND_EXC_OV:
3417 case OP_COND_EXC_NO:
3419 case OP_COND_EXC_NC:
3420 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3422 case OP_COND_EXC_IOV:
3423 case OP_COND_EXC_INO:
3424 case OP_COND_EXC_IC:
3425 case OP_COND_EXC_INC:
3426 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3438 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3446 case OP_CMOV_INE_UN:
3447 case OP_CMOV_IGE_UN:
3448 case OP_CMOV_IGT_UN:
3449 case OP_CMOV_ILE_UN:
3450 case OP_CMOV_ILT_UN:
3451 g_assert (ins->dreg == ins->sreg1);
3452 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3455 /* floating point opcodes */
3457 double d = *(double *)ins->inst_p0;
3459 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3461 } else if (d == 1.0) {
3464 if (cfg->compile_aot) {
3465 guint32 *val = (guint32*)&d;
3466 x86_push_imm (code, val [1]);
3467 x86_push_imm (code, val [0]);
3468 x86_fld_membase (code, X86_ESP, 0, TRUE);
3469 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3472 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3473 x86_fld (code, NULL, TRUE);
3479 float f = *(float *)ins->inst_p0;
3481 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3483 } else if (f == 1.0) {
3486 if (cfg->compile_aot) {
3487 guint32 val = *(guint32*)&f;
3488 x86_push_imm (code, val);
3489 x86_fld_membase (code, X86_ESP, 0, FALSE);
3490 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3493 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3494 x86_fld (code, NULL, FALSE);
3499 case OP_STORER8_MEMBASE_REG:
3500 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3502 case OP_LOADR8_MEMBASE:
3503 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3505 case OP_STORER4_MEMBASE_REG:
3506 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3508 case OP_LOADR4_MEMBASE:
3509 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3511 case OP_ICONV_TO_R4:
3512 x86_push_reg (code, ins->sreg1);
3513 x86_fild_membase (code, X86_ESP, 0, FALSE);
3514 /* Change precision */
3515 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3516 x86_fld_membase (code, X86_ESP, 0, FALSE);
3517 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3519 case OP_ICONV_TO_R8:
3520 x86_push_reg (code, ins->sreg1);
3521 x86_fild_membase (code, X86_ESP, 0, FALSE);
3522 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3524 case OP_ICONV_TO_R_UN:
3525 x86_push_imm (code, 0);
3526 x86_push_reg (code, ins->sreg1);
3527 x86_fild_membase (code, X86_ESP, 0, TRUE);
3528 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3530 case OP_X86_FP_LOAD_I8:
3531 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3533 case OP_X86_FP_LOAD_I4:
3534 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3536 case OP_FCONV_TO_R4:
3537 /* Change precision */
3538 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3539 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3540 x86_fld_membase (code, X86_ESP, 0, FALSE);
3541 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3543 case OP_FCONV_TO_I1:
3544 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3546 case OP_FCONV_TO_U1:
3547 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3549 case OP_FCONV_TO_I2:
3550 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3552 case OP_FCONV_TO_U2:
3553 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3555 case OP_FCONV_TO_I4:
3557 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3559 case OP_FCONV_TO_I8:
3560 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3561 x86_fnstcw_membase(code, X86_ESP, 0);
3562 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3563 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3564 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3565 x86_fldcw_membase (code, X86_ESP, 2);
3566 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3567 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3568 x86_pop_reg (code, ins->dreg);
3569 x86_pop_reg (code, ins->backend.reg3);
3570 x86_fldcw_membase (code, X86_ESP, 0);
3571 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3573 case OP_LCONV_TO_R8_2:
3574 x86_push_reg (code, ins->sreg2);
3575 x86_push_reg (code, ins->sreg1);
3576 x86_fild_membase (code, X86_ESP, 0, TRUE);
3577 /* Change precision */
3578 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3579 x86_fld_membase (code, X86_ESP, 0, TRUE);
3580 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3582 case OP_LCONV_TO_R4_2:
3583 x86_push_reg (code, ins->sreg2);
3584 x86_push_reg (code, ins->sreg1);
3585 x86_fild_membase (code, X86_ESP, 0, TRUE);
3586 /* Change precision */
3587 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3588 x86_fld_membase (code, X86_ESP, 0, FALSE);
3589 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3591 case OP_LCONV_TO_R_UN_2: {
3592 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3595 /* load 64bit integer to FP stack */
3596 x86_push_reg (code, ins->sreg2);
3597 x86_push_reg (code, ins->sreg1);
3598 x86_fild_membase (code, X86_ESP, 0, TRUE);
3600 /* test if lreg is negative */
3601 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3602 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3604 /* add correction constant mn */
3605 if (cfg->compile_aot) {
3606 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3607 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3608 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3609 x86_fld80_membase (code, X86_ESP, 2);
3610 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3612 x86_fld80_mem (code, mn);
3614 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3616 x86_patch (br, code);
3618 /* Change precision */
3619 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3620 x86_fld_membase (code, X86_ESP, 0, TRUE);
3622 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3626 case OP_LCONV_TO_OVF_I:
3627 case OP_LCONV_TO_OVF_I4_2: {
3628 guint8 *br [3], *label [1];
3632 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3634 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3636 /* If the low word top bit is set, see if we are negative */
3637 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3638 /* We are not negative (no top bit set, check for our top word to be zero */
3639 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3640 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3643 /* throw exception */
3644 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3646 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3647 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3648 x86_jump8 (code, 0);
3650 x86_jump32 (code, 0);
3652 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3653 x86_jump32 (code, 0);
3657 x86_patch (br [0], code);
3658 /* our top bit is set, check that top word is 0xfffffff */
3659 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3661 x86_patch (br [1], code);
3662 /* nope, emit exception */
3663 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3664 x86_patch (br [2], label [0]);
3666 if (ins->dreg != ins->sreg1)
3667 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3671 /* Not needed on the fp stack */
3673 case OP_MOVE_F_TO_I4:
3674 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
3675 x86_mov_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, 4);
3677 case OP_MOVE_I4_TO_F:
3678 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
3679 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
3682 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3685 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3688 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3691 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3699 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3704 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3711 * it really doesn't make sense to inline all this code,
3712 * it's here just to show that things may not be as simple
3715 guchar *check_pos, *end_tan, *pop_jump;
3716 x86_push_reg (code, X86_EAX);
3719 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3721 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3722 x86_fstp (code, 0); /* pop the 1.0 */
3724 x86_jump8 (code, 0);
3726 x86_fp_op (code, X86_FADD, 0);
3730 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3732 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3735 x86_patch (pop_jump, code);
3736 x86_fstp (code, 0); /* pop the 1.0 */
3737 x86_patch (check_pos, code);
3738 x86_patch (end_tan, code);
3740 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3741 x86_pop_reg (code, X86_EAX);
3748 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3757 g_assert (cfg->opt & MONO_OPT_CMOV);
3758 g_assert (ins->dreg == ins->sreg1);
3759 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3760 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3763 g_assert (cfg->opt & MONO_OPT_CMOV);
3764 g_assert (ins->dreg == ins->sreg1);
3765 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3766 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3769 g_assert (cfg->opt & MONO_OPT_CMOV);
3770 g_assert (ins->dreg == ins->sreg1);
3771 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3772 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3775 g_assert (cfg->opt & MONO_OPT_CMOV);
3776 g_assert (ins->dreg == ins->sreg1);
3777 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3778 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3784 x86_fxch (code, ins->inst_imm);
3789 x86_push_reg (code, X86_EAX);
3790 /* we need to exchange ST(0) with ST(1) */
3793 /* this requires a loop, because fprem somtimes
3794 * returns a partial remainder */
3796 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3797 /* x86_fprem1 (code); */
3800 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3802 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3808 x86_pop_reg (code, X86_EAX);
3812 if (cfg->opt & MONO_OPT_FCMOV) {
3813 x86_fcomip (code, 1);
3817 /* this overwrites EAX */
3818 EMIT_FPCOMPARE(code);
3819 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3823 if (cfg->opt & MONO_OPT_FCMOV) {
3824 /* zeroing the register at the start results in
3825 * shorter and faster code (we can also remove the widening op)
3827 guchar *unordered_check;
3828 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3829 x86_fcomip (code, 1);
3831 unordered_check = code;
3832 x86_branch8 (code, X86_CC_P, 0, FALSE);
3833 if (ins->opcode == OP_FCEQ) {
3834 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3835 x86_patch (unordered_check, code);
3837 guchar *jump_to_end;
3838 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3840 x86_jump8 (code, 0);
3841 x86_patch (unordered_check, code);
3842 x86_inc_reg (code, ins->dreg);
3843 x86_patch (jump_to_end, code);
3848 if (ins->dreg != X86_EAX)
3849 x86_push_reg (code, X86_EAX);
3851 EMIT_FPCOMPARE(code);
3852 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3853 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3854 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3855 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3857 if (ins->dreg != X86_EAX)
3858 x86_pop_reg (code, X86_EAX);
3862 if (cfg->opt & MONO_OPT_FCMOV) {
3863 /* zeroing the register at the start results in
3864 * shorter and faster code (we can also remove the widening op)
3866 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3867 x86_fcomip (code, 1);
3869 if (ins->opcode == OP_FCLT_UN) {
3870 guchar *unordered_check = code;
3871 guchar *jump_to_end;
3872 x86_branch8 (code, X86_CC_P, 0, FALSE);
3873 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3875 x86_jump8 (code, 0);
3876 x86_patch (unordered_check, code);
3877 x86_inc_reg (code, ins->dreg);
3878 x86_patch (jump_to_end, code);
3880 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3884 if (ins->dreg != X86_EAX)
3885 x86_push_reg (code, X86_EAX);
3887 EMIT_FPCOMPARE(code);
3888 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3889 if (ins->opcode == OP_FCLT_UN) {
3890 guchar *is_not_zero_check, *end_jump;
3891 is_not_zero_check = code;
3892 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3894 x86_jump8 (code, 0);
3895 x86_patch (is_not_zero_check, code);
3896 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3898 x86_patch (end_jump, code);
3900 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3901 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3903 if (ins->dreg != X86_EAX)
3904 x86_pop_reg (code, X86_EAX);
3907 guchar *unordered_check;
3908 guchar *jump_to_end;
3909 if (cfg->opt & MONO_OPT_FCMOV) {
3910 /* zeroing the register at the start results in
3911 * shorter and faster code (we can also remove the widening op)
3913 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3914 x86_fcomip (code, 1);
3916 unordered_check = code;
3917 x86_branch8 (code, X86_CC_P, 0, FALSE);
3918 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3919 x86_patch (unordered_check, code);
3922 if (ins->dreg != X86_EAX)
3923 x86_push_reg (code, X86_EAX);
3925 EMIT_FPCOMPARE(code);
3926 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3927 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3928 unordered_check = code;
3929 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3931 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3932 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3933 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3935 x86_jump8 (code, 0);
3936 x86_patch (unordered_check, code);
3937 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3938 x86_patch (jump_to_end, code);
3940 if (ins->dreg != X86_EAX)
3941 x86_pop_reg (code, X86_EAX);
3946 if (cfg->opt & MONO_OPT_FCMOV) {
3947 /* zeroing the register at the start results in
3948 * shorter and faster code (we can also remove the widening op)
3950 guchar *unordered_check;
3951 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3952 x86_fcomip (code, 1);
3954 if (ins->opcode == OP_FCGT) {
3955 unordered_check = code;
3956 x86_branch8 (code, X86_CC_P, 0, FALSE);
3957 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3958 x86_patch (unordered_check, code);
3960 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3964 if (ins->dreg != X86_EAX)
3965 x86_push_reg (code, X86_EAX);
3967 EMIT_FPCOMPARE(code);
3968 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3969 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3970 if (ins->opcode == OP_FCGT_UN) {
3971 guchar *is_not_zero_check, *end_jump;
3972 is_not_zero_check = code;
3973 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3975 x86_jump8 (code, 0);
3976 x86_patch (is_not_zero_check, code);
3977 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3979 x86_patch (end_jump, code);
3981 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3982 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3984 if (ins->dreg != X86_EAX)
3985 x86_pop_reg (code, X86_EAX);
3988 guchar *unordered_check;
3989 guchar *jump_to_end;
3990 if (cfg->opt & MONO_OPT_FCMOV) {
3991 /* zeroing the register at the start results in
3992 * shorter and faster code (we can also remove the widening op)
3994 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3995 x86_fcomip (code, 1);
3997 unordered_check = code;
3998 x86_branch8 (code, X86_CC_P, 0, FALSE);
3999 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4000 x86_patch (unordered_check, code);
4003 if (ins->dreg != X86_EAX)
4004 x86_push_reg (code, X86_EAX);
4006 EMIT_FPCOMPARE(code);
4007 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4008 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4009 unordered_check = code;
4010 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4012 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4013 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4014 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4016 x86_jump8 (code, 0);
4017 x86_patch (unordered_check, code);
4018 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4019 x86_patch (jump_to_end, code);
4021 if (ins->dreg != X86_EAX)
4022 x86_pop_reg (code, X86_EAX);
4026 if (cfg->opt & MONO_OPT_FCMOV) {
4027 guchar *jump = code;
4028 x86_branch8 (code, X86_CC_P, 0, TRUE);
4029 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4030 x86_patch (jump, code);
4033 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4034 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4037 /* Branch if C013 != 100 */
4038 if (cfg->opt & MONO_OPT_FCMOV) {
4039 /* branch if !ZF or (PF|CF) */
4040 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4041 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4042 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4045 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4046 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4049 if (cfg->opt & MONO_OPT_FCMOV) {
4050 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4053 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4056 if (cfg->opt & MONO_OPT_FCMOV) {
4057 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4058 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4061 if (ins->opcode == OP_FBLT_UN) {
4062 guchar *is_not_zero_check, *end_jump;
4063 is_not_zero_check = code;
4064 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4066 x86_jump8 (code, 0);
4067 x86_patch (is_not_zero_check, code);
4068 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4070 x86_patch (end_jump, code);
4072 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4076 if (cfg->opt & MONO_OPT_FCMOV) {
4077 if (ins->opcode == OP_FBGT) {
4080 /* skip branch if C1=1 */
4082 x86_branch8 (code, X86_CC_P, 0, FALSE);
4083 /* branch if (C0 | C3) = 1 */
4084 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4085 x86_patch (br1, code);
4087 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4091 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4092 if (ins->opcode == OP_FBGT_UN) {
4093 guchar *is_not_zero_check, *end_jump;
4094 is_not_zero_check = code;
4095 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4097 x86_jump8 (code, 0);
4098 x86_patch (is_not_zero_check, code);
4099 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4101 x86_patch (end_jump, code);
4103 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4106 /* Branch if C013 == 100 or 001 */
4107 if (cfg->opt & MONO_OPT_FCMOV) {
4110 /* skip branch if C1=1 */
4112 x86_branch8 (code, X86_CC_P, 0, FALSE);
4113 /* branch if (C0 | C3) = 1 */
4114 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4115 x86_patch (br1, code);
4118 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4119 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4120 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4121 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4124 /* Branch if C013 == 000 */
4125 if (cfg->opt & MONO_OPT_FCMOV) {
4126 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4129 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4132 /* Branch if C013=000 or 100 */
4133 if (cfg->opt & MONO_OPT_FCMOV) {
4136 /* skip branch if C1=1 */
4138 x86_branch8 (code, X86_CC_P, 0, FALSE);
4139 /* branch if C0=0 */
4140 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4141 x86_patch (br1, code);
4144 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4145 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4146 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4149 /* Branch if C013 != 001 */
4150 if (cfg->opt & MONO_OPT_FCMOV) {
4151 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4152 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4155 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4156 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4160 x86_push_reg (code, X86_EAX);
4163 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4164 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4165 x86_pop_reg (code, X86_EAX);
4167 /* Have to clean up the fp stack before throwing the exception */
4169 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4172 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
4174 x86_patch (br1, code);
4178 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4181 case OP_TLS_GET_REG: {
4182 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4186 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4189 case OP_TLS_SET_REG: {
4190 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4193 case OP_MEMORY_BARRIER: {
4194 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4195 x86_prefix (code, X86_LOCK_PREFIX);
4196 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4200 case OP_ATOMIC_ADD_I4: {
4201 int dreg = ins->dreg;
4203 g_assert (cfg->has_atomic_add_i4);
4205 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4206 if (ins->sreg2 == dreg) {
4207 if (dreg == X86_EBX) {
4209 if (ins->inst_basereg == X86_EDI)
4213 if (ins->inst_basereg == X86_EBX)
4216 } else if (ins->inst_basereg == dreg) {
4217 if (dreg == X86_EBX) {
4219 if (ins->sreg2 == X86_EDI)
4223 if (ins->sreg2 == X86_EBX)
4228 if (dreg != ins->dreg) {
4229 x86_push_reg (code, dreg);
4232 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4233 x86_prefix (code, X86_LOCK_PREFIX);
4234 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4235 /* dreg contains the old value, add with sreg2 value */
4236 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4238 if (ins->dreg != dreg) {
4239 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4240 x86_pop_reg (code, dreg);
4245 case OP_ATOMIC_EXCHANGE_I4: {
4247 int sreg2 = ins->sreg2;
4248 int breg = ins->inst_basereg;
4250 g_assert (cfg->has_atomic_exchange_i4);
4252 /* cmpxchg uses eax as comperand, need to make sure we can use it
4253 * hack to overcome limits in x86 reg allocator
4254 * (req: dreg == eax and sreg2 != eax and breg != eax)
4256 g_assert (ins->dreg == X86_EAX);
4258 /* We need the EAX reg for the cmpxchg */
4259 if (ins->sreg2 == X86_EAX) {
4260 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4261 x86_push_reg (code, sreg2);
4262 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4265 if (breg == X86_EAX) {
4266 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4267 x86_push_reg (code, breg);
4268 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4271 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4273 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4274 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4275 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4276 x86_patch (br [1], br [0]);
4278 if (breg != ins->inst_basereg)
4279 x86_pop_reg (code, breg);
4281 if (ins->sreg2 != sreg2)
4282 x86_pop_reg (code, sreg2);
4286 case OP_ATOMIC_CAS_I4: {
4287 g_assert (ins->dreg == X86_EAX);
4288 g_assert (ins->sreg3 == X86_EAX);
4289 g_assert (ins->sreg1 != X86_EAX);
4290 g_assert (ins->sreg1 != ins->sreg2);
4292 x86_prefix (code, X86_LOCK_PREFIX);
4293 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4296 case OP_ATOMIC_LOAD_I1: {
4297 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4300 case OP_ATOMIC_LOAD_U1: {
4301 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4304 case OP_ATOMIC_LOAD_I2: {
4305 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4308 case OP_ATOMIC_LOAD_U2: {
4309 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4312 case OP_ATOMIC_LOAD_I4:
4313 case OP_ATOMIC_LOAD_U4: {
4314 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4317 case OP_ATOMIC_LOAD_R4:
4318 case OP_ATOMIC_LOAD_R8: {
4319 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4322 case OP_ATOMIC_STORE_I1:
4323 case OP_ATOMIC_STORE_U1:
4324 case OP_ATOMIC_STORE_I2:
4325 case OP_ATOMIC_STORE_U2:
4326 case OP_ATOMIC_STORE_I4:
4327 case OP_ATOMIC_STORE_U4: {
4330 switch (ins->opcode) {
4331 case OP_ATOMIC_STORE_I1:
4332 case OP_ATOMIC_STORE_U1:
4335 case OP_ATOMIC_STORE_I2:
4336 case OP_ATOMIC_STORE_U2:
4339 case OP_ATOMIC_STORE_I4:
4340 case OP_ATOMIC_STORE_U4:
4345 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4347 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4351 case OP_ATOMIC_STORE_R4:
4352 case OP_ATOMIC_STORE_R8: {
4353 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4355 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4359 case OP_CARD_TABLE_WBARRIER: {
4360 int ptr = ins->sreg1;
4361 int value = ins->sreg2;
4363 int nursery_shift, card_table_shift;
4364 gpointer card_table_mask;
4365 size_t nursery_size;
4366 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4367 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4368 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4371 * We need one register we can clobber, we choose EDX and make sreg1
4372 * fixed EAX to work around limitations in the local register allocator.
4373 * sreg2 might get allocated to EDX, but that is not a problem since
4374 * we use it before clobbering EDX.
4376 g_assert (ins->sreg1 == X86_EAX);
4379 * This is the code we produce:
4382 * edx >>= nursery_shift
4383 * cmp edx, (nursery_start >> nursery_shift)
4386 * edx >>= card_table_shift
4387 * card_table[edx] = 1
4391 if (card_table_nursery_check) {
4392 if (value != X86_EDX)
4393 x86_mov_reg_reg (code, X86_EDX, value, 4);
4394 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4395 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4396 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4398 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4399 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4400 if (card_table_mask)
4401 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4402 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4403 if (card_table_nursery_check)
4404 x86_patch (br, code);
4407 #ifdef MONO_ARCH_SIMD_INTRINSICS
4409 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4412 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4415 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4418 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4421 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4424 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4427 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4428 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4431 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4434 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4437 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4440 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4443 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4446 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4449 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4452 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4455 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4458 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4461 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4464 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4467 case OP_PSHUFLEW_HIGH:
4468 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4469 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4471 case OP_PSHUFLEW_LOW:
4472 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4473 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4476 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4477 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4480 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4481 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4484 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4485 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4489 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4492 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4495 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4498 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4501 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4504 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4507 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4508 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4511 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4514 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4517 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4520 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4523 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4526 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4529 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4532 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4535 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4538 case OP_EXTRACT_MASK:
4539 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4543 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4546 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4549 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4553 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4556 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4559 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4562 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4566 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4569 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4572 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4575 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4579 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4582 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4585 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4589 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4592 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4595 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4599 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4602 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4606 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4609 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4612 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4616 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4619 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4622 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4626 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4629 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4632 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4635 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4639 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4642 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4645 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4648 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4651 case OP_PSUM_ABS_DIFF:
4652 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4655 case OP_UNPACK_LOWB:
4656 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4658 case OP_UNPACK_LOWW:
4659 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4661 case OP_UNPACK_LOWD:
4662 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4664 case OP_UNPACK_LOWQ:
4665 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4667 case OP_UNPACK_LOWPS:
4668 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4670 case OP_UNPACK_LOWPD:
4671 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4674 case OP_UNPACK_HIGHB:
4675 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4677 case OP_UNPACK_HIGHW:
4678 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4680 case OP_UNPACK_HIGHD:
4681 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4683 case OP_UNPACK_HIGHQ:
4684 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4686 case OP_UNPACK_HIGHPS:
4687 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4689 case OP_UNPACK_HIGHPD:
4690 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4694 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4697 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4700 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4703 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4706 case OP_PADDB_SAT_UN:
4707 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4709 case OP_PSUBB_SAT_UN:
4710 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4712 case OP_PADDW_SAT_UN:
4713 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4715 case OP_PSUBW_SAT_UN:
4716 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4720 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4723 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4726 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4729 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4733 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4736 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4739 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4741 case OP_PMULW_HIGH_UN:
4742 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4745 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4749 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4752 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4756 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4759 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4763 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4766 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4770 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4773 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4777 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4780 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4784 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4787 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4791 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4794 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4798 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4801 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4805 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4808 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4812 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4814 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4815 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4819 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4821 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4822 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4826 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4828 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4829 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4833 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4835 case OP_EXTRACTX_U2:
4836 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4838 case OP_INSERTX_U1_SLOW:
4839 /*sreg1 is the extracted ireg (scratch)
4840 /sreg2 is the to be inserted ireg (scratch)
4841 /dreg is the xreg to receive the value*/
4843 /*clear the bits from the extracted word*/
4844 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4845 /*shift the value to insert if needed*/
4846 if (ins->inst_c0 & 1)
4847 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4848 /*join them together*/
4849 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4850 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4852 case OP_INSERTX_I4_SLOW:
4853 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4854 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4855 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4858 case OP_INSERTX_R4_SLOW:
4859 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4860 /*TODO if inst_c0 == 0 use movss*/
4861 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4862 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4864 case OP_INSERTX_R8_SLOW:
4865 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4866 if (cfg->verbose_level)
4867 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4869 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4871 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4874 case OP_STOREX_MEMBASE_REG:
4875 case OP_STOREX_MEMBASE:
4876 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4878 case OP_LOADX_MEMBASE:
4879 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4881 case OP_LOADX_ALIGNED_MEMBASE:
4882 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4884 case OP_STOREX_ALIGNED_MEMBASE_REG:
4885 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4887 case OP_STOREX_NTA_MEMBASE_REG:
4888 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4890 case OP_PREFETCH_MEMBASE:
4891 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4895 /*FIXME the peephole pass should have killed this*/
4896 if (ins->dreg != ins->sreg1)
4897 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4900 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4903 case OP_FCONV_TO_R8_X:
4904 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4905 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4908 case OP_XCONV_R8_TO_I4:
4909 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4910 switch (ins->backend.source_opcode) {
4911 case OP_FCONV_TO_I1:
4912 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4914 case OP_FCONV_TO_U1:
4915 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4917 case OP_FCONV_TO_I2:
4918 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4920 case OP_FCONV_TO_U2:
4921 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4927 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4928 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4929 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4930 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4931 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4932 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4935 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4936 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4937 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4940 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4941 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4944 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4945 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4946 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4949 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4950 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4951 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4955 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4958 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4961 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4964 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4967 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4970 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4973 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4976 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4980 case OP_LIVERANGE_START: {
4981 if (cfg->verbose_level > 1)
4982 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4983 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4986 case OP_LIVERANGE_END: {
4987 if (cfg->verbose_level > 1)
4988 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4989 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4992 case OP_GC_SAFE_POINT: {
4993 const char *polling_func = NULL;
4994 int compare_val = 0;
4997 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
4998 polling_func = "mono_nacl_gc";
4999 compare_val = 0xFFFFFFFF;
5001 g_assert (mono_threads_is_coop_enabled ());
5002 polling_func = "mono_threads_state_poll";
5006 x86_test_membase_imm (code, ins->sreg1, 0, compare_val);
5007 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
5008 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
5009 x86_patch (br [0], code);
5013 case OP_GC_LIVENESS_DEF:
5014 case OP_GC_LIVENESS_USE:
5015 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5016 ins->backend.pc_offset = code - cfg->native_code;
5018 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5019 ins->backend.pc_offset = code - cfg->native_code;
5020 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5023 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
5026 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
5029 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
5030 g_assert_not_reached ();
5033 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
5034 #ifndef __native_client_codegen__
5035 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5036 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5037 g_assert_not_reached ();
5038 #endif /* __native_client_codegen__ */
5044 cfg->code_len = code - cfg->native_code;
5047 #endif /* DISABLE_JIT */
5050 mono_arch_register_lowlevel_calls (void)
5055 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5057 unsigned char *ip = ji->ip.i + code;
5060 case MONO_PATCH_INFO_IP:
5061 *((gconstpointer *)(ip)) = target;
5063 case MONO_PATCH_INFO_ABS:
5064 case MONO_PATCH_INFO_METHOD:
5065 case MONO_PATCH_INFO_METHOD_JUMP:
5066 case MONO_PATCH_INFO_INTERNAL_METHOD:
5067 case MONO_PATCH_INFO_BB:
5068 case MONO_PATCH_INFO_LABEL:
5069 case MONO_PATCH_INFO_RGCTX_FETCH:
5070 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5071 #if defined(__native_client_codegen__) && defined(__native_client__)
5072 if (nacl_is_code_address (code)) {
5073 /* For tail calls, code is patched after being installed */
5074 /* but not through the normal "patch callsite" method. */
5075 unsigned char buf[kNaClAlignment];
5076 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5077 unsigned char *_target = target;
5079 /* All patch targets modified in x86_patch */
5080 /* are IP relative. */
5081 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5082 memcpy (buf, aligned_code, kNaClAlignment);
5083 /* Patch a temp buffer of bundle size, */
5084 /* then install to actual location. */
5085 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5086 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5087 g_assert (ret == 0);
5090 x86_patch (ip, (unsigned char*)target);
5093 x86_patch (ip, (unsigned char*)target);
5096 case MONO_PATCH_INFO_NONE:
5098 case MONO_PATCH_INFO_R4:
5099 case MONO_PATCH_INFO_R8: {
5100 guint32 offset = mono_arch_get_patch_offset (ip);
5101 *((gconstpointer *)(ip + offset)) = target;
5105 guint32 offset = mono_arch_get_patch_offset (ip);
5106 #if !defined(__native_client__)
5107 *((gconstpointer *)(ip + offset)) = target;
5109 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5116 static G_GNUC_UNUSED void
5117 stack_unaligned (MonoMethod *m, gpointer caller)
5119 printf ("%s\n", mono_method_full_name (m, TRUE));
5120 g_assert_not_reached ();
5124 mono_arch_emit_prolog (MonoCompile *cfg)
5126 MonoMethod *method = cfg->method;
5128 MonoMethodSignature *sig;
5130 int alloc_size, pos, max_offset, i, cfa_offset;
5132 gboolean need_stack_frame;
5133 #ifdef __native_client_codegen__
5134 guint alignment_check;
5137 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5139 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5140 cfg->code_size += 512;
5142 #if defined(__default_codegen__)
5143 code = cfg->native_code = g_malloc (cfg->code_size);
5144 #elif defined(__native_client_codegen__)
5145 /* native_code_alloc is not 32-byte aligned, native_code is. */
5146 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5147 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5149 /* Align native_code to next nearest kNaclAlignment byte. */
5150 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5151 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5153 code = cfg->native_code;
5155 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5156 g_assert(alignment_check == 0);
5163 /* Check that the stack is aligned on osx */
5164 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5165 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5166 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5168 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5169 x86_push_membase (code, X86_ESP, 0);
5170 x86_push_imm (code, cfg->method);
5171 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5172 x86_call_reg (code, X86_EAX);
5173 x86_patch (br [0], code);
5177 /* Offset between RSP and the CFA */
5181 cfa_offset = sizeof (gpointer);
5182 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5183 // IP saved at CFA - 4
5184 /* There is no IP reg on x86 */
5185 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5186 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5188 need_stack_frame = needs_stack_frame (cfg);
5190 if (need_stack_frame) {
5191 x86_push_reg (code, X86_EBP);
5192 cfa_offset += sizeof (gpointer);
5193 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5194 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5195 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5196 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5197 /* These are handled automatically by the stack marking code */
5198 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5200 cfg->frame_reg = X86_ESP;
5203 cfg->stack_offset += cfg->param_area;
5204 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5206 alloc_size = cfg->stack_offset;
5209 if (!method->save_lmf) {
5210 if (cfg->used_int_regs & (1 << X86_EBX)) {
5211 x86_push_reg (code, X86_EBX);
5213 cfa_offset += sizeof (gpointer);
5214 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5215 /* These are handled automatically by the stack marking code */
5216 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5219 if (cfg->used_int_regs & (1 << X86_EDI)) {
5220 x86_push_reg (code, X86_EDI);
5222 cfa_offset += sizeof (gpointer);
5223 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5224 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5227 if (cfg->used_int_regs & (1 << X86_ESI)) {
5228 x86_push_reg (code, X86_ESI);
5230 cfa_offset += sizeof (gpointer);
5231 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5232 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5238 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5239 if (mono_do_x86_stack_align && need_stack_frame) {
5240 int tot = alloc_size + pos + 4; /* ret ip */
5241 if (need_stack_frame)
5243 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5245 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5246 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5247 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5251 cfg->arch.sp_fp_offset = alloc_size + pos;
5254 /* See mono_emit_stack_alloc */
5255 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5256 guint32 remaining_size = alloc_size;
5257 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5258 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5259 guint32 offset = code - cfg->native_code;
5260 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5261 while (required_code_size >= (cfg->code_size - offset))
5262 cfg->code_size *= 2;
5263 cfg->native_code = mono_realloc_native_code(cfg);
5264 code = cfg->native_code + offset;
5265 cfg->stat_code_reallocs++;
5267 while (remaining_size >= 0x1000) {
5268 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5269 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5270 remaining_size -= 0x1000;
5273 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5275 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5278 g_assert (need_stack_frame);
5281 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5282 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5283 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5286 #if DEBUG_STACK_ALIGNMENT
5287 /* check the stack is aligned */
5288 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5289 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5290 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5291 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5292 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5293 x86_breakpoint (code);
5297 /* compute max_offset in order to use short forward jumps */
5299 if (cfg->opt & MONO_OPT_BRANCH) {
5300 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5302 bb->max_offset = max_offset;
5304 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5306 /* max alignment for loops */
5307 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5308 max_offset += LOOP_ALIGNMENT;
5309 #ifdef __native_client_codegen__
5310 /* max alignment for native client */
5311 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5312 max_offset += kNaClAlignment;
5314 MONO_BB_FOR_EACH_INS (bb, ins) {
5315 if (ins->opcode == OP_LABEL)
5316 ins->inst_c1 = max_offset;
5317 #ifdef __native_client_codegen__
5318 switch (ins->opcode)
5330 case OP_VOIDCALL_REG:
5332 case OP_FCALL_MEMBASE:
5333 case OP_LCALL_MEMBASE:
5334 case OP_VCALL_MEMBASE:
5335 case OP_VCALL2_MEMBASE:
5336 case OP_VOIDCALL_MEMBASE:
5337 case OP_CALL_MEMBASE:
5338 max_offset += kNaClAlignment;
5341 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5344 #endif /* __native_client_codegen__ */
5345 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5350 /* store runtime generic context */
5351 if (cfg->rgctx_var) {
5352 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5354 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5357 if (method->save_lmf)
5358 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5360 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5361 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5366 if (cfg->arch.ss_tramp_var) {
5367 /* Initialize ss_tramp_var */
5368 ins = cfg->arch.ss_tramp_var;
5369 g_assert (ins->opcode == OP_REGOFFSET);
5371 g_assert (!cfg->compile_aot);
5372 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&ss_trampoline, 4);
5375 if (cfg->arch.bp_tramp_var) {
5376 /* Initialize bp_tramp_var */
5377 ins = cfg->arch.bp_tramp_var;
5378 g_assert (ins->opcode == OP_REGOFFSET);
5380 g_assert (!cfg->compile_aot);
5381 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&bp_trampoline, 4);
5385 /* load arguments allocated to register from the stack */
5386 sig = mono_method_signature (method);
5389 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5390 inst = cfg->args [pos];
5391 if (inst->opcode == OP_REGVAR) {
5392 g_assert (need_stack_frame);
5393 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5394 if (cfg->verbose_level > 2)
5395 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5400 cfg->code_len = code - cfg->native_code;
5402 g_assert (cfg->code_len < cfg->code_size);
5408 mono_arch_emit_epilog (MonoCompile *cfg)
5410 MonoMethod *method = cfg->method;
5411 MonoMethodSignature *sig = mono_method_signature (method);
5413 guint32 stack_to_pop;
5415 int max_epilog_size = 16;
5417 gboolean need_stack_frame = needs_stack_frame (cfg);
5419 if (cfg->method->save_lmf)
5420 max_epilog_size += 128;
5422 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5423 cfg->code_size *= 2;
5424 cfg->native_code = mono_realloc_native_code(cfg);
5425 cfg->stat_code_reallocs++;
5428 code = cfg->native_code + cfg->code_len;
5430 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5431 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5433 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5436 if (method->save_lmf) {
5437 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5439 gboolean supported = FALSE;
5441 if (cfg->compile_aot) {
5442 #if defined(MONO_HAVE_FAST_TLS)
5445 } else if (mono_get_jit_tls_offset () != -1) {
5449 /* check if we need to restore protection of the stack after a stack overflow */
5451 if (cfg->compile_aot) {
5452 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5454 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5456 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5459 /* we load the value in a separate instruction: this mechanism may be
5460 * used later as a safer way to do thread interruption
5462 x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5463 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5465 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5466 /* note that the call trampoline will preserve eax/edx */
5467 x86_call_reg (code, X86_ECX);
5468 x86_patch (patch, code);
5470 /* FIXME: maybe save the jit tls in the prolog */
5473 /* restore caller saved regs */
5474 if (cfg->used_int_regs & (1 << X86_EBX)) {
5475 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5478 if (cfg->used_int_regs & (1 << X86_EDI)) {
5479 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5481 if (cfg->used_int_regs & (1 << X86_ESI)) {
5482 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5485 /* EBP is restored by LEAVE */
5487 for (i = 0; i < X86_NREG; ++i) {
5488 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5494 g_assert (need_stack_frame);
5495 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5499 g_assert (need_stack_frame);
5500 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5503 if (cfg->used_int_regs & (1 << X86_ESI)) {
5504 x86_pop_reg (code, X86_ESI);
5506 if (cfg->used_int_regs & (1 << X86_EDI)) {
5507 x86_pop_reg (code, X86_EDI);
5509 if (cfg->used_int_regs & (1 << X86_EBX)) {
5510 x86_pop_reg (code, X86_EBX);
5514 /* Load returned vtypes into registers if needed */
5515 cinfo = get_call_info (cfg->mempool, sig);
5516 if (cinfo->ret.storage == ArgValuetypeInReg) {
5517 for (quad = 0; quad < 2; quad ++) {
5518 switch (cinfo->ret.pair_storage [quad]) {
5520 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5522 case ArgOnFloatFpStack:
5523 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5525 case ArgOnDoubleFpStack:
5526 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5531 g_assert_not_reached ();
5536 if (need_stack_frame)
5539 if (CALLCONV_IS_STDCALL (sig)) {
5540 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5542 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
5543 } else if (cinfo->callee_stack_pop)
5544 stack_to_pop = cinfo->callee_stack_pop;
5549 g_assert (need_stack_frame);
5550 x86_ret_imm (code, stack_to_pop);
5555 cfg->code_len = code - cfg->native_code;
5557 g_assert (cfg->code_len < cfg->code_size);
5561 mono_arch_emit_exceptions (MonoCompile *cfg)
5563 MonoJumpInfo *patch_info;
5566 MonoClass *exc_classes [16];
5567 guint8 *exc_throw_start [16], *exc_throw_end [16];
5571 /* Compute needed space */
5572 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5573 if (patch_info->type == MONO_PATCH_INFO_EXC)
5578 * make sure we have enough space for exceptions
5579 * 16 is the size of two push_imm instructions and a call
5581 if (cfg->compile_aot)
5582 code_size = exc_count * 32;
5584 code_size = exc_count * 16;
5586 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5587 cfg->code_size *= 2;
5588 cfg->native_code = mono_realloc_native_code(cfg);
5589 cfg->stat_code_reallocs++;
5592 code = cfg->native_code + cfg->code_len;
5595 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5596 switch (patch_info->type) {
5597 case MONO_PATCH_INFO_EXC: {
5598 MonoClass *exc_class;
5602 x86_patch (patch_info->ip.i + cfg->native_code, code);
5604 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5605 throw_ip = patch_info->ip.i;
5607 /* Find a throw sequence for the same exception class */
5608 for (i = 0; i < nthrows; ++i)
5609 if (exc_classes [i] == exc_class)
5612 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5613 x86_jump_code (code, exc_throw_start [i]);
5614 patch_info->type = MONO_PATCH_INFO_NONE;
5619 /* Compute size of code following the push <OFFSET> */
5620 #if defined(__default_codegen__)
5622 #elif defined(__native_client_codegen__)
5623 code = mono_nacl_align (code);
5624 size = kNaClAlignment;
5626 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5628 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5629 /* Use the shorter form */
5631 x86_push_imm (code, 0);
5635 x86_push_imm (code, 0xf0f0f0f0);
5640 exc_classes [nthrows] = exc_class;
5641 exc_throw_start [nthrows] = code;
5644 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5645 patch_info->data.name = "mono_arch_throw_corlib_exception";
5646 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5647 patch_info->ip.i = code - cfg->native_code;
5648 x86_call_code (code, 0);
5649 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5654 exc_throw_end [nthrows] = code;
5666 cfg->code_len = code - cfg->native_code;
5668 g_assert (cfg->code_len < cfg->code_size);
5672 mono_arch_flush_icache (guint8 *code, gint size)
5678 mono_arch_flush_register_windows (void)
5683 mono_arch_is_inst_imm (gint64 imm)
5689 mono_arch_finish_init (void)
5691 if (!g_getenv ("MONO_NO_TLS")) {
5692 #ifndef TARGET_WIN32
5694 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5701 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5705 // Linear handler, the bsearch head compare is shorter
5706 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5707 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5708 // x86_patch(ins,target)
5709 //[1 + 5] x86_jump_mem(inst,mem)
5712 #if defined(__default_codegen__)
5713 #define BR_SMALL_SIZE 2
5714 #define BR_LARGE_SIZE 5
5715 #elif defined(__native_client_codegen__)
5716 /* I suspect the size calculation below is actually incorrect. */
5717 /* TODO: fix the calculation that uses these sizes. */
5718 #define BR_SMALL_SIZE 16
5719 #define BR_LARGE_SIZE 12
5720 #endif /*__native_client_codegen__*/
5721 #define JUMP_IMM_SIZE 6
5722 #define ENABLE_WRONG_METHOD_CHECK 0
5726 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5728 int i, distance = 0;
5729 for (i = start; i < target; ++i)
5730 distance += imt_entries [i]->chunk_size;
5735 * LOCKING: called with the domain lock held
5738 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5739 gpointer fail_tramp)
5743 guint8 *code, *start;
5746 for (i = 0; i < count; ++i) {
5747 MonoIMTCheckItem *item = imt_entries [i];
5748 if (item->is_equals) {
5749 if (item->check_target_idx) {
5750 if (!item->compare_done)
5751 item->chunk_size += CMP_SIZE;
5752 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5755 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5757 item->chunk_size += JUMP_IMM_SIZE;
5758 #if ENABLE_WRONG_METHOD_CHECK
5759 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5764 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5765 imt_entries [item->check_target_idx]->compare_done = TRUE;
5767 size += item->chunk_size;
5769 #if defined(__native_client__) && defined(__native_client_codegen__)
5770 /* In Native Client, we don't re-use thunks, allocate from the */
5771 /* normal code manager paths. */
5772 size = NACL_BUNDLE_ALIGN_UP (size);
5773 code = mono_domain_code_reserve (domain, size);
5776 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5778 code = mono_domain_code_reserve (domain, size);
5782 unwind_ops = mono_arch_get_cie_program ();
5784 for (i = 0; i < count; ++i) {
5785 MonoIMTCheckItem *item = imt_entries [i];
5786 item->code_target = code;
5787 if (item->is_equals) {
5788 if (item->check_target_idx) {
5789 if (!item->compare_done)
5790 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5791 item->jmp_code = code;
5792 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5793 if (item->has_target_code)
5794 x86_jump_code (code, item->value.target_code);
5796 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5799 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5800 item->jmp_code = code;
5801 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5802 if (item->has_target_code)
5803 x86_jump_code (code, item->value.target_code);
5805 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5806 x86_patch (item->jmp_code, code);
5807 x86_jump_code (code, fail_tramp);
5808 item->jmp_code = NULL;
5810 /* enable the commented code to assert on wrong method */
5811 #if ENABLE_WRONG_METHOD_CHECK
5812 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5813 item->jmp_code = code;
5814 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5816 if (item->has_target_code)
5817 x86_jump_code (code, item->value.target_code);
5819 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5820 #if ENABLE_WRONG_METHOD_CHECK
5821 x86_patch (item->jmp_code, code);
5822 x86_breakpoint (code);
5823 item->jmp_code = NULL;
5828 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5829 item->jmp_code = code;
5830 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5831 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5833 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5836 /* patch the branches to get to the target items */
5837 for (i = 0; i < count; ++i) {
5838 MonoIMTCheckItem *item = imt_entries [i];
5839 if (item->jmp_code) {
5840 if (item->check_target_idx) {
5841 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5847 mono_stats.imt_thunks_size += code - start;
5848 g_assert (code - start <= size);
5852 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5853 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5857 if (mono_jit_map_is_enabled ()) {
5860 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5862 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5863 mono_emit_jit_tramp (start, code - start, buff);
5867 nacl_domain_code_validate (domain, &start, size, &code);
5868 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
5870 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
5876 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5878 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5882 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5884 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5888 mono_arch_get_cie_program (void)
5892 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5893 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5899 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5901 MonoInst *ins = NULL;
5904 if (cmethod->klass == mono_defaults.math_class) {
5905 if (strcmp (cmethod->name, "Sin") == 0) {
5907 } else if (strcmp (cmethod->name, "Cos") == 0) {
5909 } else if (strcmp (cmethod->name, "Tan") == 0) {
5911 } else if (strcmp (cmethod->name, "Atan") == 0) {
5913 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5915 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5917 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5921 if (opcode && fsig->param_count == 1) {
5922 MONO_INST_NEW (cfg, ins, opcode);
5923 ins->type = STACK_R8;
5924 ins->dreg = mono_alloc_freg (cfg);
5925 ins->sreg1 = args [0]->dreg;
5926 MONO_ADD_INS (cfg->cbb, ins);
5929 if (cfg->opt & MONO_OPT_CMOV) {
5932 if (strcmp (cmethod->name, "Min") == 0) {
5933 if (fsig->params [0]->type == MONO_TYPE_I4)
5935 } else if (strcmp (cmethod->name, "Max") == 0) {
5936 if (fsig->params [0]->type == MONO_TYPE_I4)
5940 if (opcode && fsig->param_count == 2) {
5941 MONO_INST_NEW (cfg, ins, opcode);
5942 ins->type = STACK_I4;
5943 ins->dreg = mono_alloc_ireg (cfg);
5944 ins->sreg1 = args [0]->dreg;
5945 ins->sreg2 = args [1]->dreg;
5946 MONO_ADD_INS (cfg->cbb, ins);
5951 /* OP_FREM is not IEEE compatible */
5952 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
5953 MONO_INST_NEW (cfg, ins, OP_FREM);
5954 ins->inst_i0 = args [0];
5955 ins->inst_i1 = args [1];
5964 mono_arch_print_tree (MonoInst *tree, int arity)
5970 mono_arch_get_patch_offset (guint8 *code)
5972 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5974 else if (code [0] == 0xba)
5976 else if (code [0] == 0x68)
5979 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5980 /* push <OFFSET>(<REG>) */
5982 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5983 /* call *<OFFSET>(<REG>) */
5985 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5988 else if ((code [0] == 0x58) && (code [1] == 0x05))
5989 /* pop %eax; add <OFFSET>, %eax */
5991 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5992 /* pop <REG>; add <OFFSET>, <REG> */
5994 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5995 /* mov <REG>, imm */
5998 g_assert_not_reached ();
6004 * mono_breakpoint_clean_code:
6006 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6007 * breakpoints in the original code, they are removed in the copy.
6009 * Returns TRUE if no sw breakpoint was present.
6012 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6015 * If method_start is non-NULL we need to perform bound checks, since we access memory
6016 * at code - offset we could go before the start of the method and end up in a different
6017 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6020 if (!method_start || code - offset >= method_start) {
6021 memcpy (buf, code - offset, size);
6023 int diff = code - method_start;
6024 memset (buf, 0, size);
6025 memcpy (buf + offset - diff, method_start, diff + size - offset);
6031 * mono_x86_get_this_arg_offset:
6033 * Return the offset of the stack location where this is passed during a virtual
6037 mono_x86_get_this_arg_offset (MonoMethodSignature *sig)
6043 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6045 guint32 esp = regs [X86_ESP];
6052 * The stack looks like:
6056 res = ((MonoObject**)esp) [0];
6060 #define MAX_ARCH_DELEGATE_PARAMS 10
6063 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
6065 guint8 *code, *start;
6066 int code_reserve = 64;
6069 unwind_ops = mono_arch_get_cie_program ();
6072 * The stack contains:
6078 start = code = mono_global_codeman_reserve (code_reserve);
6080 /* Replace the this argument with the target */
6081 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6082 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6083 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6084 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6086 g_assert ((code - start) < code_reserve);
6089 /* 8 for mov_reg and jump, plus 8 for each parameter */
6090 #ifdef __native_client_codegen__
6091 /* TODO: calculate this size correctly */
6092 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6094 code_reserve = 8 + (param_count * 8);
6095 #endif /* __native_client_codegen__ */
6097 * The stack contains:
6098 * <args in reverse order>
6103 * <args in reverse order>
6106 * without unbalancing the stack.
6107 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6108 * and leaving original spot of first arg as placeholder in stack so
6109 * when callee pops stack everything works.
6112 start = code = mono_global_codeman_reserve (code_reserve);
6114 /* store delegate for access to method_ptr */
6115 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6118 for (i = 0; i < param_count; ++i) {
6119 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6120 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6123 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6125 g_assert ((code - start) < code_reserve);
6128 nacl_global_codeman_validate (&start, code_reserve, &code);
6131 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
6133 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
6134 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
6138 if (mono_jit_map_is_enabled ()) {
6141 buff = (char*)"delegate_invoke_has_target";
6143 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6144 mono_emit_jit_tramp (start, code - start, buff);
6148 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6153 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
6156 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
6158 guint8 *code, *start;
6163 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
6167 * The stack contains:
6171 start = code = mono_global_codeman_reserve (size);
6173 unwind_ops = mono_arch_get_cie_program ();
6175 /* Replace the this argument with the target */
6176 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6177 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6178 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6181 /* Load the IMT reg */
6182 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
6185 /* Load the vtable */
6186 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
6187 x86_jump_membase (code, X86_EAX, offset);
6188 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6191 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
6193 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
6194 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
6195 g_free (tramp_name);
6202 mono_arch_get_delegate_invoke_impls (void)
6205 MonoTrampInfo *info;
6208 get_delegate_invoke_impl (&info, TRUE, 0);
6209 res = g_slist_prepend (res, info);
6211 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
6212 get_delegate_invoke_impl (&info, FALSE, i);
6213 res = g_slist_prepend (res, info);
6216 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
6217 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
6218 res = g_slist_prepend (res, info);
6220 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
6221 res = g_slist_prepend (res, info);
6228 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6230 guint8 *code, *start;
6232 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6235 /* FIXME: Support more cases */
6236 if (MONO_TYPE_ISSTRUCT (sig->ret))
6240 * The stack contains:
6246 static guint8* cached = NULL;
6250 if (mono_aot_only) {
6251 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6253 MonoTrampInfo *info;
6254 start = get_delegate_invoke_impl (&info, TRUE, 0);
6255 mono_tramp_info_register (info, NULL);
6258 mono_memory_barrier ();
6262 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6265 for (i = 0; i < sig->param_count; ++i)
6266 if (!mono_is_regsize_var (sig->params [i]))
6269 code = cache [sig->param_count];
6273 if (mono_aot_only) {
6274 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6275 start = mono_aot_get_trampoline (name);
6278 MonoTrampInfo *info;
6279 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
6280 mono_tramp_info_register (info, NULL);
6283 mono_memory_barrier ();
6285 cache [sig->param_count] = start;
6292 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
6294 MonoTrampInfo *info;
6297 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
6299 mono_tramp_info_register (info, NULL);
6304 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6307 case X86_EAX: return ctx->eax;
6308 case X86_EBX: return ctx->ebx;
6309 case X86_ECX: return ctx->ecx;
6310 case X86_EDX: return ctx->edx;
6311 case X86_ESP: return ctx->esp;
6312 case X86_EBP: return ctx->ebp;
6313 case X86_ESI: return ctx->esi;
6314 case X86_EDI: return ctx->edi;
6316 g_assert_not_reached ();
6322 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6350 g_assert_not_reached ();
6354 #ifdef MONO_ARCH_SIMD_INTRINSICS
6357 get_float_to_x_spill_area (MonoCompile *cfg)
6359 if (!cfg->fconv_to_r8_x_var) {
6360 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6361 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6363 return cfg->fconv_to_r8_x_var;
6367 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6370 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6373 int dreg, src_opcode;
6375 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6378 switch (src_opcode = ins->opcode) {
6379 case OP_FCONV_TO_I1:
6380 case OP_FCONV_TO_U1:
6381 case OP_FCONV_TO_I2:
6382 case OP_FCONV_TO_U2:
6383 case OP_FCONV_TO_I4:
6390 /* dreg is the IREG and sreg1 is the FREG */
6391 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6392 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6393 fconv->sreg1 = ins->sreg1;
6394 fconv->dreg = mono_alloc_ireg (cfg);
6395 fconv->type = STACK_VTYPE;
6396 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6398 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6402 ins->opcode = OP_XCONV_R8_TO_I4;
6404 ins->klass = mono_defaults.int32_class;
6405 ins->sreg1 = fconv->dreg;
6407 ins->type = STACK_I4;
6408 ins->backend.source_opcode = src_opcode;
6411 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6414 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6419 if (long_ins->opcode == OP_LNEG) {
6421 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
6422 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
6423 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->dreg));
6428 #ifdef MONO_ARCH_SIMD_INTRINSICS
6430 if (!(cfg->opt & MONO_OPT_SIMD))
6433 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6434 switch (long_ins->opcode) {
6436 vreg = long_ins->sreg1;
6438 if (long_ins->inst_c0) {
6439 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6440 ins->klass = long_ins->klass;
6441 ins->sreg1 = long_ins->sreg1;
6443 ins->type = STACK_VTYPE;
6444 ins->dreg = vreg = alloc_ireg (cfg);
6445 MONO_ADD_INS (cfg->cbb, ins);
6448 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6449 ins->klass = mono_defaults.int32_class;
6451 ins->type = STACK_I4;
6452 ins->dreg = MONO_LVREG_LS (long_ins->dreg);
6453 MONO_ADD_INS (cfg->cbb, ins);
6455 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6456 ins->klass = long_ins->klass;
6457 ins->sreg1 = long_ins->sreg1;
6458 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6459 ins->type = STACK_VTYPE;
6460 ins->dreg = vreg = alloc_ireg (cfg);
6461 MONO_ADD_INS (cfg->cbb, ins);
6463 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6464 ins->klass = mono_defaults.int32_class;
6466 ins->type = STACK_I4;
6467 ins->dreg = MONO_LVREG_MS (long_ins->dreg);
6468 MONO_ADD_INS (cfg->cbb, ins);
6470 long_ins->opcode = OP_NOP;
6472 case OP_INSERTX_I8_SLOW:
6473 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6474 ins->dreg = long_ins->dreg;
6475 ins->sreg1 = long_ins->dreg;
6476 ins->sreg2 = MONO_LVREG_LS (long_ins->sreg2);
6477 ins->inst_c0 = long_ins->inst_c0 * 2;
6478 MONO_ADD_INS (cfg->cbb, ins);
6480 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6481 ins->dreg = long_ins->dreg;
6482 ins->sreg1 = long_ins->dreg;
6483 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg2);
6484 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6485 MONO_ADD_INS (cfg->cbb, ins);
6487 long_ins->opcode = OP_NOP;
6490 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6491 ins->dreg = long_ins->dreg;
6492 ins->sreg1 = MONO_LVREG_LS (long_ins->sreg1);
6493 ins->klass = long_ins->klass;
6494 ins->type = STACK_VTYPE;
6495 MONO_ADD_INS (cfg->cbb, ins);
6497 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6498 ins->dreg = long_ins->dreg;
6499 ins->sreg1 = long_ins->dreg;
6500 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg1);
6502 ins->klass = long_ins->klass;
6503 ins->type = STACK_VTYPE;
6504 MONO_ADD_INS (cfg->cbb, ins);
6506 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6507 ins->dreg = long_ins->dreg;
6508 ins->sreg1 = long_ins->dreg;;
6509 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6510 ins->klass = long_ins->klass;
6511 ins->type = STACK_VTYPE;
6512 MONO_ADD_INS (cfg->cbb, ins);
6514 long_ins->opcode = OP_NOP;
6517 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6520 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6522 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6525 gpointer *sp, old_value;
6528 offset = clause->exvar_offset;
6531 bp = MONO_CONTEXT_GET_BP (ctx);
6532 sp = *(gpointer*)(bp + offset);
6535 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6544 * mono_aot_emit_load_got_addr:
6546 * Emit code to load the got address.
6547 * On x86, the result is placed into EBX.
6550 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6552 x86_call_imm (code, 0);
6554 * The patch needs to point to the pop, since the GOT offset needs
6555 * to be added to that address.
6558 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6560 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6561 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6562 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6568 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6571 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6573 g_assert_not_reached ();
6574 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6579 * mono_arch_emit_load_aotconst:
6581 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6582 * TARGET from the mscorlib GOT in full-aot code.
6583 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6587 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
6589 /* Load the mscorlib got address */
6590 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6591 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6592 /* arch_emit_got_access () patches this */
6593 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6598 /* Can't put this into mini-x86.h */
6600 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6603 mono_arch_get_trampolines (gboolean aot)
6605 MonoTrampInfo *info;
6606 GSList *tramps = NULL;
6608 mono_x86_get_signal_exception_trampoline (&info, aot);
6610 tramps = g_slist_append (tramps, info);
6615 /* Soft Debug support */
6616 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6619 * mono_arch_set_breakpoint:
6621 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6622 * The location should contain code emitted by OP_SEQ_POINT.
6625 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6627 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6629 g_assert (code [0] == 0x90);
6630 x86_call_membase (code, X86_ECX, 0);
6634 * mono_arch_clear_breakpoint:
6636 * Clear the breakpoint at IP.
6639 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6641 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6644 for (i = 0; i < 2; ++i)
6649 * mono_arch_start_single_stepping:
6651 * Start single stepping.
6654 mono_arch_start_single_stepping (void)
6656 ss_trampoline = mini_get_single_step_trampoline ();
6660 * mono_arch_stop_single_stepping:
6662 * Stop single stepping.
6665 mono_arch_stop_single_stepping (void)
6667 ss_trampoline = NULL;
6671 * mono_arch_is_single_step_event:
6673 * Return whenever the machine state in SIGCTX corresponds to a single
6677 mono_arch_is_single_step_event (void *info, void *sigctx)
6679 /* We use soft breakpoints */
6684 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6686 /* We use soft breakpoints */
6690 #define BREAKPOINT_SIZE 2
6693 * mono_arch_skip_breakpoint:
6695 * See mini-amd64.c for docs.
6698 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6700 g_assert_not_reached ();
6704 * mono_arch_skip_single_step:
6706 * See mini-amd64.c for docs.
6709 mono_arch_skip_single_step (MonoContext *ctx)
6711 g_assert_not_reached ();
6715 * mono_arch_get_seq_point_info:
6717 * See mini-amd64.c for docs.
6720 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6727 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6729 ext->lmf.previous_lmf = (gsize)prev_lmf;
6730 /* Mark that this is a MonoLMFExt */
6731 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6732 ext->lmf.ebp = (gssize)ext;
6738 mono_arch_opcode_supported (int opcode)
6741 case OP_ATOMIC_ADD_I4:
6742 case OP_ATOMIC_EXCHANGE_I4:
6743 case OP_ATOMIC_CAS_I4:
6744 case OP_ATOMIC_LOAD_I1:
6745 case OP_ATOMIC_LOAD_I2:
6746 case OP_ATOMIC_LOAD_I4:
6747 case OP_ATOMIC_LOAD_U1:
6748 case OP_ATOMIC_LOAD_U2:
6749 case OP_ATOMIC_LOAD_U4:
6750 case OP_ATOMIC_LOAD_R4:
6751 case OP_ATOMIC_LOAD_R8:
6752 case OP_ATOMIC_STORE_I1:
6753 case OP_ATOMIC_STORE_I2:
6754 case OP_ATOMIC_STORE_I4:
6755 case OP_ATOMIC_STORE_U1:
6756 case OP_ATOMIC_STORE_U2:
6757 case OP_ATOMIC_STORE_U4:
6758 case OP_ATOMIC_STORE_R4:
6759 case OP_ATOMIC_STORE_R8:
6767 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
6769 return get_call_info (mp, sig);