2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * (C) 2003 Ximian, Inc.
18 #include <mono/metadata/appdomain.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/metadata/threads.h>
21 #include <mono/metadata/profiler-private.h>
22 #include <mono/metadata/mono-debug.h>
23 #include <mono/utils/mono-math.h>
24 #include <mono/utils/mono-counters.h>
31 /* On windows, these hold the key returned by TlsAlloc () */
32 static gint lmf_tls_offset = -1;
33 static gint lmf_addr_tls_offset = -1;
34 static gint appdomain_tls_offset = -1;
35 static gint thread_tls_offset = -1;
38 static gboolean optimize_for_xen = TRUE;
40 #define optimize_for_xen 0
44 static gboolean is_win32 = TRUE;
46 static gboolean is_win32 = FALSE;
49 /* This mutex protects architecture specific caches */
50 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
51 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
52 static CRITICAL_SECTION mini_arch_mutex;
54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
59 /* Under windows, the default pinvoke calling convention is stdcall */
60 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT))
62 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL)
66 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
69 mono_arch_regname (int reg)
72 case X86_EAX: return "%eax";
73 case X86_EBX: return "%ebx";
74 case X86_ECX: return "%ecx";
75 case X86_EDX: return "%edx";
76 case X86_ESP: return "%esp";
77 case X86_EBP: return "%ebp";
78 case X86_EDI: return "%edi";
79 case X86_ESI: return "%esi";
85 mono_arch_fregname (int reg)
110 mono_arch_xregname (int reg)
151 /* Only if storage == ArgValuetypeInReg */
152 ArgStorage pair_storage [2];
161 gboolean need_stack_align;
162 guint32 stack_align_amount;
170 #define FLOAT_PARAM_REGS 0
172 static X86_Reg_No param_regs [] = { 0 };
174 #if defined(PLATFORM_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
175 #define SMALL_STRUCTS_IN_REGS
176 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
180 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
182 ainfo->offset = *stack_size;
184 if (*gr >= PARAM_REGS) {
185 ainfo->storage = ArgOnStack;
186 (*stack_size) += sizeof (gpointer);
189 ainfo->storage = ArgInIReg;
190 ainfo->reg = param_regs [*gr];
196 add_general_pair (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
198 ainfo->offset = *stack_size;
200 g_assert (PARAM_REGS == 0);
202 ainfo->storage = ArgOnStack;
203 (*stack_size) += sizeof (gpointer) * 2;
207 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
209 ainfo->offset = *stack_size;
211 if (*gr >= FLOAT_PARAM_REGS) {
212 ainfo->storage = ArgOnStack;
213 (*stack_size) += is_double ? 8 : 4;
216 /* A double register */
218 ainfo->storage = ArgInDoubleSSEReg;
220 ainfo->storage = ArgInFloatSSEReg;
228 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
230 guint32 *gr, guint32 *fr, guint32 *stack_size)
235 klass = mono_class_from_mono_type (type);
236 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
238 #ifdef SMALL_STRUCTS_IN_REGS
239 if (sig->pinvoke && is_return) {
240 MonoMarshalType *info;
243 * the exact rules are not very well documented, the code below seems to work with the
244 * code generated by gcc 3.3.3 -mno-cygwin.
246 info = mono_marshal_load_type_info (klass);
249 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
251 /* Special case structs with only a float member */
252 if ((info->native_size == 8) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R8)) {
253 ainfo->storage = ArgValuetypeInReg;
254 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
257 if ((info->native_size == 4) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R4)) {
258 ainfo->storage = ArgValuetypeInReg;
259 ainfo->pair_storage [0] = ArgOnFloatFpStack;
262 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
263 ainfo->storage = ArgValuetypeInReg;
264 ainfo->pair_storage [0] = ArgInIReg;
265 ainfo->pair_regs [0] = return_regs [0];
266 if (info->native_size > 4) {
267 ainfo->pair_storage [1] = ArgInIReg;
268 ainfo->pair_regs [1] = return_regs [1];
275 ainfo->offset = *stack_size;
276 ainfo->storage = ArgOnStack;
277 *stack_size += ALIGN_TO (size, sizeof (gpointer));
283 * Obtain information about a call according to the calling convention.
284 * For x86 ELF, see the "System V Application Binary Interface Intel386
285 * Architecture Processor Supplment, Fourth Edition" document for more
287 * For x86 win32, see ???.
290 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
294 int n = sig->hasthis + sig->param_count;
295 guint32 stack_size = 0;
299 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
301 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
308 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
309 switch (ret_type->type) {
310 case MONO_TYPE_BOOLEAN:
321 case MONO_TYPE_FNPTR:
322 case MONO_TYPE_CLASS:
323 case MONO_TYPE_OBJECT:
324 case MONO_TYPE_SZARRAY:
325 case MONO_TYPE_ARRAY:
326 case MONO_TYPE_STRING:
327 cinfo->ret.storage = ArgInIReg;
328 cinfo->ret.reg = X86_EAX;
332 cinfo->ret.storage = ArgInIReg;
333 cinfo->ret.reg = X86_EAX;
336 cinfo->ret.storage = ArgOnFloatFpStack;
339 cinfo->ret.storage = ArgOnDoubleFpStack;
341 case MONO_TYPE_GENERICINST:
342 if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
343 cinfo->ret.storage = ArgInIReg;
344 cinfo->ret.reg = X86_EAX;
348 case MONO_TYPE_VALUETYPE: {
349 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
351 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
352 if (cinfo->ret.storage == ArgOnStack)
353 /* The caller passes the address where the value is stored */
354 add_general (&gr, &stack_size, &cinfo->ret);
357 case MONO_TYPE_TYPEDBYREF:
358 /* Same as a valuetype with size 24 */
359 add_general (&gr, &stack_size, &cinfo->ret);
363 cinfo->ret.storage = ArgNone;
366 g_error ("Can't handle as return value 0x%x", sig->ret->type);
372 add_general (&gr, &stack_size, cinfo->args + 0);
374 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
376 fr = FLOAT_PARAM_REGS;
378 /* Emit the signature cookie just before the implicit arguments */
379 add_general (&gr, &stack_size, &cinfo->sig_cookie);
382 for (i = 0; i < sig->param_count; ++i) {
383 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
386 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
387 /* We allways pass the sig cookie on the stack for simplicity */
389 * Prevent implicit arguments + the sig cookie from being passed
393 fr = FLOAT_PARAM_REGS;
395 /* Emit the signature cookie just before the implicit arguments */
396 add_general (&gr, &stack_size, &cinfo->sig_cookie);
399 if (sig->params [i]->byref) {
400 add_general (&gr, &stack_size, ainfo);
403 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
404 switch (ptype->type) {
405 case MONO_TYPE_BOOLEAN:
408 add_general (&gr, &stack_size, ainfo);
413 add_general (&gr, &stack_size, ainfo);
417 add_general (&gr, &stack_size, ainfo);
422 case MONO_TYPE_FNPTR:
423 case MONO_TYPE_CLASS:
424 case MONO_TYPE_OBJECT:
425 case MONO_TYPE_STRING:
426 case MONO_TYPE_SZARRAY:
427 case MONO_TYPE_ARRAY:
428 add_general (&gr, &stack_size, ainfo);
430 case MONO_TYPE_GENERICINST:
431 if (!mono_type_generic_inst_is_valuetype (sig->params [i])) {
432 add_general (&gr, &stack_size, ainfo);
436 case MONO_TYPE_VALUETYPE:
437 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
439 case MONO_TYPE_TYPEDBYREF:
440 stack_size += sizeof (MonoTypedRef);
441 ainfo->storage = ArgOnStack;
445 add_general_pair (&gr, &stack_size, ainfo);
448 add_float (&fr, &stack_size, ainfo, FALSE);
451 add_float (&fr, &stack_size, ainfo, TRUE);
454 g_error ("unexpected type 0x%x", ptype->type);
455 g_assert_not_reached ();
459 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
461 fr = FLOAT_PARAM_REGS;
463 /* Emit the signature cookie just before the implicit arguments */
464 add_general (&gr, &stack_size, &cinfo->sig_cookie);
467 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
468 cinfo->need_stack_align = TRUE;
469 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
470 stack_size += cinfo->stack_align_amount;
473 cinfo->stack_usage = stack_size;
474 cinfo->reg_usage = gr;
475 cinfo->freg_usage = fr;
480 * mono_arch_get_argument_info:
481 * @csig: a method signature
482 * @param_count: the number of parameters to consider
483 * @arg_info: an array to store the result infos
485 * Gathers information on parameters such as size, alignment and
486 * padding. arg_info should be large enought to hold param_count + 1 entries.
488 * Returns the size of the argument area on the stack.
491 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
493 int k, args_size = 0;
499 cinfo = get_call_info (NULL, NULL, csig, FALSE);
501 if (MONO_TYPE_ISSTRUCT (csig->ret) && (cinfo->ret.storage == ArgOnStack)) {
502 args_size += sizeof (gpointer);
506 arg_info [0].offset = offset;
509 args_size += sizeof (gpointer);
513 arg_info [0].size = args_size;
515 for (k = 0; k < param_count; k++) {
516 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
518 /* ignore alignment for now */
521 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
522 arg_info [k].pad = pad;
524 arg_info [k + 1].pad = 0;
525 arg_info [k + 1].size = size;
527 arg_info [k + 1].offset = offset;
531 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
532 align = MONO_ARCH_FRAME_ALIGNMENT;
535 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
536 arg_info [k].pad = pad;
543 static const guchar cpuid_impl [] = {
544 0x55, /* push %ebp */
545 0x89, 0xe5, /* mov %esp,%ebp */
546 0x53, /* push %ebx */
547 0x8b, 0x45, 0x08, /* mov 0x8(%ebp),%eax */
548 0x0f, 0xa2, /* cpuid */
549 0x50, /* push %eax */
550 0x8b, 0x45, 0x10, /* mov 0x10(%ebp),%eax */
551 0x89, 0x18, /* mov %ebx,(%eax) */
552 0x8b, 0x45, 0x14, /* mov 0x14(%ebp),%eax */
553 0x89, 0x08, /* mov %ecx,(%eax) */
554 0x8b, 0x45, 0x18, /* mov 0x18(%ebp),%eax */
555 0x89, 0x10, /* mov %edx,(%eax) */
557 0x8b, 0x55, 0x0c, /* mov 0xc(%ebp),%edx */
558 0x89, 0x02, /* mov %eax,(%edx) */
564 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
567 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
571 __asm__ __volatile__ (
574 "movl %%eax, %%edx\n"
575 "xorl $0x200000, %%eax\n"
580 "xorl %%edx, %%eax\n"
581 "andl $0x200000, %%eax\n"
603 /* Have to use the code manager to get around WinXP DEP */
604 static CpuidFunc func = NULL;
607 ptr = mono_global_codeman_reserve (sizeof (cpuid_impl));
608 memcpy (ptr, cpuid_impl, sizeof (cpuid_impl));
609 func = (CpuidFunc)ptr;
611 func (id, p_eax, p_ebx, p_ecx, p_edx);
614 * We use this approach because of issues with gcc and pic code, see:
615 * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
616 __asm__ __volatile__ ("cpuid"
617 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
626 * Initialize the cpu to execute managed code.
629 mono_arch_cpu_init (void)
631 /* spec compliance requires running with double precision */
635 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
636 fpcw &= ~X86_FPCW_PRECC_MASK;
637 fpcw |= X86_FPCW_PREC_DOUBLE;
638 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
639 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
641 _control87 (_PC_53, MCW_PC);
646 * Initialize architecture specific code.
649 mono_arch_init (void)
651 InitializeCriticalSection (&mini_arch_mutex);
655 * Cleanup architecture specific code.
658 mono_arch_cleanup (void)
660 DeleteCriticalSection (&mini_arch_mutex);
664 * This function returns the optimizations supported on this cpu.
667 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
669 int eax, ebx, ecx, edx;
673 /* Feature Flags function, flags returned in EDX. */
674 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
675 if (edx & (1 << 15)) {
676 opts |= MONO_OPT_CMOV;
678 opts |= MONO_OPT_FCMOV;
680 *exclude_mask |= MONO_OPT_FCMOV;
682 *exclude_mask |= MONO_OPT_CMOV;
684 opts |= MONO_OPT_SSE2;
686 *exclude_mask |= MONO_OPT_SSE2;
688 #ifdef MONO_ARCH_SIMD_INTRINSICS
689 /*SIMD intrinsics require at least SSE2.*/
690 if (!(opts & MONO_OPT_SSE2))
691 *exclude_mask |= MONO_OPT_SIMD;
698 * This function test for all SSE functions supported.
700 * Returns a bitmask corresponding to all supported versions.
702 * TODO detect other versions like SSE4a.
705 mono_arch_cpu_enumerate_simd_versions (void)
707 int eax, ebx, ecx, edx;
708 guint32 sse_opts = 0;
710 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
712 sse_opts |= 1 << SIMD_VERSION_SSE1;
714 sse_opts |= 1 << SIMD_VERSION_SSE2;
716 sse_opts |= 1 << SIMD_VERSION_SSE3;
718 sse_opts |= 1 << SIMD_VERSION_SSSE3;
720 sse_opts |= 1 << SIMD_VERSION_SSE41;
722 sse_opts |= 1 << SIMD_VERSION_SSE42;
728 * Determine whenever the trap whose info is in SIGINFO is caused by
732 mono_arch_is_int_overflow (void *sigctx, void *info)
737 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
739 ip = (guint8*)ctx.eip;
741 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
745 switch (x86_modrm_rm (ip [1])) {
765 g_assert_not_reached ();
777 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
782 for (i = 0; i < cfg->num_varinfo; i++) {
783 MonoInst *ins = cfg->varinfo [i];
784 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
787 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
790 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
791 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
794 /* we dont allocate I1 to registers because there is no simply way to sign extend
795 * 8bit quantities in caller saved registers on x86 */
796 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
797 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
798 g_assert (i == vmv->idx);
799 vars = g_list_prepend (vars, vmv);
803 vars = mono_varlist_sort (cfg, vars, 0);
809 mono_arch_get_global_int_regs (MonoCompile *cfg)
813 /* we can use 3 registers for global allocation */
814 regs = g_list_prepend (regs, (gpointer)X86_EBX);
815 regs = g_list_prepend (regs, (gpointer)X86_ESI);
816 regs = g_list_prepend (regs, (gpointer)X86_EDI);
822 * mono_arch_regalloc_cost:
824 * Return the cost, in number of memory references, of the action of
825 * allocating the variable VMV into a register during global register
829 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
831 MonoInst *ins = cfg->varinfo [vmv->idx];
833 if (cfg->method->save_lmf)
834 /* The register is already saved */
835 return (ins->opcode == OP_ARG) ? 1 : 0;
837 /* push+pop+possible load if it is an argument */
838 return (ins->opcode == OP_ARG) ? 3 : 2;
842 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
844 static int inited = FALSE;
845 static int count = 0;
847 if (cfg->arch.need_stack_frame_inited) {
848 g_assert (cfg->arch.need_stack_frame == flag);
852 cfg->arch.need_stack_frame = flag;
853 cfg->arch.need_stack_frame_inited = TRUE;
859 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
864 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
868 needs_stack_frame (MonoCompile *cfg)
870 MonoMethodSignature *sig;
871 MonoMethodHeader *header;
872 gboolean result = FALSE;
874 if (cfg->arch.need_stack_frame_inited)
875 return cfg->arch.need_stack_frame;
877 header = mono_method_get_header (cfg->method);
878 sig = mono_method_signature (cfg->method);
880 if (cfg->disable_omit_fp)
882 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
884 else if (cfg->method->save_lmf)
886 else if (cfg->stack_offset)
888 else if (cfg->param_area)
890 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
892 else if (header->num_clauses)
894 else if (sig->param_count + sig->hasthis)
896 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
898 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
899 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
902 set_needs_stack_frame (cfg, result);
904 return cfg->arch.need_stack_frame;
908 * Set var information according to the calling convention. X86 version.
909 * The locals var stuff should most likely be split in another method.
912 mono_arch_allocate_vars (MonoCompile *cfg)
914 MonoMethodSignature *sig;
915 MonoMethodHeader *header;
917 guint32 locals_stack_size, locals_stack_align;
922 header = mono_method_get_header (cfg->method);
923 sig = mono_method_signature (cfg->method);
925 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
927 cfg->frame_reg = X86_EBP;
930 /* Reserve space to save LMF and caller saved registers */
932 if (cfg->method->save_lmf) {
933 offset += sizeof (MonoLMF);
935 if (cfg->used_int_regs & (1 << X86_EBX)) {
939 if (cfg->used_int_regs & (1 << X86_EDI)) {
943 if (cfg->used_int_regs & (1 << X86_ESI)) {
948 switch (cinfo->ret.storage) {
949 case ArgValuetypeInReg:
950 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
952 cfg->ret->opcode = OP_REGOFFSET;
953 cfg->ret->inst_basereg = X86_EBP;
954 cfg->ret->inst_offset = - offset;
960 /* Allocate locals */
961 offsets = mono_allocate_stack_slots (cfg, &locals_stack_size, &locals_stack_align);
962 if (locals_stack_align) {
963 offset += (locals_stack_align - 1);
964 offset &= ~(locals_stack_align - 1);
967 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
968 * have locals larger than 8 bytes we need to make sure that
969 * they have the appropriate offset.
971 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
972 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
973 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
974 if (offsets [i] != -1) {
975 MonoInst *inst = cfg->varinfo [i];
976 inst->opcode = OP_REGOFFSET;
977 inst->inst_basereg = X86_EBP;
978 inst->inst_offset = - (offset + offsets [i]);
979 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
982 offset += locals_stack_size;
986 * Allocate arguments+return value
989 switch (cinfo->ret.storage) {
991 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
993 * In the new IR, the cfg->vret_addr variable represents the
994 * vtype return value.
996 cfg->vret_addr->opcode = OP_REGOFFSET;
997 cfg->vret_addr->inst_basereg = cfg->frame_reg;
998 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
999 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1000 printf ("vret_addr =");
1001 mono_print_ins (cfg->vret_addr);
1004 cfg->ret->opcode = OP_REGOFFSET;
1005 cfg->ret->inst_basereg = X86_EBP;
1006 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1009 case ArgValuetypeInReg:
1012 cfg->ret->opcode = OP_REGVAR;
1013 cfg->ret->inst_c0 = cinfo->ret.reg;
1014 cfg->ret->dreg = cinfo->ret.reg;
1017 case ArgOnFloatFpStack:
1018 case ArgOnDoubleFpStack:
1021 g_assert_not_reached ();
1024 if (sig->call_convention == MONO_CALL_VARARG) {
1025 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1026 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1029 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1030 ArgInfo *ainfo = &cinfo->args [i];
1031 inst = cfg->args [i];
1032 if (inst->opcode != OP_REGVAR) {
1033 inst->opcode = OP_REGOFFSET;
1034 inst->inst_basereg = X86_EBP;
1036 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1039 cfg->stack_offset = offset;
1043 mono_arch_create_vars (MonoCompile *cfg)
1045 MonoMethodSignature *sig;
1048 sig = mono_method_signature (cfg->method);
1050 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1052 if (cinfo->ret.storage == ArgValuetypeInReg)
1053 cfg->ret_var_is_local = TRUE;
1054 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1055 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1060 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1061 * so we try to do it just once when we have multiple fp arguments in a row.
1062 * We don't use this mechanism generally because for int arguments the generated code
1063 * is slightly bigger and new generation cpus optimize away the dependency chains
1064 * created by push instructions on the esp value.
1065 * fp_arg_setup is the first argument in the execution sequence where the esp register
1068 static G_GNUC_UNUSED int
1069 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1074 for (; start_arg < sig->param_count; ++start_arg) {
1075 t = mini_type_get_underlying_type (NULL, sig->params [start_arg]);
1076 if (!t->byref && t->type == MONO_TYPE_R8) {
1077 fp_space += sizeof (double);
1078 *fp_arg_setup = start_arg;
1087 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1089 MonoMethodSignature *tmp_sig;
1091 /* FIXME: Add support for signature tokens to AOT */
1092 cfg->disable_aot = TRUE;
1095 * mono_ArgIterator_Setup assumes the signature cookie is
1096 * passed first and all the arguments which were before it are
1097 * passed on the stack after the signature. So compensate by
1098 * passing a different signature.
1100 tmp_sig = mono_metadata_signature_dup (call->signature);
1101 tmp_sig->param_count -= call->signature->sentinelpos;
1102 tmp_sig->sentinelpos = 0;
1103 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1105 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1110 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1116 LLVMCallInfo *linfo;
1118 n = sig->param_count + sig->hasthis;
1120 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1122 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1125 * LLVM always uses the native ABI while we use our own ABI, the
1126 * only difference is the handling of vtypes:
1127 * - we only pass/receive them in registers in some cases, and only
1128 * in 1 or 2 integer registers.
1130 if (cinfo->ret.storage == ArgValuetypeInReg) {
1132 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1133 cfg->disable_llvm = TRUE;
1137 cfg->exception_message = g_strdup ("vtype ret in call");
1138 cfg->disable_llvm = TRUE;
1140 linfo->ret.storage = LLVMArgVtypeInReg;
1141 for (j = 0; j < 2; ++j)
1142 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1146 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1147 /* Vtype returned using a hidden argument */
1148 linfo->ret.storage = LLVMArgVtypeRetAddr;
1151 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != ArgInIReg) {
1153 cfg->exception_message = g_strdup ("vtype ret in call");
1154 cfg->disable_llvm = TRUE;
1157 for (i = 0; i < n; ++i) {
1158 ainfo = cinfo->args + i;
1160 linfo->args [i].storage = LLVMArgNone;
1162 switch (ainfo->storage) {
1164 linfo->args [i].storage = LLVMArgInIReg;
1166 case ArgInDoubleSSEReg:
1167 case ArgInFloatSSEReg:
1168 linfo->args [i].storage = LLVMArgInFPReg;
1171 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1172 linfo->args [i].storage = LLVMArgVtypeByVal;
1174 linfo->args [i].storage = LLVMArgInIReg;
1175 if (!sig->params [i - sig->hasthis]->byref) {
1176 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1177 linfo->args [i].storage = LLVMArgInFPReg;
1178 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1179 linfo->args [i].storage = LLVMArgInFPReg;
1184 case ArgValuetypeInReg:
1186 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1187 cfg->disable_llvm = TRUE;
1191 cfg->exception_message = g_strdup ("vtype arg");
1192 cfg->disable_llvm = TRUE;
1194 linfo->args [i].storage = LLVMArgVtypeInReg;
1195 for (j = 0; j < 2; ++j)
1196 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1200 cfg->exception_message = g_strdup ("ainfo->storage");
1201 cfg->disable_llvm = TRUE;
1211 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1214 MonoMethodSignature *sig;
1217 int sentinelpos = 0;
1219 sig = call->signature;
1220 n = sig->param_count + sig->hasthis;
1222 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1224 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1225 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1227 if (cinfo->need_stack_align) {
1228 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1229 arg->dreg = X86_ESP;
1230 arg->sreg1 = X86_ESP;
1231 arg->inst_imm = cinfo->stack_align_amount;
1232 MONO_ADD_INS (cfg->cbb, arg);
1235 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1238 if (cinfo->ret.storage == ArgValuetypeInReg) {
1239 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
1241 * Tell the JIT to use a more efficient calling convention: call using
1242 * OP_CALL, compute the result location after the call, and save the
1245 call->vret_in_reg = TRUE;
1248 * The valuetype is in EAX:EDX after the call, needs to be copied to
1249 * the stack. Save the address here, so the call instruction can
1252 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1253 vtarg->sreg1 = call->vret_var->dreg;
1254 MONO_ADD_INS (cfg->cbb, vtarg);
1259 /* Handle the case where there are no implicit arguments */
1260 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1261 emit_sig_cookie (cfg, call, cinfo);
1264 /* Arguments are pushed in the reverse order */
1265 for (i = n - 1; i >= 0; i --) {
1266 ArgInfo *ainfo = cinfo->args + i;
1269 if (i >= sig->hasthis)
1270 t = sig->params [i - sig->hasthis];
1272 t = &mono_defaults.int_class->byval_arg;
1273 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1275 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1277 in = call->args [i];
1278 arg->cil_code = in->cil_code;
1279 arg->sreg1 = in->dreg;
1280 arg->type = in->type;
1282 g_assert (in->dreg != -1);
1284 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1288 g_assert (in->klass);
1290 if (t->type == MONO_TYPE_TYPEDBYREF) {
1291 size = sizeof (MonoTypedRef);
1292 align = sizeof (gpointer);
1295 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1299 arg->opcode = OP_OUTARG_VT;
1300 arg->sreg1 = in->dreg;
1301 arg->klass = in->klass;
1302 arg->backend.size = size;
1304 MONO_ADD_INS (cfg->cbb, arg);
1308 switch (ainfo->storage) {
1310 arg->opcode = OP_X86_PUSH;
1312 if (t->type == MONO_TYPE_R4) {
1313 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1314 arg->opcode = OP_STORER4_MEMBASE_REG;
1315 arg->inst_destbasereg = X86_ESP;
1316 arg->inst_offset = 0;
1317 } else if (t->type == MONO_TYPE_R8) {
1318 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1319 arg->opcode = OP_STORER8_MEMBASE_REG;
1320 arg->inst_destbasereg = X86_ESP;
1321 arg->inst_offset = 0;
1322 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1324 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1329 g_assert_not_reached ();
1332 MONO_ADD_INS (cfg->cbb, arg);
1335 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1336 /* Emit the signature cookie just before the implicit arguments */
1337 emit_sig_cookie (cfg, call, cinfo);
1341 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1344 if (cinfo->ret.storage == ArgValuetypeInReg) {
1347 else if (cinfo->ret.storage == ArgInIReg) {
1349 /* The return address is passed in a register */
1350 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1351 vtarg->sreg1 = call->inst.dreg;
1352 vtarg->dreg = mono_alloc_ireg (cfg);
1353 MONO_ADD_INS (cfg->cbb, vtarg);
1355 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1358 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1359 vtarg->type = STACK_MP;
1360 vtarg->sreg1 = call->vret_var->dreg;
1361 MONO_ADD_INS (cfg->cbb, vtarg);
1364 /* if the function returns a struct, the called method already does a ret $0x4 */
1365 cinfo->stack_usage -= 4;
1368 call->stack_usage = cinfo->stack_usage;
1372 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1375 int size = ins->backend.size;
1378 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1379 arg->sreg1 = src->dreg;
1381 MONO_ADD_INS (cfg->cbb, arg);
1382 } else if (size <= 20) {
1383 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1384 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1386 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1387 arg->inst_basereg = src->dreg;
1388 arg->inst_offset = 0;
1389 arg->inst_imm = size;
1391 MONO_ADD_INS (cfg->cbb, arg);
1396 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1398 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1401 if (ret->type == MONO_TYPE_R4) {
1402 if (COMPILE_LLVM (cfg))
1403 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1406 } else if (ret->type == MONO_TYPE_R8) {
1407 if (COMPILE_LLVM (cfg))
1408 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1411 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1412 if (COMPILE_LLVM (cfg))
1413 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1415 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1416 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1422 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1426 * Allow tracing to work with this interface (with an optional argument)
1429 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1433 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1434 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1436 /* if some args are passed in registers, we need to save them here */
1437 x86_push_reg (code, X86_EBP);
1439 if (cfg->compile_aot) {
1440 x86_push_imm (code, cfg->method);
1441 x86_mov_reg_imm (code, X86_EAX, func);
1442 x86_call_reg (code, X86_EAX);
1444 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1445 x86_push_imm (code, cfg->method);
1446 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1447 x86_call_code (code, 0);
1449 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1463 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1466 int arg_size = 0, save_mode = SAVE_NONE;
1467 MonoMethod *method = cfg->method;
1469 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret)->type) {
1470 case MONO_TYPE_VOID:
1471 /* special case string .ctor icall */
1472 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
1473 save_mode = SAVE_EAX;
1475 save_mode = SAVE_NONE;
1479 save_mode = SAVE_EAX_EDX;
1483 save_mode = SAVE_FP;
1485 case MONO_TYPE_GENERICINST:
1486 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
1487 save_mode = SAVE_EAX;
1491 case MONO_TYPE_VALUETYPE:
1492 save_mode = SAVE_STRUCT;
1495 save_mode = SAVE_EAX;
1499 switch (save_mode) {
1501 x86_push_reg (code, X86_EDX);
1502 x86_push_reg (code, X86_EAX);
1503 if (enable_arguments) {
1504 x86_push_reg (code, X86_EDX);
1505 x86_push_reg (code, X86_EAX);
1510 x86_push_reg (code, X86_EAX);
1511 if (enable_arguments) {
1512 x86_push_reg (code, X86_EAX);
1517 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1518 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1519 if (enable_arguments) {
1520 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1521 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1526 if (enable_arguments) {
1527 x86_push_membase (code, X86_EBP, 8);
1536 if (cfg->compile_aot) {
1537 x86_push_imm (code, method);
1538 x86_mov_reg_imm (code, X86_EAX, func);
1539 x86_call_reg (code, X86_EAX);
1541 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1542 x86_push_imm (code, method);
1543 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1544 x86_call_code (code, 0);
1546 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1548 switch (save_mode) {
1550 x86_pop_reg (code, X86_EAX);
1551 x86_pop_reg (code, X86_EDX);
1554 x86_pop_reg (code, X86_EAX);
1557 x86_fld_membase (code, X86_ESP, 0, TRUE);
1558 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1568 #define EMIT_COND_BRANCH(ins,cond,sign) \
1569 if (ins->inst_true_bb->native_offset) { \
1570 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1572 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1573 if ((cfg->opt & MONO_OPT_BRANCH) && \
1574 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1575 x86_branch8 (code, cond, 0, sign); \
1577 x86_branch32 (code, cond, 0, sign); \
1581 * Emit an exception if condition is fail and
1582 * if possible do a directly branch to target
1584 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1586 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1587 if (tins == NULL) { \
1588 mono_add_patch_info (cfg, code - cfg->native_code, \
1589 MONO_PATCH_INFO_EXC, exc_name); \
1590 x86_branch32 (code, cond, 0, signed); \
1592 EMIT_COND_BRANCH (tins, cond, signed); \
1596 #define EMIT_FPCOMPARE(code) do { \
1597 x86_fcompp (code); \
1598 x86_fnstsw (code); \
1603 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1605 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1606 x86_call_code (code, 0);
1611 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1614 * mono_peephole_pass_1:
1616 * Perform peephole opts which should/can be performed before local regalloc
1619 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1623 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1624 MonoInst *last_ins = ins->prev;
1626 switch (ins->opcode) {
1629 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1631 * X86_LEA is like ADD, but doesn't have the
1632 * sreg1==dreg restriction.
1634 ins->opcode = OP_X86_LEA_MEMBASE;
1635 ins->inst_basereg = ins->sreg1;
1636 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1637 ins->opcode = OP_X86_INC_REG;
1641 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1642 ins->opcode = OP_X86_LEA_MEMBASE;
1643 ins->inst_basereg = ins->sreg1;
1644 ins->inst_imm = -ins->inst_imm;
1645 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1646 ins->opcode = OP_X86_DEC_REG;
1648 case OP_COMPARE_IMM:
1649 case OP_ICOMPARE_IMM:
1650 /* OP_COMPARE_IMM (reg, 0)
1652 * OP_X86_TEST_NULL (reg)
1655 ins->opcode = OP_X86_TEST_NULL;
1657 case OP_X86_COMPARE_MEMBASE_IMM:
1659 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1660 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1662 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1663 * OP_COMPARE_IMM reg, imm
1665 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1667 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1668 ins->inst_basereg == last_ins->inst_destbasereg &&
1669 ins->inst_offset == last_ins->inst_offset) {
1670 ins->opcode = OP_COMPARE_IMM;
1671 ins->sreg1 = last_ins->sreg1;
1673 /* check if we can remove cmp reg,0 with test null */
1675 ins->opcode = OP_X86_TEST_NULL;
1679 case OP_X86_PUSH_MEMBASE:
1680 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1681 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1682 ins->inst_basereg == last_ins->inst_destbasereg &&
1683 ins->inst_offset == last_ins->inst_offset) {
1684 ins->opcode = OP_X86_PUSH;
1685 ins->sreg1 = last_ins->sreg1;
1690 mono_peephole_ins (bb, ins);
1695 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1699 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1700 switch (ins->opcode) {
1702 /* reg = 0 -> XOR (reg, reg) */
1703 /* XOR sets cflags on x86, so we cant do it always */
1704 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1707 ins->opcode = OP_IXOR;
1708 ins->sreg1 = ins->dreg;
1709 ins->sreg2 = ins->dreg;
1712 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1713 * since it takes 3 bytes instead of 7.
1715 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
1716 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1717 ins2->opcode = OP_STORE_MEMBASE_REG;
1718 ins2->sreg1 = ins->dreg;
1720 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1721 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1722 ins2->sreg1 = ins->dreg;
1724 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1725 /* Continue iteration */
1734 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1735 ins->opcode = OP_X86_INC_REG;
1739 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1740 ins->opcode = OP_X86_DEC_REG;
1744 mono_peephole_ins (bb, ins);
1749 * mono_arch_lowering_pass:
1751 * Converts complex opcodes into simpler ones so that each IR instruction
1752 * corresponds to one machine instruction.
1755 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1757 MonoInst *ins, *next;
1760 * FIXME: Need to add more instructions, but the current machine
1761 * description can't model some parts of the composite instructions like
1764 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
1765 switch (ins->opcode) {
1768 case OP_IDIV_UN_IMM:
1769 case OP_IREM_UN_IMM:
1771 * Keep the cases where we could generated optimized code, otherwise convert
1772 * to the non-imm variant.
1774 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
1776 mono_decompose_op_imm (cfg, bb, ins);
1783 bb->max_vreg = cfg->next_vreg;
1787 branch_cc_table [] = {
1788 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1789 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1790 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1793 /* Maps CMP_... constants to X86_CC_... constants */
1796 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
1797 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
1801 cc_signed_table [] = {
1802 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
1803 FALSE, FALSE, FALSE, FALSE
1806 static unsigned char*
1807 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
1809 #define XMM_TEMP_REG 0
1810 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
1811 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
1812 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
1813 /* optimize by assigning a local var for this use so we avoid
1814 * the stack manipulations */
1815 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1816 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1817 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
1818 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
1819 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1821 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
1823 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
1826 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
1827 x86_fnstcw_membase(code, X86_ESP, 0);
1828 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
1829 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
1830 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
1831 x86_fldcw_membase (code, X86_ESP, 2);
1833 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1834 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
1835 x86_pop_reg (code, dreg);
1836 /* FIXME: need the high register
1837 * x86_pop_reg (code, dreg_high);
1840 x86_push_reg (code, X86_EAX); // SP = SP - 4
1841 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
1842 x86_pop_reg (code, dreg);
1844 x86_fldcw_membase (code, X86_ESP, 0);
1845 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
1848 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
1850 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
1854 static unsigned char*
1855 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
1857 int sreg = tree->sreg1;
1858 int need_touch = FALSE;
1860 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
1869 * If requested stack size is larger than one page,
1870 * perform stack-touch operation
1873 * Generate stack probe code.
1874 * Under Windows, it is necessary to allocate one page at a time,
1875 * "touching" stack after each successful sub-allocation. This is
1876 * because of the way stack growth is implemented - there is a
1877 * guard page before the lowest stack page that is currently commited.
1878 * Stack normally grows sequentially so OS traps access to the
1879 * guard page and commits more pages when needed.
1881 x86_test_reg_imm (code, sreg, ~0xFFF);
1882 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1884 br[2] = code; /* loop */
1885 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
1886 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
1889 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
1890 * that follows only initializes the last part of the area.
1892 /* Same as the init code below with size==0x1000 */
1893 if (tree->flags & MONO_INST_INIT) {
1894 x86_push_reg (code, X86_EAX);
1895 x86_push_reg (code, X86_ECX);
1896 x86_push_reg (code, X86_EDI);
1897 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
1898 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
1899 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
1901 x86_prefix (code, X86_REP_PREFIX);
1903 x86_pop_reg (code, X86_EDI);
1904 x86_pop_reg (code, X86_ECX);
1905 x86_pop_reg (code, X86_EAX);
1908 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
1909 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
1910 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
1911 x86_patch (br[3], br[2]);
1912 x86_test_reg_reg (code, sreg, sreg);
1913 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1914 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
1916 br[1] = code; x86_jump8 (code, 0);
1918 x86_patch (br[0], code);
1919 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
1920 x86_patch (br[1], code);
1921 x86_patch (br[4], code);
1924 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
1926 if (tree->flags & MONO_INST_INIT) {
1928 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
1929 x86_push_reg (code, X86_EAX);
1932 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
1933 x86_push_reg (code, X86_ECX);
1936 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
1937 x86_push_reg (code, X86_EDI);
1941 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
1942 if (sreg != X86_ECX)
1943 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
1944 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
1946 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
1948 x86_prefix (code, X86_REP_PREFIX);
1951 if (tree->dreg != X86_EDI && sreg != X86_EDI)
1952 x86_pop_reg (code, X86_EDI);
1953 if (tree->dreg != X86_ECX && sreg != X86_ECX)
1954 x86_pop_reg (code, X86_ECX);
1955 if (tree->dreg != X86_EAX && sreg != X86_EAX)
1956 x86_pop_reg (code, X86_EAX);
1963 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
1968 /* Move return value to the target register */
1969 switch (ins->opcode) {
1972 case OP_CALL_MEMBASE:
1973 if (ins->dreg != X86_EAX)
1974 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
1978 case OP_VCALL_MEMBASE:
1981 case OP_VCALL2_MEMBASE:
1982 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
1983 if (cinfo->ret.storage == ArgValuetypeInReg) {
1984 /* Pop the destination address from the stack */
1985 x86_pop_reg (code, X86_ECX);
1987 for (quad = 0; quad < 2; quad ++) {
1988 switch (cinfo->ret.pair_storage [quad]) {
1990 g_assert (cinfo->ret.pair_regs [quad] != X86_ECX);
1991 x86_mov_membase_reg (code, X86_ECX, (quad * sizeof (gpointer)), cinfo->ret.pair_regs [quad], sizeof (gpointer));
1996 g_assert_not_reached ();
2009 * mono_x86_emit_tls_get:
2010 * @code: buffer to store code to
2011 * @dreg: hard register where to place the result
2012 * @tls_offset: offset info
2014 * mono_x86_emit_tls_get emits in @code the native code that puts in
2015 * the dreg register the item in the thread local storage identified
2018 * Returns: a pointer to the end of the stored code
2021 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2023 #ifdef PLATFORM_WIN32
2025 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2026 * Journal and/or a disassembly of the TlsGet () function.
2028 g_assert (tls_offset < 64);
2029 x86_prefix (code, X86_FS_PREFIX);
2030 x86_mov_reg_mem (code, dreg, 0x18, 4);
2031 /* Dunno what this does but TlsGetValue () contains it */
2032 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2033 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2035 if (optimize_for_xen) {
2036 x86_prefix (code, X86_GS_PREFIX);
2037 x86_mov_reg_mem (code, dreg, 0, 4);
2038 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2040 x86_prefix (code, X86_GS_PREFIX);
2041 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2048 * emit_load_volatile_arguments:
2050 * Load volatile arguments from the stack to the original input registers.
2051 * Required before a tail call.
2054 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2056 MonoMethod *method = cfg->method;
2057 MonoMethodSignature *sig;
2062 /* FIXME: Generate intermediate code instead */
2064 sig = mono_method_signature (method);
2066 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
2068 /* This is the opposite of the code in emit_prolog */
2070 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2071 ArgInfo *ainfo = cinfo->args + i;
2073 inst = cfg->args [i];
2075 if (sig->hasthis && (i == 0))
2076 arg_type = &mono_defaults.object_class->byval_arg;
2078 arg_type = sig->params [i - sig->hasthis];
2081 * On x86, the arguments are either in their original stack locations, or in
2084 if (inst->opcode == OP_REGVAR) {
2085 g_assert (ainfo->storage == ArgOnStack);
2087 x86_mov_membase_reg (code, X86_EBP, inst->inst_offset, inst->dreg, 4);
2094 #define REAL_PRINT_REG(text,reg) \
2095 mono_assert (reg >= 0); \
2096 x86_push_reg (code, X86_EAX); \
2097 x86_push_reg (code, X86_EDX); \
2098 x86_push_reg (code, X86_ECX); \
2099 x86_push_reg (code, reg); \
2100 x86_push_imm (code, reg); \
2101 x86_push_imm (code, text " %d %p\n"); \
2102 x86_mov_reg_imm (code, X86_EAX, printf); \
2103 x86_call_reg (code, X86_EAX); \
2104 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2105 x86_pop_reg (code, X86_ECX); \
2106 x86_pop_reg (code, X86_EDX); \
2107 x86_pop_reg (code, X86_EAX);
2109 /* benchmark and set based on cpu */
2110 #define LOOP_ALIGNMENT 8
2111 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2116 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2121 guint8 *code = cfg->native_code + cfg->code_len;
2124 if (cfg->opt & MONO_OPT_LOOP) {
2125 int pad, align = LOOP_ALIGNMENT;
2126 /* set alignment depending on cpu */
2127 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2129 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2130 x86_padding (code, pad);
2131 cfg->code_len += pad;
2132 bb->native_offset = cfg->code_len;
2136 if (cfg->verbose_level > 2)
2137 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2139 cpos = bb->max_offset;
2141 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2142 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2143 g_assert (!cfg->compile_aot);
2146 cov->data [bb->dfn].cil_code = bb->cil_code;
2147 /* this is not thread save, but good enough */
2148 x86_inc_mem (code, &cov->data [bb->dfn].count);
2151 offset = code - cfg->native_code;
2153 mono_debug_open_block (cfg, bb, offset);
2155 MONO_BB_FOR_EACH_INS (bb, ins) {
2156 offset = code - cfg->native_code;
2158 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2160 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2161 cfg->code_size *= 2;
2162 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2163 code = cfg->native_code + offset;
2164 mono_jit_stats.code_reallocs++;
2167 if (cfg->debug_info)
2168 mono_debug_record_line_number (cfg, ins, offset);
2170 switch (ins->opcode) {
2172 x86_mul_reg (code, ins->sreg2, TRUE);
2175 x86_mul_reg (code, ins->sreg2, FALSE);
2177 case OP_X86_SETEQ_MEMBASE:
2178 case OP_X86_SETNE_MEMBASE:
2179 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2180 ins->inst_basereg, ins->inst_offset, TRUE);
2182 case OP_STOREI1_MEMBASE_IMM:
2183 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2185 case OP_STOREI2_MEMBASE_IMM:
2186 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2188 case OP_STORE_MEMBASE_IMM:
2189 case OP_STOREI4_MEMBASE_IMM:
2190 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2192 case OP_STOREI1_MEMBASE_REG:
2193 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2195 case OP_STOREI2_MEMBASE_REG:
2196 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2198 case OP_STORE_MEMBASE_REG:
2199 case OP_STOREI4_MEMBASE_REG:
2200 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2202 case OP_STORE_MEM_IMM:
2203 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2206 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2210 /* These are created by the cprop pass so they use inst_imm as the source */
2211 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2214 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2217 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2219 case OP_LOAD_MEMBASE:
2220 case OP_LOADI4_MEMBASE:
2221 case OP_LOADU4_MEMBASE:
2222 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2224 case OP_LOADU1_MEMBASE:
2225 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2227 case OP_LOADI1_MEMBASE:
2228 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2230 case OP_LOADU2_MEMBASE:
2231 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2233 case OP_LOADI2_MEMBASE:
2234 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2236 case OP_ICONV_TO_I1:
2238 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2240 case OP_ICONV_TO_I2:
2242 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2244 case OP_ICONV_TO_U1:
2245 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2247 case OP_ICONV_TO_U2:
2248 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2252 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2254 case OP_COMPARE_IMM:
2255 case OP_ICOMPARE_IMM:
2256 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2258 case OP_X86_COMPARE_MEMBASE_REG:
2259 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2261 case OP_X86_COMPARE_MEMBASE_IMM:
2262 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2264 case OP_X86_COMPARE_MEMBASE8_IMM:
2265 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2267 case OP_X86_COMPARE_REG_MEMBASE:
2268 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2270 case OP_X86_COMPARE_MEM_IMM:
2271 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2273 case OP_X86_TEST_NULL:
2274 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2276 case OP_X86_ADD_MEMBASE_IMM:
2277 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2279 case OP_X86_ADD_REG_MEMBASE:
2280 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2282 case OP_X86_SUB_MEMBASE_IMM:
2283 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2285 case OP_X86_SUB_REG_MEMBASE:
2286 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2288 case OP_X86_AND_MEMBASE_IMM:
2289 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2291 case OP_X86_OR_MEMBASE_IMM:
2292 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2294 case OP_X86_XOR_MEMBASE_IMM:
2295 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2297 case OP_X86_ADD_MEMBASE_REG:
2298 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2300 case OP_X86_SUB_MEMBASE_REG:
2301 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2303 case OP_X86_AND_MEMBASE_REG:
2304 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2306 case OP_X86_OR_MEMBASE_REG:
2307 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2309 case OP_X86_XOR_MEMBASE_REG:
2310 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2312 case OP_X86_INC_MEMBASE:
2313 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2315 case OP_X86_INC_REG:
2316 x86_inc_reg (code, ins->dreg);
2318 case OP_X86_DEC_MEMBASE:
2319 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2321 case OP_X86_DEC_REG:
2322 x86_dec_reg (code, ins->dreg);
2324 case OP_X86_MUL_REG_MEMBASE:
2325 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2327 case OP_X86_AND_REG_MEMBASE:
2328 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2330 case OP_X86_OR_REG_MEMBASE:
2331 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2333 case OP_X86_XOR_REG_MEMBASE:
2334 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2337 x86_breakpoint (code);
2339 case OP_RELAXED_NOP:
2340 x86_prefix (code, X86_REP_PREFIX);
2348 case OP_DUMMY_STORE:
2349 case OP_NOT_REACHED:
2355 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2359 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2364 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2368 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2373 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2377 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2382 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2386 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2389 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2393 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2398 * The code is the same for div/rem, the allocator will allocate dreg
2399 * to RAX/RDX as appropriate.
2401 if (ins->sreg2 == X86_EDX) {
2402 /* cdq clobbers this */
2403 x86_push_reg (code, ins->sreg2);
2405 x86_div_membase (code, X86_ESP, 0, TRUE);
2406 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2409 x86_div_reg (code, ins->sreg2, TRUE);
2414 if (ins->sreg2 == X86_EDX) {
2415 x86_push_reg (code, ins->sreg2);
2416 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2417 x86_div_membase (code, X86_ESP, 0, FALSE);
2418 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2420 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2421 x86_div_reg (code, ins->sreg2, FALSE);
2425 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2427 x86_div_reg (code, ins->sreg2, TRUE);
2430 int power = mono_is_power_of_two (ins->inst_imm);
2432 g_assert (ins->sreg1 == X86_EAX);
2433 g_assert (ins->dreg == X86_EAX);
2434 g_assert (power >= 0);
2437 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2439 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2441 * If the divident is >= 0, this does not nothing. If it is positive, it
2442 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2444 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2445 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2447 /* Based on gcc code */
2449 /* Add compensation for negative dividents */
2451 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2452 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2453 /* Compute remainder */
2454 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2455 /* Remove compensation */
2456 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2461 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2465 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2468 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2472 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2475 g_assert (ins->sreg2 == X86_ECX);
2476 x86_shift_reg (code, X86_SHL, ins->dreg);
2479 g_assert (ins->sreg2 == X86_ECX);
2480 x86_shift_reg (code, X86_SAR, ins->dreg);
2484 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2487 case OP_ISHR_UN_IMM:
2488 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2491 g_assert (ins->sreg2 == X86_ECX);
2492 x86_shift_reg (code, X86_SHR, ins->dreg);
2496 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2499 guint8 *jump_to_end;
2501 /* handle shifts below 32 bits */
2502 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2503 x86_shift_reg (code, X86_SHL, ins->sreg1);
2505 x86_test_reg_imm (code, X86_ECX, 32);
2506 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2508 /* handle shift over 32 bit */
2509 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2510 x86_clear_reg (code, ins->sreg1);
2512 x86_patch (jump_to_end, code);
2516 guint8 *jump_to_end;
2518 /* handle shifts below 32 bits */
2519 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2520 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2522 x86_test_reg_imm (code, X86_ECX, 32);
2523 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2525 /* handle shifts over 31 bits */
2526 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2527 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2529 x86_patch (jump_to_end, code);
2533 guint8 *jump_to_end;
2535 /* handle shifts below 32 bits */
2536 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2537 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2539 x86_test_reg_imm (code, X86_ECX, 32);
2540 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2542 /* handle shifts over 31 bits */
2543 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2544 x86_clear_reg (code, ins->backend.reg3);
2546 x86_patch (jump_to_end, code);
2550 if (ins->inst_imm >= 32) {
2551 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2552 x86_clear_reg (code, ins->sreg1);
2553 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2555 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2556 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2560 if (ins->inst_imm >= 32) {
2561 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2562 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2563 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2565 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2566 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2569 case OP_LSHR_UN_IMM:
2570 if (ins->inst_imm >= 32) {
2571 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2572 x86_clear_reg (code, ins->backend.reg3);
2573 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2575 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2576 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2580 x86_not_reg (code, ins->sreg1);
2583 x86_neg_reg (code, ins->sreg1);
2587 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2591 switch (ins->inst_imm) {
2595 if (ins->dreg != ins->sreg1)
2596 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2597 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2600 /* LEA r1, [r2 + r2*2] */
2601 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2604 /* LEA r1, [r2 + r2*4] */
2605 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2608 /* LEA r1, [r2 + r2*2] */
2610 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2611 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2614 /* LEA r1, [r2 + r2*8] */
2615 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2618 /* LEA r1, [r2 + r2*4] */
2620 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2621 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2624 /* LEA r1, [r2 + r2*2] */
2626 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2627 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2630 /* LEA r1, [r2 + r2*4] */
2631 /* LEA r1, [r1 + r1*4] */
2632 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2633 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2636 /* LEA r1, [r2 + r2*4] */
2638 /* LEA r1, [r1 + r1*4] */
2639 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2640 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2641 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2644 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2649 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2650 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2652 case OP_IMUL_OVF_UN: {
2653 /* the mul operation and the exception check should most likely be split */
2654 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2655 /*g_assert (ins->sreg2 == X86_EAX);
2656 g_assert (ins->dreg == X86_EAX);*/
2657 if (ins->sreg2 == X86_EAX) {
2658 non_eax_reg = ins->sreg1;
2659 } else if (ins->sreg1 == X86_EAX) {
2660 non_eax_reg = ins->sreg2;
2662 /* no need to save since we're going to store to it anyway */
2663 if (ins->dreg != X86_EAX) {
2665 x86_push_reg (code, X86_EAX);
2667 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
2668 non_eax_reg = ins->sreg2;
2670 if (ins->dreg == X86_EDX) {
2673 x86_push_reg (code, X86_EAX);
2675 } else if (ins->dreg != X86_EAX) {
2677 x86_push_reg (code, X86_EDX);
2679 x86_mul_reg (code, non_eax_reg, FALSE);
2680 /* save before the check since pop and mov don't change the flags */
2681 if (ins->dreg != X86_EAX)
2682 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2684 x86_pop_reg (code, X86_EDX);
2686 x86_pop_reg (code, X86_EAX);
2687 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2691 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
2694 g_assert_not_reached ();
2695 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2696 x86_mov_reg_imm (code, ins->dreg, 0);
2699 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2700 x86_mov_reg_imm (code, ins->dreg, 0);
2702 case OP_LOAD_GOTADDR:
2703 x86_call_imm (code, 0);
2705 * The patch needs to point to the pop, since the GOT offset needs
2706 * to be added to that address.
2708 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
2709 x86_pop_reg (code, ins->dreg);
2710 x86_alu_reg_imm (code, X86_ADD, ins->dreg, 0xf0f0f0f0);
2713 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2714 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
2716 case OP_X86_PUSH_GOT_ENTRY:
2717 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2718 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
2721 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2725 * Note: this 'frame destruction' logic is useful for tail calls, too.
2726 * Keep in sync with the code in emit_epilog.
2730 /* FIXME: no tracing support... */
2731 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2732 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2733 /* reset offset to make max_len work */
2734 offset = code - cfg->native_code;
2736 g_assert (!cfg->method->save_lmf);
2738 code = emit_load_volatile_arguments (cfg, code);
2740 if (cfg->used_int_regs & (1 << X86_EBX))
2742 if (cfg->used_int_regs & (1 << X86_EDI))
2744 if (cfg->used_int_regs & (1 << X86_ESI))
2747 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
2749 if (cfg->used_int_regs & (1 << X86_ESI))
2750 x86_pop_reg (code, X86_ESI);
2751 if (cfg->used_int_regs & (1 << X86_EDI))
2752 x86_pop_reg (code, X86_EDI);
2753 if (cfg->used_int_regs & (1 << X86_EBX))
2754 x86_pop_reg (code, X86_EBX);
2756 /* restore ESP/EBP */
2758 offset = code - cfg->native_code;
2759 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2760 x86_jump32 (code, 0);
2762 cfg->disable_aot = TRUE;
2766 /* ensure ins->sreg1 is not NULL
2767 * note that cmp DWORD PTR [eax], eax is one byte shorter than
2768 * cmp DWORD PTR [eax], 0
2770 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
2773 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
2774 x86_push_reg (code, hreg);
2775 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
2776 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
2777 x86_pop_reg (code, hreg);
2786 call = (MonoCallInst*)ins;
2787 if (ins->flags & MONO_INST_HAS_METHOD)
2788 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2790 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2791 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
2792 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
2793 * bytes to pop, we want to use pops. GCC does this (note it won't happen
2794 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
2795 * smart enough to do that optimization yet
2797 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
2798 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
2799 * (most likely from locality benefits). People with other processors should
2800 * check on theirs to see what happens.
2802 if (call->stack_usage == 4) {
2803 /* we want to use registers that won't get used soon, so use
2804 * ecx, as eax will get allocated first. edx is used by long calls,
2805 * so we can't use that.
2808 x86_pop_reg (code, X86_ECX);
2810 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2813 code = emit_move_return_value (cfg, ins, code);
2819 case OP_VOIDCALL_REG:
2821 call = (MonoCallInst*)ins;
2822 x86_call_reg (code, ins->sreg1);
2823 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
2824 if (call->stack_usage == 4)
2825 x86_pop_reg (code, X86_ECX);
2827 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2829 code = emit_move_return_value (cfg, ins, code);
2831 case OP_FCALL_MEMBASE:
2832 case OP_LCALL_MEMBASE:
2833 case OP_VCALL_MEMBASE:
2834 case OP_VCALL2_MEMBASE:
2835 case OP_VOIDCALL_MEMBASE:
2836 case OP_CALL_MEMBASE:
2837 call = (MonoCallInst*)ins;
2840 * Emit a few nops to simplify get_vcall_slot ().
2846 x86_call_membase (code, ins->sreg1, ins->inst_offset);
2847 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
2848 if (call->stack_usage == 4)
2849 x86_pop_reg (code, X86_ECX);
2851 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2853 code = emit_move_return_value (cfg, ins, code);
2856 x86_push_reg (code, ins->sreg1);
2858 case OP_X86_PUSH_IMM:
2859 x86_push_imm (code, ins->inst_imm);
2861 case OP_X86_PUSH_MEMBASE:
2862 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
2864 case OP_X86_PUSH_OBJ:
2865 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
2866 x86_push_reg (code, X86_EDI);
2867 x86_push_reg (code, X86_ESI);
2868 x86_push_reg (code, X86_ECX);
2869 if (ins->inst_offset)
2870 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
2872 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
2873 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2874 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
2876 x86_prefix (code, X86_REP_PREFIX);
2878 x86_pop_reg (code, X86_ECX);
2879 x86_pop_reg (code, X86_ESI);
2880 x86_pop_reg (code, X86_EDI);
2883 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
2885 case OP_X86_LEA_MEMBASE:
2886 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
2889 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
2892 /* keep alignment */
2893 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
2894 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
2895 code = mono_emit_stack_alloc (code, ins);
2896 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2898 case OP_LOCALLOC_IMM: {
2899 guint32 size = ins->inst_imm;
2900 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
2902 if (ins->flags & MONO_INST_INIT) {
2903 /* FIXME: Optimize this */
2904 x86_mov_reg_imm (code, ins->dreg, size);
2905 ins->sreg1 = ins->dreg;
2907 code = mono_emit_stack_alloc (code, ins);
2908 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2910 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
2911 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2916 x86_push_reg (code, ins->sreg1);
2917 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
2918 (gpointer)"mono_arch_throw_exception");
2922 x86_push_reg (code, ins->sreg1);
2923 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
2924 (gpointer)"mono_arch_rethrow_exception");
2927 case OP_CALL_HANDLER:
2928 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
2929 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2930 x86_call_imm (code, 0);
2931 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
2933 case OP_START_HANDLER: {
2934 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
2935 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
2938 case OP_ENDFINALLY: {
2939 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
2940 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
2944 case OP_ENDFILTER: {
2945 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
2946 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
2947 /* The local allocator will put the result into EAX */
2953 ins->inst_c0 = code - cfg->native_code;
2956 if (ins->inst_target_bb->native_offset) {
2957 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
2959 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2960 if ((cfg->opt & MONO_OPT_BRANCH) &&
2961 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
2962 x86_jump8 (code, 0);
2964 x86_jump32 (code, 0);
2968 x86_jump_reg (code, ins->sreg1);
2981 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
2982 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2984 case OP_COND_EXC_EQ:
2985 case OP_COND_EXC_NE_UN:
2986 case OP_COND_EXC_LT:
2987 case OP_COND_EXC_LT_UN:
2988 case OP_COND_EXC_GT:
2989 case OP_COND_EXC_GT_UN:
2990 case OP_COND_EXC_GE:
2991 case OP_COND_EXC_GE_UN:
2992 case OP_COND_EXC_LE:
2993 case OP_COND_EXC_LE_UN:
2994 case OP_COND_EXC_IEQ:
2995 case OP_COND_EXC_INE_UN:
2996 case OP_COND_EXC_ILT:
2997 case OP_COND_EXC_ILT_UN:
2998 case OP_COND_EXC_IGT:
2999 case OP_COND_EXC_IGT_UN:
3000 case OP_COND_EXC_IGE:
3001 case OP_COND_EXC_IGE_UN:
3002 case OP_COND_EXC_ILE:
3003 case OP_COND_EXC_ILE_UN:
3004 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3006 case OP_COND_EXC_OV:
3007 case OP_COND_EXC_NO:
3009 case OP_COND_EXC_NC:
3010 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3012 case OP_COND_EXC_IOV:
3013 case OP_COND_EXC_INO:
3014 case OP_COND_EXC_IC:
3015 case OP_COND_EXC_INC:
3016 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3028 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3036 case OP_CMOV_INE_UN:
3037 case OP_CMOV_IGE_UN:
3038 case OP_CMOV_IGT_UN:
3039 case OP_CMOV_ILE_UN:
3040 case OP_CMOV_ILT_UN:
3041 g_assert (ins->dreg == ins->sreg1);
3042 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3045 /* floating point opcodes */
3047 double d = *(double *)ins->inst_p0;
3049 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3051 } else if (d == 1.0) {
3054 if (cfg->compile_aot) {
3055 guint32 *val = (guint32*)&d;
3056 x86_push_imm (code, val [1]);
3057 x86_push_imm (code, val [0]);
3058 x86_fld_membase (code, X86_ESP, 0, TRUE);
3059 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3062 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3063 x86_fld (code, NULL, TRUE);
3069 float f = *(float *)ins->inst_p0;
3071 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3073 } else if (f == 1.0) {
3076 if (cfg->compile_aot) {
3077 guint32 val = *(guint32*)&f;
3078 x86_push_imm (code, val);
3079 x86_fld_membase (code, X86_ESP, 0, FALSE);
3080 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3083 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3084 x86_fld (code, NULL, FALSE);
3089 case OP_STORER8_MEMBASE_REG:
3090 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3092 case OP_LOADR8_SPILL_MEMBASE:
3093 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3096 case OP_LOADR8_MEMBASE:
3097 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3099 case OP_STORER4_MEMBASE_REG:
3100 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3102 case OP_LOADR4_MEMBASE:
3103 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3105 case OP_ICONV_TO_R4:
3106 x86_push_reg (code, ins->sreg1);
3107 x86_fild_membase (code, X86_ESP, 0, FALSE);
3108 /* Change precision */
3109 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3110 x86_fld_membase (code, X86_ESP, 0, FALSE);
3111 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3113 case OP_ICONV_TO_R8:
3114 x86_push_reg (code, ins->sreg1);
3115 x86_fild_membase (code, X86_ESP, 0, FALSE);
3116 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3118 case OP_ICONV_TO_R_UN:
3119 x86_push_imm (code, 0);
3120 x86_push_reg (code, ins->sreg1);
3121 x86_fild_membase (code, X86_ESP, 0, TRUE);
3122 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3124 case OP_X86_FP_LOAD_I8:
3125 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3127 case OP_X86_FP_LOAD_I4:
3128 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3130 case OP_FCONV_TO_R4:
3131 /* Change precision */
3132 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3133 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3134 x86_fld_membase (code, X86_ESP, 0, FALSE);
3135 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3137 case OP_FCONV_TO_I1:
3138 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3140 case OP_FCONV_TO_U1:
3141 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3143 case OP_FCONV_TO_I2:
3144 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3146 case OP_FCONV_TO_U2:
3147 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3149 case OP_FCONV_TO_I4:
3151 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3153 case OP_FCONV_TO_I8:
3154 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3155 x86_fnstcw_membase(code, X86_ESP, 0);
3156 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3157 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3158 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3159 x86_fldcw_membase (code, X86_ESP, 2);
3160 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3161 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3162 x86_pop_reg (code, ins->dreg);
3163 x86_pop_reg (code, ins->backend.reg3);
3164 x86_fldcw_membase (code, X86_ESP, 0);
3165 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3167 case OP_LCONV_TO_R8_2:
3168 x86_push_reg (code, ins->sreg2);
3169 x86_push_reg (code, ins->sreg1);
3170 x86_fild_membase (code, X86_ESP, 0, TRUE);
3171 /* Change precision */
3172 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3173 x86_fld_membase (code, X86_ESP, 0, TRUE);
3174 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3176 case OP_LCONV_TO_R4_2:
3177 x86_push_reg (code, ins->sreg2);
3178 x86_push_reg (code, ins->sreg1);
3179 x86_fild_membase (code, X86_ESP, 0, TRUE);
3180 /* Change precision */
3181 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3182 x86_fld_membase (code, X86_ESP, 0, FALSE);
3183 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3185 case OP_LCONV_TO_R_UN:
3186 case OP_LCONV_TO_R_UN_2: {
3187 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3190 /* load 64bit integer to FP stack */
3191 x86_push_reg (code, ins->sreg2);
3192 x86_push_reg (code, ins->sreg1);
3193 x86_fild_membase (code, X86_ESP, 0, TRUE);
3195 /* test if lreg is negative */
3196 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3197 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3199 /* add correction constant mn */
3200 x86_fld80_mem (code, mn);
3201 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3203 x86_patch (br, code);
3205 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3209 case OP_LCONV_TO_OVF_I:
3210 case OP_LCONV_TO_OVF_I4_2: {
3211 guint8 *br [3], *label [1];
3215 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3217 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3219 /* If the low word top bit is set, see if we are negative */
3220 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3221 /* We are not negative (no top bit set, check for our top word to be zero */
3222 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3223 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3226 /* throw exception */
3227 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3229 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3230 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3231 x86_jump8 (code, 0);
3233 x86_jump32 (code, 0);
3235 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3236 x86_jump32 (code, 0);
3240 x86_patch (br [0], code);
3241 /* our top bit is set, check that top word is 0xfffffff */
3242 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3244 x86_patch (br [1], code);
3245 /* nope, emit exception */
3246 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3247 x86_patch (br [2], label [0]);
3249 if (ins->dreg != ins->sreg1)
3250 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3254 /* Not needed on the fp stack */
3257 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3260 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3263 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3266 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3274 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3279 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3286 * it really doesn't make sense to inline all this code,
3287 * it's here just to show that things may not be as simple
3290 guchar *check_pos, *end_tan, *pop_jump;
3291 x86_push_reg (code, X86_EAX);
3294 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3296 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3297 x86_fstp (code, 0); /* pop the 1.0 */
3299 x86_jump8 (code, 0);
3301 x86_fp_op (code, X86_FADD, 0);
3305 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3307 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3310 x86_patch (pop_jump, code);
3311 x86_fstp (code, 0); /* pop the 1.0 */
3312 x86_patch (check_pos, code);
3313 x86_patch (end_tan, code);
3315 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3316 x86_pop_reg (code, X86_EAX);
3323 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3332 g_assert (cfg->opt & MONO_OPT_CMOV);
3333 g_assert (ins->dreg == ins->sreg1);
3334 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3335 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3338 g_assert (cfg->opt & MONO_OPT_CMOV);
3339 g_assert (ins->dreg == ins->sreg1);
3340 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3341 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3344 g_assert (cfg->opt & MONO_OPT_CMOV);
3345 g_assert (ins->dreg == ins->sreg1);
3346 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3347 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3350 g_assert (cfg->opt & MONO_OPT_CMOV);
3351 g_assert (ins->dreg == ins->sreg1);
3352 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3353 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3359 x86_fxch (code, ins->inst_imm);
3364 x86_push_reg (code, X86_EAX);
3365 /* we need to exchange ST(0) with ST(1) */
3368 /* this requires a loop, because fprem somtimes
3369 * returns a partial remainder */
3371 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3372 /* x86_fprem1 (code); */
3375 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3377 x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3382 x86_pop_reg (code, X86_EAX);
3386 if (cfg->opt & MONO_OPT_FCMOV) {
3387 x86_fcomip (code, 1);
3391 /* this overwrites EAX */
3392 EMIT_FPCOMPARE(code);
3393 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3396 if (cfg->opt & MONO_OPT_FCMOV) {
3397 /* zeroing the register at the start results in
3398 * shorter and faster code (we can also remove the widening op)
3400 guchar *unordered_check;
3401 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3402 x86_fcomip (code, 1);
3404 unordered_check = code;
3405 x86_branch8 (code, X86_CC_P, 0, FALSE);
3406 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3407 x86_patch (unordered_check, code);
3410 if (ins->dreg != X86_EAX)
3411 x86_push_reg (code, X86_EAX);
3413 EMIT_FPCOMPARE(code);
3414 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3415 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3416 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3417 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3419 if (ins->dreg != X86_EAX)
3420 x86_pop_reg (code, X86_EAX);
3424 if (cfg->opt & MONO_OPT_FCMOV) {
3425 /* zeroing the register at the start results in
3426 * shorter and faster code (we can also remove the widening op)
3428 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3429 x86_fcomip (code, 1);
3431 if (ins->opcode == OP_FCLT_UN) {
3432 guchar *unordered_check = code;
3433 guchar *jump_to_end;
3434 x86_branch8 (code, X86_CC_P, 0, FALSE);
3435 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3437 x86_jump8 (code, 0);
3438 x86_patch (unordered_check, code);
3439 x86_inc_reg (code, ins->dreg);
3440 x86_patch (jump_to_end, code);
3442 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3446 if (ins->dreg != X86_EAX)
3447 x86_push_reg (code, X86_EAX);
3449 EMIT_FPCOMPARE(code);
3450 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3451 if (ins->opcode == OP_FCLT_UN) {
3452 guchar *is_not_zero_check, *end_jump;
3453 is_not_zero_check = code;
3454 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3456 x86_jump8 (code, 0);
3457 x86_patch (is_not_zero_check, code);
3458 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3460 x86_patch (end_jump, code);
3462 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3463 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3465 if (ins->dreg != X86_EAX)
3466 x86_pop_reg (code, X86_EAX);
3470 if (cfg->opt & MONO_OPT_FCMOV) {
3471 /* zeroing the register at the start results in
3472 * shorter and faster code (we can also remove the widening op)
3474 guchar *unordered_check;
3475 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3476 x86_fcomip (code, 1);
3478 if (ins->opcode == OP_FCGT) {
3479 unordered_check = code;
3480 x86_branch8 (code, X86_CC_P, 0, FALSE);
3481 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3482 x86_patch (unordered_check, code);
3484 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3488 if (ins->dreg != X86_EAX)
3489 x86_push_reg (code, X86_EAX);
3491 EMIT_FPCOMPARE(code);
3492 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3493 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3494 if (ins->opcode == OP_FCGT_UN) {
3495 guchar *is_not_zero_check, *end_jump;
3496 is_not_zero_check = code;
3497 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3499 x86_jump8 (code, 0);
3500 x86_patch (is_not_zero_check, code);
3501 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3503 x86_patch (end_jump, code);
3505 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3506 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3508 if (ins->dreg != X86_EAX)
3509 x86_pop_reg (code, X86_EAX);
3512 if (cfg->opt & MONO_OPT_FCMOV) {
3513 guchar *jump = code;
3514 x86_branch8 (code, X86_CC_P, 0, TRUE);
3515 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3516 x86_patch (jump, code);
3519 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3520 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3523 /* Branch if C013 != 100 */
3524 if (cfg->opt & MONO_OPT_FCMOV) {
3525 /* branch if !ZF or (PF|CF) */
3526 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3527 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3528 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3531 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3532 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3535 if (cfg->opt & MONO_OPT_FCMOV) {
3536 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3539 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3542 if (cfg->opt & MONO_OPT_FCMOV) {
3543 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3544 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3547 if (ins->opcode == OP_FBLT_UN) {
3548 guchar *is_not_zero_check, *end_jump;
3549 is_not_zero_check = code;
3550 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3552 x86_jump8 (code, 0);
3553 x86_patch (is_not_zero_check, code);
3554 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3556 x86_patch (end_jump, code);
3558 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3562 if (cfg->opt & MONO_OPT_FCMOV) {
3563 if (ins->opcode == OP_FBGT) {
3566 /* skip branch if C1=1 */
3568 x86_branch8 (code, X86_CC_P, 0, FALSE);
3569 /* branch if (C0 | C3) = 1 */
3570 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3571 x86_patch (br1, code);
3573 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3577 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3578 if (ins->opcode == OP_FBGT_UN) {
3579 guchar *is_not_zero_check, *end_jump;
3580 is_not_zero_check = code;
3581 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3583 x86_jump8 (code, 0);
3584 x86_patch (is_not_zero_check, code);
3585 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3587 x86_patch (end_jump, code);
3589 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3592 /* Branch if C013 == 100 or 001 */
3593 if (cfg->opt & MONO_OPT_FCMOV) {
3596 /* skip branch if C1=1 */
3598 x86_branch8 (code, X86_CC_P, 0, FALSE);
3599 /* branch if (C0 | C3) = 1 */
3600 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3601 x86_patch (br1, code);
3604 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3605 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3606 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3607 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3610 /* Branch if C013 == 000 */
3611 if (cfg->opt & MONO_OPT_FCMOV) {
3612 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3615 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3618 /* Branch if C013=000 or 100 */
3619 if (cfg->opt & MONO_OPT_FCMOV) {
3622 /* skip branch if C1=1 */
3624 x86_branch8 (code, X86_CC_P, 0, FALSE);
3625 /* branch if C0=0 */
3626 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3627 x86_patch (br1, code);
3630 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
3631 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
3632 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3635 /* Branch if C013 != 001 */
3636 if (cfg->opt & MONO_OPT_FCMOV) {
3637 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3638 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3641 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3642 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3646 x86_push_reg (code, X86_EAX);
3649 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
3650 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3651 x86_pop_reg (code, X86_EAX);
3653 /* Have to clean up the fp stack before throwing the exception */
3655 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3658 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3660 x86_patch (br1, code);
3664 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
3667 case OP_MEMORY_BARRIER: {
3668 /* Not needed on x86 */
3671 case OP_ATOMIC_ADD_I4: {
3672 int dreg = ins->dreg;
3674 if (dreg == ins->inst_basereg) {
3675 x86_push_reg (code, ins->sreg2);
3679 if (dreg != ins->sreg2)
3680 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
3682 x86_prefix (code, X86_LOCK_PREFIX);
3683 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
3685 if (dreg != ins->dreg) {
3686 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
3687 x86_pop_reg (code, dreg);
3692 case OP_ATOMIC_ADD_NEW_I4: {
3693 int dreg = ins->dreg;
3695 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
3696 if (ins->sreg2 == dreg) {
3697 if (dreg == X86_EBX) {
3699 if (ins->inst_basereg == X86_EDI)
3703 if (ins->inst_basereg == X86_EBX)
3706 } else if (ins->inst_basereg == dreg) {
3707 if (dreg == X86_EBX) {
3709 if (ins->sreg2 == X86_EDI)
3713 if (ins->sreg2 == X86_EBX)
3718 if (dreg != ins->dreg) {
3719 x86_push_reg (code, dreg);
3722 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
3723 x86_prefix (code, X86_LOCK_PREFIX);
3724 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
3725 /* dreg contains the old value, add with sreg2 value */
3726 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
3728 if (ins->dreg != dreg) {
3729 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
3730 x86_pop_reg (code, dreg);
3735 case OP_ATOMIC_EXCHANGE_I4: {
3737 int sreg2 = ins->sreg2;
3738 int breg = ins->inst_basereg;
3740 /* cmpxchg uses eax as comperand, need to make sure we can use it
3741 * hack to overcome limits in x86 reg allocator
3742 * (req: dreg == eax and sreg2 != eax and breg != eax)
3744 g_assert (ins->dreg == X86_EAX);
3746 /* We need the EAX reg for the cmpxchg */
3747 if (ins->sreg2 == X86_EAX) {
3748 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
3749 x86_push_reg (code, sreg2);
3750 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
3753 if (breg == X86_EAX) {
3754 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
3755 x86_push_reg (code, breg);
3756 x86_mov_reg_reg (code, breg, X86_EAX, 4);
3759 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
3761 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
3762 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
3763 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
3764 x86_patch (br [1], br [0]);
3766 if (breg != ins->inst_basereg)
3767 x86_pop_reg (code, breg);
3769 if (ins->sreg2 != sreg2)
3770 x86_pop_reg (code, sreg2);
3774 case OP_ATOMIC_CAS_I4: {
3775 g_assert (ins->sreg3 == X86_EAX);
3776 g_assert (ins->sreg1 != X86_EAX);
3777 g_assert (ins->sreg1 != ins->sreg2);
3779 x86_prefix (code, X86_LOCK_PREFIX);
3780 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
3782 if (ins->dreg != X86_EAX)
3783 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3786 #ifdef MONO_ARCH_SIMD_INTRINSICS
3788 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
3791 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
3794 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
3797 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
3800 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
3803 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
3806 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
3807 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
3810 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
3813 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
3816 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
3819 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
3822 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
3825 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
3828 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
3831 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
3834 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
3837 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
3840 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
3843 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
3846 case OP_PSHUFLEW_HIGH:
3847 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
3848 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
3850 case OP_PSHUFLEW_LOW:
3851 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
3852 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
3855 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
3856 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
3860 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
3863 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
3866 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
3869 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
3872 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
3875 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
3878 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
3879 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
3882 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
3885 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
3888 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
3891 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
3894 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
3897 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
3900 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
3903 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
3906 case OP_EXTRACT_MASK:
3907 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
3911 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
3914 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
3917 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
3921 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
3924 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
3927 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
3930 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
3934 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
3937 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
3940 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
3943 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
3947 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
3950 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
3953 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
3957 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
3960 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
3963 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
3967 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
3970 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
3974 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
3977 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
3980 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
3984 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
3987 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
3990 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
3994 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
3997 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4000 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4003 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4007 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4010 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4013 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4016 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4019 case OP_PSUM_ABS_DIFF:
4020 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4023 case OP_UNPACK_LOWB:
4024 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4026 case OP_UNPACK_LOWW:
4027 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4029 case OP_UNPACK_LOWD:
4030 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4032 case OP_UNPACK_LOWQ:
4033 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4035 case OP_UNPACK_LOWPS:
4036 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4038 case OP_UNPACK_LOWPD:
4039 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4042 case OP_UNPACK_HIGHB:
4043 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4045 case OP_UNPACK_HIGHW:
4046 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4048 case OP_UNPACK_HIGHD:
4049 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4051 case OP_UNPACK_HIGHQ:
4052 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4054 case OP_UNPACK_HIGHPS:
4055 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4057 case OP_UNPACK_HIGHPD:
4058 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4062 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4065 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4068 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4071 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4074 case OP_PADDB_SAT_UN:
4075 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4077 case OP_PSUBB_SAT_UN:
4078 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4080 case OP_PADDW_SAT_UN:
4081 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4083 case OP_PSUBW_SAT_UN:
4084 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4088 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4091 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4094 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4097 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4101 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4104 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4107 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4109 case OP_PMULW_HIGH_UN:
4110 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4113 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4117 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4120 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4124 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4127 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4131 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4134 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4138 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4141 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4145 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4148 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4152 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4155 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4159 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4162 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4166 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4169 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4173 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4176 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4180 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4182 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4183 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4187 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4189 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4190 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4194 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4196 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4197 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4201 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4203 case OP_EXTRACTX_U2:
4204 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4206 case OP_INSERTX_U1_SLOW:
4207 /*sreg1 is the extracted ireg (scratch)
4208 /sreg2 is the to be inserted ireg (scratch)
4209 /dreg is the xreg to receive the value*/
4211 /*clear the bits from the extracted word*/
4212 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4213 /*shift the value to insert if needed*/
4214 if (ins->inst_c0 & 1)
4215 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4216 /*join them together*/
4217 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4218 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4220 case OP_INSERTX_I4_SLOW:
4221 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4222 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4223 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4226 case OP_INSERTX_R4_SLOW:
4227 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4228 /*TODO if inst_c0 == 0 use movss*/
4229 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4230 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4232 case OP_INSERTX_R8_SLOW:
4233 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4235 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4237 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVSD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4240 case OP_STOREX_MEMBASE_REG:
4241 case OP_STOREX_MEMBASE:
4242 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4244 case OP_LOADX_MEMBASE:
4245 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4247 case OP_LOADX_ALIGNED_MEMBASE:
4248 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4250 case OP_STOREX_ALIGNED_MEMBASE_REG:
4251 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4253 case OP_STOREX_NTA_MEMBASE_REG:
4254 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4256 case OP_PREFETCH_MEMBASE:
4257 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4261 /*FIXME the peephole pass should have killed this*/
4262 if (ins->dreg != ins->sreg1)
4263 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4266 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4268 case OP_ICONV_TO_R8_RAW:
4269 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4270 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4273 case OP_FCONV_TO_R8_X:
4274 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4275 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4278 case OP_XCONV_R8_TO_I4:
4279 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4280 switch (ins->backend.source_opcode) {
4281 case OP_FCONV_TO_I1:
4282 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4284 case OP_FCONV_TO_U1:
4285 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4287 case OP_FCONV_TO_I2:
4288 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4290 case OP_FCONV_TO_U2:
4291 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4297 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4298 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4299 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4300 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4301 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4302 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4305 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4306 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4307 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4310 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4311 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4314 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4315 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4316 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4319 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4320 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4321 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4324 case OP_LIVERANGE_START: {
4325 if (cfg->verbose_level > 1)
4326 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4327 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4330 case OP_LIVERANGE_END: {
4331 if (cfg->verbose_level > 1)
4332 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4333 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4337 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4338 g_assert_not_reached ();
4341 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4342 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4343 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4344 g_assert_not_reached ();
4350 cfg->code_len = code - cfg->native_code;
4353 #endif /* DISABLE_JIT */
4356 mono_arch_register_lowlevel_calls (void)
4361 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4363 MonoJumpInfo *patch_info;
4364 gboolean compile_aot = !run_cctors;
4366 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4367 unsigned char *ip = patch_info->ip.i + code;
4368 const unsigned char *target;
4370 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4373 switch (patch_info->type) {
4374 case MONO_PATCH_INFO_BB:
4375 case MONO_PATCH_INFO_LABEL:
4378 /* No need to patch these */
4383 switch (patch_info->type) {
4384 case MONO_PATCH_INFO_IP:
4385 *((gconstpointer *)(ip)) = target;
4387 case MONO_PATCH_INFO_CLASS_INIT: {
4389 /* Might already been changed to a nop */
4390 x86_call_code (code, 0);
4391 x86_patch (ip, target);
4394 case MONO_PATCH_INFO_ABS:
4395 case MONO_PATCH_INFO_METHOD:
4396 case MONO_PATCH_INFO_METHOD_JUMP:
4397 case MONO_PATCH_INFO_INTERNAL_METHOD:
4398 case MONO_PATCH_INFO_BB:
4399 case MONO_PATCH_INFO_LABEL:
4400 case MONO_PATCH_INFO_RGCTX_FETCH:
4401 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
4402 case MONO_PATCH_INFO_MONITOR_ENTER:
4403 case MONO_PATCH_INFO_MONITOR_EXIT:
4404 x86_patch (ip, target);
4406 case MONO_PATCH_INFO_NONE:
4409 guint32 offset = mono_arch_get_patch_offset (ip);
4410 *((gconstpointer *)(ip + offset)) = target;
4418 mono_arch_emit_prolog (MonoCompile *cfg)
4420 MonoMethod *method = cfg->method;
4422 MonoMethodSignature *sig;
4424 int alloc_size, pos, max_offset, i, cfa_offset;
4426 gboolean need_stack_frame;
4428 cfg->code_size = MAX (mono_method_get_header (method)->code_size * 4, 10240);
4430 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4431 cfg->code_size += 512;
4433 code = cfg->native_code = g_malloc (cfg->code_size);
4435 /* Offset between RSP and the CFA */
4439 cfa_offset = sizeof (gpointer);
4440 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
4441 // IP saved at CFA - 4
4442 /* There is no IP reg on x86 */
4443 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
4445 need_stack_frame = needs_stack_frame (cfg);
4447 if (need_stack_frame) {
4448 x86_push_reg (code, X86_EBP);
4449 cfa_offset += sizeof (gpointer);
4450 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4451 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
4452 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
4453 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
4456 alloc_size = cfg->stack_offset;
4459 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4460 /* Might need to attach the thread to the JIT or change the domain for the callback */
4461 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4462 guint8 *buf, *no_domain_branch;
4464 code = mono_x86_emit_tls_get (code, X86_EAX, appdomain_tls_offset);
4465 x86_alu_reg_imm (code, X86_CMP, X86_EAX, GPOINTER_TO_UINT (cfg->domain));
4466 no_domain_branch = code;
4467 x86_branch8 (code, X86_CC_NE, 0, 0);
4468 code = mono_x86_emit_tls_get ( code, X86_EAX, lmf_tls_offset);
4469 x86_test_reg_reg (code, X86_EAX, X86_EAX);
4471 x86_branch8 (code, X86_CC_NE, 0, 0);
4472 x86_patch (no_domain_branch, code);
4473 x86_push_imm (code, cfg->domain);
4474 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4475 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
4476 x86_patch (buf, code);
4477 #ifdef PLATFORM_WIN32
4478 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4479 /* FIXME: Add a separate key for LMF to avoid this */
4480 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4484 g_assert (!cfg->compile_aot);
4485 x86_push_imm (code, cfg->domain);
4486 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4487 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
4491 if (method->save_lmf) {
4492 pos += sizeof (MonoLMF);
4494 /* save the current IP */
4495 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
4496 x86_push_imm_template (code);
4497 cfa_offset += sizeof (gpointer);
4499 /* save all caller saved regs */
4500 x86_push_reg (code, X86_EBP);
4501 cfa_offset += sizeof (gpointer);
4502 x86_push_reg (code, X86_ESI);
4503 cfa_offset += sizeof (gpointer);
4504 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
4505 x86_push_reg (code, X86_EDI);
4506 cfa_offset += sizeof (gpointer);
4507 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
4508 x86_push_reg (code, X86_EBX);
4509 cfa_offset += sizeof (gpointer);
4510 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
4512 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
4514 * Optimized version which uses the mono_lmf TLS variable instead of indirection
4515 * through the mono_lmf_addr TLS variable.
4517 /* %eax = previous_lmf */
4518 x86_prefix (code, X86_GS_PREFIX);
4519 x86_mov_reg_mem (code, X86_EAX, lmf_tls_offset, 4);
4520 /* skip esp + method_info + lmf */
4521 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 12);
4522 /* push previous_lmf */
4523 x86_push_reg (code, X86_EAX);
4525 x86_prefix (code, X86_GS_PREFIX);
4526 x86_mov_mem_reg (code, lmf_tls_offset, X86_ESP, 4);
4528 /* get the address of lmf for the current thread */
4530 * This is performance critical so we try to use some tricks to make
4534 if (lmf_addr_tls_offset != -1) {
4535 /* Load lmf quicky using the GS register */
4536 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
4537 #ifdef PLATFORM_WIN32
4538 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4539 /* FIXME: Add a separate key for LMF to avoid this */
4540 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4543 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
4546 /* Skip esp + method info */
4547 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
4550 x86_push_reg (code, X86_EAX);
4551 /* push *lfm (previous_lmf) */
4552 x86_push_membase (code, X86_EAX, 0);
4554 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
4558 if (cfg->used_int_regs & (1 << X86_EBX)) {
4559 x86_push_reg (code, X86_EBX);
4561 cfa_offset += sizeof (gpointer);
4562 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
4565 if (cfg->used_int_regs & (1 << X86_EDI)) {
4566 x86_push_reg (code, X86_EDI);
4568 cfa_offset += sizeof (gpointer);
4569 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
4572 if (cfg->used_int_regs & (1 << X86_ESI)) {
4573 x86_push_reg (code, X86_ESI);
4575 cfa_offset += sizeof (gpointer);
4576 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
4582 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
4583 if (mono_do_x86_stack_align && need_stack_frame) {
4584 int tot = alloc_size + pos + 4; /* ret ip */
4585 if (need_stack_frame)
4587 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
4589 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
4593 /* See mono_emit_stack_alloc */
4594 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4595 guint32 remaining_size = alloc_size;
4596 while (remaining_size >= 0x1000) {
4597 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
4598 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
4599 remaining_size -= 0x1000;
4602 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
4604 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
4607 g_assert (need_stack_frame);
4610 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
4611 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
4612 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
4615 #if DEBUG_STACK_ALIGNMENT
4616 /* check the stack is aligned */
4617 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
4618 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
4619 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
4620 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
4621 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
4622 x86_breakpoint (code);
4626 /* compute max_offset in order to use short forward jumps */
4628 if (cfg->opt & MONO_OPT_BRANCH) {
4629 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4631 bb->max_offset = max_offset;
4633 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4635 /* max alignment for loops */
4636 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4637 max_offset += LOOP_ALIGNMENT;
4639 MONO_BB_FOR_EACH_INS (bb, ins) {
4640 if (ins->opcode == OP_LABEL)
4641 ins->inst_c1 = max_offset;
4643 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4648 /* store runtime generic context */
4649 if (cfg->rgctx_var) {
4650 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
4652 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
4655 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4656 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4658 /* load arguments allocated to register from the stack */
4659 sig = mono_method_signature (method);
4662 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4663 inst = cfg->args [pos];
4664 if (inst->opcode == OP_REGVAR) {
4665 g_assert (need_stack_frame);
4666 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
4667 if (cfg->verbose_level > 2)
4668 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
4673 cfg->code_len = code - cfg->native_code;
4675 g_assert (cfg->code_len < cfg->code_size);
4681 mono_arch_emit_epilog (MonoCompile *cfg)
4683 MonoMethod *method = cfg->method;
4684 MonoMethodSignature *sig = mono_method_signature (method);
4686 guint32 stack_to_pop;
4688 int max_epilog_size = 16;
4690 gboolean need_stack_frame = needs_stack_frame (cfg);
4692 if (cfg->method->save_lmf)
4693 max_epilog_size += 128;
4695 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4696 cfg->code_size *= 2;
4697 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4698 mono_jit_stats.code_reallocs++;
4701 code = cfg->native_code + cfg->code_len;
4703 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4704 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4706 /* the code restoring the registers must be kept in sync with OP_JMP */
4709 if (method->save_lmf) {
4710 gint32 prev_lmf_reg;
4711 gint32 lmf_offset = -sizeof (MonoLMF);
4713 /* check if we need to restore protection of the stack after a stack overflow */
4714 if (mono_get_jit_tls_offset () != -1) {
4716 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
4717 /* we load the value in a separate instruction: this mechanism may be
4718 * used later as a safer way to do thread interruption
4720 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
4721 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
4723 x86_branch8 (code, X86_CC_Z, 0, FALSE);
4724 /* note that the call trampoline will preserve eax/edx */
4725 x86_call_reg (code, X86_ECX);
4726 x86_patch (patch, code);
4728 /* FIXME: maybe save the jit tls in the prolog */
4730 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
4732 * Optimized version which uses the mono_lmf TLS variable instead of indirection
4733 * through the mono_lmf_addr TLS variable.
4735 /* reg = previous_lmf */
4736 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
4738 /* lmf = previous_lmf */
4739 x86_prefix (code, X86_GS_PREFIX);
4740 x86_mov_mem_reg (code, lmf_tls_offset, X86_ECX, 4);
4742 /* Find a spare register */
4743 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
4746 prev_lmf_reg = X86_EDI;
4747 cfg->used_int_regs |= (1 << X86_EDI);
4750 prev_lmf_reg = X86_EDX;
4754 /* reg = previous_lmf */
4755 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
4758 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
4760 /* *(lmf) = previous_lmf */
4761 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
4764 /* restore caller saved regs */
4765 if (cfg->used_int_regs & (1 << X86_EBX)) {
4766 x86_mov_reg_membase (code, X86_EBX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
4769 if (cfg->used_int_regs & (1 << X86_EDI)) {
4770 x86_mov_reg_membase (code, X86_EDI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
4772 if (cfg->used_int_regs & (1 << X86_ESI)) {
4773 x86_mov_reg_membase (code, X86_ESI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
4776 /* EBP is restored by LEAVE */
4778 if (cfg->used_int_regs & (1 << X86_EBX)) {
4781 if (cfg->used_int_regs & (1 << X86_EDI)) {
4784 if (cfg->used_int_regs & (1 << X86_ESI)) {
4789 g_assert (need_stack_frame);
4790 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
4793 if (cfg->used_int_regs & (1 << X86_ESI)) {
4794 x86_pop_reg (code, X86_ESI);
4796 if (cfg->used_int_regs & (1 << X86_EDI)) {
4797 x86_pop_reg (code, X86_EDI);
4799 if (cfg->used_int_regs & (1 << X86_EBX)) {
4800 x86_pop_reg (code, X86_EBX);
4804 /* Load returned vtypes into registers if needed */
4805 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
4806 if (cinfo->ret.storage == ArgValuetypeInReg) {
4807 for (quad = 0; quad < 2; quad ++) {
4808 switch (cinfo->ret.pair_storage [quad]) {
4810 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
4812 case ArgOnFloatFpStack:
4813 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
4815 case ArgOnDoubleFpStack:
4816 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
4821 g_assert_not_reached ();
4826 if (need_stack_frame)
4829 if (CALLCONV_IS_STDCALL (sig)) {
4830 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
4832 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
4833 } else if (MONO_TYPE_ISSTRUCT (mono_method_signature (cfg->method)->ret) && (cinfo->ret.storage == ArgOnStack))
4839 g_assert (need_stack_frame);
4840 x86_ret_imm (code, stack_to_pop);
4845 cfg->code_len = code - cfg->native_code;
4847 g_assert (cfg->code_len < cfg->code_size);
4851 mono_arch_emit_exceptions (MonoCompile *cfg)
4853 MonoJumpInfo *patch_info;
4856 MonoClass *exc_classes [16];
4857 guint8 *exc_throw_start [16], *exc_throw_end [16];
4861 /* Compute needed space */
4862 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4863 if (patch_info->type == MONO_PATCH_INFO_EXC)
4868 * make sure we have enough space for exceptions
4869 * 16 is the size of two push_imm instructions and a call
4871 if (cfg->compile_aot)
4872 code_size = exc_count * 32;
4874 code_size = exc_count * 16;
4876 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4877 cfg->code_size *= 2;
4878 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4879 mono_jit_stats.code_reallocs++;
4882 code = cfg->native_code + cfg->code_len;
4885 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4886 switch (patch_info->type) {
4887 case MONO_PATCH_INFO_EXC: {
4888 MonoClass *exc_class;
4892 x86_patch (patch_info->ip.i + cfg->native_code, code);
4894 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4895 g_assert (exc_class);
4896 throw_ip = patch_info->ip.i;
4898 /* Find a throw sequence for the same exception class */
4899 for (i = 0; i < nthrows; ++i)
4900 if (exc_classes [i] == exc_class)
4903 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
4904 x86_jump_code (code, exc_throw_start [i]);
4905 patch_info->type = MONO_PATCH_INFO_NONE;
4910 /* Compute size of code following the push <OFFSET> */
4913 if ((code - cfg->native_code) - throw_ip < 126 - size) {
4914 /* Use the shorter form */
4916 x86_push_imm (code, 0);
4920 x86_push_imm (code, 0xf0f0f0f0);
4925 exc_classes [nthrows] = exc_class;
4926 exc_throw_start [nthrows] = code;
4929 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
4930 patch_info->data.name = "mono_arch_throw_corlib_exception";
4931 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4932 patch_info->ip.i = code - cfg->native_code;
4933 x86_call_code (code, 0);
4934 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
4939 exc_throw_end [nthrows] = code;
4951 cfg->code_len = code - cfg->native_code;
4953 g_assert (cfg->code_len < cfg->code_size);
4957 mono_arch_flush_icache (guint8 *code, gint size)
4963 mono_arch_flush_register_windows (void)
4968 mono_arch_is_inst_imm (gint64 imm)
4974 * Support for fast access to the thread-local lmf structure using the GS
4975 * segment register on NPTL + kernel 2.6.x.
4978 static gboolean tls_offset_inited = FALSE;
4981 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
4983 if (!tls_offset_inited) {
4984 if (!getenv ("MONO_NO_TLS")) {
4985 #ifdef PLATFORM_WIN32
4987 * We need to init this multiple times, since when we are first called, the key might not
4988 * be initialized yet.
4990 appdomain_tls_offset = mono_domain_get_tls_key ();
4991 lmf_tls_offset = mono_get_jit_tls_key ();
4992 thread_tls_offset = mono_thread_get_tls_key ();
4994 /* Only 64 tls entries can be accessed using inline code */
4995 if (appdomain_tls_offset >= 64)
4996 appdomain_tls_offset = -1;
4997 if (lmf_tls_offset >= 64)
4998 lmf_tls_offset = -1;
4999 if (thread_tls_offset >= 64)
5000 thread_tls_offset = -1;
5003 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5005 tls_offset_inited = TRUE;
5006 appdomain_tls_offset = mono_domain_get_tls_offset ();
5007 lmf_tls_offset = mono_get_lmf_tls_offset ();
5008 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5009 thread_tls_offset = mono_thread_get_tls_offset ();
5016 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5020 #ifdef MONO_ARCH_HAVE_IMT
5022 // Linear handler, the bsearch head compare is shorter
5023 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5024 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5025 // x86_patch(ins,target)
5026 //[1 + 5] x86_jump_mem(inst,mem)
5029 #define BR_SMALL_SIZE 2
5030 #define BR_LARGE_SIZE 5
5031 #define JUMP_IMM_SIZE 6
5032 #define ENABLE_WRONG_METHOD_CHECK 0
5035 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5037 int i, distance = 0;
5038 for (i = start; i < target; ++i)
5039 distance += imt_entries [i]->chunk_size;
5044 * LOCKING: called with the domain lock held
5047 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5048 gpointer fail_tramp)
5052 guint8 *code, *start;
5054 for (i = 0; i < count; ++i) {
5055 MonoIMTCheckItem *item = imt_entries [i];
5056 if (item->is_equals) {
5057 if (item->check_target_idx) {
5058 if (!item->compare_done)
5059 item->chunk_size += CMP_SIZE;
5060 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5063 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5065 item->chunk_size += JUMP_IMM_SIZE;
5066 #if ENABLE_WRONG_METHOD_CHECK
5067 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5072 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5073 imt_entries [item->check_target_idx]->compare_done = TRUE;
5075 size += item->chunk_size;
5078 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5080 code = mono_domain_code_reserve (domain, size);
5082 for (i = 0; i < count; ++i) {
5083 MonoIMTCheckItem *item = imt_entries [i];
5084 item->code_target = code;
5085 if (item->is_equals) {
5086 if (item->check_target_idx) {
5087 if (!item->compare_done)
5088 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5089 item->jmp_code = code;
5090 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5091 if (item->has_target_code)
5092 x86_jump_code (code, item->value.target_code);
5094 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5097 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5098 item->jmp_code = code;
5099 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5100 if (item->has_target_code)
5101 x86_jump_code (code, item->value.target_code);
5103 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5104 x86_patch (item->jmp_code, code);
5105 x86_jump_code (code, fail_tramp);
5106 item->jmp_code = NULL;
5108 /* enable the commented code to assert on wrong method */
5109 #if ENABLE_WRONG_METHOD_CHECK
5110 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5111 item->jmp_code = code;
5112 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5114 if (item->has_target_code)
5115 x86_jump_code (code, item->value.target_code);
5117 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5118 #if ENABLE_WRONG_METHOD_CHECK
5119 x86_patch (item->jmp_code, code);
5120 x86_breakpoint (code);
5121 item->jmp_code = NULL;
5126 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5127 item->jmp_code = code;
5128 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5129 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5131 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5134 /* patch the branches to get to the target items */
5135 for (i = 0; i < count; ++i) {
5136 MonoIMTCheckItem *item = imt_entries [i];
5137 if (item->jmp_code) {
5138 if (item->check_target_idx) {
5139 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5145 mono_stats.imt_thunks_size += code - start;
5146 g_assert (code - start <= size);
5151 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
5153 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5157 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
5159 MonoMethodSignature *sig = mono_method_signature (method);
5160 CallInfo *cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5161 int this_argument_offset;
5162 MonoObject *this_argument;
5165 * this is the offset of the this arg from esp as saved at the start of
5166 * mono_arch_create_trampoline_code () in tramp-x86.c.
5168 this_argument_offset = 5;
5169 if (MONO_TYPE_ISSTRUCT (sig->ret) && (cinfo->ret.storage == ArgOnStack))
5170 this_argument_offset++;
5172 this_argument = * (MonoObject**) (((guint8*) regs [X86_ESP]) + this_argument_offset * sizeof (gpointer));
5175 return this_argument;
5180 mono_arch_find_static_call_vtable (gpointer *regs, guint8 *code)
5182 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5186 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5188 MonoInst *ins = NULL;
5191 if (cmethod->klass == mono_defaults.math_class) {
5192 if (strcmp (cmethod->name, "Sin") == 0) {
5194 } else if (strcmp (cmethod->name, "Cos") == 0) {
5196 } else if (strcmp (cmethod->name, "Tan") == 0) {
5198 } else if (strcmp (cmethod->name, "Atan") == 0) {
5200 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5202 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5204 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5209 MONO_INST_NEW (cfg, ins, opcode);
5210 ins->type = STACK_R8;
5211 ins->dreg = mono_alloc_freg (cfg);
5212 ins->sreg1 = args [0]->dreg;
5213 MONO_ADD_INS (cfg->cbb, ins);
5216 if (cfg->opt & MONO_OPT_CMOV) {
5219 if (strcmp (cmethod->name, "Min") == 0) {
5220 if (fsig->params [0]->type == MONO_TYPE_I4)
5222 } else if (strcmp (cmethod->name, "Max") == 0) {
5223 if (fsig->params [0]->type == MONO_TYPE_I4)
5228 MONO_INST_NEW (cfg, ins, opcode);
5229 ins->type = STACK_I4;
5230 ins->dreg = mono_alloc_ireg (cfg);
5231 ins->sreg1 = args [0]->dreg;
5232 ins->sreg2 = args [1]->dreg;
5233 MONO_ADD_INS (cfg->cbb, ins);
5238 /* OP_FREM is not IEEE compatible */
5239 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5240 MONO_INST_NEW (cfg, ins, OP_FREM);
5241 ins->inst_i0 = args [0];
5242 ins->inst_i1 = args [1];
5251 mono_arch_print_tree (MonoInst *tree, int arity)
5256 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5262 if (appdomain_tls_offset == -1)
5265 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5266 ins->inst_offset = appdomain_tls_offset;
5270 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
5274 if (thread_tls_offset == -1)
5277 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5278 ins->inst_offset = thread_tls_offset;
5283 mono_arch_get_patch_offset (guint8 *code)
5285 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5287 else if ((code [0] == 0xba))
5289 else if ((code [0] == 0x68))
5292 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5293 /* push <OFFSET>(<REG>) */
5295 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5296 /* call *<OFFSET>(<REG>) */
5298 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5301 else if ((code [0] == 0x58) && (code [1] == 0x05))
5302 /* pop %eax; add <OFFSET>, %eax */
5304 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5305 /* pop <REG>; add <OFFSET>, <REG> */
5307 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5308 /* mov <REG>, imm */
5311 g_assert_not_reached ();
5317 * mono_breakpoint_clean_code:
5319 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5320 * breakpoints in the original code, they are removed in the copy.
5322 * Returns TRUE if no sw breakpoint was present.
5325 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5328 gboolean can_write = TRUE;
5330 * If method_start is non-NULL we need to perform bound checks, since we access memory
5331 * at code - offset we could go before the start of the method and end up in a different
5332 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5335 if (!method_start || code - offset >= method_start) {
5336 memcpy (buf, code - offset, size);
5338 int diff = code - method_start;
5339 memset (buf, 0, size);
5340 memcpy (buf + offset - diff, method_start, diff + size - offset);
5343 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5344 int idx = mono_breakpoint_info_index [i];
5348 ptr = mono_breakpoint_info [idx].address;
5349 if (ptr >= code && ptr < code + size) {
5350 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5352 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5353 buf [ptr - code] = saved_byte;
5360 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5366 mono_breakpoint_clean_code (NULL, code, 8, buf, sizeof (buf));
5374 * A given byte sequence can match more than case here, so we have to be
5375 * really careful about the ordering of the cases. Longer sequences
5377 * There are two types of calls:
5378 * - direct calls: 0xff address_byte 8/32 bits displacement
5379 * - indirect calls: nop nop nop <call>
5380 * The nops make sure we don't confuse the instruction preceeding an indirect
5381 * call with a direct call.
5383 if ((code [1] != 0xe8) && (code [3] == 0xff) && ((code [4] & 0x18) == 0x10) && ((code [4] >> 6) == 1)) {
5384 reg = code [4] & 0x07;
5385 disp = (signed char)code [5];
5386 } else if ((code [0] == 0xff) && ((code [1] & 0x18) == 0x10) && ((code [1] >> 6) == 2)) {
5387 reg = code [1] & 0x07;
5388 disp = *((gint32*)(code + 2));
5389 } else if ((code [1] == 0xe8)) {
5391 } else if ((code [4] == 0xff) && (((code [5] >> 6) & 0x3) == 0) && (((code [5] >> 3) & 0x7) == 2)) {
5393 * This is a interface call
5394 * 8b 40 30 mov 0x30(%eax),%eax
5395 * ff 10 call *(%eax)
5398 reg = code [5] & 0x07;
5403 *displacement = disp;
5408 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig,
5409 gssize *regs, guint8 *code)
5411 guint32 esp = regs [X86_ESP];
5412 CallInfo *cinfo = NULL;
5417 * Avoid expensive calls to get_generic_context_from_code () + get_call_info
5420 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5422 gsctx = mono_get_generic_context_from_code (code);
5423 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5425 offset = cinfo->args [0].offset;
5431 * The stack looks like:
5434 * <possible vtype return address>
5436 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
5438 res = (((MonoObject**)esp) [5 + (offset / 4)]);
5444 #define MAX_ARCH_DELEGATE_PARAMS 10
5447 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5449 guint8 *code, *start;
5451 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5454 /* FIXME: Support more cases */
5455 if (MONO_TYPE_ISSTRUCT (sig->ret))
5459 * The stack contains:
5465 static guint8* cached = NULL;
5469 start = code = mono_global_codeman_reserve (64);
5471 /* Replace the this argument with the target */
5472 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5473 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
5474 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5475 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5477 g_assert ((code - start) < 64);
5479 mono_debug_add_delegate_trampoline (start, code - start);
5481 mono_memory_barrier ();
5485 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5487 /* 8 for mov_reg and jump, plus 8 for each parameter */
5488 int code_reserve = 8 + (sig->param_count * 8);
5490 for (i = 0; i < sig->param_count; ++i)
5491 if (!mono_is_regsize_var (sig->params [i]))
5494 code = cache [sig->param_count];
5499 * The stack contains:
5500 * <args in reverse order>
5505 * <args in reverse order>
5508 * without unbalancing the stack.
5509 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
5510 * and leaving original spot of first arg as placeholder in stack so
5511 * when callee pops stack everything works.
5514 start = code = mono_global_codeman_reserve (code_reserve);
5516 /* store delegate for access to method_ptr */
5517 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
5520 for (i = 0; i < sig->param_count; ++i) {
5521 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
5522 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
5525 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5527 g_assert ((code - start) < code_reserve);
5529 mono_debug_add_delegate_trampoline (start, code - start);
5531 mono_memory_barrier ();
5533 cache [sig->param_count] = start;
5540 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5543 case X86_EAX: return (gpointer)ctx->eax;
5544 case X86_EBX: return (gpointer)ctx->ebx;
5545 case X86_ECX: return (gpointer)ctx->ecx;
5546 case X86_EDX: return (gpointer)ctx->edx;
5547 case X86_ESP: return (gpointer)ctx->esp;
5548 case X86_EBP: return (gpointer)ctx->ebp;
5549 case X86_ESI: return (gpointer)ctx->esi;
5550 case X86_EDI: return (gpointer)ctx->edi;
5551 default: g_assert_not_reached ();
5555 #ifdef MONO_ARCH_SIMD_INTRINSICS
5558 get_float_to_x_spill_area (MonoCompile *cfg)
5560 if (!cfg->fconv_to_r8_x_var) {
5561 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
5562 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
5564 return cfg->fconv_to_r8_x_var;
5568 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
5571 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
5574 int dreg, src_opcode;
5576 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
5579 switch (src_opcode = ins->opcode) {
5580 case OP_FCONV_TO_I1:
5581 case OP_FCONV_TO_U1:
5582 case OP_FCONV_TO_I2:
5583 case OP_FCONV_TO_U2:
5584 case OP_FCONV_TO_I4:
5591 /* dreg is the IREG and sreg1 is the FREG */
5592 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
5593 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
5594 fconv->sreg1 = ins->sreg1;
5595 fconv->dreg = mono_alloc_ireg (cfg);
5596 fconv->type = STACK_VTYPE;
5597 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
5599 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
5603 ins->opcode = OP_XCONV_R8_TO_I4;
5605 ins->klass = mono_defaults.int32_class;
5606 ins->sreg1 = fconv->dreg;
5608 ins->type = STACK_I4;
5609 ins->backend.source_opcode = src_opcode;
5612 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
5615 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
5620 if (long_ins->opcode == OP_LNEG) {
5622 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
5623 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
5624 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
5629 #ifdef MONO_ARCH_SIMD_INTRINSICS
5631 if (!(cfg->opt & MONO_OPT_SIMD))
5634 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
5635 switch (long_ins->opcode) {
5637 vreg = long_ins->sreg1;
5639 if (long_ins->inst_c0) {
5640 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
5641 ins->klass = long_ins->klass;
5642 ins->sreg1 = long_ins->sreg1;
5644 ins->type = STACK_VTYPE;
5645 ins->dreg = vreg = alloc_ireg (cfg);
5646 MONO_ADD_INS (cfg->cbb, ins);
5649 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
5650 ins->klass = mono_defaults.int32_class;
5652 ins->type = STACK_I4;
5653 ins->dreg = long_ins->dreg + 1;
5654 MONO_ADD_INS (cfg->cbb, ins);
5656 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
5657 ins->klass = long_ins->klass;
5658 ins->sreg1 = long_ins->sreg1;
5659 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
5660 ins->type = STACK_VTYPE;
5661 ins->dreg = vreg = alloc_ireg (cfg);
5662 MONO_ADD_INS (cfg->cbb, ins);
5664 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
5665 ins->klass = mono_defaults.int32_class;
5667 ins->type = STACK_I4;
5668 ins->dreg = long_ins->dreg + 2;
5669 MONO_ADD_INS (cfg->cbb, ins);
5671 long_ins->opcode = OP_NOP;
5673 case OP_INSERTX_I8_SLOW:
5674 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
5675 ins->dreg = long_ins->dreg;
5676 ins->sreg1 = long_ins->dreg;
5677 ins->sreg2 = long_ins->sreg2 + 1;
5678 ins->inst_c0 = long_ins->inst_c0 * 2;
5679 MONO_ADD_INS (cfg->cbb, ins);
5681 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
5682 ins->dreg = long_ins->dreg;
5683 ins->sreg1 = long_ins->dreg;
5684 ins->sreg2 = long_ins->sreg2 + 2;
5685 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
5686 MONO_ADD_INS (cfg->cbb, ins);
5688 long_ins->opcode = OP_NOP;
5691 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
5692 ins->dreg = long_ins->dreg;
5693 ins->sreg1 = long_ins->sreg1 + 1;
5694 ins->klass = long_ins->klass;
5695 ins->type = STACK_VTYPE;
5696 MONO_ADD_INS (cfg->cbb, ins);
5698 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
5699 ins->dreg = long_ins->dreg;
5700 ins->sreg1 = long_ins->dreg;
5701 ins->sreg2 = long_ins->sreg1 + 2;
5703 ins->klass = long_ins->klass;
5704 ins->type = STACK_VTYPE;
5705 MONO_ADD_INS (cfg->cbb, ins);
5707 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
5708 ins->dreg = long_ins->dreg;
5709 ins->sreg1 = long_ins->dreg;;
5710 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
5711 ins->klass = long_ins->klass;
5712 ins->type = STACK_VTYPE;
5713 MONO_ADD_INS (cfg->cbb, ins);
5715 long_ins->opcode = OP_NOP;
5718 #endif /* MONO_ARCH_SIMD_INTRINSICS */