2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/appdomain.h>
21 #include <mono/metadata/debug-helpers.h>
22 #include <mono/metadata/threads.h>
23 #include <mono/metadata/profiler-private.h>
24 #include <mono/metadata/mono-debug.h>
25 #include <mono/metadata/gc-internal.h>
26 #include <mono/utils/mono-math.h>
27 #include <mono/utils/mono-counters.h>
28 #include <mono/utils/mono-mmap.h>
29 #include <mono/utils/mono-memory-model.h>
30 #include <mono/utils/mono-hwcap-x86.h>
38 /* On windows, these hold the key returned by TlsAlloc () */
39 static gint lmf_tls_offset = -1;
41 static gint jit_tls_offset = -1;
43 static gint lmf_addr_tls_offset = -1;
45 static gint appdomain_tls_offset = -1;
48 static gboolean optimize_for_xen = TRUE;
50 #define optimize_for_xen 0
54 static gboolean is_win32 = TRUE;
56 static gboolean is_win32 = FALSE;
59 /* This mutex protects architecture specific caches */
60 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
61 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
62 static CRITICAL_SECTION mini_arch_mutex;
64 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
69 /* Under windows, the default pinvoke calling convention is stdcall */
70 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT))
72 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL)
75 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
78 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
81 #ifdef __native_client_codegen__
83 /* Default alignment for Native Client is 32-byte. */
84 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
86 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
87 /* Check that alignment doesn't cross an alignment boundary. */
89 mono_arch_nacl_pad (guint8 *code, int pad)
91 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
93 if (pad == 0) return code;
94 /* assertion: alignment cannot cross a block boundary */
95 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
96 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
97 while (pad >= kMaxPadding) {
98 x86_padding (code, kMaxPadding);
101 if (pad != 0) x86_padding (code, pad);
106 mono_arch_nacl_skip_nops (guint8 *code)
108 x86_skip_nops (code);
112 #endif /* __native_client_codegen__ */
115 * The code generated for sequence points reads from this location, which is
116 * made read-only when single stepping is enabled.
118 static gpointer ss_trigger_page;
120 /* Enabled breakpoints read from this trigger page */
121 static gpointer bp_trigger_page;
124 mono_arch_regname (int reg)
127 case X86_EAX: return "%eax";
128 case X86_EBX: return "%ebx";
129 case X86_ECX: return "%ecx";
130 case X86_EDX: return "%edx";
131 case X86_ESP: return "%esp";
132 case X86_EBP: return "%ebp";
133 case X86_EDI: return "%edi";
134 case X86_ESI: return "%esi";
140 mono_arch_fregname (int reg)
165 mono_arch_xregname (int reg)
190 mono_x86_patch (unsigned char* code, gpointer target)
192 x86_patch (code, (unsigned char*)target);
203 /* gsharedvt argument passed by addr */
215 /* Only if storage == ArgValuetypeInReg */
216 ArgStorage pair_storage [2];
225 gboolean need_stack_align;
226 guint32 stack_align_amount;
227 gboolean vtype_retaddr;
228 /* The index of the vret arg in the argument list */
238 #define FLOAT_PARAM_REGS 0
240 static X86_Reg_No param_regs [] = { 0 };
242 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
243 #define SMALL_STRUCTS_IN_REGS
244 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
248 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
250 ainfo->offset = *stack_size;
252 if (*gr >= PARAM_REGS) {
253 ainfo->storage = ArgOnStack;
255 (*stack_size) += sizeof (gpointer);
258 ainfo->storage = ArgInIReg;
259 ainfo->reg = param_regs [*gr];
265 add_general_pair (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
267 ainfo->offset = *stack_size;
269 g_assert (PARAM_REGS == 0);
271 ainfo->storage = ArgOnStack;
272 (*stack_size) += sizeof (gpointer) * 2;
277 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
279 ainfo->offset = *stack_size;
281 if (*gr >= FLOAT_PARAM_REGS) {
282 ainfo->storage = ArgOnStack;
283 (*stack_size) += is_double ? 8 : 4;
284 ainfo->nslots = is_double ? 2 : 1;
287 /* A double register */
289 ainfo->storage = ArgInDoubleSSEReg;
291 ainfo->storage = ArgInFloatSSEReg;
299 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
301 guint32 *gr, guint32 *fr, guint32 *stack_size)
306 klass = mono_class_from_mono_type (type);
307 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
309 #ifdef SMALL_STRUCTS_IN_REGS
310 if (sig->pinvoke && is_return) {
311 MonoMarshalType *info;
314 * the exact rules are not very well documented, the code below seems to work with the
315 * code generated by gcc 3.3.3 -mno-cygwin.
317 info = mono_marshal_load_type_info (klass);
320 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
322 /* Special case structs with only a float member */
323 if ((info->native_size == 8) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R8)) {
324 ainfo->storage = ArgValuetypeInReg;
325 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
328 if ((info->native_size == 4) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R4)) {
329 ainfo->storage = ArgValuetypeInReg;
330 ainfo->pair_storage [0] = ArgOnFloatFpStack;
333 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
334 ainfo->storage = ArgValuetypeInReg;
335 ainfo->pair_storage [0] = ArgInIReg;
336 ainfo->pair_regs [0] = return_regs [0];
337 if (info->native_size > 4) {
338 ainfo->pair_storage [1] = ArgInIReg;
339 ainfo->pair_regs [1] = return_regs [1];
346 ainfo->offset = *stack_size;
347 ainfo->storage = ArgOnStack;
348 *stack_size += ALIGN_TO (size, sizeof (gpointer));
349 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
355 * Obtain information about a call according to the calling convention.
356 * For x86 ELF, see the "System V Application Binary Interface Intel386
357 * Architecture Processor Supplment, Fourth Edition" document for more
359 * For x86 win32, see ???.
362 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
364 guint32 i, gr, fr, pstart;
366 int n = sig->hasthis + sig->param_count;
367 guint32 stack_size = 0;
368 gboolean is_pinvoke = sig->pinvoke;
376 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
377 switch (ret_type->type) {
378 case MONO_TYPE_BOOLEAN:
389 case MONO_TYPE_FNPTR:
390 case MONO_TYPE_CLASS:
391 case MONO_TYPE_OBJECT:
392 case MONO_TYPE_SZARRAY:
393 case MONO_TYPE_ARRAY:
394 case MONO_TYPE_STRING:
395 cinfo->ret.storage = ArgInIReg;
396 cinfo->ret.reg = X86_EAX;
400 cinfo->ret.storage = ArgInIReg;
401 cinfo->ret.reg = X86_EAX;
402 cinfo->ret.is_pair = TRUE;
405 cinfo->ret.storage = ArgOnFloatFpStack;
408 cinfo->ret.storage = ArgOnDoubleFpStack;
410 case MONO_TYPE_GENERICINST:
411 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
412 cinfo->ret.storage = ArgInIReg;
413 cinfo->ret.reg = X86_EAX;
416 if (mini_is_gsharedvt_type_gsctx (gsctx, ret_type)) {
417 cinfo->ret.storage = ArgOnStack;
418 cinfo->vtype_retaddr = TRUE;
422 case MONO_TYPE_VALUETYPE:
423 case MONO_TYPE_TYPEDBYREF: {
424 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
426 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
427 if (cinfo->ret.storage == ArgOnStack) {
428 cinfo->vtype_retaddr = TRUE;
429 /* The caller passes the address where the value is stored */
435 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ret_type));
436 cinfo->ret.storage = ArgOnStack;
437 cinfo->vtype_retaddr = TRUE;
440 cinfo->ret.storage = ArgNone;
443 g_error ("Can't handle as return value 0x%x", sig->ret->type);
449 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
450 * the first argument, allowing 'this' to be always passed in the first arg reg.
451 * Also do this if the first argument is a reference type, since virtual calls
452 * are sometimes made using calli without sig->hasthis set, like in the delegate
455 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
457 add_general (&gr, &stack_size, cinfo->args + 0);
459 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
462 cinfo->vret_arg_offset = stack_size;
463 add_general (&gr, &stack_size, &cinfo->ret);
464 cinfo->vret_arg_index = 1;
468 add_general (&gr, &stack_size, cinfo->args + 0);
470 if (cinfo->vtype_retaddr)
471 add_general (&gr, &stack_size, &cinfo->ret);
474 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
476 fr = FLOAT_PARAM_REGS;
478 /* Emit the signature cookie just before the implicit arguments */
479 add_general (&gr, &stack_size, &cinfo->sig_cookie);
482 for (i = pstart; i < sig->param_count; ++i) {
483 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
486 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
487 /* We allways pass the sig cookie on the stack for simplicity */
489 * Prevent implicit arguments + the sig cookie from being passed
493 fr = FLOAT_PARAM_REGS;
495 /* Emit the signature cookie just before the implicit arguments */
496 add_general (&gr, &stack_size, &cinfo->sig_cookie);
499 if (sig->params [i]->byref) {
500 add_general (&gr, &stack_size, ainfo);
503 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
504 switch (ptype->type) {
505 case MONO_TYPE_BOOLEAN:
508 add_general (&gr, &stack_size, ainfo);
513 add_general (&gr, &stack_size, ainfo);
517 add_general (&gr, &stack_size, ainfo);
522 case MONO_TYPE_FNPTR:
523 case MONO_TYPE_CLASS:
524 case MONO_TYPE_OBJECT:
525 case MONO_TYPE_STRING:
526 case MONO_TYPE_SZARRAY:
527 case MONO_TYPE_ARRAY:
528 add_general (&gr, &stack_size, ainfo);
530 case MONO_TYPE_GENERICINST:
531 if (!mono_type_generic_inst_is_valuetype (ptype)) {
532 add_general (&gr, &stack_size, ainfo);
535 if (mini_is_gsharedvt_type_gsctx (gsctx, ptype)) {
536 /* gsharedvt arguments are passed by ref */
537 add_general (&gr, &stack_size, ainfo);
538 g_assert (ainfo->storage == ArgOnStack);
539 ainfo->storage = ArgGSharedVt;
543 case MONO_TYPE_VALUETYPE:
544 case MONO_TYPE_TYPEDBYREF:
545 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
549 add_general_pair (&gr, &stack_size, ainfo);
552 add_float (&fr, &stack_size, ainfo, FALSE);
555 add_float (&fr, &stack_size, ainfo, TRUE);
559 /* gsharedvt arguments are passed by ref */
560 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ptype));
561 add_general (&gr, &stack_size, ainfo);
562 g_assert (ainfo->storage == ArgOnStack);
563 ainfo->storage = ArgGSharedVt;
566 g_error ("unexpected type 0x%x", ptype->type);
567 g_assert_not_reached ();
571 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
573 fr = FLOAT_PARAM_REGS;
575 /* Emit the signature cookie just before the implicit arguments */
576 add_general (&gr, &stack_size, &cinfo->sig_cookie);
579 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
580 cinfo->need_stack_align = TRUE;
581 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
582 stack_size += cinfo->stack_align_amount;
585 cinfo->stack_usage = stack_size;
586 cinfo->reg_usage = gr;
587 cinfo->freg_usage = fr;
592 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
594 int n = sig->hasthis + sig->param_count;
598 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
600 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
602 return get_call_info_internal (gsctx, cinfo, sig);
606 * mono_arch_get_argument_info:
607 * @csig: a method signature
608 * @param_count: the number of parameters to consider
609 * @arg_info: an array to store the result infos
611 * Gathers information on parameters such as size, alignment and
612 * padding. arg_info should be large enought to hold param_count + 1 entries.
614 * Returns the size of the argument area on the stack.
615 * This should be signal safe, since it is called from
616 * mono_arch_find_jit_info ().
617 * FIXME: The metadata calls might not be signal safe.
620 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
622 int len, k, args_size = 0;
628 /* Avoid g_malloc as it is not signal safe */
629 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
630 cinfo = (CallInfo*)g_newa (guint8*, len);
631 memset (cinfo, 0, len);
633 cinfo = get_call_info_internal (gsctx, cinfo, csig);
635 arg_info [0].offset = offset;
637 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
638 args_size += sizeof (gpointer);
643 args_size += sizeof (gpointer);
647 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
648 /* Emitted after this */
649 args_size += sizeof (gpointer);
653 arg_info [0].size = args_size;
655 for (k = 0; k < param_count; k++) {
656 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
658 /* ignore alignment for now */
661 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
662 arg_info [k].pad = pad;
664 arg_info [k + 1].pad = 0;
665 arg_info [k + 1].size = size;
667 arg_info [k + 1].offset = offset;
670 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
671 /* Emitted after the first arg */
672 args_size += sizeof (gpointer);
677 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
678 align = MONO_ARCH_FRAME_ALIGNMENT;
681 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
682 arg_info [k].pad = pad;
688 mono_x86_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
693 c1 = get_call_info (NULL, NULL, caller_sig);
694 c2 = get_call_info (NULL, NULL, callee_sig);
695 res = c1->stack_usage >= c2->stack_usage;
696 if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
697 /* An address on the callee's stack is passed as the first argument */
707 * Initialize the cpu to execute managed code.
710 mono_arch_cpu_init (void)
712 /* spec compliance requires running with double precision */
716 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
717 fpcw &= ~X86_FPCW_PRECC_MASK;
718 fpcw |= X86_FPCW_PREC_DOUBLE;
719 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
720 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
722 _control87 (_PC_53, MCW_PC);
727 * Initialize architecture specific code.
730 mono_arch_init (void)
732 InitializeCriticalSection (&mini_arch_mutex);
734 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
735 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
736 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
738 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
739 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
740 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
741 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
746 * Cleanup architecture specific code.
749 mono_arch_cleanup (void)
752 mono_vfree (ss_trigger_page, mono_pagesize ());
754 mono_vfree (bp_trigger_page, mono_pagesize ());
755 DeleteCriticalSection (&mini_arch_mutex);
759 * This function returns the optimizations supported on this cpu.
762 mono_arch_cpu_optimizations (guint32 *exclude_mask)
764 #if !defined(__native_client__)
769 if (mono_hwcap_x86_has_cmov) {
770 opts |= MONO_OPT_CMOV;
772 if (mono_hwcap_x86_has_fcmov)
773 opts |= MONO_OPT_FCMOV;
775 *exclude_mask |= MONO_OPT_FCMOV;
777 *exclude_mask |= MONO_OPT_CMOV;
780 if (mono_hwcap_x86_has_sse2)
781 opts |= MONO_OPT_SSE2;
783 *exclude_mask |= MONO_OPT_SSE2;
785 #ifdef MONO_ARCH_SIMD_INTRINSICS
786 /*SIMD intrinsics require at least SSE2.*/
787 if (!mono_hwcap_x86_has_sse2)
788 *exclude_mask |= MONO_OPT_SIMD;
793 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
798 * This function test for all SSE functions supported.
800 * Returns a bitmask corresponding to all supported versions.
804 mono_arch_cpu_enumerate_simd_versions (void)
806 guint32 sse_opts = 0;
808 if (mono_hwcap_x86_has_sse1)
809 sse_opts |= SIMD_VERSION_SSE1;
811 if (mono_hwcap_x86_has_sse2)
812 sse_opts |= SIMD_VERSION_SSE2;
814 if (mono_hwcap_x86_has_sse3)
815 sse_opts |= SIMD_VERSION_SSE3;
817 if (mono_hwcap_x86_has_ssse3)
818 sse_opts |= SIMD_VERSION_SSSE3;
820 if (mono_hwcap_x86_has_sse41)
821 sse_opts |= SIMD_VERSION_SSE41;
823 if (mono_hwcap_x86_has_sse42)
824 sse_opts |= SIMD_VERSION_SSE42;
826 if (mono_hwcap_x86_has_sse4a)
827 sse_opts |= SIMD_VERSION_SSE4a;
833 * Determine whenever the trap whose info is in SIGINFO is caused by
837 mono_arch_is_int_overflow (void *sigctx, void *info)
842 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
844 ip = (guint8*)ctx.eip;
846 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
850 switch (x86_modrm_rm (ip [1])) {
870 g_assert_not_reached ();
882 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
887 for (i = 0; i < cfg->num_varinfo; i++) {
888 MonoInst *ins = cfg->varinfo [i];
889 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
892 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
895 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
896 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
899 /* we dont allocate I1 to registers because there is no simply way to sign extend
900 * 8bit quantities in caller saved registers on x86 */
901 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
902 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
903 g_assert (i == vmv->idx);
904 vars = g_list_prepend (vars, vmv);
908 vars = mono_varlist_sort (cfg, vars, 0);
914 mono_arch_get_global_int_regs (MonoCompile *cfg)
918 /* we can use 3 registers for global allocation */
919 regs = g_list_prepend (regs, (gpointer)X86_EBX);
920 regs = g_list_prepend (regs, (gpointer)X86_ESI);
921 regs = g_list_prepend (regs, (gpointer)X86_EDI);
927 * mono_arch_regalloc_cost:
929 * Return the cost, in number of memory references, of the action of
930 * allocating the variable VMV into a register during global register
934 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
936 MonoInst *ins = cfg->varinfo [vmv->idx];
938 if (cfg->method->save_lmf)
939 /* The register is already saved */
940 return (ins->opcode == OP_ARG) ? 1 : 0;
942 /* push+pop+possible load if it is an argument */
943 return (ins->opcode == OP_ARG) ? 3 : 2;
947 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
949 static int inited = FALSE;
950 static int count = 0;
952 if (cfg->arch.need_stack_frame_inited) {
953 g_assert (cfg->arch.need_stack_frame == flag);
957 cfg->arch.need_stack_frame = flag;
958 cfg->arch.need_stack_frame_inited = TRUE;
964 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
969 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
973 needs_stack_frame (MonoCompile *cfg)
975 MonoMethodSignature *sig;
976 MonoMethodHeader *header;
977 gboolean result = FALSE;
979 #if defined(__APPLE__)
980 /*OSX requires stack frame code to have the correct alignment. */
984 if (cfg->arch.need_stack_frame_inited)
985 return cfg->arch.need_stack_frame;
987 header = cfg->header;
988 sig = mono_method_signature (cfg->method);
990 if (cfg->disable_omit_fp)
992 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
994 else if (cfg->method->save_lmf)
996 else if (cfg->stack_offset)
998 else if (cfg->param_area)
1000 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1002 else if (header->num_clauses)
1004 else if (sig->param_count + sig->hasthis)
1006 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1008 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1009 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1012 set_needs_stack_frame (cfg, result);
1014 return cfg->arch.need_stack_frame;
1018 * Set var information according to the calling convention. X86 version.
1019 * The locals var stuff should most likely be split in another method.
1022 mono_arch_allocate_vars (MonoCompile *cfg)
1024 MonoMethodSignature *sig;
1025 MonoMethodHeader *header;
1027 guint32 locals_stack_size, locals_stack_align;
1032 header = cfg->header;
1033 sig = mono_method_signature (cfg->method);
1035 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1037 cfg->frame_reg = X86_EBP;
1040 /* Reserve space to save LMF and caller saved registers */
1042 if (cfg->method->save_lmf) {
1043 offset += sizeof (MonoLMF);
1045 if (cfg->used_int_regs & (1 << X86_EBX)) {
1049 if (cfg->used_int_regs & (1 << X86_EDI)) {
1053 if (cfg->used_int_regs & (1 << X86_ESI)) {
1058 switch (cinfo->ret.storage) {
1059 case ArgValuetypeInReg:
1060 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1062 cfg->ret->opcode = OP_REGOFFSET;
1063 cfg->ret->inst_basereg = X86_EBP;
1064 cfg->ret->inst_offset = - offset;
1070 /* Allocate locals */
1071 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1072 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1073 char *mname = mono_method_full_name (cfg->method, TRUE);
1074 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1075 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1079 if (locals_stack_align) {
1080 int prev_offset = offset;
1082 offset += (locals_stack_align - 1);
1083 offset &= ~(locals_stack_align - 1);
1085 while (prev_offset < offset) {
1087 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1090 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1091 cfg->locals_max_stack_offset = - offset;
1093 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1094 * have locals larger than 8 bytes we need to make sure that
1095 * they have the appropriate offset.
1097 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1098 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1099 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1100 if (offsets [i] != -1) {
1101 MonoInst *inst = cfg->varinfo [i];
1102 inst->opcode = OP_REGOFFSET;
1103 inst->inst_basereg = X86_EBP;
1104 inst->inst_offset = - (offset + offsets [i]);
1105 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1108 offset += locals_stack_size;
1112 * Allocate arguments+return value
1115 switch (cinfo->ret.storage) {
1117 if (cfg->vret_addr) {
1119 * In the new IR, the cfg->vret_addr variable represents the
1120 * vtype return value.
1122 cfg->vret_addr->opcode = OP_REGOFFSET;
1123 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1124 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1125 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1126 printf ("vret_addr =");
1127 mono_print_ins (cfg->vret_addr);
1130 cfg->ret->opcode = OP_REGOFFSET;
1131 cfg->ret->inst_basereg = X86_EBP;
1132 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1135 case ArgValuetypeInReg:
1138 cfg->ret->opcode = OP_REGVAR;
1139 cfg->ret->inst_c0 = cinfo->ret.reg;
1140 cfg->ret->dreg = cinfo->ret.reg;
1143 case ArgOnFloatFpStack:
1144 case ArgOnDoubleFpStack:
1147 g_assert_not_reached ();
1150 if (sig->call_convention == MONO_CALL_VARARG) {
1151 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1152 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1155 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1156 ArgInfo *ainfo = &cinfo->args [i];
1157 inst = cfg->args [i];
1158 if (inst->opcode != OP_REGVAR) {
1159 inst->opcode = OP_REGOFFSET;
1160 inst->inst_basereg = X86_EBP;
1162 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1165 cfg->stack_offset = offset;
1169 mono_arch_create_vars (MonoCompile *cfg)
1171 MonoMethodSignature *sig;
1174 sig = mono_method_signature (cfg->method);
1176 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1178 if (cinfo->ret.storage == ArgValuetypeInReg)
1179 cfg->ret_var_is_local = TRUE;
1180 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig->ret) || mini_is_gsharedvt_variable_type (cfg, sig->ret))) {
1181 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1184 cfg->arch_eh_jit_info = 1;
1188 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1189 * so we try to do it just once when we have multiple fp arguments in a row.
1190 * We don't use this mechanism generally because for int arguments the generated code
1191 * is slightly bigger and new generation cpus optimize away the dependency chains
1192 * created by push instructions on the esp value.
1193 * fp_arg_setup is the first argument in the execution sequence where the esp register
1196 static G_GNUC_UNUSED int
1197 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1202 for (; start_arg < sig->param_count; ++start_arg) {
1203 t = mini_type_get_underlying_type (NULL, sig->params [start_arg]);
1204 if (!t->byref && t->type == MONO_TYPE_R8) {
1205 fp_space += sizeof (double);
1206 *fp_arg_setup = start_arg;
1215 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1217 MonoMethodSignature *tmp_sig;
1221 * mono_ArgIterator_Setup assumes the signature cookie is
1222 * passed first and all the arguments which were before it are
1223 * passed on the stack after the signature. So compensate by
1224 * passing a different signature.
1226 tmp_sig = mono_metadata_signature_dup (call->signature);
1227 tmp_sig->param_count -= call->signature->sentinelpos;
1228 tmp_sig->sentinelpos = 0;
1229 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1231 if (cfg->compile_aot) {
1232 sig_reg = mono_alloc_ireg (cfg);
1233 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1234 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, sig_reg);
1236 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1242 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1247 LLVMCallInfo *linfo;
1250 n = sig->param_count + sig->hasthis;
1252 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1254 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1257 * LLVM always uses the native ABI while we use our own ABI, the
1258 * only difference is the handling of vtypes:
1259 * - we only pass/receive them in registers in some cases, and only
1260 * in 1 or 2 integer registers.
1262 if (cinfo->ret.storage == ArgValuetypeInReg) {
1264 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1265 cfg->disable_llvm = TRUE;
1269 cfg->exception_message = g_strdup ("vtype ret in call");
1270 cfg->disable_llvm = TRUE;
1272 linfo->ret.storage = LLVMArgVtypeInReg;
1273 for (j = 0; j < 2; ++j)
1274 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1278 if (mini_type_is_vtype (cfg, sig->ret) && cinfo->ret.storage == ArgInIReg) {
1279 /* Vtype returned using a hidden argument */
1280 linfo->ret.storage = LLVMArgVtypeRetAddr;
1281 linfo->vret_arg_index = cinfo->vret_arg_index;
1284 if (mini_type_is_vtype (cfg, sig->ret) && cinfo->ret.storage != ArgInIReg) {
1286 cfg->exception_message = g_strdup ("vtype ret in call");
1287 cfg->disable_llvm = TRUE;
1290 for (i = 0; i < n; ++i) {
1291 ainfo = cinfo->args + i;
1293 if (i >= sig->hasthis)
1294 t = sig->params [i - sig->hasthis];
1296 t = &mono_defaults.int_class->byval_arg;
1298 linfo->args [i].storage = LLVMArgNone;
1300 switch (ainfo->storage) {
1302 linfo->args [i].storage = LLVMArgInIReg;
1304 case ArgInDoubleSSEReg:
1305 case ArgInFloatSSEReg:
1306 linfo->args [i].storage = LLVMArgInFPReg;
1309 if (mini_type_is_vtype (cfg, t)) {
1310 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1311 /* LLVM seems to allocate argument space for empty structures too */
1312 linfo->args [i].storage = LLVMArgNone;
1314 linfo->args [i].storage = LLVMArgVtypeByVal;
1316 linfo->args [i].storage = LLVMArgInIReg;
1318 if (t->type == MONO_TYPE_R4)
1319 linfo->args [i].storage = LLVMArgInFPReg;
1320 else if (t->type == MONO_TYPE_R8)
1321 linfo->args [i].storage = LLVMArgInFPReg;
1325 case ArgValuetypeInReg:
1327 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1328 cfg->disable_llvm = TRUE;
1332 cfg->exception_message = g_strdup ("vtype arg");
1333 cfg->disable_llvm = TRUE;
1335 linfo->args [i].storage = LLVMArgVtypeInReg;
1336 for (j = 0; j < 2; ++j)
1337 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1341 linfo->args [i].storage = LLVMArgGSharedVt;
1344 cfg->exception_message = g_strdup ("ainfo->storage");
1345 cfg->disable_llvm = TRUE;
1355 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1357 if (cfg->compute_gc_maps) {
1360 /* On x86, the offsets are from the sp value before the start of the call sequence */
1362 t = &mono_defaults.int_class->byval_arg;
1363 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1368 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1371 MonoMethodSignature *sig;
1374 int sentinelpos = 0, sp_offset = 0;
1376 sig = call->signature;
1377 n = sig->param_count + sig->hasthis;
1379 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1381 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1382 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1384 if (cinfo->need_stack_align) {
1385 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1386 arg->dreg = X86_ESP;
1387 arg->sreg1 = X86_ESP;
1388 arg->inst_imm = cinfo->stack_align_amount;
1389 MONO_ADD_INS (cfg->cbb, arg);
1390 for (i = 0; i < cinfo->stack_align_amount; i += sizeof (mgreg_t)) {
1393 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1397 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1398 if (cinfo->ret.storage == ArgValuetypeInReg) {
1400 * Tell the JIT to use a more efficient calling convention: call using
1401 * OP_CALL, compute the result location after the call, and save the
1404 call->vret_in_reg = TRUE;
1406 NULLIFY_INS (call->vret_var);
1410 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1412 /* Handle the case where there are no implicit arguments */
1413 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1414 emit_sig_cookie (cfg, call, cinfo);
1416 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1419 /* Arguments are pushed in the reverse order */
1420 for (i = n - 1; i >= 0; i --) {
1421 ArgInfo *ainfo = cinfo->args + i;
1422 MonoType *orig_type, *t;
1425 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1426 /* Push the vret arg before the first argument */
1428 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1429 vtarg->type = STACK_MP;
1430 vtarg->sreg1 = call->vret_var->dreg;
1431 MONO_ADD_INS (cfg->cbb, vtarg);
1433 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1436 if (i >= sig->hasthis)
1437 t = sig->params [i - sig->hasthis];
1439 t = &mono_defaults.int_class->byval_arg;
1441 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1443 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1445 in = call->args [i];
1446 arg->cil_code = in->cil_code;
1447 arg->sreg1 = in->dreg;
1448 arg->type = in->type;
1450 g_assert (in->dreg != -1);
1452 if (ainfo->storage == ArgGSharedVt) {
1453 arg->opcode = OP_OUTARG_VT;
1454 arg->sreg1 = in->dreg;
1455 arg->klass = in->klass;
1457 MONO_ADD_INS (cfg->cbb, arg);
1458 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1462 g_assert (in->klass);
1464 if (t->type == MONO_TYPE_TYPEDBYREF) {
1465 size = sizeof (MonoTypedRef);
1466 align = sizeof (gpointer);
1469 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1473 arg->opcode = OP_OUTARG_VT;
1474 arg->sreg1 = in->dreg;
1475 arg->klass = in->klass;
1476 arg->backend.size = size;
1478 MONO_ADD_INS (cfg->cbb, arg);
1480 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1485 switch (ainfo->storage) {
1487 arg->opcode = OP_X86_PUSH;
1489 if (t->type == MONO_TYPE_R4) {
1490 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1491 arg->opcode = OP_STORER4_MEMBASE_REG;
1492 arg->inst_destbasereg = X86_ESP;
1493 arg->inst_offset = 0;
1495 } else if (t->type == MONO_TYPE_R8) {
1496 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1497 arg->opcode = OP_STORER8_MEMBASE_REG;
1498 arg->inst_destbasereg = X86_ESP;
1499 arg->inst_offset = 0;
1501 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1503 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1509 g_assert_not_reached ();
1512 MONO_ADD_INS (cfg->cbb, arg);
1514 sp_offset += argsize;
1516 if (cfg->compute_gc_maps) {
1518 /* FIXME: The == STACK_OBJ check might be fragile ? */
1519 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1521 if (call->need_unbox_trampoline)
1522 /* The unbox trampoline transforms this into a managed pointer */
1523 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.int_class->this_arg);
1525 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.object_class->byval_arg);
1527 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1531 for (j = 0; j < argsize; j += 4)
1532 emit_gc_param_slot_def (cfg, sp_offset - j, NULL);
1537 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1538 /* Emit the signature cookie just before the implicit arguments */
1539 emit_sig_cookie (cfg, call, cinfo);
1541 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1545 if (sig->ret && (MONO_TYPE_ISSTRUCT (sig->ret) || cinfo->vtype_retaddr)) {
1548 if (cinfo->ret.storage == ArgValuetypeInReg) {
1551 else if (cinfo->ret.storage == ArgInIReg) {
1553 /* The return address is passed in a register */
1554 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1555 vtarg->sreg1 = call->inst.dreg;
1556 vtarg->dreg = mono_alloc_ireg (cfg);
1557 MONO_ADD_INS (cfg->cbb, vtarg);
1559 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1560 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1562 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1563 vtarg->type = STACK_MP;
1564 vtarg->sreg1 = call->vret_var->dreg;
1565 MONO_ADD_INS (cfg->cbb, vtarg);
1567 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1570 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1571 if (cinfo->ret.storage != ArgValuetypeInReg)
1572 cinfo->stack_usage -= 4;
1575 call->stack_usage = cinfo->stack_usage;
1576 call->stack_align_amount = cinfo->stack_align_amount;
1577 cfg->arch.param_area_size = MAX (cfg->arch.param_area_size, sp_offset);
1581 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1584 int size = ins->backend.size;
1586 if (cfg->gsharedvt && mini_is_gsharedvt_klass (cfg, ins->klass)) {
1588 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1589 arg->sreg1 = src->dreg;
1590 MONO_ADD_INS (cfg->cbb, arg);
1591 } else if (size <= 4) {
1592 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1593 arg->sreg1 = src->dreg;
1595 MONO_ADD_INS (cfg->cbb, arg);
1596 } else if (size <= 20) {
1597 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1598 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1600 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1601 arg->inst_basereg = src->dreg;
1602 arg->inst_offset = 0;
1603 arg->inst_imm = size;
1605 MONO_ADD_INS (cfg->cbb, arg);
1610 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1612 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1615 if (ret->type == MONO_TYPE_R4) {
1616 if (COMPILE_LLVM (cfg))
1617 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1620 } else if (ret->type == MONO_TYPE_R8) {
1621 if (COMPILE_LLVM (cfg))
1622 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1625 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1626 if (COMPILE_LLVM (cfg))
1627 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1629 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1630 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1636 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1640 * Allow tracing to work with this interface (with an optional argument)
1643 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1647 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1648 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1650 /* if some args are passed in registers, we need to save them here */
1651 x86_push_reg (code, X86_EBP);
1653 if (cfg->compile_aot) {
1654 x86_push_imm (code, cfg->method);
1655 x86_mov_reg_imm (code, X86_EAX, func);
1656 x86_call_reg (code, X86_EAX);
1658 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1659 x86_push_imm (code, cfg->method);
1660 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1661 x86_call_code (code, 0);
1663 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1677 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1680 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1681 MonoMethod *method = cfg->method;
1682 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1684 switch (ret_type->type) {
1685 case MONO_TYPE_VOID:
1686 /* special case string .ctor icall */
1687 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1688 save_mode = SAVE_EAX;
1689 stack_usage = enable_arguments ? 8 : 4;
1691 save_mode = SAVE_NONE;
1695 save_mode = SAVE_EAX_EDX;
1696 stack_usage = enable_arguments ? 16 : 8;
1700 save_mode = SAVE_FP;
1701 stack_usage = enable_arguments ? 16 : 8;
1703 case MONO_TYPE_GENERICINST:
1704 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1705 save_mode = SAVE_EAX;
1706 stack_usage = enable_arguments ? 8 : 4;
1710 case MONO_TYPE_VALUETYPE:
1711 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1712 save_mode = SAVE_STRUCT;
1713 stack_usage = enable_arguments ? 4 : 0;
1716 save_mode = SAVE_EAX;
1717 stack_usage = enable_arguments ? 8 : 4;
1721 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1723 switch (save_mode) {
1725 x86_push_reg (code, X86_EDX);
1726 x86_push_reg (code, X86_EAX);
1727 if (enable_arguments) {
1728 x86_push_reg (code, X86_EDX);
1729 x86_push_reg (code, X86_EAX);
1734 x86_push_reg (code, X86_EAX);
1735 if (enable_arguments) {
1736 x86_push_reg (code, X86_EAX);
1741 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1742 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1743 if (enable_arguments) {
1744 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1745 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1750 if (enable_arguments) {
1751 x86_push_membase (code, X86_EBP, 8);
1760 if (cfg->compile_aot) {
1761 x86_push_imm (code, method);
1762 x86_mov_reg_imm (code, X86_EAX, func);
1763 x86_call_reg (code, X86_EAX);
1765 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1766 x86_push_imm (code, method);
1767 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1768 x86_call_code (code, 0);
1771 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1773 switch (save_mode) {
1775 x86_pop_reg (code, X86_EAX);
1776 x86_pop_reg (code, X86_EDX);
1779 x86_pop_reg (code, X86_EAX);
1782 x86_fld_membase (code, X86_ESP, 0, TRUE);
1783 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1790 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1795 #define EMIT_COND_BRANCH(ins,cond,sign) \
1796 if (ins->inst_true_bb->native_offset) { \
1797 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1799 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1800 if ((cfg->opt & MONO_OPT_BRANCH) && \
1801 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1802 x86_branch8 (code, cond, 0, sign); \
1804 x86_branch32 (code, cond, 0, sign); \
1808 * Emit an exception if condition is fail and
1809 * if possible do a directly branch to target
1811 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1813 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1814 if (tins == NULL) { \
1815 mono_add_patch_info (cfg, code - cfg->native_code, \
1816 MONO_PATCH_INFO_EXC, exc_name); \
1817 x86_branch32 (code, cond, 0, signed); \
1819 EMIT_COND_BRANCH (tins, cond, signed); \
1823 #define EMIT_FPCOMPARE(code) do { \
1824 x86_fcompp (code); \
1825 x86_fnstsw (code); \
1830 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1832 gboolean needs_paddings = TRUE;
1834 MonoJumpInfo *jinfo = NULL;
1836 if (cfg->abs_patches) {
1837 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1838 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1839 needs_paddings = FALSE;
1842 if (cfg->compile_aot)
1843 needs_paddings = FALSE;
1844 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1845 This is required for code patching to be safe on SMP machines.
1847 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1848 #ifndef __native_client_codegen__
1849 if (needs_paddings && pad_size)
1850 x86_padding (code, 4 - pad_size);
1853 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1854 x86_call_code (code, 0);
1859 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1862 * mono_peephole_pass_1:
1864 * Perform peephole opts which should/can be performed before local regalloc
1867 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1871 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1872 MonoInst *last_ins = ins->prev;
1874 switch (ins->opcode) {
1877 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1879 * X86_LEA is like ADD, but doesn't have the
1880 * sreg1==dreg restriction.
1882 ins->opcode = OP_X86_LEA_MEMBASE;
1883 ins->inst_basereg = ins->sreg1;
1884 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1885 ins->opcode = OP_X86_INC_REG;
1889 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1890 ins->opcode = OP_X86_LEA_MEMBASE;
1891 ins->inst_basereg = ins->sreg1;
1892 ins->inst_imm = -ins->inst_imm;
1893 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1894 ins->opcode = OP_X86_DEC_REG;
1896 case OP_COMPARE_IMM:
1897 case OP_ICOMPARE_IMM:
1898 /* OP_COMPARE_IMM (reg, 0)
1900 * OP_X86_TEST_NULL (reg)
1903 ins->opcode = OP_X86_TEST_NULL;
1905 case OP_X86_COMPARE_MEMBASE_IMM:
1907 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1908 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1910 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1911 * OP_COMPARE_IMM reg, imm
1913 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1915 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1916 ins->inst_basereg == last_ins->inst_destbasereg &&
1917 ins->inst_offset == last_ins->inst_offset) {
1918 ins->opcode = OP_COMPARE_IMM;
1919 ins->sreg1 = last_ins->sreg1;
1921 /* check if we can remove cmp reg,0 with test null */
1923 ins->opcode = OP_X86_TEST_NULL;
1927 case OP_X86_PUSH_MEMBASE:
1928 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1929 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1930 ins->inst_basereg == last_ins->inst_destbasereg &&
1931 ins->inst_offset == last_ins->inst_offset) {
1932 ins->opcode = OP_X86_PUSH;
1933 ins->sreg1 = last_ins->sreg1;
1938 mono_peephole_ins (bb, ins);
1943 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1947 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1948 switch (ins->opcode) {
1950 /* reg = 0 -> XOR (reg, reg) */
1951 /* XOR sets cflags on x86, so we cant do it always */
1952 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1955 ins->opcode = OP_IXOR;
1956 ins->sreg1 = ins->dreg;
1957 ins->sreg2 = ins->dreg;
1960 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1961 * since it takes 3 bytes instead of 7.
1963 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
1964 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1965 ins2->opcode = OP_STORE_MEMBASE_REG;
1966 ins2->sreg1 = ins->dreg;
1968 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1969 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1970 ins2->sreg1 = ins->dreg;
1972 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1973 /* Continue iteration */
1982 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1983 ins->opcode = OP_X86_INC_REG;
1987 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1988 ins->opcode = OP_X86_DEC_REG;
1992 mono_peephole_ins (bb, ins);
1997 * mono_arch_lowering_pass:
1999 * Converts complex opcodes into simpler ones so that each IR instruction
2000 * corresponds to one machine instruction.
2003 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2005 MonoInst *ins, *next;
2008 * FIXME: Need to add more instructions, but the current machine
2009 * description can't model some parts of the composite instructions like
2012 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2013 switch (ins->opcode) {
2016 case OP_IDIV_UN_IMM:
2017 case OP_IREM_UN_IMM:
2019 * Keep the cases where we could generated optimized code, otherwise convert
2020 * to the non-imm variant.
2022 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2024 mono_decompose_op_imm (cfg, bb, ins);
2031 bb->max_vreg = cfg->next_vreg;
2035 branch_cc_table [] = {
2036 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2037 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2038 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2041 /* Maps CMP_... constants to X86_CC_... constants */
2044 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2045 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2049 cc_signed_table [] = {
2050 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2051 FALSE, FALSE, FALSE, FALSE
2054 static unsigned char*
2055 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2057 #define XMM_TEMP_REG 0
2058 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2059 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2060 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2061 /* optimize by assigning a local var for this use so we avoid
2062 * the stack manipulations */
2063 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2064 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2065 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2066 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2067 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2069 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2071 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2074 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2075 x86_fnstcw_membase(code, X86_ESP, 0);
2076 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2077 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2078 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2079 x86_fldcw_membase (code, X86_ESP, 2);
2081 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2082 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2083 x86_pop_reg (code, dreg);
2084 /* FIXME: need the high register
2085 * x86_pop_reg (code, dreg_high);
2088 x86_push_reg (code, X86_EAX); // SP = SP - 4
2089 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2090 x86_pop_reg (code, dreg);
2092 x86_fldcw_membase (code, X86_ESP, 0);
2093 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2096 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2098 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2102 static unsigned char*
2103 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2105 int sreg = tree->sreg1;
2106 int need_touch = FALSE;
2108 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2117 * If requested stack size is larger than one page,
2118 * perform stack-touch operation
2121 * Generate stack probe code.
2122 * Under Windows, it is necessary to allocate one page at a time,
2123 * "touching" stack after each successful sub-allocation. This is
2124 * because of the way stack growth is implemented - there is a
2125 * guard page before the lowest stack page that is currently commited.
2126 * Stack normally grows sequentially so OS traps access to the
2127 * guard page and commits more pages when needed.
2129 x86_test_reg_imm (code, sreg, ~0xFFF);
2130 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2132 br[2] = code; /* loop */
2133 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2134 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2137 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2138 * that follows only initializes the last part of the area.
2140 /* Same as the init code below with size==0x1000 */
2141 if (tree->flags & MONO_INST_INIT) {
2142 x86_push_reg (code, X86_EAX);
2143 x86_push_reg (code, X86_ECX);
2144 x86_push_reg (code, X86_EDI);
2145 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2146 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2147 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2149 x86_prefix (code, X86_REP_PREFIX);
2151 x86_pop_reg (code, X86_EDI);
2152 x86_pop_reg (code, X86_ECX);
2153 x86_pop_reg (code, X86_EAX);
2156 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2157 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2158 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2159 x86_patch (br[3], br[2]);
2160 x86_test_reg_reg (code, sreg, sreg);
2161 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2162 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2164 br[1] = code; x86_jump8 (code, 0);
2166 x86_patch (br[0], code);
2167 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2168 x86_patch (br[1], code);
2169 x86_patch (br[4], code);
2172 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2174 if (tree->flags & MONO_INST_INIT) {
2176 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2177 x86_push_reg (code, X86_EAX);
2180 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2181 x86_push_reg (code, X86_ECX);
2184 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2185 x86_push_reg (code, X86_EDI);
2189 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2190 if (sreg != X86_ECX)
2191 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2192 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2194 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2196 x86_prefix (code, X86_REP_PREFIX);
2199 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2200 x86_pop_reg (code, X86_EDI);
2201 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2202 x86_pop_reg (code, X86_ECX);
2203 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2204 x86_pop_reg (code, X86_EAX);
2211 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2213 /* Move return value to the target register */
2214 switch (ins->opcode) {
2217 case OP_CALL_MEMBASE:
2218 if (ins->dreg != X86_EAX)
2219 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2229 static int tls_gs_offset;
2233 mono_x86_have_tls_get (void)
2236 static gboolean have_tls_get = FALSE;
2237 static gboolean inited = FALSE;
2241 return have_tls_get;
2243 ins = (guint32*)pthread_getspecific;
2245 * We're looking for these two instructions:
2247 * mov 0x4(%esp),%eax
2248 * mov %gs:[offset](,%eax,4),%eax
2250 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2251 tls_gs_offset = ins [2];
2255 return have_tls_get;
2256 #elif defined(TARGET_ANDROID)
2264 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2266 #if defined(__APPLE__)
2267 x86_prefix (code, X86_GS_PREFIX);
2268 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2269 #elif defined(TARGET_WIN32)
2270 g_assert_not_reached ();
2272 x86_prefix (code, X86_GS_PREFIX);
2273 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2279 * mono_x86_emit_tls_get:
2280 * @code: buffer to store code to
2281 * @dreg: hard register where to place the result
2282 * @tls_offset: offset info
2284 * mono_x86_emit_tls_get emits in @code the native code that puts in
2285 * the dreg register the item in the thread local storage identified
2288 * Returns: a pointer to the end of the stored code
2291 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2293 #if defined(__APPLE__)
2294 x86_prefix (code, X86_GS_PREFIX);
2295 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2296 #elif defined(TARGET_WIN32)
2298 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2299 * Journal and/or a disassembly of the TlsGet () function.
2301 g_assert (tls_offset < 64);
2302 x86_prefix (code, X86_FS_PREFIX);
2303 x86_mov_reg_mem (code, dreg, 0x18, 4);
2304 /* Dunno what this does but TlsGetValue () contains it */
2305 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2306 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2308 if (optimize_for_xen) {
2309 x86_prefix (code, X86_GS_PREFIX);
2310 x86_mov_reg_mem (code, dreg, 0, 4);
2311 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2313 x86_prefix (code, X86_GS_PREFIX);
2314 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2321 * emit_load_volatile_arguments:
2323 * Load volatile arguments from the stack to the original input registers.
2324 * Required before a tail call.
2327 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2329 MonoMethod *method = cfg->method;
2330 MonoMethodSignature *sig;
2335 /* FIXME: Generate intermediate code instead */
2337 sig = mono_method_signature (method);
2339 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2341 /* This is the opposite of the code in emit_prolog */
2343 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2344 ArgInfo *ainfo = cinfo->args + i;
2346 inst = cfg->args [i];
2348 if (sig->hasthis && (i == 0))
2349 arg_type = &mono_defaults.object_class->byval_arg;
2351 arg_type = sig->params [i - sig->hasthis];
2354 * On x86, the arguments are either in their original stack locations, or in
2357 if (inst->opcode == OP_REGVAR) {
2358 g_assert (ainfo->storage == ArgOnStack);
2360 x86_mov_membase_reg (code, X86_EBP, inst->inst_offset, inst->dreg, 4);
2367 #define REAL_PRINT_REG(text,reg) \
2368 mono_assert (reg >= 0); \
2369 x86_push_reg (code, X86_EAX); \
2370 x86_push_reg (code, X86_EDX); \
2371 x86_push_reg (code, X86_ECX); \
2372 x86_push_reg (code, reg); \
2373 x86_push_imm (code, reg); \
2374 x86_push_imm (code, text " %d %p\n"); \
2375 x86_mov_reg_imm (code, X86_EAX, printf); \
2376 x86_call_reg (code, X86_EAX); \
2377 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2378 x86_pop_reg (code, X86_ECX); \
2379 x86_pop_reg (code, X86_EDX); \
2380 x86_pop_reg (code, X86_EAX);
2382 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2383 #ifdef __native__client_codegen__
2384 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2387 /* benchmark and set based on cpu */
2388 #define LOOP_ALIGNMENT 8
2389 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2393 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2398 guint8 *code = cfg->native_code + cfg->code_len;
2401 if (cfg->opt & MONO_OPT_LOOP) {
2402 int pad, align = LOOP_ALIGNMENT;
2403 /* set alignment depending on cpu */
2404 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2406 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2407 x86_padding (code, pad);
2408 cfg->code_len += pad;
2409 bb->native_offset = cfg->code_len;
2412 #ifdef __native_client_codegen__
2414 /* For Native Client, all indirect call/jump targets must be */
2415 /* 32-byte aligned. Exception handler blocks are jumped to */
2416 /* indirectly as well. */
2417 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2418 (bb->flags & BB_EXCEPTION_HANDLER);
2420 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2421 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2422 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2423 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2424 cfg->code_len += pad;
2425 bb->native_offset = cfg->code_len;
2428 #endif /* __native_client_codegen__ */
2429 if (cfg->verbose_level > 2)
2430 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2432 cpos = bb->max_offset;
2434 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2435 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2436 g_assert (!cfg->compile_aot);
2439 cov->data [bb->dfn].cil_code = bb->cil_code;
2440 /* this is not thread save, but good enough */
2441 x86_inc_mem (code, &cov->data [bb->dfn].count);
2444 offset = code - cfg->native_code;
2446 mono_debug_open_block (cfg, bb, offset);
2448 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2449 x86_breakpoint (code);
2451 MONO_BB_FOR_EACH_INS (bb, ins) {
2452 offset = code - cfg->native_code;
2454 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2456 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2458 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2459 cfg->code_size *= 2;
2460 cfg->native_code = mono_realloc_native_code(cfg);
2461 code = cfg->native_code + offset;
2462 cfg->stat_code_reallocs++;
2465 if (cfg->debug_info)
2466 mono_debug_record_line_number (cfg, ins, offset);
2468 switch (ins->opcode) {
2470 x86_mul_reg (code, ins->sreg2, TRUE);
2473 x86_mul_reg (code, ins->sreg2, FALSE);
2475 case OP_X86_SETEQ_MEMBASE:
2476 case OP_X86_SETNE_MEMBASE:
2477 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2478 ins->inst_basereg, ins->inst_offset, TRUE);
2480 case OP_STOREI1_MEMBASE_IMM:
2481 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2483 case OP_STOREI2_MEMBASE_IMM:
2484 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2486 case OP_STORE_MEMBASE_IMM:
2487 case OP_STOREI4_MEMBASE_IMM:
2488 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2490 case OP_STOREI1_MEMBASE_REG:
2491 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2493 case OP_STOREI2_MEMBASE_REG:
2494 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2496 case OP_STORE_MEMBASE_REG:
2497 case OP_STOREI4_MEMBASE_REG:
2498 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2500 case OP_STORE_MEM_IMM:
2501 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2504 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2508 /* These are created by the cprop pass so they use inst_imm as the source */
2509 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2512 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2515 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2517 case OP_LOAD_MEMBASE:
2518 case OP_LOADI4_MEMBASE:
2519 case OP_LOADU4_MEMBASE:
2520 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2522 case OP_LOADU1_MEMBASE:
2523 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2525 case OP_LOADI1_MEMBASE:
2526 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2528 case OP_LOADU2_MEMBASE:
2529 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2531 case OP_LOADI2_MEMBASE:
2532 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2534 case OP_ICONV_TO_I1:
2536 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2538 case OP_ICONV_TO_I2:
2540 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2542 case OP_ICONV_TO_U1:
2543 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2545 case OP_ICONV_TO_U2:
2546 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2550 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2552 case OP_COMPARE_IMM:
2553 case OP_ICOMPARE_IMM:
2554 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2556 case OP_X86_COMPARE_MEMBASE_REG:
2557 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2559 case OP_X86_COMPARE_MEMBASE_IMM:
2560 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2562 case OP_X86_COMPARE_MEMBASE8_IMM:
2563 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2565 case OP_X86_COMPARE_REG_MEMBASE:
2566 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2568 case OP_X86_COMPARE_MEM_IMM:
2569 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2571 case OP_X86_TEST_NULL:
2572 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2574 case OP_X86_ADD_MEMBASE_IMM:
2575 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2577 case OP_X86_ADD_REG_MEMBASE:
2578 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2580 case OP_X86_SUB_MEMBASE_IMM:
2581 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2583 case OP_X86_SUB_REG_MEMBASE:
2584 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2586 case OP_X86_AND_MEMBASE_IMM:
2587 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2589 case OP_X86_OR_MEMBASE_IMM:
2590 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2592 case OP_X86_XOR_MEMBASE_IMM:
2593 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2595 case OP_X86_ADD_MEMBASE_REG:
2596 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2598 case OP_X86_SUB_MEMBASE_REG:
2599 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2601 case OP_X86_AND_MEMBASE_REG:
2602 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2604 case OP_X86_OR_MEMBASE_REG:
2605 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2607 case OP_X86_XOR_MEMBASE_REG:
2608 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2610 case OP_X86_INC_MEMBASE:
2611 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2613 case OP_X86_INC_REG:
2614 x86_inc_reg (code, ins->dreg);
2616 case OP_X86_DEC_MEMBASE:
2617 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2619 case OP_X86_DEC_REG:
2620 x86_dec_reg (code, ins->dreg);
2622 case OP_X86_MUL_REG_MEMBASE:
2623 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2625 case OP_X86_AND_REG_MEMBASE:
2626 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2628 case OP_X86_OR_REG_MEMBASE:
2629 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2631 case OP_X86_XOR_REG_MEMBASE:
2632 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2635 x86_breakpoint (code);
2637 case OP_RELAXED_NOP:
2638 x86_prefix (code, X86_REP_PREFIX);
2646 case OP_DUMMY_STORE:
2647 case OP_NOT_REACHED:
2650 case OP_SEQ_POINT: {
2653 if (cfg->compile_aot)
2657 * Read from the single stepping trigger page. This will cause a
2658 * SIGSEGV when single stepping is enabled.
2659 * We do this _before_ the breakpoint, so single stepping after
2660 * a breakpoint is hit will step to the next IL offset.
2662 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2663 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2665 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2668 * A placeholder for a possible breakpoint inserted by
2669 * mono_arch_set_breakpoint ().
2671 for (i = 0; i < 6; ++i)
2674 * Add an additional nop so skipping the bp doesn't cause the ip to point
2675 * to another IL offset.
2683 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2687 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2692 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2696 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2701 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2705 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2710 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2714 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2717 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2721 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2725 #if defined( __native_client_codegen__ )
2726 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2727 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2730 * The code is the same for div/rem, the allocator will allocate dreg
2731 * to RAX/RDX as appropriate.
2733 if (ins->sreg2 == X86_EDX) {
2734 /* cdq clobbers this */
2735 x86_push_reg (code, ins->sreg2);
2737 x86_div_membase (code, X86_ESP, 0, TRUE);
2738 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2741 x86_div_reg (code, ins->sreg2, TRUE);
2746 #if defined( __native_client_codegen__ )
2747 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2748 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2750 if (ins->sreg2 == X86_EDX) {
2751 x86_push_reg (code, ins->sreg2);
2752 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2753 x86_div_membase (code, X86_ESP, 0, FALSE);
2754 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2756 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2757 x86_div_reg (code, ins->sreg2, FALSE);
2761 #if defined( __native_client_codegen__ )
2762 if (ins->inst_imm == 0) {
2763 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2764 x86_jump32 (code, 0);
2768 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2770 x86_div_reg (code, ins->sreg2, TRUE);
2773 int power = mono_is_power_of_two (ins->inst_imm);
2775 g_assert (ins->sreg1 == X86_EAX);
2776 g_assert (ins->dreg == X86_EAX);
2777 g_assert (power >= 0);
2780 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2782 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2784 * If the divident is >= 0, this does not nothing. If it is positive, it
2785 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2787 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2788 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2789 } else if (power == 0) {
2790 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2792 /* Based on gcc code */
2794 /* Add compensation for negative dividents */
2796 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2797 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2798 /* Compute remainder */
2799 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2800 /* Remove compensation */
2801 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2806 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2810 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2813 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2817 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2820 g_assert (ins->sreg2 == X86_ECX);
2821 x86_shift_reg (code, X86_SHL, ins->dreg);
2824 g_assert (ins->sreg2 == X86_ECX);
2825 x86_shift_reg (code, X86_SAR, ins->dreg);
2829 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2832 case OP_ISHR_UN_IMM:
2833 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2836 g_assert (ins->sreg2 == X86_ECX);
2837 x86_shift_reg (code, X86_SHR, ins->dreg);
2841 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2844 guint8 *jump_to_end;
2846 /* handle shifts below 32 bits */
2847 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2848 x86_shift_reg (code, X86_SHL, ins->sreg1);
2850 x86_test_reg_imm (code, X86_ECX, 32);
2851 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2853 /* handle shift over 32 bit */
2854 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2855 x86_clear_reg (code, ins->sreg1);
2857 x86_patch (jump_to_end, code);
2861 guint8 *jump_to_end;
2863 /* handle shifts below 32 bits */
2864 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2865 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2867 x86_test_reg_imm (code, X86_ECX, 32);
2868 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2870 /* handle shifts over 31 bits */
2871 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2872 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2874 x86_patch (jump_to_end, code);
2878 guint8 *jump_to_end;
2880 /* handle shifts below 32 bits */
2881 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2882 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2884 x86_test_reg_imm (code, X86_ECX, 32);
2885 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2887 /* handle shifts over 31 bits */
2888 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2889 x86_clear_reg (code, ins->backend.reg3);
2891 x86_patch (jump_to_end, code);
2895 if (ins->inst_imm >= 32) {
2896 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2897 x86_clear_reg (code, ins->sreg1);
2898 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2900 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2901 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2905 if (ins->inst_imm >= 32) {
2906 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2907 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2908 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2910 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2911 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2914 case OP_LSHR_UN_IMM:
2915 if (ins->inst_imm >= 32) {
2916 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2917 x86_clear_reg (code, ins->backend.reg3);
2918 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2920 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2921 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2925 x86_not_reg (code, ins->sreg1);
2928 x86_neg_reg (code, ins->sreg1);
2932 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2936 switch (ins->inst_imm) {
2940 if (ins->dreg != ins->sreg1)
2941 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2942 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2945 /* LEA r1, [r2 + r2*2] */
2946 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2949 /* LEA r1, [r2 + r2*4] */
2950 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2953 /* LEA r1, [r2 + r2*2] */
2955 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2956 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2959 /* LEA r1, [r2 + r2*8] */
2960 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2963 /* LEA r1, [r2 + r2*4] */
2965 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2966 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2969 /* LEA r1, [r2 + r2*2] */
2971 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2972 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2975 /* LEA r1, [r2 + r2*4] */
2976 /* LEA r1, [r1 + r1*4] */
2977 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2978 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2981 /* LEA r1, [r2 + r2*4] */
2983 /* LEA r1, [r1 + r1*4] */
2984 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2985 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2986 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2989 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2994 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2995 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2997 case OP_IMUL_OVF_UN: {
2998 /* the mul operation and the exception check should most likely be split */
2999 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3000 /*g_assert (ins->sreg2 == X86_EAX);
3001 g_assert (ins->dreg == X86_EAX);*/
3002 if (ins->sreg2 == X86_EAX) {
3003 non_eax_reg = ins->sreg1;
3004 } else if (ins->sreg1 == X86_EAX) {
3005 non_eax_reg = ins->sreg2;
3007 /* no need to save since we're going to store to it anyway */
3008 if (ins->dreg != X86_EAX) {
3010 x86_push_reg (code, X86_EAX);
3012 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3013 non_eax_reg = ins->sreg2;
3015 if (ins->dreg == X86_EDX) {
3018 x86_push_reg (code, X86_EAX);
3020 } else if (ins->dreg != X86_EAX) {
3022 x86_push_reg (code, X86_EDX);
3024 x86_mul_reg (code, non_eax_reg, FALSE);
3025 /* save before the check since pop and mov don't change the flags */
3026 if (ins->dreg != X86_EAX)
3027 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3029 x86_pop_reg (code, X86_EDX);
3031 x86_pop_reg (code, X86_EAX);
3032 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3036 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3039 g_assert_not_reached ();
3040 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3041 x86_mov_reg_imm (code, ins->dreg, 0);
3044 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3045 x86_mov_reg_imm (code, ins->dreg, 0);
3047 case OP_LOAD_GOTADDR:
3048 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3049 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3052 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3053 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3055 case OP_X86_PUSH_GOT_ENTRY:
3056 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3057 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3060 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3064 * Note: this 'frame destruction' logic is useful for tail calls, too.
3065 * Keep in sync with the code in emit_epilog.
3069 /* FIXME: no tracing support... */
3070 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3071 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3072 /* reset offset to make max_len work */
3073 offset = code - cfg->native_code;
3075 g_assert (!cfg->method->save_lmf);
3077 code = emit_load_volatile_arguments (cfg, code);
3079 if (cfg->used_int_regs & (1 << X86_EBX))
3081 if (cfg->used_int_regs & (1 << X86_EDI))
3083 if (cfg->used_int_regs & (1 << X86_ESI))
3086 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
3088 if (cfg->used_int_regs & (1 << X86_ESI))
3089 x86_pop_reg (code, X86_ESI);
3090 if (cfg->used_int_regs & (1 << X86_EDI))
3091 x86_pop_reg (code, X86_EDI);
3092 if (cfg->used_int_regs & (1 << X86_EBX))
3093 x86_pop_reg (code, X86_EBX);
3095 /* restore ESP/EBP */
3097 offset = code - cfg->native_code;
3098 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3099 x86_jump32 (code, 0);
3101 cfg->disable_aot = TRUE;
3105 MonoCallInst *call = (MonoCallInst*)ins;
3108 ins->flags |= MONO_INST_GC_CALLSITE;
3109 ins->backend.pc_offset = code - cfg->native_code;
3111 /* FIXME: no tracing support... */
3112 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3113 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3114 /* reset offset to make max_len work */
3115 offset = code - cfg->native_code;
3117 g_assert (!cfg->method->save_lmf);
3119 //code = emit_load_volatile_arguments (cfg, code);
3121 /* restore callee saved registers */
3122 for (i = 0; i < X86_NREG; ++i)
3123 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3125 if (cfg->used_int_regs & (1 << X86_ESI)) {
3126 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3129 if (cfg->used_int_regs & (1 << X86_EDI)) {
3130 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3133 if (cfg->used_int_regs & (1 << X86_EBX)) {
3134 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3138 /* Copy arguments on the stack to our argument area */
3139 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3140 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3141 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3144 /* restore ESP/EBP */
3146 offset = code - cfg->native_code;
3147 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3148 x86_jump32 (code, 0);
3150 ins->flags |= MONO_INST_GC_CALLSITE;
3151 cfg->disable_aot = TRUE;
3155 /* ensure ins->sreg1 is not NULL
3156 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3157 * cmp DWORD PTR [eax], 0
3159 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3162 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3163 x86_push_reg (code, hreg);
3164 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3165 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3166 x86_pop_reg (code, hreg);
3175 call = (MonoCallInst*)ins;
3176 if (ins->flags & MONO_INST_HAS_METHOD)
3177 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3179 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3180 ins->flags |= MONO_INST_GC_CALLSITE;
3181 ins->backend.pc_offset = code - cfg->native_code;
3182 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3183 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
3184 * bytes to pop, we want to use pops. GCC does this (note it won't happen
3185 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
3186 * smart enough to do that optimization yet
3188 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
3189 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
3190 * (most likely from locality benefits). People with other processors should
3191 * check on theirs to see what happens.
3193 if (call->stack_usage == 4) {
3194 /* we want to use registers that won't get used soon, so use
3195 * ecx, as eax will get allocated first. edx is used by long calls,
3196 * so we can't use that.
3199 x86_pop_reg (code, X86_ECX);
3201 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3204 code = emit_move_return_value (cfg, ins, code);
3210 case OP_VOIDCALL_REG:
3212 call = (MonoCallInst*)ins;
3213 x86_call_reg (code, ins->sreg1);
3214 ins->flags |= MONO_INST_GC_CALLSITE;
3215 ins->backend.pc_offset = code - cfg->native_code;
3216 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3217 if (call->stack_usage == 4)
3218 x86_pop_reg (code, X86_ECX);
3220 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3222 code = emit_move_return_value (cfg, ins, code);
3224 case OP_FCALL_MEMBASE:
3225 case OP_LCALL_MEMBASE:
3226 case OP_VCALL_MEMBASE:
3227 case OP_VCALL2_MEMBASE:
3228 case OP_VOIDCALL_MEMBASE:
3229 case OP_CALL_MEMBASE:
3230 call = (MonoCallInst*)ins;
3232 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3233 ins->flags |= MONO_INST_GC_CALLSITE;
3234 ins->backend.pc_offset = code - cfg->native_code;
3235 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3236 if (call->stack_usage == 4)
3237 x86_pop_reg (code, X86_ECX);
3239 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3241 code = emit_move_return_value (cfg, ins, code);
3244 x86_push_reg (code, ins->sreg1);
3246 case OP_X86_PUSH_IMM:
3247 x86_push_imm (code, ins->inst_imm);
3249 case OP_X86_PUSH_MEMBASE:
3250 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
3252 case OP_X86_PUSH_OBJ:
3253 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
3254 x86_push_reg (code, X86_EDI);
3255 x86_push_reg (code, X86_ESI);
3256 x86_push_reg (code, X86_ECX);
3257 if (ins->inst_offset)
3258 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
3260 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
3261 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
3262 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
3264 x86_prefix (code, X86_REP_PREFIX);
3266 x86_pop_reg (code, X86_ECX);
3267 x86_pop_reg (code, X86_ESI);
3268 x86_pop_reg (code, X86_EDI);
3271 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3273 case OP_X86_LEA_MEMBASE:
3274 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3277 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3280 /* keep alignment */
3281 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3282 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3283 code = mono_emit_stack_alloc (code, ins);
3284 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3286 case OP_LOCALLOC_IMM: {
3287 guint32 size = ins->inst_imm;
3288 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3290 if (ins->flags & MONO_INST_INIT) {
3291 /* FIXME: Optimize this */
3292 x86_mov_reg_imm (code, ins->dreg, size);
3293 ins->sreg1 = ins->dreg;
3295 code = mono_emit_stack_alloc (code, ins);
3296 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3298 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3299 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3304 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3305 x86_push_reg (code, ins->sreg1);
3306 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3307 (gpointer)"mono_arch_throw_exception");
3308 ins->flags |= MONO_INST_GC_CALLSITE;
3309 ins->backend.pc_offset = code - cfg->native_code;
3313 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3314 x86_push_reg (code, ins->sreg1);
3315 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3316 (gpointer)"mono_arch_rethrow_exception");
3317 ins->flags |= MONO_INST_GC_CALLSITE;
3318 ins->backend.pc_offset = code - cfg->native_code;
3321 case OP_CALL_HANDLER:
3322 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3323 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3324 x86_call_imm (code, 0);
3325 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3326 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3328 case OP_START_HANDLER: {
3329 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3330 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3333 case OP_ENDFINALLY: {
3334 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3335 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3339 case OP_ENDFILTER: {
3340 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3341 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3342 /* The local allocator will put the result into EAX */
3348 ins->inst_c0 = code - cfg->native_code;
3351 if (ins->inst_target_bb->native_offset) {
3352 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3354 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3355 if ((cfg->opt & MONO_OPT_BRANCH) &&
3356 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3357 x86_jump8 (code, 0);
3359 x86_jump32 (code, 0);
3363 x86_jump_reg (code, ins->sreg1);
3376 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3377 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3379 case OP_COND_EXC_EQ:
3380 case OP_COND_EXC_NE_UN:
3381 case OP_COND_EXC_LT:
3382 case OP_COND_EXC_LT_UN:
3383 case OP_COND_EXC_GT:
3384 case OP_COND_EXC_GT_UN:
3385 case OP_COND_EXC_GE:
3386 case OP_COND_EXC_GE_UN:
3387 case OP_COND_EXC_LE:
3388 case OP_COND_EXC_LE_UN:
3389 case OP_COND_EXC_IEQ:
3390 case OP_COND_EXC_INE_UN:
3391 case OP_COND_EXC_ILT:
3392 case OP_COND_EXC_ILT_UN:
3393 case OP_COND_EXC_IGT:
3394 case OP_COND_EXC_IGT_UN:
3395 case OP_COND_EXC_IGE:
3396 case OP_COND_EXC_IGE_UN:
3397 case OP_COND_EXC_ILE:
3398 case OP_COND_EXC_ILE_UN:
3399 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3401 case OP_COND_EXC_OV:
3402 case OP_COND_EXC_NO:
3404 case OP_COND_EXC_NC:
3405 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3407 case OP_COND_EXC_IOV:
3408 case OP_COND_EXC_INO:
3409 case OP_COND_EXC_IC:
3410 case OP_COND_EXC_INC:
3411 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3423 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3431 case OP_CMOV_INE_UN:
3432 case OP_CMOV_IGE_UN:
3433 case OP_CMOV_IGT_UN:
3434 case OP_CMOV_ILE_UN:
3435 case OP_CMOV_ILT_UN:
3436 g_assert (ins->dreg == ins->sreg1);
3437 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3440 /* floating point opcodes */
3442 double d = *(double *)ins->inst_p0;
3444 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3446 } else if (d == 1.0) {
3449 if (cfg->compile_aot) {
3450 guint32 *val = (guint32*)&d;
3451 x86_push_imm (code, val [1]);
3452 x86_push_imm (code, val [0]);
3453 x86_fld_membase (code, X86_ESP, 0, TRUE);
3454 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3457 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3458 x86_fld (code, NULL, TRUE);
3464 float f = *(float *)ins->inst_p0;
3466 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3468 } else if (f == 1.0) {
3471 if (cfg->compile_aot) {
3472 guint32 val = *(guint32*)&f;
3473 x86_push_imm (code, val);
3474 x86_fld_membase (code, X86_ESP, 0, FALSE);
3475 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3478 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3479 x86_fld (code, NULL, FALSE);
3484 case OP_STORER8_MEMBASE_REG:
3485 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3487 case OP_LOADR8_MEMBASE:
3488 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3490 case OP_STORER4_MEMBASE_REG:
3491 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3493 case OP_LOADR4_MEMBASE:
3494 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3496 case OP_ICONV_TO_R4:
3497 x86_push_reg (code, ins->sreg1);
3498 x86_fild_membase (code, X86_ESP, 0, FALSE);
3499 /* Change precision */
3500 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3501 x86_fld_membase (code, X86_ESP, 0, FALSE);
3502 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3504 case OP_ICONV_TO_R8:
3505 x86_push_reg (code, ins->sreg1);
3506 x86_fild_membase (code, X86_ESP, 0, FALSE);
3507 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3509 case OP_ICONV_TO_R_UN:
3510 x86_push_imm (code, 0);
3511 x86_push_reg (code, ins->sreg1);
3512 x86_fild_membase (code, X86_ESP, 0, TRUE);
3513 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3515 case OP_X86_FP_LOAD_I8:
3516 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3518 case OP_X86_FP_LOAD_I4:
3519 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3521 case OP_FCONV_TO_R4:
3522 /* Change precision */
3523 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3524 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3525 x86_fld_membase (code, X86_ESP, 0, FALSE);
3526 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3528 case OP_FCONV_TO_I1:
3529 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3531 case OP_FCONV_TO_U1:
3532 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3534 case OP_FCONV_TO_I2:
3535 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3537 case OP_FCONV_TO_U2:
3538 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3540 case OP_FCONV_TO_I4:
3542 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3544 case OP_FCONV_TO_I8:
3545 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3546 x86_fnstcw_membase(code, X86_ESP, 0);
3547 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3548 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3549 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3550 x86_fldcw_membase (code, X86_ESP, 2);
3551 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3552 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3553 x86_pop_reg (code, ins->dreg);
3554 x86_pop_reg (code, ins->backend.reg3);
3555 x86_fldcw_membase (code, X86_ESP, 0);
3556 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3558 case OP_LCONV_TO_R8_2:
3559 x86_push_reg (code, ins->sreg2);
3560 x86_push_reg (code, ins->sreg1);
3561 x86_fild_membase (code, X86_ESP, 0, TRUE);
3562 /* Change precision */
3563 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3564 x86_fld_membase (code, X86_ESP, 0, TRUE);
3565 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3567 case OP_LCONV_TO_R4_2:
3568 x86_push_reg (code, ins->sreg2);
3569 x86_push_reg (code, ins->sreg1);
3570 x86_fild_membase (code, X86_ESP, 0, TRUE);
3571 /* Change precision */
3572 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3573 x86_fld_membase (code, X86_ESP, 0, FALSE);
3574 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3576 case OP_LCONV_TO_R_UN_2: {
3577 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3580 /* load 64bit integer to FP stack */
3581 x86_push_reg (code, ins->sreg2);
3582 x86_push_reg (code, ins->sreg1);
3583 x86_fild_membase (code, X86_ESP, 0, TRUE);
3585 /* test if lreg is negative */
3586 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3587 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3589 /* add correction constant mn */
3590 if (cfg->compile_aot) {
3591 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3592 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3593 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3594 x86_fld80_membase (code, X86_ESP, 2);
3595 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3597 x86_fld80_mem (code, mn);
3599 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3601 x86_patch (br, code);
3603 /* Change precision */
3604 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3605 x86_fld_membase (code, X86_ESP, 0, TRUE);
3607 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3611 case OP_LCONV_TO_OVF_I:
3612 case OP_LCONV_TO_OVF_I4_2: {
3613 guint8 *br [3], *label [1];
3617 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3619 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3621 /* If the low word top bit is set, see if we are negative */
3622 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3623 /* We are not negative (no top bit set, check for our top word to be zero */
3624 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3625 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3628 /* throw exception */
3629 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3631 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3632 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3633 x86_jump8 (code, 0);
3635 x86_jump32 (code, 0);
3637 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3638 x86_jump32 (code, 0);
3642 x86_patch (br [0], code);
3643 /* our top bit is set, check that top word is 0xfffffff */
3644 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3646 x86_patch (br [1], code);
3647 /* nope, emit exception */
3648 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3649 x86_patch (br [2], label [0]);
3651 if (ins->dreg != ins->sreg1)
3652 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3656 /* Not needed on the fp stack */
3659 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3662 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3665 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3668 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3676 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3681 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3688 * it really doesn't make sense to inline all this code,
3689 * it's here just to show that things may not be as simple
3692 guchar *check_pos, *end_tan, *pop_jump;
3693 x86_push_reg (code, X86_EAX);
3696 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3698 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3699 x86_fstp (code, 0); /* pop the 1.0 */
3701 x86_jump8 (code, 0);
3703 x86_fp_op (code, X86_FADD, 0);
3707 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3709 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3712 x86_patch (pop_jump, code);
3713 x86_fstp (code, 0); /* pop the 1.0 */
3714 x86_patch (check_pos, code);
3715 x86_patch (end_tan, code);
3717 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3718 x86_pop_reg (code, X86_EAX);
3725 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3734 g_assert (cfg->opt & MONO_OPT_CMOV);
3735 g_assert (ins->dreg == ins->sreg1);
3736 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3737 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3740 g_assert (cfg->opt & MONO_OPT_CMOV);
3741 g_assert (ins->dreg == ins->sreg1);
3742 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3743 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3746 g_assert (cfg->opt & MONO_OPT_CMOV);
3747 g_assert (ins->dreg == ins->sreg1);
3748 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3749 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3752 g_assert (cfg->opt & MONO_OPT_CMOV);
3753 g_assert (ins->dreg == ins->sreg1);
3754 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3755 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3761 x86_fxch (code, ins->inst_imm);
3766 x86_push_reg (code, X86_EAX);
3767 /* we need to exchange ST(0) with ST(1) */
3770 /* this requires a loop, because fprem somtimes
3771 * returns a partial remainder */
3773 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3774 /* x86_fprem1 (code); */
3777 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3779 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3785 x86_pop_reg (code, X86_EAX);
3789 if (cfg->opt & MONO_OPT_FCMOV) {
3790 x86_fcomip (code, 1);
3794 /* this overwrites EAX */
3795 EMIT_FPCOMPARE(code);
3796 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3799 if (cfg->opt & MONO_OPT_FCMOV) {
3800 /* zeroing the register at the start results in
3801 * shorter and faster code (we can also remove the widening op)
3803 guchar *unordered_check;
3804 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3805 x86_fcomip (code, 1);
3807 unordered_check = code;
3808 x86_branch8 (code, X86_CC_P, 0, FALSE);
3809 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3810 x86_patch (unordered_check, code);
3813 if (ins->dreg != X86_EAX)
3814 x86_push_reg (code, X86_EAX);
3816 EMIT_FPCOMPARE(code);
3817 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3818 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3819 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3820 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3822 if (ins->dreg != X86_EAX)
3823 x86_pop_reg (code, X86_EAX);
3827 if (cfg->opt & MONO_OPT_FCMOV) {
3828 /* zeroing the register at the start results in
3829 * shorter and faster code (we can also remove the widening op)
3831 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3832 x86_fcomip (code, 1);
3834 if (ins->opcode == OP_FCLT_UN) {
3835 guchar *unordered_check = code;
3836 guchar *jump_to_end;
3837 x86_branch8 (code, X86_CC_P, 0, FALSE);
3838 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3840 x86_jump8 (code, 0);
3841 x86_patch (unordered_check, code);
3842 x86_inc_reg (code, ins->dreg);
3843 x86_patch (jump_to_end, code);
3845 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3849 if (ins->dreg != X86_EAX)
3850 x86_push_reg (code, X86_EAX);
3852 EMIT_FPCOMPARE(code);
3853 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3854 if (ins->opcode == OP_FCLT_UN) {
3855 guchar *is_not_zero_check, *end_jump;
3856 is_not_zero_check = code;
3857 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3859 x86_jump8 (code, 0);
3860 x86_patch (is_not_zero_check, code);
3861 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3863 x86_patch (end_jump, code);
3865 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3866 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3868 if (ins->dreg != X86_EAX)
3869 x86_pop_reg (code, X86_EAX);
3873 if (cfg->opt & MONO_OPT_FCMOV) {
3874 /* zeroing the register at the start results in
3875 * shorter and faster code (we can also remove the widening op)
3877 guchar *unordered_check;
3878 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3879 x86_fcomip (code, 1);
3881 if (ins->opcode == OP_FCGT) {
3882 unordered_check = code;
3883 x86_branch8 (code, X86_CC_P, 0, FALSE);
3884 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3885 x86_patch (unordered_check, code);
3887 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3891 if (ins->dreg != X86_EAX)
3892 x86_push_reg (code, X86_EAX);
3894 EMIT_FPCOMPARE(code);
3895 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3896 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3897 if (ins->opcode == OP_FCGT_UN) {
3898 guchar *is_not_zero_check, *end_jump;
3899 is_not_zero_check = code;
3900 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3902 x86_jump8 (code, 0);
3903 x86_patch (is_not_zero_check, code);
3904 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3906 x86_patch (end_jump, code);
3908 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3909 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3911 if (ins->dreg != X86_EAX)
3912 x86_pop_reg (code, X86_EAX);
3915 if (cfg->opt & MONO_OPT_FCMOV) {
3916 guchar *jump = code;
3917 x86_branch8 (code, X86_CC_P, 0, TRUE);
3918 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3919 x86_patch (jump, code);
3922 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3923 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3926 /* Branch if C013 != 100 */
3927 if (cfg->opt & MONO_OPT_FCMOV) {
3928 /* branch if !ZF or (PF|CF) */
3929 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3930 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3931 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3934 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3935 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3938 if (cfg->opt & MONO_OPT_FCMOV) {
3939 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3942 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3945 if (cfg->opt & MONO_OPT_FCMOV) {
3946 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3947 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3950 if (ins->opcode == OP_FBLT_UN) {
3951 guchar *is_not_zero_check, *end_jump;
3952 is_not_zero_check = code;
3953 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3955 x86_jump8 (code, 0);
3956 x86_patch (is_not_zero_check, code);
3957 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3959 x86_patch (end_jump, code);
3961 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3965 if (cfg->opt & MONO_OPT_FCMOV) {
3966 if (ins->opcode == OP_FBGT) {
3969 /* skip branch if C1=1 */
3971 x86_branch8 (code, X86_CC_P, 0, FALSE);
3972 /* branch if (C0 | C3) = 1 */
3973 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3974 x86_patch (br1, code);
3976 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3980 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3981 if (ins->opcode == OP_FBGT_UN) {
3982 guchar *is_not_zero_check, *end_jump;
3983 is_not_zero_check = code;
3984 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3986 x86_jump8 (code, 0);
3987 x86_patch (is_not_zero_check, code);
3988 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3990 x86_patch (end_jump, code);
3992 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3995 /* Branch if C013 == 100 or 001 */
3996 if (cfg->opt & MONO_OPT_FCMOV) {
3999 /* skip branch if C1=1 */
4001 x86_branch8 (code, X86_CC_P, 0, FALSE);
4002 /* branch if (C0 | C3) = 1 */
4003 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4004 x86_patch (br1, code);
4007 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4008 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4009 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4010 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4013 /* Branch if C013 == 000 */
4014 if (cfg->opt & MONO_OPT_FCMOV) {
4015 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4018 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4021 /* Branch if C013=000 or 100 */
4022 if (cfg->opt & MONO_OPT_FCMOV) {
4025 /* skip branch if C1=1 */
4027 x86_branch8 (code, X86_CC_P, 0, FALSE);
4028 /* branch if C0=0 */
4029 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4030 x86_patch (br1, code);
4033 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4034 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4035 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4038 /* Branch if C013 != 001 */
4039 if (cfg->opt & MONO_OPT_FCMOV) {
4040 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4041 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4044 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4045 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4049 x86_push_reg (code, X86_EAX);
4052 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4053 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4054 x86_pop_reg (code, X86_EAX);
4056 /* Have to clean up the fp stack before throwing the exception */
4058 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4061 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4063 x86_patch (br1, code);
4067 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4070 case OP_TLS_GET_REG: {
4072 // FIXME: tls_gs_offset can change too, do these when calculating the tls offset
4073 if (ins->dreg != ins->sreg1)
4074 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
4075 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4077 x86_alu_reg_imm (code, X86_ADD, ins->dreg, tls_gs_offset);
4078 x86_prefix (code, X86_GS_PREFIX);
4079 x86_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof (gpointer));
4081 g_assert_not_reached ();
4085 case OP_MEMORY_BARRIER: {
4086 /* x86 only needs barrier for StoreLoad and FullBarrier */
4087 switch (ins->backend.memory_barrier_kind) {
4088 case StoreLoadBarrier:
4090 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4091 x86_prefix (code, X86_LOCK_PREFIX);
4092 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4097 case OP_ATOMIC_ADD_I4: {
4098 int dreg = ins->dreg;
4100 if (dreg == ins->inst_basereg) {
4101 x86_push_reg (code, ins->sreg2);
4105 if (dreg != ins->sreg2)
4106 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
4108 x86_prefix (code, X86_LOCK_PREFIX);
4109 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4111 if (dreg != ins->dreg) {
4112 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4113 x86_pop_reg (code, dreg);
4118 case OP_ATOMIC_ADD_NEW_I4: {
4119 int dreg = ins->dreg;
4121 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4122 if (ins->sreg2 == dreg) {
4123 if (dreg == X86_EBX) {
4125 if (ins->inst_basereg == X86_EDI)
4129 if (ins->inst_basereg == X86_EBX)
4132 } else if (ins->inst_basereg == dreg) {
4133 if (dreg == X86_EBX) {
4135 if (ins->sreg2 == X86_EDI)
4139 if (ins->sreg2 == X86_EBX)
4144 if (dreg != ins->dreg) {
4145 x86_push_reg (code, dreg);
4148 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4149 x86_prefix (code, X86_LOCK_PREFIX);
4150 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4151 /* dreg contains the old value, add with sreg2 value */
4152 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4154 if (ins->dreg != dreg) {
4155 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4156 x86_pop_reg (code, dreg);
4161 case OP_ATOMIC_EXCHANGE_I4: {
4163 int sreg2 = ins->sreg2;
4164 int breg = ins->inst_basereg;
4166 /* cmpxchg uses eax as comperand, need to make sure we can use it
4167 * hack to overcome limits in x86 reg allocator
4168 * (req: dreg == eax and sreg2 != eax and breg != eax)
4170 g_assert (ins->dreg == X86_EAX);
4172 /* We need the EAX reg for the cmpxchg */
4173 if (ins->sreg2 == X86_EAX) {
4174 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4175 x86_push_reg (code, sreg2);
4176 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4179 if (breg == X86_EAX) {
4180 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4181 x86_push_reg (code, breg);
4182 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4185 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4187 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4188 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4189 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4190 x86_patch (br [1], br [0]);
4192 if (breg != ins->inst_basereg)
4193 x86_pop_reg (code, breg);
4195 if (ins->sreg2 != sreg2)
4196 x86_pop_reg (code, sreg2);
4200 case OP_ATOMIC_CAS_I4: {
4201 g_assert (ins->dreg == X86_EAX);
4202 g_assert (ins->sreg3 == X86_EAX);
4203 g_assert (ins->sreg1 != X86_EAX);
4204 g_assert (ins->sreg1 != ins->sreg2);
4206 x86_prefix (code, X86_LOCK_PREFIX);
4207 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4210 case OP_CARD_TABLE_WBARRIER: {
4211 int ptr = ins->sreg1;
4212 int value = ins->sreg2;
4214 int nursery_shift, card_table_shift;
4215 gpointer card_table_mask;
4216 size_t nursery_size;
4217 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4218 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4219 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4222 * We need one register we can clobber, we choose EDX and make sreg1
4223 * fixed EAX to work around limitations in the local register allocator.
4224 * sreg2 might get allocated to EDX, but that is not a problem since
4225 * we use it before clobbering EDX.
4227 g_assert (ins->sreg1 == X86_EAX);
4230 * This is the code we produce:
4233 * edx >>= nursery_shift
4234 * cmp edx, (nursery_start >> nursery_shift)
4237 * edx >>= card_table_shift
4238 * card_table[edx] = 1
4242 if (card_table_nursery_check) {
4243 if (value != X86_EDX)
4244 x86_mov_reg_reg (code, X86_EDX, value, 4);
4245 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4246 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4247 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4249 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4250 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4251 if (card_table_mask)
4252 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4253 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4254 if (card_table_nursery_check)
4255 x86_patch (br, code);
4258 #ifdef MONO_ARCH_SIMD_INTRINSICS
4260 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4263 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4266 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4269 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4272 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4275 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4278 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4279 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4282 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4285 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4288 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4291 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4294 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4297 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4300 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4303 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4306 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4309 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4312 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4315 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4318 case OP_PSHUFLEW_HIGH:
4319 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4320 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4322 case OP_PSHUFLEW_LOW:
4323 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4324 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4327 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4328 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4331 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4332 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4335 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4336 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4340 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4343 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4346 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4349 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4352 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4355 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4358 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4359 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4362 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4365 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4368 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4371 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4374 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4377 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4380 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4383 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4386 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4389 case OP_EXTRACT_MASK:
4390 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4394 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4397 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4400 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4404 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4407 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4410 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4413 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4417 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4420 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4423 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4426 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4430 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4433 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4436 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4440 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4443 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4446 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4450 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4453 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4457 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4460 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4463 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4467 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4470 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4473 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4477 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4480 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4483 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4486 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4490 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4493 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4496 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4499 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4502 case OP_PSUM_ABS_DIFF:
4503 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4506 case OP_UNPACK_LOWB:
4507 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4509 case OP_UNPACK_LOWW:
4510 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4512 case OP_UNPACK_LOWD:
4513 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4515 case OP_UNPACK_LOWQ:
4516 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4518 case OP_UNPACK_LOWPS:
4519 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4521 case OP_UNPACK_LOWPD:
4522 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4525 case OP_UNPACK_HIGHB:
4526 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4528 case OP_UNPACK_HIGHW:
4529 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4531 case OP_UNPACK_HIGHD:
4532 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4534 case OP_UNPACK_HIGHQ:
4535 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4537 case OP_UNPACK_HIGHPS:
4538 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4540 case OP_UNPACK_HIGHPD:
4541 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4545 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4548 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4551 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4554 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4557 case OP_PADDB_SAT_UN:
4558 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4560 case OP_PSUBB_SAT_UN:
4561 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4563 case OP_PADDW_SAT_UN:
4564 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4566 case OP_PSUBW_SAT_UN:
4567 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4571 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4574 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4577 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4580 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4584 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4587 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4590 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4592 case OP_PMULW_HIGH_UN:
4593 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4596 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4600 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4603 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4607 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4610 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4614 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4617 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4621 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4624 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4628 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4631 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4635 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4638 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4642 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4645 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4649 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4652 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4656 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4659 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4663 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4665 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4666 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4670 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4672 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4673 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4677 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4679 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4680 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4684 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4686 case OP_EXTRACTX_U2:
4687 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4689 case OP_INSERTX_U1_SLOW:
4690 /*sreg1 is the extracted ireg (scratch)
4691 /sreg2 is the to be inserted ireg (scratch)
4692 /dreg is the xreg to receive the value*/
4694 /*clear the bits from the extracted word*/
4695 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4696 /*shift the value to insert if needed*/
4697 if (ins->inst_c0 & 1)
4698 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4699 /*join them together*/
4700 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4701 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4703 case OP_INSERTX_I4_SLOW:
4704 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4705 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4706 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4709 case OP_INSERTX_R4_SLOW:
4710 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4711 /*TODO if inst_c0 == 0 use movss*/
4712 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4713 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4715 case OP_INSERTX_R8_SLOW:
4716 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4717 if (cfg->verbose_level)
4718 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4720 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4722 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4725 case OP_STOREX_MEMBASE_REG:
4726 case OP_STOREX_MEMBASE:
4727 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4729 case OP_LOADX_MEMBASE:
4730 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4732 case OP_LOADX_ALIGNED_MEMBASE:
4733 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4735 case OP_STOREX_ALIGNED_MEMBASE_REG:
4736 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4738 case OP_STOREX_NTA_MEMBASE_REG:
4739 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4741 case OP_PREFETCH_MEMBASE:
4742 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4746 /*FIXME the peephole pass should have killed this*/
4747 if (ins->dreg != ins->sreg1)
4748 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4751 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4753 case OP_ICONV_TO_R8_RAW:
4754 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4755 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4758 case OP_FCONV_TO_R8_X:
4759 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4760 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4763 case OP_XCONV_R8_TO_I4:
4764 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4765 switch (ins->backend.source_opcode) {
4766 case OP_FCONV_TO_I1:
4767 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4769 case OP_FCONV_TO_U1:
4770 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4772 case OP_FCONV_TO_I2:
4773 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4775 case OP_FCONV_TO_U2:
4776 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4782 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4783 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4784 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4785 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4786 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4787 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4790 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4791 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4792 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4795 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4796 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4799 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4800 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4801 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4804 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4805 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4806 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4810 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4813 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4816 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4819 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4822 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4825 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4828 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4831 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4835 case OP_LIVERANGE_START: {
4836 if (cfg->verbose_level > 1)
4837 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4838 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4841 case OP_LIVERANGE_END: {
4842 if (cfg->verbose_level > 1)
4843 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4844 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4847 case OP_NACL_GC_SAFE_POINT: {
4848 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
4849 if (cfg->compile_aot)
4850 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
4854 x86_test_mem_imm8 (code, (gpointer)&__nacl_thread_suspension_needed, 0xFFFFFFFF);
4855 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4856 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
4857 x86_patch (br[0], code);
4862 case OP_GC_LIVENESS_DEF:
4863 case OP_GC_LIVENESS_USE:
4864 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4865 ins->backend.pc_offset = code - cfg->native_code;
4867 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4868 ins->backend.pc_offset = code - cfg->native_code;
4869 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4872 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4873 g_assert_not_reached ();
4876 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4877 #ifndef __native_client_codegen__
4878 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4879 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4880 g_assert_not_reached ();
4881 #endif /* __native_client_codegen__ */
4887 cfg->code_len = code - cfg->native_code;
4890 #endif /* DISABLE_JIT */
4893 mono_arch_register_lowlevel_calls (void)
4898 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4900 MonoJumpInfo *patch_info;
4901 gboolean compile_aot = !run_cctors;
4903 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4904 unsigned char *ip = patch_info->ip.i + code;
4905 const unsigned char *target;
4907 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4910 switch (patch_info->type) {
4911 case MONO_PATCH_INFO_BB:
4912 case MONO_PATCH_INFO_LABEL:
4915 /* No need to patch these */
4920 switch (patch_info->type) {
4921 case MONO_PATCH_INFO_IP:
4922 *((gconstpointer *)(ip)) = target;
4924 case MONO_PATCH_INFO_CLASS_INIT: {
4926 /* Might already been changed to a nop */
4927 x86_call_code (code, 0);
4928 x86_patch (ip, target);
4931 case MONO_PATCH_INFO_ABS:
4932 case MONO_PATCH_INFO_METHOD:
4933 case MONO_PATCH_INFO_METHOD_JUMP:
4934 case MONO_PATCH_INFO_INTERNAL_METHOD:
4935 case MONO_PATCH_INFO_BB:
4936 case MONO_PATCH_INFO_LABEL:
4937 case MONO_PATCH_INFO_RGCTX_FETCH:
4938 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
4939 case MONO_PATCH_INFO_MONITOR_ENTER:
4940 case MONO_PATCH_INFO_MONITOR_EXIT:
4941 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
4942 #if defined(__native_client_codegen__) && defined(__native_client__)
4943 if (nacl_is_code_address (code)) {
4944 /* For tail calls, code is patched after being installed */
4945 /* but not through the normal "patch callsite" method. */
4946 unsigned char buf[kNaClAlignment];
4947 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
4948 unsigned char *_target = target;
4950 /* All patch targets modified in x86_patch */
4951 /* are IP relative. */
4952 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
4953 memcpy (buf, aligned_code, kNaClAlignment);
4954 /* Patch a temp buffer of bundle size, */
4955 /* then install to actual location. */
4956 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
4957 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
4958 g_assert (ret == 0);
4961 x86_patch (ip, target);
4964 x86_patch (ip, target);
4967 case MONO_PATCH_INFO_NONE:
4969 case MONO_PATCH_INFO_R4:
4970 case MONO_PATCH_INFO_R8: {
4971 guint32 offset = mono_arch_get_patch_offset (ip);
4972 *((gconstpointer *)(ip + offset)) = target;
4976 guint32 offset = mono_arch_get_patch_offset (ip);
4977 #if !defined(__native_client__)
4978 *((gconstpointer *)(ip + offset)) = target;
4980 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
4988 static G_GNUC_UNUSED void
4989 stack_unaligned (MonoMethod *m, gpointer caller)
4991 printf ("%s\n", mono_method_full_name (m, TRUE));
4992 g_assert_not_reached ();
4996 mono_arch_emit_prolog (MonoCompile *cfg)
4998 MonoMethod *method = cfg->method;
5000 MonoMethodSignature *sig;
5002 int alloc_size, pos, max_offset, i, cfa_offset;
5004 gboolean need_stack_frame;
5005 #ifdef __native_client_codegen__
5006 guint alignment_check;
5009 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5011 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5012 cfg->code_size += 512;
5014 #if defined(__default_codegen__)
5015 code = cfg->native_code = g_malloc (cfg->code_size);
5016 #elif defined(__native_client_codegen__)
5017 /* native_code_alloc is not 32-byte aligned, native_code is. */
5018 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5019 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5021 /* Align native_code to next nearest kNaclAlignment byte. */
5022 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5023 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5025 code = cfg->native_code;
5027 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5028 g_assert(alignment_check == 0);
5035 /* Check that the stack is aligned on osx */
5036 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5037 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5038 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5040 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5041 x86_push_membase (code, X86_ESP, 0);
5042 x86_push_imm (code, cfg->method);
5043 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5044 x86_call_reg (code, X86_EAX);
5045 x86_patch (br [0], code);
5049 /* Offset between RSP and the CFA */
5053 cfa_offset = sizeof (gpointer);
5054 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5055 // IP saved at CFA - 4
5056 /* There is no IP reg on x86 */
5057 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5058 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5060 need_stack_frame = needs_stack_frame (cfg);
5062 if (need_stack_frame) {
5063 x86_push_reg (code, X86_EBP);
5064 cfa_offset += sizeof (gpointer);
5065 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5066 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5067 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5068 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5069 /* These are handled automatically by the stack marking code */
5070 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5072 cfg->frame_reg = X86_ESP;
5075 alloc_size = cfg->stack_offset;
5078 if (method->save_lmf) {
5079 pos += sizeof (MonoLMF);
5081 /* save the current IP */
5082 if (cfg->compile_aot) {
5083 /* This pushes the current ip */
5084 x86_call_imm (code, 0);
5086 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
5087 x86_push_imm_template (code);
5089 cfa_offset += sizeof (gpointer);
5090 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5092 /* save all caller saved regs */
5093 x86_push_reg (code, X86_EBP);
5094 cfa_offset += sizeof (gpointer);
5095 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5096 x86_push_reg (code, X86_ESI);
5097 cfa_offset += sizeof (gpointer);
5098 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5099 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5100 x86_push_reg (code, X86_EDI);
5101 cfa_offset += sizeof (gpointer);
5102 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5103 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5104 x86_push_reg (code, X86_EBX);
5105 cfa_offset += sizeof (gpointer);
5106 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5107 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5109 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5111 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5112 * through the mono_lmf_addr TLS variable.
5114 /* %eax = previous_lmf */
5115 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_tls_offset);
5116 /* skip esp + method_info + lmf */
5117 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 12);
5119 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5120 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + 4, SLOT_NOREF);
5121 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + 8, SLOT_NOREF);
5122 /* push previous_lmf */
5123 x86_push_reg (code, X86_EAX);
5125 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5127 code = mono_x86_emit_tls_set (code, X86_ESP, lmf_tls_offset);
5129 /* get the address of lmf for the current thread */
5131 * This is performance critical so we try to use some tricks to make
5134 gboolean have_fastpath = FALSE;
5137 if (jit_tls_offset != -1) {
5138 code = mono_x86_emit_tls_get (code, X86_EAX, jit_tls_offset);
5139 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5140 have_fastpath = TRUE;
5143 if (lmf_addr_tls_offset != -1) {
5144 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
5145 have_fastpath = TRUE;
5148 if (!have_fastpath) {
5149 if (cfg->compile_aot)
5150 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
5151 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
5154 /* Skip esp + method info */
5155 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
5158 x86_push_reg (code, X86_EAX);
5159 /* push *lfm (previous_lmf) */
5160 x86_push_membase (code, X86_EAX, 0);
5162 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
5166 if (cfg->used_int_regs & (1 << X86_EBX)) {
5167 x86_push_reg (code, X86_EBX);
5169 cfa_offset += sizeof (gpointer);
5170 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5171 /* These are handled automatically by the stack marking code */
5172 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5175 if (cfg->used_int_regs & (1 << X86_EDI)) {
5176 x86_push_reg (code, X86_EDI);
5178 cfa_offset += sizeof (gpointer);
5179 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5180 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5183 if (cfg->used_int_regs & (1 << X86_ESI)) {
5184 x86_push_reg (code, X86_ESI);
5186 cfa_offset += sizeof (gpointer);
5187 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5188 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5194 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5195 if (mono_do_x86_stack_align && need_stack_frame) {
5196 int tot = alloc_size + pos + 4; /* ret ip */
5197 if (need_stack_frame)
5199 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5201 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5202 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5203 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5207 cfg->arch.sp_fp_offset = alloc_size + pos;
5210 /* See mono_emit_stack_alloc */
5211 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5212 guint32 remaining_size = alloc_size;
5213 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5214 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5215 guint32 offset = code - cfg->native_code;
5216 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5217 while (required_code_size >= (cfg->code_size - offset))
5218 cfg->code_size *= 2;
5219 cfg->native_code = mono_realloc_native_code(cfg);
5220 code = cfg->native_code + offset;
5221 cfg->stat_code_reallocs++;
5223 while (remaining_size >= 0x1000) {
5224 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5225 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5226 remaining_size -= 0x1000;
5229 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5231 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5234 g_assert (need_stack_frame);
5237 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5238 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5239 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5242 #if DEBUG_STACK_ALIGNMENT
5243 /* check the stack is aligned */
5244 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5245 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5246 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5247 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5248 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5249 x86_breakpoint (code);
5253 /* compute max_offset in order to use short forward jumps */
5255 if (cfg->opt & MONO_OPT_BRANCH) {
5256 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5258 bb->max_offset = max_offset;
5260 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5262 /* max alignment for loops */
5263 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5264 max_offset += LOOP_ALIGNMENT;
5265 #ifdef __native_client_codegen__
5266 /* max alignment for native client */
5267 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5268 max_offset += kNaClAlignment;
5270 MONO_BB_FOR_EACH_INS (bb, ins) {
5271 if (ins->opcode == OP_LABEL)
5272 ins->inst_c1 = max_offset;
5273 #ifdef __native_client_codegen__
5274 switch (ins->opcode)
5286 case OP_VOIDCALL_REG:
5288 case OP_FCALL_MEMBASE:
5289 case OP_LCALL_MEMBASE:
5290 case OP_VCALL_MEMBASE:
5291 case OP_VCALL2_MEMBASE:
5292 case OP_VOIDCALL_MEMBASE:
5293 case OP_CALL_MEMBASE:
5294 max_offset += kNaClAlignment;
5297 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5300 #endif /* __native_client_codegen__ */
5301 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5306 /* store runtime generic context */
5307 if (cfg->rgctx_var) {
5308 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5310 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5313 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5314 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5316 /* load arguments allocated to register from the stack */
5317 sig = mono_method_signature (method);
5320 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5321 inst = cfg->args [pos];
5322 if (inst->opcode == OP_REGVAR) {
5323 g_assert (need_stack_frame);
5324 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5325 if (cfg->verbose_level > 2)
5326 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5331 cfg->code_len = code - cfg->native_code;
5333 g_assert (cfg->code_len < cfg->code_size);
5339 mono_arch_emit_epilog (MonoCompile *cfg)
5341 MonoMethod *method = cfg->method;
5342 MonoMethodSignature *sig = mono_method_signature (method);
5344 guint32 stack_to_pop;
5346 int max_epilog_size = 16;
5348 gboolean need_stack_frame = needs_stack_frame (cfg);
5350 if (cfg->method->save_lmf)
5351 max_epilog_size += 128;
5353 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5354 cfg->code_size *= 2;
5355 cfg->native_code = mono_realloc_native_code(cfg);
5356 cfg->stat_code_reallocs++;
5359 code = cfg->native_code + cfg->code_len;
5361 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5362 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5364 /* the code restoring the registers must be kept in sync with OP_JMP */
5367 if (method->save_lmf) {
5368 gint32 prev_lmf_reg;
5369 gint32 lmf_offset = -sizeof (MonoLMF);
5371 /* check if we need to restore protection of the stack after a stack overflow */
5372 if (mono_get_jit_tls_offset () != -1) {
5374 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5375 /* we load the value in a separate instruction: this mechanism may be
5376 * used later as a safer way to do thread interruption
5378 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5379 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5381 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5382 /* note that the call trampoline will preserve eax/edx */
5383 x86_call_reg (code, X86_ECX);
5384 x86_patch (patch, code);
5386 /* FIXME: maybe save the jit tls in the prolog */
5388 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5390 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5391 * through the mono_lmf_addr TLS variable.
5393 /* reg = previous_lmf */
5394 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5396 /* lmf = previous_lmf */
5397 code = mono_x86_emit_tls_set (code, X86_ECX, lmf_tls_offset);
5399 /* Find a spare register */
5400 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
5403 prev_lmf_reg = X86_EDI;
5404 cfg->used_int_regs |= (1 << X86_EDI);
5407 prev_lmf_reg = X86_EDX;
5411 /* reg = previous_lmf */
5412 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5415 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
5417 /* *(lmf) = previous_lmf */
5418 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
5421 /* restore caller saved regs */
5422 if (cfg->used_int_regs & (1 << X86_EBX)) {
5423 x86_mov_reg_membase (code, X86_EBX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
5426 if (cfg->used_int_regs & (1 << X86_EDI)) {
5427 x86_mov_reg_membase (code, X86_EDI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
5429 if (cfg->used_int_regs & (1 << X86_ESI)) {
5430 x86_mov_reg_membase (code, X86_ESI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
5433 /* EBP is restored by LEAVE */
5435 if (cfg->used_int_regs & (1 << X86_EBX)) {
5438 if (cfg->used_int_regs & (1 << X86_EDI)) {
5441 if (cfg->used_int_regs & (1 << X86_ESI)) {
5446 g_assert (need_stack_frame);
5447 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5450 if (cfg->used_int_regs & (1 << X86_ESI)) {
5451 x86_pop_reg (code, X86_ESI);
5453 if (cfg->used_int_regs & (1 << X86_EDI)) {
5454 x86_pop_reg (code, X86_EDI);
5456 if (cfg->used_int_regs & (1 << X86_EBX)) {
5457 x86_pop_reg (code, X86_EBX);
5461 /* Load returned vtypes into registers if needed */
5462 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5463 if (cinfo->ret.storage == ArgValuetypeInReg) {
5464 for (quad = 0; quad < 2; quad ++) {
5465 switch (cinfo->ret.pair_storage [quad]) {
5467 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5469 case ArgOnFloatFpStack:
5470 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5472 case ArgOnDoubleFpStack:
5473 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5478 g_assert_not_reached ();
5483 if (need_stack_frame)
5486 if (CALLCONV_IS_STDCALL (sig)) {
5487 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5489 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5490 } else if (cinfo->vtype_retaddr)
5496 g_assert (need_stack_frame);
5497 x86_ret_imm (code, stack_to_pop);
5502 cfg->code_len = code - cfg->native_code;
5504 g_assert (cfg->code_len < cfg->code_size);
5508 mono_arch_emit_exceptions (MonoCompile *cfg)
5510 MonoJumpInfo *patch_info;
5513 MonoClass *exc_classes [16];
5514 guint8 *exc_throw_start [16], *exc_throw_end [16];
5518 /* Compute needed space */
5519 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5520 if (patch_info->type == MONO_PATCH_INFO_EXC)
5525 * make sure we have enough space for exceptions
5526 * 16 is the size of two push_imm instructions and a call
5528 if (cfg->compile_aot)
5529 code_size = exc_count * 32;
5531 code_size = exc_count * 16;
5533 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5534 cfg->code_size *= 2;
5535 cfg->native_code = mono_realloc_native_code(cfg);
5536 cfg->stat_code_reallocs++;
5539 code = cfg->native_code + cfg->code_len;
5542 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5543 switch (patch_info->type) {
5544 case MONO_PATCH_INFO_EXC: {
5545 MonoClass *exc_class;
5549 x86_patch (patch_info->ip.i + cfg->native_code, code);
5551 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5552 g_assert (exc_class);
5553 throw_ip = patch_info->ip.i;
5555 /* Find a throw sequence for the same exception class */
5556 for (i = 0; i < nthrows; ++i)
5557 if (exc_classes [i] == exc_class)
5560 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5561 x86_jump_code (code, exc_throw_start [i]);
5562 patch_info->type = MONO_PATCH_INFO_NONE;
5567 /* Compute size of code following the push <OFFSET> */
5568 #if defined(__default_codegen__)
5570 #elif defined(__native_client_codegen__)
5571 code = mono_nacl_align (code);
5572 size = kNaClAlignment;
5574 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5576 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5577 /* Use the shorter form */
5579 x86_push_imm (code, 0);
5583 x86_push_imm (code, 0xf0f0f0f0);
5588 exc_classes [nthrows] = exc_class;
5589 exc_throw_start [nthrows] = code;
5592 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5593 patch_info->data.name = "mono_arch_throw_corlib_exception";
5594 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5595 patch_info->ip.i = code - cfg->native_code;
5596 x86_call_code (code, 0);
5597 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5602 exc_throw_end [nthrows] = code;
5614 cfg->code_len = code - cfg->native_code;
5616 g_assert (cfg->code_len < cfg->code_size);
5620 mono_arch_flush_icache (guint8 *code, gint size)
5626 mono_arch_flush_register_windows (void)
5631 mono_arch_is_inst_imm (gint64 imm)
5637 mono_arch_finish_init (void)
5639 if (!getenv ("MONO_NO_TLS")) {
5642 * We need to init this multiple times, since when we are first called, the key might not
5643 * be initialized yet.
5645 appdomain_tls_offset = mono_domain_get_tls_key ();
5646 jit_tls_offset = mono_get_jit_tls_key ();
5648 /* Only 64 tls entries can be accessed using inline code */
5649 if (appdomain_tls_offset >= 64)
5650 appdomain_tls_offset = -1;
5651 if (jit_tls_offset >= 64)
5652 jit_tls_offset = -1;
5655 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5657 appdomain_tls_offset = mono_domain_get_tls_offset ();
5658 lmf_tls_offset = mono_get_lmf_tls_offset ();
5659 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5665 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5669 #ifdef MONO_ARCH_HAVE_IMT
5671 // Linear handler, the bsearch head compare is shorter
5672 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5673 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5674 // x86_patch(ins,target)
5675 //[1 + 5] x86_jump_mem(inst,mem)
5678 #if defined(__default_codegen__)
5679 #define BR_SMALL_SIZE 2
5680 #define BR_LARGE_SIZE 5
5681 #elif defined(__native_client_codegen__)
5682 /* I suspect the size calculation below is actually incorrect. */
5683 /* TODO: fix the calculation that uses these sizes. */
5684 #define BR_SMALL_SIZE 16
5685 #define BR_LARGE_SIZE 12
5686 #endif /*__native_client_codegen__*/
5687 #define JUMP_IMM_SIZE 6
5688 #define ENABLE_WRONG_METHOD_CHECK 0
5692 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5694 int i, distance = 0;
5695 for (i = start; i < target; ++i)
5696 distance += imt_entries [i]->chunk_size;
5701 * LOCKING: called with the domain lock held
5704 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5705 gpointer fail_tramp)
5709 guint8 *code, *start;
5711 for (i = 0; i < count; ++i) {
5712 MonoIMTCheckItem *item = imt_entries [i];
5713 if (item->is_equals) {
5714 if (item->check_target_idx) {
5715 if (!item->compare_done)
5716 item->chunk_size += CMP_SIZE;
5717 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5720 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5722 item->chunk_size += JUMP_IMM_SIZE;
5723 #if ENABLE_WRONG_METHOD_CHECK
5724 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5729 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5730 imt_entries [item->check_target_idx]->compare_done = TRUE;
5732 size += item->chunk_size;
5734 #if defined(__native_client__) && defined(__native_client_codegen__)
5735 /* In Native Client, we don't re-use thunks, allocate from the */
5736 /* normal code manager paths. */
5737 size = NACL_BUNDLE_ALIGN_UP (size);
5738 code = mono_domain_code_reserve (domain, size);
5741 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5743 code = mono_domain_code_reserve (domain, size);
5746 for (i = 0; i < count; ++i) {
5747 MonoIMTCheckItem *item = imt_entries [i];
5748 item->code_target = code;
5749 if (item->is_equals) {
5750 if (item->check_target_idx) {
5751 if (!item->compare_done)
5752 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5753 item->jmp_code = code;
5754 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5755 if (item->has_target_code)
5756 x86_jump_code (code, item->value.target_code);
5758 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5761 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5762 item->jmp_code = code;
5763 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5764 if (item->has_target_code)
5765 x86_jump_code (code, item->value.target_code);
5767 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5768 x86_patch (item->jmp_code, code);
5769 x86_jump_code (code, fail_tramp);
5770 item->jmp_code = NULL;
5772 /* enable the commented code to assert on wrong method */
5773 #if ENABLE_WRONG_METHOD_CHECK
5774 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5775 item->jmp_code = code;
5776 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5778 if (item->has_target_code)
5779 x86_jump_code (code, item->value.target_code);
5781 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5782 #if ENABLE_WRONG_METHOD_CHECK
5783 x86_patch (item->jmp_code, code);
5784 x86_breakpoint (code);
5785 item->jmp_code = NULL;
5790 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5791 item->jmp_code = code;
5792 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5793 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5795 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5798 /* patch the branches to get to the target items */
5799 for (i = 0; i < count; ++i) {
5800 MonoIMTCheckItem *item = imt_entries [i];
5801 if (item->jmp_code) {
5802 if (item->check_target_idx) {
5803 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5809 mono_stats.imt_thunks_size += code - start;
5810 g_assert (code - start <= size);
5814 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5815 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5819 if (mono_jit_map_is_enabled ()) {
5822 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5824 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5825 mono_emit_jit_tramp (start, code - start, buff);
5829 nacl_domain_code_validate (domain, &start, size, &code);
5835 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5837 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5842 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5844 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5848 mono_arch_get_cie_program (void)
5852 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5853 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5859 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5861 MonoInst *ins = NULL;
5864 if (cmethod->klass == mono_defaults.math_class) {
5865 if (strcmp (cmethod->name, "Sin") == 0) {
5867 } else if (strcmp (cmethod->name, "Cos") == 0) {
5869 } else if (strcmp (cmethod->name, "Tan") == 0) {
5871 } else if (strcmp (cmethod->name, "Atan") == 0) {
5873 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5875 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5877 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5882 MONO_INST_NEW (cfg, ins, opcode);
5883 ins->type = STACK_R8;
5884 ins->dreg = mono_alloc_freg (cfg);
5885 ins->sreg1 = args [0]->dreg;
5886 MONO_ADD_INS (cfg->cbb, ins);
5889 if (cfg->opt & MONO_OPT_CMOV) {
5892 if (strcmp (cmethod->name, "Min") == 0) {
5893 if (fsig->params [0]->type == MONO_TYPE_I4)
5895 } else if (strcmp (cmethod->name, "Max") == 0) {
5896 if (fsig->params [0]->type == MONO_TYPE_I4)
5901 MONO_INST_NEW (cfg, ins, opcode);
5902 ins->type = STACK_I4;
5903 ins->dreg = mono_alloc_ireg (cfg);
5904 ins->sreg1 = args [0]->dreg;
5905 ins->sreg2 = args [1]->dreg;
5906 MONO_ADD_INS (cfg->cbb, ins);
5911 /* OP_FREM is not IEEE compatible */
5912 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5913 MONO_INST_NEW (cfg, ins, OP_FREM);
5914 ins->inst_i0 = args [0];
5915 ins->inst_i1 = args [1];
5924 mono_arch_print_tree (MonoInst *tree, int arity)
5929 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5935 if (appdomain_tls_offset == -1)
5938 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5939 ins->inst_offset = appdomain_tls_offset;
5944 mono_arch_get_patch_offset (guint8 *code)
5946 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5948 else if (code [0] == 0xba)
5950 else if (code [0] == 0x68)
5953 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5954 /* push <OFFSET>(<REG>) */
5956 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5957 /* call *<OFFSET>(<REG>) */
5959 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5962 else if ((code [0] == 0x58) && (code [1] == 0x05))
5963 /* pop %eax; add <OFFSET>, %eax */
5965 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5966 /* pop <REG>; add <OFFSET>, <REG> */
5968 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5969 /* mov <REG>, imm */
5972 g_assert_not_reached ();
5978 * mono_breakpoint_clean_code:
5980 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5981 * breakpoints in the original code, they are removed in the copy.
5983 * Returns TRUE if no sw breakpoint was present.
5986 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5989 gboolean can_write = TRUE;
5991 * If method_start is non-NULL we need to perform bound checks, since we access memory
5992 * at code - offset we could go before the start of the method and end up in a different
5993 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5996 if (!method_start || code - offset >= method_start) {
5997 memcpy (buf, code - offset, size);
5999 int diff = code - method_start;
6000 memset (buf, 0, size);
6001 memcpy (buf + offset - diff, method_start, diff + size - offset);
6004 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6005 int idx = mono_breakpoint_info_index [i];
6009 ptr = mono_breakpoint_info [idx].address;
6010 if (ptr >= code && ptr < code + size) {
6011 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6013 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6014 buf [ptr - code] = saved_byte;
6021 * mono_x86_get_this_arg_offset:
6023 * Return the offset of the stack location where this is passed during a virtual
6027 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6033 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6035 guint32 esp = regs [X86_ESP];
6036 CallInfo *cinfo = NULL;
6043 * The stack looks like:
6047 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
6049 res = (((MonoObject**)esp) [5 + (offset / 4)]);
6055 #define MAX_ARCH_DELEGATE_PARAMS 10
6058 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6060 guint8 *code, *start;
6061 int code_reserve = 64;
6064 * The stack contains:
6070 start = code = mono_global_codeman_reserve (code_reserve);
6072 /* Replace the this argument with the target */
6073 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6074 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
6075 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6076 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6078 g_assert ((code - start) < code_reserve);
6081 /* 8 for mov_reg and jump, plus 8 for each parameter */
6082 #ifdef __native_client_codegen__
6083 /* TODO: calculate this size correctly */
6084 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6086 code_reserve = 8 + (param_count * 8);
6087 #endif /* __native_client_codegen__ */
6089 * The stack contains:
6090 * <args in reverse order>
6095 * <args in reverse order>
6098 * without unbalancing the stack.
6099 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6100 * and leaving original spot of first arg as placeholder in stack so
6101 * when callee pops stack everything works.
6104 start = code = mono_global_codeman_reserve (code_reserve);
6106 /* store delegate for access to method_ptr */
6107 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6110 for (i = 0; i < param_count; ++i) {
6111 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6112 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6115 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6117 g_assert ((code - start) < code_reserve);
6120 nacl_global_codeman_validate(&start, code_reserve, &code);
6121 mono_debug_add_delegate_trampoline (start, code - start);
6124 *code_len = code - start;
6126 if (mono_jit_map_is_enabled ()) {
6129 buff = (char*)"delegate_invoke_has_target";
6131 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6132 mono_emit_jit_tramp (start, code - start, buff);
6141 mono_arch_get_delegate_invoke_impls (void)
6149 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6150 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
6152 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6153 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6154 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
6155 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
6156 g_free (tramp_name);
6163 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6165 guint8 *code, *start;
6167 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6170 /* FIXME: Support more cases */
6171 if (MONO_TYPE_ISSTRUCT (sig->ret))
6175 * The stack contains:
6181 static guint8* cached = NULL;
6186 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6188 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6190 mono_memory_barrier ();
6194 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6197 for (i = 0; i < sig->param_count; ++i)
6198 if (!mono_is_regsize_var (sig->params [i]))
6201 code = cache [sig->param_count];
6205 if (mono_aot_only) {
6206 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6207 start = mono_aot_get_trampoline (name);
6210 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6213 mono_memory_barrier ();
6215 cache [sig->param_count] = start;
6222 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6225 case X86_EAX: return ctx->eax;
6226 case X86_EBX: return ctx->ebx;
6227 case X86_ECX: return ctx->ecx;
6228 case X86_EDX: return ctx->edx;
6229 case X86_ESP: return ctx->esp;
6230 case X86_EBP: return ctx->ebp;
6231 case X86_ESI: return ctx->esi;
6232 case X86_EDI: return ctx->edi;
6234 g_assert_not_reached ();
6240 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6268 g_assert_not_reached ();
6272 #ifdef MONO_ARCH_SIMD_INTRINSICS
6275 get_float_to_x_spill_area (MonoCompile *cfg)
6277 if (!cfg->fconv_to_r8_x_var) {
6278 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6279 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6281 return cfg->fconv_to_r8_x_var;
6285 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6288 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6291 int dreg, src_opcode;
6293 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6296 switch (src_opcode = ins->opcode) {
6297 case OP_FCONV_TO_I1:
6298 case OP_FCONV_TO_U1:
6299 case OP_FCONV_TO_I2:
6300 case OP_FCONV_TO_U2:
6301 case OP_FCONV_TO_I4:
6308 /* dreg is the IREG and sreg1 is the FREG */
6309 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6310 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6311 fconv->sreg1 = ins->sreg1;
6312 fconv->dreg = mono_alloc_ireg (cfg);
6313 fconv->type = STACK_VTYPE;
6314 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6316 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6320 ins->opcode = OP_XCONV_R8_TO_I4;
6322 ins->klass = mono_defaults.int32_class;
6323 ins->sreg1 = fconv->dreg;
6325 ins->type = STACK_I4;
6326 ins->backend.source_opcode = src_opcode;
6329 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6332 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6337 if (long_ins->opcode == OP_LNEG) {
6339 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6340 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6341 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6346 #ifdef MONO_ARCH_SIMD_INTRINSICS
6348 if (!(cfg->opt & MONO_OPT_SIMD))
6351 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6352 switch (long_ins->opcode) {
6354 vreg = long_ins->sreg1;
6356 if (long_ins->inst_c0) {
6357 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6358 ins->klass = long_ins->klass;
6359 ins->sreg1 = long_ins->sreg1;
6361 ins->type = STACK_VTYPE;
6362 ins->dreg = vreg = alloc_ireg (cfg);
6363 MONO_ADD_INS (cfg->cbb, ins);
6366 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6367 ins->klass = mono_defaults.int32_class;
6369 ins->type = STACK_I4;
6370 ins->dreg = long_ins->dreg + 1;
6371 MONO_ADD_INS (cfg->cbb, ins);
6373 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6374 ins->klass = long_ins->klass;
6375 ins->sreg1 = long_ins->sreg1;
6376 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6377 ins->type = STACK_VTYPE;
6378 ins->dreg = vreg = alloc_ireg (cfg);
6379 MONO_ADD_INS (cfg->cbb, ins);
6381 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6382 ins->klass = mono_defaults.int32_class;
6384 ins->type = STACK_I4;
6385 ins->dreg = long_ins->dreg + 2;
6386 MONO_ADD_INS (cfg->cbb, ins);
6388 long_ins->opcode = OP_NOP;
6390 case OP_INSERTX_I8_SLOW:
6391 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6392 ins->dreg = long_ins->dreg;
6393 ins->sreg1 = long_ins->dreg;
6394 ins->sreg2 = long_ins->sreg2 + 1;
6395 ins->inst_c0 = long_ins->inst_c0 * 2;
6396 MONO_ADD_INS (cfg->cbb, ins);
6398 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6399 ins->dreg = long_ins->dreg;
6400 ins->sreg1 = long_ins->dreg;
6401 ins->sreg2 = long_ins->sreg2 + 2;
6402 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6403 MONO_ADD_INS (cfg->cbb, ins);
6405 long_ins->opcode = OP_NOP;
6408 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6409 ins->dreg = long_ins->dreg;
6410 ins->sreg1 = long_ins->sreg1 + 1;
6411 ins->klass = long_ins->klass;
6412 ins->type = STACK_VTYPE;
6413 MONO_ADD_INS (cfg->cbb, ins);
6415 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6416 ins->dreg = long_ins->dreg;
6417 ins->sreg1 = long_ins->dreg;
6418 ins->sreg2 = long_ins->sreg1 + 2;
6420 ins->klass = long_ins->klass;
6421 ins->type = STACK_VTYPE;
6422 MONO_ADD_INS (cfg->cbb, ins);
6424 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6425 ins->dreg = long_ins->dreg;
6426 ins->sreg1 = long_ins->dreg;;
6427 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6428 ins->klass = long_ins->klass;
6429 ins->type = STACK_VTYPE;
6430 MONO_ADD_INS (cfg->cbb, ins);
6432 long_ins->opcode = OP_NOP;
6435 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6438 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6440 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6443 gpointer *sp, old_value;
6445 const unsigned char *handler;
6447 /*Decode the first instruction to figure out where did we store the spvar*/
6448 /*Our jit MUST generate the following:
6450 Which is encoded as: 0x89 mod_rm.
6451 mod_rm (esp, ebp, imm) which can be: (imm will never be zero)
6452 mod (reg + imm8): 01 reg(esp): 100 rm(ebp): 101 -> 01100101 (0x65)
6453 mod (reg + imm32): 10 reg(esp): 100 rm(ebp): 101 -> 10100101 (0xA5)
6455 handler = clause->handler_start;
6457 if (*handler != 0x89)
6462 if (*handler == 0x65)
6463 offset = *(signed char*)(handler + 1);
6464 else if (*handler == 0xA5)
6465 offset = *(int*)(handler + 1);
6470 bp = MONO_CONTEXT_GET_BP (ctx);
6471 sp = *(gpointer*)(bp + offset);
6474 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6483 * mono_aot_emit_load_got_addr:
6485 * Emit code to load the got address.
6486 * On x86, the result is placed into EBX.
6489 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6491 x86_call_imm (code, 0);
6493 * The patch needs to point to the pop, since the GOT offset needs
6494 * to be added to that address.
6497 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6499 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6500 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6501 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6507 * mono_ppc_emit_load_aotconst:
6509 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6510 * TARGET from the mscorlib GOT in full-aot code.
6511 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6515 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6517 /* Load the mscorlib got address */
6518 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6519 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6520 /* arch_emit_got_access () patches this */
6521 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6526 /* Can't put this into mini-x86.h */
6528 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6531 mono_arch_get_trampolines (gboolean aot)
6533 MonoTrampInfo *info;
6534 GSList *tramps = NULL;
6536 mono_x86_get_signal_exception_trampoline (&info, aot);
6538 tramps = g_slist_append (tramps, info);
6545 #define DBG_SIGNAL SIGBUS
6547 #define DBG_SIGNAL SIGSEGV
6550 /* Soft Debug support */
6551 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6554 * mono_arch_set_breakpoint:
6556 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6557 * The location should contain code emitted by OP_SEQ_POINT.
6560 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6565 * In production, we will use int3 (has to fix the size in the md
6566 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6569 g_assert (code [0] == 0x90);
6570 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6574 * mono_arch_clear_breakpoint:
6576 * Clear the breakpoint at IP.
6579 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6584 for (i = 0; i < 6; ++i)
6589 * mono_arch_start_single_stepping:
6591 * Start single stepping.
6594 mono_arch_start_single_stepping (void)
6596 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6600 * mono_arch_stop_single_stepping:
6602 * Stop single stepping.
6605 mono_arch_stop_single_stepping (void)
6607 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6611 * mono_arch_is_single_step_event:
6613 * Return whenever the machine state in SIGCTX corresponds to a single
6617 mono_arch_is_single_step_event (void *info, void *sigctx)
6620 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6622 if (((gpointer)einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6627 siginfo_t* sinfo = (siginfo_t*) info;
6628 /* Sometimes the address is off by 4 */
6629 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6637 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6640 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6641 if (((gpointer)einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6646 siginfo_t* sinfo = (siginfo_t*)info;
6647 /* Sometimes the address is off by 4 */
6648 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6655 #define BREAKPOINT_SIZE 6
6658 * mono_arch_skip_breakpoint:
6660 * See mini-amd64.c for docs.
6663 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6665 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6669 * mono_arch_skip_single_step:
6671 * See mini-amd64.c for docs.
6674 mono_arch_skip_single_step (MonoContext *ctx)
6676 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6680 * mono_arch_get_seq_point_info:
6682 * See mini-amd64.c for docs.
6685 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6693 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
6695 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6697 #endif /* !MONOTOUCH */