2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * (C) 2003 Ximian, Inc.
18 #include <mono/metadata/appdomain.h>
19 #include <mono/metadata/debug-helpers.h>
20 #include <mono/metadata/threads.h>
21 #include <mono/metadata/profiler-private.h>
22 #include <mono/metadata/mono-debug.h>
23 #include <mono/utils/mono-math.h>
24 #include <mono/utils/mono-counters.h>
25 #include <mono/utils/mono-mmap.h>
32 /* On windows, these hold the key returned by TlsAlloc () */
33 static gint lmf_tls_offset = -1;
34 static gint lmf_addr_tls_offset = -1;
35 static gint appdomain_tls_offset = -1;
38 static gboolean optimize_for_xen = TRUE;
40 #define optimize_for_xen 0
44 static gboolean is_win32 = TRUE;
46 static gboolean is_win32 = FALSE;
49 /* This mutex protects architecture specific caches */
50 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
51 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
52 static CRITICAL_SECTION mini_arch_mutex;
54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
59 /* Under windows, the default pinvoke calling convention is stdcall */
60 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT))
62 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL)
66 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
69 * The code generated for sequence points reads from this location, which is
70 * made read-only when single stepping is enabled.
72 static gpointer ss_trigger_page;
74 /* Enabled breakpoints read from this trigger page */
75 static gpointer bp_trigger_page;
78 mono_arch_regname (int reg)
81 case X86_EAX: return "%eax";
82 case X86_EBX: return "%ebx";
83 case X86_ECX: return "%ecx";
84 case X86_EDX: return "%edx";
85 case X86_ESP: return "%esp";
86 case X86_EBP: return "%ebp";
87 case X86_EDI: return "%edi";
88 case X86_ESI: return "%esi";
94 mono_arch_fregname (int reg)
119 mono_arch_xregname (int reg)
160 /* Only if storage == ArgValuetypeInReg */
161 ArgStorage pair_storage [2];
170 gboolean need_stack_align;
171 guint32 stack_align_amount;
179 #define FLOAT_PARAM_REGS 0
181 static X86_Reg_No param_regs [] = { 0 };
183 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
184 #define SMALL_STRUCTS_IN_REGS
185 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
189 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
191 ainfo->offset = *stack_size;
193 if (*gr >= PARAM_REGS) {
194 ainfo->storage = ArgOnStack;
195 (*stack_size) += sizeof (gpointer);
198 ainfo->storage = ArgInIReg;
199 ainfo->reg = param_regs [*gr];
205 add_general_pair (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
207 ainfo->offset = *stack_size;
209 g_assert (PARAM_REGS == 0);
211 ainfo->storage = ArgOnStack;
212 (*stack_size) += sizeof (gpointer) * 2;
216 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
218 ainfo->offset = *stack_size;
220 if (*gr >= FLOAT_PARAM_REGS) {
221 ainfo->storage = ArgOnStack;
222 (*stack_size) += is_double ? 8 : 4;
225 /* A double register */
227 ainfo->storage = ArgInDoubleSSEReg;
229 ainfo->storage = ArgInFloatSSEReg;
237 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
239 guint32 *gr, guint32 *fr, guint32 *stack_size)
244 klass = mono_class_from_mono_type (type);
245 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
247 #ifdef SMALL_STRUCTS_IN_REGS
248 if (sig->pinvoke && is_return) {
249 MonoMarshalType *info;
252 * the exact rules are not very well documented, the code below seems to work with the
253 * code generated by gcc 3.3.3 -mno-cygwin.
255 info = mono_marshal_load_type_info (klass);
258 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
260 /* Special case structs with only a float member */
261 if ((info->native_size == 8) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R8)) {
262 ainfo->storage = ArgValuetypeInReg;
263 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
266 if ((info->native_size == 4) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R4)) {
267 ainfo->storage = ArgValuetypeInReg;
268 ainfo->pair_storage [0] = ArgOnFloatFpStack;
271 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
272 ainfo->storage = ArgValuetypeInReg;
273 ainfo->pair_storage [0] = ArgInIReg;
274 ainfo->pair_regs [0] = return_regs [0];
275 if (info->native_size > 4) {
276 ainfo->pair_storage [1] = ArgInIReg;
277 ainfo->pair_regs [1] = return_regs [1];
284 ainfo->offset = *stack_size;
285 ainfo->storage = ArgOnStack;
286 *stack_size += ALIGN_TO (size, sizeof (gpointer));
292 * Obtain information about a call according to the calling convention.
293 * For x86 ELF, see the "System V Application Binary Interface Intel386
294 * Architecture Processor Supplment, Fourth Edition" document for more
296 * For x86 win32, see ???.
299 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig, gboolean is_pinvoke)
303 int n = sig->hasthis + sig->param_count;
304 guint32 stack_size = 0;
311 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
312 switch (ret_type->type) {
313 case MONO_TYPE_BOOLEAN:
324 case MONO_TYPE_FNPTR:
325 case MONO_TYPE_CLASS:
326 case MONO_TYPE_OBJECT:
327 case MONO_TYPE_SZARRAY:
328 case MONO_TYPE_ARRAY:
329 case MONO_TYPE_STRING:
330 cinfo->ret.storage = ArgInIReg;
331 cinfo->ret.reg = X86_EAX;
335 cinfo->ret.storage = ArgInIReg;
336 cinfo->ret.reg = X86_EAX;
339 cinfo->ret.storage = ArgOnFloatFpStack;
342 cinfo->ret.storage = ArgOnDoubleFpStack;
344 case MONO_TYPE_GENERICINST:
345 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
346 cinfo->ret.storage = ArgInIReg;
347 cinfo->ret.reg = X86_EAX;
351 case MONO_TYPE_VALUETYPE: {
352 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
354 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
355 if (cinfo->ret.storage == ArgOnStack)
356 /* The caller passes the address where the value is stored */
357 add_general (&gr, &stack_size, &cinfo->ret);
360 case MONO_TYPE_TYPEDBYREF:
361 /* Same as a valuetype with size 24 */
362 add_general (&gr, &stack_size, &cinfo->ret);
366 cinfo->ret.storage = ArgNone;
369 g_error ("Can't handle as return value 0x%x", sig->ret->type);
375 add_general (&gr, &stack_size, cinfo->args + 0);
377 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
379 fr = FLOAT_PARAM_REGS;
381 /* Emit the signature cookie just before the implicit arguments */
382 add_general (&gr, &stack_size, &cinfo->sig_cookie);
385 for (i = 0; i < sig->param_count; ++i) {
386 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
389 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
390 /* We allways pass the sig cookie on the stack for simplicity */
392 * Prevent implicit arguments + the sig cookie from being passed
396 fr = FLOAT_PARAM_REGS;
398 /* Emit the signature cookie just before the implicit arguments */
399 add_general (&gr, &stack_size, &cinfo->sig_cookie);
402 if (sig->params [i]->byref) {
403 add_general (&gr, &stack_size, ainfo);
406 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
407 switch (ptype->type) {
408 case MONO_TYPE_BOOLEAN:
411 add_general (&gr, &stack_size, ainfo);
416 add_general (&gr, &stack_size, ainfo);
420 add_general (&gr, &stack_size, ainfo);
425 case MONO_TYPE_FNPTR:
426 case MONO_TYPE_CLASS:
427 case MONO_TYPE_OBJECT:
428 case MONO_TYPE_STRING:
429 case MONO_TYPE_SZARRAY:
430 case MONO_TYPE_ARRAY:
431 add_general (&gr, &stack_size, ainfo);
433 case MONO_TYPE_GENERICINST:
434 if (!mono_type_generic_inst_is_valuetype (ptype)) {
435 add_general (&gr, &stack_size, ainfo);
439 case MONO_TYPE_VALUETYPE:
440 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
442 case MONO_TYPE_TYPEDBYREF:
443 stack_size += sizeof (MonoTypedRef);
444 ainfo->storage = ArgOnStack;
448 add_general_pair (&gr, &stack_size, ainfo);
451 add_float (&fr, &stack_size, ainfo, FALSE);
454 add_float (&fr, &stack_size, ainfo, TRUE);
457 g_error ("unexpected type 0x%x", ptype->type);
458 g_assert_not_reached ();
462 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
464 fr = FLOAT_PARAM_REGS;
466 /* Emit the signature cookie just before the implicit arguments */
467 add_general (&gr, &stack_size, &cinfo->sig_cookie);
470 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
471 cinfo->need_stack_align = TRUE;
472 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
473 stack_size += cinfo->stack_align_amount;
476 cinfo->stack_usage = stack_size;
477 cinfo->reg_usage = gr;
478 cinfo->freg_usage = fr;
483 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
485 int n = sig->hasthis + sig->param_count;
489 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
491 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
493 return get_call_info_internal (gsctx, cinfo, sig, is_pinvoke);
497 * mono_arch_get_argument_info:
498 * @csig: a method signature
499 * @param_count: the number of parameters to consider
500 * @arg_info: an array to store the result infos
502 * Gathers information on parameters such as size, alignment and
503 * padding. arg_info should be large enought to hold param_count + 1 entries.
505 * Returns the size of the argument area on the stack.
506 * This should be signal safe, since it is called from
507 * mono_arch_find_jit_info_ext ().
508 * FIXME: The metadata calls might not be signal safe.
511 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
513 int k, args_size = 0;
519 /* Avoid g_malloc as it is not signal safe */
520 cinfo = (CallInfo*)g_newa (guint8*, sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1)));
522 cinfo = get_call_info_internal (NULL, cinfo, csig, FALSE);
524 if (MONO_TYPE_ISSTRUCT (csig->ret) && (cinfo->ret.storage == ArgOnStack)) {
525 args_size += sizeof (gpointer);
529 arg_info [0].offset = offset;
532 args_size += sizeof (gpointer);
536 arg_info [0].size = args_size;
538 for (k = 0; k < param_count; k++) {
539 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
541 /* ignore alignment for now */
544 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
545 arg_info [k].pad = pad;
547 arg_info [k + 1].pad = 0;
548 arg_info [k + 1].size = size;
550 arg_info [k + 1].offset = offset;
554 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
555 align = MONO_ARCH_FRAME_ALIGNMENT;
558 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
559 arg_info [k].pad = pad;
564 static const guchar cpuid_impl [] = {
565 0x55, /* push %ebp */
566 0x89, 0xe5, /* mov %esp,%ebp */
567 0x53, /* push %ebx */
568 0x8b, 0x45, 0x08, /* mov 0x8(%ebp),%eax */
569 0x0f, 0xa2, /* cpuid */
570 0x50, /* push %eax */
571 0x8b, 0x45, 0x10, /* mov 0x10(%ebp),%eax */
572 0x89, 0x18, /* mov %ebx,(%eax) */
573 0x8b, 0x45, 0x14, /* mov 0x14(%ebp),%eax */
574 0x89, 0x08, /* mov %ecx,(%eax) */
575 0x8b, 0x45, 0x18, /* mov 0x18(%ebp),%eax */
576 0x89, 0x10, /* mov %edx,(%eax) */
578 0x8b, 0x55, 0x0c, /* mov 0xc(%ebp),%edx */
579 0x89, 0x02, /* mov %eax,(%edx) */
585 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
588 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
592 __asm__ __volatile__ (
595 "movl %%eax, %%edx\n"
596 "xorl $0x200000, %%eax\n"
601 "xorl %%edx, %%eax\n"
602 "andl $0x200000, %%eax\n"
624 /* Have to use the code manager to get around WinXP DEP */
625 static CpuidFunc func = NULL;
628 ptr = mono_global_codeman_reserve (sizeof (cpuid_impl));
629 memcpy (ptr, cpuid_impl, sizeof (cpuid_impl));
630 func = (CpuidFunc)ptr;
632 func (id, p_eax, p_ebx, p_ecx, p_edx);
635 * We use this approach because of issues with gcc and pic code, see:
636 * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
637 __asm__ __volatile__ ("cpuid"
638 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
647 * Initialize the cpu to execute managed code.
650 mono_arch_cpu_init (void)
652 /* spec compliance requires running with double precision */
656 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
657 fpcw &= ~X86_FPCW_PRECC_MASK;
658 fpcw |= X86_FPCW_PREC_DOUBLE;
659 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
660 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
662 _control87 (_PC_53, MCW_PC);
667 * Initialize architecture specific code.
670 mono_arch_init (void)
672 InitializeCriticalSection (&mini_arch_mutex);
674 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
675 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
676 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
680 * Cleanup architecture specific code.
683 mono_arch_cleanup (void)
685 DeleteCriticalSection (&mini_arch_mutex);
689 * This function returns the optimizations supported on this cpu.
692 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
694 int eax, ebx, ecx, edx;
698 /* Feature Flags function, flags returned in EDX. */
699 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
700 if (edx & (1 << 15)) {
701 opts |= MONO_OPT_CMOV;
703 opts |= MONO_OPT_FCMOV;
705 *exclude_mask |= MONO_OPT_FCMOV;
707 *exclude_mask |= MONO_OPT_CMOV;
709 opts |= MONO_OPT_SSE2;
711 *exclude_mask |= MONO_OPT_SSE2;
713 #ifdef MONO_ARCH_SIMD_INTRINSICS
714 /*SIMD intrinsics require at least SSE2.*/
715 if (!(opts & MONO_OPT_SSE2))
716 *exclude_mask |= MONO_OPT_SIMD;
723 * This function test for all SSE functions supported.
725 * Returns a bitmask corresponding to all supported versions.
729 mono_arch_cpu_enumerate_simd_versions (void)
731 int eax, ebx, ecx, edx;
732 guint32 sse_opts = 0;
734 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
736 sse_opts |= 1 << SIMD_VERSION_SSE1;
738 sse_opts |= 1 << SIMD_VERSION_SSE2;
740 sse_opts |= 1 << SIMD_VERSION_SSE3;
742 sse_opts |= 1 << SIMD_VERSION_SSSE3;
744 sse_opts |= 1 << SIMD_VERSION_SSE41;
746 sse_opts |= 1 << SIMD_VERSION_SSE42;
749 /* Yes, all this needs to be done to check for sse4a.
750 See: "Amd: CPUID Specification"
752 if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
753 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
754 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
755 cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
757 sse_opts |= 1 << SIMD_VERSION_SSE4a;
766 * Determine whenever the trap whose info is in SIGINFO is caused by
770 mono_arch_is_int_overflow (void *sigctx, void *info)
775 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
777 ip = (guint8*)ctx.eip;
779 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
783 switch (x86_modrm_rm (ip [1])) {
803 g_assert_not_reached ();
815 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
820 for (i = 0; i < cfg->num_varinfo; i++) {
821 MonoInst *ins = cfg->varinfo [i];
822 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
825 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
828 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
829 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
832 /* we dont allocate I1 to registers because there is no simply way to sign extend
833 * 8bit quantities in caller saved registers on x86 */
834 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
835 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
836 g_assert (i == vmv->idx);
837 vars = g_list_prepend (vars, vmv);
841 vars = mono_varlist_sort (cfg, vars, 0);
847 mono_arch_get_global_int_regs (MonoCompile *cfg)
851 /* we can use 3 registers for global allocation */
852 regs = g_list_prepend (regs, (gpointer)X86_EBX);
853 regs = g_list_prepend (regs, (gpointer)X86_ESI);
854 regs = g_list_prepend (regs, (gpointer)X86_EDI);
860 * mono_arch_regalloc_cost:
862 * Return the cost, in number of memory references, of the action of
863 * allocating the variable VMV into a register during global register
867 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
869 MonoInst *ins = cfg->varinfo [vmv->idx];
871 if (cfg->method->save_lmf)
872 /* The register is already saved */
873 return (ins->opcode == OP_ARG) ? 1 : 0;
875 /* push+pop+possible load if it is an argument */
876 return (ins->opcode == OP_ARG) ? 3 : 2;
880 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
882 static int inited = FALSE;
883 static int count = 0;
885 if (cfg->arch.need_stack_frame_inited) {
886 g_assert (cfg->arch.need_stack_frame == flag);
890 cfg->arch.need_stack_frame = flag;
891 cfg->arch.need_stack_frame_inited = TRUE;
897 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
902 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
906 needs_stack_frame (MonoCompile *cfg)
908 MonoMethodSignature *sig;
909 MonoMethodHeader *header;
910 gboolean result = FALSE;
912 #if defined(__APPLE__)
913 /*OSX requires stack frame code to have the correct alignment. */
917 if (cfg->arch.need_stack_frame_inited)
918 return cfg->arch.need_stack_frame;
920 header = mono_method_get_header (cfg->method);
921 sig = mono_method_signature (cfg->method);
923 if (cfg->disable_omit_fp)
925 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
927 else if (cfg->method->save_lmf)
929 else if (cfg->stack_offset)
931 else if (cfg->param_area)
933 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
935 else if (header->num_clauses)
937 else if (sig->param_count + sig->hasthis)
939 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
941 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
942 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
945 set_needs_stack_frame (cfg, result);
947 return cfg->arch.need_stack_frame;
951 * Set var information according to the calling convention. X86 version.
952 * The locals var stuff should most likely be split in another method.
955 mono_arch_allocate_vars (MonoCompile *cfg)
957 MonoMethodSignature *sig;
958 MonoMethodHeader *header;
960 guint32 locals_stack_size, locals_stack_align;
965 header = mono_method_get_header (cfg->method);
966 sig = mono_method_signature (cfg->method);
968 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
970 cfg->frame_reg = X86_EBP;
973 /* Reserve space to save LMF and caller saved registers */
975 if (cfg->method->save_lmf) {
976 offset += sizeof (MonoLMF);
978 if (cfg->used_int_regs & (1 << X86_EBX)) {
982 if (cfg->used_int_regs & (1 << X86_EDI)) {
986 if (cfg->used_int_regs & (1 << X86_ESI)) {
991 switch (cinfo->ret.storage) {
992 case ArgValuetypeInReg:
993 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
995 cfg->ret->opcode = OP_REGOFFSET;
996 cfg->ret->inst_basereg = X86_EBP;
997 cfg->ret->inst_offset = - offset;
1003 /* Allocate locals */
1004 offsets = mono_allocate_stack_slots (cfg, &locals_stack_size, &locals_stack_align);
1005 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1006 char *mname = mono_method_full_name (cfg->method, TRUE);
1007 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1008 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1012 if (locals_stack_align) {
1013 offset += (locals_stack_align - 1);
1014 offset &= ~(locals_stack_align - 1);
1017 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1018 * have locals larger than 8 bytes we need to make sure that
1019 * they have the appropriate offset.
1021 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1022 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1023 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1024 if (offsets [i] != -1) {
1025 MonoInst *inst = cfg->varinfo [i];
1026 inst->opcode = OP_REGOFFSET;
1027 inst->inst_basereg = X86_EBP;
1028 inst->inst_offset = - (offset + offsets [i]);
1029 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1032 offset += locals_stack_size;
1036 * Allocate arguments+return value
1039 switch (cinfo->ret.storage) {
1041 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1043 * In the new IR, the cfg->vret_addr variable represents the
1044 * vtype return value.
1046 cfg->vret_addr->opcode = OP_REGOFFSET;
1047 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1048 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1049 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1050 printf ("vret_addr =");
1051 mono_print_ins (cfg->vret_addr);
1054 cfg->ret->opcode = OP_REGOFFSET;
1055 cfg->ret->inst_basereg = X86_EBP;
1056 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1059 case ArgValuetypeInReg:
1062 cfg->ret->opcode = OP_REGVAR;
1063 cfg->ret->inst_c0 = cinfo->ret.reg;
1064 cfg->ret->dreg = cinfo->ret.reg;
1067 case ArgOnFloatFpStack:
1068 case ArgOnDoubleFpStack:
1071 g_assert_not_reached ();
1074 if (sig->call_convention == MONO_CALL_VARARG) {
1075 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1076 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1079 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1080 ArgInfo *ainfo = &cinfo->args [i];
1081 inst = cfg->args [i];
1082 if (inst->opcode != OP_REGVAR) {
1083 inst->opcode = OP_REGOFFSET;
1084 inst->inst_basereg = X86_EBP;
1086 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1089 cfg->stack_offset = offset;
1093 mono_arch_create_vars (MonoCompile *cfg)
1095 MonoMethodSignature *sig;
1098 sig = mono_method_signature (cfg->method);
1100 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1102 if (cinfo->ret.storage == ArgValuetypeInReg)
1103 cfg->ret_var_is_local = TRUE;
1104 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1105 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1110 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1111 * so we try to do it just once when we have multiple fp arguments in a row.
1112 * We don't use this mechanism generally because for int arguments the generated code
1113 * is slightly bigger and new generation cpus optimize away the dependency chains
1114 * created by push instructions on the esp value.
1115 * fp_arg_setup is the first argument in the execution sequence where the esp register
1118 static G_GNUC_UNUSED int
1119 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1124 for (; start_arg < sig->param_count; ++start_arg) {
1125 t = mini_type_get_underlying_type (NULL, sig->params [start_arg]);
1126 if (!t->byref && t->type == MONO_TYPE_R8) {
1127 fp_space += sizeof (double);
1128 *fp_arg_setup = start_arg;
1137 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1139 MonoMethodSignature *tmp_sig;
1141 /* FIXME: Add support for signature tokens to AOT */
1142 cfg->disable_aot = TRUE;
1145 * mono_ArgIterator_Setup assumes the signature cookie is
1146 * passed first and all the arguments which were before it are
1147 * passed on the stack after the signature. So compensate by
1148 * passing a different signature.
1150 tmp_sig = mono_metadata_signature_dup (call->signature);
1151 tmp_sig->param_count -= call->signature->sentinelpos;
1152 tmp_sig->sentinelpos = 0;
1153 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1155 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1160 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1165 LLVMCallInfo *linfo;
1167 n = sig->param_count + sig->hasthis;
1169 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1171 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1174 * LLVM always uses the native ABI while we use our own ABI, the
1175 * only difference is the handling of vtypes:
1176 * - we only pass/receive them in registers in some cases, and only
1177 * in 1 or 2 integer registers.
1179 if (cinfo->ret.storage == ArgValuetypeInReg) {
1181 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1182 cfg->disable_llvm = TRUE;
1186 cfg->exception_message = g_strdup ("vtype ret in call");
1187 cfg->disable_llvm = TRUE;
1189 linfo->ret.storage = LLVMArgVtypeInReg;
1190 for (j = 0; j < 2; ++j)
1191 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1195 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1196 /* Vtype returned using a hidden argument */
1197 linfo->ret.storage = LLVMArgVtypeRetAddr;
1200 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != ArgInIReg) {
1202 cfg->exception_message = g_strdup ("vtype ret in call");
1203 cfg->disable_llvm = TRUE;
1206 for (i = 0; i < n; ++i) {
1207 ainfo = cinfo->args + i;
1209 linfo->args [i].storage = LLVMArgNone;
1211 switch (ainfo->storage) {
1213 linfo->args [i].storage = LLVMArgInIReg;
1215 case ArgInDoubleSSEReg:
1216 case ArgInFloatSSEReg:
1217 linfo->args [i].storage = LLVMArgInFPReg;
1220 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1221 linfo->args [i].storage = LLVMArgVtypeByVal;
1223 linfo->args [i].storage = LLVMArgInIReg;
1224 if (!sig->params [i - sig->hasthis]->byref) {
1225 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1226 linfo->args [i].storage = LLVMArgInFPReg;
1227 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1228 linfo->args [i].storage = LLVMArgInFPReg;
1233 case ArgValuetypeInReg:
1235 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1236 cfg->disable_llvm = TRUE;
1240 cfg->exception_message = g_strdup ("vtype arg");
1241 cfg->disable_llvm = TRUE;
1243 linfo->args [i].storage = LLVMArgVtypeInReg;
1244 for (j = 0; j < 2; ++j)
1245 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1249 cfg->exception_message = g_strdup ("ainfo->storage");
1250 cfg->disable_llvm = TRUE;
1260 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1263 MonoMethodSignature *sig;
1266 int sentinelpos = 0;
1268 sig = call->signature;
1269 n = sig->param_count + sig->hasthis;
1271 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1273 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1274 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1276 if (cinfo->need_stack_align) {
1277 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1278 arg->dreg = X86_ESP;
1279 arg->sreg1 = X86_ESP;
1280 arg->inst_imm = cinfo->stack_align_amount;
1281 MONO_ADD_INS (cfg->cbb, arg);
1284 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1285 if (cinfo->ret.storage == ArgValuetypeInReg) {
1287 * Tell the JIT to use a more efficient calling convention: call using
1288 * OP_CALL, compute the result location after the call, and save the
1291 call->vret_in_reg = TRUE;
1293 NULLIFY_INS (call->vret_var);
1297 /* Handle the case where there are no implicit arguments */
1298 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1299 emit_sig_cookie (cfg, call, cinfo);
1302 /* Arguments are pushed in the reverse order */
1303 for (i = n - 1; i >= 0; i --) {
1304 ArgInfo *ainfo = cinfo->args + i;
1307 if (i >= sig->hasthis)
1308 t = sig->params [i - sig->hasthis];
1310 t = &mono_defaults.int_class->byval_arg;
1311 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1313 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1315 in = call->args [i];
1316 arg->cil_code = in->cil_code;
1317 arg->sreg1 = in->dreg;
1318 arg->type = in->type;
1320 g_assert (in->dreg != -1);
1322 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1326 g_assert (in->klass);
1328 if (t->type == MONO_TYPE_TYPEDBYREF) {
1329 size = sizeof (MonoTypedRef);
1330 align = sizeof (gpointer);
1333 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1337 arg->opcode = OP_OUTARG_VT;
1338 arg->sreg1 = in->dreg;
1339 arg->klass = in->klass;
1340 arg->backend.size = size;
1342 MONO_ADD_INS (cfg->cbb, arg);
1346 switch (ainfo->storage) {
1348 arg->opcode = OP_X86_PUSH;
1350 if (t->type == MONO_TYPE_R4) {
1351 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1352 arg->opcode = OP_STORER4_MEMBASE_REG;
1353 arg->inst_destbasereg = X86_ESP;
1354 arg->inst_offset = 0;
1355 } else if (t->type == MONO_TYPE_R8) {
1356 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1357 arg->opcode = OP_STORER8_MEMBASE_REG;
1358 arg->inst_destbasereg = X86_ESP;
1359 arg->inst_offset = 0;
1360 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1362 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1367 g_assert_not_reached ();
1370 MONO_ADD_INS (cfg->cbb, arg);
1373 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1374 /* Emit the signature cookie just before the implicit arguments */
1375 emit_sig_cookie (cfg, call, cinfo);
1379 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1382 if (cinfo->ret.storage == ArgValuetypeInReg) {
1385 else if (cinfo->ret.storage == ArgInIReg) {
1387 /* The return address is passed in a register */
1388 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1389 vtarg->sreg1 = call->inst.dreg;
1390 vtarg->dreg = mono_alloc_ireg (cfg);
1391 MONO_ADD_INS (cfg->cbb, vtarg);
1393 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1396 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1397 vtarg->type = STACK_MP;
1398 vtarg->sreg1 = call->vret_var->dreg;
1399 MONO_ADD_INS (cfg->cbb, vtarg);
1402 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1403 if (cinfo->ret.storage != ArgValuetypeInReg)
1404 cinfo->stack_usage -= 4;
1407 call->stack_usage = cinfo->stack_usage;
1411 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1414 int size = ins->backend.size;
1417 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1418 arg->sreg1 = src->dreg;
1420 MONO_ADD_INS (cfg->cbb, arg);
1421 } else if (size <= 20) {
1422 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1423 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1425 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1426 arg->inst_basereg = src->dreg;
1427 arg->inst_offset = 0;
1428 arg->inst_imm = size;
1430 MONO_ADD_INS (cfg->cbb, arg);
1435 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1437 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1440 if (ret->type == MONO_TYPE_R4) {
1441 if (COMPILE_LLVM (cfg))
1442 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1445 } else if (ret->type == MONO_TYPE_R8) {
1446 if (COMPILE_LLVM (cfg))
1447 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1450 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1451 if (COMPILE_LLVM (cfg))
1452 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1454 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1455 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1461 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1465 * Allow tracing to work with this interface (with an optional argument)
1468 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1472 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1473 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1475 /* if some args are passed in registers, we need to save them here */
1476 x86_push_reg (code, X86_EBP);
1478 if (cfg->compile_aot) {
1479 x86_push_imm (code, cfg->method);
1480 x86_mov_reg_imm (code, X86_EAX, func);
1481 x86_call_reg (code, X86_EAX);
1483 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1484 x86_push_imm (code, cfg->method);
1485 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1486 x86_call_code (code, 0);
1488 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1502 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1505 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1506 MonoMethod *method = cfg->method;
1507 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1509 switch (ret_type->type) {
1510 case MONO_TYPE_VOID:
1511 /* special case string .ctor icall */
1512 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1513 save_mode = SAVE_EAX;
1514 stack_usage = enable_arguments ? 8 : 4;
1516 save_mode = SAVE_NONE;
1520 save_mode = SAVE_EAX_EDX;
1521 stack_usage = enable_arguments ? 16 : 8;
1525 save_mode = SAVE_FP;
1526 stack_usage = enable_arguments ? 16 : 8;
1528 case MONO_TYPE_GENERICINST:
1529 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1530 save_mode = SAVE_EAX;
1531 stack_usage = enable_arguments ? 8 : 4;
1535 case MONO_TYPE_VALUETYPE:
1536 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1537 save_mode = SAVE_STRUCT;
1538 stack_usage = enable_arguments ? 4 : 0;
1541 save_mode = SAVE_EAX;
1542 stack_usage = enable_arguments ? 8 : 4;
1546 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1548 switch (save_mode) {
1550 x86_push_reg (code, X86_EDX);
1551 x86_push_reg (code, X86_EAX);
1552 if (enable_arguments) {
1553 x86_push_reg (code, X86_EDX);
1554 x86_push_reg (code, X86_EAX);
1559 x86_push_reg (code, X86_EAX);
1560 if (enable_arguments) {
1561 x86_push_reg (code, X86_EAX);
1566 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1567 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1568 if (enable_arguments) {
1569 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1570 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1575 if (enable_arguments) {
1576 x86_push_membase (code, X86_EBP, 8);
1585 if (cfg->compile_aot) {
1586 x86_push_imm (code, method);
1587 x86_mov_reg_imm (code, X86_EAX, func);
1588 x86_call_reg (code, X86_EAX);
1590 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1591 x86_push_imm (code, method);
1592 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1593 x86_call_code (code, 0);
1596 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1598 switch (save_mode) {
1600 x86_pop_reg (code, X86_EAX);
1601 x86_pop_reg (code, X86_EDX);
1604 x86_pop_reg (code, X86_EAX);
1607 x86_fld_membase (code, X86_ESP, 0, TRUE);
1608 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1615 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1620 #define EMIT_COND_BRANCH(ins,cond,sign) \
1621 if (ins->inst_true_bb->native_offset) { \
1622 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1624 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1625 if ((cfg->opt & MONO_OPT_BRANCH) && \
1626 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1627 x86_branch8 (code, cond, 0, sign); \
1629 x86_branch32 (code, cond, 0, sign); \
1633 * Emit an exception if condition is fail and
1634 * if possible do a directly branch to target
1636 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1638 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1639 if (tins == NULL) { \
1640 mono_add_patch_info (cfg, code - cfg->native_code, \
1641 MONO_PATCH_INFO_EXC, exc_name); \
1642 x86_branch32 (code, cond, 0, signed); \
1644 EMIT_COND_BRANCH (tins, cond, signed); \
1648 #define EMIT_FPCOMPARE(code) do { \
1649 x86_fcompp (code); \
1650 x86_fnstsw (code); \
1655 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1657 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1658 x86_call_code (code, 0);
1663 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1666 * mono_peephole_pass_1:
1668 * Perform peephole opts which should/can be performed before local regalloc
1671 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1675 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1676 MonoInst *last_ins = ins->prev;
1678 switch (ins->opcode) {
1681 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1683 * X86_LEA is like ADD, but doesn't have the
1684 * sreg1==dreg restriction.
1686 ins->opcode = OP_X86_LEA_MEMBASE;
1687 ins->inst_basereg = ins->sreg1;
1688 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1689 ins->opcode = OP_X86_INC_REG;
1693 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1694 ins->opcode = OP_X86_LEA_MEMBASE;
1695 ins->inst_basereg = ins->sreg1;
1696 ins->inst_imm = -ins->inst_imm;
1697 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1698 ins->opcode = OP_X86_DEC_REG;
1700 case OP_COMPARE_IMM:
1701 case OP_ICOMPARE_IMM:
1702 /* OP_COMPARE_IMM (reg, 0)
1704 * OP_X86_TEST_NULL (reg)
1707 ins->opcode = OP_X86_TEST_NULL;
1709 case OP_X86_COMPARE_MEMBASE_IMM:
1711 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1712 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1714 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1715 * OP_COMPARE_IMM reg, imm
1717 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1719 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1720 ins->inst_basereg == last_ins->inst_destbasereg &&
1721 ins->inst_offset == last_ins->inst_offset) {
1722 ins->opcode = OP_COMPARE_IMM;
1723 ins->sreg1 = last_ins->sreg1;
1725 /* check if we can remove cmp reg,0 with test null */
1727 ins->opcode = OP_X86_TEST_NULL;
1731 case OP_X86_PUSH_MEMBASE:
1732 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1733 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1734 ins->inst_basereg == last_ins->inst_destbasereg &&
1735 ins->inst_offset == last_ins->inst_offset) {
1736 ins->opcode = OP_X86_PUSH;
1737 ins->sreg1 = last_ins->sreg1;
1742 mono_peephole_ins (bb, ins);
1747 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1751 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1752 switch (ins->opcode) {
1754 /* reg = 0 -> XOR (reg, reg) */
1755 /* XOR sets cflags on x86, so we cant do it always */
1756 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
1759 ins->opcode = OP_IXOR;
1760 ins->sreg1 = ins->dreg;
1761 ins->sreg2 = ins->dreg;
1764 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
1765 * since it takes 3 bytes instead of 7.
1767 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
1768 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1769 ins2->opcode = OP_STORE_MEMBASE_REG;
1770 ins2->sreg1 = ins->dreg;
1772 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
1773 ins2->opcode = OP_STOREI4_MEMBASE_REG;
1774 ins2->sreg1 = ins->dreg;
1776 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
1777 /* Continue iteration */
1786 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1787 ins->opcode = OP_X86_INC_REG;
1791 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1792 ins->opcode = OP_X86_DEC_REG;
1796 mono_peephole_ins (bb, ins);
1801 * mono_arch_lowering_pass:
1803 * Converts complex opcodes into simpler ones so that each IR instruction
1804 * corresponds to one machine instruction.
1807 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1809 MonoInst *ins, *next;
1812 * FIXME: Need to add more instructions, but the current machine
1813 * description can't model some parts of the composite instructions like
1816 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
1817 switch (ins->opcode) {
1820 case OP_IDIV_UN_IMM:
1821 case OP_IREM_UN_IMM:
1823 * Keep the cases where we could generated optimized code, otherwise convert
1824 * to the non-imm variant.
1826 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
1828 mono_decompose_op_imm (cfg, bb, ins);
1835 bb->max_vreg = cfg->next_vreg;
1839 branch_cc_table [] = {
1840 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1841 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1842 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1845 /* Maps CMP_... constants to X86_CC_... constants */
1848 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
1849 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
1853 cc_signed_table [] = {
1854 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
1855 FALSE, FALSE, FALSE, FALSE
1858 static unsigned char*
1859 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
1861 #define XMM_TEMP_REG 0
1862 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
1863 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
1864 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
1865 /* optimize by assigning a local var for this use so we avoid
1866 * the stack manipulations */
1867 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1868 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1869 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
1870 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
1871 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1873 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
1875 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
1878 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
1879 x86_fnstcw_membase(code, X86_ESP, 0);
1880 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
1881 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
1882 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
1883 x86_fldcw_membase (code, X86_ESP, 2);
1885 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1886 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
1887 x86_pop_reg (code, dreg);
1888 /* FIXME: need the high register
1889 * x86_pop_reg (code, dreg_high);
1892 x86_push_reg (code, X86_EAX); // SP = SP - 4
1893 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
1894 x86_pop_reg (code, dreg);
1896 x86_fldcw_membase (code, X86_ESP, 0);
1897 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
1900 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
1902 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
1906 static unsigned char*
1907 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
1909 int sreg = tree->sreg1;
1910 int need_touch = FALSE;
1912 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
1921 * If requested stack size is larger than one page,
1922 * perform stack-touch operation
1925 * Generate stack probe code.
1926 * Under Windows, it is necessary to allocate one page at a time,
1927 * "touching" stack after each successful sub-allocation. This is
1928 * because of the way stack growth is implemented - there is a
1929 * guard page before the lowest stack page that is currently commited.
1930 * Stack normally grows sequentially so OS traps access to the
1931 * guard page and commits more pages when needed.
1933 x86_test_reg_imm (code, sreg, ~0xFFF);
1934 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1936 br[2] = code; /* loop */
1937 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
1938 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
1941 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
1942 * that follows only initializes the last part of the area.
1944 /* Same as the init code below with size==0x1000 */
1945 if (tree->flags & MONO_INST_INIT) {
1946 x86_push_reg (code, X86_EAX);
1947 x86_push_reg (code, X86_ECX);
1948 x86_push_reg (code, X86_EDI);
1949 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
1950 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
1951 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
1953 x86_prefix (code, X86_REP_PREFIX);
1955 x86_pop_reg (code, X86_EDI);
1956 x86_pop_reg (code, X86_ECX);
1957 x86_pop_reg (code, X86_EAX);
1960 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
1961 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
1962 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
1963 x86_patch (br[3], br[2]);
1964 x86_test_reg_reg (code, sreg, sreg);
1965 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1966 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
1968 br[1] = code; x86_jump8 (code, 0);
1970 x86_patch (br[0], code);
1971 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
1972 x86_patch (br[1], code);
1973 x86_patch (br[4], code);
1976 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
1978 if (tree->flags & MONO_INST_INIT) {
1980 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
1981 x86_push_reg (code, X86_EAX);
1984 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
1985 x86_push_reg (code, X86_ECX);
1988 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
1989 x86_push_reg (code, X86_EDI);
1993 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
1994 if (sreg != X86_ECX)
1995 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
1996 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
1998 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2000 x86_prefix (code, X86_REP_PREFIX);
2003 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2004 x86_pop_reg (code, X86_EDI);
2005 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2006 x86_pop_reg (code, X86_ECX);
2007 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2008 x86_pop_reg (code, X86_EAX);
2015 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2017 /* Move return value to the target register */
2018 switch (ins->opcode) {
2021 case OP_CALL_MEMBASE:
2022 if (ins->dreg != X86_EAX)
2023 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2033 * mono_x86_emit_tls_get:
2034 * @code: buffer to store code to
2035 * @dreg: hard register where to place the result
2036 * @tls_offset: offset info
2038 * mono_x86_emit_tls_get emits in @code the native code that puts in
2039 * the dreg register the item in the thread local storage identified
2042 * Returns: a pointer to the end of the stored code
2045 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2049 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2050 * Journal and/or a disassembly of the TlsGet () function.
2052 g_assert (tls_offset < 64);
2053 x86_prefix (code, X86_FS_PREFIX);
2054 x86_mov_reg_mem (code, dreg, 0x18, 4);
2055 /* Dunno what this does but TlsGetValue () contains it */
2056 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2057 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2059 if (optimize_for_xen) {
2060 x86_prefix (code, X86_GS_PREFIX);
2061 x86_mov_reg_mem (code, dreg, 0, 4);
2062 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2064 x86_prefix (code, X86_GS_PREFIX);
2065 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2072 * emit_load_volatile_arguments:
2074 * Load volatile arguments from the stack to the original input registers.
2075 * Required before a tail call.
2078 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2080 MonoMethod *method = cfg->method;
2081 MonoMethodSignature *sig;
2086 /* FIXME: Generate intermediate code instead */
2088 sig = mono_method_signature (method);
2090 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
2092 /* This is the opposite of the code in emit_prolog */
2094 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2095 ArgInfo *ainfo = cinfo->args + i;
2097 inst = cfg->args [i];
2099 if (sig->hasthis && (i == 0))
2100 arg_type = &mono_defaults.object_class->byval_arg;
2102 arg_type = sig->params [i - sig->hasthis];
2105 * On x86, the arguments are either in their original stack locations, or in
2108 if (inst->opcode == OP_REGVAR) {
2109 g_assert (ainfo->storage == ArgOnStack);
2111 x86_mov_membase_reg (code, X86_EBP, inst->inst_offset, inst->dreg, 4);
2118 #define REAL_PRINT_REG(text,reg) \
2119 mono_assert (reg >= 0); \
2120 x86_push_reg (code, X86_EAX); \
2121 x86_push_reg (code, X86_EDX); \
2122 x86_push_reg (code, X86_ECX); \
2123 x86_push_reg (code, reg); \
2124 x86_push_imm (code, reg); \
2125 x86_push_imm (code, text " %d %p\n"); \
2126 x86_mov_reg_imm (code, X86_EAX, printf); \
2127 x86_call_reg (code, X86_EAX); \
2128 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2129 x86_pop_reg (code, X86_ECX); \
2130 x86_pop_reg (code, X86_EDX); \
2131 x86_pop_reg (code, X86_EAX);
2133 /* benchmark and set based on cpu */
2134 #define LOOP_ALIGNMENT 8
2135 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2140 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2145 guint8 *code = cfg->native_code + cfg->code_len;
2148 if (cfg->opt & MONO_OPT_LOOP) {
2149 int pad, align = LOOP_ALIGNMENT;
2150 /* set alignment depending on cpu */
2151 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2153 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2154 x86_padding (code, pad);
2155 cfg->code_len += pad;
2156 bb->native_offset = cfg->code_len;
2160 if (cfg->verbose_level > 2)
2161 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2163 cpos = bb->max_offset;
2165 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2166 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2167 g_assert (!cfg->compile_aot);
2170 cov->data [bb->dfn].cil_code = bb->cil_code;
2171 /* this is not thread save, but good enough */
2172 x86_inc_mem (code, &cov->data [bb->dfn].count);
2175 offset = code - cfg->native_code;
2177 mono_debug_open_block (cfg, bb, offset);
2179 MONO_BB_FOR_EACH_INS (bb, ins) {
2180 offset = code - cfg->native_code;
2182 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2184 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2185 cfg->code_size *= 2;
2186 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2187 code = cfg->native_code + offset;
2188 mono_jit_stats.code_reallocs++;
2191 if (cfg->debug_info)
2192 mono_debug_record_line_number (cfg, ins, offset);
2194 switch (ins->opcode) {
2196 x86_mul_reg (code, ins->sreg2, TRUE);
2199 x86_mul_reg (code, ins->sreg2, FALSE);
2201 case OP_X86_SETEQ_MEMBASE:
2202 case OP_X86_SETNE_MEMBASE:
2203 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2204 ins->inst_basereg, ins->inst_offset, TRUE);
2206 case OP_STOREI1_MEMBASE_IMM:
2207 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2209 case OP_STOREI2_MEMBASE_IMM:
2210 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2212 case OP_STORE_MEMBASE_IMM:
2213 case OP_STOREI4_MEMBASE_IMM:
2214 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2216 case OP_STOREI1_MEMBASE_REG:
2217 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2219 case OP_STOREI2_MEMBASE_REG:
2220 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2222 case OP_STORE_MEMBASE_REG:
2223 case OP_STOREI4_MEMBASE_REG:
2224 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2226 case OP_STORE_MEM_IMM:
2227 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2230 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2234 /* These are created by the cprop pass so they use inst_imm as the source */
2235 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2238 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2241 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2243 case OP_LOAD_MEMBASE:
2244 case OP_LOADI4_MEMBASE:
2245 case OP_LOADU4_MEMBASE:
2246 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2248 case OP_LOADU1_MEMBASE:
2249 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2251 case OP_LOADI1_MEMBASE:
2252 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2254 case OP_LOADU2_MEMBASE:
2255 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2257 case OP_LOADI2_MEMBASE:
2258 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2260 case OP_ICONV_TO_I1:
2262 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2264 case OP_ICONV_TO_I2:
2266 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2268 case OP_ICONV_TO_U1:
2269 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2271 case OP_ICONV_TO_U2:
2272 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2276 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2278 case OP_COMPARE_IMM:
2279 case OP_ICOMPARE_IMM:
2280 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2282 case OP_X86_COMPARE_MEMBASE_REG:
2283 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2285 case OP_X86_COMPARE_MEMBASE_IMM:
2286 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2288 case OP_X86_COMPARE_MEMBASE8_IMM:
2289 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2291 case OP_X86_COMPARE_REG_MEMBASE:
2292 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2294 case OP_X86_COMPARE_MEM_IMM:
2295 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2297 case OP_X86_TEST_NULL:
2298 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2300 case OP_X86_ADD_MEMBASE_IMM:
2301 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2303 case OP_X86_ADD_REG_MEMBASE:
2304 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2306 case OP_X86_SUB_MEMBASE_IMM:
2307 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2309 case OP_X86_SUB_REG_MEMBASE:
2310 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2312 case OP_X86_AND_MEMBASE_IMM:
2313 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2315 case OP_X86_OR_MEMBASE_IMM:
2316 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2318 case OP_X86_XOR_MEMBASE_IMM:
2319 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2321 case OP_X86_ADD_MEMBASE_REG:
2322 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2324 case OP_X86_SUB_MEMBASE_REG:
2325 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2327 case OP_X86_AND_MEMBASE_REG:
2328 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2330 case OP_X86_OR_MEMBASE_REG:
2331 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2333 case OP_X86_XOR_MEMBASE_REG:
2334 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2336 case OP_X86_INC_MEMBASE:
2337 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2339 case OP_X86_INC_REG:
2340 x86_inc_reg (code, ins->dreg);
2342 case OP_X86_DEC_MEMBASE:
2343 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2345 case OP_X86_DEC_REG:
2346 x86_dec_reg (code, ins->dreg);
2348 case OP_X86_MUL_REG_MEMBASE:
2349 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2351 case OP_X86_AND_REG_MEMBASE:
2352 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2354 case OP_X86_OR_REG_MEMBASE:
2355 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2357 case OP_X86_XOR_REG_MEMBASE:
2358 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2361 x86_breakpoint (code);
2363 case OP_RELAXED_NOP:
2364 x86_prefix (code, X86_REP_PREFIX);
2372 case OP_DUMMY_STORE:
2373 case OP_NOT_REACHED:
2376 case OP_SEQ_POINT: {
2379 if (cfg->compile_aot)
2383 * Read from the single stepping trigger page. This will cause a
2384 * SIGSEGV when single stepping is enabled.
2385 * We do this _before_ the breakpoint, so single stepping after
2386 * a breakpoint is hit will step to the next IL offset.
2388 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2389 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2391 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2394 * A placeholder for a possible breakpoint inserted by
2395 * mono_arch_set_breakpoint ().
2397 for (i = 0; i < 6; ++i)
2404 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2408 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2413 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2417 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2422 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2426 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2431 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2435 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2438 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2442 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2447 * The code is the same for div/rem, the allocator will allocate dreg
2448 * to RAX/RDX as appropriate.
2450 if (ins->sreg2 == X86_EDX) {
2451 /* cdq clobbers this */
2452 x86_push_reg (code, ins->sreg2);
2454 x86_div_membase (code, X86_ESP, 0, TRUE);
2455 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2458 x86_div_reg (code, ins->sreg2, TRUE);
2463 if (ins->sreg2 == X86_EDX) {
2464 x86_push_reg (code, ins->sreg2);
2465 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2466 x86_div_membase (code, X86_ESP, 0, FALSE);
2467 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2469 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2470 x86_div_reg (code, ins->sreg2, FALSE);
2474 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2476 x86_div_reg (code, ins->sreg2, TRUE);
2479 int power = mono_is_power_of_two (ins->inst_imm);
2481 g_assert (ins->sreg1 == X86_EAX);
2482 g_assert (ins->dreg == X86_EAX);
2483 g_assert (power >= 0);
2486 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2488 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2490 * If the divident is >= 0, this does not nothing. If it is positive, it
2491 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2493 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2494 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2495 } else if (power == 0) {
2496 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2498 /* Based on gcc code */
2500 /* Add compensation for negative dividents */
2502 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2503 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2504 /* Compute remainder */
2505 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2506 /* Remove compensation */
2507 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2512 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2516 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2519 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2523 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2526 g_assert (ins->sreg2 == X86_ECX);
2527 x86_shift_reg (code, X86_SHL, ins->dreg);
2530 g_assert (ins->sreg2 == X86_ECX);
2531 x86_shift_reg (code, X86_SAR, ins->dreg);
2535 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2538 case OP_ISHR_UN_IMM:
2539 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2542 g_assert (ins->sreg2 == X86_ECX);
2543 x86_shift_reg (code, X86_SHR, ins->dreg);
2547 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2550 guint8 *jump_to_end;
2552 /* handle shifts below 32 bits */
2553 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2554 x86_shift_reg (code, X86_SHL, ins->sreg1);
2556 x86_test_reg_imm (code, X86_ECX, 32);
2557 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2559 /* handle shift over 32 bit */
2560 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2561 x86_clear_reg (code, ins->sreg1);
2563 x86_patch (jump_to_end, code);
2567 guint8 *jump_to_end;
2569 /* handle shifts below 32 bits */
2570 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2571 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2573 x86_test_reg_imm (code, X86_ECX, 32);
2574 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2576 /* handle shifts over 31 bits */
2577 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2578 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2580 x86_patch (jump_to_end, code);
2584 guint8 *jump_to_end;
2586 /* handle shifts below 32 bits */
2587 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2588 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2590 x86_test_reg_imm (code, X86_ECX, 32);
2591 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2593 /* handle shifts over 31 bits */
2594 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2595 x86_clear_reg (code, ins->backend.reg3);
2597 x86_patch (jump_to_end, code);
2601 if (ins->inst_imm >= 32) {
2602 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2603 x86_clear_reg (code, ins->sreg1);
2604 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2606 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2607 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2611 if (ins->inst_imm >= 32) {
2612 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2613 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2614 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2616 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2617 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2620 case OP_LSHR_UN_IMM:
2621 if (ins->inst_imm >= 32) {
2622 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2623 x86_clear_reg (code, ins->backend.reg3);
2624 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2626 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2627 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2631 x86_not_reg (code, ins->sreg1);
2634 x86_neg_reg (code, ins->sreg1);
2638 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2642 switch (ins->inst_imm) {
2646 if (ins->dreg != ins->sreg1)
2647 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2648 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2651 /* LEA r1, [r2 + r2*2] */
2652 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2655 /* LEA r1, [r2 + r2*4] */
2656 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2659 /* LEA r1, [r2 + r2*2] */
2661 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2662 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2665 /* LEA r1, [r2 + r2*8] */
2666 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2669 /* LEA r1, [r2 + r2*4] */
2671 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2672 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2675 /* LEA r1, [r2 + r2*2] */
2677 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2678 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2681 /* LEA r1, [r2 + r2*4] */
2682 /* LEA r1, [r1 + r1*4] */
2683 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2684 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2687 /* LEA r1, [r2 + r2*4] */
2689 /* LEA r1, [r1 + r1*4] */
2690 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2691 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2692 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2695 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2700 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2701 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2703 case OP_IMUL_OVF_UN: {
2704 /* the mul operation and the exception check should most likely be split */
2705 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2706 /*g_assert (ins->sreg2 == X86_EAX);
2707 g_assert (ins->dreg == X86_EAX);*/
2708 if (ins->sreg2 == X86_EAX) {
2709 non_eax_reg = ins->sreg1;
2710 } else if (ins->sreg1 == X86_EAX) {
2711 non_eax_reg = ins->sreg2;
2713 /* no need to save since we're going to store to it anyway */
2714 if (ins->dreg != X86_EAX) {
2716 x86_push_reg (code, X86_EAX);
2718 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
2719 non_eax_reg = ins->sreg2;
2721 if (ins->dreg == X86_EDX) {
2724 x86_push_reg (code, X86_EAX);
2726 } else if (ins->dreg != X86_EAX) {
2728 x86_push_reg (code, X86_EDX);
2730 x86_mul_reg (code, non_eax_reg, FALSE);
2731 /* save before the check since pop and mov don't change the flags */
2732 if (ins->dreg != X86_EAX)
2733 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2735 x86_pop_reg (code, X86_EDX);
2737 x86_pop_reg (code, X86_EAX);
2738 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2742 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
2745 g_assert_not_reached ();
2746 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2747 x86_mov_reg_imm (code, ins->dreg, 0);
2750 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2751 x86_mov_reg_imm (code, ins->dreg, 0);
2753 case OP_LOAD_GOTADDR:
2754 x86_call_imm (code, 0);
2756 * The patch needs to point to the pop, since the GOT offset needs
2757 * to be added to that address.
2759 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
2760 x86_pop_reg (code, ins->dreg);
2761 x86_alu_reg_imm (code, X86_ADD, ins->dreg, 0xf0f0f0f0);
2764 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2765 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
2767 case OP_X86_PUSH_GOT_ENTRY:
2768 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
2769 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
2772 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2776 * Note: this 'frame destruction' logic is useful for tail calls, too.
2777 * Keep in sync with the code in emit_epilog.
2781 /* FIXME: no tracing support... */
2782 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2783 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2784 /* reset offset to make max_len work */
2785 offset = code - cfg->native_code;
2787 g_assert (!cfg->method->save_lmf);
2789 code = emit_load_volatile_arguments (cfg, code);
2791 if (cfg->used_int_regs & (1 << X86_EBX))
2793 if (cfg->used_int_regs & (1 << X86_EDI))
2795 if (cfg->used_int_regs & (1 << X86_ESI))
2798 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
2800 if (cfg->used_int_regs & (1 << X86_ESI))
2801 x86_pop_reg (code, X86_ESI);
2802 if (cfg->used_int_regs & (1 << X86_EDI))
2803 x86_pop_reg (code, X86_EDI);
2804 if (cfg->used_int_regs & (1 << X86_EBX))
2805 x86_pop_reg (code, X86_EBX);
2807 /* restore ESP/EBP */
2809 offset = code - cfg->native_code;
2810 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2811 x86_jump32 (code, 0);
2813 cfg->disable_aot = TRUE;
2817 /* ensure ins->sreg1 is not NULL
2818 * note that cmp DWORD PTR [eax], eax is one byte shorter than
2819 * cmp DWORD PTR [eax], 0
2821 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
2824 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
2825 x86_push_reg (code, hreg);
2826 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
2827 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
2828 x86_pop_reg (code, hreg);
2837 call = (MonoCallInst*)ins;
2838 if (ins->flags & MONO_INST_HAS_METHOD)
2839 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2841 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2842 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
2843 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
2844 * bytes to pop, we want to use pops. GCC does this (note it won't happen
2845 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
2846 * smart enough to do that optimization yet
2848 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
2849 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
2850 * (most likely from locality benefits). People with other processors should
2851 * check on theirs to see what happens.
2853 if (call->stack_usage == 4) {
2854 /* we want to use registers that won't get used soon, so use
2855 * ecx, as eax will get allocated first. edx is used by long calls,
2856 * so we can't use that.
2859 x86_pop_reg (code, X86_ECX);
2861 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2864 code = emit_move_return_value (cfg, ins, code);
2870 case OP_VOIDCALL_REG:
2872 call = (MonoCallInst*)ins;
2873 x86_call_reg (code, ins->sreg1);
2874 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
2875 if (call->stack_usage == 4)
2876 x86_pop_reg (code, X86_ECX);
2878 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2880 code = emit_move_return_value (cfg, ins, code);
2882 case OP_FCALL_MEMBASE:
2883 case OP_LCALL_MEMBASE:
2884 case OP_VCALL_MEMBASE:
2885 case OP_VCALL2_MEMBASE:
2886 case OP_VOIDCALL_MEMBASE:
2887 case OP_CALL_MEMBASE:
2888 call = (MonoCallInst*)ins;
2891 * Emit a few nops to simplify get_vcall_slot ().
2897 x86_call_membase (code, ins->sreg1, ins->inst_offset);
2898 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
2899 if (call->stack_usage == 4)
2900 x86_pop_reg (code, X86_ECX);
2902 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2904 code = emit_move_return_value (cfg, ins, code);
2907 x86_push_reg (code, ins->sreg1);
2909 case OP_X86_PUSH_IMM:
2910 x86_push_imm (code, ins->inst_imm);
2912 case OP_X86_PUSH_MEMBASE:
2913 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
2915 case OP_X86_PUSH_OBJ:
2916 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
2917 x86_push_reg (code, X86_EDI);
2918 x86_push_reg (code, X86_ESI);
2919 x86_push_reg (code, X86_ECX);
2920 if (ins->inst_offset)
2921 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
2923 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
2924 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2925 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
2927 x86_prefix (code, X86_REP_PREFIX);
2929 x86_pop_reg (code, X86_ECX);
2930 x86_pop_reg (code, X86_ESI);
2931 x86_pop_reg (code, X86_EDI);
2934 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
2936 case OP_X86_LEA_MEMBASE:
2937 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
2940 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
2943 /* keep alignment */
2944 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
2945 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
2946 code = mono_emit_stack_alloc (code, ins);
2947 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2949 case OP_LOCALLOC_IMM: {
2950 guint32 size = ins->inst_imm;
2951 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
2953 if (ins->flags & MONO_INST_INIT) {
2954 /* FIXME: Optimize this */
2955 x86_mov_reg_imm (code, ins->dreg, size);
2956 ins->sreg1 = ins->dreg;
2958 code = mono_emit_stack_alloc (code, ins);
2959 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2961 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
2962 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2967 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
2968 x86_push_reg (code, ins->sreg1);
2969 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
2970 (gpointer)"mono_arch_throw_exception");
2974 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
2975 x86_push_reg (code, ins->sreg1);
2976 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
2977 (gpointer)"mono_arch_rethrow_exception");
2980 case OP_CALL_HANDLER:
2981 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
2982 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2983 x86_call_imm (code, 0);
2984 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
2986 case OP_START_HANDLER: {
2987 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
2988 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
2991 case OP_ENDFINALLY: {
2992 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
2993 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
2997 case OP_ENDFILTER: {
2998 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
2999 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3000 /* The local allocator will put the result into EAX */
3006 ins->inst_c0 = code - cfg->native_code;
3009 if (ins->inst_target_bb->native_offset) {
3010 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3012 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3013 if ((cfg->opt & MONO_OPT_BRANCH) &&
3014 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3015 x86_jump8 (code, 0);
3017 x86_jump32 (code, 0);
3021 x86_jump_reg (code, ins->sreg1);
3034 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3035 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3037 case OP_COND_EXC_EQ:
3038 case OP_COND_EXC_NE_UN:
3039 case OP_COND_EXC_LT:
3040 case OP_COND_EXC_LT_UN:
3041 case OP_COND_EXC_GT:
3042 case OP_COND_EXC_GT_UN:
3043 case OP_COND_EXC_GE:
3044 case OP_COND_EXC_GE_UN:
3045 case OP_COND_EXC_LE:
3046 case OP_COND_EXC_LE_UN:
3047 case OP_COND_EXC_IEQ:
3048 case OP_COND_EXC_INE_UN:
3049 case OP_COND_EXC_ILT:
3050 case OP_COND_EXC_ILT_UN:
3051 case OP_COND_EXC_IGT:
3052 case OP_COND_EXC_IGT_UN:
3053 case OP_COND_EXC_IGE:
3054 case OP_COND_EXC_IGE_UN:
3055 case OP_COND_EXC_ILE:
3056 case OP_COND_EXC_ILE_UN:
3057 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3059 case OP_COND_EXC_OV:
3060 case OP_COND_EXC_NO:
3062 case OP_COND_EXC_NC:
3063 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3065 case OP_COND_EXC_IOV:
3066 case OP_COND_EXC_INO:
3067 case OP_COND_EXC_IC:
3068 case OP_COND_EXC_INC:
3069 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3081 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3089 case OP_CMOV_INE_UN:
3090 case OP_CMOV_IGE_UN:
3091 case OP_CMOV_IGT_UN:
3092 case OP_CMOV_ILE_UN:
3093 case OP_CMOV_ILT_UN:
3094 g_assert (ins->dreg == ins->sreg1);
3095 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3098 /* floating point opcodes */
3100 double d = *(double *)ins->inst_p0;
3102 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3104 } else if (d == 1.0) {
3107 if (cfg->compile_aot) {
3108 guint32 *val = (guint32*)&d;
3109 x86_push_imm (code, val [1]);
3110 x86_push_imm (code, val [0]);
3111 x86_fld_membase (code, X86_ESP, 0, TRUE);
3112 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3115 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3116 x86_fld (code, NULL, TRUE);
3122 float f = *(float *)ins->inst_p0;
3124 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3126 } else if (f == 1.0) {
3129 if (cfg->compile_aot) {
3130 guint32 val = *(guint32*)&f;
3131 x86_push_imm (code, val);
3132 x86_fld_membase (code, X86_ESP, 0, FALSE);
3133 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3136 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3137 x86_fld (code, NULL, FALSE);
3142 case OP_STORER8_MEMBASE_REG:
3143 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3145 case OP_LOADR8_MEMBASE:
3146 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3148 case OP_STORER4_MEMBASE_REG:
3149 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3151 case OP_LOADR4_MEMBASE:
3152 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3154 case OP_ICONV_TO_R4:
3155 x86_push_reg (code, ins->sreg1);
3156 x86_fild_membase (code, X86_ESP, 0, FALSE);
3157 /* Change precision */
3158 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3159 x86_fld_membase (code, X86_ESP, 0, FALSE);
3160 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3162 case OP_ICONV_TO_R8:
3163 x86_push_reg (code, ins->sreg1);
3164 x86_fild_membase (code, X86_ESP, 0, FALSE);
3165 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3167 case OP_ICONV_TO_R_UN:
3168 x86_push_imm (code, 0);
3169 x86_push_reg (code, ins->sreg1);
3170 x86_fild_membase (code, X86_ESP, 0, TRUE);
3171 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3173 case OP_X86_FP_LOAD_I8:
3174 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3176 case OP_X86_FP_LOAD_I4:
3177 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3179 case OP_FCONV_TO_R4:
3180 /* Change precision */
3181 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3182 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3183 x86_fld_membase (code, X86_ESP, 0, FALSE);
3184 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3186 case OP_FCONV_TO_I1:
3187 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3189 case OP_FCONV_TO_U1:
3190 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3192 case OP_FCONV_TO_I2:
3193 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3195 case OP_FCONV_TO_U2:
3196 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3198 case OP_FCONV_TO_I4:
3200 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3202 case OP_FCONV_TO_I8:
3203 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3204 x86_fnstcw_membase(code, X86_ESP, 0);
3205 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3206 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3207 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3208 x86_fldcw_membase (code, X86_ESP, 2);
3209 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3210 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3211 x86_pop_reg (code, ins->dreg);
3212 x86_pop_reg (code, ins->backend.reg3);
3213 x86_fldcw_membase (code, X86_ESP, 0);
3214 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3216 case OP_LCONV_TO_R8_2:
3217 x86_push_reg (code, ins->sreg2);
3218 x86_push_reg (code, ins->sreg1);
3219 x86_fild_membase (code, X86_ESP, 0, TRUE);
3220 /* Change precision */
3221 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3222 x86_fld_membase (code, X86_ESP, 0, TRUE);
3223 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3225 case OP_LCONV_TO_R4_2:
3226 x86_push_reg (code, ins->sreg2);
3227 x86_push_reg (code, ins->sreg1);
3228 x86_fild_membase (code, X86_ESP, 0, TRUE);
3229 /* Change precision */
3230 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3231 x86_fld_membase (code, X86_ESP, 0, FALSE);
3232 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3234 case OP_LCONV_TO_R_UN_2: {
3235 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3238 /* load 64bit integer to FP stack */
3239 x86_push_reg (code, ins->sreg2);
3240 x86_push_reg (code, ins->sreg1);
3241 x86_fild_membase (code, X86_ESP, 0, TRUE);
3243 /* test if lreg is negative */
3244 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3245 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3247 /* add correction constant mn */
3248 x86_fld80_mem (code, mn);
3249 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3251 x86_patch (br, code);
3253 /* Change precision */
3254 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3255 x86_fld_membase (code, X86_ESP, 0, TRUE);
3257 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3261 case OP_LCONV_TO_OVF_I:
3262 case OP_LCONV_TO_OVF_I4_2: {
3263 guint8 *br [3], *label [1];
3267 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3269 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3271 /* If the low word top bit is set, see if we are negative */
3272 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3273 /* We are not negative (no top bit set, check for our top word to be zero */
3274 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3275 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3278 /* throw exception */
3279 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3281 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3282 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3283 x86_jump8 (code, 0);
3285 x86_jump32 (code, 0);
3287 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3288 x86_jump32 (code, 0);
3292 x86_patch (br [0], code);
3293 /* our top bit is set, check that top word is 0xfffffff */
3294 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3296 x86_patch (br [1], code);
3297 /* nope, emit exception */
3298 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3299 x86_patch (br [2], label [0]);
3301 if (ins->dreg != ins->sreg1)
3302 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3306 /* Not needed on the fp stack */
3309 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3312 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3315 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3318 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3326 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3331 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3338 * it really doesn't make sense to inline all this code,
3339 * it's here just to show that things may not be as simple
3342 guchar *check_pos, *end_tan, *pop_jump;
3343 x86_push_reg (code, X86_EAX);
3346 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3348 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3349 x86_fstp (code, 0); /* pop the 1.0 */
3351 x86_jump8 (code, 0);
3353 x86_fp_op (code, X86_FADD, 0);
3357 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3359 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3362 x86_patch (pop_jump, code);
3363 x86_fstp (code, 0); /* pop the 1.0 */
3364 x86_patch (check_pos, code);
3365 x86_patch (end_tan, code);
3367 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3368 x86_pop_reg (code, X86_EAX);
3375 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3384 g_assert (cfg->opt & MONO_OPT_CMOV);
3385 g_assert (ins->dreg == ins->sreg1);
3386 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3387 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3390 g_assert (cfg->opt & MONO_OPT_CMOV);
3391 g_assert (ins->dreg == ins->sreg1);
3392 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3393 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3396 g_assert (cfg->opt & MONO_OPT_CMOV);
3397 g_assert (ins->dreg == ins->sreg1);
3398 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3399 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3402 g_assert (cfg->opt & MONO_OPT_CMOV);
3403 g_assert (ins->dreg == ins->sreg1);
3404 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3405 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3411 x86_fxch (code, ins->inst_imm);
3416 x86_push_reg (code, X86_EAX);
3417 /* we need to exchange ST(0) with ST(1) */
3420 /* this requires a loop, because fprem somtimes
3421 * returns a partial remainder */
3423 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3424 /* x86_fprem1 (code); */
3427 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3429 x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3434 x86_pop_reg (code, X86_EAX);
3438 if (cfg->opt & MONO_OPT_FCMOV) {
3439 x86_fcomip (code, 1);
3443 /* this overwrites EAX */
3444 EMIT_FPCOMPARE(code);
3445 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3448 if (cfg->opt & MONO_OPT_FCMOV) {
3449 /* zeroing the register at the start results in
3450 * shorter and faster code (we can also remove the widening op)
3452 guchar *unordered_check;
3453 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3454 x86_fcomip (code, 1);
3456 unordered_check = code;
3457 x86_branch8 (code, X86_CC_P, 0, FALSE);
3458 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3459 x86_patch (unordered_check, code);
3462 if (ins->dreg != X86_EAX)
3463 x86_push_reg (code, X86_EAX);
3465 EMIT_FPCOMPARE(code);
3466 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3467 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3468 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3469 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3471 if (ins->dreg != X86_EAX)
3472 x86_pop_reg (code, X86_EAX);
3476 if (cfg->opt & MONO_OPT_FCMOV) {
3477 /* zeroing the register at the start results in
3478 * shorter and faster code (we can also remove the widening op)
3480 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3481 x86_fcomip (code, 1);
3483 if (ins->opcode == OP_FCLT_UN) {
3484 guchar *unordered_check = code;
3485 guchar *jump_to_end;
3486 x86_branch8 (code, X86_CC_P, 0, FALSE);
3487 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3489 x86_jump8 (code, 0);
3490 x86_patch (unordered_check, code);
3491 x86_inc_reg (code, ins->dreg);
3492 x86_patch (jump_to_end, code);
3494 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3498 if (ins->dreg != X86_EAX)
3499 x86_push_reg (code, X86_EAX);
3501 EMIT_FPCOMPARE(code);
3502 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3503 if (ins->opcode == OP_FCLT_UN) {
3504 guchar *is_not_zero_check, *end_jump;
3505 is_not_zero_check = code;
3506 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3508 x86_jump8 (code, 0);
3509 x86_patch (is_not_zero_check, code);
3510 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3512 x86_patch (end_jump, code);
3514 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3515 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3517 if (ins->dreg != X86_EAX)
3518 x86_pop_reg (code, X86_EAX);
3522 if (cfg->opt & MONO_OPT_FCMOV) {
3523 /* zeroing the register at the start results in
3524 * shorter and faster code (we can also remove the widening op)
3526 guchar *unordered_check;
3527 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3528 x86_fcomip (code, 1);
3530 if (ins->opcode == OP_FCGT) {
3531 unordered_check = code;
3532 x86_branch8 (code, X86_CC_P, 0, FALSE);
3533 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3534 x86_patch (unordered_check, code);
3536 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3540 if (ins->dreg != X86_EAX)
3541 x86_push_reg (code, X86_EAX);
3543 EMIT_FPCOMPARE(code);
3544 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3545 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3546 if (ins->opcode == OP_FCGT_UN) {
3547 guchar *is_not_zero_check, *end_jump;
3548 is_not_zero_check = code;
3549 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3551 x86_jump8 (code, 0);
3552 x86_patch (is_not_zero_check, code);
3553 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3555 x86_patch (end_jump, code);
3557 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3558 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3560 if (ins->dreg != X86_EAX)
3561 x86_pop_reg (code, X86_EAX);
3564 if (cfg->opt & MONO_OPT_FCMOV) {
3565 guchar *jump = code;
3566 x86_branch8 (code, X86_CC_P, 0, TRUE);
3567 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3568 x86_patch (jump, code);
3571 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3572 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3575 /* Branch if C013 != 100 */
3576 if (cfg->opt & MONO_OPT_FCMOV) {
3577 /* branch if !ZF or (PF|CF) */
3578 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3579 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3580 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3583 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3584 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3587 if (cfg->opt & MONO_OPT_FCMOV) {
3588 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3591 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3594 if (cfg->opt & MONO_OPT_FCMOV) {
3595 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3596 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3599 if (ins->opcode == OP_FBLT_UN) {
3600 guchar *is_not_zero_check, *end_jump;
3601 is_not_zero_check = code;
3602 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3604 x86_jump8 (code, 0);
3605 x86_patch (is_not_zero_check, code);
3606 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3608 x86_patch (end_jump, code);
3610 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3614 if (cfg->opt & MONO_OPT_FCMOV) {
3615 if (ins->opcode == OP_FBGT) {
3618 /* skip branch if C1=1 */
3620 x86_branch8 (code, X86_CC_P, 0, FALSE);
3621 /* branch if (C0 | C3) = 1 */
3622 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3623 x86_patch (br1, code);
3625 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3629 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3630 if (ins->opcode == OP_FBGT_UN) {
3631 guchar *is_not_zero_check, *end_jump;
3632 is_not_zero_check = code;
3633 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3635 x86_jump8 (code, 0);
3636 x86_patch (is_not_zero_check, code);
3637 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3639 x86_patch (end_jump, code);
3641 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3644 /* Branch if C013 == 100 or 001 */
3645 if (cfg->opt & MONO_OPT_FCMOV) {
3648 /* skip branch if C1=1 */
3650 x86_branch8 (code, X86_CC_P, 0, FALSE);
3651 /* branch if (C0 | C3) = 1 */
3652 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3653 x86_patch (br1, code);
3656 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3657 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3658 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3659 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3662 /* Branch if C013 == 000 */
3663 if (cfg->opt & MONO_OPT_FCMOV) {
3664 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3667 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3670 /* Branch if C013=000 or 100 */
3671 if (cfg->opt & MONO_OPT_FCMOV) {
3674 /* skip branch if C1=1 */
3676 x86_branch8 (code, X86_CC_P, 0, FALSE);
3677 /* branch if C0=0 */
3678 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3679 x86_patch (br1, code);
3682 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
3683 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
3684 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3687 /* Branch if C013 != 001 */
3688 if (cfg->opt & MONO_OPT_FCMOV) {
3689 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3690 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3693 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3694 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3698 x86_push_reg (code, X86_EAX);
3701 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
3702 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3703 x86_pop_reg (code, X86_EAX);
3705 /* Have to clean up the fp stack before throwing the exception */
3707 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3710 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3712 x86_patch (br1, code);
3716 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
3719 case OP_MEMORY_BARRIER: {
3720 /* Not needed on x86 */
3723 case OP_ATOMIC_ADD_I4: {
3724 int dreg = ins->dreg;
3726 if (dreg == ins->inst_basereg) {
3727 x86_push_reg (code, ins->sreg2);
3731 if (dreg != ins->sreg2)
3732 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
3734 x86_prefix (code, X86_LOCK_PREFIX);
3735 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
3737 if (dreg != ins->dreg) {
3738 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
3739 x86_pop_reg (code, dreg);
3744 case OP_ATOMIC_ADD_NEW_I4: {
3745 int dreg = ins->dreg;
3747 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
3748 if (ins->sreg2 == dreg) {
3749 if (dreg == X86_EBX) {
3751 if (ins->inst_basereg == X86_EDI)
3755 if (ins->inst_basereg == X86_EBX)
3758 } else if (ins->inst_basereg == dreg) {
3759 if (dreg == X86_EBX) {
3761 if (ins->sreg2 == X86_EDI)
3765 if (ins->sreg2 == X86_EBX)
3770 if (dreg != ins->dreg) {
3771 x86_push_reg (code, dreg);
3774 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
3775 x86_prefix (code, X86_LOCK_PREFIX);
3776 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
3777 /* dreg contains the old value, add with sreg2 value */
3778 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
3780 if (ins->dreg != dreg) {
3781 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
3782 x86_pop_reg (code, dreg);
3787 case OP_ATOMIC_EXCHANGE_I4: {
3789 int sreg2 = ins->sreg2;
3790 int breg = ins->inst_basereg;
3792 /* cmpxchg uses eax as comperand, need to make sure we can use it
3793 * hack to overcome limits in x86 reg allocator
3794 * (req: dreg == eax and sreg2 != eax and breg != eax)
3796 g_assert (ins->dreg == X86_EAX);
3798 /* We need the EAX reg for the cmpxchg */
3799 if (ins->sreg2 == X86_EAX) {
3800 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
3801 x86_push_reg (code, sreg2);
3802 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
3805 if (breg == X86_EAX) {
3806 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
3807 x86_push_reg (code, breg);
3808 x86_mov_reg_reg (code, breg, X86_EAX, 4);
3811 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
3813 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
3814 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
3815 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
3816 x86_patch (br [1], br [0]);
3818 if (breg != ins->inst_basereg)
3819 x86_pop_reg (code, breg);
3821 if (ins->sreg2 != sreg2)
3822 x86_pop_reg (code, sreg2);
3826 case OP_ATOMIC_CAS_I4: {
3827 g_assert (ins->sreg3 == X86_EAX);
3828 g_assert (ins->sreg1 != X86_EAX);
3829 g_assert (ins->sreg1 != ins->sreg2);
3831 x86_prefix (code, X86_LOCK_PREFIX);
3832 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
3834 if (ins->dreg != X86_EAX)
3835 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3838 #ifdef MONO_ARCH_SIMD_INTRINSICS
3840 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
3843 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
3846 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
3849 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
3852 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
3855 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
3858 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
3859 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
3862 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
3865 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
3868 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
3871 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
3874 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
3877 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
3880 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
3883 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
3886 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
3889 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
3892 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
3895 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
3898 case OP_PSHUFLEW_HIGH:
3899 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
3900 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
3902 case OP_PSHUFLEW_LOW:
3903 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
3904 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
3907 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
3908 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
3912 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
3915 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
3918 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
3921 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
3924 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
3927 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
3930 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
3931 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
3934 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
3937 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
3940 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
3943 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
3946 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
3949 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
3952 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
3955 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
3958 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
3961 case OP_EXTRACT_MASK:
3962 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
3966 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
3969 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
3972 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
3976 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
3979 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
3982 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
3985 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
3989 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
3992 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
3995 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
3998 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4002 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4005 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4008 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4012 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4015 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4018 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4022 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4025 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4029 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4032 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4035 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4039 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4042 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4045 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4049 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4052 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4055 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4058 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4062 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4065 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4068 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4071 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4074 case OP_PSUM_ABS_DIFF:
4075 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4078 case OP_UNPACK_LOWB:
4079 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4081 case OP_UNPACK_LOWW:
4082 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4084 case OP_UNPACK_LOWD:
4085 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4087 case OP_UNPACK_LOWQ:
4088 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4090 case OP_UNPACK_LOWPS:
4091 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4093 case OP_UNPACK_LOWPD:
4094 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4097 case OP_UNPACK_HIGHB:
4098 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4100 case OP_UNPACK_HIGHW:
4101 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4103 case OP_UNPACK_HIGHD:
4104 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4106 case OP_UNPACK_HIGHQ:
4107 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4109 case OP_UNPACK_HIGHPS:
4110 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4112 case OP_UNPACK_HIGHPD:
4113 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4117 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4120 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4123 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4126 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4129 case OP_PADDB_SAT_UN:
4130 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4132 case OP_PSUBB_SAT_UN:
4133 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4135 case OP_PADDW_SAT_UN:
4136 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4138 case OP_PSUBW_SAT_UN:
4139 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4143 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4146 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4149 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4152 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4156 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4159 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4162 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4164 case OP_PMULW_HIGH_UN:
4165 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4168 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4172 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4175 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4179 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4182 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4186 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4189 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4193 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4196 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4200 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4203 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4207 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4210 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4214 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4217 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4221 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4224 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4228 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4231 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4235 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4237 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4238 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4242 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4244 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4245 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4249 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4251 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4252 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4256 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4258 case OP_EXTRACTX_U2:
4259 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4261 case OP_INSERTX_U1_SLOW:
4262 /*sreg1 is the extracted ireg (scratch)
4263 /sreg2 is the to be inserted ireg (scratch)
4264 /dreg is the xreg to receive the value*/
4266 /*clear the bits from the extracted word*/
4267 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4268 /*shift the value to insert if needed*/
4269 if (ins->inst_c0 & 1)
4270 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4271 /*join them together*/
4272 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4273 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4275 case OP_INSERTX_I4_SLOW:
4276 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4277 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4278 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4281 case OP_INSERTX_R4_SLOW:
4282 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4283 /*TODO if inst_c0 == 0 use movss*/
4284 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4285 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4287 case OP_INSERTX_R8_SLOW:
4288 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4290 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4292 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVSD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4295 case OP_STOREX_MEMBASE_REG:
4296 case OP_STOREX_MEMBASE:
4297 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4299 case OP_LOADX_MEMBASE:
4300 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4302 case OP_LOADX_ALIGNED_MEMBASE:
4303 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4305 case OP_STOREX_ALIGNED_MEMBASE_REG:
4306 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4308 case OP_STOREX_NTA_MEMBASE_REG:
4309 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4311 case OP_PREFETCH_MEMBASE:
4312 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4316 /*FIXME the peephole pass should have killed this*/
4317 if (ins->dreg != ins->sreg1)
4318 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4321 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4323 case OP_ICONV_TO_R8_RAW:
4324 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4325 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4328 case OP_FCONV_TO_R8_X:
4329 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4330 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4333 case OP_XCONV_R8_TO_I4:
4334 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4335 switch (ins->backend.source_opcode) {
4336 case OP_FCONV_TO_I1:
4337 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4339 case OP_FCONV_TO_U1:
4340 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4342 case OP_FCONV_TO_I2:
4343 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4345 case OP_FCONV_TO_U2:
4346 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4352 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4353 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4354 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4355 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4356 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4357 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4360 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4361 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4362 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4365 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4366 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4369 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4370 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4371 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4374 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4375 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4376 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4379 case OP_LIVERANGE_START: {
4380 if (cfg->verbose_level > 1)
4381 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4382 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4385 case OP_LIVERANGE_END: {
4386 if (cfg->verbose_level > 1)
4387 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4388 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4392 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4393 g_assert_not_reached ();
4396 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4397 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4398 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4399 g_assert_not_reached ();
4405 cfg->code_len = code - cfg->native_code;
4408 #endif /* DISABLE_JIT */
4411 mono_arch_register_lowlevel_calls (void)
4416 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4418 MonoJumpInfo *patch_info;
4419 gboolean compile_aot = !run_cctors;
4421 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4422 unsigned char *ip = patch_info->ip.i + code;
4423 const unsigned char *target;
4425 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4428 switch (patch_info->type) {
4429 case MONO_PATCH_INFO_BB:
4430 case MONO_PATCH_INFO_LABEL:
4433 /* No need to patch these */
4438 switch (patch_info->type) {
4439 case MONO_PATCH_INFO_IP:
4440 *((gconstpointer *)(ip)) = target;
4442 case MONO_PATCH_INFO_CLASS_INIT: {
4444 /* Might already been changed to a nop */
4445 x86_call_code (code, 0);
4446 x86_patch (ip, target);
4449 case MONO_PATCH_INFO_ABS:
4450 case MONO_PATCH_INFO_METHOD:
4451 case MONO_PATCH_INFO_METHOD_JUMP:
4452 case MONO_PATCH_INFO_INTERNAL_METHOD:
4453 case MONO_PATCH_INFO_BB:
4454 case MONO_PATCH_INFO_LABEL:
4455 case MONO_PATCH_INFO_RGCTX_FETCH:
4456 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
4457 case MONO_PATCH_INFO_MONITOR_ENTER:
4458 case MONO_PATCH_INFO_MONITOR_EXIT:
4459 x86_patch (ip, target);
4461 case MONO_PATCH_INFO_NONE:
4464 guint32 offset = mono_arch_get_patch_offset (ip);
4465 *((gconstpointer *)(ip + offset)) = target;
4473 mono_arch_emit_prolog (MonoCompile *cfg)
4475 MonoMethod *method = cfg->method;
4477 MonoMethodSignature *sig;
4479 int alloc_size, pos, max_offset, i, cfa_offset;
4481 gboolean need_stack_frame;
4483 cfg->code_size = MAX (mono_method_get_header (method)->code_size * 4, 10240);
4485 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4486 cfg->code_size += 512;
4488 code = cfg->native_code = g_malloc (cfg->code_size);
4490 /* Offset between RSP and the CFA */
4494 cfa_offset = sizeof (gpointer);
4495 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
4496 // IP saved at CFA - 4
4497 /* There is no IP reg on x86 */
4498 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
4500 need_stack_frame = needs_stack_frame (cfg);
4502 if (need_stack_frame) {
4503 x86_push_reg (code, X86_EBP);
4504 cfa_offset += sizeof (gpointer);
4505 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
4506 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
4507 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
4508 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
4511 alloc_size = cfg->stack_offset;
4514 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4515 /* Might need to attach the thread to the JIT or change the domain for the callback */
4516 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4517 guint8 *buf, *no_domain_branch;
4519 code = mono_x86_emit_tls_get (code, X86_EAX, appdomain_tls_offset);
4520 x86_alu_reg_imm (code, X86_CMP, X86_EAX, GPOINTER_TO_UINT (cfg->domain));
4521 no_domain_branch = code;
4522 x86_branch8 (code, X86_CC_NE, 0, 0);
4523 code = mono_x86_emit_tls_get ( code, X86_EAX, lmf_tls_offset);
4524 x86_test_reg_reg (code, X86_EAX, X86_EAX);
4526 x86_branch8 (code, X86_CC_NE, 0, 0);
4527 x86_patch (no_domain_branch, code);
4528 x86_push_imm (code, cfg->domain);
4529 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4530 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
4531 x86_patch (buf, code);
4533 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4534 /* FIXME: Add a separate key for LMF to avoid this */
4535 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4539 g_assert (!cfg->compile_aot);
4540 x86_push_imm (code, cfg->domain);
4541 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4542 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
4546 if (method->save_lmf) {
4547 pos += sizeof (MonoLMF);
4549 if (cfg->compile_aot)
4550 cfg->disable_aot = TRUE;
4552 /* save the current IP */
4553 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
4554 x86_push_imm_template (code);
4555 cfa_offset += sizeof (gpointer);
4557 /* save all caller saved regs */
4558 x86_push_reg (code, X86_EBP);
4559 cfa_offset += sizeof (gpointer);
4560 x86_push_reg (code, X86_ESI);
4561 cfa_offset += sizeof (gpointer);
4562 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
4563 x86_push_reg (code, X86_EDI);
4564 cfa_offset += sizeof (gpointer);
4565 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
4566 x86_push_reg (code, X86_EBX);
4567 cfa_offset += sizeof (gpointer);
4568 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
4570 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
4572 * Optimized version which uses the mono_lmf TLS variable instead of indirection
4573 * through the mono_lmf_addr TLS variable.
4575 /* %eax = previous_lmf */
4576 x86_prefix (code, X86_GS_PREFIX);
4577 x86_mov_reg_mem (code, X86_EAX, lmf_tls_offset, 4);
4578 /* skip esp + method_info + lmf */
4579 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 12);
4580 /* push previous_lmf */
4581 x86_push_reg (code, X86_EAX);
4583 x86_prefix (code, X86_GS_PREFIX);
4584 x86_mov_mem_reg (code, lmf_tls_offset, X86_ESP, 4);
4586 /* get the address of lmf for the current thread */
4588 * This is performance critical so we try to use some tricks to make
4592 if (lmf_addr_tls_offset != -1) {
4593 /* Load lmf quicky using the GS register */
4594 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
4596 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
4597 /* FIXME: Add a separate key for LMF to avoid this */
4598 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
4601 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
4604 /* Skip esp + method info */
4605 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
4608 x86_push_reg (code, X86_EAX);
4609 /* push *lfm (previous_lmf) */
4610 x86_push_membase (code, X86_EAX, 0);
4612 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
4616 if (cfg->used_int_regs & (1 << X86_EBX)) {
4617 x86_push_reg (code, X86_EBX);
4619 cfa_offset += sizeof (gpointer);
4620 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
4623 if (cfg->used_int_regs & (1 << X86_EDI)) {
4624 x86_push_reg (code, X86_EDI);
4626 cfa_offset += sizeof (gpointer);
4627 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
4630 if (cfg->used_int_regs & (1 << X86_ESI)) {
4631 x86_push_reg (code, X86_ESI);
4633 cfa_offset += sizeof (gpointer);
4634 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
4640 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
4641 if (mono_do_x86_stack_align && need_stack_frame) {
4642 int tot = alloc_size + pos + 4; /* ret ip */
4643 if (need_stack_frame)
4645 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
4647 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
4651 /* See mono_emit_stack_alloc */
4652 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4653 guint32 remaining_size = alloc_size;
4654 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
4655 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
4656 guint32 offset = code - cfg->native_code;
4657 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
4658 while (required_code_size >= (cfg->code_size - offset))
4659 cfg->code_size *= 2;
4660 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4661 code = cfg->native_code + offset;
4662 mono_jit_stats.code_reallocs++;
4664 while (remaining_size >= 0x1000) {
4665 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
4666 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
4667 remaining_size -= 0x1000;
4670 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
4672 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
4675 g_assert (need_stack_frame);
4678 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
4679 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
4680 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
4683 #if DEBUG_STACK_ALIGNMENT
4684 /* check the stack is aligned */
4685 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
4686 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
4687 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
4688 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
4689 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
4690 x86_breakpoint (code);
4694 /* compute max_offset in order to use short forward jumps */
4696 if (cfg->opt & MONO_OPT_BRANCH) {
4697 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4699 bb->max_offset = max_offset;
4701 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4703 /* max alignment for loops */
4704 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4705 max_offset += LOOP_ALIGNMENT;
4707 MONO_BB_FOR_EACH_INS (bb, ins) {
4708 if (ins->opcode == OP_LABEL)
4709 ins->inst_c1 = max_offset;
4711 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4716 /* store runtime generic context */
4717 if (cfg->rgctx_var) {
4718 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
4720 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
4723 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4724 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4726 /* load arguments allocated to register from the stack */
4727 sig = mono_method_signature (method);
4730 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4731 inst = cfg->args [pos];
4732 if (inst->opcode == OP_REGVAR) {
4733 g_assert (need_stack_frame);
4734 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
4735 if (cfg->verbose_level > 2)
4736 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
4741 cfg->code_len = code - cfg->native_code;
4743 g_assert (cfg->code_len < cfg->code_size);
4749 mono_arch_emit_epilog (MonoCompile *cfg)
4751 MonoMethod *method = cfg->method;
4752 MonoMethodSignature *sig = mono_method_signature (method);
4754 guint32 stack_to_pop;
4756 int max_epilog_size = 16;
4758 gboolean need_stack_frame = needs_stack_frame (cfg);
4760 if (cfg->method->save_lmf)
4761 max_epilog_size += 128;
4763 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4764 cfg->code_size *= 2;
4765 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4766 mono_jit_stats.code_reallocs++;
4769 code = cfg->native_code + cfg->code_len;
4771 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4772 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4774 /* the code restoring the registers must be kept in sync with OP_JMP */
4777 if (method->save_lmf) {
4778 gint32 prev_lmf_reg;
4779 gint32 lmf_offset = -sizeof (MonoLMF);
4781 /* check if we need to restore protection of the stack after a stack overflow */
4782 if (mono_get_jit_tls_offset () != -1) {
4784 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
4785 /* we load the value in a separate instruction: this mechanism may be
4786 * used later as a safer way to do thread interruption
4788 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
4789 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
4791 x86_branch8 (code, X86_CC_Z, 0, FALSE);
4792 /* note that the call trampoline will preserve eax/edx */
4793 x86_call_reg (code, X86_ECX);
4794 x86_patch (patch, code);
4796 /* FIXME: maybe save the jit tls in the prolog */
4798 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
4800 * Optimized version which uses the mono_lmf TLS variable instead of indirection
4801 * through the mono_lmf_addr TLS variable.
4803 /* reg = previous_lmf */
4804 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
4806 /* lmf = previous_lmf */
4807 x86_prefix (code, X86_GS_PREFIX);
4808 x86_mov_mem_reg (code, lmf_tls_offset, X86_ECX, 4);
4810 /* Find a spare register */
4811 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
4814 prev_lmf_reg = X86_EDI;
4815 cfg->used_int_regs |= (1 << X86_EDI);
4818 prev_lmf_reg = X86_EDX;
4822 /* reg = previous_lmf */
4823 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
4826 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
4828 /* *(lmf) = previous_lmf */
4829 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
4832 /* restore caller saved regs */
4833 if (cfg->used_int_regs & (1 << X86_EBX)) {
4834 x86_mov_reg_membase (code, X86_EBX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
4837 if (cfg->used_int_regs & (1 << X86_EDI)) {
4838 x86_mov_reg_membase (code, X86_EDI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
4840 if (cfg->used_int_regs & (1 << X86_ESI)) {
4841 x86_mov_reg_membase (code, X86_ESI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
4844 /* EBP is restored by LEAVE */
4846 if (cfg->used_int_regs & (1 << X86_EBX)) {
4849 if (cfg->used_int_regs & (1 << X86_EDI)) {
4852 if (cfg->used_int_regs & (1 << X86_ESI)) {
4857 g_assert (need_stack_frame);
4858 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
4861 if (cfg->used_int_regs & (1 << X86_ESI)) {
4862 x86_pop_reg (code, X86_ESI);
4864 if (cfg->used_int_regs & (1 << X86_EDI)) {
4865 x86_pop_reg (code, X86_EDI);
4867 if (cfg->used_int_regs & (1 << X86_EBX)) {
4868 x86_pop_reg (code, X86_EBX);
4872 /* Load returned vtypes into registers if needed */
4873 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
4874 if (cinfo->ret.storage == ArgValuetypeInReg) {
4875 for (quad = 0; quad < 2; quad ++) {
4876 switch (cinfo->ret.pair_storage [quad]) {
4878 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
4880 case ArgOnFloatFpStack:
4881 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
4883 case ArgOnDoubleFpStack:
4884 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
4889 g_assert_not_reached ();
4894 if (need_stack_frame)
4897 if (CALLCONV_IS_STDCALL (sig)) {
4898 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
4900 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
4901 } else if (MONO_TYPE_ISSTRUCT (mono_method_signature (cfg->method)->ret) && (cinfo->ret.storage == ArgOnStack))
4907 g_assert (need_stack_frame);
4908 x86_ret_imm (code, stack_to_pop);
4913 cfg->code_len = code - cfg->native_code;
4915 g_assert (cfg->code_len < cfg->code_size);
4919 mono_arch_emit_exceptions (MonoCompile *cfg)
4921 MonoJumpInfo *patch_info;
4924 MonoClass *exc_classes [16];
4925 guint8 *exc_throw_start [16], *exc_throw_end [16];
4929 /* Compute needed space */
4930 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4931 if (patch_info->type == MONO_PATCH_INFO_EXC)
4936 * make sure we have enough space for exceptions
4937 * 16 is the size of two push_imm instructions and a call
4939 if (cfg->compile_aot)
4940 code_size = exc_count * 32;
4942 code_size = exc_count * 16;
4944 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4945 cfg->code_size *= 2;
4946 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4947 mono_jit_stats.code_reallocs++;
4950 code = cfg->native_code + cfg->code_len;
4953 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4954 switch (patch_info->type) {
4955 case MONO_PATCH_INFO_EXC: {
4956 MonoClass *exc_class;
4960 x86_patch (patch_info->ip.i + cfg->native_code, code);
4962 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4963 g_assert (exc_class);
4964 throw_ip = patch_info->ip.i;
4966 /* Find a throw sequence for the same exception class */
4967 for (i = 0; i < nthrows; ++i)
4968 if (exc_classes [i] == exc_class)
4971 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
4972 x86_jump_code (code, exc_throw_start [i]);
4973 patch_info->type = MONO_PATCH_INFO_NONE;
4978 /* Compute size of code following the push <OFFSET> */
4981 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
4983 if ((code - cfg->native_code) - throw_ip < 126 - size) {
4984 /* Use the shorter form */
4986 x86_push_imm (code, 0);
4990 x86_push_imm (code, 0xf0f0f0f0);
4995 exc_classes [nthrows] = exc_class;
4996 exc_throw_start [nthrows] = code;
4999 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5000 patch_info->data.name = "mono_arch_throw_corlib_exception";
5001 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5002 patch_info->ip.i = code - cfg->native_code;
5003 x86_call_code (code, 0);
5004 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5009 exc_throw_end [nthrows] = code;
5021 cfg->code_len = code - cfg->native_code;
5023 g_assert (cfg->code_len < cfg->code_size);
5027 mono_arch_flush_icache (guint8 *code, gint size)
5033 mono_arch_flush_register_windows (void)
5038 mono_arch_is_inst_imm (gint64 imm)
5044 * Support for fast access to the thread-local lmf structure using the GS
5045 * segment register on NPTL + kernel 2.6.x.
5048 static gboolean tls_offset_inited = FALSE;
5051 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5053 if (!tls_offset_inited) {
5054 if (!getenv ("MONO_NO_TLS")) {
5057 * We need to init this multiple times, since when we are first called, the key might not
5058 * be initialized yet.
5060 appdomain_tls_offset = mono_domain_get_tls_key ();
5061 lmf_tls_offset = mono_get_jit_tls_key ();
5063 /* Only 64 tls entries can be accessed using inline code */
5064 if (appdomain_tls_offset >= 64)
5065 appdomain_tls_offset = -1;
5066 if (lmf_tls_offset >= 64)
5067 lmf_tls_offset = -1;
5070 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5072 tls_offset_inited = TRUE;
5073 appdomain_tls_offset = mono_domain_get_tls_offset ();
5074 lmf_tls_offset = mono_get_lmf_tls_offset ();
5075 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5082 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5086 #ifdef MONO_ARCH_HAVE_IMT
5088 // Linear handler, the bsearch head compare is shorter
5089 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5090 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5091 // x86_patch(ins,target)
5092 //[1 + 5] x86_jump_mem(inst,mem)
5095 #define BR_SMALL_SIZE 2
5096 #define BR_LARGE_SIZE 5
5097 #define JUMP_IMM_SIZE 6
5098 #define ENABLE_WRONG_METHOD_CHECK 0
5102 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5104 int i, distance = 0;
5105 for (i = start; i < target; ++i)
5106 distance += imt_entries [i]->chunk_size;
5111 * LOCKING: called with the domain lock held
5114 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5115 gpointer fail_tramp)
5119 guint8 *code, *start;
5121 for (i = 0; i < count; ++i) {
5122 MonoIMTCheckItem *item = imt_entries [i];
5123 if (item->is_equals) {
5124 if (item->check_target_idx) {
5125 if (!item->compare_done)
5126 item->chunk_size += CMP_SIZE;
5127 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5130 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5132 item->chunk_size += JUMP_IMM_SIZE;
5133 #if ENABLE_WRONG_METHOD_CHECK
5134 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5139 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5140 imt_entries [item->check_target_idx]->compare_done = TRUE;
5142 size += item->chunk_size;
5145 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5147 code = mono_domain_code_reserve (domain, size);
5149 for (i = 0; i < count; ++i) {
5150 MonoIMTCheckItem *item = imt_entries [i];
5151 item->code_target = code;
5152 if (item->is_equals) {
5153 if (item->check_target_idx) {
5154 if (!item->compare_done)
5155 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5156 item->jmp_code = code;
5157 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5158 if (item->has_target_code)
5159 x86_jump_code (code, item->value.target_code);
5161 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5164 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5165 item->jmp_code = code;
5166 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5167 if (item->has_target_code)
5168 x86_jump_code (code, item->value.target_code);
5170 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5171 x86_patch (item->jmp_code, code);
5172 x86_jump_code (code, fail_tramp);
5173 item->jmp_code = NULL;
5175 /* enable the commented code to assert on wrong method */
5176 #if ENABLE_WRONG_METHOD_CHECK
5177 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5178 item->jmp_code = code;
5179 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5181 if (item->has_target_code)
5182 x86_jump_code (code, item->value.target_code);
5184 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5185 #if ENABLE_WRONG_METHOD_CHECK
5186 x86_patch (item->jmp_code, code);
5187 x86_breakpoint (code);
5188 item->jmp_code = NULL;
5193 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5194 item->jmp_code = code;
5195 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5196 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5198 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5201 /* patch the branches to get to the target items */
5202 for (i = 0; i < count; ++i) {
5203 MonoIMTCheckItem *item = imt_entries [i];
5204 if (item->jmp_code) {
5205 if (item->check_target_idx) {
5206 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5212 mono_stats.imt_thunks_size += code - start;
5213 g_assert (code - start <= size);
5217 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5218 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5227 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5229 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5234 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5236 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5240 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5242 MonoInst *ins = NULL;
5245 if (cmethod->klass == mono_defaults.math_class) {
5246 if (strcmp (cmethod->name, "Sin") == 0) {
5248 } else if (strcmp (cmethod->name, "Cos") == 0) {
5250 } else if (strcmp (cmethod->name, "Tan") == 0) {
5252 } else if (strcmp (cmethod->name, "Atan") == 0) {
5254 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5256 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5258 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5263 MONO_INST_NEW (cfg, ins, opcode);
5264 ins->type = STACK_R8;
5265 ins->dreg = mono_alloc_freg (cfg);
5266 ins->sreg1 = args [0]->dreg;
5267 MONO_ADD_INS (cfg->cbb, ins);
5270 if (cfg->opt & MONO_OPT_CMOV) {
5273 if (strcmp (cmethod->name, "Min") == 0) {
5274 if (fsig->params [0]->type == MONO_TYPE_I4)
5276 } else if (strcmp (cmethod->name, "Max") == 0) {
5277 if (fsig->params [0]->type == MONO_TYPE_I4)
5282 MONO_INST_NEW (cfg, ins, opcode);
5283 ins->type = STACK_I4;
5284 ins->dreg = mono_alloc_ireg (cfg);
5285 ins->sreg1 = args [0]->dreg;
5286 ins->sreg2 = args [1]->dreg;
5287 MONO_ADD_INS (cfg->cbb, ins);
5292 /* OP_FREM is not IEEE compatible */
5293 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5294 MONO_INST_NEW (cfg, ins, OP_FREM);
5295 ins->inst_i0 = args [0];
5296 ins->inst_i1 = args [1];
5305 mono_arch_print_tree (MonoInst *tree, int arity)
5310 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5316 if (appdomain_tls_offset == -1)
5319 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5320 ins->inst_offset = appdomain_tls_offset;
5325 mono_arch_get_patch_offset (guint8 *code)
5327 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5329 else if ((code [0] == 0xba))
5331 else if ((code [0] == 0x68))
5334 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5335 /* push <OFFSET>(<REG>) */
5337 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5338 /* call *<OFFSET>(<REG>) */
5340 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5343 else if ((code [0] == 0x58) && (code [1] == 0x05))
5344 /* pop %eax; add <OFFSET>, %eax */
5346 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5347 /* pop <REG>; add <OFFSET>, <REG> */
5349 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5350 /* mov <REG>, imm */
5353 g_assert_not_reached ();
5359 * mono_breakpoint_clean_code:
5361 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5362 * breakpoints in the original code, they are removed in the copy.
5364 * Returns TRUE if no sw breakpoint was present.
5367 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5370 gboolean can_write = TRUE;
5372 * If method_start is non-NULL we need to perform bound checks, since we access memory
5373 * at code - offset we could go before the start of the method and end up in a different
5374 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5377 if (!method_start || code - offset >= method_start) {
5378 memcpy (buf, code - offset, size);
5380 int diff = code - method_start;
5381 memset (buf, 0, size);
5382 memcpy (buf + offset - diff, method_start, diff + size - offset);
5385 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5386 int idx = mono_breakpoint_info_index [i];
5390 ptr = mono_breakpoint_info [idx].address;
5391 if (ptr >= code && ptr < code + size) {
5392 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5394 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5395 buf [ptr - code] = saved_byte;
5402 mono_arch_get_vcall_slot (guint8 *code, mgreg_t *regs, int *displacement)
5408 mono_breakpoint_clean_code (NULL, code, 8, buf, sizeof (buf));
5416 * A given byte sequence can match more than case here, so we have to be
5417 * really careful about the ordering of the cases. Longer sequences
5419 * There are two types of calls:
5420 * - direct calls: 0xff address_byte 8/32 bits displacement
5421 * - indirect calls: nop nop nop <call>
5422 * The nops make sure we don't confuse the instruction preceeding an indirect
5423 * call with a direct call.
5425 if ((code [1] != 0xe8) && (code [3] == 0xff) && ((code [4] & 0x18) == 0x10) && ((code [4] >> 6) == 1)) {
5426 reg = code [4] & 0x07;
5427 disp = (signed char)code [5];
5428 } else if ((code [0] == 0xff) && ((code [1] & 0x18) == 0x10) && ((code [1] >> 6) == 2)) {
5429 reg = code [1] & 0x07;
5430 disp = *((gint32*)(code + 2));
5431 } else if ((code [1] == 0xe8)) {
5433 } else if ((code [4] == 0xff) && (((code [5] >> 6) & 0x3) == 0) && (((code [5] >> 3) & 0x7) == 2)) {
5435 * This is a interface call
5436 * 8b 40 30 mov 0x30(%eax),%eax
5437 * ff 10 call *(%eax)
5440 reg = code [5] & 0x07;
5445 *displacement = disp;
5446 return (gpointer)regs [reg];
5450 * mono_x86_get_this_arg_offset:
5452 * Return the offset of the stack location where this is passed during a virtual
5456 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
5458 CallInfo *cinfo = NULL;
5461 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5462 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5464 offset = cinfo->args [0].offset;
5473 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig,
5474 mgreg_t *regs, guint8 *code)
5476 guint32 esp = regs [X86_ESP];
5477 CallInfo *cinfo = NULL;
5482 * Avoid expensive calls to get_generic_context_from_code () + get_call_info
5485 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5487 gsctx = mono_get_generic_context_from_code (code);
5488 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5490 offset = cinfo->args [0].offset;
5496 * The stack looks like:
5499 * <possible vtype return address>
5501 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
5503 res = (((MonoObject**)esp) [5 + (offset / 4)]);
5509 #define MAX_ARCH_DELEGATE_PARAMS 10
5512 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5514 guint8 *code, *start;
5516 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5519 /* FIXME: Support more cases */
5520 if (MONO_TYPE_ISSTRUCT (sig->ret))
5524 * The stack contains:
5530 static guint8* cached = NULL;
5534 start = code = mono_global_codeman_reserve (64);
5536 /* Replace the this argument with the target */
5537 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
5538 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
5539 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
5540 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5542 g_assert ((code - start) < 64);
5544 mono_debug_add_delegate_trampoline (start, code - start);
5546 mono_memory_barrier ();
5550 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5552 /* 8 for mov_reg and jump, plus 8 for each parameter */
5553 int code_reserve = 8 + (sig->param_count * 8);
5555 for (i = 0; i < sig->param_count; ++i)
5556 if (!mono_is_regsize_var (sig->params [i]))
5559 code = cache [sig->param_count];
5564 * The stack contains:
5565 * <args in reverse order>
5570 * <args in reverse order>
5573 * without unbalancing the stack.
5574 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
5575 * and leaving original spot of first arg as placeholder in stack so
5576 * when callee pops stack everything works.
5579 start = code = mono_global_codeman_reserve (code_reserve);
5581 /* store delegate for access to method_ptr */
5582 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
5585 for (i = 0; i < sig->param_count; ++i) {
5586 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
5587 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
5590 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5592 g_assert ((code - start) < code_reserve);
5594 mono_debug_add_delegate_trampoline (start, code - start);
5596 mono_memory_barrier ();
5598 cache [sig->param_count] = start;
5605 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5608 case X86_EAX: return (gpointer)ctx->eax;
5609 case X86_EBX: return (gpointer)ctx->ebx;
5610 case X86_ECX: return (gpointer)ctx->ecx;
5611 case X86_EDX: return (gpointer)ctx->edx;
5612 case X86_ESP: return (gpointer)ctx->esp;
5613 case X86_EBP: return (gpointer)ctx->ebp;
5614 case X86_ESI: return (gpointer)ctx->esi;
5615 case X86_EDI: return (gpointer)ctx->edi;
5616 default: g_assert_not_reached ();
5620 #ifdef MONO_ARCH_SIMD_INTRINSICS
5623 get_float_to_x_spill_area (MonoCompile *cfg)
5625 if (!cfg->fconv_to_r8_x_var) {
5626 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
5627 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
5629 return cfg->fconv_to_r8_x_var;
5633 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
5636 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
5639 int dreg, src_opcode;
5641 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
5644 switch (src_opcode = ins->opcode) {
5645 case OP_FCONV_TO_I1:
5646 case OP_FCONV_TO_U1:
5647 case OP_FCONV_TO_I2:
5648 case OP_FCONV_TO_U2:
5649 case OP_FCONV_TO_I4:
5656 /* dreg is the IREG and sreg1 is the FREG */
5657 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
5658 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
5659 fconv->sreg1 = ins->sreg1;
5660 fconv->dreg = mono_alloc_ireg (cfg);
5661 fconv->type = STACK_VTYPE;
5662 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
5664 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
5668 ins->opcode = OP_XCONV_R8_TO_I4;
5670 ins->klass = mono_defaults.int32_class;
5671 ins->sreg1 = fconv->dreg;
5673 ins->type = STACK_I4;
5674 ins->backend.source_opcode = src_opcode;
5677 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
5680 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
5685 if (long_ins->opcode == OP_LNEG) {
5687 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
5688 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
5689 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
5694 #ifdef MONO_ARCH_SIMD_INTRINSICS
5696 if (!(cfg->opt & MONO_OPT_SIMD))
5699 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
5700 switch (long_ins->opcode) {
5702 vreg = long_ins->sreg1;
5704 if (long_ins->inst_c0) {
5705 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
5706 ins->klass = long_ins->klass;
5707 ins->sreg1 = long_ins->sreg1;
5709 ins->type = STACK_VTYPE;
5710 ins->dreg = vreg = alloc_ireg (cfg);
5711 MONO_ADD_INS (cfg->cbb, ins);
5714 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
5715 ins->klass = mono_defaults.int32_class;
5717 ins->type = STACK_I4;
5718 ins->dreg = long_ins->dreg + 1;
5719 MONO_ADD_INS (cfg->cbb, ins);
5721 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
5722 ins->klass = long_ins->klass;
5723 ins->sreg1 = long_ins->sreg1;
5724 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
5725 ins->type = STACK_VTYPE;
5726 ins->dreg = vreg = alloc_ireg (cfg);
5727 MONO_ADD_INS (cfg->cbb, ins);
5729 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
5730 ins->klass = mono_defaults.int32_class;
5732 ins->type = STACK_I4;
5733 ins->dreg = long_ins->dreg + 2;
5734 MONO_ADD_INS (cfg->cbb, ins);
5736 long_ins->opcode = OP_NOP;
5738 case OP_INSERTX_I8_SLOW:
5739 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
5740 ins->dreg = long_ins->dreg;
5741 ins->sreg1 = long_ins->dreg;
5742 ins->sreg2 = long_ins->sreg2 + 1;
5743 ins->inst_c0 = long_ins->inst_c0 * 2;
5744 MONO_ADD_INS (cfg->cbb, ins);
5746 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
5747 ins->dreg = long_ins->dreg;
5748 ins->sreg1 = long_ins->dreg;
5749 ins->sreg2 = long_ins->sreg2 + 2;
5750 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
5751 MONO_ADD_INS (cfg->cbb, ins);
5753 long_ins->opcode = OP_NOP;
5756 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
5757 ins->dreg = long_ins->dreg;
5758 ins->sreg1 = long_ins->sreg1 + 1;
5759 ins->klass = long_ins->klass;
5760 ins->type = STACK_VTYPE;
5761 MONO_ADD_INS (cfg->cbb, ins);
5763 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
5764 ins->dreg = long_ins->dreg;
5765 ins->sreg1 = long_ins->dreg;
5766 ins->sreg2 = long_ins->sreg1 + 2;
5768 ins->klass = long_ins->klass;
5769 ins->type = STACK_VTYPE;
5770 MONO_ADD_INS (cfg->cbb, ins);
5772 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
5773 ins->dreg = long_ins->dreg;
5774 ins->sreg1 = long_ins->dreg;;
5775 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
5776 ins->klass = long_ins->klass;
5777 ins->type = STACK_VTYPE;
5778 MONO_ADD_INS (cfg->cbb, ins);
5780 long_ins->opcode = OP_NOP;
5783 #endif /* MONO_ARCH_SIMD_INTRINSICS */
5787 #define DBG_SIGNAL SIGBUS
5789 #define DBG_SIGNAL SIGSEGV
5792 /* Soft Debug support */
5793 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
5796 * mono_arch_set_breakpoint:
5798 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
5799 * The location should contain code emitted by OP_SEQ_POINT.
5802 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
5807 * In production, we will use int3 (has to fix the size in the md
5808 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
5811 g_assert (code [0] == 0x90);
5812 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
5816 * mono_arch_clear_breakpoint:
5818 * Clear the breakpoint at IP.
5821 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
5826 for (i = 0; i < 6; ++i)
5831 * mono_arch_start_single_stepping:
5833 * Start single stepping.
5836 mono_arch_start_single_stepping (void)
5838 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
5842 * mono_arch_stop_single_stepping:
5844 * Stop single stepping.
5847 mono_arch_stop_single_stepping (void)
5849 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
5853 * mono_arch_is_single_step_event:
5855 * Return whenever the machine state in SIGCTX corresponds to a single
5859 mono_arch_is_single_step_event (void *info, void *sigctx)
5862 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info; /* Sometimes the address is off by 4 */
5863 if ((einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
5868 siginfo_t* sinfo = (siginfo_t*) info;
5869 /* Sometimes the address is off by 4 */
5870 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
5878 mono_arch_is_breakpoint_event (void *info, void *sigctx)
5881 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info; /* Sometimes the address is off by 4 */
5882 if ((einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
5887 siginfo_t* sinfo = (siginfo_t*)info;
5888 /* Sometimes the address is off by 4 */
5889 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
5897 * mono_arch_get_ip_for_breakpoint:
5899 * See mini-amd64.c for docs.
5902 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
5904 guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
5909 #define BREAKPOINT_SIZE 6
5912 * mono_arch_get_ip_for_single_step:
5914 * See mini-amd64.c for docs.
5917 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
5919 guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
5921 /* Size of x86_alu_reg_imm */
5928 * mono_arch_skip_breakpoint:
5930 * See mini-amd64.c for docs.
5933 mono_arch_skip_breakpoint (MonoContext *ctx)
5935 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
5939 * mono_arch_skip_single_step:
5941 * See mini-amd64.c for docs.
5944 mono_arch_skip_single_step (MonoContext *ctx)
5946 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
5950 * mono_arch_get_seq_point_info:
5952 * See mini-amd64.c for docs.
5955 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)