2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/abi-details.h>
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/metadata/gc-internal.h>
27 #include <mono/utils/mono-math.h>
28 #include <mono/utils/mono-counters.h>
29 #include <mono/utils/mono-mmap.h>
30 #include <mono/utils/mono-memory-model.h>
31 #include <mono/utils/mono-hwcap-x86.h>
41 static gboolean optimize_for_xen = TRUE;
43 #define optimize_for_xen 0
47 /* This mutex protects architecture specific caches */
48 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
49 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
50 static mono_mutex_t mini_arch_mutex;
52 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
57 /* Under windows, the default pinvoke calling convention is stdcall */
58 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
60 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
63 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
66 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
69 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
71 #ifdef __native_client_codegen__
73 /* Default alignment for Native Client is 32-byte. */
74 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
76 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
77 /* Check that alignment doesn't cross an alignment boundary. */
79 mono_arch_nacl_pad (guint8 *code, int pad)
81 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
83 if (pad == 0) return code;
84 /* assertion: alignment cannot cross a block boundary */
85 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
86 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
87 while (pad >= kMaxPadding) {
88 x86_padding (code, kMaxPadding);
91 if (pad != 0) x86_padding (code, pad);
96 mono_arch_nacl_skip_nops (guint8 *code)
102 #endif /* __native_client_codegen__ */
105 * The code generated for sequence points reads from this location, which is
106 * made read-only when single stepping is enabled.
108 static gpointer ss_trigger_page;
110 /* Enabled breakpoints read from this trigger page */
111 static gpointer bp_trigger_page;
114 mono_arch_regname (int reg)
117 case X86_EAX: return "%eax";
118 case X86_EBX: return "%ebx";
119 case X86_ECX: return "%ecx";
120 case X86_EDX: return "%edx";
121 case X86_ESP: return "%esp";
122 case X86_EBP: return "%ebp";
123 case X86_EDI: return "%edi";
124 case X86_ESI: return "%esi";
130 mono_arch_fregname (int reg)
155 mono_arch_xregname (int reg)
180 mono_x86_patch (unsigned char* code, gpointer target)
182 x86_patch (code, (unsigned char*)target);
193 /* gsharedvt argument passed by addr */
205 /* Only if storage == ArgValuetypeInReg */
206 ArgStorage pair_storage [2];
215 gboolean need_stack_align;
216 guint32 stack_align_amount;
217 gboolean vtype_retaddr;
218 /* The index of the vret arg in the argument list */
221 /* Argument space popped by the callee */
222 int callee_stack_pop;
228 #define FLOAT_PARAM_REGS 0
230 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
232 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
237 switch (sig->call_convention) {
238 case MONO_CALL_THISCALL:
239 return thiscall_param_regs;
245 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
246 #define SMALL_STRUCTS_IN_REGS
247 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
251 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
253 ainfo->offset = *stack_size;
255 if (!param_regs || param_regs [*gr] == X86_NREG) {
256 ainfo->storage = ArgOnStack;
258 (*stack_size) += sizeof (gpointer);
261 ainfo->storage = ArgInIReg;
262 ainfo->reg = param_regs [*gr];
268 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
270 ainfo->offset = *stack_size;
272 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
274 ainfo->storage = ArgOnStack;
275 (*stack_size) += sizeof (gpointer) * 2;
280 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
282 ainfo->offset = *stack_size;
284 if (*gr >= FLOAT_PARAM_REGS) {
285 ainfo->storage = ArgOnStack;
286 (*stack_size) += is_double ? 8 : 4;
287 ainfo->nslots = is_double ? 2 : 1;
290 /* A double register */
292 ainfo->storage = ArgInDoubleSSEReg;
294 ainfo->storage = ArgInFloatSSEReg;
302 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
304 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
309 klass = mono_class_from_mono_type (type);
310 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
312 #ifdef SMALL_STRUCTS_IN_REGS
313 if (sig->pinvoke && is_return) {
314 MonoMarshalType *info;
317 * the exact rules are not very well documented, the code below seems to work with the
318 * code generated by gcc 3.3.3 -mno-cygwin.
320 info = mono_marshal_load_type_info (klass);
323 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
325 /* Special case structs with only a float member */
326 if (info->num_fields == 1) {
327 int ftype = mini_type_get_underlying_type (gsctx, info->fields [0].field->type)->type;
328 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
329 ainfo->storage = ArgValuetypeInReg;
330 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
333 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
334 ainfo->storage = ArgValuetypeInReg;
335 ainfo->pair_storage [0] = ArgOnFloatFpStack;
339 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
340 ainfo->storage = ArgValuetypeInReg;
341 ainfo->pair_storage [0] = ArgInIReg;
342 ainfo->pair_regs [0] = return_regs [0];
343 if (info->native_size > 4) {
344 ainfo->pair_storage [1] = ArgInIReg;
345 ainfo->pair_regs [1] = return_regs [1];
352 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
353 g_assert (size <= 4);
354 ainfo->storage = ArgValuetypeInReg;
355 ainfo->reg = param_regs [*gr];
360 ainfo->offset = *stack_size;
361 ainfo->storage = ArgOnStack;
362 *stack_size += ALIGN_TO (size, sizeof (gpointer));
363 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
369 * Obtain information about a call according to the calling convention.
370 * For x86 ELF, see the "System V Application Binary Interface Intel386
371 * Architecture Processor Supplment, Fourth Edition" document for more
373 * For x86 win32, see ???.
376 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
378 guint32 i, gr, fr, pstart;
379 const guint32 *param_regs;
381 int n = sig->hasthis + sig->param_count;
382 guint32 stack_size = 0;
383 gboolean is_pinvoke = sig->pinvoke;
389 param_regs = callconv_param_regs(sig);
393 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
394 switch (ret_type->type) {
404 case MONO_TYPE_FNPTR:
405 case MONO_TYPE_CLASS:
406 case MONO_TYPE_OBJECT:
407 case MONO_TYPE_SZARRAY:
408 case MONO_TYPE_ARRAY:
409 case MONO_TYPE_STRING:
410 cinfo->ret.storage = ArgInIReg;
411 cinfo->ret.reg = X86_EAX;
415 cinfo->ret.storage = ArgInIReg;
416 cinfo->ret.reg = X86_EAX;
417 cinfo->ret.is_pair = TRUE;
420 cinfo->ret.storage = ArgOnFloatFpStack;
423 cinfo->ret.storage = ArgOnDoubleFpStack;
425 case MONO_TYPE_GENERICINST:
426 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
427 cinfo->ret.storage = ArgInIReg;
428 cinfo->ret.reg = X86_EAX;
431 if (mini_is_gsharedvt_type_gsctx (gsctx, ret_type)) {
432 cinfo->ret.storage = ArgOnStack;
433 cinfo->vtype_retaddr = TRUE;
437 case MONO_TYPE_VALUETYPE:
438 case MONO_TYPE_TYPEDBYREF: {
439 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
441 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
442 if (cinfo->ret.storage == ArgOnStack) {
443 cinfo->vtype_retaddr = TRUE;
444 /* The caller passes the address where the value is stored */
450 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ret_type));
451 cinfo->ret.storage = ArgOnStack;
452 cinfo->vtype_retaddr = TRUE;
455 cinfo->ret.storage = ArgNone;
458 g_error ("Can't handle as return value 0x%x", ret_type->type);
464 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
465 * the first argument, allowing 'this' to be always passed in the first arg reg.
466 * Also do this if the first argument is a reference type, since virtual calls
467 * are sometimes made using calli without sig->hasthis set, like in the delegate
470 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
472 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
474 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
477 cinfo->vret_arg_offset = stack_size;
478 add_general (&gr, NULL, &stack_size, &cinfo->ret);
479 cinfo->vret_arg_index = 1;
483 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
485 if (cinfo->vtype_retaddr)
486 add_general (&gr, NULL, &stack_size, &cinfo->ret);
489 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
490 fr = FLOAT_PARAM_REGS;
492 /* Emit the signature cookie just before the implicit arguments */
493 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
496 for (i = pstart; i < sig->param_count; ++i) {
497 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
500 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
501 /* We allways pass the sig cookie on the stack for simplicity */
503 * Prevent implicit arguments + the sig cookie from being passed
506 fr = FLOAT_PARAM_REGS;
508 /* Emit the signature cookie just before the implicit arguments */
509 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
512 if (sig->params [i]->byref) {
513 add_general (&gr, param_regs, &stack_size, ainfo);
516 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
517 switch (ptype->type) {
520 add_general (&gr, param_regs, &stack_size, ainfo);
524 add_general (&gr, param_regs, &stack_size, ainfo);
528 add_general (&gr, param_regs, &stack_size, ainfo);
533 case MONO_TYPE_FNPTR:
534 case MONO_TYPE_CLASS:
535 case MONO_TYPE_OBJECT:
536 case MONO_TYPE_STRING:
537 case MONO_TYPE_SZARRAY:
538 case MONO_TYPE_ARRAY:
539 add_general (&gr, param_regs, &stack_size, ainfo);
541 case MONO_TYPE_GENERICINST:
542 if (!mono_type_generic_inst_is_valuetype (ptype)) {
543 add_general (&gr, param_regs, &stack_size, ainfo);
546 if (mini_is_gsharedvt_type_gsctx (gsctx, ptype)) {
547 /* gsharedvt arguments are passed by ref */
548 add_general (&gr, param_regs, &stack_size, ainfo);
549 g_assert (ainfo->storage == ArgOnStack);
550 ainfo->storage = ArgGSharedVt;
554 case MONO_TYPE_VALUETYPE:
555 case MONO_TYPE_TYPEDBYREF:
556 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
560 add_general_pair (&gr, param_regs, &stack_size, ainfo);
563 add_float (&fr, &stack_size, ainfo, FALSE);
566 add_float (&fr, &stack_size, ainfo, TRUE);
570 /* gsharedvt arguments are passed by ref */
571 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ptype));
572 add_general (&gr, param_regs, &stack_size, ainfo);
573 g_assert (ainfo->storage == ArgOnStack);
574 ainfo->storage = ArgGSharedVt;
577 g_error ("unexpected type 0x%x", ptype->type);
578 g_assert_not_reached ();
582 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
583 fr = FLOAT_PARAM_REGS;
585 /* Emit the signature cookie just before the implicit arguments */
586 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
589 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
590 cinfo->need_stack_align = TRUE;
591 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
592 stack_size += cinfo->stack_align_amount;
595 if (cinfo->vtype_retaddr) {
596 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
597 cinfo->callee_stack_pop = 4;
600 cinfo->stack_usage = stack_size;
601 cinfo->reg_usage = gr;
602 cinfo->freg_usage = fr;
607 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
609 int n = sig->hasthis + sig->param_count;
613 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
615 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
617 return get_call_info_internal (gsctx, cinfo, sig);
621 * mono_arch_get_argument_info:
622 * @csig: a method signature
623 * @param_count: the number of parameters to consider
624 * @arg_info: an array to store the result infos
626 * Gathers information on parameters such as size, alignment and
627 * padding. arg_info should be large enought to hold param_count + 1 entries.
629 * Returns the size of the argument area on the stack.
630 * This should be signal safe, since it is called from
631 * mono_arch_find_jit_info ().
632 * FIXME: The metadata calls might not be signal safe.
635 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
637 int len, k, args_size = 0;
643 /* Avoid g_malloc as it is not signal safe */
644 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
645 cinfo = (CallInfo*)g_newa (guint8*, len);
646 memset (cinfo, 0, len);
648 cinfo = get_call_info_internal (gsctx, cinfo, csig);
650 arg_info [0].offset = offset;
652 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
653 args_size += sizeof (gpointer);
658 args_size += sizeof (gpointer);
662 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
663 /* Emitted after this */
664 args_size += sizeof (gpointer);
668 arg_info [0].size = args_size;
670 for (k = 0; k < param_count; k++) {
671 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
673 /* ignore alignment for now */
676 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
677 arg_info [k].pad = pad;
679 arg_info [k + 1].pad = 0;
680 arg_info [k + 1].size = size;
682 arg_info [k + 1].offset = offset;
685 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
686 /* Emitted after the first arg */
687 args_size += sizeof (gpointer);
692 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
693 align = MONO_ARCH_FRAME_ALIGNMENT;
696 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
697 arg_info [k].pad = pad;
703 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
705 MonoType *callee_ret;
709 if (cfg->compile_aot && !cfg->full_aot)
710 /* OP_TAILCALL doesn't work with AOT */
713 c1 = get_call_info (NULL, NULL, caller_sig);
714 c2 = get_call_info (NULL, NULL, callee_sig);
716 * Tail calls with more callee stack usage than the caller cannot be supported, since
717 * the extra stack space would be left on the stack after the tail call.
719 res = c1->stack_usage >= c2->stack_usage;
720 callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
721 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
722 /* An address on the callee's stack is passed as the first argument */
732 * Initialize the cpu to execute managed code.
735 mono_arch_cpu_init (void)
737 /* spec compliance requires running with double precision */
741 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
742 fpcw &= ~X86_FPCW_PRECC_MASK;
743 fpcw |= X86_FPCW_PREC_DOUBLE;
744 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
745 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
747 _control87 (_PC_53, MCW_PC);
752 * Initialize architecture specific code.
755 mono_arch_init (void)
757 mono_mutex_init_recursive (&mini_arch_mutex);
759 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
760 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
761 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
763 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
764 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
765 #if defined(ENABLE_GSHAREDVT)
766 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
771 * Cleanup architecture specific code.
774 mono_arch_cleanup (void)
777 mono_vfree (ss_trigger_page, mono_pagesize ());
779 mono_vfree (bp_trigger_page, mono_pagesize ());
780 mono_mutex_destroy (&mini_arch_mutex);
784 * This function returns the optimizations supported on this cpu.
787 mono_arch_cpu_optimizations (guint32 *exclude_mask)
789 #if !defined(__native_client__)
794 if (mono_hwcap_x86_has_cmov) {
795 opts |= MONO_OPT_CMOV;
797 if (mono_hwcap_x86_has_fcmov)
798 opts |= MONO_OPT_FCMOV;
800 *exclude_mask |= MONO_OPT_FCMOV;
802 *exclude_mask |= MONO_OPT_CMOV;
805 if (mono_hwcap_x86_has_sse2)
806 opts |= MONO_OPT_SSE2;
808 *exclude_mask |= MONO_OPT_SSE2;
810 #ifdef MONO_ARCH_SIMD_INTRINSICS
811 /*SIMD intrinsics require at least SSE2.*/
812 if (!mono_hwcap_x86_has_sse2)
813 *exclude_mask |= MONO_OPT_SIMD;
818 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
823 * This function test for all SSE functions supported.
825 * Returns a bitmask corresponding to all supported versions.
829 mono_arch_cpu_enumerate_simd_versions (void)
831 guint32 sse_opts = 0;
833 if (mono_hwcap_x86_has_sse1)
834 sse_opts |= SIMD_VERSION_SSE1;
836 if (mono_hwcap_x86_has_sse2)
837 sse_opts |= SIMD_VERSION_SSE2;
839 if (mono_hwcap_x86_has_sse3)
840 sse_opts |= SIMD_VERSION_SSE3;
842 if (mono_hwcap_x86_has_ssse3)
843 sse_opts |= SIMD_VERSION_SSSE3;
845 if (mono_hwcap_x86_has_sse41)
846 sse_opts |= SIMD_VERSION_SSE41;
848 if (mono_hwcap_x86_has_sse42)
849 sse_opts |= SIMD_VERSION_SSE42;
851 if (mono_hwcap_x86_has_sse4a)
852 sse_opts |= SIMD_VERSION_SSE4a;
858 * Determine whenever the trap whose info is in SIGINFO is caused by
862 mono_arch_is_int_overflow (void *sigctx, void *info)
867 mono_sigctx_to_monoctx (sigctx, &ctx);
869 ip = (guint8*)ctx.eip;
871 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
875 switch (x86_modrm_rm (ip [1])) {
895 g_assert_not_reached ();
907 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
912 for (i = 0; i < cfg->num_varinfo; i++) {
913 MonoInst *ins = cfg->varinfo [i];
914 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
917 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
920 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
921 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
924 /* we dont allocate I1 to registers because there is no simply way to sign extend
925 * 8bit quantities in caller saved registers on x86 */
926 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
927 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
928 g_assert (i == vmv->idx);
929 vars = g_list_prepend (vars, vmv);
933 vars = mono_varlist_sort (cfg, vars, 0);
939 mono_arch_get_global_int_regs (MonoCompile *cfg)
943 /* we can use 3 registers for global allocation */
944 regs = g_list_prepend (regs, (gpointer)X86_EBX);
945 regs = g_list_prepend (regs, (gpointer)X86_ESI);
946 regs = g_list_prepend (regs, (gpointer)X86_EDI);
952 * mono_arch_regalloc_cost:
954 * Return the cost, in number of memory references, of the action of
955 * allocating the variable VMV into a register during global register
959 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
961 MonoInst *ins = cfg->varinfo [vmv->idx];
963 if (cfg->method->save_lmf)
964 /* The register is already saved */
965 return (ins->opcode == OP_ARG) ? 1 : 0;
967 /* push+pop+possible load if it is an argument */
968 return (ins->opcode == OP_ARG) ? 3 : 2;
972 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
974 static int inited = FALSE;
975 static int count = 0;
977 if (cfg->arch.need_stack_frame_inited) {
978 g_assert (cfg->arch.need_stack_frame == flag);
982 cfg->arch.need_stack_frame = flag;
983 cfg->arch.need_stack_frame_inited = TRUE;
989 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
994 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
998 needs_stack_frame (MonoCompile *cfg)
1000 MonoMethodSignature *sig;
1001 MonoMethodHeader *header;
1002 gboolean result = FALSE;
1004 #if defined(__APPLE__)
1005 /*OSX requires stack frame code to have the correct alignment. */
1009 if (cfg->arch.need_stack_frame_inited)
1010 return cfg->arch.need_stack_frame;
1012 header = cfg->header;
1013 sig = mono_method_signature (cfg->method);
1015 if (cfg->disable_omit_fp)
1017 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1019 else if (cfg->method->save_lmf)
1021 else if (cfg->stack_offset)
1023 else if (cfg->param_area)
1025 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1027 else if (header->num_clauses)
1029 else if (sig->param_count + sig->hasthis)
1031 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1033 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1034 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1037 set_needs_stack_frame (cfg, result);
1039 return cfg->arch.need_stack_frame;
1043 * Set var information according to the calling convention. X86 version.
1044 * The locals var stuff should most likely be split in another method.
1047 mono_arch_allocate_vars (MonoCompile *cfg)
1049 MonoMethodSignature *sig;
1050 MonoMethodHeader *header;
1052 guint32 locals_stack_size, locals_stack_align;
1057 header = cfg->header;
1058 sig = mono_method_signature (cfg->method);
1060 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1062 cfg->frame_reg = X86_EBP;
1065 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1066 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1067 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1070 /* Reserve space to save LMF and caller saved registers */
1072 if (cfg->method->save_lmf) {
1073 /* The LMF var is allocated normally */
1075 if (cfg->used_int_regs & (1 << X86_EBX)) {
1079 if (cfg->used_int_regs & (1 << X86_EDI)) {
1083 if (cfg->used_int_regs & (1 << X86_ESI)) {
1088 switch (cinfo->ret.storage) {
1089 case ArgValuetypeInReg:
1090 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1092 cfg->ret->opcode = OP_REGOFFSET;
1093 cfg->ret->inst_basereg = X86_EBP;
1094 cfg->ret->inst_offset = - offset;
1100 /* Allocate locals */
1101 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1102 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1103 char *mname = mono_method_full_name (cfg->method, TRUE);
1104 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1105 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1109 if (locals_stack_align) {
1110 int prev_offset = offset;
1112 offset += (locals_stack_align - 1);
1113 offset &= ~(locals_stack_align - 1);
1115 while (prev_offset < offset) {
1117 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1120 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1121 cfg->locals_max_stack_offset = - offset;
1123 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1124 * have locals larger than 8 bytes we need to make sure that
1125 * they have the appropriate offset.
1127 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1128 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1129 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1130 if (offsets [i] != -1) {
1131 MonoInst *inst = cfg->varinfo [i];
1132 inst->opcode = OP_REGOFFSET;
1133 inst->inst_basereg = X86_EBP;
1134 inst->inst_offset = - (offset + offsets [i]);
1135 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1138 offset += locals_stack_size;
1142 * Allocate arguments+return value
1145 switch (cinfo->ret.storage) {
1147 if (cfg->vret_addr) {
1149 * In the new IR, the cfg->vret_addr variable represents the
1150 * vtype return value.
1152 cfg->vret_addr->opcode = OP_REGOFFSET;
1153 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1154 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1155 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1156 printf ("vret_addr =");
1157 mono_print_ins (cfg->vret_addr);
1160 cfg->ret->opcode = OP_REGOFFSET;
1161 cfg->ret->inst_basereg = X86_EBP;
1162 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1165 case ArgValuetypeInReg:
1168 cfg->ret->opcode = OP_REGVAR;
1169 cfg->ret->inst_c0 = cinfo->ret.reg;
1170 cfg->ret->dreg = cinfo->ret.reg;
1173 case ArgOnFloatFpStack:
1174 case ArgOnDoubleFpStack:
1177 g_assert_not_reached ();
1180 if (sig->call_convention == MONO_CALL_VARARG) {
1181 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1182 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1185 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1186 ArgInfo *ainfo = &cinfo->args [i];
1187 inst = cfg->args [i];
1188 if (inst->opcode != OP_REGVAR) {
1189 inst->opcode = OP_REGOFFSET;
1190 inst->inst_basereg = X86_EBP;
1192 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1195 cfg->stack_offset = offset;
1199 mono_arch_create_vars (MonoCompile *cfg)
1202 MonoMethodSignature *sig;
1205 sig = mono_method_signature (cfg->method);
1207 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1208 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1210 if (cinfo->ret.storage == ArgValuetypeInReg)
1211 cfg->ret_var_is_local = TRUE;
1212 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (cfg, sig_ret))) {
1213 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1216 if (cfg->method->save_lmf) {
1217 cfg->create_lmf_var = TRUE;
1220 cfg->lmf_ir_mono_lmf = TRUE;
1224 cfg->arch_eh_jit_info = 1;
1228 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1229 * so we try to do it just once when we have multiple fp arguments in a row.
1230 * We don't use this mechanism generally because for int arguments the generated code
1231 * is slightly bigger and new generation cpus optimize away the dependency chains
1232 * created by push instructions on the esp value.
1233 * fp_arg_setup is the first argument in the execution sequence where the esp register
1236 static G_GNUC_UNUSED int
1237 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1242 for (; start_arg < sig->param_count; ++start_arg) {
1243 t = mini_replace_type (sig->params [start_arg]);
1244 if (!t->byref && t->type == MONO_TYPE_R8) {
1245 fp_space += sizeof (double);
1246 *fp_arg_setup = start_arg;
1255 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1257 MonoMethodSignature *tmp_sig;
1261 * mono_ArgIterator_Setup assumes the signature cookie is
1262 * passed first and all the arguments which were before it are
1263 * passed on the stack after the signature. So compensate by
1264 * passing a different signature.
1266 tmp_sig = mono_metadata_signature_dup (call->signature);
1267 tmp_sig->param_count -= call->signature->sentinelpos;
1268 tmp_sig->sentinelpos = 0;
1269 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1271 if (cfg->compile_aot) {
1272 sig_reg = mono_alloc_ireg (cfg);
1273 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1274 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1276 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1282 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1287 LLVMCallInfo *linfo;
1288 MonoType *t, *sig_ret;
1290 n = sig->param_count + sig->hasthis;
1292 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1295 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1298 * LLVM always uses the native ABI while we use our own ABI, the
1299 * only difference is the handling of vtypes:
1300 * - we only pass/receive them in registers in some cases, and only
1301 * in 1 or 2 integer registers.
1303 if (cinfo->ret.storage == ArgValuetypeInReg) {
1305 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1306 cfg->disable_llvm = TRUE;
1310 cfg->exception_message = g_strdup ("vtype ret in call");
1311 cfg->disable_llvm = TRUE;
1313 linfo->ret.storage = LLVMArgVtypeInReg;
1314 for (j = 0; j < 2; ++j)
1315 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1319 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage == ArgInIReg) {
1320 /* Vtype returned using a hidden argument */
1321 linfo->ret.storage = LLVMArgVtypeRetAddr;
1322 linfo->vret_arg_index = cinfo->vret_arg_index;
1325 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage != ArgInIReg) {
1327 cfg->exception_message = g_strdup ("vtype ret in call");
1328 cfg->disable_llvm = TRUE;
1331 for (i = 0; i < n; ++i) {
1332 ainfo = cinfo->args + i;
1334 if (i >= sig->hasthis)
1335 t = sig->params [i - sig->hasthis];
1337 t = &mono_defaults.int_class->byval_arg;
1339 linfo->args [i].storage = LLVMArgNone;
1341 switch (ainfo->storage) {
1343 linfo->args [i].storage = LLVMArgInIReg;
1345 case ArgInDoubleSSEReg:
1346 case ArgInFloatSSEReg:
1347 linfo->args [i].storage = LLVMArgInFPReg;
1350 if (mini_type_is_vtype (cfg, t)) {
1351 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1352 /* LLVM seems to allocate argument space for empty structures too */
1353 linfo->args [i].storage = LLVMArgNone;
1355 linfo->args [i].storage = LLVMArgVtypeByVal;
1357 linfo->args [i].storage = LLVMArgInIReg;
1359 if (t->type == MONO_TYPE_R4)
1360 linfo->args [i].storage = LLVMArgInFPReg;
1361 else if (t->type == MONO_TYPE_R8)
1362 linfo->args [i].storage = LLVMArgInFPReg;
1366 case ArgValuetypeInReg:
1368 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1369 cfg->disable_llvm = TRUE;
1373 cfg->exception_message = g_strdup ("vtype arg");
1374 cfg->disable_llvm = TRUE;
1376 linfo->args [i].storage = LLVMArgVtypeInReg;
1377 for (j = 0; j < 2; ++j)
1378 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1382 linfo->args [i].storage = LLVMArgGSharedVt;
1385 cfg->exception_message = g_strdup ("ainfo->storage");
1386 cfg->disable_llvm = TRUE;
1396 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1398 if (cfg->compute_gc_maps) {
1401 /* Needs checking if the feature will be enabled again */
1402 g_assert_not_reached ();
1404 /* On x86, the offsets are from the sp value before the start of the call sequence */
1406 t = &mono_defaults.int_class->byval_arg;
1407 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1412 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1416 MonoMethodSignature *sig;
1419 int sentinelpos = 0, sp_offset = 0;
1421 sig = call->signature;
1422 n = sig->param_count + sig->hasthis;
1423 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1425 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1426 call->call_info = cinfo;
1428 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1429 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1431 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1432 if (cinfo->ret.storage == ArgValuetypeInReg) {
1434 * Tell the JIT to use a more efficient calling convention: call using
1435 * OP_CALL, compute the result location after the call, and save the
1438 call->vret_in_reg = TRUE;
1439 #if defined(__APPLE__)
1440 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1441 call->vret_in_reg_fp = TRUE;
1444 NULLIFY_INS (call->vret_var);
1448 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1450 /* Handle the case where there are no implicit arguments */
1451 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1452 emit_sig_cookie (cfg, call, cinfo);
1453 sp_offset = cinfo->sig_cookie.offset;
1454 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1457 /* Arguments are pushed in the reverse order */
1458 for (i = n - 1; i >= 0; i --) {
1459 ArgInfo *ainfo = cinfo->args + i;
1460 MonoType *orig_type, *t;
1463 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1466 /* Push the vret arg before the first argument */
1467 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1468 vtarg->type = STACK_MP;
1469 vtarg->inst_destbasereg = X86_ESP;
1470 vtarg->sreg1 = call->vret_var->dreg;
1471 vtarg->inst_offset = cinfo->ret.offset;
1472 MONO_ADD_INS (cfg->cbb, vtarg);
1473 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1476 if (i >= sig->hasthis)
1477 t = sig->params [i - sig->hasthis];
1479 t = &mono_defaults.int_class->byval_arg;
1481 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1483 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1485 in = call->args [i];
1486 arg->cil_code = in->cil_code;
1487 arg->sreg1 = in->dreg;
1488 arg->type = in->type;
1490 g_assert (in->dreg != -1);
1492 if (ainfo->storage == ArgGSharedVt) {
1493 arg->opcode = OP_OUTARG_VT;
1494 arg->sreg1 = in->dreg;
1495 arg->klass = in->klass;
1496 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1497 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1499 MONO_ADD_INS (cfg->cbb, arg);
1500 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1504 g_assert (in->klass);
1506 if (t->type == MONO_TYPE_TYPEDBYREF) {
1507 size = sizeof (MonoTypedRef);
1508 align = sizeof (gpointer);
1511 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1515 arg->opcode = OP_OUTARG_VT;
1516 arg->sreg1 = in->dreg;
1517 arg->klass = in->klass;
1518 arg->backend.size = size;
1519 arg->inst_p0 = call;
1520 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1521 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1523 MONO_ADD_INS (cfg->cbb, arg);
1524 if (ainfo->storage != ArgValuetypeInReg) {
1525 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1529 switch (ainfo->storage) {
1532 if (t->type == MONO_TYPE_R4) {
1533 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1535 } else if (t->type == MONO_TYPE_R8) {
1536 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1538 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1539 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, in->dreg + 2);
1540 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg + 1);
1543 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1547 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1552 arg->opcode = OP_MOVE;
1553 arg->dreg = ainfo->reg;
1554 MONO_ADD_INS (cfg->cbb, arg);
1558 g_assert_not_reached ();
1561 if (cfg->compute_gc_maps) {
1563 /* FIXME: The == STACK_OBJ check might be fragile ? */
1564 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1566 if (call->need_unbox_trampoline)
1567 /* The unbox trampoline transforms this into a managed pointer */
1568 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.int_class->this_arg);
1570 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.object_class->byval_arg);
1572 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1576 for (j = 0; j < argsize; j += 4)
1577 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1582 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1583 /* Emit the signature cookie just before the implicit arguments */
1584 emit_sig_cookie (cfg, call, cinfo);
1585 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1589 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1592 if (cinfo->ret.storage == ArgValuetypeInReg) {
1595 else if (cinfo->ret.storage == ArgInIReg) {
1597 /* The return address is passed in a register */
1598 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1599 vtarg->sreg1 = call->inst.dreg;
1600 vtarg->dreg = mono_alloc_ireg (cfg);
1601 MONO_ADD_INS (cfg->cbb, vtarg);
1603 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1604 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1605 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1606 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1610 call->stack_usage = cinfo->stack_usage;
1611 call->stack_align_amount = cinfo->stack_align_amount;
1615 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1617 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1618 ArgInfo *ainfo = ins->inst_p1;
1619 int size = ins->backend.size;
1621 if (ainfo->storage == ArgValuetypeInReg) {
1622 int dreg = mono_alloc_ireg (cfg);
1625 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1628 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1631 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1635 g_assert_not_reached ();
1637 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1640 if (cfg->gsharedvt && mini_is_gsharedvt_klass (cfg, ins->klass)) {
1642 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1643 } else if (size <= 4) {
1644 int dreg = mono_alloc_ireg (cfg);
1645 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1646 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1647 } else if (size <= 20) {
1648 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1650 // FIXME: Code growth
1651 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1657 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1659 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1662 if (ret->type == MONO_TYPE_R4) {
1663 if (COMPILE_LLVM (cfg))
1664 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1667 } else if (ret->type == MONO_TYPE_R8) {
1668 if (COMPILE_LLVM (cfg))
1669 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1672 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1673 if (COMPILE_LLVM (cfg))
1674 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1676 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1677 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1683 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1687 * Allow tracing to work with this interface (with an optional argument)
1690 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1694 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1695 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1697 /* if some args are passed in registers, we need to save them here */
1698 x86_push_reg (code, X86_EBP);
1700 if (cfg->compile_aot) {
1701 x86_push_imm (code, cfg->method);
1702 x86_mov_reg_imm (code, X86_EAX, func);
1703 x86_call_reg (code, X86_EAX);
1705 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1706 x86_push_imm (code, cfg->method);
1707 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1708 x86_call_code (code, 0);
1710 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1724 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1727 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1728 MonoMethod *method = cfg->method;
1729 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1731 switch (ret_type->type) {
1732 case MONO_TYPE_VOID:
1733 /* special case string .ctor icall */
1734 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1735 save_mode = SAVE_EAX;
1736 stack_usage = enable_arguments ? 8 : 4;
1738 save_mode = SAVE_NONE;
1742 save_mode = SAVE_EAX_EDX;
1743 stack_usage = enable_arguments ? 16 : 8;
1747 save_mode = SAVE_FP;
1748 stack_usage = enable_arguments ? 16 : 8;
1750 case MONO_TYPE_GENERICINST:
1751 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1752 save_mode = SAVE_EAX;
1753 stack_usage = enable_arguments ? 8 : 4;
1757 case MONO_TYPE_VALUETYPE:
1758 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1759 save_mode = SAVE_STRUCT;
1760 stack_usage = enable_arguments ? 4 : 0;
1763 save_mode = SAVE_EAX;
1764 stack_usage = enable_arguments ? 8 : 4;
1768 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1770 switch (save_mode) {
1772 x86_push_reg (code, X86_EDX);
1773 x86_push_reg (code, X86_EAX);
1774 if (enable_arguments) {
1775 x86_push_reg (code, X86_EDX);
1776 x86_push_reg (code, X86_EAX);
1781 x86_push_reg (code, X86_EAX);
1782 if (enable_arguments) {
1783 x86_push_reg (code, X86_EAX);
1788 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1789 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1790 if (enable_arguments) {
1791 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1792 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1797 if (enable_arguments) {
1798 x86_push_membase (code, X86_EBP, 8);
1807 if (cfg->compile_aot) {
1808 x86_push_imm (code, method);
1809 x86_mov_reg_imm (code, X86_EAX, func);
1810 x86_call_reg (code, X86_EAX);
1812 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1813 x86_push_imm (code, method);
1814 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1815 x86_call_code (code, 0);
1818 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1820 switch (save_mode) {
1822 x86_pop_reg (code, X86_EAX);
1823 x86_pop_reg (code, X86_EDX);
1826 x86_pop_reg (code, X86_EAX);
1829 x86_fld_membase (code, X86_ESP, 0, TRUE);
1830 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1837 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1842 #define EMIT_COND_BRANCH(ins,cond,sign) \
1843 if (ins->inst_true_bb->native_offset) { \
1844 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1846 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1847 if ((cfg->opt & MONO_OPT_BRANCH) && \
1848 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1849 x86_branch8 (code, cond, 0, sign); \
1851 x86_branch32 (code, cond, 0, sign); \
1855 * Emit an exception if condition is fail and
1856 * if possible do a directly branch to target
1858 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1860 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1861 if (tins == NULL) { \
1862 mono_add_patch_info (cfg, code - cfg->native_code, \
1863 MONO_PATCH_INFO_EXC, exc_name); \
1864 x86_branch32 (code, cond, 0, signed); \
1866 EMIT_COND_BRANCH (tins, cond, signed); \
1870 #define EMIT_FPCOMPARE(code) do { \
1871 x86_fcompp (code); \
1872 x86_fnstsw (code); \
1877 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1879 gboolean needs_paddings = TRUE;
1881 MonoJumpInfo *jinfo = NULL;
1883 if (cfg->abs_patches) {
1884 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1885 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1886 needs_paddings = FALSE;
1889 if (cfg->compile_aot)
1890 needs_paddings = FALSE;
1891 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1892 This is required for code patching to be safe on SMP machines.
1894 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1895 #ifndef __native_client_codegen__
1896 if (needs_paddings && pad_size)
1897 x86_padding (code, 4 - pad_size);
1900 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1901 x86_call_code (code, 0);
1906 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1909 * mono_peephole_pass_1:
1911 * Perform peephole opts which should/can be performed before local regalloc
1914 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1918 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1919 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1921 switch (ins->opcode) {
1924 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1926 * X86_LEA is like ADD, but doesn't have the
1927 * sreg1==dreg restriction.
1929 ins->opcode = OP_X86_LEA_MEMBASE;
1930 ins->inst_basereg = ins->sreg1;
1931 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1932 ins->opcode = OP_X86_INC_REG;
1936 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1937 ins->opcode = OP_X86_LEA_MEMBASE;
1938 ins->inst_basereg = ins->sreg1;
1939 ins->inst_imm = -ins->inst_imm;
1940 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1941 ins->opcode = OP_X86_DEC_REG;
1943 case OP_COMPARE_IMM:
1944 case OP_ICOMPARE_IMM:
1945 /* OP_COMPARE_IMM (reg, 0)
1947 * OP_X86_TEST_NULL (reg)
1950 ins->opcode = OP_X86_TEST_NULL;
1952 case OP_X86_COMPARE_MEMBASE_IMM:
1954 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1955 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1957 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1958 * OP_COMPARE_IMM reg, imm
1960 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1962 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1963 ins->inst_basereg == last_ins->inst_destbasereg &&
1964 ins->inst_offset == last_ins->inst_offset) {
1965 ins->opcode = OP_COMPARE_IMM;
1966 ins->sreg1 = last_ins->sreg1;
1968 /* check if we can remove cmp reg,0 with test null */
1970 ins->opcode = OP_X86_TEST_NULL;
1974 case OP_X86_PUSH_MEMBASE:
1975 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1976 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1977 ins->inst_basereg == last_ins->inst_destbasereg &&
1978 ins->inst_offset == last_ins->inst_offset) {
1979 ins->opcode = OP_X86_PUSH;
1980 ins->sreg1 = last_ins->sreg1;
1985 mono_peephole_ins (bb, ins);
1990 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1994 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1995 switch (ins->opcode) {
1997 /* reg = 0 -> XOR (reg, reg) */
1998 /* XOR sets cflags on x86, so we cant do it always */
1999 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2002 ins->opcode = OP_IXOR;
2003 ins->sreg1 = ins->dreg;
2004 ins->sreg2 = ins->dreg;
2007 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2008 * since it takes 3 bytes instead of 7.
2010 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
2011 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2012 ins2->opcode = OP_STORE_MEMBASE_REG;
2013 ins2->sreg1 = ins->dreg;
2015 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2016 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2017 ins2->sreg1 = ins->dreg;
2019 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2020 /* Continue iteration */
2029 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2030 ins->opcode = OP_X86_INC_REG;
2034 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2035 ins->opcode = OP_X86_DEC_REG;
2039 mono_peephole_ins (bb, ins);
2044 * mono_arch_lowering_pass:
2046 * Converts complex opcodes into simpler ones so that each IR instruction
2047 * corresponds to one machine instruction.
2050 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2052 MonoInst *ins, *next;
2055 * FIXME: Need to add more instructions, but the current machine
2056 * description can't model some parts of the composite instructions like
2059 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2060 switch (ins->opcode) {
2063 case OP_IDIV_UN_IMM:
2064 case OP_IREM_UN_IMM:
2066 * Keep the cases where we could generated optimized code, otherwise convert
2067 * to the non-imm variant.
2069 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2071 mono_decompose_op_imm (cfg, bb, ins);
2078 bb->max_vreg = cfg->next_vreg;
2082 branch_cc_table [] = {
2083 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2084 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2085 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2088 /* Maps CMP_... constants to X86_CC_... constants */
2091 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2092 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2096 cc_signed_table [] = {
2097 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2098 FALSE, FALSE, FALSE, FALSE
2101 static unsigned char*
2102 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2104 #define XMM_TEMP_REG 0
2105 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2106 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2107 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2108 /* optimize by assigning a local var for this use so we avoid
2109 * the stack manipulations */
2110 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2111 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2112 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2113 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2114 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2116 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2118 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2121 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2122 x86_fnstcw_membase(code, X86_ESP, 0);
2123 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2124 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2125 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2126 x86_fldcw_membase (code, X86_ESP, 2);
2128 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2129 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2130 x86_pop_reg (code, dreg);
2131 /* FIXME: need the high register
2132 * x86_pop_reg (code, dreg_high);
2135 x86_push_reg (code, X86_EAX); // SP = SP - 4
2136 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2137 x86_pop_reg (code, dreg);
2139 x86_fldcw_membase (code, X86_ESP, 0);
2140 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2143 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2145 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2149 static unsigned char*
2150 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2152 int sreg = tree->sreg1;
2153 int need_touch = FALSE;
2155 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2164 * If requested stack size is larger than one page,
2165 * perform stack-touch operation
2168 * Generate stack probe code.
2169 * Under Windows, it is necessary to allocate one page at a time,
2170 * "touching" stack after each successful sub-allocation. This is
2171 * because of the way stack growth is implemented - there is a
2172 * guard page before the lowest stack page that is currently commited.
2173 * Stack normally grows sequentially so OS traps access to the
2174 * guard page and commits more pages when needed.
2176 x86_test_reg_imm (code, sreg, ~0xFFF);
2177 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2179 br[2] = code; /* loop */
2180 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2181 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2184 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2185 * that follows only initializes the last part of the area.
2187 /* Same as the init code below with size==0x1000 */
2188 if (tree->flags & MONO_INST_INIT) {
2189 x86_push_reg (code, X86_EAX);
2190 x86_push_reg (code, X86_ECX);
2191 x86_push_reg (code, X86_EDI);
2192 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2193 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2194 if (cfg->param_area)
2195 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2197 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2199 x86_prefix (code, X86_REP_PREFIX);
2201 x86_pop_reg (code, X86_EDI);
2202 x86_pop_reg (code, X86_ECX);
2203 x86_pop_reg (code, X86_EAX);
2206 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2207 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2208 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2209 x86_patch (br[3], br[2]);
2210 x86_test_reg_reg (code, sreg, sreg);
2211 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2212 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2214 br[1] = code; x86_jump8 (code, 0);
2216 x86_patch (br[0], code);
2217 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2218 x86_patch (br[1], code);
2219 x86_patch (br[4], code);
2222 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2224 if (tree->flags & MONO_INST_INIT) {
2226 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2227 x86_push_reg (code, X86_EAX);
2230 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2231 x86_push_reg (code, X86_ECX);
2234 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2235 x86_push_reg (code, X86_EDI);
2239 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2240 if (sreg != X86_ECX)
2241 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2242 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2244 if (cfg->param_area)
2245 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2247 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2249 x86_prefix (code, X86_REP_PREFIX);
2252 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2253 x86_pop_reg (code, X86_EDI);
2254 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2255 x86_pop_reg (code, X86_ECX);
2256 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2257 x86_pop_reg (code, X86_EAX);
2264 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2266 /* Move return value to the target register */
2267 switch (ins->opcode) {
2270 case OP_CALL_MEMBASE:
2271 if (ins->dreg != X86_EAX)
2272 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2282 static int tls_gs_offset;
2286 mono_x86_have_tls_get (void)
2289 static gboolean have_tls_get = FALSE;
2290 static gboolean inited = FALSE;
2294 return have_tls_get;
2296 ins = (guint32*)pthread_getspecific;
2298 * We're looking for these two instructions:
2300 * mov 0x4(%esp),%eax
2301 * mov %gs:[offset](,%eax,4),%eax
2303 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2304 tls_gs_offset = ins [2];
2308 return have_tls_get;
2309 #elif defined(TARGET_ANDROID)
2317 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2319 #if defined(__APPLE__)
2320 x86_prefix (code, X86_GS_PREFIX);
2321 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2322 #elif defined(TARGET_WIN32)
2323 g_assert_not_reached ();
2325 x86_prefix (code, X86_GS_PREFIX);
2326 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2332 * mono_x86_emit_tls_get:
2333 * @code: buffer to store code to
2334 * @dreg: hard register where to place the result
2335 * @tls_offset: offset info
2337 * mono_x86_emit_tls_get emits in @code the native code that puts in
2338 * the dreg register the item in the thread local storage identified
2341 * Returns: a pointer to the end of the stored code
2344 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2346 #if defined(__APPLE__)
2347 x86_prefix (code, X86_GS_PREFIX);
2348 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2349 #elif defined(TARGET_WIN32)
2351 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2352 * Journal and/or a disassembly of the TlsGet () function.
2354 x86_prefix (code, X86_FS_PREFIX);
2355 x86_mov_reg_mem (code, dreg, 0x18, 4);
2356 if (tls_offset < 64) {
2357 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2361 g_assert (tls_offset < 0x440);
2362 /* Load TEB->TlsExpansionSlots */
2363 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2364 x86_test_reg_reg (code, dreg, dreg);
2366 x86_branch (code, X86_CC_EQ, code, TRUE);
2367 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2368 x86_patch (buf [0], code);
2371 if (optimize_for_xen) {
2372 x86_prefix (code, X86_GS_PREFIX);
2373 x86_mov_reg_mem (code, dreg, 0, 4);
2374 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2376 x86_prefix (code, X86_GS_PREFIX);
2377 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2384 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2386 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2387 #if defined(__APPLE__) || defined(__linux__)
2388 if (dreg != offset_reg)
2389 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2390 x86_prefix (code, X86_GS_PREFIX);
2391 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2393 g_assert_not_reached ();
2399 mono_x86_emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2401 return emit_tls_get_reg (code, dreg, offset_reg);
2405 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2407 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2409 g_assert_not_reached ();
2410 #elif defined(__APPLE__) || defined(__linux__)
2411 x86_prefix (code, X86_GS_PREFIX);
2412 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2414 g_assert_not_reached ();
2420 * mono_arch_translate_tls_offset:
2422 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2425 mono_arch_translate_tls_offset (int offset)
2428 return tls_gs_offset + (offset * 4);
2437 * Emit code to initialize an LMF structure at LMF_OFFSET.
2440 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2442 /* save all caller saved regs */
2443 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2444 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2445 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2446 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2447 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2448 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2449 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2451 /* save the current IP */
2452 if (cfg->compile_aot) {
2453 /* This pushes the current ip */
2454 x86_call_imm (code, 0);
2455 x86_pop_reg (code, X86_EAX);
2457 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2458 x86_mov_reg_imm (code, X86_EAX, 0);
2460 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2462 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2463 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2464 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2465 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2466 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2467 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2468 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2469 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2470 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2475 #define REAL_PRINT_REG(text,reg) \
2476 mono_assert (reg >= 0); \
2477 x86_push_reg (code, X86_EAX); \
2478 x86_push_reg (code, X86_EDX); \
2479 x86_push_reg (code, X86_ECX); \
2480 x86_push_reg (code, reg); \
2481 x86_push_imm (code, reg); \
2482 x86_push_imm (code, text " %d %p\n"); \
2483 x86_mov_reg_imm (code, X86_EAX, printf); \
2484 x86_call_reg (code, X86_EAX); \
2485 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2486 x86_pop_reg (code, X86_ECX); \
2487 x86_pop_reg (code, X86_EDX); \
2488 x86_pop_reg (code, X86_EAX);
2490 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2491 #ifdef __native__client_codegen__
2492 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2495 /* benchmark and set based on cpu */
2496 #define LOOP_ALIGNMENT 8
2497 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2501 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2506 guint8 *code = cfg->native_code + cfg->code_len;
2509 if (cfg->opt & MONO_OPT_LOOP) {
2510 int pad, align = LOOP_ALIGNMENT;
2511 /* set alignment depending on cpu */
2512 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2514 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2515 x86_padding (code, pad);
2516 cfg->code_len += pad;
2517 bb->native_offset = cfg->code_len;
2520 #ifdef __native_client_codegen__
2522 /* For Native Client, all indirect call/jump targets must be */
2523 /* 32-byte aligned. Exception handler blocks are jumped to */
2524 /* indirectly as well. */
2525 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2526 (bb->flags & BB_EXCEPTION_HANDLER);
2528 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2529 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2530 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2531 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2532 cfg->code_len += pad;
2533 bb->native_offset = cfg->code_len;
2536 #endif /* __native_client_codegen__ */
2537 if (cfg->verbose_level > 2)
2538 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2540 cpos = bb->max_offset;
2542 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
2543 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2544 g_assert (!cfg->compile_aot);
2547 cov->data [bb->dfn].cil_code = bb->cil_code;
2548 /* this is not thread save, but good enough */
2549 x86_inc_mem (code, &cov->data [bb->dfn].count);
2552 offset = code - cfg->native_code;
2554 mono_debug_open_block (cfg, bb, offset);
2556 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2557 x86_breakpoint (code);
2559 MONO_BB_FOR_EACH_INS (bb, ins) {
2560 offset = code - cfg->native_code;
2562 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2564 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2566 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2567 cfg->code_size *= 2;
2568 cfg->native_code = mono_realloc_native_code(cfg);
2569 code = cfg->native_code + offset;
2570 cfg->stat_code_reallocs++;
2573 if (cfg->debug_info)
2574 mono_debug_record_line_number (cfg, ins, offset);
2576 switch (ins->opcode) {
2578 x86_mul_reg (code, ins->sreg2, TRUE);
2581 x86_mul_reg (code, ins->sreg2, FALSE);
2583 case OP_X86_SETEQ_MEMBASE:
2584 case OP_X86_SETNE_MEMBASE:
2585 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2586 ins->inst_basereg, ins->inst_offset, TRUE);
2588 case OP_STOREI1_MEMBASE_IMM:
2589 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2591 case OP_STOREI2_MEMBASE_IMM:
2592 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2594 case OP_STORE_MEMBASE_IMM:
2595 case OP_STOREI4_MEMBASE_IMM:
2596 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2598 case OP_STOREI1_MEMBASE_REG:
2599 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2601 case OP_STOREI2_MEMBASE_REG:
2602 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2604 case OP_STORE_MEMBASE_REG:
2605 case OP_STOREI4_MEMBASE_REG:
2606 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2608 case OP_STORE_MEM_IMM:
2609 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2612 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2616 /* These are created by the cprop pass so they use inst_imm as the source */
2617 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2620 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2623 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2625 case OP_LOAD_MEMBASE:
2626 case OP_LOADI4_MEMBASE:
2627 case OP_LOADU4_MEMBASE:
2628 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2630 case OP_LOADU1_MEMBASE:
2631 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2633 case OP_LOADI1_MEMBASE:
2634 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2636 case OP_LOADU2_MEMBASE:
2637 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2639 case OP_LOADI2_MEMBASE:
2640 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2642 case OP_ICONV_TO_I1:
2644 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2646 case OP_ICONV_TO_I2:
2648 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2650 case OP_ICONV_TO_U1:
2651 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2653 case OP_ICONV_TO_U2:
2654 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2658 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2660 case OP_COMPARE_IMM:
2661 case OP_ICOMPARE_IMM:
2662 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2664 case OP_X86_COMPARE_MEMBASE_REG:
2665 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2667 case OP_X86_COMPARE_MEMBASE_IMM:
2668 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2670 case OP_X86_COMPARE_MEMBASE8_IMM:
2671 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2673 case OP_X86_COMPARE_REG_MEMBASE:
2674 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2676 case OP_X86_COMPARE_MEM_IMM:
2677 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2679 case OP_X86_TEST_NULL:
2680 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2682 case OP_X86_ADD_MEMBASE_IMM:
2683 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2685 case OP_X86_ADD_REG_MEMBASE:
2686 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2688 case OP_X86_SUB_MEMBASE_IMM:
2689 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2691 case OP_X86_SUB_REG_MEMBASE:
2692 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2694 case OP_X86_AND_MEMBASE_IMM:
2695 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2697 case OP_X86_OR_MEMBASE_IMM:
2698 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2700 case OP_X86_XOR_MEMBASE_IMM:
2701 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2703 case OP_X86_ADD_MEMBASE_REG:
2704 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2706 case OP_X86_SUB_MEMBASE_REG:
2707 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2709 case OP_X86_AND_MEMBASE_REG:
2710 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2712 case OP_X86_OR_MEMBASE_REG:
2713 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2715 case OP_X86_XOR_MEMBASE_REG:
2716 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2718 case OP_X86_INC_MEMBASE:
2719 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2721 case OP_X86_INC_REG:
2722 x86_inc_reg (code, ins->dreg);
2724 case OP_X86_DEC_MEMBASE:
2725 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2727 case OP_X86_DEC_REG:
2728 x86_dec_reg (code, ins->dreg);
2730 case OP_X86_MUL_REG_MEMBASE:
2731 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2733 case OP_X86_AND_REG_MEMBASE:
2734 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2736 case OP_X86_OR_REG_MEMBASE:
2737 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2739 case OP_X86_XOR_REG_MEMBASE:
2740 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2743 x86_breakpoint (code);
2745 case OP_RELAXED_NOP:
2746 x86_prefix (code, X86_REP_PREFIX);
2754 case OP_DUMMY_STORE:
2755 case OP_DUMMY_ICONST:
2756 case OP_DUMMY_R8CONST:
2757 case OP_NOT_REACHED:
2760 case OP_IL_SEQ_POINT:
2761 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2763 case OP_SEQ_POINT: {
2766 if (cfg->compile_aot)
2770 * Read from the single stepping trigger page. This will cause a
2771 * SIGSEGV when single stepping is enabled.
2772 * We do this _before_ the breakpoint, so single stepping after
2773 * a breakpoint is hit will step to the next IL offset.
2775 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2776 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2778 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2781 * A placeholder for a possible breakpoint inserted by
2782 * mono_arch_set_breakpoint ().
2784 for (i = 0; i < 6; ++i)
2787 * Add an additional nop so skipping the bp doesn't cause the ip to point
2788 * to another IL offset.
2796 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2800 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2805 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2809 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2814 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2818 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2823 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2827 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2830 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2834 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2838 #if defined( __native_client_codegen__ )
2839 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2840 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2843 * The code is the same for div/rem, the allocator will allocate dreg
2844 * to RAX/RDX as appropriate.
2846 if (ins->sreg2 == X86_EDX) {
2847 /* cdq clobbers this */
2848 x86_push_reg (code, ins->sreg2);
2850 x86_div_membase (code, X86_ESP, 0, TRUE);
2851 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2854 x86_div_reg (code, ins->sreg2, TRUE);
2859 #if defined( __native_client_codegen__ )
2860 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2861 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2863 if (ins->sreg2 == X86_EDX) {
2864 x86_push_reg (code, ins->sreg2);
2865 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2866 x86_div_membase (code, X86_ESP, 0, FALSE);
2867 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2869 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2870 x86_div_reg (code, ins->sreg2, FALSE);
2874 #if defined( __native_client_codegen__ )
2875 if (ins->inst_imm == 0) {
2876 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2877 x86_jump32 (code, 0);
2881 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2883 x86_div_reg (code, ins->sreg2, TRUE);
2886 int power = mono_is_power_of_two (ins->inst_imm);
2888 g_assert (ins->sreg1 == X86_EAX);
2889 g_assert (ins->dreg == X86_EAX);
2890 g_assert (power >= 0);
2893 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2895 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2897 * If the divident is >= 0, this does not nothing. If it is positive, it
2898 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2900 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2901 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2902 } else if (power == 0) {
2903 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2905 /* Based on gcc code */
2907 /* Add compensation for negative dividents */
2909 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2910 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2911 /* Compute remainder */
2912 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2913 /* Remove compensation */
2914 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2919 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2923 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2926 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2930 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2933 g_assert (ins->sreg2 == X86_ECX);
2934 x86_shift_reg (code, X86_SHL, ins->dreg);
2937 g_assert (ins->sreg2 == X86_ECX);
2938 x86_shift_reg (code, X86_SAR, ins->dreg);
2942 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2945 case OP_ISHR_UN_IMM:
2946 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2949 g_assert (ins->sreg2 == X86_ECX);
2950 x86_shift_reg (code, X86_SHR, ins->dreg);
2954 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2957 guint8 *jump_to_end;
2959 /* handle shifts below 32 bits */
2960 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2961 x86_shift_reg (code, X86_SHL, ins->sreg1);
2963 x86_test_reg_imm (code, X86_ECX, 32);
2964 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2966 /* handle shift over 32 bit */
2967 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2968 x86_clear_reg (code, ins->sreg1);
2970 x86_patch (jump_to_end, code);
2974 guint8 *jump_to_end;
2976 /* handle shifts below 32 bits */
2977 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2978 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2980 x86_test_reg_imm (code, X86_ECX, 32);
2981 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2983 /* handle shifts over 31 bits */
2984 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2985 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2987 x86_patch (jump_to_end, code);
2991 guint8 *jump_to_end;
2993 /* handle shifts below 32 bits */
2994 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2995 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2997 x86_test_reg_imm (code, X86_ECX, 32);
2998 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3000 /* handle shifts over 31 bits */
3001 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3002 x86_clear_reg (code, ins->backend.reg3);
3004 x86_patch (jump_to_end, code);
3008 if (ins->inst_imm >= 32) {
3009 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3010 x86_clear_reg (code, ins->sreg1);
3011 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
3013 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
3014 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
3018 if (ins->inst_imm >= 32) {
3019 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3020 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
3021 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
3023 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3024 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3027 case OP_LSHR_UN_IMM:
3028 if (ins->inst_imm >= 32) {
3029 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3030 x86_clear_reg (code, ins->backend.reg3);
3031 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3033 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3034 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3038 x86_not_reg (code, ins->sreg1);
3041 x86_neg_reg (code, ins->sreg1);
3045 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3049 switch (ins->inst_imm) {
3053 if (ins->dreg != ins->sreg1)
3054 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3055 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3058 /* LEA r1, [r2 + r2*2] */
3059 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3062 /* LEA r1, [r2 + r2*4] */
3063 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3066 /* LEA r1, [r2 + r2*2] */
3068 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3069 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3072 /* LEA r1, [r2 + r2*8] */
3073 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3076 /* LEA r1, [r2 + r2*4] */
3078 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3079 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3082 /* LEA r1, [r2 + r2*2] */
3084 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3085 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3088 /* LEA r1, [r2 + r2*4] */
3089 /* LEA r1, [r1 + r1*4] */
3090 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3091 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3094 /* LEA r1, [r2 + r2*4] */
3096 /* LEA r1, [r1 + r1*4] */
3097 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3098 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3099 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3102 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3107 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3108 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3110 case OP_IMUL_OVF_UN: {
3111 /* the mul operation and the exception check should most likely be split */
3112 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3113 /*g_assert (ins->sreg2 == X86_EAX);
3114 g_assert (ins->dreg == X86_EAX);*/
3115 if (ins->sreg2 == X86_EAX) {
3116 non_eax_reg = ins->sreg1;
3117 } else if (ins->sreg1 == X86_EAX) {
3118 non_eax_reg = ins->sreg2;
3120 /* no need to save since we're going to store to it anyway */
3121 if (ins->dreg != X86_EAX) {
3123 x86_push_reg (code, X86_EAX);
3125 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3126 non_eax_reg = ins->sreg2;
3128 if (ins->dreg == X86_EDX) {
3131 x86_push_reg (code, X86_EAX);
3133 } else if (ins->dreg != X86_EAX) {
3135 x86_push_reg (code, X86_EDX);
3137 x86_mul_reg (code, non_eax_reg, FALSE);
3138 /* save before the check since pop and mov don't change the flags */
3139 if (ins->dreg != X86_EAX)
3140 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3142 x86_pop_reg (code, X86_EDX);
3144 x86_pop_reg (code, X86_EAX);
3145 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3149 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3152 g_assert_not_reached ();
3153 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3154 x86_mov_reg_imm (code, ins->dreg, 0);
3157 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3158 x86_mov_reg_imm (code, ins->dreg, 0);
3160 case OP_LOAD_GOTADDR:
3161 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3162 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3165 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3166 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3168 case OP_X86_PUSH_GOT_ENTRY:
3169 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3170 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3173 if (ins->dreg != ins->sreg1)
3174 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3177 MonoCallInst *call = (MonoCallInst*)ins;
3180 ins->flags |= MONO_INST_GC_CALLSITE;
3181 ins->backend.pc_offset = code - cfg->native_code;
3183 /* reset offset to make max_len work */
3184 offset = code - cfg->native_code;
3186 g_assert (!cfg->method->save_lmf);
3188 /* restore callee saved registers */
3189 for (i = 0; i < X86_NREG; ++i)
3190 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3192 if (cfg->used_int_regs & (1 << X86_ESI)) {
3193 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3196 if (cfg->used_int_regs & (1 << X86_EDI)) {
3197 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3200 if (cfg->used_int_regs & (1 << X86_EBX)) {
3201 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3205 /* Copy arguments on the stack to our argument area */
3206 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3207 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3208 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3211 /* restore ESP/EBP */
3213 offset = code - cfg->native_code;
3214 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3215 x86_jump32 (code, 0);
3217 ins->flags |= MONO_INST_GC_CALLSITE;
3218 cfg->disable_aot = TRUE;
3222 /* ensure ins->sreg1 is not NULL
3223 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3224 * cmp DWORD PTR [eax], 0
3226 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3229 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3230 x86_push_reg (code, hreg);
3231 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3232 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3233 x86_pop_reg (code, hreg);
3246 case OP_VOIDCALL_REG:
3248 case OP_FCALL_MEMBASE:
3249 case OP_LCALL_MEMBASE:
3250 case OP_VCALL_MEMBASE:
3251 case OP_VCALL2_MEMBASE:
3252 case OP_VOIDCALL_MEMBASE:
3253 case OP_CALL_MEMBASE: {
3256 call = (MonoCallInst*)ins;
3257 cinfo = (CallInfo*)call->call_info;
3259 switch (ins->opcode) {
3266 if (ins->flags & MONO_INST_HAS_METHOD)
3267 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3269 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3275 case OP_VOIDCALL_REG:
3277 x86_call_reg (code, ins->sreg1);
3279 case OP_FCALL_MEMBASE:
3280 case OP_LCALL_MEMBASE:
3281 case OP_VCALL_MEMBASE:
3282 case OP_VCALL2_MEMBASE:
3283 case OP_VOIDCALL_MEMBASE:
3284 case OP_CALL_MEMBASE:
3285 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3288 g_assert_not_reached ();
3291 ins->flags |= MONO_INST_GC_CALLSITE;
3292 ins->backend.pc_offset = code - cfg->native_code;
3293 if (cinfo->callee_stack_pop) {
3294 /* Have to compensate for the stack space popped by the callee */
3295 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3297 code = emit_move_return_value (cfg, ins, code);
3301 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3303 case OP_X86_LEA_MEMBASE:
3304 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3307 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3310 /* keep alignment */
3311 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3312 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3313 code = mono_emit_stack_alloc (cfg, code, ins);
3314 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3315 if (cfg->param_area)
3316 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3318 case OP_LOCALLOC_IMM: {
3319 guint32 size = ins->inst_imm;
3320 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3322 if (ins->flags & MONO_INST_INIT) {
3323 /* FIXME: Optimize this */
3324 x86_mov_reg_imm (code, ins->dreg, size);
3325 ins->sreg1 = ins->dreg;
3327 code = mono_emit_stack_alloc (cfg, code, ins);
3328 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3330 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3331 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3333 if (cfg->param_area)
3334 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3338 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3339 x86_push_reg (code, ins->sreg1);
3340 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3341 (gpointer)"mono_arch_throw_exception");
3342 ins->flags |= MONO_INST_GC_CALLSITE;
3343 ins->backend.pc_offset = code - cfg->native_code;
3347 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3348 x86_push_reg (code, ins->sreg1);
3349 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3350 (gpointer)"mono_arch_rethrow_exception");
3351 ins->flags |= MONO_INST_GC_CALLSITE;
3352 ins->backend.pc_offset = code - cfg->native_code;
3355 case OP_CALL_HANDLER:
3356 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3357 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3358 x86_call_imm (code, 0);
3359 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3360 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3362 case OP_START_HANDLER: {
3363 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3364 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3365 if (cfg->param_area)
3366 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3369 case OP_ENDFINALLY: {
3370 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3371 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3375 case OP_ENDFILTER: {
3376 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3377 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3378 /* The local allocator will put the result into EAX */
3384 ins->inst_c0 = code - cfg->native_code;
3387 if (ins->inst_target_bb->native_offset) {
3388 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3390 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3391 if ((cfg->opt & MONO_OPT_BRANCH) &&
3392 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3393 x86_jump8 (code, 0);
3395 x86_jump32 (code, 0);
3399 x86_jump_reg (code, ins->sreg1);
3418 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3419 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3421 case OP_COND_EXC_EQ:
3422 case OP_COND_EXC_NE_UN:
3423 case OP_COND_EXC_LT:
3424 case OP_COND_EXC_LT_UN:
3425 case OP_COND_EXC_GT:
3426 case OP_COND_EXC_GT_UN:
3427 case OP_COND_EXC_GE:
3428 case OP_COND_EXC_GE_UN:
3429 case OP_COND_EXC_LE:
3430 case OP_COND_EXC_LE_UN:
3431 case OP_COND_EXC_IEQ:
3432 case OP_COND_EXC_INE_UN:
3433 case OP_COND_EXC_ILT:
3434 case OP_COND_EXC_ILT_UN:
3435 case OP_COND_EXC_IGT:
3436 case OP_COND_EXC_IGT_UN:
3437 case OP_COND_EXC_IGE:
3438 case OP_COND_EXC_IGE_UN:
3439 case OP_COND_EXC_ILE:
3440 case OP_COND_EXC_ILE_UN:
3441 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3443 case OP_COND_EXC_OV:
3444 case OP_COND_EXC_NO:
3446 case OP_COND_EXC_NC:
3447 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3449 case OP_COND_EXC_IOV:
3450 case OP_COND_EXC_INO:
3451 case OP_COND_EXC_IC:
3452 case OP_COND_EXC_INC:
3453 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3465 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3473 case OP_CMOV_INE_UN:
3474 case OP_CMOV_IGE_UN:
3475 case OP_CMOV_IGT_UN:
3476 case OP_CMOV_ILE_UN:
3477 case OP_CMOV_ILT_UN:
3478 g_assert (ins->dreg == ins->sreg1);
3479 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3482 /* floating point opcodes */
3484 double d = *(double *)ins->inst_p0;
3486 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3488 } else if (d == 1.0) {
3491 if (cfg->compile_aot) {
3492 guint32 *val = (guint32*)&d;
3493 x86_push_imm (code, val [1]);
3494 x86_push_imm (code, val [0]);
3495 x86_fld_membase (code, X86_ESP, 0, TRUE);
3496 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3499 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3500 x86_fld (code, NULL, TRUE);
3506 float f = *(float *)ins->inst_p0;
3508 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3510 } else if (f == 1.0) {
3513 if (cfg->compile_aot) {
3514 guint32 val = *(guint32*)&f;
3515 x86_push_imm (code, val);
3516 x86_fld_membase (code, X86_ESP, 0, FALSE);
3517 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3520 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3521 x86_fld (code, NULL, FALSE);
3526 case OP_STORER8_MEMBASE_REG:
3527 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3529 case OP_LOADR8_MEMBASE:
3530 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3532 case OP_STORER4_MEMBASE_REG:
3533 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3535 case OP_LOADR4_MEMBASE:
3536 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3538 case OP_ICONV_TO_R4:
3539 x86_push_reg (code, ins->sreg1);
3540 x86_fild_membase (code, X86_ESP, 0, FALSE);
3541 /* Change precision */
3542 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3543 x86_fld_membase (code, X86_ESP, 0, FALSE);
3544 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3546 case OP_ICONV_TO_R8:
3547 x86_push_reg (code, ins->sreg1);
3548 x86_fild_membase (code, X86_ESP, 0, FALSE);
3549 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3551 case OP_ICONV_TO_R_UN:
3552 x86_push_imm (code, 0);
3553 x86_push_reg (code, ins->sreg1);
3554 x86_fild_membase (code, X86_ESP, 0, TRUE);
3555 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3557 case OP_X86_FP_LOAD_I8:
3558 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3560 case OP_X86_FP_LOAD_I4:
3561 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3563 case OP_FCONV_TO_R4:
3564 /* Change precision */
3565 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3566 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3567 x86_fld_membase (code, X86_ESP, 0, FALSE);
3568 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3570 case OP_FCONV_TO_I1:
3571 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3573 case OP_FCONV_TO_U1:
3574 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3576 case OP_FCONV_TO_I2:
3577 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3579 case OP_FCONV_TO_U2:
3580 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3582 case OP_FCONV_TO_I4:
3584 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3586 case OP_FCONV_TO_I8:
3587 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3588 x86_fnstcw_membase(code, X86_ESP, 0);
3589 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3590 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3591 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3592 x86_fldcw_membase (code, X86_ESP, 2);
3593 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3594 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3595 x86_pop_reg (code, ins->dreg);
3596 x86_pop_reg (code, ins->backend.reg3);
3597 x86_fldcw_membase (code, X86_ESP, 0);
3598 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3600 case OP_LCONV_TO_R8_2:
3601 x86_push_reg (code, ins->sreg2);
3602 x86_push_reg (code, ins->sreg1);
3603 x86_fild_membase (code, X86_ESP, 0, TRUE);
3604 /* Change precision */
3605 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3606 x86_fld_membase (code, X86_ESP, 0, TRUE);
3607 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3609 case OP_LCONV_TO_R4_2:
3610 x86_push_reg (code, ins->sreg2);
3611 x86_push_reg (code, ins->sreg1);
3612 x86_fild_membase (code, X86_ESP, 0, TRUE);
3613 /* Change precision */
3614 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3615 x86_fld_membase (code, X86_ESP, 0, FALSE);
3616 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3618 case OP_LCONV_TO_R_UN_2: {
3619 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3622 /* load 64bit integer to FP stack */
3623 x86_push_reg (code, ins->sreg2);
3624 x86_push_reg (code, ins->sreg1);
3625 x86_fild_membase (code, X86_ESP, 0, TRUE);
3627 /* test if lreg is negative */
3628 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3629 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3631 /* add correction constant mn */
3632 if (cfg->compile_aot) {
3633 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3634 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3635 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3636 x86_fld80_membase (code, X86_ESP, 2);
3637 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3639 x86_fld80_mem (code, mn);
3641 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3643 x86_patch (br, code);
3645 /* Change precision */
3646 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3647 x86_fld_membase (code, X86_ESP, 0, TRUE);
3649 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3653 case OP_LCONV_TO_OVF_I:
3654 case OP_LCONV_TO_OVF_I4_2: {
3655 guint8 *br [3], *label [1];
3659 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3661 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3663 /* If the low word top bit is set, see if we are negative */
3664 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3665 /* We are not negative (no top bit set, check for our top word to be zero */
3666 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3667 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3670 /* throw exception */
3671 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3673 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3674 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3675 x86_jump8 (code, 0);
3677 x86_jump32 (code, 0);
3679 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3680 x86_jump32 (code, 0);
3684 x86_patch (br [0], code);
3685 /* our top bit is set, check that top word is 0xfffffff */
3686 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3688 x86_patch (br [1], code);
3689 /* nope, emit exception */
3690 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3691 x86_patch (br [2], label [0]);
3693 if (ins->dreg != ins->sreg1)
3694 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3698 /* Not needed on the fp stack */
3700 case OP_MOVE_F_TO_I4:
3701 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
3702 x86_mov_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, 4);
3704 case OP_MOVE_I4_TO_F:
3705 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
3706 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
3709 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3712 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3715 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3718 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3726 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3731 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3738 * it really doesn't make sense to inline all this code,
3739 * it's here just to show that things may not be as simple
3742 guchar *check_pos, *end_tan, *pop_jump;
3743 x86_push_reg (code, X86_EAX);
3746 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3748 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3749 x86_fstp (code, 0); /* pop the 1.0 */
3751 x86_jump8 (code, 0);
3753 x86_fp_op (code, X86_FADD, 0);
3757 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3759 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3762 x86_patch (pop_jump, code);
3763 x86_fstp (code, 0); /* pop the 1.0 */
3764 x86_patch (check_pos, code);
3765 x86_patch (end_tan, code);
3767 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3768 x86_pop_reg (code, X86_EAX);
3775 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3784 g_assert (cfg->opt & MONO_OPT_CMOV);
3785 g_assert (ins->dreg == ins->sreg1);
3786 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3787 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3790 g_assert (cfg->opt & MONO_OPT_CMOV);
3791 g_assert (ins->dreg == ins->sreg1);
3792 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3793 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3796 g_assert (cfg->opt & MONO_OPT_CMOV);
3797 g_assert (ins->dreg == ins->sreg1);
3798 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3799 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3802 g_assert (cfg->opt & MONO_OPT_CMOV);
3803 g_assert (ins->dreg == ins->sreg1);
3804 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3805 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3811 x86_fxch (code, ins->inst_imm);
3816 x86_push_reg (code, X86_EAX);
3817 /* we need to exchange ST(0) with ST(1) */
3820 /* this requires a loop, because fprem somtimes
3821 * returns a partial remainder */
3823 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3824 /* x86_fprem1 (code); */
3827 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3829 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3835 x86_pop_reg (code, X86_EAX);
3839 if (cfg->opt & MONO_OPT_FCMOV) {
3840 x86_fcomip (code, 1);
3844 /* this overwrites EAX */
3845 EMIT_FPCOMPARE(code);
3846 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3850 if (cfg->opt & MONO_OPT_FCMOV) {
3851 /* zeroing the register at the start results in
3852 * shorter and faster code (we can also remove the widening op)
3854 guchar *unordered_check;
3855 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3856 x86_fcomip (code, 1);
3858 unordered_check = code;
3859 x86_branch8 (code, X86_CC_P, 0, FALSE);
3860 if (ins->opcode == OP_FCEQ) {
3861 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3862 x86_patch (unordered_check, code);
3864 guchar *jump_to_end;
3865 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3867 x86_jump8 (code, 0);
3868 x86_patch (unordered_check, code);
3869 x86_inc_reg (code, ins->dreg);
3870 x86_patch (jump_to_end, code);
3875 if (ins->dreg != X86_EAX)
3876 x86_push_reg (code, X86_EAX);
3878 EMIT_FPCOMPARE(code);
3879 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3880 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3881 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3882 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3884 if (ins->dreg != X86_EAX)
3885 x86_pop_reg (code, X86_EAX);
3889 if (cfg->opt & MONO_OPT_FCMOV) {
3890 /* zeroing the register at the start results in
3891 * shorter and faster code (we can also remove the widening op)
3893 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3894 x86_fcomip (code, 1);
3896 if (ins->opcode == OP_FCLT_UN) {
3897 guchar *unordered_check = code;
3898 guchar *jump_to_end;
3899 x86_branch8 (code, X86_CC_P, 0, FALSE);
3900 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3902 x86_jump8 (code, 0);
3903 x86_patch (unordered_check, code);
3904 x86_inc_reg (code, ins->dreg);
3905 x86_patch (jump_to_end, code);
3907 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3911 if (ins->dreg != X86_EAX)
3912 x86_push_reg (code, X86_EAX);
3914 EMIT_FPCOMPARE(code);
3915 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3916 if (ins->opcode == OP_FCLT_UN) {
3917 guchar *is_not_zero_check, *end_jump;
3918 is_not_zero_check = code;
3919 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3921 x86_jump8 (code, 0);
3922 x86_patch (is_not_zero_check, code);
3923 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3925 x86_patch (end_jump, code);
3927 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3928 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3930 if (ins->dreg != X86_EAX)
3931 x86_pop_reg (code, X86_EAX);
3934 guchar *unordered_check;
3935 guchar *jump_to_end;
3936 if (cfg->opt & MONO_OPT_FCMOV) {
3937 /* zeroing the register at the start results in
3938 * shorter and faster code (we can also remove the widening op)
3940 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3941 x86_fcomip (code, 1);
3943 unordered_check = code;
3944 x86_branch8 (code, X86_CC_P, 0, FALSE);
3945 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3946 x86_patch (unordered_check, code);
3949 if (ins->dreg != X86_EAX)
3950 x86_push_reg (code, X86_EAX);
3952 EMIT_FPCOMPARE(code);
3953 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3954 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3955 unordered_check = code;
3956 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3958 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3959 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3960 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3962 x86_jump8 (code, 0);
3963 x86_patch (unordered_check, code);
3964 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3965 x86_patch (jump_to_end, code);
3967 if (ins->dreg != X86_EAX)
3968 x86_pop_reg (code, X86_EAX);
3973 if (cfg->opt & MONO_OPT_FCMOV) {
3974 /* zeroing the register at the start results in
3975 * shorter and faster code (we can also remove the widening op)
3977 guchar *unordered_check;
3978 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3979 x86_fcomip (code, 1);
3981 if (ins->opcode == OP_FCGT) {
3982 unordered_check = code;
3983 x86_branch8 (code, X86_CC_P, 0, FALSE);
3984 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3985 x86_patch (unordered_check, code);
3987 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3991 if (ins->dreg != X86_EAX)
3992 x86_push_reg (code, X86_EAX);
3994 EMIT_FPCOMPARE(code);
3995 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3996 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3997 if (ins->opcode == OP_FCGT_UN) {
3998 guchar *is_not_zero_check, *end_jump;
3999 is_not_zero_check = code;
4000 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4002 x86_jump8 (code, 0);
4003 x86_patch (is_not_zero_check, code);
4004 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4006 x86_patch (end_jump, code);
4008 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4009 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4011 if (ins->dreg != X86_EAX)
4012 x86_pop_reg (code, X86_EAX);
4015 guchar *unordered_check;
4016 guchar *jump_to_end;
4017 if (cfg->opt & MONO_OPT_FCMOV) {
4018 /* zeroing the register at the start results in
4019 * shorter and faster code (we can also remove the widening op)
4021 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4022 x86_fcomip (code, 1);
4024 unordered_check = code;
4025 x86_branch8 (code, X86_CC_P, 0, FALSE);
4026 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4027 x86_patch (unordered_check, code);
4030 if (ins->dreg != X86_EAX)
4031 x86_push_reg (code, X86_EAX);
4033 EMIT_FPCOMPARE(code);
4034 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4035 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4036 unordered_check = code;
4037 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4039 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4040 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4041 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4043 x86_jump8 (code, 0);
4044 x86_patch (unordered_check, code);
4045 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4046 x86_patch (jump_to_end, code);
4048 if (ins->dreg != X86_EAX)
4049 x86_pop_reg (code, X86_EAX);
4053 if (cfg->opt & MONO_OPT_FCMOV) {
4054 guchar *jump = code;
4055 x86_branch8 (code, X86_CC_P, 0, TRUE);
4056 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4057 x86_patch (jump, code);
4060 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4061 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4064 /* Branch if C013 != 100 */
4065 if (cfg->opt & MONO_OPT_FCMOV) {
4066 /* branch if !ZF or (PF|CF) */
4067 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4068 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4069 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4072 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4073 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4076 if (cfg->opt & MONO_OPT_FCMOV) {
4077 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4080 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4083 if (cfg->opt & MONO_OPT_FCMOV) {
4084 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4085 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4088 if (ins->opcode == OP_FBLT_UN) {
4089 guchar *is_not_zero_check, *end_jump;
4090 is_not_zero_check = code;
4091 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4093 x86_jump8 (code, 0);
4094 x86_patch (is_not_zero_check, code);
4095 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4097 x86_patch (end_jump, code);
4099 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4103 if (cfg->opt & MONO_OPT_FCMOV) {
4104 if (ins->opcode == OP_FBGT) {
4107 /* skip branch if C1=1 */
4109 x86_branch8 (code, X86_CC_P, 0, FALSE);
4110 /* branch if (C0 | C3) = 1 */
4111 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4112 x86_patch (br1, code);
4114 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4118 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4119 if (ins->opcode == OP_FBGT_UN) {
4120 guchar *is_not_zero_check, *end_jump;
4121 is_not_zero_check = code;
4122 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4124 x86_jump8 (code, 0);
4125 x86_patch (is_not_zero_check, code);
4126 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4128 x86_patch (end_jump, code);
4130 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4133 /* Branch if C013 == 100 or 001 */
4134 if (cfg->opt & MONO_OPT_FCMOV) {
4137 /* skip branch if C1=1 */
4139 x86_branch8 (code, X86_CC_P, 0, FALSE);
4140 /* branch if (C0 | C3) = 1 */
4141 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4142 x86_patch (br1, code);
4145 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4146 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4147 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4148 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4151 /* Branch if C013 == 000 */
4152 if (cfg->opt & MONO_OPT_FCMOV) {
4153 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4156 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4159 /* Branch if C013=000 or 100 */
4160 if (cfg->opt & MONO_OPT_FCMOV) {
4163 /* skip branch if C1=1 */
4165 x86_branch8 (code, X86_CC_P, 0, FALSE);
4166 /* branch if C0=0 */
4167 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4168 x86_patch (br1, code);
4171 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4172 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4173 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4176 /* Branch if C013 != 001 */
4177 if (cfg->opt & MONO_OPT_FCMOV) {
4178 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4179 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4182 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4183 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4187 x86_push_reg (code, X86_EAX);
4190 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4191 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4192 x86_pop_reg (code, X86_EAX);
4194 /* Have to clean up the fp stack before throwing the exception */
4196 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4199 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4201 x86_patch (br1, code);
4205 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4208 case OP_TLS_GET_REG: {
4209 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4213 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4216 case OP_TLS_SET_REG: {
4217 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4220 case OP_MEMORY_BARRIER: {
4221 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4222 x86_prefix (code, X86_LOCK_PREFIX);
4223 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4227 case OP_ATOMIC_ADD_I4: {
4228 int dreg = ins->dreg;
4230 g_assert (cfg->has_atomic_add_i4);
4232 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4233 if (ins->sreg2 == dreg) {
4234 if (dreg == X86_EBX) {
4236 if (ins->inst_basereg == X86_EDI)
4240 if (ins->inst_basereg == X86_EBX)
4243 } else if (ins->inst_basereg == dreg) {
4244 if (dreg == X86_EBX) {
4246 if (ins->sreg2 == X86_EDI)
4250 if (ins->sreg2 == X86_EBX)
4255 if (dreg != ins->dreg) {
4256 x86_push_reg (code, dreg);
4259 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4260 x86_prefix (code, X86_LOCK_PREFIX);
4261 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4262 /* dreg contains the old value, add with sreg2 value */
4263 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4265 if (ins->dreg != dreg) {
4266 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4267 x86_pop_reg (code, dreg);
4272 case OP_ATOMIC_EXCHANGE_I4: {
4274 int sreg2 = ins->sreg2;
4275 int breg = ins->inst_basereg;
4277 g_assert (cfg->has_atomic_exchange_i4);
4279 /* cmpxchg uses eax as comperand, need to make sure we can use it
4280 * hack to overcome limits in x86 reg allocator
4281 * (req: dreg == eax and sreg2 != eax and breg != eax)
4283 g_assert (ins->dreg == X86_EAX);
4285 /* We need the EAX reg for the cmpxchg */
4286 if (ins->sreg2 == X86_EAX) {
4287 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4288 x86_push_reg (code, sreg2);
4289 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4292 if (breg == X86_EAX) {
4293 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4294 x86_push_reg (code, breg);
4295 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4298 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4300 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4301 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4302 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4303 x86_patch (br [1], br [0]);
4305 if (breg != ins->inst_basereg)
4306 x86_pop_reg (code, breg);
4308 if (ins->sreg2 != sreg2)
4309 x86_pop_reg (code, sreg2);
4313 case OP_ATOMIC_CAS_I4: {
4314 g_assert (ins->dreg == X86_EAX);
4315 g_assert (ins->sreg3 == X86_EAX);
4316 g_assert (ins->sreg1 != X86_EAX);
4317 g_assert (ins->sreg1 != ins->sreg2);
4319 x86_prefix (code, X86_LOCK_PREFIX);
4320 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4323 case OP_ATOMIC_LOAD_I1: {
4324 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4327 case OP_ATOMIC_LOAD_U1: {
4328 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4331 case OP_ATOMIC_LOAD_I2: {
4332 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4335 case OP_ATOMIC_LOAD_U2: {
4336 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4339 case OP_ATOMIC_LOAD_I4:
4340 case OP_ATOMIC_LOAD_U4: {
4341 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4344 case OP_ATOMIC_LOAD_R4:
4345 case OP_ATOMIC_LOAD_R8: {
4346 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4349 case OP_ATOMIC_STORE_I1:
4350 case OP_ATOMIC_STORE_U1:
4351 case OP_ATOMIC_STORE_I2:
4352 case OP_ATOMIC_STORE_U2:
4353 case OP_ATOMIC_STORE_I4:
4354 case OP_ATOMIC_STORE_U4: {
4357 switch (ins->opcode) {
4358 case OP_ATOMIC_STORE_I1:
4359 case OP_ATOMIC_STORE_U1:
4362 case OP_ATOMIC_STORE_I2:
4363 case OP_ATOMIC_STORE_U2:
4366 case OP_ATOMIC_STORE_I4:
4367 case OP_ATOMIC_STORE_U4:
4372 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4374 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4378 case OP_ATOMIC_STORE_R4:
4379 case OP_ATOMIC_STORE_R8: {
4380 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4382 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4386 case OP_CARD_TABLE_WBARRIER: {
4387 int ptr = ins->sreg1;
4388 int value = ins->sreg2;
4390 int nursery_shift, card_table_shift;
4391 gpointer card_table_mask;
4392 size_t nursery_size;
4393 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4394 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4395 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4398 * We need one register we can clobber, we choose EDX and make sreg1
4399 * fixed EAX to work around limitations in the local register allocator.
4400 * sreg2 might get allocated to EDX, but that is not a problem since
4401 * we use it before clobbering EDX.
4403 g_assert (ins->sreg1 == X86_EAX);
4406 * This is the code we produce:
4409 * edx >>= nursery_shift
4410 * cmp edx, (nursery_start >> nursery_shift)
4413 * edx >>= card_table_shift
4414 * card_table[edx] = 1
4418 if (card_table_nursery_check) {
4419 if (value != X86_EDX)
4420 x86_mov_reg_reg (code, X86_EDX, value, 4);
4421 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4422 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4423 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4425 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4426 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4427 if (card_table_mask)
4428 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4429 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4430 if (card_table_nursery_check)
4431 x86_patch (br, code);
4434 #ifdef MONO_ARCH_SIMD_INTRINSICS
4436 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4439 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4442 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4445 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4448 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4451 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4454 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4455 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4458 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4461 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4464 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4467 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4470 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4473 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4476 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4479 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4482 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4485 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4488 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4491 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4494 case OP_PSHUFLEW_HIGH:
4495 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4496 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4498 case OP_PSHUFLEW_LOW:
4499 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4500 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4503 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4504 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4507 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4508 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4511 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4512 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4516 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4519 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4522 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4525 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4528 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4531 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4534 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4535 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4538 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4541 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4544 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4547 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4550 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4553 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4556 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4559 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4562 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4565 case OP_EXTRACT_MASK:
4566 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4570 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4573 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4576 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4580 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4583 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4586 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4589 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4593 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4596 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4599 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4602 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4606 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4609 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4612 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4616 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4619 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4622 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4626 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4629 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4633 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4636 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4639 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4643 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4646 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4649 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4653 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4656 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4659 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4662 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4666 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4669 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4672 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4675 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4678 case OP_PSUM_ABS_DIFF:
4679 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4682 case OP_UNPACK_LOWB:
4683 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4685 case OP_UNPACK_LOWW:
4686 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4688 case OP_UNPACK_LOWD:
4689 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4691 case OP_UNPACK_LOWQ:
4692 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4694 case OP_UNPACK_LOWPS:
4695 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4697 case OP_UNPACK_LOWPD:
4698 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4701 case OP_UNPACK_HIGHB:
4702 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4704 case OP_UNPACK_HIGHW:
4705 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4707 case OP_UNPACK_HIGHD:
4708 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4710 case OP_UNPACK_HIGHQ:
4711 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4713 case OP_UNPACK_HIGHPS:
4714 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4716 case OP_UNPACK_HIGHPD:
4717 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4721 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4724 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4727 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4730 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4733 case OP_PADDB_SAT_UN:
4734 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4736 case OP_PSUBB_SAT_UN:
4737 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4739 case OP_PADDW_SAT_UN:
4740 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4742 case OP_PSUBW_SAT_UN:
4743 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4747 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4750 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4753 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4756 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4760 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4763 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4766 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4768 case OP_PMULW_HIGH_UN:
4769 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4772 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4776 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4779 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4783 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4786 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4790 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4793 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4797 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4800 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4804 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4807 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4811 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4814 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4818 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4821 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4825 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4828 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4832 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4835 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4839 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4841 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4842 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4846 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4848 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4849 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4853 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4855 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4856 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4860 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4862 case OP_EXTRACTX_U2:
4863 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4865 case OP_INSERTX_U1_SLOW:
4866 /*sreg1 is the extracted ireg (scratch)
4867 /sreg2 is the to be inserted ireg (scratch)
4868 /dreg is the xreg to receive the value*/
4870 /*clear the bits from the extracted word*/
4871 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4872 /*shift the value to insert if needed*/
4873 if (ins->inst_c0 & 1)
4874 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4875 /*join them together*/
4876 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4877 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4879 case OP_INSERTX_I4_SLOW:
4880 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4881 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4882 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4885 case OP_INSERTX_R4_SLOW:
4886 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4887 /*TODO if inst_c0 == 0 use movss*/
4888 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4889 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4891 case OP_INSERTX_R8_SLOW:
4892 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4893 if (cfg->verbose_level)
4894 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4896 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4898 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4901 case OP_STOREX_MEMBASE_REG:
4902 case OP_STOREX_MEMBASE:
4903 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4905 case OP_LOADX_MEMBASE:
4906 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4908 case OP_LOADX_ALIGNED_MEMBASE:
4909 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4911 case OP_STOREX_ALIGNED_MEMBASE_REG:
4912 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4914 case OP_STOREX_NTA_MEMBASE_REG:
4915 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4917 case OP_PREFETCH_MEMBASE:
4918 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4922 /*FIXME the peephole pass should have killed this*/
4923 if (ins->dreg != ins->sreg1)
4924 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4927 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4930 case OP_FCONV_TO_R8_X:
4931 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4932 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4935 case OP_XCONV_R8_TO_I4:
4936 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4937 switch (ins->backend.source_opcode) {
4938 case OP_FCONV_TO_I1:
4939 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4941 case OP_FCONV_TO_U1:
4942 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4944 case OP_FCONV_TO_I2:
4945 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4947 case OP_FCONV_TO_U2:
4948 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4954 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4955 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4956 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4957 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4958 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4959 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4962 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4963 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4964 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4967 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4968 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4971 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4972 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4973 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4976 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4977 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4978 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4982 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4985 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4988 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4991 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4994 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4997 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
5000 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
5003 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
5007 case OP_LIVERANGE_START: {
5008 if (cfg->verbose_level > 1)
5009 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5010 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5013 case OP_LIVERANGE_END: {
5014 if (cfg->verbose_level > 1)
5015 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5016 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5019 case OP_NACL_GC_SAFE_POINT: {
5020 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
5021 if (cfg->compile_aot)
5022 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5026 x86_test_mem_imm8 (code, (gpointer)&__nacl_thread_suspension_needed, 0xFFFFFFFF);
5027 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
5028 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5029 x86_patch (br[0], code);
5034 case OP_GC_LIVENESS_DEF:
5035 case OP_GC_LIVENESS_USE:
5036 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5037 ins->backend.pc_offset = code - cfg->native_code;
5039 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5040 ins->backend.pc_offset = code - cfg->native_code;
5041 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5044 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
5047 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
5050 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
5051 g_assert_not_reached ();
5054 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
5055 #ifndef __native_client_codegen__
5056 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5057 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5058 g_assert_not_reached ();
5059 #endif /* __native_client_codegen__ */
5065 cfg->code_len = code - cfg->native_code;
5068 #endif /* DISABLE_JIT */
5071 mono_arch_register_lowlevel_calls (void)
5076 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
5078 MonoJumpInfo *patch_info;
5079 gboolean compile_aot = !run_cctors;
5081 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5082 unsigned char *ip = patch_info->ip.i + code;
5083 const unsigned char *target;
5086 switch (patch_info->type) {
5087 case MONO_PATCH_INFO_BB:
5088 case MONO_PATCH_INFO_LABEL:
5091 /* No need to patch these */
5096 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5098 switch (patch_info->type) {
5099 case MONO_PATCH_INFO_IP:
5100 *((gconstpointer *)(ip)) = target;
5102 case MONO_PATCH_INFO_CLASS_INIT: {
5104 /* Might already been changed to a nop */
5105 x86_call_code (code, 0);
5106 x86_patch (ip, target);
5109 case MONO_PATCH_INFO_ABS:
5110 case MONO_PATCH_INFO_METHOD:
5111 case MONO_PATCH_INFO_METHOD_JUMP:
5112 case MONO_PATCH_INFO_INTERNAL_METHOD:
5113 case MONO_PATCH_INFO_BB:
5114 case MONO_PATCH_INFO_LABEL:
5115 case MONO_PATCH_INFO_RGCTX_FETCH:
5116 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
5117 case MONO_PATCH_INFO_MONITOR_ENTER:
5118 case MONO_PATCH_INFO_MONITOR_ENTER_V4:
5119 case MONO_PATCH_INFO_MONITOR_EXIT:
5120 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5121 #if defined(__native_client_codegen__) && defined(__native_client__)
5122 if (nacl_is_code_address (code)) {
5123 /* For tail calls, code is patched after being installed */
5124 /* but not through the normal "patch callsite" method. */
5125 unsigned char buf[kNaClAlignment];
5126 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5127 unsigned char *_target = target;
5129 /* All patch targets modified in x86_patch */
5130 /* are IP relative. */
5131 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5132 memcpy (buf, aligned_code, kNaClAlignment);
5133 /* Patch a temp buffer of bundle size, */
5134 /* then install to actual location. */
5135 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5136 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5137 g_assert (ret == 0);
5140 x86_patch (ip, target);
5143 x86_patch (ip, target);
5146 case MONO_PATCH_INFO_NONE:
5148 case MONO_PATCH_INFO_R4:
5149 case MONO_PATCH_INFO_R8: {
5150 guint32 offset = mono_arch_get_patch_offset (ip);
5151 *((gconstpointer *)(ip + offset)) = target;
5155 guint32 offset = mono_arch_get_patch_offset (ip);
5156 #if !defined(__native_client__)
5157 *((gconstpointer *)(ip + offset)) = target;
5159 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5167 static G_GNUC_UNUSED void
5168 stack_unaligned (MonoMethod *m, gpointer caller)
5170 printf ("%s\n", mono_method_full_name (m, TRUE));
5171 g_assert_not_reached ();
5175 mono_arch_emit_prolog (MonoCompile *cfg)
5177 MonoMethod *method = cfg->method;
5179 MonoMethodSignature *sig;
5181 int alloc_size, pos, max_offset, i, cfa_offset;
5183 gboolean need_stack_frame;
5184 #ifdef __native_client_codegen__
5185 guint alignment_check;
5188 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5190 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5191 cfg->code_size += 512;
5193 #if defined(__default_codegen__)
5194 code = cfg->native_code = g_malloc (cfg->code_size);
5195 #elif defined(__native_client_codegen__)
5196 /* native_code_alloc is not 32-byte aligned, native_code is. */
5197 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5198 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5200 /* Align native_code to next nearest kNaclAlignment byte. */
5201 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5202 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5204 code = cfg->native_code;
5206 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5207 g_assert(alignment_check == 0);
5214 /* Check that the stack is aligned on osx */
5215 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5216 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5217 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5219 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5220 x86_push_membase (code, X86_ESP, 0);
5221 x86_push_imm (code, cfg->method);
5222 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5223 x86_call_reg (code, X86_EAX);
5224 x86_patch (br [0], code);
5228 /* Offset between RSP and the CFA */
5232 cfa_offset = sizeof (gpointer);
5233 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5234 // IP saved at CFA - 4
5235 /* There is no IP reg on x86 */
5236 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5237 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5239 need_stack_frame = needs_stack_frame (cfg);
5241 if (need_stack_frame) {
5242 x86_push_reg (code, X86_EBP);
5243 cfa_offset += sizeof (gpointer);
5244 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5245 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5246 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5247 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5248 /* These are handled automatically by the stack marking code */
5249 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5251 cfg->frame_reg = X86_ESP;
5254 cfg->stack_offset += cfg->param_area;
5255 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5257 alloc_size = cfg->stack_offset;
5260 if (!method->save_lmf) {
5261 if (cfg->used_int_regs & (1 << X86_EBX)) {
5262 x86_push_reg (code, X86_EBX);
5264 cfa_offset += sizeof (gpointer);
5265 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5266 /* These are handled automatically by the stack marking code */
5267 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5270 if (cfg->used_int_regs & (1 << X86_EDI)) {
5271 x86_push_reg (code, X86_EDI);
5273 cfa_offset += sizeof (gpointer);
5274 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5275 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5278 if (cfg->used_int_regs & (1 << X86_ESI)) {
5279 x86_push_reg (code, X86_ESI);
5281 cfa_offset += sizeof (gpointer);
5282 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5283 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5289 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5290 if (mono_do_x86_stack_align && need_stack_frame) {
5291 int tot = alloc_size + pos + 4; /* ret ip */
5292 if (need_stack_frame)
5294 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5296 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5297 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5298 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5302 cfg->arch.sp_fp_offset = alloc_size + pos;
5305 /* See mono_emit_stack_alloc */
5306 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5307 guint32 remaining_size = alloc_size;
5308 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5309 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5310 guint32 offset = code - cfg->native_code;
5311 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5312 while (required_code_size >= (cfg->code_size - offset))
5313 cfg->code_size *= 2;
5314 cfg->native_code = mono_realloc_native_code(cfg);
5315 code = cfg->native_code + offset;
5316 cfg->stat_code_reallocs++;
5318 while (remaining_size >= 0x1000) {
5319 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5320 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5321 remaining_size -= 0x1000;
5324 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5326 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5329 g_assert (need_stack_frame);
5332 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5333 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5334 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5337 #if DEBUG_STACK_ALIGNMENT
5338 /* check the stack is aligned */
5339 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5340 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5341 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5342 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5343 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5344 x86_breakpoint (code);
5348 /* compute max_offset in order to use short forward jumps */
5350 if (cfg->opt & MONO_OPT_BRANCH) {
5351 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5353 bb->max_offset = max_offset;
5355 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5357 /* max alignment for loops */
5358 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5359 max_offset += LOOP_ALIGNMENT;
5360 #ifdef __native_client_codegen__
5361 /* max alignment for native client */
5362 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5363 max_offset += kNaClAlignment;
5365 MONO_BB_FOR_EACH_INS (bb, ins) {
5366 if (ins->opcode == OP_LABEL)
5367 ins->inst_c1 = max_offset;
5368 #ifdef __native_client_codegen__
5369 switch (ins->opcode)
5381 case OP_VOIDCALL_REG:
5383 case OP_FCALL_MEMBASE:
5384 case OP_LCALL_MEMBASE:
5385 case OP_VCALL_MEMBASE:
5386 case OP_VCALL2_MEMBASE:
5387 case OP_VOIDCALL_MEMBASE:
5388 case OP_CALL_MEMBASE:
5389 max_offset += kNaClAlignment;
5392 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5395 #endif /* __native_client_codegen__ */
5396 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5401 /* store runtime generic context */
5402 if (cfg->rgctx_var) {
5403 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5405 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5408 if (method->save_lmf)
5409 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5411 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5412 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5414 /* load arguments allocated to register from the stack */
5415 sig = mono_method_signature (method);
5418 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5419 inst = cfg->args [pos];
5420 if (inst->opcode == OP_REGVAR) {
5421 g_assert (need_stack_frame);
5422 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5423 if (cfg->verbose_level > 2)
5424 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5429 cfg->code_len = code - cfg->native_code;
5431 g_assert (cfg->code_len < cfg->code_size);
5437 mono_arch_emit_epilog (MonoCompile *cfg)
5439 MonoMethod *method = cfg->method;
5440 MonoMethodSignature *sig = mono_method_signature (method);
5442 guint32 stack_to_pop;
5444 int max_epilog_size = 16;
5446 gboolean need_stack_frame = needs_stack_frame (cfg);
5448 if (cfg->method->save_lmf)
5449 max_epilog_size += 128;
5451 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5452 cfg->code_size *= 2;
5453 cfg->native_code = mono_realloc_native_code(cfg);
5454 cfg->stat_code_reallocs++;
5457 code = cfg->native_code + cfg->code_len;
5459 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5460 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5462 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5465 if (method->save_lmf) {
5466 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5468 gboolean supported = FALSE;
5470 if (cfg->compile_aot) {
5471 #if defined(__APPLE__) || defined(__linux__)
5474 } else if (mono_get_jit_tls_offset () != -1) {
5478 /* check if we need to restore protection of the stack after a stack overflow */
5480 if (cfg->compile_aot) {
5481 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5483 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5485 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5488 /* we load the value in a separate instruction: this mechanism may be
5489 * used later as a safer way to do thread interruption
5491 x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5492 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5494 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5495 /* note that the call trampoline will preserve eax/edx */
5496 x86_call_reg (code, X86_ECX);
5497 x86_patch (patch, code);
5499 /* FIXME: maybe save the jit tls in the prolog */
5502 /* restore caller saved regs */
5503 if (cfg->used_int_regs & (1 << X86_EBX)) {
5504 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5507 if (cfg->used_int_regs & (1 << X86_EDI)) {
5508 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5510 if (cfg->used_int_regs & (1 << X86_ESI)) {
5511 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5514 /* EBP is restored by LEAVE */
5516 for (i = 0; i < X86_NREG; ++i) {
5517 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5523 g_assert (need_stack_frame);
5524 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5528 g_assert (need_stack_frame);
5529 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5532 if (cfg->used_int_regs & (1 << X86_ESI)) {
5533 x86_pop_reg (code, X86_ESI);
5535 if (cfg->used_int_regs & (1 << X86_EDI)) {
5536 x86_pop_reg (code, X86_EDI);
5538 if (cfg->used_int_regs & (1 << X86_EBX)) {
5539 x86_pop_reg (code, X86_EBX);
5543 /* Load returned vtypes into registers if needed */
5544 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5545 if (cinfo->ret.storage == ArgValuetypeInReg) {
5546 for (quad = 0; quad < 2; quad ++) {
5547 switch (cinfo->ret.pair_storage [quad]) {
5549 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5551 case ArgOnFloatFpStack:
5552 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5554 case ArgOnDoubleFpStack:
5555 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5560 g_assert_not_reached ();
5565 if (need_stack_frame)
5568 if (CALLCONV_IS_STDCALL (sig)) {
5569 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5571 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5572 } else if (cinfo->callee_stack_pop)
5573 stack_to_pop = cinfo->callee_stack_pop;
5578 g_assert (need_stack_frame);
5579 x86_ret_imm (code, stack_to_pop);
5584 cfg->code_len = code - cfg->native_code;
5586 g_assert (cfg->code_len < cfg->code_size);
5590 mono_arch_emit_exceptions (MonoCompile *cfg)
5592 MonoJumpInfo *patch_info;
5595 MonoClass *exc_classes [16];
5596 guint8 *exc_throw_start [16], *exc_throw_end [16];
5600 /* Compute needed space */
5601 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5602 if (patch_info->type == MONO_PATCH_INFO_EXC)
5607 * make sure we have enough space for exceptions
5608 * 16 is the size of two push_imm instructions and a call
5610 if (cfg->compile_aot)
5611 code_size = exc_count * 32;
5613 code_size = exc_count * 16;
5615 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5616 cfg->code_size *= 2;
5617 cfg->native_code = mono_realloc_native_code(cfg);
5618 cfg->stat_code_reallocs++;
5621 code = cfg->native_code + cfg->code_len;
5624 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5625 switch (patch_info->type) {
5626 case MONO_PATCH_INFO_EXC: {
5627 MonoClass *exc_class;
5631 x86_patch (patch_info->ip.i + cfg->native_code, code);
5633 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5634 g_assert (exc_class);
5635 throw_ip = patch_info->ip.i;
5637 /* Find a throw sequence for the same exception class */
5638 for (i = 0; i < nthrows; ++i)
5639 if (exc_classes [i] == exc_class)
5642 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5643 x86_jump_code (code, exc_throw_start [i]);
5644 patch_info->type = MONO_PATCH_INFO_NONE;
5649 /* Compute size of code following the push <OFFSET> */
5650 #if defined(__default_codegen__)
5652 #elif defined(__native_client_codegen__)
5653 code = mono_nacl_align (code);
5654 size = kNaClAlignment;
5656 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5658 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5659 /* Use the shorter form */
5661 x86_push_imm (code, 0);
5665 x86_push_imm (code, 0xf0f0f0f0);
5670 exc_classes [nthrows] = exc_class;
5671 exc_throw_start [nthrows] = code;
5674 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5675 patch_info->data.name = "mono_arch_throw_corlib_exception";
5676 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5677 patch_info->ip.i = code - cfg->native_code;
5678 x86_call_code (code, 0);
5679 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5684 exc_throw_end [nthrows] = code;
5696 cfg->code_len = code - cfg->native_code;
5698 g_assert (cfg->code_len < cfg->code_size);
5702 mono_arch_flush_icache (guint8 *code, gint size)
5708 mono_arch_flush_register_windows (void)
5713 mono_arch_is_inst_imm (gint64 imm)
5719 mono_arch_finish_init (void)
5721 if (!g_getenv ("MONO_NO_TLS")) {
5722 #ifndef TARGET_WIN32
5724 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5731 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5735 // Linear handler, the bsearch head compare is shorter
5736 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5737 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5738 // x86_patch(ins,target)
5739 //[1 + 5] x86_jump_mem(inst,mem)
5742 #if defined(__default_codegen__)
5743 #define BR_SMALL_SIZE 2
5744 #define BR_LARGE_SIZE 5
5745 #elif defined(__native_client_codegen__)
5746 /* I suspect the size calculation below is actually incorrect. */
5747 /* TODO: fix the calculation that uses these sizes. */
5748 #define BR_SMALL_SIZE 16
5749 #define BR_LARGE_SIZE 12
5750 #endif /*__native_client_codegen__*/
5751 #define JUMP_IMM_SIZE 6
5752 #define ENABLE_WRONG_METHOD_CHECK 0
5756 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5758 int i, distance = 0;
5759 for (i = start; i < target; ++i)
5760 distance += imt_entries [i]->chunk_size;
5765 * LOCKING: called with the domain lock held
5768 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5769 gpointer fail_tramp)
5773 guint8 *code, *start;
5775 for (i = 0; i < count; ++i) {
5776 MonoIMTCheckItem *item = imt_entries [i];
5777 if (item->is_equals) {
5778 if (item->check_target_idx) {
5779 if (!item->compare_done)
5780 item->chunk_size += CMP_SIZE;
5781 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5784 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5786 item->chunk_size += JUMP_IMM_SIZE;
5787 #if ENABLE_WRONG_METHOD_CHECK
5788 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5793 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5794 imt_entries [item->check_target_idx]->compare_done = TRUE;
5796 size += item->chunk_size;
5798 #if defined(__native_client__) && defined(__native_client_codegen__)
5799 /* In Native Client, we don't re-use thunks, allocate from the */
5800 /* normal code manager paths. */
5801 size = NACL_BUNDLE_ALIGN_UP (size);
5802 code = mono_domain_code_reserve (domain, size);
5805 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5807 code = mono_domain_code_reserve (domain, size);
5810 for (i = 0; i < count; ++i) {
5811 MonoIMTCheckItem *item = imt_entries [i];
5812 item->code_target = code;
5813 if (item->is_equals) {
5814 if (item->check_target_idx) {
5815 if (!item->compare_done)
5816 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5817 item->jmp_code = code;
5818 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5819 if (item->has_target_code)
5820 x86_jump_code (code, item->value.target_code);
5822 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5825 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5826 item->jmp_code = code;
5827 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5828 if (item->has_target_code)
5829 x86_jump_code (code, item->value.target_code);
5831 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5832 x86_patch (item->jmp_code, code);
5833 x86_jump_code (code, fail_tramp);
5834 item->jmp_code = NULL;
5836 /* enable the commented code to assert on wrong method */
5837 #if ENABLE_WRONG_METHOD_CHECK
5838 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5839 item->jmp_code = code;
5840 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5842 if (item->has_target_code)
5843 x86_jump_code (code, item->value.target_code);
5845 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5846 #if ENABLE_WRONG_METHOD_CHECK
5847 x86_patch (item->jmp_code, code);
5848 x86_breakpoint (code);
5849 item->jmp_code = NULL;
5854 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5855 item->jmp_code = code;
5856 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5857 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5859 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5862 /* patch the branches to get to the target items */
5863 for (i = 0; i < count; ++i) {
5864 MonoIMTCheckItem *item = imt_entries [i];
5865 if (item->jmp_code) {
5866 if (item->check_target_idx) {
5867 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5873 mono_stats.imt_thunks_size += code - start;
5874 g_assert (code - start <= size);
5878 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5879 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5883 if (mono_jit_map_is_enabled ()) {
5886 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5888 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5889 mono_emit_jit_tramp (start, code - start, buff);
5893 nacl_domain_code_validate (domain, &start, size, &code);
5894 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
5900 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5902 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5906 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5908 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5912 mono_arch_get_cie_program (void)
5916 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5917 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5923 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5925 MonoInst *ins = NULL;
5928 if (cmethod->klass == mono_defaults.math_class) {
5929 if (strcmp (cmethod->name, "Sin") == 0) {
5931 } else if (strcmp (cmethod->name, "Cos") == 0) {
5933 } else if (strcmp (cmethod->name, "Tan") == 0) {
5935 } else if (strcmp (cmethod->name, "Atan") == 0) {
5937 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5939 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5941 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5945 if (opcode && fsig->param_count == 1) {
5946 MONO_INST_NEW (cfg, ins, opcode);
5947 ins->type = STACK_R8;
5948 ins->dreg = mono_alloc_freg (cfg);
5949 ins->sreg1 = args [0]->dreg;
5950 MONO_ADD_INS (cfg->cbb, ins);
5953 if (cfg->opt & MONO_OPT_CMOV) {
5956 if (strcmp (cmethod->name, "Min") == 0) {
5957 if (fsig->params [0]->type == MONO_TYPE_I4)
5959 } else if (strcmp (cmethod->name, "Max") == 0) {
5960 if (fsig->params [0]->type == MONO_TYPE_I4)
5964 if (opcode && fsig->param_count == 2) {
5965 MONO_INST_NEW (cfg, ins, opcode);
5966 ins->type = STACK_I4;
5967 ins->dreg = mono_alloc_ireg (cfg);
5968 ins->sreg1 = args [0]->dreg;
5969 ins->sreg2 = args [1]->dreg;
5970 MONO_ADD_INS (cfg->cbb, ins);
5975 /* OP_FREM is not IEEE compatible */
5976 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
5977 MONO_INST_NEW (cfg, ins, OP_FREM);
5978 ins->inst_i0 = args [0];
5979 ins->inst_i1 = args [1];
5988 mono_arch_print_tree (MonoInst *tree, int arity)
5994 mono_arch_get_patch_offset (guint8 *code)
5996 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5998 else if (code [0] == 0xba)
6000 else if (code [0] == 0x68)
6003 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
6004 /* push <OFFSET>(<REG>) */
6006 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
6007 /* call *<OFFSET>(<REG>) */
6009 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
6012 else if ((code [0] == 0x58) && (code [1] == 0x05))
6013 /* pop %eax; add <OFFSET>, %eax */
6015 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6016 /* pop <REG>; add <OFFSET>, <REG> */
6018 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6019 /* mov <REG>, imm */
6022 g_assert_not_reached ();
6028 * mono_breakpoint_clean_code:
6030 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6031 * breakpoints in the original code, they are removed in the copy.
6033 * Returns TRUE if no sw breakpoint was present.
6036 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6039 * If method_start is non-NULL we need to perform bound checks, since we access memory
6040 * at code - offset we could go before the start of the method and end up in a different
6041 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6044 if (!method_start || code - offset >= method_start) {
6045 memcpy (buf, code - offset, size);
6047 int diff = code - method_start;
6048 memset (buf, 0, size);
6049 memcpy (buf + offset - diff, method_start, diff + size - offset);
6055 * mono_x86_get_this_arg_offset:
6057 * Return the offset of the stack location where this is passed during a virtual
6061 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6067 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6069 guint32 esp = regs [X86_ESP];
6076 * The stack looks like:
6080 res = ((MonoObject**)esp) [0];
6084 #define MAX_ARCH_DELEGATE_PARAMS 10
6087 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6089 guint8 *code, *start;
6090 int code_reserve = 64;
6093 * The stack contains:
6099 start = code = mono_global_codeman_reserve (code_reserve);
6101 /* Replace the this argument with the target */
6102 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6103 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6104 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6105 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6107 g_assert ((code - start) < code_reserve);
6110 /* 8 for mov_reg and jump, plus 8 for each parameter */
6111 #ifdef __native_client_codegen__
6112 /* TODO: calculate this size correctly */
6113 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6115 code_reserve = 8 + (param_count * 8);
6116 #endif /* __native_client_codegen__ */
6118 * The stack contains:
6119 * <args in reverse order>
6124 * <args in reverse order>
6127 * without unbalancing the stack.
6128 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6129 * and leaving original spot of first arg as placeholder in stack so
6130 * when callee pops stack everything works.
6133 start = code = mono_global_codeman_reserve (code_reserve);
6135 /* store delegate for access to method_ptr */
6136 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6139 for (i = 0; i < param_count; ++i) {
6140 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6141 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6144 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6146 g_assert ((code - start) < code_reserve);
6149 nacl_global_codeman_validate (&start, code_reserve, &code);
6152 *code_len = code - start;
6154 if (mono_jit_map_is_enabled ()) {
6157 buff = (char*)"delegate_invoke_has_target";
6159 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6160 mono_emit_jit_tramp (start, code - start, buff);
6164 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6170 mono_arch_get_delegate_invoke_impls (void)
6178 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6179 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
6181 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6182 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6183 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
6184 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
6185 g_free (tramp_name);
6192 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6194 guint8 *code, *start;
6196 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6199 /* FIXME: Support more cases */
6200 if (MONO_TYPE_ISSTRUCT (sig->ret))
6204 * The stack contains:
6210 static guint8* cached = NULL;
6215 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6217 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6219 mono_memory_barrier ();
6223 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6226 for (i = 0; i < sig->param_count; ++i)
6227 if (!mono_is_regsize_var (sig->params [i]))
6230 code = cache [sig->param_count];
6234 if (mono_aot_only) {
6235 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6236 start = mono_aot_get_trampoline (name);
6239 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6242 mono_memory_barrier ();
6244 cache [sig->param_count] = start;
6251 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
6253 guint8 *code, *start;
6257 * The stack contains:
6261 start = code = mono_global_codeman_reserve (size);
6263 /* Replace the this argument with the target */
6264 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6265 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6266 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6269 /* Load the IMT reg */
6270 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
6273 /* Load the vtable */
6274 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
6275 x86_jump_membase (code, X86_EAX, offset);
6276 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6282 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6285 case X86_EAX: return ctx->eax;
6286 case X86_EBX: return ctx->ebx;
6287 case X86_ECX: return ctx->ecx;
6288 case X86_EDX: return ctx->edx;
6289 case X86_ESP: return ctx->esp;
6290 case X86_EBP: return ctx->ebp;
6291 case X86_ESI: return ctx->esi;
6292 case X86_EDI: return ctx->edi;
6294 g_assert_not_reached ();
6300 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6328 g_assert_not_reached ();
6332 #ifdef MONO_ARCH_SIMD_INTRINSICS
6335 get_float_to_x_spill_area (MonoCompile *cfg)
6337 if (!cfg->fconv_to_r8_x_var) {
6338 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6339 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6341 return cfg->fconv_to_r8_x_var;
6345 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6348 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6351 int dreg, src_opcode;
6353 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6356 switch (src_opcode = ins->opcode) {
6357 case OP_FCONV_TO_I1:
6358 case OP_FCONV_TO_U1:
6359 case OP_FCONV_TO_I2:
6360 case OP_FCONV_TO_U2:
6361 case OP_FCONV_TO_I4:
6368 /* dreg is the IREG and sreg1 is the FREG */
6369 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6370 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6371 fconv->sreg1 = ins->sreg1;
6372 fconv->dreg = mono_alloc_ireg (cfg);
6373 fconv->type = STACK_VTYPE;
6374 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6376 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6380 ins->opcode = OP_XCONV_R8_TO_I4;
6382 ins->klass = mono_defaults.int32_class;
6383 ins->sreg1 = fconv->dreg;
6385 ins->type = STACK_I4;
6386 ins->backend.source_opcode = src_opcode;
6389 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6392 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6397 if (long_ins->opcode == OP_LNEG) {
6399 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6400 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6401 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6406 #ifdef MONO_ARCH_SIMD_INTRINSICS
6408 if (!(cfg->opt & MONO_OPT_SIMD))
6411 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6412 switch (long_ins->opcode) {
6414 vreg = long_ins->sreg1;
6416 if (long_ins->inst_c0) {
6417 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6418 ins->klass = long_ins->klass;
6419 ins->sreg1 = long_ins->sreg1;
6421 ins->type = STACK_VTYPE;
6422 ins->dreg = vreg = alloc_ireg (cfg);
6423 MONO_ADD_INS (cfg->cbb, ins);
6426 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6427 ins->klass = mono_defaults.int32_class;
6429 ins->type = STACK_I4;
6430 ins->dreg = long_ins->dreg + 1;
6431 MONO_ADD_INS (cfg->cbb, ins);
6433 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6434 ins->klass = long_ins->klass;
6435 ins->sreg1 = long_ins->sreg1;
6436 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6437 ins->type = STACK_VTYPE;
6438 ins->dreg = vreg = alloc_ireg (cfg);
6439 MONO_ADD_INS (cfg->cbb, ins);
6441 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6442 ins->klass = mono_defaults.int32_class;
6444 ins->type = STACK_I4;
6445 ins->dreg = long_ins->dreg + 2;
6446 MONO_ADD_INS (cfg->cbb, ins);
6448 long_ins->opcode = OP_NOP;
6450 case OP_INSERTX_I8_SLOW:
6451 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6452 ins->dreg = long_ins->dreg;
6453 ins->sreg1 = long_ins->dreg;
6454 ins->sreg2 = long_ins->sreg2 + 1;
6455 ins->inst_c0 = long_ins->inst_c0 * 2;
6456 MONO_ADD_INS (cfg->cbb, ins);
6458 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6459 ins->dreg = long_ins->dreg;
6460 ins->sreg1 = long_ins->dreg;
6461 ins->sreg2 = long_ins->sreg2 + 2;
6462 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6463 MONO_ADD_INS (cfg->cbb, ins);
6465 long_ins->opcode = OP_NOP;
6468 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6469 ins->dreg = long_ins->dreg;
6470 ins->sreg1 = long_ins->sreg1 + 1;
6471 ins->klass = long_ins->klass;
6472 ins->type = STACK_VTYPE;
6473 MONO_ADD_INS (cfg->cbb, ins);
6475 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6476 ins->dreg = long_ins->dreg;
6477 ins->sreg1 = long_ins->dreg;
6478 ins->sreg2 = long_ins->sreg1 + 2;
6480 ins->klass = long_ins->klass;
6481 ins->type = STACK_VTYPE;
6482 MONO_ADD_INS (cfg->cbb, ins);
6484 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6485 ins->dreg = long_ins->dreg;
6486 ins->sreg1 = long_ins->dreg;;
6487 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6488 ins->klass = long_ins->klass;
6489 ins->type = STACK_VTYPE;
6490 MONO_ADD_INS (cfg->cbb, ins);
6492 long_ins->opcode = OP_NOP;
6495 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6498 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6500 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6503 gpointer *sp, old_value;
6506 offset = clause->exvar_offset;
6509 bp = MONO_CONTEXT_GET_BP (ctx);
6510 sp = *(gpointer*)(bp + offset);
6513 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6522 * mono_aot_emit_load_got_addr:
6524 * Emit code to load the got address.
6525 * On x86, the result is placed into EBX.
6528 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6530 x86_call_imm (code, 0);
6532 * The patch needs to point to the pop, since the GOT offset needs
6533 * to be added to that address.
6536 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6538 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6539 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6540 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6546 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6549 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6551 g_assert_not_reached ();
6552 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6557 * mono_arch_emit_load_aotconst:
6559 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6560 * TARGET from the mscorlib GOT in full-aot code.
6561 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6565 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6567 /* Load the mscorlib got address */
6568 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6569 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6570 /* arch_emit_got_access () patches this */
6571 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6576 /* Can't put this into mini-x86.h */
6578 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6581 mono_arch_get_trampolines (gboolean aot)
6583 MonoTrampInfo *info;
6584 GSList *tramps = NULL;
6586 mono_x86_get_signal_exception_trampoline (&info, aot);
6588 tramps = g_slist_append (tramps, info);
6595 #define DBG_SIGNAL SIGBUS
6597 #define DBG_SIGNAL SIGSEGV
6600 /* Soft Debug support */
6601 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6604 * mono_arch_set_breakpoint:
6606 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6607 * The location should contain code emitted by OP_SEQ_POINT.
6610 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6615 * In production, we will use int3 (has to fix the size in the md
6616 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6619 g_assert (code [0] == 0x90);
6620 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6624 * mono_arch_clear_breakpoint:
6626 * Clear the breakpoint at IP.
6629 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6634 for (i = 0; i < 6; ++i)
6639 * mono_arch_start_single_stepping:
6641 * Start single stepping.
6644 mono_arch_start_single_stepping (void)
6646 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6650 * mono_arch_stop_single_stepping:
6652 * Stop single stepping.
6655 mono_arch_stop_single_stepping (void)
6657 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6661 * mono_arch_is_single_step_event:
6663 * Return whenever the machine state in SIGCTX corresponds to a single
6667 mono_arch_is_single_step_event (void *info, void *sigctx)
6670 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6672 if (((gpointer)einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6677 siginfo_t* sinfo = (siginfo_t*) info;
6678 /* Sometimes the address is off by 4 */
6679 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6687 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6690 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6691 if (((gpointer)einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6696 siginfo_t* sinfo = (siginfo_t*)info;
6697 /* Sometimes the address is off by 4 */
6698 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6705 #define BREAKPOINT_SIZE 6
6708 * mono_arch_skip_breakpoint:
6710 * See mini-amd64.c for docs.
6713 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6715 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6719 * mono_arch_skip_single_step:
6721 * See mini-amd64.c for docs.
6724 mono_arch_skip_single_step (MonoContext *ctx)
6726 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6730 * mono_arch_get_seq_point_info:
6732 * See mini-amd64.c for docs.
6735 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6742 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6744 ext->lmf.previous_lmf = (gsize)prev_lmf;
6745 /* Mark that this is a MonoLMFExt */
6746 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6747 ext->lmf.ebp = (gssize)ext;
6753 mono_arch_opcode_supported (int opcode)
6756 case OP_ATOMIC_ADD_I4:
6757 case OP_ATOMIC_EXCHANGE_I4:
6758 case OP_ATOMIC_CAS_I4:
6759 case OP_ATOMIC_LOAD_I1:
6760 case OP_ATOMIC_LOAD_I2:
6761 case OP_ATOMIC_LOAD_I4:
6762 case OP_ATOMIC_LOAD_U1:
6763 case OP_ATOMIC_LOAD_U2:
6764 case OP_ATOMIC_LOAD_U4:
6765 case OP_ATOMIC_LOAD_R4:
6766 case OP_ATOMIC_LOAD_R8:
6767 case OP_ATOMIC_STORE_I1:
6768 case OP_ATOMIC_STORE_I2:
6769 case OP_ATOMIC_STORE_I4:
6770 case OP_ATOMIC_STORE_U1:
6771 case OP_ATOMIC_STORE_U2:
6772 case OP_ATOMIC_STORE_U4:
6773 case OP_ATOMIC_STORE_R4:
6774 case OP_ATOMIC_STORE_R8:
6781 #if defined(ENABLE_GSHAREDVT)
6783 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6785 #endif /* !MONOTOUCH */