2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/abi-details.h>
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/metadata/gc-internal.h>
27 #include <mono/utils/mono-math.h>
28 #include <mono/utils/mono-counters.h>
29 #include <mono/utils/mono-mmap.h>
30 #include <mono/utils/mono-memory-model.h>
31 #include <mono/utils/mono-hwcap-x86.h>
32 #include <mono/utils/mono-threads.h>
42 static gboolean optimize_for_xen = TRUE;
44 #define optimize_for_xen 0
48 /* The single step trampoline */
49 static gpointer ss_trampoline;
51 /* The breakpoint trampoline */
52 static gpointer bp_trampoline;
54 /* This mutex protects architecture specific caches */
55 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
56 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
57 static mono_mutex_t mini_arch_mutex;
59 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
64 /* Under windows, the default pinvoke calling convention is stdcall */
65 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
67 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
70 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
72 #define OP_SEQ_POINT_BP_OFFSET 7
75 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
77 #ifdef __native_client_codegen__
79 /* Default alignment for Native Client is 32-byte. */
80 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
82 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
83 /* Check that alignment doesn't cross an alignment boundary. */
85 mono_arch_nacl_pad (guint8 *code, int pad)
87 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
89 if (pad == 0) return code;
90 /* assertion: alignment cannot cross a block boundary */
91 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
92 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
93 while (pad >= kMaxPadding) {
94 x86_padding (code, kMaxPadding);
97 if (pad != 0) x86_padding (code, pad);
102 mono_arch_nacl_skip_nops (guint8 *code)
104 x86_skip_nops (code);
108 #endif /* __native_client_codegen__ */
111 mono_arch_regname (int reg)
114 case X86_EAX: return "%eax";
115 case X86_EBX: return "%ebx";
116 case X86_ECX: return "%ecx";
117 case X86_EDX: return "%edx";
118 case X86_ESP: return "%esp";
119 case X86_EBP: return "%ebp";
120 case X86_EDI: return "%edi";
121 case X86_ESI: return "%esi";
127 mono_arch_fregname (int reg)
152 mono_arch_xregname (int reg)
177 mono_x86_patch (unsigned char* code, gpointer target)
179 x86_patch (code, (unsigned char*)target);
190 /* gsharedvt argument passed by addr */
202 /* Only if storage == ArgValuetypeInReg */
203 ArgStorage pair_storage [2];
212 gboolean need_stack_align;
213 guint32 stack_align_amount;
214 gboolean vtype_retaddr;
215 /* The index of the vret arg in the argument list */
218 /* Argument space popped by the callee */
219 int callee_stack_pop;
225 #define FLOAT_PARAM_REGS 0
227 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
229 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
234 switch (sig->call_convention) {
235 case MONO_CALL_THISCALL:
236 return thiscall_param_regs;
242 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
243 #define SMALL_STRUCTS_IN_REGS
244 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
248 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
250 ainfo->offset = *stack_size;
252 if (!param_regs || param_regs [*gr] == X86_NREG) {
253 ainfo->storage = ArgOnStack;
255 (*stack_size) += sizeof (gpointer);
258 ainfo->storage = ArgInIReg;
259 ainfo->reg = param_regs [*gr];
265 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
267 ainfo->offset = *stack_size;
269 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
271 ainfo->storage = ArgOnStack;
272 (*stack_size) += sizeof (gpointer) * 2;
277 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
279 ainfo->offset = *stack_size;
281 if (*gr >= FLOAT_PARAM_REGS) {
282 ainfo->storage = ArgOnStack;
283 (*stack_size) += is_double ? 8 : 4;
284 ainfo->nslots = is_double ? 2 : 1;
287 /* A double register */
289 ainfo->storage = ArgInDoubleSSEReg;
291 ainfo->storage = ArgInFloatSSEReg;
299 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
301 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
306 klass = mono_class_from_mono_type (type);
307 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
309 #ifdef SMALL_STRUCTS_IN_REGS
310 if (sig->pinvoke && is_return) {
311 MonoMarshalType *info;
314 * the exact rules are not very well documented, the code below seems to work with the
315 * code generated by gcc 3.3.3 -mno-cygwin.
317 info = mono_marshal_load_type_info (klass);
320 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
322 /* Special case structs with only a float member */
323 if (info->num_fields == 1) {
324 int ftype = mini_get_underlying_type (info->fields [0].field->type)->type;
325 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
326 ainfo->storage = ArgValuetypeInReg;
327 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
330 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
331 ainfo->storage = ArgValuetypeInReg;
332 ainfo->pair_storage [0] = ArgOnFloatFpStack;
336 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
337 ainfo->storage = ArgValuetypeInReg;
338 ainfo->pair_storage [0] = ArgInIReg;
339 ainfo->pair_regs [0] = return_regs [0];
340 if (info->native_size > 4) {
341 ainfo->pair_storage [1] = ArgInIReg;
342 ainfo->pair_regs [1] = return_regs [1];
349 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
350 g_assert (size <= 4);
351 ainfo->storage = ArgValuetypeInReg;
352 ainfo->reg = param_regs [*gr];
357 ainfo->offset = *stack_size;
358 ainfo->storage = ArgOnStack;
359 *stack_size += ALIGN_TO (size, sizeof (gpointer));
360 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
366 * Obtain information about a call according to the calling convention.
367 * For x86 ELF, see the "System V Application Binary Interface Intel386
368 * Architecture Processor Supplment, Fourth Edition" document for more
370 * For x86 win32, see ???.
373 get_call_info_internal (CallInfo *cinfo, MonoMethodSignature *sig)
375 guint32 i, gr, fr, pstart;
376 const guint32 *param_regs;
378 int n = sig->hasthis + sig->param_count;
379 guint32 stack_size = 0;
380 gboolean is_pinvoke = sig->pinvoke;
386 param_regs = callconv_param_regs(sig);
390 ret_type = mini_get_underlying_type (sig->ret);
391 switch (ret_type->type) {
401 case MONO_TYPE_FNPTR:
402 case MONO_TYPE_CLASS:
403 case MONO_TYPE_OBJECT:
404 case MONO_TYPE_SZARRAY:
405 case MONO_TYPE_ARRAY:
406 case MONO_TYPE_STRING:
407 cinfo->ret.storage = ArgInIReg;
408 cinfo->ret.reg = X86_EAX;
412 cinfo->ret.storage = ArgInIReg;
413 cinfo->ret.reg = X86_EAX;
414 cinfo->ret.is_pair = TRUE;
417 cinfo->ret.storage = ArgOnFloatFpStack;
420 cinfo->ret.storage = ArgOnDoubleFpStack;
422 case MONO_TYPE_GENERICINST:
423 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
424 cinfo->ret.storage = ArgInIReg;
425 cinfo->ret.reg = X86_EAX;
428 if (mini_is_gsharedvt_type (ret_type)) {
429 cinfo->ret.storage = ArgOnStack;
430 cinfo->vtype_retaddr = TRUE;
434 case MONO_TYPE_VALUETYPE:
435 case MONO_TYPE_TYPEDBYREF: {
436 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
438 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
439 if (cinfo->ret.storage == ArgOnStack) {
440 cinfo->vtype_retaddr = TRUE;
441 /* The caller passes the address where the value is stored */
447 g_assert (mini_is_gsharedvt_type (ret_type));
448 cinfo->ret.storage = ArgOnStack;
449 cinfo->vtype_retaddr = TRUE;
452 cinfo->ret.storage = ArgNone;
455 g_error ("Can't handle as return value 0x%x", ret_type->type);
461 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
462 * the first argument, allowing 'this' to be always passed in the first arg reg.
463 * Also do this if the first argument is a reference type, since virtual calls
464 * are sometimes made using calli without sig->hasthis set, like in the delegate
467 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
469 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
471 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
474 cinfo->vret_arg_offset = stack_size;
475 add_general (&gr, NULL, &stack_size, &cinfo->ret);
476 cinfo->vret_arg_index = 1;
480 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
482 if (cinfo->vtype_retaddr)
483 add_general (&gr, NULL, &stack_size, &cinfo->ret);
486 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
487 fr = FLOAT_PARAM_REGS;
489 /* Emit the signature cookie just before the implicit arguments */
490 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
493 for (i = pstart; i < sig->param_count; ++i) {
494 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
497 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
498 /* We allways pass the sig cookie on the stack for simplicity */
500 * Prevent implicit arguments + the sig cookie from being passed
503 fr = FLOAT_PARAM_REGS;
505 /* Emit the signature cookie just before the implicit arguments */
506 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
509 if (sig->params [i]->byref) {
510 add_general (&gr, param_regs, &stack_size, ainfo);
513 ptype = mini_get_underlying_type (sig->params [i]);
514 switch (ptype->type) {
517 add_general (&gr, param_regs, &stack_size, ainfo);
521 add_general (&gr, param_regs, &stack_size, ainfo);
525 add_general (&gr, param_regs, &stack_size, ainfo);
530 case MONO_TYPE_FNPTR:
531 case MONO_TYPE_CLASS:
532 case MONO_TYPE_OBJECT:
533 case MONO_TYPE_STRING:
534 case MONO_TYPE_SZARRAY:
535 case MONO_TYPE_ARRAY:
536 add_general (&gr, param_regs, &stack_size, ainfo);
538 case MONO_TYPE_GENERICINST:
539 if (!mono_type_generic_inst_is_valuetype (ptype)) {
540 add_general (&gr, param_regs, &stack_size, ainfo);
543 if (mini_is_gsharedvt_type (ptype)) {
544 /* gsharedvt arguments are passed by ref */
545 add_general (&gr, param_regs, &stack_size, ainfo);
546 g_assert (ainfo->storage == ArgOnStack);
547 ainfo->storage = ArgGSharedVt;
551 case MONO_TYPE_VALUETYPE:
552 case MONO_TYPE_TYPEDBYREF:
553 add_valuetype (sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
557 add_general_pair (&gr, param_regs, &stack_size, ainfo);
560 add_float (&fr, &stack_size, ainfo, FALSE);
563 add_float (&fr, &stack_size, ainfo, TRUE);
567 /* gsharedvt arguments are passed by ref */
568 g_assert (mini_is_gsharedvt_type (ptype));
569 add_general (&gr, param_regs, &stack_size, ainfo);
570 g_assert (ainfo->storage == ArgOnStack);
571 ainfo->storage = ArgGSharedVt;
574 g_error ("unexpected type 0x%x", ptype->type);
575 g_assert_not_reached ();
579 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
580 fr = FLOAT_PARAM_REGS;
582 /* Emit the signature cookie just before the implicit arguments */
583 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
586 if (cinfo->vtype_retaddr) {
587 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
588 cinfo->callee_stack_pop = 4;
589 } else if (CALLCONV_IS_STDCALL (sig) && sig->pinvoke) {
590 /* Have to compensate for the stack space popped by the native callee */
591 cinfo->callee_stack_pop = stack_size;
594 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
595 cinfo->need_stack_align = TRUE;
596 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
597 stack_size += cinfo->stack_align_amount;
600 cinfo->stack_usage = stack_size;
601 cinfo->reg_usage = gr;
602 cinfo->freg_usage = fr;
607 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
609 int n = sig->hasthis + sig->param_count;
613 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
615 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
617 return get_call_info_internal (cinfo, sig);
621 * mono_arch_get_argument_info:
622 * @csig: a method signature
623 * @param_count: the number of parameters to consider
624 * @arg_info: an array to store the result infos
626 * Gathers information on parameters such as size, alignment and
627 * padding. arg_info should be large enought to hold param_count + 1 entries.
629 * Returns the size of the argument area on the stack.
630 * This should be signal safe, since it is called from
631 * mono_arch_unwind_frame ().
632 * FIXME: The metadata calls might not be signal safe.
635 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
637 int len, k, args_size = 0;
643 /* Avoid g_malloc as it is not signal safe */
644 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
645 cinfo = (CallInfo*)g_newa (guint8*, len);
646 memset (cinfo, 0, len);
648 cinfo = get_call_info_internal (cinfo, csig);
650 arg_info [0].offset = offset;
652 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
653 args_size += sizeof (gpointer);
658 args_size += sizeof (gpointer);
662 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
663 /* Emitted after this */
664 args_size += sizeof (gpointer);
668 arg_info [0].size = args_size;
670 for (k = 0; k < param_count; k++) {
671 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
673 /* ignore alignment for now */
676 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
677 arg_info [k].pad = pad;
679 arg_info [k + 1].pad = 0;
680 arg_info [k + 1].size = size;
682 arg_info [k + 1].offset = offset;
685 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
686 /* Emitted after the first arg */
687 args_size += sizeof (gpointer);
692 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
693 align = MONO_ARCH_FRAME_ALIGNMENT;
696 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
697 arg_info [k].pad = pad;
703 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
705 MonoType *callee_ret;
709 if (cfg->compile_aot && !cfg->full_aot)
710 /* OP_TAILCALL doesn't work with AOT */
713 c1 = get_call_info (NULL, caller_sig);
714 c2 = get_call_info (NULL, callee_sig);
716 * Tail calls with more callee stack usage than the caller cannot be supported, since
717 * the extra stack space would be left on the stack after the tail call.
719 res = c1->stack_usage >= c2->stack_usage;
720 callee_ret = mini_get_underlying_type (callee_sig->ret);
721 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
722 /* An address on the callee's stack is passed as the first argument */
732 * Initialize the cpu to execute managed code.
735 mono_arch_cpu_init (void)
737 /* spec compliance requires running with double precision */
741 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
742 fpcw &= ~X86_FPCW_PRECC_MASK;
743 fpcw |= X86_FPCW_PREC_DOUBLE;
744 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
745 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
747 _control87 (_PC_53, MCW_PC);
752 * Initialize architecture specific code.
755 mono_arch_init (void)
757 mono_mutex_init_recursive (&mini_arch_mutex);
760 bp_trampoline = mini_get_breakpoint_trampoline ();
762 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
763 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
764 #if defined(ENABLE_GSHAREDVT)
765 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
770 * Cleanup architecture specific code.
773 mono_arch_cleanup (void)
775 mono_mutex_destroy (&mini_arch_mutex);
779 * This function returns the optimizations supported on this cpu.
782 mono_arch_cpu_optimizations (guint32 *exclude_mask)
784 #if !defined(__native_client__)
789 if (mono_hwcap_x86_has_cmov) {
790 opts |= MONO_OPT_CMOV;
792 if (mono_hwcap_x86_has_fcmov)
793 opts |= MONO_OPT_FCMOV;
795 *exclude_mask |= MONO_OPT_FCMOV;
797 *exclude_mask |= MONO_OPT_CMOV;
800 if (mono_hwcap_x86_has_sse2)
801 opts |= MONO_OPT_SSE2;
803 *exclude_mask |= MONO_OPT_SSE2;
805 #ifdef MONO_ARCH_SIMD_INTRINSICS
806 /*SIMD intrinsics require at least SSE2.*/
807 if (!mono_hwcap_x86_has_sse2)
808 *exclude_mask |= MONO_OPT_SIMD;
813 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
818 * This function test for all SSE functions supported.
820 * Returns a bitmask corresponding to all supported versions.
824 mono_arch_cpu_enumerate_simd_versions (void)
826 guint32 sse_opts = 0;
828 if (mono_hwcap_x86_has_sse1)
829 sse_opts |= SIMD_VERSION_SSE1;
831 if (mono_hwcap_x86_has_sse2)
832 sse_opts |= SIMD_VERSION_SSE2;
834 if (mono_hwcap_x86_has_sse3)
835 sse_opts |= SIMD_VERSION_SSE3;
837 if (mono_hwcap_x86_has_ssse3)
838 sse_opts |= SIMD_VERSION_SSSE3;
840 if (mono_hwcap_x86_has_sse41)
841 sse_opts |= SIMD_VERSION_SSE41;
843 if (mono_hwcap_x86_has_sse42)
844 sse_opts |= SIMD_VERSION_SSE42;
846 if (mono_hwcap_x86_has_sse4a)
847 sse_opts |= SIMD_VERSION_SSE4a;
853 * Determine whenever the trap whose info is in SIGINFO is caused by
857 mono_arch_is_int_overflow (void *sigctx, void *info)
862 mono_sigctx_to_monoctx (sigctx, &ctx);
864 ip = (guint8*)ctx.eip;
866 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
870 switch (x86_modrm_rm (ip [1])) {
890 g_assert_not_reached ();
902 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
907 for (i = 0; i < cfg->num_varinfo; i++) {
908 MonoInst *ins = cfg->varinfo [i];
909 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
912 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
915 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
916 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
919 /* we dont allocate I1 to registers because there is no simply way to sign extend
920 * 8bit quantities in caller saved registers on x86 */
921 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
922 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
923 g_assert (i == vmv->idx);
924 vars = g_list_prepend (vars, vmv);
928 vars = mono_varlist_sort (cfg, vars, 0);
934 mono_arch_get_global_int_regs (MonoCompile *cfg)
938 /* we can use 3 registers for global allocation */
939 regs = g_list_prepend (regs, (gpointer)X86_EBX);
940 regs = g_list_prepend (regs, (gpointer)X86_ESI);
941 regs = g_list_prepend (regs, (gpointer)X86_EDI);
947 * mono_arch_regalloc_cost:
949 * Return the cost, in number of memory references, of the action of
950 * allocating the variable VMV into a register during global register
954 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
956 MonoInst *ins = cfg->varinfo [vmv->idx];
958 if (cfg->method->save_lmf)
959 /* The register is already saved */
960 return (ins->opcode == OP_ARG) ? 1 : 0;
962 /* push+pop+possible load if it is an argument */
963 return (ins->opcode == OP_ARG) ? 3 : 2;
967 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
969 static int inited = FALSE;
970 static int count = 0;
972 if (cfg->arch.need_stack_frame_inited) {
973 g_assert (cfg->arch.need_stack_frame == flag);
977 cfg->arch.need_stack_frame = flag;
978 cfg->arch.need_stack_frame_inited = TRUE;
984 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
989 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
993 needs_stack_frame (MonoCompile *cfg)
995 MonoMethodSignature *sig;
996 MonoMethodHeader *header;
997 gboolean result = FALSE;
999 #if defined(__APPLE__)
1000 /*OSX requires stack frame code to have the correct alignment. */
1004 if (cfg->arch.need_stack_frame_inited)
1005 return cfg->arch.need_stack_frame;
1007 header = cfg->header;
1008 sig = mono_method_signature (cfg->method);
1010 if (cfg->disable_omit_fp)
1012 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1014 else if (cfg->method->save_lmf)
1016 else if (cfg->stack_offset)
1018 else if (cfg->param_area)
1020 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1022 else if (header->num_clauses)
1024 else if (sig->param_count + sig->hasthis)
1026 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1028 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1029 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1032 set_needs_stack_frame (cfg, result);
1034 return cfg->arch.need_stack_frame;
1038 * Set var information according to the calling convention. X86 version.
1039 * The locals var stuff should most likely be split in another method.
1042 mono_arch_allocate_vars (MonoCompile *cfg)
1044 MonoMethodSignature *sig;
1045 MonoMethodHeader *header;
1047 guint32 locals_stack_size, locals_stack_align;
1052 header = cfg->header;
1053 sig = mono_method_signature (cfg->method);
1055 cinfo = get_call_info (cfg->mempool, sig);
1057 cfg->frame_reg = X86_EBP;
1060 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1061 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1062 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1065 /* Reserve space to save LMF and caller saved registers */
1067 if (cfg->method->save_lmf) {
1068 /* The LMF var is allocated normally */
1070 if (cfg->used_int_regs & (1 << X86_EBX)) {
1074 if (cfg->used_int_regs & (1 << X86_EDI)) {
1078 if (cfg->used_int_regs & (1 << X86_ESI)) {
1083 switch (cinfo->ret.storage) {
1084 case ArgValuetypeInReg:
1085 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1087 cfg->ret->opcode = OP_REGOFFSET;
1088 cfg->ret->inst_basereg = X86_EBP;
1089 cfg->ret->inst_offset = - offset;
1095 /* Allocate locals */
1096 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1097 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1098 char *mname = mono_method_full_name (cfg->method, TRUE);
1099 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1100 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1104 if (locals_stack_align) {
1105 int prev_offset = offset;
1107 offset += (locals_stack_align - 1);
1108 offset &= ~(locals_stack_align - 1);
1110 while (prev_offset < offset) {
1112 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1115 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1116 cfg->locals_max_stack_offset = - offset;
1118 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1119 * have locals larger than 8 bytes we need to make sure that
1120 * they have the appropriate offset.
1122 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1123 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1124 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1125 if (offsets [i] != -1) {
1126 MonoInst *inst = cfg->varinfo [i];
1127 inst->opcode = OP_REGOFFSET;
1128 inst->inst_basereg = X86_EBP;
1129 inst->inst_offset = - (offset + offsets [i]);
1130 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1133 offset += locals_stack_size;
1137 * Allocate arguments+return value
1140 switch (cinfo->ret.storage) {
1142 if (cfg->vret_addr) {
1144 * In the new IR, the cfg->vret_addr variable represents the
1145 * vtype return value.
1147 cfg->vret_addr->opcode = OP_REGOFFSET;
1148 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1149 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1150 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1151 printf ("vret_addr =");
1152 mono_print_ins (cfg->vret_addr);
1155 cfg->ret->opcode = OP_REGOFFSET;
1156 cfg->ret->inst_basereg = X86_EBP;
1157 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1160 case ArgValuetypeInReg:
1163 cfg->ret->opcode = OP_REGVAR;
1164 cfg->ret->inst_c0 = cinfo->ret.reg;
1165 cfg->ret->dreg = cinfo->ret.reg;
1168 case ArgOnFloatFpStack:
1169 case ArgOnDoubleFpStack:
1172 g_assert_not_reached ();
1175 if (sig->call_convention == MONO_CALL_VARARG) {
1176 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1177 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1180 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1181 ArgInfo *ainfo = &cinfo->args [i];
1182 inst = cfg->args [i];
1183 if (inst->opcode != OP_REGVAR) {
1184 inst->opcode = OP_REGOFFSET;
1185 inst->inst_basereg = X86_EBP;
1187 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1190 cfg->stack_offset = offset;
1194 mono_arch_create_vars (MonoCompile *cfg)
1197 MonoMethodSignature *sig;
1200 sig = mono_method_signature (cfg->method);
1202 cinfo = get_call_info (cfg->mempool, sig);
1203 sig_ret = mini_get_underlying_type (sig->ret);
1205 if (cinfo->ret.storage == ArgValuetypeInReg)
1206 cfg->ret_var_is_local = TRUE;
1207 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (sig_ret))) {
1208 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1211 if (cfg->gen_sdb_seq_points) {
1214 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1215 ins->flags |= MONO_INST_VOLATILE;
1216 cfg->arch.ss_tramp_var = ins;
1218 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1219 ins->flags |= MONO_INST_VOLATILE;
1220 cfg->arch.bp_tramp_var = ins;
1223 if (cfg->method->save_lmf) {
1224 cfg->create_lmf_var = TRUE;
1227 cfg->lmf_ir_mono_lmf = TRUE;
1231 cfg->arch_eh_jit_info = 1;
1235 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1236 * so we try to do it just once when we have multiple fp arguments in a row.
1237 * We don't use this mechanism generally because for int arguments the generated code
1238 * is slightly bigger and new generation cpus optimize away the dependency chains
1239 * created by push instructions on the esp value.
1240 * fp_arg_setup is the first argument in the execution sequence where the esp register
1243 static G_GNUC_UNUSED int
1244 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1249 for (; start_arg < sig->param_count; ++start_arg) {
1250 t = mini_get_underlying_type (sig->params [start_arg]);
1251 if (!t->byref && t->type == MONO_TYPE_R8) {
1252 fp_space += sizeof (double);
1253 *fp_arg_setup = start_arg;
1262 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1264 MonoMethodSignature *tmp_sig;
1268 * mono_ArgIterator_Setup assumes the signature cookie is
1269 * passed first and all the arguments which were before it are
1270 * passed on the stack after the signature. So compensate by
1271 * passing a different signature.
1273 tmp_sig = mono_metadata_signature_dup (call->signature);
1274 tmp_sig->param_count -= call->signature->sentinelpos;
1275 tmp_sig->sentinelpos = 0;
1276 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1278 if (cfg->compile_aot) {
1279 sig_reg = mono_alloc_ireg (cfg);
1280 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1281 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1283 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1289 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1294 LLVMCallInfo *linfo;
1295 MonoType *t, *sig_ret;
1297 n = sig->param_count + sig->hasthis;
1299 cinfo = get_call_info (cfg->mempool, sig);
1302 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1305 * LLVM always uses the native ABI while we use our own ABI, the
1306 * only difference is the handling of vtypes:
1307 * - we only pass/receive them in registers in some cases, and only
1308 * in 1 or 2 integer registers.
1310 if (cinfo->ret.storage == ArgValuetypeInReg) {
1312 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1313 cfg->disable_llvm = TRUE;
1317 cfg->exception_message = g_strdup ("vtype ret in call");
1318 cfg->disable_llvm = TRUE;
1320 linfo->ret.storage = LLVMArgVtypeInReg;
1321 for (j = 0; j < 2; ++j)
1322 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1326 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage == ArgInIReg) {
1327 /* Vtype returned using a hidden argument */
1328 linfo->ret.storage = LLVMArgVtypeRetAddr;
1329 linfo->vret_arg_index = cinfo->vret_arg_index;
1332 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage != ArgInIReg) {
1334 cfg->exception_message = g_strdup ("vtype ret in call");
1335 cfg->disable_llvm = TRUE;
1338 for (i = 0; i < n; ++i) {
1339 ainfo = cinfo->args + i;
1341 if (i >= sig->hasthis)
1342 t = sig->params [i - sig->hasthis];
1344 t = &mono_defaults.int_class->byval_arg;
1346 linfo->args [i].storage = LLVMArgNone;
1348 switch (ainfo->storage) {
1350 linfo->args [i].storage = LLVMArgInIReg;
1352 case ArgInDoubleSSEReg:
1353 case ArgInFloatSSEReg:
1354 linfo->args [i].storage = LLVMArgInFPReg;
1357 if (mini_type_is_vtype (t)) {
1358 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1359 /* LLVM seems to allocate argument space for empty structures too */
1360 linfo->args [i].storage = LLVMArgNone;
1362 linfo->args [i].storage = LLVMArgVtypeByVal;
1364 linfo->args [i].storage = LLVMArgInIReg;
1366 if (t->type == MONO_TYPE_R4)
1367 linfo->args [i].storage = LLVMArgInFPReg;
1368 else if (t->type == MONO_TYPE_R8)
1369 linfo->args [i].storage = LLVMArgInFPReg;
1373 case ArgValuetypeInReg:
1375 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1376 cfg->disable_llvm = TRUE;
1380 cfg->exception_message = g_strdup ("vtype arg");
1381 cfg->disable_llvm = TRUE;
1383 linfo->args [i].storage = LLVMArgVtypeInReg;
1384 for (j = 0; j < 2; ++j)
1385 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1389 linfo->args [i].storage = LLVMArgGSharedVt;
1392 cfg->exception_message = g_strdup ("ainfo->storage");
1393 cfg->disable_llvm = TRUE;
1403 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1405 if (cfg->compute_gc_maps) {
1408 /* Needs checking if the feature will be enabled again */
1409 g_assert_not_reached ();
1411 /* On x86, the offsets are from the sp value before the start of the call sequence */
1413 t = &mono_defaults.int_class->byval_arg;
1414 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1419 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1423 MonoMethodSignature *sig;
1426 int sentinelpos = 0, sp_offset = 0;
1428 sig = call->signature;
1429 n = sig->param_count + sig->hasthis;
1430 sig_ret = mini_get_underlying_type (sig->ret);
1432 cinfo = get_call_info (cfg->mempool, sig);
1433 call->call_info = cinfo;
1435 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1436 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1438 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1439 if (cinfo->ret.storage == ArgValuetypeInReg) {
1441 * Tell the JIT to use a more efficient calling convention: call using
1442 * OP_CALL, compute the result location after the call, and save the
1445 call->vret_in_reg = TRUE;
1446 #if defined(__APPLE__)
1447 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1448 call->vret_in_reg_fp = TRUE;
1451 NULLIFY_INS (call->vret_var);
1455 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1457 /* Handle the case where there are no implicit arguments */
1458 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1459 emit_sig_cookie (cfg, call, cinfo);
1460 sp_offset = cinfo->sig_cookie.offset;
1461 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1464 /* Arguments are pushed in the reverse order */
1465 for (i = n - 1; i >= 0; i --) {
1466 ArgInfo *ainfo = cinfo->args + i;
1467 MonoType *orig_type, *t;
1470 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1473 /* Push the vret arg before the first argument */
1474 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1475 vtarg->type = STACK_MP;
1476 vtarg->inst_destbasereg = X86_ESP;
1477 vtarg->sreg1 = call->vret_var->dreg;
1478 vtarg->inst_offset = cinfo->ret.offset;
1479 MONO_ADD_INS (cfg->cbb, vtarg);
1480 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1483 if (i >= sig->hasthis)
1484 t = sig->params [i - sig->hasthis];
1486 t = &mono_defaults.int_class->byval_arg;
1488 t = mini_get_underlying_type (t);
1490 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1492 in = call->args [i];
1493 arg->cil_code = in->cil_code;
1494 arg->sreg1 = in->dreg;
1495 arg->type = in->type;
1497 g_assert (in->dreg != -1);
1499 if (ainfo->storage == ArgGSharedVt) {
1500 arg->opcode = OP_OUTARG_VT;
1501 arg->sreg1 = in->dreg;
1502 arg->klass = in->klass;
1503 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1504 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1506 MONO_ADD_INS (cfg->cbb, arg);
1507 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1511 g_assert (in->klass);
1513 if (t->type == MONO_TYPE_TYPEDBYREF) {
1514 size = sizeof (MonoTypedRef);
1515 align = sizeof (gpointer);
1518 size = mini_type_stack_size_full (&in->klass->byval_arg, &align, sig->pinvoke);
1522 arg->opcode = OP_OUTARG_VT;
1523 arg->sreg1 = in->dreg;
1524 arg->klass = in->klass;
1525 arg->backend.size = size;
1526 arg->inst_p0 = call;
1527 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1528 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1530 MONO_ADD_INS (cfg->cbb, arg);
1531 if (ainfo->storage != ArgValuetypeInReg) {
1532 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1536 switch (ainfo->storage) {
1539 if (t->type == MONO_TYPE_R4) {
1540 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1542 } else if (t->type == MONO_TYPE_R8) {
1543 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1545 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1546 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, in->dreg + 2);
1547 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg + 1);
1550 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1554 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1559 arg->opcode = OP_MOVE;
1560 arg->dreg = ainfo->reg;
1561 MONO_ADD_INS (cfg->cbb, arg);
1565 g_assert_not_reached ();
1568 if (cfg->compute_gc_maps) {
1570 /* FIXME: The == STACK_OBJ check might be fragile ? */
1571 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1573 if (call->need_unbox_trampoline)
1574 /* The unbox trampoline transforms this into a managed pointer */
1575 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.int_class->this_arg);
1577 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.object_class->byval_arg);
1579 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1583 for (j = 0; j < argsize; j += 4)
1584 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1589 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1590 /* Emit the signature cookie just before the implicit arguments */
1591 emit_sig_cookie (cfg, call, cinfo);
1592 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1596 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1599 if (cinfo->ret.storage == ArgValuetypeInReg) {
1602 else if (cinfo->ret.storage == ArgInIReg) {
1604 /* The return address is passed in a register */
1605 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1606 vtarg->sreg1 = call->inst.dreg;
1607 vtarg->dreg = mono_alloc_ireg (cfg);
1608 MONO_ADD_INS (cfg->cbb, vtarg);
1610 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1611 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1612 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1613 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1617 call->stack_usage = cinfo->stack_usage;
1618 call->stack_align_amount = cinfo->stack_align_amount;
1622 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1624 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1625 ArgInfo *ainfo = ins->inst_p1;
1626 int size = ins->backend.size;
1628 if (ainfo->storage == ArgValuetypeInReg) {
1629 int dreg = mono_alloc_ireg (cfg);
1632 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1635 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1638 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1642 g_assert_not_reached ();
1644 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1647 if (cfg->gsharedvt && mini_is_gsharedvt_klass (ins->klass)) {
1649 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1650 } else if (size <= 4) {
1651 int dreg = mono_alloc_ireg (cfg);
1652 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1653 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1654 } else if (size <= 20) {
1655 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1657 // FIXME: Code growth
1658 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1664 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1666 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
1669 if (ret->type == MONO_TYPE_R4) {
1670 if (COMPILE_LLVM (cfg))
1671 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1674 } else if (ret->type == MONO_TYPE_R8) {
1675 if (COMPILE_LLVM (cfg))
1676 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1679 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1680 if (COMPILE_LLVM (cfg))
1681 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1683 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1684 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1690 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1694 * Allow tracing to work with this interface (with an optional argument)
1697 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1701 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1702 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1704 /* if some args are passed in registers, we need to save them here */
1705 x86_push_reg (code, X86_EBP);
1707 if (cfg->compile_aot) {
1708 x86_push_imm (code, cfg->method);
1709 x86_mov_reg_imm (code, X86_EAX, func);
1710 x86_call_reg (code, X86_EAX);
1712 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1713 x86_push_imm (code, cfg->method);
1714 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1715 x86_call_code (code, 0);
1717 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1731 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1734 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1735 MonoMethod *method = cfg->method;
1736 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
1738 switch (ret_type->type) {
1739 case MONO_TYPE_VOID:
1740 /* special case string .ctor icall */
1741 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1742 save_mode = SAVE_EAX;
1743 stack_usage = enable_arguments ? 8 : 4;
1745 save_mode = SAVE_NONE;
1749 save_mode = SAVE_EAX_EDX;
1750 stack_usage = enable_arguments ? 16 : 8;
1754 save_mode = SAVE_FP;
1755 stack_usage = enable_arguments ? 16 : 8;
1757 case MONO_TYPE_GENERICINST:
1758 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1759 save_mode = SAVE_EAX;
1760 stack_usage = enable_arguments ? 8 : 4;
1764 case MONO_TYPE_VALUETYPE:
1765 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1766 save_mode = SAVE_STRUCT;
1767 stack_usage = enable_arguments ? 4 : 0;
1770 save_mode = SAVE_EAX;
1771 stack_usage = enable_arguments ? 8 : 4;
1775 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1777 switch (save_mode) {
1779 x86_push_reg (code, X86_EDX);
1780 x86_push_reg (code, X86_EAX);
1781 if (enable_arguments) {
1782 x86_push_reg (code, X86_EDX);
1783 x86_push_reg (code, X86_EAX);
1788 x86_push_reg (code, X86_EAX);
1789 if (enable_arguments) {
1790 x86_push_reg (code, X86_EAX);
1795 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1796 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1797 if (enable_arguments) {
1798 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1799 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1804 if (enable_arguments) {
1805 x86_push_membase (code, X86_EBP, 8);
1814 if (cfg->compile_aot) {
1815 x86_push_imm (code, method);
1816 x86_mov_reg_imm (code, X86_EAX, func);
1817 x86_call_reg (code, X86_EAX);
1819 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1820 x86_push_imm (code, method);
1821 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1822 x86_call_code (code, 0);
1825 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1827 switch (save_mode) {
1829 x86_pop_reg (code, X86_EAX);
1830 x86_pop_reg (code, X86_EDX);
1833 x86_pop_reg (code, X86_EAX);
1836 x86_fld_membase (code, X86_ESP, 0, TRUE);
1837 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1844 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1849 #define EMIT_COND_BRANCH(ins,cond,sign) \
1850 if (ins->inst_true_bb->native_offset) { \
1851 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1853 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1854 if ((cfg->opt & MONO_OPT_BRANCH) && \
1855 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1856 x86_branch8 (code, cond, 0, sign); \
1858 x86_branch32 (code, cond, 0, sign); \
1862 * Emit an exception if condition is fail and
1863 * if possible do a directly branch to target
1865 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1867 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1868 if (tins == NULL) { \
1869 mono_add_patch_info (cfg, code - cfg->native_code, \
1870 MONO_PATCH_INFO_EXC, exc_name); \
1871 x86_branch32 (code, cond, 0, signed); \
1873 EMIT_COND_BRANCH (tins, cond, signed); \
1877 #define EMIT_FPCOMPARE(code) do { \
1878 x86_fcompp (code); \
1879 x86_fnstsw (code); \
1884 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1886 gboolean needs_paddings = TRUE;
1888 MonoJumpInfo *jinfo = NULL;
1890 if (cfg->abs_patches) {
1891 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1892 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1893 needs_paddings = FALSE;
1896 if (cfg->compile_aot)
1897 needs_paddings = FALSE;
1898 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1899 This is required for code patching to be safe on SMP machines.
1901 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1902 #ifndef __native_client_codegen__
1903 if (needs_paddings && pad_size)
1904 x86_padding (code, 4 - pad_size);
1907 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1908 x86_call_code (code, 0);
1913 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1916 * mono_peephole_pass_1:
1918 * Perform peephole opts which should/can be performed before local regalloc
1921 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1925 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1926 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1928 switch (ins->opcode) {
1931 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1933 * X86_LEA is like ADD, but doesn't have the
1934 * sreg1==dreg restriction.
1936 ins->opcode = OP_X86_LEA_MEMBASE;
1937 ins->inst_basereg = ins->sreg1;
1938 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1939 ins->opcode = OP_X86_INC_REG;
1943 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1944 ins->opcode = OP_X86_LEA_MEMBASE;
1945 ins->inst_basereg = ins->sreg1;
1946 ins->inst_imm = -ins->inst_imm;
1947 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1948 ins->opcode = OP_X86_DEC_REG;
1950 case OP_COMPARE_IMM:
1951 case OP_ICOMPARE_IMM:
1952 /* OP_COMPARE_IMM (reg, 0)
1954 * OP_X86_TEST_NULL (reg)
1957 ins->opcode = OP_X86_TEST_NULL;
1959 case OP_X86_COMPARE_MEMBASE_IMM:
1961 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1962 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1964 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1965 * OP_COMPARE_IMM reg, imm
1967 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1969 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1970 ins->inst_basereg == last_ins->inst_destbasereg &&
1971 ins->inst_offset == last_ins->inst_offset) {
1972 ins->opcode = OP_COMPARE_IMM;
1973 ins->sreg1 = last_ins->sreg1;
1975 /* check if we can remove cmp reg,0 with test null */
1977 ins->opcode = OP_X86_TEST_NULL;
1981 case OP_X86_PUSH_MEMBASE:
1982 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1983 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1984 ins->inst_basereg == last_ins->inst_destbasereg &&
1985 ins->inst_offset == last_ins->inst_offset) {
1986 ins->opcode = OP_X86_PUSH;
1987 ins->sreg1 = last_ins->sreg1;
1992 mono_peephole_ins (bb, ins);
1997 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2001 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2002 switch (ins->opcode) {
2004 /* reg = 0 -> XOR (reg, reg) */
2005 /* XOR sets cflags on x86, so we cant do it always */
2006 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2009 ins->opcode = OP_IXOR;
2010 ins->sreg1 = ins->dreg;
2011 ins->sreg2 = ins->dreg;
2014 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2015 * since it takes 3 bytes instead of 7.
2017 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
2018 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2019 ins2->opcode = OP_STORE_MEMBASE_REG;
2020 ins2->sreg1 = ins->dreg;
2022 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2023 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2024 ins2->sreg1 = ins->dreg;
2026 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2027 /* Continue iteration */
2036 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2037 ins->opcode = OP_X86_INC_REG;
2041 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2042 ins->opcode = OP_X86_DEC_REG;
2046 mono_peephole_ins (bb, ins);
2051 * mono_arch_lowering_pass:
2053 * Converts complex opcodes into simpler ones so that each IR instruction
2054 * corresponds to one machine instruction.
2057 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2059 MonoInst *ins, *next;
2062 * FIXME: Need to add more instructions, but the current machine
2063 * description can't model some parts of the composite instructions like
2066 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2067 switch (ins->opcode) {
2070 case OP_IDIV_UN_IMM:
2071 case OP_IREM_UN_IMM:
2073 * Keep the cases where we could generated optimized code, otherwise convert
2074 * to the non-imm variant.
2076 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2078 mono_decompose_op_imm (cfg, bb, ins);
2085 bb->max_vreg = cfg->next_vreg;
2089 branch_cc_table [] = {
2090 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2091 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2092 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2095 /* Maps CMP_... constants to X86_CC_... constants */
2098 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2099 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2103 cc_signed_table [] = {
2104 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2105 FALSE, FALSE, FALSE, FALSE
2108 static unsigned char*
2109 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2111 #define XMM_TEMP_REG 0
2112 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2113 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2114 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2115 /* optimize by assigning a local var for this use so we avoid
2116 * the stack manipulations */
2117 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2118 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2119 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2120 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2121 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2123 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2125 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2128 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2129 x86_fnstcw_membase(code, X86_ESP, 0);
2130 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2131 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2132 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2133 x86_fldcw_membase (code, X86_ESP, 2);
2135 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2136 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2137 x86_pop_reg (code, dreg);
2138 /* FIXME: need the high register
2139 * x86_pop_reg (code, dreg_high);
2142 x86_push_reg (code, X86_EAX); // SP = SP - 4
2143 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2144 x86_pop_reg (code, dreg);
2146 x86_fldcw_membase (code, X86_ESP, 0);
2147 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2150 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2152 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2156 static unsigned char*
2157 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2159 int sreg = tree->sreg1;
2160 int need_touch = FALSE;
2162 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2171 * If requested stack size is larger than one page,
2172 * perform stack-touch operation
2175 * Generate stack probe code.
2176 * Under Windows, it is necessary to allocate one page at a time,
2177 * "touching" stack after each successful sub-allocation. This is
2178 * because of the way stack growth is implemented - there is a
2179 * guard page before the lowest stack page that is currently commited.
2180 * Stack normally grows sequentially so OS traps access to the
2181 * guard page and commits more pages when needed.
2183 x86_test_reg_imm (code, sreg, ~0xFFF);
2184 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2186 br[2] = code; /* loop */
2187 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2188 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2191 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2192 * that follows only initializes the last part of the area.
2194 /* Same as the init code below with size==0x1000 */
2195 if (tree->flags & MONO_INST_INIT) {
2196 x86_push_reg (code, X86_EAX);
2197 x86_push_reg (code, X86_ECX);
2198 x86_push_reg (code, X86_EDI);
2199 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2200 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2201 if (cfg->param_area)
2202 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2204 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2206 x86_prefix (code, X86_REP_PREFIX);
2208 x86_pop_reg (code, X86_EDI);
2209 x86_pop_reg (code, X86_ECX);
2210 x86_pop_reg (code, X86_EAX);
2213 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2214 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2215 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2216 x86_patch (br[3], br[2]);
2217 x86_test_reg_reg (code, sreg, sreg);
2218 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2219 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2221 br[1] = code; x86_jump8 (code, 0);
2223 x86_patch (br[0], code);
2224 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2225 x86_patch (br[1], code);
2226 x86_patch (br[4], code);
2229 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2231 if (tree->flags & MONO_INST_INIT) {
2233 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2234 x86_push_reg (code, X86_EAX);
2237 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2238 x86_push_reg (code, X86_ECX);
2241 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2242 x86_push_reg (code, X86_EDI);
2246 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2247 if (sreg != X86_ECX)
2248 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2249 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2251 if (cfg->param_area)
2252 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2254 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2256 x86_prefix (code, X86_REP_PREFIX);
2259 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2260 x86_pop_reg (code, X86_EDI);
2261 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2262 x86_pop_reg (code, X86_ECX);
2263 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2264 x86_pop_reg (code, X86_EAX);
2271 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2273 /* Move return value to the target register */
2274 switch (ins->opcode) {
2277 case OP_CALL_MEMBASE:
2278 if (ins->dreg != X86_EAX)
2279 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2289 static int tls_gs_offset;
2293 mono_x86_have_tls_get (void)
2296 static gboolean have_tls_get = FALSE;
2297 static gboolean inited = FALSE;
2300 return have_tls_get;
2302 #ifdef MONO_HAVE_FAST_TLS
2305 ins = (guint32*)pthread_getspecific;
2307 * We're looking for these two instructions:
2309 * mov 0x4(%esp),%eax
2310 * mov %gs:[offset](,%eax,4),%eax
2312 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2313 tls_gs_offset = ins [2];
2318 return have_tls_get;
2319 #elif defined(TARGET_ANDROID)
2327 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2329 #if defined(__APPLE__)
2330 x86_prefix (code, X86_GS_PREFIX);
2331 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2332 #elif defined(TARGET_WIN32)
2333 g_assert_not_reached ();
2335 x86_prefix (code, X86_GS_PREFIX);
2336 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2342 * mono_x86_emit_tls_get:
2343 * @code: buffer to store code to
2344 * @dreg: hard register where to place the result
2345 * @tls_offset: offset info
2347 * mono_x86_emit_tls_get emits in @code the native code that puts in
2348 * the dreg register the item in the thread local storage identified
2351 * Returns: a pointer to the end of the stored code
2354 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2356 #if defined(__APPLE__)
2357 x86_prefix (code, X86_GS_PREFIX);
2358 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2359 #elif defined(TARGET_WIN32)
2361 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2362 * Journal and/or a disassembly of the TlsGet () function.
2364 x86_prefix (code, X86_FS_PREFIX);
2365 x86_mov_reg_mem (code, dreg, 0x18, 4);
2366 if (tls_offset < 64) {
2367 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2371 g_assert (tls_offset < 0x440);
2372 /* Load TEB->TlsExpansionSlots */
2373 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2374 x86_test_reg_reg (code, dreg, dreg);
2376 x86_branch (code, X86_CC_EQ, code, TRUE);
2377 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2378 x86_patch (buf [0], code);
2381 if (optimize_for_xen) {
2382 x86_prefix (code, X86_GS_PREFIX);
2383 x86_mov_reg_mem (code, dreg, 0, 4);
2384 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2386 x86_prefix (code, X86_GS_PREFIX);
2387 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2394 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2396 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2397 #if defined(__APPLE__) || defined(__linux__)
2398 if (dreg != offset_reg)
2399 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2400 x86_prefix (code, X86_GS_PREFIX);
2401 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2403 g_assert_not_reached ();
2409 mono_x86_emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2411 return emit_tls_get_reg (code, dreg, offset_reg);
2415 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2417 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2419 g_assert_not_reached ();
2420 #elif defined(__APPLE__) || defined(__linux__)
2421 x86_prefix (code, X86_GS_PREFIX);
2422 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2424 g_assert_not_reached ();
2430 * mono_arch_translate_tls_offset:
2432 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2435 mono_arch_translate_tls_offset (int offset)
2438 return tls_gs_offset + (offset * 4);
2447 * Emit code to initialize an LMF structure at LMF_OFFSET.
2450 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2452 /* save all caller saved regs */
2453 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2454 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2455 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2456 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2457 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2458 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2459 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2461 /* save the current IP */
2462 if (cfg->compile_aot) {
2463 /* This pushes the current ip */
2464 x86_call_imm (code, 0);
2465 x86_pop_reg (code, X86_EAX);
2467 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2468 x86_mov_reg_imm (code, X86_EAX, 0);
2470 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2472 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2473 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2474 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2475 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2476 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2477 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2478 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2479 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2480 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2485 #define REAL_PRINT_REG(text,reg) \
2486 mono_assert (reg >= 0); \
2487 x86_push_reg (code, X86_EAX); \
2488 x86_push_reg (code, X86_EDX); \
2489 x86_push_reg (code, X86_ECX); \
2490 x86_push_reg (code, reg); \
2491 x86_push_imm (code, reg); \
2492 x86_push_imm (code, text " %d %p\n"); \
2493 x86_mov_reg_imm (code, X86_EAX, printf); \
2494 x86_call_reg (code, X86_EAX); \
2495 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2496 x86_pop_reg (code, X86_ECX); \
2497 x86_pop_reg (code, X86_EDX); \
2498 x86_pop_reg (code, X86_EAX);
2500 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2501 #ifdef __native__client_codegen__
2502 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2505 /* benchmark and set based on cpu */
2506 #define LOOP_ALIGNMENT 8
2507 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2511 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2516 guint8 *code = cfg->native_code + cfg->code_len;
2519 if (cfg->opt & MONO_OPT_LOOP) {
2520 int pad, align = LOOP_ALIGNMENT;
2521 /* set alignment depending on cpu */
2522 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2524 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2525 x86_padding (code, pad);
2526 cfg->code_len += pad;
2527 bb->native_offset = cfg->code_len;
2530 #ifdef __native_client_codegen__
2532 /* For Native Client, all indirect call/jump targets must be */
2533 /* 32-byte aligned. Exception handler blocks are jumped to */
2534 /* indirectly as well. */
2535 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2536 (bb->flags & BB_EXCEPTION_HANDLER);
2538 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2539 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2540 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2541 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2542 cfg->code_len += pad;
2543 bb->native_offset = cfg->code_len;
2546 #endif /* __native_client_codegen__ */
2547 if (cfg->verbose_level > 2)
2548 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2550 cpos = bb->max_offset;
2552 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
2553 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2554 g_assert (!cfg->compile_aot);
2557 cov->data [bb->dfn].cil_code = bb->cil_code;
2558 /* this is not thread save, but good enough */
2559 x86_inc_mem (code, &cov->data [bb->dfn].count);
2562 offset = code - cfg->native_code;
2564 mono_debug_open_block (cfg, bb, offset);
2566 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2567 x86_breakpoint (code);
2569 MONO_BB_FOR_EACH_INS (bb, ins) {
2570 offset = code - cfg->native_code;
2572 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2574 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2576 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2577 cfg->code_size *= 2;
2578 cfg->native_code = mono_realloc_native_code(cfg);
2579 code = cfg->native_code + offset;
2580 cfg->stat_code_reallocs++;
2583 if (cfg->debug_info)
2584 mono_debug_record_line_number (cfg, ins, offset);
2586 switch (ins->opcode) {
2588 x86_mul_reg (code, ins->sreg2, TRUE);
2591 x86_mul_reg (code, ins->sreg2, FALSE);
2593 case OP_X86_SETEQ_MEMBASE:
2594 case OP_X86_SETNE_MEMBASE:
2595 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2596 ins->inst_basereg, ins->inst_offset, TRUE);
2598 case OP_STOREI1_MEMBASE_IMM:
2599 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2601 case OP_STOREI2_MEMBASE_IMM:
2602 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2604 case OP_STORE_MEMBASE_IMM:
2605 case OP_STOREI4_MEMBASE_IMM:
2606 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2608 case OP_STOREI1_MEMBASE_REG:
2609 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2611 case OP_STOREI2_MEMBASE_REG:
2612 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2614 case OP_STORE_MEMBASE_REG:
2615 case OP_STOREI4_MEMBASE_REG:
2616 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2618 case OP_STORE_MEM_IMM:
2619 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2622 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2626 /* These are created by the cprop pass so they use inst_imm as the source */
2627 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2630 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2633 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2635 case OP_LOAD_MEMBASE:
2636 case OP_LOADI4_MEMBASE:
2637 case OP_LOADU4_MEMBASE:
2638 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2640 case OP_LOADU1_MEMBASE:
2641 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2643 case OP_LOADI1_MEMBASE:
2644 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2646 case OP_LOADU2_MEMBASE:
2647 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2649 case OP_LOADI2_MEMBASE:
2650 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2652 case OP_ICONV_TO_I1:
2654 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2656 case OP_ICONV_TO_I2:
2658 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2660 case OP_ICONV_TO_U1:
2661 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2663 case OP_ICONV_TO_U2:
2664 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2668 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2670 case OP_COMPARE_IMM:
2671 case OP_ICOMPARE_IMM:
2672 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2674 case OP_X86_COMPARE_MEMBASE_REG:
2675 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2677 case OP_X86_COMPARE_MEMBASE_IMM:
2678 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2680 case OP_X86_COMPARE_MEMBASE8_IMM:
2681 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2683 case OP_X86_COMPARE_REG_MEMBASE:
2684 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2686 case OP_X86_COMPARE_MEM_IMM:
2687 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2689 case OP_X86_TEST_NULL:
2690 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2692 case OP_X86_ADD_MEMBASE_IMM:
2693 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2695 case OP_X86_ADD_REG_MEMBASE:
2696 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2698 case OP_X86_SUB_MEMBASE_IMM:
2699 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2701 case OP_X86_SUB_REG_MEMBASE:
2702 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2704 case OP_X86_AND_MEMBASE_IMM:
2705 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2707 case OP_X86_OR_MEMBASE_IMM:
2708 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2710 case OP_X86_XOR_MEMBASE_IMM:
2711 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2713 case OP_X86_ADD_MEMBASE_REG:
2714 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2716 case OP_X86_SUB_MEMBASE_REG:
2717 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2719 case OP_X86_AND_MEMBASE_REG:
2720 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2722 case OP_X86_OR_MEMBASE_REG:
2723 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2725 case OP_X86_XOR_MEMBASE_REG:
2726 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2728 case OP_X86_INC_MEMBASE:
2729 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2731 case OP_X86_INC_REG:
2732 x86_inc_reg (code, ins->dreg);
2734 case OP_X86_DEC_MEMBASE:
2735 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2737 case OP_X86_DEC_REG:
2738 x86_dec_reg (code, ins->dreg);
2740 case OP_X86_MUL_REG_MEMBASE:
2741 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2743 case OP_X86_AND_REG_MEMBASE:
2744 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2746 case OP_X86_OR_REG_MEMBASE:
2747 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2749 case OP_X86_XOR_REG_MEMBASE:
2750 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2753 x86_breakpoint (code);
2755 case OP_RELAXED_NOP:
2756 x86_prefix (code, X86_REP_PREFIX);
2764 case OP_DUMMY_STORE:
2765 case OP_DUMMY_ICONST:
2766 case OP_DUMMY_R8CONST:
2767 case OP_NOT_REACHED:
2770 case OP_IL_SEQ_POINT:
2771 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2773 case OP_SEQ_POINT: {
2776 if (cfg->compile_aot)
2779 /* Have to use ecx as a temp reg since this can occur after OP_SETRET */
2782 * Read from the single stepping trigger page. This will cause a
2783 * SIGSEGV when single stepping is enabled.
2784 * We do this _before_ the breakpoint, so single stepping after
2785 * a breakpoint is hit will step to the next IL offset.
2787 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
2788 MonoInst *var = cfg->arch.ss_tramp_var;
2792 g_assert (var->opcode == OP_REGOFFSET);
2793 /* Load ss_tramp_var */
2794 /* This is equal to &ss_trampoline */
2795 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, sizeof (mgreg_t));
2796 x86_alu_membase_imm (code, X86_CMP, X86_ECX, 0, 0);
2797 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2798 x86_call_membase (code, X86_ECX, 0);
2799 x86_patch (br [0], code);
2803 * Many parts of sdb depend on the ip after the single step trampoline call to be equal to the seq point offset.
2804 * This means we have to put the loading of bp_tramp_var after the offset.
2807 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2809 MonoInst *var = cfg->arch.bp_tramp_var;
2812 g_assert (var->opcode == OP_REGOFFSET);
2813 /* Load the address of the bp trampoline */
2814 /* This needs to be constant size */
2815 guint8 *start = code;
2816 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, 4);
2817 if (code < start + OP_SEQ_POINT_BP_OFFSET) {
2818 int size = start + OP_SEQ_POINT_BP_OFFSET - code;
2819 x86_padding (code, size);
2822 * A placeholder for a possible breakpoint inserted by
2823 * mono_arch_set_breakpoint ().
2825 for (i = 0; i < 2; ++i)
2828 * Add an additional nop so skipping the bp doesn't cause the ip to point
2829 * to another IL offset.
2837 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2841 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2846 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2850 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2855 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2859 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2864 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2868 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2871 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2875 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2879 #if defined( __native_client_codegen__ )
2880 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2881 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2884 * The code is the same for div/rem, the allocator will allocate dreg
2885 * to RAX/RDX as appropriate.
2887 if (ins->sreg2 == X86_EDX) {
2888 /* cdq clobbers this */
2889 x86_push_reg (code, ins->sreg2);
2891 x86_div_membase (code, X86_ESP, 0, TRUE);
2892 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2895 x86_div_reg (code, ins->sreg2, TRUE);
2900 #if defined( __native_client_codegen__ )
2901 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2902 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2904 if (ins->sreg2 == X86_EDX) {
2905 x86_push_reg (code, ins->sreg2);
2906 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2907 x86_div_membase (code, X86_ESP, 0, FALSE);
2908 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2910 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2911 x86_div_reg (code, ins->sreg2, FALSE);
2915 #if defined( __native_client_codegen__ )
2916 if (ins->inst_imm == 0) {
2917 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2918 x86_jump32 (code, 0);
2922 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2924 x86_div_reg (code, ins->sreg2, TRUE);
2927 int power = mono_is_power_of_two (ins->inst_imm);
2929 g_assert (ins->sreg1 == X86_EAX);
2930 g_assert (ins->dreg == X86_EAX);
2931 g_assert (power >= 0);
2934 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2936 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2938 * If the divident is >= 0, this does not nothing. If it is positive, it
2939 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2941 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2942 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2943 } else if (power == 0) {
2944 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2946 /* Based on gcc code */
2948 /* Add compensation for negative dividents */
2950 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2951 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2952 /* Compute remainder */
2953 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2954 /* Remove compensation */
2955 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2960 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2964 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2967 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2971 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2974 g_assert (ins->sreg2 == X86_ECX);
2975 x86_shift_reg (code, X86_SHL, ins->dreg);
2978 g_assert (ins->sreg2 == X86_ECX);
2979 x86_shift_reg (code, X86_SAR, ins->dreg);
2983 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2986 case OP_ISHR_UN_IMM:
2987 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2990 g_assert (ins->sreg2 == X86_ECX);
2991 x86_shift_reg (code, X86_SHR, ins->dreg);
2995 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2998 guint8 *jump_to_end;
3000 /* handle shifts below 32 bits */
3001 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
3002 x86_shift_reg (code, X86_SHL, ins->sreg1);
3004 x86_test_reg_imm (code, X86_ECX, 32);
3005 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3007 /* handle shift over 32 bit */
3008 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3009 x86_clear_reg (code, ins->sreg1);
3011 x86_patch (jump_to_end, code);
3015 guint8 *jump_to_end;
3017 /* handle shifts below 32 bits */
3018 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3019 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
3021 x86_test_reg_imm (code, X86_ECX, 32);
3022 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3024 /* handle shifts over 31 bits */
3025 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3026 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
3028 x86_patch (jump_to_end, code);
3032 guint8 *jump_to_end;
3034 /* handle shifts below 32 bits */
3035 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3036 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
3038 x86_test_reg_imm (code, X86_ECX, 32);
3039 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3041 /* handle shifts over 31 bits */
3042 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3043 x86_clear_reg (code, ins->backend.reg3);
3045 x86_patch (jump_to_end, code);
3049 if (ins->inst_imm >= 32) {
3050 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3051 x86_clear_reg (code, ins->sreg1);
3052 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
3054 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
3055 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
3059 if (ins->inst_imm >= 32) {
3060 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3061 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
3062 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
3064 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3065 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3068 case OP_LSHR_UN_IMM:
3069 if (ins->inst_imm >= 32) {
3070 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3071 x86_clear_reg (code, ins->backend.reg3);
3072 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3074 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3075 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3079 x86_not_reg (code, ins->sreg1);
3082 x86_neg_reg (code, ins->sreg1);
3086 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3090 switch (ins->inst_imm) {
3094 if (ins->dreg != ins->sreg1)
3095 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3096 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3099 /* LEA r1, [r2 + r2*2] */
3100 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3103 /* LEA r1, [r2 + r2*4] */
3104 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3107 /* LEA r1, [r2 + r2*2] */
3109 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3110 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3113 /* LEA r1, [r2 + r2*8] */
3114 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3117 /* LEA r1, [r2 + r2*4] */
3119 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3120 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3123 /* LEA r1, [r2 + r2*2] */
3125 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3126 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3129 /* LEA r1, [r2 + r2*4] */
3130 /* LEA r1, [r1 + r1*4] */
3131 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3132 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3135 /* LEA r1, [r2 + r2*4] */
3137 /* LEA r1, [r1 + r1*4] */
3138 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3139 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3140 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3143 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3148 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3149 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3151 case OP_IMUL_OVF_UN: {
3152 /* the mul operation and the exception check should most likely be split */
3153 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3154 /*g_assert (ins->sreg2 == X86_EAX);
3155 g_assert (ins->dreg == X86_EAX);*/
3156 if (ins->sreg2 == X86_EAX) {
3157 non_eax_reg = ins->sreg1;
3158 } else if (ins->sreg1 == X86_EAX) {
3159 non_eax_reg = ins->sreg2;
3161 /* no need to save since we're going to store to it anyway */
3162 if (ins->dreg != X86_EAX) {
3164 x86_push_reg (code, X86_EAX);
3166 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3167 non_eax_reg = ins->sreg2;
3169 if (ins->dreg == X86_EDX) {
3172 x86_push_reg (code, X86_EAX);
3174 } else if (ins->dreg != X86_EAX) {
3176 x86_push_reg (code, X86_EDX);
3178 x86_mul_reg (code, non_eax_reg, FALSE);
3179 /* save before the check since pop and mov don't change the flags */
3180 if (ins->dreg != X86_EAX)
3181 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3183 x86_pop_reg (code, X86_EDX);
3185 x86_pop_reg (code, X86_EAX);
3186 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3190 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3193 g_assert_not_reached ();
3194 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3195 x86_mov_reg_imm (code, ins->dreg, 0);
3198 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3199 x86_mov_reg_imm (code, ins->dreg, 0);
3201 case OP_LOAD_GOTADDR:
3202 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3203 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3206 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3207 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3209 case OP_X86_PUSH_GOT_ENTRY:
3210 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3211 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3214 if (ins->dreg != ins->sreg1)
3215 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3218 MonoCallInst *call = (MonoCallInst*)ins;
3221 ins->flags |= MONO_INST_GC_CALLSITE;
3222 ins->backend.pc_offset = code - cfg->native_code;
3224 /* reset offset to make max_len work */
3225 offset = code - cfg->native_code;
3227 g_assert (!cfg->method->save_lmf);
3229 /* restore callee saved registers */
3230 for (i = 0; i < X86_NREG; ++i)
3231 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3233 if (cfg->used_int_regs & (1 << X86_ESI)) {
3234 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3237 if (cfg->used_int_regs & (1 << X86_EDI)) {
3238 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3241 if (cfg->used_int_regs & (1 << X86_EBX)) {
3242 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3246 /* Copy arguments on the stack to our argument area */
3247 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3248 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3249 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3252 /* restore ESP/EBP */
3254 offset = code - cfg->native_code;
3255 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3256 x86_jump32 (code, 0);
3258 ins->flags |= MONO_INST_GC_CALLSITE;
3259 cfg->disable_aot = TRUE;
3263 /* ensure ins->sreg1 is not NULL
3264 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3265 * cmp DWORD PTR [eax], 0
3267 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3270 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3271 x86_push_reg (code, hreg);
3272 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3273 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3274 x86_pop_reg (code, hreg);
3287 case OP_VOIDCALL_REG:
3289 case OP_FCALL_MEMBASE:
3290 case OP_LCALL_MEMBASE:
3291 case OP_VCALL_MEMBASE:
3292 case OP_VCALL2_MEMBASE:
3293 case OP_VOIDCALL_MEMBASE:
3294 case OP_CALL_MEMBASE: {
3297 call = (MonoCallInst*)ins;
3298 cinfo = (CallInfo*)call->call_info;
3300 switch (ins->opcode) {
3307 if (ins->flags & MONO_INST_HAS_METHOD)
3308 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3310 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3316 case OP_VOIDCALL_REG:
3318 x86_call_reg (code, ins->sreg1);
3320 case OP_FCALL_MEMBASE:
3321 case OP_LCALL_MEMBASE:
3322 case OP_VCALL_MEMBASE:
3323 case OP_VCALL2_MEMBASE:
3324 case OP_VOIDCALL_MEMBASE:
3325 case OP_CALL_MEMBASE:
3326 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3329 g_assert_not_reached ();
3332 ins->flags |= MONO_INST_GC_CALLSITE;
3333 ins->backend.pc_offset = code - cfg->native_code;
3334 if (cinfo->callee_stack_pop) {
3335 /* Have to compensate for the stack space popped by the callee */
3336 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3338 code = emit_move_return_value (cfg, ins, code);
3342 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3344 case OP_X86_LEA_MEMBASE:
3345 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3348 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3351 /* keep alignment */
3352 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3353 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3354 code = mono_emit_stack_alloc (cfg, code, ins);
3355 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3356 if (cfg->param_area)
3357 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3359 case OP_LOCALLOC_IMM: {
3360 guint32 size = ins->inst_imm;
3361 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3363 if (ins->flags & MONO_INST_INIT) {
3364 /* FIXME: Optimize this */
3365 x86_mov_reg_imm (code, ins->dreg, size);
3366 ins->sreg1 = ins->dreg;
3368 code = mono_emit_stack_alloc (cfg, code, ins);
3369 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3371 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3372 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3374 if (cfg->param_area)
3375 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3379 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3380 x86_push_reg (code, ins->sreg1);
3381 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3382 (gpointer)"mono_arch_throw_exception");
3383 ins->flags |= MONO_INST_GC_CALLSITE;
3384 ins->backend.pc_offset = code - cfg->native_code;
3388 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3389 x86_push_reg (code, ins->sreg1);
3390 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3391 (gpointer)"mono_arch_rethrow_exception");
3392 ins->flags |= MONO_INST_GC_CALLSITE;
3393 ins->backend.pc_offset = code - cfg->native_code;
3396 case OP_CALL_HANDLER:
3397 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3398 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3399 x86_call_imm (code, 0);
3400 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3401 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3403 case OP_START_HANDLER: {
3404 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3405 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3406 if (cfg->param_area)
3407 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3410 case OP_ENDFINALLY: {
3411 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3412 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3416 case OP_ENDFILTER: {
3417 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3418 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3419 /* The local allocator will put the result into EAX */
3424 if (ins->dreg != X86_EAX)
3425 x86_mov_reg_reg (code, ins->dreg, X86_EAX, sizeof (gpointer));
3429 ins->inst_c0 = code - cfg->native_code;
3432 if (ins->inst_target_bb->native_offset) {
3433 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3435 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3436 if ((cfg->opt & MONO_OPT_BRANCH) &&
3437 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3438 x86_jump8 (code, 0);
3440 x86_jump32 (code, 0);
3444 x86_jump_reg (code, ins->sreg1);
3463 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3464 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3466 case OP_COND_EXC_EQ:
3467 case OP_COND_EXC_NE_UN:
3468 case OP_COND_EXC_LT:
3469 case OP_COND_EXC_LT_UN:
3470 case OP_COND_EXC_GT:
3471 case OP_COND_EXC_GT_UN:
3472 case OP_COND_EXC_GE:
3473 case OP_COND_EXC_GE_UN:
3474 case OP_COND_EXC_LE:
3475 case OP_COND_EXC_LE_UN:
3476 case OP_COND_EXC_IEQ:
3477 case OP_COND_EXC_INE_UN:
3478 case OP_COND_EXC_ILT:
3479 case OP_COND_EXC_ILT_UN:
3480 case OP_COND_EXC_IGT:
3481 case OP_COND_EXC_IGT_UN:
3482 case OP_COND_EXC_IGE:
3483 case OP_COND_EXC_IGE_UN:
3484 case OP_COND_EXC_ILE:
3485 case OP_COND_EXC_ILE_UN:
3486 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3488 case OP_COND_EXC_OV:
3489 case OP_COND_EXC_NO:
3491 case OP_COND_EXC_NC:
3492 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3494 case OP_COND_EXC_IOV:
3495 case OP_COND_EXC_INO:
3496 case OP_COND_EXC_IC:
3497 case OP_COND_EXC_INC:
3498 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3510 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3518 case OP_CMOV_INE_UN:
3519 case OP_CMOV_IGE_UN:
3520 case OP_CMOV_IGT_UN:
3521 case OP_CMOV_ILE_UN:
3522 case OP_CMOV_ILT_UN:
3523 g_assert (ins->dreg == ins->sreg1);
3524 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3527 /* floating point opcodes */
3529 double d = *(double *)ins->inst_p0;
3531 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3533 } else if (d == 1.0) {
3536 if (cfg->compile_aot) {
3537 guint32 *val = (guint32*)&d;
3538 x86_push_imm (code, val [1]);
3539 x86_push_imm (code, val [0]);
3540 x86_fld_membase (code, X86_ESP, 0, TRUE);
3541 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3544 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3545 x86_fld (code, NULL, TRUE);
3551 float f = *(float *)ins->inst_p0;
3553 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3555 } else if (f == 1.0) {
3558 if (cfg->compile_aot) {
3559 guint32 val = *(guint32*)&f;
3560 x86_push_imm (code, val);
3561 x86_fld_membase (code, X86_ESP, 0, FALSE);
3562 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3565 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3566 x86_fld (code, NULL, FALSE);
3571 case OP_STORER8_MEMBASE_REG:
3572 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3574 case OP_LOADR8_MEMBASE:
3575 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3577 case OP_STORER4_MEMBASE_REG:
3578 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3580 case OP_LOADR4_MEMBASE:
3581 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3583 case OP_ICONV_TO_R4:
3584 x86_push_reg (code, ins->sreg1);
3585 x86_fild_membase (code, X86_ESP, 0, FALSE);
3586 /* Change precision */
3587 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3588 x86_fld_membase (code, X86_ESP, 0, FALSE);
3589 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3591 case OP_ICONV_TO_R8:
3592 x86_push_reg (code, ins->sreg1);
3593 x86_fild_membase (code, X86_ESP, 0, FALSE);
3594 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3596 case OP_ICONV_TO_R_UN:
3597 x86_push_imm (code, 0);
3598 x86_push_reg (code, ins->sreg1);
3599 x86_fild_membase (code, X86_ESP, 0, TRUE);
3600 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3602 case OP_X86_FP_LOAD_I8:
3603 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3605 case OP_X86_FP_LOAD_I4:
3606 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3608 case OP_FCONV_TO_R4:
3609 /* Change precision */
3610 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3611 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3612 x86_fld_membase (code, X86_ESP, 0, FALSE);
3613 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3615 case OP_FCONV_TO_I1:
3616 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3618 case OP_FCONV_TO_U1:
3619 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3621 case OP_FCONV_TO_I2:
3622 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3624 case OP_FCONV_TO_U2:
3625 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3627 case OP_FCONV_TO_I4:
3629 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3631 case OP_FCONV_TO_I8:
3632 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3633 x86_fnstcw_membase(code, X86_ESP, 0);
3634 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3635 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3636 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3637 x86_fldcw_membase (code, X86_ESP, 2);
3638 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3639 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3640 x86_pop_reg (code, ins->dreg);
3641 x86_pop_reg (code, ins->backend.reg3);
3642 x86_fldcw_membase (code, X86_ESP, 0);
3643 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3645 case OP_LCONV_TO_R8_2:
3646 x86_push_reg (code, ins->sreg2);
3647 x86_push_reg (code, ins->sreg1);
3648 x86_fild_membase (code, X86_ESP, 0, TRUE);
3649 /* Change precision */
3650 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3651 x86_fld_membase (code, X86_ESP, 0, TRUE);
3652 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3654 case OP_LCONV_TO_R4_2:
3655 x86_push_reg (code, ins->sreg2);
3656 x86_push_reg (code, ins->sreg1);
3657 x86_fild_membase (code, X86_ESP, 0, TRUE);
3658 /* Change precision */
3659 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3660 x86_fld_membase (code, X86_ESP, 0, FALSE);
3661 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3663 case OP_LCONV_TO_R_UN_2: {
3664 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3667 /* load 64bit integer to FP stack */
3668 x86_push_reg (code, ins->sreg2);
3669 x86_push_reg (code, ins->sreg1);
3670 x86_fild_membase (code, X86_ESP, 0, TRUE);
3672 /* test if lreg is negative */
3673 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3674 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3676 /* add correction constant mn */
3677 if (cfg->compile_aot) {
3678 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3679 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3680 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3681 x86_fld80_membase (code, X86_ESP, 2);
3682 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3684 x86_fld80_mem (code, mn);
3686 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3688 x86_patch (br, code);
3690 /* Change precision */
3691 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3692 x86_fld_membase (code, X86_ESP, 0, TRUE);
3694 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3698 case OP_LCONV_TO_OVF_I:
3699 case OP_LCONV_TO_OVF_I4_2: {
3700 guint8 *br [3], *label [1];
3704 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3706 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3708 /* If the low word top bit is set, see if we are negative */
3709 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3710 /* We are not negative (no top bit set, check for our top word to be zero */
3711 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3712 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3715 /* throw exception */
3716 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3718 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3719 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3720 x86_jump8 (code, 0);
3722 x86_jump32 (code, 0);
3724 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3725 x86_jump32 (code, 0);
3729 x86_patch (br [0], code);
3730 /* our top bit is set, check that top word is 0xfffffff */
3731 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3733 x86_patch (br [1], code);
3734 /* nope, emit exception */
3735 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3736 x86_patch (br [2], label [0]);
3738 if (ins->dreg != ins->sreg1)
3739 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3743 /* Not needed on the fp stack */
3745 case OP_MOVE_F_TO_I4:
3746 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
3747 x86_mov_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, 4);
3749 case OP_MOVE_I4_TO_F:
3750 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
3751 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
3754 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3757 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3760 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3763 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3771 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3776 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3783 * it really doesn't make sense to inline all this code,
3784 * it's here just to show that things may not be as simple
3787 guchar *check_pos, *end_tan, *pop_jump;
3788 x86_push_reg (code, X86_EAX);
3791 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3793 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3794 x86_fstp (code, 0); /* pop the 1.0 */
3796 x86_jump8 (code, 0);
3798 x86_fp_op (code, X86_FADD, 0);
3802 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3804 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3807 x86_patch (pop_jump, code);
3808 x86_fstp (code, 0); /* pop the 1.0 */
3809 x86_patch (check_pos, code);
3810 x86_patch (end_tan, code);
3812 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3813 x86_pop_reg (code, X86_EAX);
3820 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3829 g_assert (cfg->opt & MONO_OPT_CMOV);
3830 g_assert (ins->dreg == ins->sreg1);
3831 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3832 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3835 g_assert (cfg->opt & MONO_OPT_CMOV);
3836 g_assert (ins->dreg == ins->sreg1);
3837 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3838 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3841 g_assert (cfg->opt & MONO_OPT_CMOV);
3842 g_assert (ins->dreg == ins->sreg1);
3843 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3844 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3847 g_assert (cfg->opt & MONO_OPT_CMOV);
3848 g_assert (ins->dreg == ins->sreg1);
3849 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3850 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3856 x86_fxch (code, ins->inst_imm);
3861 x86_push_reg (code, X86_EAX);
3862 /* we need to exchange ST(0) with ST(1) */
3865 /* this requires a loop, because fprem somtimes
3866 * returns a partial remainder */
3868 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3869 /* x86_fprem1 (code); */
3872 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3874 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3880 x86_pop_reg (code, X86_EAX);
3884 if (cfg->opt & MONO_OPT_FCMOV) {
3885 x86_fcomip (code, 1);
3889 /* this overwrites EAX */
3890 EMIT_FPCOMPARE(code);
3891 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3895 if (cfg->opt & MONO_OPT_FCMOV) {
3896 /* zeroing the register at the start results in
3897 * shorter and faster code (we can also remove the widening op)
3899 guchar *unordered_check;
3900 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3901 x86_fcomip (code, 1);
3903 unordered_check = code;
3904 x86_branch8 (code, X86_CC_P, 0, FALSE);
3905 if (ins->opcode == OP_FCEQ) {
3906 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3907 x86_patch (unordered_check, code);
3909 guchar *jump_to_end;
3910 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3912 x86_jump8 (code, 0);
3913 x86_patch (unordered_check, code);
3914 x86_inc_reg (code, ins->dreg);
3915 x86_patch (jump_to_end, code);
3920 if (ins->dreg != X86_EAX)
3921 x86_push_reg (code, X86_EAX);
3923 EMIT_FPCOMPARE(code);
3924 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3925 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3926 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3927 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3929 if (ins->dreg != X86_EAX)
3930 x86_pop_reg (code, X86_EAX);
3934 if (cfg->opt & MONO_OPT_FCMOV) {
3935 /* zeroing the register at the start results in
3936 * shorter and faster code (we can also remove the widening op)
3938 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3939 x86_fcomip (code, 1);
3941 if (ins->opcode == OP_FCLT_UN) {
3942 guchar *unordered_check = code;
3943 guchar *jump_to_end;
3944 x86_branch8 (code, X86_CC_P, 0, FALSE);
3945 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3947 x86_jump8 (code, 0);
3948 x86_patch (unordered_check, code);
3949 x86_inc_reg (code, ins->dreg);
3950 x86_patch (jump_to_end, code);
3952 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3956 if (ins->dreg != X86_EAX)
3957 x86_push_reg (code, X86_EAX);
3959 EMIT_FPCOMPARE(code);
3960 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3961 if (ins->opcode == OP_FCLT_UN) {
3962 guchar *is_not_zero_check, *end_jump;
3963 is_not_zero_check = code;
3964 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3966 x86_jump8 (code, 0);
3967 x86_patch (is_not_zero_check, code);
3968 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3970 x86_patch (end_jump, code);
3972 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3973 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3975 if (ins->dreg != X86_EAX)
3976 x86_pop_reg (code, X86_EAX);
3979 guchar *unordered_check;
3980 guchar *jump_to_end;
3981 if (cfg->opt & MONO_OPT_FCMOV) {
3982 /* zeroing the register at the start results in
3983 * shorter and faster code (we can also remove the widening op)
3985 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3986 x86_fcomip (code, 1);
3988 unordered_check = code;
3989 x86_branch8 (code, X86_CC_P, 0, FALSE);
3990 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3991 x86_patch (unordered_check, code);
3994 if (ins->dreg != X86_EAX)
3995 x86_push_reg (code, X86_EAX);
3997 EMIT_FPCOMPARE(code);
3998 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3999 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4000 unordered_check = code;
4001 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4003 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4004 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
4005 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4007 x86_jump8 (code, 0);
4008 x86_patch (unordered_check, code);
4009 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4010 x86_patch (jump_to_end, code);
4012 if (ins->dreg != X86_EAX)
4013 x86_pop_reg (code, X86_EAX);
4018 if (cfg->opt & MONO_OPT_FCMOV) {
4019 /* zeroing the register at the start results in
4020 * shorter and faster code (we can also remove the widening op)
4022 guchar *unordered_check;
4023 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4024 x86_fcomip (code, 1);
4026 if (ins->opcode == OP_FCGT) {
4027 unordered_check = code;
4028 x86_branch8 (code, X86_CC_P, 0, FALSE);
4029 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4030 x86_patch (unordered_check, code);
4032 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4036 if (ins->dreg != X86_EAX)
4037 x86_push_reg (code, X86_EAX);
4039 EMIT_FPCOMPARE(code);
4040 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4041 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4042 if (ins->opcode == OP_FCGT_UN) {
4043 guchar *is_not_zero_check, *end_jump;
4044 is_not_zero_check = code;
4045 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4047 x86_jump8 (code, 0);
4048 x86_patch (is_not_zero_check, code);
4049 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4051 x86_patch (end_jump, code);
4053 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4054 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4056 if (ins->dreg != X86_EAX)
4057 x86_pop_reg (code, X86_EAX);
4060 guchar *unordered_check;
4061 guchar *jump_to_end;
4062 if (cfg->opt & MONO_OPT_FCMOV) {
4063 /* zeroing the register at the start results in
4064 * shorter and faster code (we can also remove the widening op)
4066 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4067 x86_fcomip (code, 1);
4069 unordered_check = code;
4070 x86_branch8 (code, X86_CC_P, 0, FALSE);
4071 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4072 x86_patch (unordered_check, code);
4075 if (ins->dreg != X86_EAX)
4076 x86_push_reg (code, X86_EAX);
4078 EMIT_FPCOMPARE(code);
4079 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4080 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4081 unordered_check = code;
4082 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4084 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4085 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4086 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4088 x86_jump8 (code, 0);
4089 x86_patch (unordered_check, code);
4090 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4091 x86_patch (jump_to_end, code);
4093 if (ins->dreg != X86_EAX)
4094 x86_pop_reg (code, X86_EAX);
4098 if (cfg->opt & MONO_OPT_FCMOV) {
4099 guchar *jump = code;
4100 x86_branch8 (code, X86_CC_P, 0, TRUE);
4101 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4102 x86_patch (jump, code);
4105 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4106 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4109 /* Branch if C013 != 100 */
4110 if (cfg->opt & MONO_OPT_FCMOV) {
4111 /* branch if !ZF or (PF|CF) */
4112 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4113 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4114 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4117 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4118 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4121 if (cfg->opt & MONO_OPT_FCMOV) {
4122 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4125 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4128 if (cfg->opt & MONO_OPT_FCMOV) {
4129 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4130 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4133 if (ins->opcode == OP_FBLT_UN) {
4134 guchar *is_not_zero_check, *end_jump;
4135 is_not_zero_check = code;
4136 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4138 x86_jump8 (code, 0);
4139 x86_patch (is_not_zero_check, code);
4140 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4142 x86_patch (end_jump, code);
4144 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4148 if (cfg->opt & MONO_OPT_FCMOV) {
4149 if (ins->opcode == OP_FBGT) {
4152 /* skip branch if C1=1 */
4154 x86_branch8 (code, X86_CC_P, 0, FALSE);
4155 /* branch if (C0 | C3) = 1 */
4156 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4157 x86_patch (br1, code);
4159 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4163 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4164 if (ins->opcode == OP_FBGT_UN) {
4165 guchar *is_not_zero_check, *end_jump;
4166 is_not_zero_check = code;
4167 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4169 x86_jump8 (code, 0);
4170 x86_patch (is_not_zero_check, code);
4171 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4173 x86_patch (end_jump, code);
4175 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4178 /* Branch if C013 == 100 or 001 */
4179 if (cfg->opt & MONO_OPT_FCMOV) {
4182 /* skip branch if C1=1 */
4184 x86_branch8 (code, X86_CC_P, 0, FALSE);
4185 /* branch if (C0 | C3) = 1 */
4186 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4187 x86_patch (br1, code);
4190 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4191 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4192 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4193 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4196 /* Branch if C013 == 000 */
4197 if (cfg->opt & MONO_OPT_FCMOV) {
4198 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4201 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4204 /* Branch if C013=000 or 100 */
4205 if (cfg->opt & MONO_OPT_FCMOV) {
4208 /* skip branch if C1=1 */
4210 x86_branch8 (code, X86_CC_P, 0, FALSE);
4211 /* branch if C0=0 */
4212 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4213 x86_patch (br1, code);
4216 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4217 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4218 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4221 /* Branch if C013 != 001 */
4222 if (cfg->opt & MONO_OPT_FCMOV) {
4223 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4224 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4227 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4228 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4232 x86_push_reg (code, X86_EAX);
4235 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4236 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4237 x86_pop_reg (code, X86_EAX);
4239 /* Have to clean up the fp stack before throwing the exception */
4241 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4244 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4246 x86_patch (br1, code);
4250 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4253 case OP_TLS_GET_REG: {
4254 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4258 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4261 case OP_TLS_SET_REG: {
4262 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4265 case OP_MEMORY_BARRIER: {
4266 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4267 x86_prefix (code, X86_LOCK_PREFIX);
4268 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4272 case OP_ATOMIC_ADD_I4: {
4273 int dreg = ins->dreg;
4275 g_assert (cfg->has_atomic_add_i4);
4277 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4278 if (ins->sreg2 == dreg) {
4279 if (dreg == X86_EBX) {
4281 if (ins->inst_basereg == X86_EDI)
4285 if (ins->inst_basereg == X86_EBX)
4288 } else if (ins->inst_basereg == dreg) {
4289 if (dreg == X86_EBX) {
4291 if (ins->sreg2 == X86_EDI)
4295 if (ins->sreg2 == X86_EBX)
4300 if (dreg != ins->dreg) {
4301 x86_push_reg (code, dreg);
4304 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4305 x86_prefix (code, X86_LOCK_PREFIX);
4306 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4307 /* dreg contains the old value, add with sreg2 value */
4308 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4310 if (ins->dreg != dreg) {
4311 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4312 x86_pop_reg (code, dreg);
4317 case OP_ATOMIC_EXCHANGE_I4: {
4319 int sreg2 = ins->sreg2;
4320 int breg = ins->inst_basereg;
4322 g_assert (cfg->has_atomic_exchange_i4);
4324 /* cmpxchg uses eax as comperand, need to make sure we can use it
4325 * hack to overcome limits in x86 reg allocator
4326 * (req: dreg == eax and sreg2 != eax and breg != eax)
4328 g_assert (ins->dreg == X86_EAX);
4330 /* We need the EAX reg for the cmpxchg */
4331 if (ins->sreg2 == X86_EAX) {
4332 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4333 x86_push_reg (code, sreg2);
4334 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4337 if (breg == X86_EAX) {
4338 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4339 x86_push_reg (code, breg);
4340 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4343 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4345 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4346 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4347 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4348 x86_patch (br [1], br [0]);
4350 if (breg != ins->inst_basereg)
4351 x86_pop_reg (code, breg);
4353 if (ins->sreg2 != sreg2)
4354 x86_pop_reg (code, sreg2);
4358 case OP_ATOMIC_CAS_I4: {
4359 g_assert (ins->dreg == X86_EAX);
4360 g_assert (ins->sreg3 == X86_EAX);
4361 g_assert (ins->sreg1 != X86_EAX);
4362 g_assert (ins->sreg1 != ins->sreg2);
4364 x86_prefix (code, X86_LOCK_PREFIX);
4365 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4368 case OP_ATOMIC_LOAD_I1: {
4369 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4372 case OP_ATOMIC_LOAD_U1: {
4373 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4376 case OP_ATOMIC_LOAD_I2: {
4377 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4380 case OP_ATOMIC_LOAD_U2: {
4381 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4384 case OP_ATOMIC_LOAD_I4:
4385 case OP_ATOMIC_LOAD_U4: {
4386 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4389 case OP_ATOMIC_LOAD_R4:
4390 case OP_ATOMIC_LOAD_R8: {
4391 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4394 case OP_ATOMIC_STORE_I1:
4395 case OP_ATOMIC_STORE_U1:
4396 case OP_ATOMIC_STORE_I2:
4397 case OP_ATOMIC_STORE_U2:
4398 case OP_ATOMIC_STORE_I4:
4399 case OP_ATOMIC_STORE_U4: {
4402 switch (ins->opcode) {
4403 case OP_ATOMIC_STORE_I1:
4404 case OP_ATOMIC_STORE_U1:
4407 case OP_ATOMIC_STORE_I2:
4408 case OP_ATOMIC_STORE_U2:
4411 case OP_ATOMIC_STORE_I4:
4412 case OP_ATOMIC_STORE_U4:
4417 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4419 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4423 case OP_ATOMIC_STORE_R4:
4424 case OP_ATOMIC_STORE_R8: {
4425 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4427 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4431 case OP_CARD_TABLE_WBARRIER: {
4432 int ptr = ins->sreg1;
4433 int value = ins->sreg2;
4435 int nursery_shift, card_table_shift;
4436 gpointer card_table_mask;
4437 size_t nursery_size;
4438 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4439 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4440 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4443 * We need one register we can clobber, we choose EDX and make sreg1
4444 * fixed EAX to work around limitations in the local register allocator.
4445 * sreg2 might get allocated to EDX, but that is not a problem since
4446 * we use it before clobbering EDX.
4448 g_assert (ins->sreg1 == X86_EAX);
4451 * This is the code we produce:
4454 * edx >>= nursery_shift
4455 * cmp edx, (nursery_start >> nursery_shift)
4458 * edx >>= card_table_shift
4459 * card_table[edx] = 1
4463 if (card_table_nursery_check) {
4464 if (value != X86_EDX)
4465 x86_mov_reg_reg (code, X86_EDX, value, 4);
4466 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4467 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4468 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4470 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4471 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4472 if (card_table_mask)
4473 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4474 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4475 if (card_table_nursery_check)
4476 x86_patch (br, code);
4479 #ifdef MONO_ARCH_SIMD_INTRINSICS
4481 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4484 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4487 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4490 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4493 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4496 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4499 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4500 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4503 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4506 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4509 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4512 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4515 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4518 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4521 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4524 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4527 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4530 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4533 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4536 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4539 case OP_PSHUFLEW_HIGH:
4540 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4541 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4543 case OP_PSHUFLEW_LOW:
4544 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4545 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4548 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4549 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4552 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4553 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4556 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4557 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4561 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4564 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4567 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4570 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4573 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4576 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4579 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4580 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4583 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4586 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4589 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4592 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4595 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4598 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4601 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4604 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4607 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4610 case OP_EXTRACT_MASK:
4611 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4615 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4618 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4621 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4625 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4628 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4631 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4634 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4638 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4641 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4644 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4647 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4651 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4654 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4657 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4661 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4664 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4667 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4671 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4674 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4678 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4681 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4684 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4688 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4691 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4694 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4698 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4701 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4704 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4707 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4711 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4714 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4717 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4720 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4723 case OP_PSUM_ABS_DIFF:
4724 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4727 case OP_UNPACK_LOWB:
4728 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4730 case OP_UNPACK_LOWW:
4731 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4733 case OP_UNPACK_LOWD:
4734 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4736 case OP_UNPACK_LOWQ:
4737 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4739 case OP_UNPACK_LOWPS:
4740 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4742 case OP_UNPACK_LOWPD:
4743 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4746 case OP_UNPACK_HIGHB:
4747 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4749 case OP_UNPACK_HIGHW:
4750 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4752 case OP_UNPACK_HIGHD:
4753 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4755 case OP_UNPACK_HIGHQ:
4756 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4758 case OP_UNPACK_HIGHPS:
4759 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4761 case OP_UNPACK_HIGHPD:
4762 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4766 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4769 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4772 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4775 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4778 case OP_PADDB_SAT_UN:
4779 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4781 case OP_PSUBB_SAT_UN:
4782 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4784 case OP_PADDW_SAT_UN:
4785 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4787 case OP_PSUBW_SAT_UN:
4788 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4792 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4795 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4798 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4801 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4805 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4808 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4811 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4813 case OP_PMULW_HIGH_UN:
4814 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4817 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4821 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4824 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4828 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4831 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4835 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4838 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4842 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4845 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4849 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4852 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4856 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4859 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4863 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4866 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4870 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4873 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4877 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4880 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4884 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4886 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4887 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4891 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4893 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4894 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4898 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4900 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4901 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4905 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4907 case OP_EXTRACTX_U2:
4908 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4910 case OP_INSERTX_U1_SLOW:
4911 /*sreg1 is the extracted ireg (scratch)
4912 /sreg2 is the to be inserted ireg (scratch)
4913 /dreg is the xreg to receive the value*/
4915 /*clear the bits from the extracted word*/
4916 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4917 /*shift the value to insert if needed*/
4918 if (ins->inst_c0 & 1)
4919 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4920 /*join them together*/
4921 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4922 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4924 case OP_INSERTX_I4_SLOW:
4925 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4926 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4927 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4930 case OP_INSERTX_R4_SLOW:
4931 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4932 /*TODO if inst_c0 == 0 use movss*/
4933 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4934 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4936 case OP_INSERTX_R8_SLOW:
4937 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4938 if (cfg->verbose_level)
4939 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4941 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4943 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4946 case OP_STOREX_MEMBASE_REG:
4947 case OP_STOREX_MEMBASE:
4948 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4950 case OP_LOADX_MEMBASE:
4951 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4953 case OP_LOADX_ALIGNED_MEMBASE:
4954 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4956 case OP_STOREX_ALIGNED_MEMBASE_REG:
4957 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4959 case OP_STOREX_NTA_MEMBASE_REG:
4960 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4962 case OP_PREFETCH_MEMBASE:
4963 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4967 /*FIXME the peephole pass should have killed this*/
4968 if (ins->dreg != ins->sreg1)
4969 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4972 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4975 case OP_FCONV_TO_R8_X:
4976 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4977 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4980 case OP_XCONV_R8_TO_I4:
4981 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4982 switch (ins->backend.source_opcode) {
4983 case OP_FCONV_TO_I1:
4984 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4986 case OP_FCONV_TO_U1:
4987 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4989 case OP_FCONV_TO_I2:
4990 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4992 case OP_FCONV_TO_U2:
4993 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4999 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
5000 /*The +4 is to get a mov ?h, ?l over the same reg.*/
5001 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
5002 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
5003 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
5004 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5007 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
5008 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
5009 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5012 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
5013 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5016 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
5017 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5018 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5021 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
5022 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5023 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
5027 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
5030 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
5033 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
5036 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
5039 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
5042 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
5045 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
5048 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
5052 case OP_LIVERANGE_START: {
5053 if (cfg->verbose_level > 1)
5054 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5055 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5058 case OP_LIVERANGE_END: {
5059 if (cfg->verbose_level > 1)
5060 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5061 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5064 case OP_GC_SAFE_POINT: {
5065 const char *polling_func = NULL;
5066 int compare_val = 0;
5069 #if defined (USE_COOP_GC)
5070 polling_func = "mono_threads_state_poll";
5072 #elif defined(__native_client_codegen__) && defined(__native_client_gc__)
5073 polling_func = "mono_nacl_gc";
5074 compare_val = 0xFFFFFFFF;
5079 x86_test_membase_imm (code, ins->sreg1, 0, compare_val);
5080 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
5081 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
5082 x86_patch (br [0], code);
5086 case OP_GC_LIVENESS_DEF:
5087 case OP_GC_LIVENESS_USE:
5088 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5089 ins->backend.pc_offset = code - cfg->native_code;
5091 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5092 ins->backend.pc_offset = code - cfg->native_code;
5093 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5096 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
5099 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
5102 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
5103 g_assert_not_reached ();
5106 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
5107 #ifndef __native_client_codegen__
5108 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5109 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5110 g_assert_not_reached ();
5111 #endif /* __native_client_codegen__ */
5117 cfg->code_len = code - cfg->native_code;
5120 #endif /* DISABLE_JIT */
5123 mono_arch_register_lowlevel_calls (void)
5128 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5130 unsigned char *ip = ji->ip.i + code;
5133 case MONO_PATCH_INFO_IP:
5134 *((gconstpointer *)(ip)) = target;
5136 case MONO_PATCH_INFO_ABS:
5137 case MONO_PATCH_INFO_METHOD:
5138 case MONO_PATCH_INFO_METHOD_JUMP:
5139 case MONO_PATCH_INFO_INTERNAL_METHOD:
5140 case MONO_PATCH_INFO_BB:
5141 case MONO_PATCH_INFO_LABEL:
5142 case MONO_PATCH_INFO_RGCTX_FETCH:
5143 case MONO_PATCH_INFO_MONITOR_ENTER:
5144 case MONO_PATCH_INFO_MONITOR_ENTER_V4:
5145 case MONO_PATCH_INFO_MONITOR_EXIT:
5146 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5147 #if defined(__native_client_codegen__) && defined(__native_client__)
5148 if (nacl_is_code_address (code)) {
5149 /* For tail calls, code is patched after being installed */
5150 /* but not through the normal "patch callsite" method. */
5151 unsigned char buf[kNaClAlignment];
5152 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5153 unsigned char *_target = target;
5155 /* All patch targets modified in x86_patch */
5156 /* are IP relative. */
5157 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5158 memcpy (buf, aligned_code, kNaClAlignment);
5159 /* Patch a temp buffer of bundle size, */
5160 /* then install to actual location. */
5161 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5162 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5163 g_assert (ret == 0);
5166 x86_patch (ip, (unsigned char*)target);
5169 x86_patch (ip, (unsigned char*)target);
5172 case MONO_PATCH_INFO_NONE:
5174 case MONO_PATCH_INFO_R4:
5175 case MONO_PATCH_INFO_R8: {
5176 guint32 offset = mono_arch_get_patch_offset (ip);
5177 *((gconstpointer *)(ip + offset)) = target;
5181 guint32 offset = mono_arch_get_patch_offset (ip);
5182 #if !defined(__native_client__)
5183 *((gconstpointer *)(ip + offset)) = target;
5185 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5192 static G_GNUC_UNUSED void
5193 stack_unaligned (MonoMethod *m, gpointer caller)
5195 printf ("%s\n", mono_method_full_name (m, TRUE));
5196 g_assert_not_reached ();
5200 mono_arch_emit_prolog (MonoCompile *cfg)
5202 MonoMethod *method = cfg->method;
5204 MonoMethodSignature *sig;
5206 int alloc_size, pos, max_offset, i, cfa_offset;
5208 gboolean need_stack_frame;
5209 #ifdef __native_client_codegen__
5210 guint alignment_check;
5213 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5215 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5216 cfg->code_size += 512;
5218 #if defined(__default_codegen__)
5219 code = cfg->native_code = g_malloc (cfg->code_size);
5220 #elif defined(__native_client_codegen__)
5221 /* native_code_alloc is not 32-byte aligned, native_code is. */
5222 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5223 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5225 /* Align native_code to next nearest kNaclAlignment byte. */
5226 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5227 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5229 code = cfg->native_code;
5231 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5232 g_assert(alignment_check == 0);
5239 /* Check that the stack is aligned on osx */
5240 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5241 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5242 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5244 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5245 x86_push_membase (code, X86_ESP, 0);
5246 x86_push_imm (code, cfg->method);
5247 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5248 x86_call_reg (code, X86_EAX);
5249 x86_patch (br [0], code);
5253 /* Offset between RSP and the CFA */
5257 cfa_offset = sizeof (gpointer);
5258 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5259 // IP saved at CFA - 4
5260 /* There is no IP reg on x86 */
5261 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5262 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5264 need_stack_frame = needs_stack_frame (cfg);
5266 if (need_stack_frame) {
5267 x86_push_reg (code, X86_EBP);
5268 cfa_offset += sizeof (gpointer);
5269 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5270 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5271 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5272 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5273 /* These are handled automatically by the stack marking code */
5274 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5276 cfg->frame_reg = X86_ESP;
5279 cfg->stack_offset += cfg->param_area;
5280 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5282 alloc_size = cfg->stack_offset;
5285 if (!method->save_lmf) {
5286 if (cfg->used_int_regs & (1 << X86_EBX)) {
5287 x86_push_reg (code, X86_EBX);
5289 cfa_offset += sizeof (gpointer);
5290 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5291 /* These are handled automatically by the stack marking code */
5292 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5295 if (cfg->used_int_regs & (1 << X86_EDI)) {
5296 x86_push_reg (code, X86_EDI);
5298 cfa_offset += sizeof (gpointer);
5299 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5300 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5303 if (cfg->used_int_regs & (1 << X86_ESI)) {
5304 x86_push_reg (code, X86_ESI);
5306 cfa_offset += sizeof (gpointer);
5307 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5308 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5314 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5315 if (mono_do_x86_stack_align && need_stack_frame) {
5316 int tot = alloc_size + pos + 4; /* ret ip */
5317 if (need_stack_frame)
5319 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5321 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5322 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5323 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5327 cfg->arch.sp_fp_offset = alloc_size + pos;
5330 /* See mono_emit_stack_alloc */
5331 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5332 guint32 remaining_size = alloc_size;
5333 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5334 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5335 guint32 offset = code - cfg->native_code;
5336 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5337 while (required_code_size >= (cfg->code_size - offset))
5338 cfg->code_size *= 2;
5339 cfg->native_code = mono_realloc_native_code(cfg);
5340 code = cfg->native_code + offset;
5341 cfg->stat_code_reallocs++;
5343 while (remaining_size >= 0x1000) {
5344 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5345 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5346 remaining_size -= 0x1000;
5349 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5351 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5354 g_assert (need_stack_frame);
5357 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5358 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5359 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5362 #if DEBUG_STACK_ALIGNMENT
5363 /* check the stack is aligned */
5364 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5365 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5366 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5367 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5368 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5369 x86_breakpoint (code);
5373 /* compute max_offset in order to use short forward jumps */
5375 if (cfg->opt & MONO_OPT_BRANCH) {
5376 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5378 bb->max_offset = max_offset;
5380 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5382 /* max alignment for loops */
5383 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5384 max_offset += LOOP_ALIGNMENT;
5385 #ifdef __native_client_codegen__
5386 /* max alignment for native client */
5387 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5388 max_offset += kNaClAlignment;
5390 MONO_BB_FOR_EACH_INS (bb, ins) {
5391 if (ins->opcode == OP_LABEL)
5392 ins->inst_c1 = max_offset;
5393 #ifdef __native_client_codegen__
5394 switch (ins->opcode)
5406 case OP_VOIDCALL_REG:
5408 case OP_FCALL_MEMBASE:
5409 case OP_LCALL_MEMBASE:
5410 case OP_VCALL_MEMBASE:
5411 case OP_VCALL2_MEMBASE:
5412 case OP_VOIDCALL_MEMBASE:
5413 case OP_CALL_MEMBASE:
5414 max_offset += kNaClAlignment;
5417 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5420 #endif /* __native_client_codegen__ */
5421 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5426 /* store runtime generic context */
5427 if (cfg->rgctx_var) {
5428 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5430 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5433 if (method->save_lmf)
5434 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5436 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5437 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5442 if (cfg->arch.ss_tramp_var) {
5443 /* Initialize ss_tramp_var */
5444 ins = cfg->arch.ss_tramp_var;
5445 g_assert (ins->opcode == OP_REGOFFSET);
5447 g_assert (!cfg->compile_aot);
5448 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&ss_trampoline, 4);
5451 if (cfg->arch.bp_tramp_var) {
5452 /* Initialize bp_tramp_var */
5453 ins = cfg->arch.bp_tramp_var;
5454 g_assert (ins->opcode == OP_REGOFFSET);
5456 g_assert (!cfg->compile_aot);
5457 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&bp_trampoline, 4);
5461 /* load arguments allocated to register from the stack */
5462 sig = mono_method_signature (method);
5465 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5466 inst = cfg->args [pos];
5467 if (inst->opcode == OP_REGVAR) {
5468 g_assert (need_stack_frame);
5469 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5470 if (cfg->verbose_level > 2)
5471 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5476 cfg->code_len = code - cfg->native_code;
5478 g_assert (cfg->code_len < cfg->code_size);
5484 mono_arch_emit_epilog (MonoCompile *cfg)
5486 MonoMethod *method = cfg->method;
5487 MonoMethodSignature *sig = mono_method_signature (method);
5489 guint32 stack_to_pop;
5491 int max_epilog_size = 16;
5493 gboolean need_stack_frame = needs_stack_frame (cfg);
5495 if (cfg->method->save_lmf)
5496 max_epilog_size += 128;
5498 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5499 cfg->code_size *= 2;
5500 cfg->native_code = mono_realloc_native_code(cfg);
5501 cfg->stat_code_reallocs++;
5504 code = cfg->native_code + cfg->code_len;
5506 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5507 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5509 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5512 if (method->save_lmf) {
5513 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5515 gboolean supported = FALSE;
5517 if (cfg->compile_aot) {
5518 #if defined(MONO_HAVE_FAST_TLS)
5521 } else if (mono_get_jit_tls_offset () != -1) {
5525 /* check if we need to restore protection of the stack after a stack overflow */
5527 if (cfg->compile_aot) {
5528 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5530 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5532 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5535 /* we load the value in a separate instruction: this mechanism may be
5536 * used later as a safer way to do thread interruption
5538 x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5539 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5541 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5542 /* note that the call trampoline will preserve eax/edx */
5543 x86_call_reg (code, X86_ECX);
5544 x86_patch (patch, code);
5546 /* FIXME: maybe save the jit tls in the prolog */
5549 /* restore caller saved regs */
5550 if (cfg->used_int_regs & (1 << X86_EBX)) {
5551 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5554 if (cfg->used_int_regs & (1 << X86_EDI)) {
5555 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5557 if (cfg->used_int_regs & (1 << X86_ESI)) {
5558 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5561 /* EBP is restored by LEAVE */
5563 for (i = 0; i < X86_NREG; ++i) {
5564 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5570 g_assert (need_stack_frame);
5571 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5575 g_assert (need_stack_frame);
5576 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5579 if (cfg->used_int_regs & (1 << X86_ESI)) {
5580 x86_pop_reg (code, X86_ESI);
5582 if (cfg->used_int_regs & (1 << X86_EDI)) {
5583 x86_pop_reg (code, X86_EDI);
5585 if (cfg->used_int_regs & (1 << X86_EBX)) {
5586 x86_pop_reg (code, X86_EBX);
5590 /* Load returned vtypes into registers if needed */
5591 cinfo = get_call_info (cfg->mempool, sig);
5592 if (cinfo->ret.storage == ArgValuetypeInReg) {
5593 for (quad = 0; quad < 2; quad ++) {
5594 switch (cinfo->ret.pair_storage [quad]) {
5596 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5598 case ArgOnFloatFpStack:
5599 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5601 case ArgOnDoubleFpStack:
5602 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5607 g_assert_not_reached ();
5612 if (need_stack_frame)
5615 if (CALLCONV_IS_STDCALL (sig)) {
5616 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5618 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
5619 } else if (cinfo->callee_stack_pop)
5620 stack_to_pop = cinfo->callee_stack_pop;
5625 g_assert (need_stack_frame);
5626 x86_ret_imm (code, stack_to_pop);
5631 cfg->code_len = code - cfg->native_code;
5633 g_assert (cfg->code_len < cfg->code_size);
5637 mono_arch_emit_exceptions (MonoCompile *cfg)
5639 MonoJumpInfo *patch_info;
5642 MonoClass *exc_classes [16];
5643 guint8 *exc_throw_start [16], *exc_throw_end [16];
5647 /* Compute needed space */
5648 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5649 if (patch_info->type == MONO_PATCH_INFO_EXC)
5654 * make sure we have enough space for exceptions
5655 * 16 is the size of two push_imm instructions and a call
5657 if (cfg->compile_aot)
5658 code_size = exc_count * 32;
5660 code_size = exc_count * 16;
5662 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5663 cfg->code_size *= 2;
5664 cfg->native_code = mono_realloc_native_code(cfg);
5665 cfg->stat_code_reallocs++;
5668 code = cfg->native_code + cfg->code_len;
5671 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5672 switch (patch_info->type) {
5673 case MONO_PATCH_INFO_EXC: {
5674 MonoClass *exc_class;
5678 x86_patch (patch_info->ip.i + cfg->native_code, code);
5680 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5681 g_assert (exc_class);
5682 throw_ip = patch_info->ip.i;
5684 /* Find a throw sequence for the same exception class */
5685 for (i = 0; i < nthrows; ++i)
5686 if (exc_classes [i] == exc_class)
5689 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5690 x86_jump_code (code, exc_throw_start [i]);
5691 patch_info->type = MONO_PATCH_INFO_NONE;
5696 /* Compute size of code following the push <OFFSET> */
5697 #if defined(__default_codegen__)
5699 #elif defined(__native_client_codegen__)
5700 code = mono_nacl_align (code);
5701 size = kNaClAlignment;
5703 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5705 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5706 /* Use the shorter form */
5708 x86_push_imm (code, 0);
5712 x86_push_imm (code, 0xf0f0f0f0);
5717 exc_classes [nthrows] = exc_class;
5718 exc_throw_start [nthrows] = code;
5721 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5722 patch_info->data.name = "mono_arch_throw_corlib_exception";
5723 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5724 patch_info->ip.i = code - cfg->native_code;
5725 x86_call_code (code, 0);
5726 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5731 exc_throw_end [nthrows] = code;
5743 cfg->code_len = code - cfg->native_code;
5745 g_assert (cfg->code_len < cfg->code_size);
5749 mono_arch_flush_icache (guint8 *code, gint size)
5755 mono_arch_flush_register_windows (void)
5760 mono_arch_is_inst_imm (gint64 imm)
5766 mono_arch_finish_init (void)
5768 if (!g_getenv ("MONO_NO_TLS")) {
5769 #ifndef TARGET_WIN32
5771 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5778 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5782 // Linear handler, the bsearch head compare is shorter
5783 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5784 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5785 // x86_patch(ins,target)
5786 //[1 + 5] x86_jump_mem(inst,mem)
5789 #if defined(__default_codegen__)
5790 #define BR_SMALL_SIZE 2
5791 #define BR_LARGE_SIZE 5
5792 #elif defined(__native_client_codegen__)
5793 /* I suspect the size calculation below is actually incorrect. */
5794 /* TODO: fix the calculation that uses these sizes. */
5795 #define BR_SMALL_SIZE 16
5796 #define BR_LARGE_SIZE 12
5797 #endif /*__native_client_codegen__*/
5798 #define JUMP_IMM_SIZE 6
5799 #define ENABLE_WRONG_METHOD_CHECK 0
5803 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5805 int i, distance = 0;
5806 for (i = start; i < target; ++i)
5807 distance += imt_entries [i]->chunk_size;
5812 * LOCKING: called with the domain lock held
5815 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5816 gpointer fail_tramp)
5820 guint8 *code, *start;
5823 for (i = 0; i < count; ++i) {
5824 MonoIMTCheckItem *item = imt_entries [i];
5825 if (item->is_equals) {
5826 if (item->check_target_idx) {
5827 if (!item->compare_done)
5828 item->chunk_size += CMP_SIZE;
5829 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5832 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5834 item->chunk_size += JUMP_IMM_SIZE;
5835 #if ENABLE_WRONG_METHOD_CHECK
5836 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5841 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5842 imt_entries [item->check_target_idx]->compare_done = TRUE;
5844 size += item->chunk_size;
5846 #if defined(__native_client__) && defined(__native_client_codegen__)
5847 /* In Native Client, we don't re-use thunks, allocate from the */
5848 /* normal code manager paths. */
5849 size = NACL_BUNDLE_ALIGN_UP (size);
5850 code = mono_domain_code_reserve (domain, size);
5853 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5855 code = mono_domain_code_reserve (domain, size);
5859 unwind_ops = mono_arch_get_cie_program ();
5861 for (i = 0; i < count; ++i) {
5862 MonoIMTCheckItem *item = imt_entries [i];
5863 item->code_target = code;
5864 if (item->is_equals) {
5865 if (item->check_target_idx) {
5866 if (!item->compare_done)
5867 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5868 item->jmp_code = code;
5869 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5870 if (item->has_target_code)
5871 x86_jump_code (code, item->value.target_code);
5873 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5876 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5877 item->jmp_code = code;
5878 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5879 if (item->has_target_code)
5880 x86_jump_code (code, item->value.target_code);
5882 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5883 x86_patch (item->jmp_code, code);
5884 x86_jump_code (code, fail_tramp);
5885 item->jmp_code = NULL;
5887 /* enable the commented code to assert on wrong method */
5888 #if ENABLE_WRONG_METHOD_CHECK
5889 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5890 item->jmp_code = code;
5891 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5893 if (item->has_target_code)
5894 x86_jump_code (code, item->value.target_code);
5896 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5897 #if ENABLE_WRONG_METHOD_CHECK
5898 x86_patch (item->jmp_code, code);
5899 x86_breakpoint (code);
5900 item->jmp_code = NULL;
5905 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5906 item->jmp_code = code;
5907 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5908 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5910 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5913 /* patch the branches to get to the target items */
5914 for (i = 0; i < count; ++i) {
5915 MonoIMTCheckItem *item = imt_entries [i];
5916 if (item->jmp_code) {
5917 if (item->check_target_idx) {
5918 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5924 mono_stats.imt_thunks_size += code - start;
5925 g_assert (code - start <= size);
5929 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5930 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5934 if (mono_jit_map_is_enabled ()) {
5937 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5939 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5940 mono_emit_jit_tramp (start, code - start, buff);
5944 nacl_domain_code_validate (domain, &start, size, &code);
5945 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
5947 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
5953 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5955 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5959 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5961 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5965 mono_arch_get_cie_program (void)
5969 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5970 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5976 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5978 MonoInst *ins = NULL;
5981 if (cmethod->klass == mono_defaults.math_class) {
5982 if (strcmp (cmethod->name, "Sin") == 0) {
5984 } else if (strcmp (cmethod->name, "Cos") == 0) {
5986 } else if (strcmp (cmethod->name, "Tan") == 0) {
5988 } else if (strcmp (cmethod->name, "Atan") == 0) {
5990 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5992 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5994 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5998 if (opcode && fsig->param_count == 1) {
5999 MONO_INST_NEW (cfg, ins, opcode);
6000 ins->type = STACK_R8;
6001 ins->dreg = mono_alloc_freg (cfg);
6002 ins->sreg1 = args [0]->dreg;
6003 MONO_ADD_INS (cfg->cbb, ins);
6006 if (cfg->opt & MONO_OPT_CMOV) {
6009 if (strcmp (cmethod->name, "Min") == 0) {
6010 if (fsig->params [0]->type == MONO_TYPE_I4)
6012 } else if (strcmp (cmethod->name, "Max") == 0) {
6013 if (fsig->params [0]->type == MONO_TYPE_I4)
6017 if (opcode && fsig->param_count == 2) {
6018 MONO_INST_NEW (cfg, ins, opcode);
6019 ins->type = STACK_I4;
6020 ins->dreg = mono_alloc_ireg (cfg);
6021 ins->sreg1 = args [0]->dreg;
6022 ins->sreg2 = args [1]->dreg;
6023 MONO_ADD_INS (cfg->cbb, ins);
6028 /* OP_FREM is not IEEE compatible */
6029 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
6030 MONO_INST_NEW (cfg, ins, OP_FREM);
6031 ins->inst_i0 = args [0];
6032 ins->inst_i1 = args [1];
6041 mono_arch_print_tree (MonoInst *tree, int arity)
6047 mono_arch_get_patch_offset (guint8 *code)
6049 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
6051 else if (code [0] == 0xba)
6053 else if (code [0] == 0x68)
6056 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
6057 /* push <OFFSET>(<REG>) */
6059 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
6060 /* call *<OFFSET>(<REG>) */
6062 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
6065 else if ((code [0] == 0x58) && (code [1] == 0x05))
6066 /* pop %eax; add <OFFSET>, %eax */
6068 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6069 /* pop <REG>; add <OFFSET>, <REG> */
6071 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6072 /* mov <REG>, imm */
6075 g_assert_not_reached ();
6081 * mono_breakpoint_clean_code:
6083 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6084 * breakpoints in the original code, they are removed in the copy.
6086 * Returns TRUE if no sw breakpoint was present.
6089 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6092 * If method_start is non-NULL we need to perform bound checks, since we access memory
6093 * at code - offset we could go before the start of the method and end up in a different
6094 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6097 if (!method_start || code - offset >= method_start) {
6098 memcpy (buf, code - offset, size);
6100 int diff = code - method_start;
6101 memset (buf, 0, size);
6102 memcpy (buf + offset - diff, method_start, diff + size - offset);
6108 * mono_x86_get_this_arg_offset:
6110 * Return the offset of the stack location where this is passed during a virtual
6114 mono_x86_get_this_arg_offset (MonoMethodSignature *sig)
6120 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6122 guint32 esp = regs [X86_ESP];
6129 * The stack looks like:
6133 res = ((MonoObject**)esp) [0];
6137 #define MAX_ARCH_DELEGATE_PARAMS 10
6140 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
6142 guint8 *code, *start;
6143 int code_reserve = 64;
6146 unwind_ops = mono_arch_get_cie_program ();
6149 * The stack contains:
6155 start = code = mono_global_codeman_reserve (code_reserve);
6157 /* Replace the this argument with the target */
6158 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6159 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6160 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6161 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6163 g_assert ((code - start) < code_reserve);
6166 /* 8 for mov_reg and jump, plus 8 for each parameter */
6167 #ifdef __native_client_codegen__
6168 /* TODO: calculate this size correctly */
6169 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6171 code_reserve = 8 + (param_count * 8);
6172 #endif /* __native_client_codegen__ */
6174 * The stack contains:
6175 * <args in reverse order>
6180 * <args in reverse order>
6183 * without unbalancing the stack.
6184 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6185 * and leaving original spot of first arg as placeholder in stack so
6186 * when callee pops stack everything works.
6189 start = code = mono_global_codeman_reserve (code_reserve);
6191 /* store delegate for access to method_ptr */
6192 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6195 for (i = 0; i < param_count; ++i) {
6196 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6197 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6200 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6202 g_assert ((code - start) < code_reserve);
6205 nacl_global_codeman_validate (&start, code_reserve, &code);
6208 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
6210 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
6211 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
6215 if (mono_jit_map_is_enabled ()) {
6218 buff = (char*)"delegate_invoke_has_target";
6220 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6221 mono_emit_jit_tramp (start, code - start, buff);
6225 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6230 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
6233 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
6235 guint8 *code, *start;
6240 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
6244 * The stack contains:
6248 start = code = mono_global_codeman_reserve (size);
6250 unwind_ops = mono_arch_get_cie_program ();
6252 /* Replace the this argument with the target */
6253 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6254 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6255 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6258 /* Load the IMT reg */
6259 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
6262 /* Load the vtable */
6263 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
6264 x86_jump_membase (code, X86_EAX, offset);
6265 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6268 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
6270 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
6271 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
6272 g_free (tramp_name);
6279 mono_arch_get_delegate_invoke_impls (void)
6282 MonoTrampInfo *info;
6285 get_delegate_invoke_impl (&info, TRUE, 0);
6286 res = g_slist_prepend (res, info);
6288 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
6289 get_delegate_invoke_impl (&info, FALSE, i);
6290 res = g_slist_prepend (res, info);
6293 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
6294 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
6295 res = g_slist_prepend (res, info);
6297 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
6298 res = g_slist_prepend (res, info);
6305 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6307 guint8 *code, *start;
6309 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6312 /* FIXME: Support more cases */
6313 if (MONO_TYPE_ISSTRUCT (sig->ret))
6317 * The stack contains:
6323 static guint8* cached = NULL;
6327 if (mono_aot_only) {
6328 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6330 MonoTrampInfo *info;
6331 start = get_delegate_invoke_impl (&info, TRUE, 0);
6332 mono_tramp_info_register (info, NULL);
6335 mono_memory_barrier ();
6339 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6342 for (i = 0; i < sig->param_count; ++i)
6343 if (!mono_is_regsize_var (sig->params [i]))
6346 code = cache [sig->param_count];
6350 if (mono_aot_only) {
6351 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6352 start = mono_aot_get_trampoline (name);
6355 MonoTrampInfo *info;
6356 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
6357 mono_tramp_info_register (info, NULL);
6360 mono_memory_barrier ();
6362 cache [sig->param_count] = start;
6369 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
6371 MonoTrampInfo *info;
6374 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
6376 mono_tramp_info_register (info, NULL);
6381 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6384 case X86_EAX: return ctx->eax;
6385 case X86_EBX: return ctx->ebx;
6386 case X86_ECX: return ctx->ecx;
6387 case X86_EDX: return ctx->edx;
6388 case X86_ESP: return ctx->esp;
6389 case X86_EBP: return ctx->ebp;
6390 case X86_ESI: return ctx->esi;
6391 case X86_EDI: return ctx->edi;
6393 g_assert_not_reached ();
6399 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6427 g_assert_not_reached ();
6431 #ifdef MONO_ARCH_SIMD_INTRINSICS
6434 get_float_to_x_spill_area (MonoCompile *cfg)
6436 if (!cfg->fconv_to_r8_x_var) {
6437 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6438 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6440 return cfg->fconv_to_r8_x_var;
6444 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6447 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6450 int dreg, src_opcode;
6452 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6455 switch (src_opcode = ins->opcode) {
6456 case OP_FCONV_TO_I1:
6457 case OP_FCONV_TO_U1:
6458 case OP_FCONV_TO_I2:
6459 case OP_FCONV_TO_U2:
6460 case OP_FCONV_TO_I4:
6467 /* dreg is the IREG and sreg1 is the FREG */
6468 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6469 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6470 fconv->sreg1 = ins->sreg1;
6471 fconv->dreg = mono_alloc_ireg (cfg);
6472 fconv->type = STACK_VTYPE;
6473 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6475 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6479 ins->opcode = OP_XCONV_R8_TO_I4;
6481 ins->klass = mono_defaults.int32_class;
6482 ins->sreg1 = fconv->dreg;
6484 ins->type = STACK_I4;
6485 ins->backend.source_opcode = src_opcode;
6488 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6491 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6496 if (long_ins->opcode == OP_LNEG) {
6498 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6499 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6500 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6505 #ifdef MONO_ARCH_SIMD_INTRINSICS
6507 if (!(cfg->opt & MONO_OPT_SIMD))
6510 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6511 switch (long_ins->opcode) {
6513 vreg = long_ins->sreg1;
6515 if (long_ins->inst_c0) {
6516 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6517 ins->klass = long_ins->klass;
6518 ins->sreg1 = long_ins->sreg1;
6520 ins->type = STACK_VTYPE;
6521 ins->dreg = vreg = alloc_ireg (cfg);
6522 MONO_ADD_INS (cfg->cbb, ins);
6525 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6526 ins->klass = mono_defaults.int32_class;
6528 ins->type = STACK_I4;
6529 ins->dreg = long_ins->dreg + 1;
6530 MONO_ADD_INS (cfg->cbb, ins);
6532 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6533 ins->klass = long_ins->klass;
6534 ins->sreg1 = long_ins->sreg1;
6535 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6536 ins->type = STACK_VTYPE;
6537 ins->dreg = vreg = alloc_ireg (cfg);
6538 MONO_ADD_INS (cfg->cbb, ins);
6540 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6541 ins->klass = mono_defaults.int32_class;
6543 ins->type = STACK_I4;
6544 ins->dreg = long_ins->dreg + 2;
6545 MONO_ADD_INS (cfg->cbb, ins);
6547 long_ins->opcode = OP_NOP;
6549 case OP_INSERTX_I8_SLOW:
6550 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6551 ins->dreg = long_ins->dreg;
6552 ins->sreg1 = long_ins->dreg;
6553 ins->sreg2 = long_ins->sreg2 + 1;
6554 ins->inst_c0 = long_ins->inst_c0 * 2;
6555 MONO_ADD_INS (cfg->cbb, ins);
6557 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6558 ins->dreg = long_ins->dreg;
6559 ins->sreg1 = long_ins->dreg;
6560 ins->sreg2 = long_ins->sreg2 + 2;
6561 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6562 MONO_ADD_INS (cfg->cbb, ins);
6564 long_ins->opcode = OP_NOP;
6567 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6568 ins->dreg = long_ins->dreg;
6569 ins->sreg1 = long_ins->sreg1 + 1;
6570 ins->klass = long_ins->klass;
6571 ins->type = STACK_VTYPE;
6572 MONO_ADD_INS (cfg->cbb, ins);
6574 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6575 ins->dreg = long_ins->dreg;
6576 ins->sreg1 = long_ins->dreg;
6577 ins->sreg2 = long_ins->sreg1 + 2;
6579 ins->klass = long_ins->klass;
6580 ins->type = STACK_VTYPE;
6581 MONO_ADD_INS (cfg->cbb, ins);
6583 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6584 ins->dreg = long_ins->dreg;
6585 ins->sreg1 = long_ins->dreg;;
6586 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6587 ins->klass = long_ins->klass;
6588 ins->type = STACK_VTYPE;
6589 MONO_ADD_INS (cfg->cbb, ins);
6591 long_ins->opcode = OP_NOP;
6594 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6597 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6599 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6602 gpointer *sp, old_value;
6605 offset = clause->exvar_offset;
6608 bp = MONO_CONTEXT_GET_BP (ctx);
6609 sp = *(gpointer*)(bp + offset);
6612 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6621 * mono_aot_emit_load_got_addr:
6623 * Emit code to load the got address.
6624 * On x86, the result is placed into EBX.
6627 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6629 x86_call_imm (code, 0);
6631 * The patch needs to point to the pop, since the GOT offset needs
6632 * to be added to that address.
6635 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6637 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6638 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6639 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6645 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6648 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6650 g_assert_not_reached ();
6651 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6656 * mono_arch_emit_load_aotconst:
6658 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6659 * TARGET from the mscorlib GOT in full-aot code.
6660 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6664 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6666 /* Load the mscorlib got address */
6667 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6668 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6669 /* arch_emit_got_access () patches this */
6670 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6675 /* Can't put this into mini-x86.h */
6677 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6680 mono_arch_get_trampolines (gboolean aot)
6682 MonoTrampInfo *info;
6683 GSList *tramps = NULL;
6685 mono_x86_get_signal_exception_trampoline (&info, aot);
6687 tramps = g_slist_append (tramps, info);
6692 /* Soft Debug support */
6693 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6696 * mono_arch_set_breakpoint:
6698 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6699 * The location should contain code emitted by OP_SEQ_POINT.
6702 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6704 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6706 g_assert (code [0] == 0x90);
6707 x86_call_membase (code, X86_ECX, 0);
6711 * mono_arch_clear_breakpoint:
6713 * Clear the breakpoint at IP.
6716 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6718 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6721 for (i = 0; i < 2; ++i)
6726 * mono_arch_start_single_stepping:
6728 * Start single stepping.
6731 mono_arch_start_single_stepping (void)
6733 ss_trampoline = mini_get_single_step_trampoline ();
6737 * mono_arch_stop_single_stepping:
6739 * Stop single stepping.
6742 mono_arch_stop_single_stepping (void)
6744 ss_trampoline = NULL;
6748 * mono_arch_is_single_step_event:
6750 * Return whenever the machine state in SIGCTX corresponds to a single
6754 mono_arch_is_single_step_event (void *info, void *sigctx)
6756 /* We use soft breakpoints */
6761 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6763 /* We use soft breakpoints */
6767 #define BREAKPOINT_SIZE 2
6770 * mono_arch_skip_breakpoint:
6772 * See mini-amd64.c for docs.
6775 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6777 g_assert_not_reached ();
6781 * mono_arch_skip_single_step:
6783 * See mini-amd64.c for docs.
6786 mono_arch_skip_single_step (MonoContext *ctx)
6788 g_assert_not_reached ();
6792 * mono_arch_get_seq_point_info:
6794 * See mini-amd64.c for docs.
6797 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6804 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6806 ext->lmf.previous_lmf = (gsize)prev_lmf;
6807 /* Mark that this is a MonoLMFExt */
6808 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6809 ext->lmf.ebp = (gssize)ext;
6815 mono_arch_opcode_supported (int opcode)
6818 case OP_ATOMIC_ADD_I4:
6819 case OP_ATOMIC_EXCHANGE_I4:
6820 case OP_ATOMIC_CAS_I4:
6821 case OP_ATOMIC_LOAD_I1:
6822 case OP_ATOMIC_LOAD_I2:
6823 case OP_ATOMIC_LOAD_I4:
6824 case OP_ATOMIC_LOAD_U1:
6825 case OP_ATOMIC_LOAD_U2:
6826 case OP_ATOMIC_LOAD_U4:
6827 case OP_ATOMIC_LOAD_R4:
6828 case OP_ATOMIC_LOAD_R8:
6829 case OP_ATOMIC_STORE_I1:
6830 case OP_ATOMIC_STORE_I2:
6831 case OP_ATOMIC_STORE_I4:
6832 case OP_ATOMIC_STORE_U1:
6833 case OP_ATOMIC_STORE_U2:
6834 case OP_ATOMIC_STORE_U4:
6835 case OP_ATOMIC_STORE_R4:
6836 case OP_ATOMIC_STORE_R8:
6843 #if defined(ENABLE_GSHAREDVT)
6845 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6847 #endif /* !MONOTOUCH */