2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/abi-details.h>
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/metadata/gc-internals.h>
27 #include <mono/utils/mono-math.h>
28 #include <mono/utils/mono-counters.h>
29 #include <mono/utils/mono-mmap.h>
30 #include <mono/utils/mono-memory-model.h>
31 #include <mono/utils/mono-hwcap-x86.h>
32 #include <mono/utils/mono-threads.h>
42 static gboolean optimize_for_xen = TRUE;
44 #define optimize_for_xen 0
48 /* The single step trampoline */
49 static gpointer ss_trampoline;
51 /* The breakpoint trampoline */
52 static gpointer bp_trampoline;
54 /* This mutex protects architecture specific caches */
55 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
56 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
57 static mono_mutex_t mini_arch_mutex;
59 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
64 /* Under windows, the default pinvoke calling convention is stdcall */
65 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
67 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
70 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
72 #define OP_SEQ_POINT_BP_OFFSET 7
75 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
77 #ifdef __native_client_codegen__
79 /* Default alignment for Native Client is 32-byte. */
80 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
82 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
83 /* Check that alignment doesn't cross an alignment boundary. */
85 mono_arch_nacl_pad (guint8 *code, int pad)
87 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
89 if (pad == 0) return code;
90 /* assertion: alignment cannot cross a block boundary */
91 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
92 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
93 while (pad >= kMaxPadding) {
94 x86_padding (code, kMaxPadding);
97 if (pad != 0) x86_padding (code, pad);
102 mono_arch_nacl_skip_nops (guint8 *code)
104 x86_skip_nops (code);
108 #endif /* __native_client_codegen__ */
111 mono_arch_regname (int reg)
114 case X86_EAX: return "%eax";
115 case X86_EBX: return "%ebx";
116 case X86_ECX: return "%ecx";
117 case X86_EDX: return "%edx";
118 case X86_ESP: return "%esp";
119 case X86_EBP: return "%ebp";
120 case X86_EDI: return "%edi";
121 case X86_ESI: return "%esi";
127 mono_arch_fregname (int reg)
152 mono_arch_xregname (int reg)
177 mono_x86_patch (unsigned char* code, gpointer target)
179 x86_patch (code, (unsigned char*)target);
190 /* gsharedvt argument passed by addr */
202 /* Only if storage == ArgValuetypeInReg */
203 ArgStorage pair_storage [2];
212 gboolean need_stack_align;
213 guint32 stack_align_amount;
214 gboolean vtype_retaddr;
215 /* The index of the vret arg in the argument list */
218 /* Argument space popped by the callee */
219 int callee_stack_pop;
225 #define FLOAT_PARAM_REGS 0
227 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
229 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
234 switch (sig->call_convention) {
235 case MONO_CALL_THISCALL:
236 return thiscall_param_regs;
242 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
243 #define SMALL_STRUCTS_IN_REGS
244 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
248 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
250 ainfo->offset = *stack_size;
252 if (!param_regs || param_regs [*gr] == X86_NREG) {
253 ainfo->storage = ArgOnStack;
255 (*stack_size) += sizeof (gpointer);
258 ainfo->storage = ArgInIReg;
259 ainfo->reg = param_regs [*gr];
265 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
267 ainfo->offset = *stack_size;
269 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
271 ainfo->storage = ArgOnStack;
272 (*stack_size) += sizeof (gpointer) * 2;
277 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
279 ainfo->offset = *stack_size;
281 if (*gr >= FLOAT_PARAM_REGS) {
282 ainfo->storage = ArgOnStack;
283 (*stack_size) += is_double ? 8 : 4;
284 ainfo->nslots = is_double ? 2 : 1;
287 /* A double register */
289 ainfo->storage = ArgInDoubleSSEReg;
291 ainfo->storage = ArgInFloatSSEReg;
299 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
301 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
306 klass = mono_class_from_mono_type (type);
307 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
309 #ifdef SMALL_STRUCTS_IN_REGS
310 if (sig->pinvoke && is_return) {
311 MonoMarshalType *info;
314 * the exact rules are not very well documented, the code below seems to work with the
315 * code generated by gcc 3.3.3 -mno-cygwin.
317 info = mono_marshal_load_type_info (klass);
320 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
322 /* Special case structs with only a float member */
323 if (info->num_fields == 1) {
324 int ftype = mini_get_underlying_type (info->fields [0].field->type)->type;
325 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
326 ainfo->storage = ArgValuetypeInReg;
327 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
330 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
331 ainfo->storage = ArgValuetypeInReg;
332 ainfo->pair_storage [0] = ArgOnFloatFpStack;
336 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
337 ainfo->storage = ArgValuetypeInReg;
338 ainfo->pair_storage [0] = ArgInIReg;
339 ainfo->pair_regs [0] = return_regs [0];
340 if (info->native_size > 4) {
341 ainfo->pair_storage [1] = ArgInIReg;
342 ainfo->pair_regs [1] = return_regs [1];
349 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
350 g_assert (size <= 4);
351 ainfo->storage = ArgValuetypeInReg;
352 ainfo->reg = param_regs [*gr];
357 ainfo->offset = *stack_size;
358 ainfo->storage = ArgOnStack;
359 *stack_size += ALIGN_TO (size, sizeof (gpointer));
360 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
366 * Obtain information about a call according to the calling convention.
367 * For x86 ELF, see the "System V Application Binary Interface Intel386
368 * Architecture Processor Supplment, Fourth Edition" document for more
370 * For x86 win32, see ???.
373 get_call_info_internal (CallInfo *cinfo, MonoMethodSignature *sig)
375 guint32 i, gr, fr, pstart;
376 const guint32 *param_regs;
378 int n = sig->hasthis + sig->param_count;
379 guint32 stack_size = 0;
380 gboolean is_pinvoke = sig->pinvoke;
386 param_regs = callconv_param_regs(sig);
390 ret_type = mini_get_underlying_type (sig->ret);
391 switch (ret_type->type) {
401 case MONO_TYPE_FNPTR:
402 case MONO_TYPE_CLASS:
403 case MONO_TYPE_OBJECT:
404 case MONO_TYPE_SZARRAY:
405 case MONO_TYPE_ARRAY:
406 case MONO_TYPE_STRING:
407 cinfo->ret.storage = ArgInIReg;
408 cinfo->ret.reg = X86_EAX;
412 cinfo->ret.storage = ArgInIReg;
413 cinfo->ret.reg = X86_EAX;
414 cinfo->ret.is_pair = TRUE;
417 cinfo->ret.storage = ArgOnFloatFpStack;
420 cinfo->ret.storage = ArgOnDoubleFpStack;
422 case MONO_TYPE_GENERICINST:
423 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
424 cinfo->ret.storage = ArgInIReg;
425 cinfo->ret.reg = X86_EAX;
428 if (mini_is_gsharedvt_type (ret_type)) {
429 cinfo->ret.storage = ArgOnStack;
430 cinfo->vtype_retaddr = TRUE;
434 case MONO_TYPE_VALUETYPE:
435 case MONO_TYPE_TYPEDBYREF: {
436 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
438 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
439 if (cinfo->ret.storage == ArgOnStack) {
440 cinfo->vtype_retaddr = TRUE;
441 /* The caller passes the address where the value is stored */
447 g_assert (mini_is_gsharedvt_type (ret_type));
448 cinfo->ret.storage = ArgOnStack;
449 cinfo->vtype_retaddr = TRUE;
452 cinfo->ret.storage = ArgNone;
455 g_error ("Can't handle as return value 0x%x", ret_type->type);
461 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
462 * the first argument, allowing 'this' to be always passed in the first arg reg.
463 * Also do this if the first argument is a reference type, since virtual calls
464 * are sometimes made using calli without sig->hasthis set, like in the delegate
467 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
469 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
471 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
474 cinfo->vret_arg_offset = stack_size;
475 add_general (&gr, NULL, &stack_size, &cinfo->ret);
476 cinfo->vret_arg_index = 1;
480 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
482 if (cinfo->vtype_retaddr)
483 add_general (&gr, NULL, &stack_size, &cinfo->ret);
486 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
487 fr = FLOAT_PARAM_REGS;
489 /* Emit the signature cookie just before the implicit arguments */
490 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
493 for (i = pstart; i < sig->param_count; ++i) {
494 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
497 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
498 /* We allways pass the sig cookie on the stack for simplicity */
500 * Prevent implicit arguments + the sig cookie from being passed
503 fr = FLOAT_PARAM_REGS;
505 /* Emit the signature cookie just before the implicit arguments */
506 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
509 if (sig->params [i]->byref) {
510 add_general (&gr, param_regs, &stack_size, ainfo);
513 ptype = mini_get_underlying_type (sig->params [i]);
514 switch (ptype->type) {
517 add_general (&gr, param_regs, &stack_size, ainfo);
521 add_general (&gr, param_regs, &stack_size, ainfo);
525 add_general (&gr, param_regs, &stack_size, ainfo);
530 case MONO_TYPE_FNPTR:
531 case MONO_TYPE_CLASS:
532 case MONO_TYPE_OBJECT:
533 case MONO_TYPE_STRING:
534 case MONO_TYPE_SZARRAY:
535 case MONO_TYPE_ARRAY:
536 add_general (&gr, param_regs, &stack_size, ainfo);
538 case MONO_TYPE_GENERICINST:
539 if (!mono_type_generic_inst_is_valuetype (ptype)) {
540 add_general (&gr, param_regs, &stack_size, ainfo);
543 if (mini_is_gsharedvt_type (ptype)) {
544 /* gsharedvt arguments are passed by ref */
545 add_general (&gr, param_regs, &stack_size, ainfo);
546 g_assert (ainfo->storage == ArgOnStack);
547 ainfo->storage = ArgGSharedVt;
551 case MONO_TYPE_VALUETYPE:
552 case MONO_TYPE_TYPEDBYREF:
553 add_valuetype (sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
557 add_general_pair (&gr, param_regs, &stack_size, ainfo);
560 add_float (&fr, &stack_size, ainfo, FALSE);
563 add_float (&fr, &stack_size, ainfo, TRUE);
567 /* gsharedvt arguments are passed by ref */
568 g_assert (mini_is_gsharedvt_type (ptype));
569 add_general (&gr, param_regs, &stack_size, ainfo);
570 g_assert (ainfo->storage == ArgOnStack);
571 ainfo->storage = ArgGSharedVt;
574 g_error ("unexpected type 0x%x", ptype->type);
575 g_assert_not_reached ();
579 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
580 fr = FLOAT_PARAM_REGS;
582 /* Emit the signature cookie just before the implicit arguments */
583 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
586 if (cinfo->vtype_retaddr) {
587 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
588 cinfo->callee_stack_pop = 4;
589 } else if (CALLCONV_IS_STDCALL (sig) && sig->pinvoke) {
590 /* Have to compensate for the stack space popped by the native callee */
591 cinfo->callee_stack_pop = stack_size;
594 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
595 cinfo->need_stack_align = TRUE;
596 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
597 stack_size += cinfo->stack_align_amount;
600 cinfo->stack_usage = stack_size;
601 cinfo->reg_usage = gr;
602 cinfo->freg_usage = fr;
607 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
609 int n = sig->hasthis + sig->param_count;
613 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
615 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
617 return get_call_info_internal (cinfo, sig);
621 * mono_arch_get_argument_info:
622 * @csig: a method signature
623 * @param_count: the number of parameters to consider
624 * @arg_info: an array to store the result infos
626 * Gathers information on parameters such as size, alignment and
627 * padding. arg_info should be large enought to hold param_count + 1 entries.
629 * Returns the size of the argument area on the stack.
630 * This should be signal safe, since it is called from
631 * mono_arch_unwind_frame ().
632 * FIXME: The metadata calls might not be signal safe.
635 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
637 int len, k, args_size = 0;
643 /* Avoid g_malloc as it is not signal safe */
644 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
645 cinfo = (CallInfo*)g_newa (guint8*, len);
646 memset (cinfo, 0, len);
648 cinfo = get_call_info_internal (cinfo, csig);
650 arg_info [0].offset = offset;
652 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
653 args_size += sizeof (gpointer);
658 args_size += sizeof (gpointer);
662 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
663 /* Emitted after this */
664 args_size += sizeof (gpointer);
668 arg_info [0].size = args_size;
670 for (k = 0; k < param_count; k++) {
671 size = mini_type_stack_size_full (csig->params [k], &align, csig->pinvoke);
673 /* ignore alignment for now */
676 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
677 arg_info [k].pad = pad;
679 arg_info [k + 1].pad = 0;
680 arg_info [k + 1].size = size;
682 arg_info [k + 1].offset = offset;
685 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
686 /* Emitted after the first arg */
687 args_size += sizeof (gpointer);
692 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
693 align = MONO_ARCH_FRAME_ALIGNMENT;
696 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
697 arg_info [k].pad = pad;
703 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
705 MonoType *callee_ret;
709 if (cfg->compile_aot && !cfg->full_aot)
710 /* OP_TAILCALL doesn't work with AOT */
713 c1 = get_call_info (NULL, caller_sig);
714 c2 = get_call_info (NULL, callee_sig);
716 * Tail calls with more callee stack usage than the caller cannot be supported, since
717 * the extra stack space would be left on the stack after the tail call.
719 res = c1->stack_usage >= c2->stack_usage;
720 callee_ret = mini_get_underlying_type (callee_sig->ret);
721 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
722 /* An address on the callee's stack is passed as the first argument */
732 * Initialize the cpu to execute managed code.
735 mono_arch_cpu_init (void)
737 /* spec compliance requires running with double precision */
741 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
742 fpcw &= ~X86_FPCW_PRECC_MASK;
743 fpcw |= X86_FPCW_PREC_DOUBLE;
744 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
745 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
747 _control87 (_PC_53, MCW_PC);
752 * Initialize architecture specific code.
755 mono_arch_init (void)
757 mono_os_mutex_init_recursive (&mini_arch_mutex);
760 bp_trampoline = mini_get_breakpoint_trampoline ();
762 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
763 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
764 #if defined(ENABLE_GSHAREDVT)
765 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
770 * Cleanup architecture specific code.
773 mono_arch_cleanup (void)
775 mono_os_mutex_destroy (&mini_arch_mutex);
779 * This function returns the optimizations supported on this cpu.
782 mono_arch_cpu_optimizations (guint32 *exclude_mask)
784 #if !defined(__native_client__)
789 if (mono_hwcap_x86_has_cmov) {
790 opts |= MONO_OPT_CMOV;
792 if (mono_hwcap_x86_has_fcmov)
793 opts |= MONO_OPT_FCMOV;
795 *exclude_mask |= MONO_OPT_FCMOV;
797 *exclude_mask |= MONO_OPT_CMOV;
800 if (mono_hwcap_x86_has_sse2)
801 opts |= MONO_OPT_SSE2;
803 *exclude_mask |= MONO_OPT_SSE2;
805 #ifdef MONO_ARCH_SIMD_INTRINSICS
806 /*SIMD intrinsics require at least SSE2.*/
807 if (!mono_hwcap_x86_has_sse2)
808 *exclude_mask |= MONO_OPT_SIMD;
813 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
818 * This function test for all SSE functions supported.
820 * Returns a bitmask corresponding to all supported versions.
824 mono_arch_cpu_enumerate_simd_versions (void)
826 guint32 sse_opts = 0;
828 if (mono_hwcap_x86_has_sse1)
829 sse_opts |= SIMD_VERSION_SSE1;
831 if (mono_hwcap_x86_has_sse2)
832 sse_opts |= SIMD_VERSION_SSE2;
834 if (mono_hwcap_x86_has_sse3)
835 sse_opts |= SIMD_VERSION_SSE3;
837 if (mono_hwcap_x86_has_ssse3)
838 sse_opts |= SIMD_VERSION_SSSE3;
840 if (mono_hwcap_x86_has_sse41)
841 sse_opts |= SIMD_VERSION_SSE41;
843 if (mono_hwcap_x86_has_sse42)
844 sse_opts |= SIMD_VERSION_SSE42;
846 if (mono_hwcap_x86_has_sse4a)
847 sse_opts |= SIMD_VERSION_SSE4a;
853 * Determine whenever the trap whose info is in SIGINFO is caused by
857 mono_arch_is_int_overflow (void *sigctx, void *info)
862 mono_sigctx_to_monoctx (sigctx, &ctx);
864 ip = (guint8*)ctx.eip;
866 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
870 switch (x86_modrm_rm (ip [1])) {
890 g_assert_not_reached ();
902 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
907 for (i = 0; i < cfg->num_varinfo; i++) {
908 MonoInst *ins = cfg->varinfo [i];
909 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
912 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
915 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
916 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
919 /* we dont allocate I1 to registers because there is no simply way to sign extend
920 * 8bit quantities in caller saved registers on x86 */
921 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
922 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
923 g_assert (i == vmv->idx);
924 vars = g_list_prepend (vars, vmv);
928 vars = mono_varlist_sort (cfg, vars, 0);
934 mono_arch_get_global_int_regs (MonoCompile *cfg)
938 /* we can use 3 registers for global allocation */
939 regs = g_list_prepend (regs, (gpointer)X86_EBX);
940 regs = g_list_prepend (regs, (gpointer)X86_ESI);
941 regs = g_list_prepend (regs, (gpointer)X86_EDI);
947 * mono_arch_regalloc_cost:
949 * Return the cost, in number of memory references, of the action of
950 * allocating the variable VMV into a register during global register
954 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
956 MonoInst *ins = cfg->varinfo [vmv->idx];
958 if (cfg->method->save_lmf)
959 /* The register is already saved */
960 return (ins->opcode == OP_ARG) ? 1 : 0;
962 /* push+pop+possible load if it is an argument */
963 return (ins->opcode == OP_ARG) ? 3 : 2;
967 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
969 static int inited = FALSE;
970 static int count = 0;
972 if (cfg->arch.need_stack_frame_inited) {
973 g_assert (cfg->arch.need_stack_frame == flag);
977 cfg->arch.need_stack_frame = flag;
978 cfg->arch.need_stack_frame_inited = TRUE;
984 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
989 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
993 needs_stack_frame (MonoCompile *cfg)
995 MonoMethodSignature *sig;
996 MonoMethodHeader *header;
997 gboolean result = FALSE;
999 #if defined(__APPLE__)
1000 /*OSX requires stack frame code to have the correct alignment. */
1004 if (cfg->arch.need_stack_frame_inited)
1005 return cfg->arch.need_stack_frame;
1007 header = cfg->header;
1008 sig = mono_method_signature (cfg->method);
1010 if (cfg->disable_omit_fp)
1012 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1014 else if (cfg->method->save_lmf)
1016 else if (cfg->stack_offset)
1018 else if (cfg->param_area)
1020 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1022 else if (header->num_clauses)
1024 else if (sig->param_count + sig->hasthis)
1026 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1028 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1029 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1032 set_needs_stack_frame (cfg, result);
1034 return cfg->arch.need_stack_frame;
1038 * Set var information according to the calling convention. X86 version.
1039 * The locals var stuff should most likely be split in another method.
1042 mono_arch_allocate_vars (MonoCompile *cfg)
1044 MonoMethodSignature *sig;
1045 MonoMethodHeader *header;
1047 guint32 locals_stack_size, locals_stack_align;
1052 header = cfg->header;
1053 sig = mono_method_signature (cfg->method);
1055 cinfo = get_call_info (cfg->mempool, sig);
1057 cfg->frame_reg = X86_EBP;
1060 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1061 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1062 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1065 /* Reserve space to save LMF and caller saved registers */
1067 if (cfg->method->save_lmf) {
1068 /* The LMF var is allocated normally */
1070 if (cfg->used_int_regs & (1 << X86_EBX)) {
1074 if (cfg->used_int_regs & (1 << X86_EDI)) {
1078 if (cfg->used_int_regs & (1 << X86_ESI)) {
1083 switch (cinfo->ret.storage) {
1084 case ArgValuetypeInReg:
1085 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1087 cfg->ret->opcode = OP_REGOFFSET;
1088 cfg->ret->inst_basereg = X86_EBP;
1089 cfg->ret->inst_offset = - offset;
1095 /* Allocate locals */
1096 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1097 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1098 char *mname = mono_method_full_name (cfg->method, TRUE);
1099 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1103 if (locals_stack_align) {
1104 int prev_offset = offset;
1106 offset += (locals_stack_align - 1);
1107 offset &= ~(locals_stack_align - 1);
1109 while (prev_offset < offset) {
1111 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1114 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1115 cfg->locals_max_stack_offset = - offset;
1117 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1118 * have locals larger than 8 bytes we need to make sure that
1119 * they have the appropriate offset.
1121 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1122 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1123 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1124 if (offsets [i] != -1) {
1125 MonoInst *inst = cfg->varinfo [i];
1126 inst->opcode = OP_REGOFFSET;
1127 inst->inst_basereg = X86_EBP;
1128 inst->inst_offset = - (offset + offsets [i]);
1129 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1132 offset += locals_stack_size;
1136 * Allocate arguments+return value
1139 switch (cinfo->ret.storage) {
1141 if (cfg->vret_addr) {
1143 * In the new IR, the cfg->vret_addr variable represents the
1144 * vtype return value.
1146 cfg->vret_addr->opcode = OP_REGOFFSET;
1147 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1148 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1149 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1150 printf ("vret_addr =");
1151 mono_print_ins (cfg->vret_addr);
1154 cfg->ret->opcode = OP_REGOFFSET;
1155 cfg->ret->inst_basereg = X86_EBP;
1156 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1159 case ArgValuetypeInReg:
1162 cfg->ret->opcode = OP_REGVAR;
1163 cfg->ret->inst_c0 = cinfo->ret.reg;
1164 cfg->ret->dreg = cinfo->ret.reg;
1167 case ArgOnFloatFpStack:
1168 case ArgOnDoubleFpStack:
1171 g_assert_not_reached ();
1174 if (sig->call_convention == MONO_CALL_VARARG) {
1175 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1176 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1179 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1180 ArgInfo *ainfo = &cinfo->args [i];
1181 inst = cfg->args [i];
1182 if (inst->opcode != OP_REGVAR) {
1183 inst->opcode = OP_REGOFFSET;
1184 inst->inst_basereg = X86_EBP;
1186 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1189 cfg->stack_offset = offset;
1193 mono_arch_create_vars (MonoCompile *cfg)
1196 MonoMethodSignature *sig;
1199 sig = mono_method_signature (cfg->method);
1201 cinfo = get_call_info (cfg->mempool, sig);
1202 sig_ret = mini_get_underlying_type (sig->ret);
1204 if (cinfo->ret.storage == ArgValuetypeInReg)
1205 cfg->ret_var_is_local = TRUE;
1206 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (sig_ret))) {
1207 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1210 if (cfg->gen_sdb_seq_points) {
1213 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1214 ins->flags |= MONO_INST_VOLATILE;
1215 cfg->arch.ss_tramp_var = ins;
1217 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1218 ins->flags |= MONO_INST_VOLATILE;
1219 cfg->arch.bp_tramp_var = ins;
1222 if (cfg->method->save_lmf) {
1223 cfg->create_lmf_var = TRUE;
1226 cfg->lmf_ir_mono_lmf = TRUE;
1230 cfg->arch_eh_jit_info = 1;
1234 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1235 * so we try to do it just once when we have multiple fp arguments in a row.
1236 * We don't use this mechanism generally because for int arguments the generated code
1237 * is slightly bigger and new generation cpus optimize away the dependency chains
1238 * created by push instructions on the esp value.
1239 * fp_arg_setup is the first argument in the execution sequence where the esp register
1242 static G_GNUC_UNUSED int
1243 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1248 for (; start_arg < sig->param_count; ++start_arg) {
1249 t = mini_get_underlying_type (sig->params [start_arg]);
1250 if (!t->byref && t->type == MONO_TYPE_R8) {
1251 fp_space += sizeof (double);
1252 *fp_arg_setup = start_arg;
1261 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1263 MonoMethodSignature *tmp_sig;
1267 * mono_ArgIterator_Setup assumes the signature cookie is
1268 * passed first and all the arguments which were before it are
1269 * passed on the stack after the signature. So compensate by
1270 * passing a different signature.
1272 tmp_sig = mono_metadata_signature_dup (call->signature);
1273 tmp_sig->param_count -= call->signature->sentinelpos;
1274 tmp_sig->sentinelpos = 0;
1275 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1277 if (cfg->compile_aot) {
1278 sig_reg = mono_alloc_ireg (cfg);
1279 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1280 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1282 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1288 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1293 LLVMCallInfo *linfo;
1294 MonoType *t, *sig_ret;
1296 n = sig->param_count + sig->hasthis;
1298 cinfo = get_call_info (cfg->mempool, sig);
1301 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1304 * LLVM always uses the native ABI while we use our own ABI, the
1305 * only difference is the handling of vtypes:
1306 * - we only pass/receive them in registers in some cases, and only
1307 * in 1 or 2 integer registers.
1309 if (cinfo->ret.storage == ArgValuetypeInReg) {
1311 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1312 cfg->disable_llvm = TRUE;
1316 cfg->exception_message = g_strdup ("vtype ret in call");
1317 cfg->disable_llvm = TRUE;
1319 linfo->ret.storage = LLVMArgVtypeInReg;
1320 for (j = 0; j < 2; ++j)
1321 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1325 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage == ArgInIReg) {
1326 /* Vtype returned using a hidden argument */
1327 linfo->ret.storage = LLVMArgVtypeRetAddr;
1328 linfo->vret_arg_index = cinfo->vret_arg_index;
1331 if (mini_type_is_vtype (sig_ret) && cinfo->ret.storage != ArgInIReg) {
1333 cfg->exception_message = g_strdup ("vtype ret in call");
1334 cfg->disable_llvm = TRUE;
1337 for (i = 0; i < n; ++i) {
1338 ainfo = cinfo->args + i;
1340 if (i >= sig->hasthis)
1341 t = sig->params [i - sig->hasthis];
1343 t = &mono_defaults.int_class->byval_arg;
1345 linfo->args [i].storage = LLVMArgNone;
1347 switch (ainfo->storage) {
1349 linfo->args [i].storage = LLVMArgNormal;
1351 case ArgInDoubleSSEReg:
1352 case ArgInFloatSSEReg:
1353 linfo->args [i].storage = LLVMArgNormal;
1356 if (mini_type_is_vtype (t)) {
1357 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1358 /* LLVM seems to allocate argument space for empty structures too */
1359 linfo->args [i].storage = LLVMArgNone;
1361 linfo->args [i].storage = LLVMArgVtypeByVal;
1363 linfo->args [i].storage = LLVMArgNormal;
1366 case ArgValuetypeInReg:
1368 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1369 cfg->disable_llvm = TRUE;
1373 cfg->exception_message = g_strdup ("vtype arg");
1374 cfg->disable_llvm = TRUE;
1376 linfo->args [i].storage = LLVMArgVtypeInReg;
1377 for (j = 0; j < 2; ++j)
1378 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1382 linfo->args [i].storage = LLVMArgGSharedVt;
1385 cfg->exception_message = g_strdup ("ainfo->storage");
1386 cfg->disable_llvm = TRUE;
1396 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1398 if (cfg->compute_gc_maps) {
1401 /* Needs checking if the feature will be enabled again */
1402 g_assert_not_reached ();
1404 /* On x86, the offsets are from the sp value before the start of the call sequence */
1406 t = &mono_defaults.int_class->byval_arg;
1407 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1412 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1416 MonoMethodSignature *sig;
1419 int sentinelpos = 0, sp_offset = 0;
1421 sig = call->signature;
1422 n = sig->param_count + sig->hasthis;
1423 sig_ret = mini_get_underlying_type (sig->ret);
1425 cinfo = get_call_info (cfg->mempool, sig);
1426 call->call_info = cinfo;
1428 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1429 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1431 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1432 if (cinfo->ret.storage == ArgValuetypeInReg) {
1434 * Tell the JIT to use a more efficient calling convention: call using
1435 * OP_CALL, compute the result location after the call, and save the
1438 call->vret_in_reg = TRUE;
1439 #if defined(__APPLE__)
1440 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1441 call->vret_in_reg_fp = TRUE;
1444 NULLIFY_INS (call->vret_var);
1448 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1450 /* Handle the case where there are no implicit arguments */
1451 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1452 emit_sig_cookie (cfg, call, cinfo);
1453 sp_offset = cinfo->sig_cookie.offset;
1454 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1457 /* Arguments are pushed in the reverse order */
1458 for (i = n - 1; i >= 0; i --) {
1459 ArgInfo *ainfo = cinfo->args + i;
1460 MonoType *orig_type, *t;
1463 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1466 /* Push the vret arg before the first argument */
1467 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1468 vtarg->type = STACK_MP;
1469 vtarg->inst_destbasereg = X86_ESP;
1470 vtarg->sreg1 = call->vret_var->dreg;
1471 vtarg->inst_offset = cinfo->ret.offset;
1472 MONO_ADD_INS (cfg->cbb, vtarg);
1473 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1476 if (i >= sig->hasthis)
1477 t = sig->params [i - sig->hasthis];
1479 t = &mono_defaults.int_class->byval_arg;
1481 t = mini_get_underlying_type (t);
1483 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1485 in = call->args [i];
1486 arg->cil_code = in->cil_code;
1487 arg->sreg1 = in->dreg;
1488 arg->type = in->type;
1490 g_assert (in->dreg != -1);
1492 if (ainfo->storage == ArgGSharedVt) {
1493 arg->opcode = OP_OUTARG_VT;
1494 arg->sreg1 = in->dreg;
1495 arg->klass = in->klass;
1496 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1497 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1499 MONO_ADD_INS (cfg->cbb, arg);
1500 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1504 g_assert (in->klass);
1506 if (t->type == MONO_TYPE_TYPEDBYREF) {
1507 size = sizeof (MonoTypedRef);
1508 align = sizeof (gpointer);
1511 size = mini_type_stack_size_full (&in->klass->byval_arg, &align, sig->pinvoke);
1515 arg->opcode = OP_OUTARG_VT;
1516 arg->sreg1 = in->dreg;
1517 arg->klass = in->klass;
1518 arg->backend.size = size;
1519 arg->inst_p0 = call;
1520 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1521 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1523 MONO_ADD_INS (cfg->cbb, arg);
1524 if (ainfo->storage != ArgValuetypeInReg) {
1525 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1529 switch (ainfo->storage) {
1532 if (t->type == MONO_TYPE_R4) {
1533 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1535 } else if (t->type == MONO_TYPE_R8) {
1536 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1538 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1539 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, MONO_LVREG_MS (in->dreg));
1540 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, MONO_LVREG_LS (in->dreg));
1543 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1547 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1552 arg->opcode = OP_MOVE;
1553 arg->dreg = ainfo->reg;
1554 MONO_ADD_INS (cfg->cbb, arg);
1558 g_assert_not_reached ();
1561 if (cfg->compute_gc_maps) {
1563 /* FIXME: The == STACK_OBJ check might be fragile ? */
1564 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1566 if (call->need_unbox_trampoline)
1567 /* The unbox trampoline transforms this into a managed pointer */
1568 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.int_class->this_arg);
1570 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.object_class->byval_arg);
1572 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1576 for (j = 0; j < argsize; j += 4)
1577 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1582 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1583 /* Emit the signature cookie just before the implicit arguments */
1584 emit_sig_cookie (cfg, call, cinfo);
1585 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1589 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1592 if (cinfo->ret.storage == ArgValuetypeInReg) {
1595 else if (cinfo->ret.storage == ArgInIReg) {
1597 /* The return address is passed in a register */
1598 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1599 vtarg->sreg1 = call->inst.dreg;
1600 vtarg->dreg = mono_alloc_ireg (cfg);
1601 MONO_ADD_INS (cfg->cbb, vtarg);
1603 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1604 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1605 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1606 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1610 call->stack_usage = cinfo->stack_usage;
1611 call->stack_align_amount = cinfo->stack_align_amount;
1615 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1617 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1618 ArgInfo *ainfo = ins->inst_p1;
1619 int size = ins->backend.size;
1621 if (ainfo->storage == ArgValuetypeInReg) {
1622 int dreg = mono_alloc_ireg (cfg);
1625 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1628 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1631 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1635 g_assert_not_reached ();
1637 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1640 if (cfg->gsharedvt && mini_is_gsharedvt_klass (ins->klass)) {
1642 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1643 } else if (size <= 4) {
1644 int dreg = mono_alloc_ireg (cfg);
1645 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1646 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1647 } else if (size <= 20) {
1648 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1650 // FIXME: Code growth
1651 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1657 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1659 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
1662 if (ret->type == MONO_TYPE_R4) {
1663 if (COMPILE_LLVM (cfg))
1664 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1667 } else if (ret->type == MONO_TYPE_R8) {
1668 if (COMPILE_LLVM (cfg))
1669 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1672 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1673 if (COMPILE_LLVM (cfg))
1674 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1676 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, MONO_LVREG_LS (val->dreg));
1677 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, MONO_LVREG_MS (val->dreg));
1683 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1687 * Allow tracing to work with this interface (with an optional argument)
1690 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1694 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1695 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1697 /* if some args are passed in registers, we need to save them here */
1698 x86_push_reg (code, X86_EBP);
1700 if (cfg->compile_aot) {
1701 x86_push_imm (code, cfg->method);
1702 x86_mov_reg_imm (code, X86_EAX, func);
1703 x86_call_reg (code, X86_EAX);
1705 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1706 x86_push_imm (code, cfg->method);
1707 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1708 x86_call_code (code, 0);
1710 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1724 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1727 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1728 MonoMethod *method = cfg->method;
1729 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
1731 switch (ret_type->type) {
1732 case MONO_TYPE_VOID:
1733 /* special case string .ctor icall */
1734 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1735 save_mode = SAVE_EAX;
1736 stack_usage = enable_arguments ? 8 : 4;
1738 save_mode = SAVE_NONE;
1742 save_mode = SAVE_EAX_EDX;
1743 stack_usage = enable_arguments ? 16 : 8;
1747 save_mode = SAVE_FP;
1748 stack_usage = enable_arguments ? 16 : 8;
1750 case MONO_TYPE_GENERICINST:
1751 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1752 save_mode = SAVE_EAX;
1753 stack_usage = enable_arguments ? 8 : 4;
1757 case MONO_TYPE_VALUETYPE:
1758 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1759 save_mode = SAVE_STRUCT;
1760 stack_usage = enable_arguments ? 4 : 0;
1763 save_mode = SAVE_EAX;
1764 stack_usage = enable_arguments ? 8 : 4;
1768 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1770 switch (save_mode) {
1772 x86_push_reg (code, X86_EDX);
1773 x86_push_reg (code, X86_EAX);
1774 if (enable_arguments) {
1775 x86_push_reg (code, X86_EDX);
1776 x86_push_reg (code, X86_EAX);
1781 x86_push_reg (code, X86_EAX);
1782 if (enable_arguments) {
1783 x86_push_reg (code, X86_EAX);
1788 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1789 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1790 if (enable_arguments) {
1791 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1792 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1797 if (enable_arguments) {
1798 x86_push_membase (code, X86_EBP, 8);
1807 if (cfg->compile_aot) {
1808 x86_push_imm (code, method);
1809 x86_mov_reg_imm (code, X86_EAX, func);
1810 x86_call_reg (code, X86_EAX);
1812 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1813 x86_push_imm (code, method);
1814 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1815 x86_call_code (code, 0);
1818 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1820 switch (save_mode) {
1822 x86_pop_reg (code, X86_EAX);
1823 x86_pop_reg (code, X86_EDX);
1826 x86_pop_reg (code, X86_EAX);
1829 x86_fld_membase (code, X86_ESP, 0, TRUE);
1830 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1837 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1842 #define EMIT_COND_BRANCH(ins,cond,sign) \
1843 if (ins->inst_true_bb->native_offset) { \
1844 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1846 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1847 if ((cfg->opt & MONO_OPT_BRANCH) && \
1848 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1849 x86_branch8 (code, cond, 0, sign); \
1851 x86_branch32 (code, cond, 0, sign); \
1855 * Emit an exception if condition is fail and
1856 * if possible do a directly branch to target
1858 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1860 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1861 if (tins == NULL) { \
1862 mono_add_patch_info (cfg, code - cfg->native_code, \
1863 MONO_PATCH_INFO_EXC, exc_name); \
1864 x86_branch32 (code, cond, 0, signed); \
1866 EMIT_COND_BRANCH (tins, cond, signed); \
1870 #define EMIT_FPCOMPARE(code) do { \
1871 x86_fcompp (code); \
1872 x86_fnstsw (code); \
1877 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1879 gboolean needs_paddings = TRUE;
1881 MonoJumpInfo *jinfo = NULL;
1883 if (cfg->abs_patches) {
1884 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1885 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1886 needs_paddings = FALSE;
1889 if (cfg->compile_aot)
1890 needs_paddings = FALSE;
1891 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1892 This is required for code patching to be safe on SMP machines.
1894 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1895 #ifndef __native_client_codegen__
1896 if (needs_paddings && pad_size)
1897 x86_padding (code, 4 - pad_size);
1900 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1901 x86_call_code (code, 0);
1906 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1909 * mono_peephole_pass_1:
1911 * Perform peephole opts which should/can be performed before local regalloc
1914 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1918 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1919 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1921 switch (ins->opcode) {
1924 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1926 * X86_LEA is like ADD, but doesn't have the
1927 * sreg1==dreg restriction.
1929 ins->opcode = OP_X86_LEA_MEMBASE;
1930 ins->inst_basereg = ins->sreg1;
1931 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1932 ins->opcode = OP_X86_INC_REG;
1936 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1937 ins->opcode = OP_X86_LEA_MEMBASE;
1938 ins->inst_basereg = ins->sreg1;
1939 ins->inst_imm = -ins->inst_imm;
1940 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1941 ins->opcode = OP_X86_DEC_REG;
1943 case OP_COMPARE_IMM:
1944 case OP_ICOMPARE_IMM:
1945 /* OP_COMPARE_IMM (reg, 0)
1947 * OP_X86_TEST_NULL (reg)
1950 ins->opcode = OP_X86_TEST_NULL;
1952 case OP_X86_COMPARE_MEMBASE_IMM:
1954 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1955 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1957 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1958 * OP_COMPARE_IMM reg, imm
1960 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1962 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1963 ins->inst_basereg == last_ins->inst_destbasereg &&
1964 ins->inst_offset == last_ins->inst_offset) {
1965 ins->opcode = OP_COMPARE_IMM;
1966 ins->sreg1 = last_ins->sreg1;
1968 /* check if we can remove cmp reg,0 with test null */
1970 ins->opcode = OP_X86_TEST_NULL;
1974 case OP_X86_PUSH_MEMBASE:
1975 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1976 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1977 ins->inst_basereg == last_ins->inst_destbasereg &&
1978 ins->inst_offset == last_ins->inst_offset) {
1979 ins->opcode = OP_X86_PUSH;
1980 ins->sreg1 = last_ins->sreg1;
1985 mono_peephole_ins (bb, ins);
1990 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1994 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1995 switch (ins->opcode) {
1997 /* reg = 0 -> XOR (reg, reg) */
1998 /* XOR sets cflags on x86, so we cant do it always */
1999 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2002 ins->opcode = OP_IXOR;
2003 ins->sreg1 = ins->dreg;
2004 ins->sreg2 = ins->dreg;
2007 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2008 * since it takes 3 bytes instead of 7.
2010 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
2011 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2012 ins2->opcode = OP_STORE_MEMBASE_REG;
2013 ins2->sreg1 = ins->dreg;
2015 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2016 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2017 ins2->sreg1 = ins->dreg;
2019 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2020 /* Continue iteration */
2029 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2030 ins->opcode = OP_X86_INC_REG;
2034 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2035 ins->opcode = OP_X86_DEC_REG;
2039 mono_peephole_ins (bb, ins);
2044 * mono_arch_lowering_pass:
2046 * Converts complex opcodes into simpler ones so that each IR instruction
2047 * corresponds to one machine instruction.
2050 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2052 MonoInst *ins, *next;
2055 * FIXME: Need to add more instructions, but the current machine
2056 * description can't model some parts of the composite instructions like
2059 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2060 switch (ins->opcode) {
2063 case OP_IDIV_UN_IMM:
2064 case OP_IREM_UN_IMM:
2066 * Keep the cases where we could generated optimized code, otherwise convert
2067 * to the non-imm variant.
2069 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2071 mono_decompose_op_imm (cfg, bb, ins);
2078 bb->max_vreg = cfg->next_vreg;
2082 branch_cc_table [] = {
2083 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2084 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2085 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2088 /* Maps CMP_... constants to X86_CC_... constants */
2091 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2092 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2096 cc_signed_table [] = {
2097 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2098 FALSE, FALSE, FALSE, FALSE
2101 static unsigned char*
2102 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2104 #define XMM_TEMP_REG 0
2105 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2106 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2107 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2108 /* optimize by assigning a local var for this use so we avoid
2109 * the stack manipulations */
2110 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2111 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2112 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2113 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2114 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2116 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2118 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2121 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2122 x86_fnstcw_membase(code, X86_ESP, 0);
2123 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2124 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2125 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2126 x86_fldcw_membase (code, X86_ESP, 2);
2128 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2129 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2130 x86_pop_reg (code, dreg);
2131 /* FIXME: need the high register
2132 * x86_pop_reg (code, dreg_high);
2135 x86_push_reg (code, X86_EAX); // SP = SP - 4
2136 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2137 x86_pop_reg (code, dreg);
2139 x86_fldcw_membase (code, X86_ESP, 0);
2140 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2143 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2145 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2149 static unsigned char*
2150 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2152 int sreg = tree->sreg1;
2153 int need_touch = FALSE;
2155 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2164 * If requested stack size is larger than one page,
2165 * perform stack-touch operation
2168 * Generate stack probe code.
2169 * Under Windows, it is necessary to allocate one page at a time,
2170 * "touching" stack after each successful sub-allocation. This is
2171 * because of the way stack growth is implemented - there is a
2172 * guard page before the lowest stack page that is currently commited.
2173 * Stack normally grows sequentially so OS traps access to the
2174 * guard page and commits more pages when needed.
2176 x86_test_reg_imm (code, sreg, ~0xFFF);
2177 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2179 br[2] = code; /* loop */
2180 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2181 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2184 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2185 * that follows only initializes the last part of the area.
2187 /* Same as the init code below with size==0x1000 */
2188 if (tree->flags & MONO_INST_INIT) {
2189 x86_push_reg (code, X86_EAX);
2190 x86_push_reg (code, X86_ECX);
2191 x86_push_reg (code, X86_EDI);
2192 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2193 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2194 if (cfg->param_area)
2195 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2197 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2199 x86_prefix (code, X86_REP_PREFIX);
2201 x86_pop_reg (code, X86_EDI);
2202 x86_pop_reg (code, X86_ECX);
2203 x86_pop_reg (code, X86_EAX);
2206 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2207 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2208 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2209 x86_patch (br[3], br[2]);
2210 x86_test_reg_reg (code, sreg, sreg);
2211 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2212 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2214 br[1] = code; x86_jump8 (code, 0);
2216 x86_patch (br[0], code);
2217 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2218 x86_patch (br[1], code);
2219 x86_patch (br[4], code);
2222 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2224 if (tree->flags & MONO_INST_INIT) {
2226 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2227 x86_push_reg (code, X86_EAX);
2230 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2231 x86_push_reg (code, X86_ECX);
2234 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2235 x86_push_reg (code, X86_EDI);
2239 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2240 if (sreg != X86_ECX)
2241 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2242 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2244 if (cfg->param_area)
2245 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2247 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2249 x86_prefix (code, X86_REP_PREFIX);
2252 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2253 x86_pop_reg (code, X86_EDI);
2254 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2255 x86_pop_reg (code, X86_ECX);
2256 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2257 x86_pop_reg (code, X86_EAX);
2264 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2266 /* Move return value to the target register */
2267 switch (ins->opcode) {
2270 case OP_CALL_MEMBASE:
2271 if (ins->dreg != X86_EAX)
2272 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2282 static int tls_gs_offset;
2286 mono_x86_have_tls_get (void)
2289 static gboolean have_tls_get = FALSE;
2290 static gboolean inited = FALSE;
2293 return have_tls_get;
2295 #ifdef MONO_HAVE_FAST_TLS
2298 ins = (guint32*)pthread_getspecific;
2300 * We're looking for these two instructions:
2302 * mov 0x4(%esp),%eax
2303 * mov %gs:[offset](,%eax,4),%eax
2305 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2306 tls_gs_offset = ins [2];
2311 return have_tls_get;
2312 #elif defined(TARGET_ANDROID)
2320 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2322 #if defined(__APPLE__)
2323 x86_prefix (code, X86_GS_PREFIX);
2324 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2325 #elif defined(TARGET_WIN32)
2326 g_assert_not_reached ();
2328 x86_prefix (code, X86_GS_PREFIX);
2329 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2335 * mono_x86_emit_tls_get:
2336 * @code: buffer to store code to
2337 * @dreg: hard register where to place the result
2338 * @tls_offset: offset info
2340 * mono_x86_emit_tls_get emits in @code the native code that puts in
2341 * the dreg register the item in the thread local storage identified
2344 * Returns: a pointer to the end of the stored code
2347 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2349 #if defined(__APPLE__)
2350 x86_prefix (code, X86_GS_PREFIX);
2351 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2352 #elif defined(TARGET_WIN32)
2354 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2355 * Journal and/or a disassembly of the TlsGet () function.
2357 x86_prefix (code, X86_FS_PREFIX);
2358 x86_mov_reg_mem (code, dreg, 0x18, 4);
2359 if (tls_offset < 64) {
2360 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2364 g_assert (tls_offset < 0x440);
2365 /* Load TEB->TlsExpansionSlots */
2366 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2367 x86_test_reg_reg (code, dreg, dreg);
2369 x86_branch (code, X86_CC_EQ, code, TRUE);
2370 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2371 x86_patch (buf [0], code);
2374 if (optimize_for_xen) {
2375 x86_prefix (code, X86_GS_PREFIX);
2376 x86_mov_reg_mem (code, dreg, 0, 4);
2377 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2379 x86_prefix (code, X86_GS_PREFIX);
2380 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2387 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2389 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2390 #if defined(__APPLE__) || defined(__linux__)
2391 if (dreg != offset_reg)
2392 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2393 x86_prefix (code, X86_GS_PREFIX);
2394 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2396 g_assert_not_reached ();
2402 mono_x86_emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2404 return emit_tls_get_reg (code, dreg, offset_reg);
2408 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2410 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2412 g_assert_not_reached ();
2413 #elif defined(__APPLE__) || defined(__linux__)
2414 x86_prefix (code, X86_GS_PREFIX);
2415 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2417 g_assert_not_reached ();
2423 * mono_arch_translate_tls_offset:
2425 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2428 mono_arch_translate_tls_offset (int offset)
2431 return tls_gs_offset + (offset * 4);
2440 * Emit code to initialize an LMF structure at LMF_OFFSET.
2443 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2445 /* save all caller saved regs */
2446 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2447 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2448 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2449 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2450 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2451 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2452 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2454 /* save the current IP */
2455 if (cfg->compile_aot) {
2456 /* This pushes the current ip */
2457 x86_call_imm (code, 0);
2458 x86_pop_reg (code, X86_EAX);
2460 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2461 x86_mov_reg_imm (code, X86_EAX, 0);
2463 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2465 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2466 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2467 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2468 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2469 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2470 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2471 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2472 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2473 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2478 #define REAL_PRINT_REG(text,reg) \
2479 mono_assert (reg >= 0); \
2480 x86_push_reg (code, X86_EAX); \
2481 x86_push_reg (code, X86_EDX); \
2482 x86_push_reg (code, X86_ECX); \
2483 x86_push_reg (code, reg); \
2484 x86_push_imm (code, reg); \
2485 x86_push_imm (code, text " %d %p\n"); \
2486 x86_mov_reg_imm (code, X86_EAX, printf); \
2487 x86_call_reg (code, X86_EAX); \
2488 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2489 x86_pop_reg (code, X86_ECX); \
2490 x86_pop_reg (code, X86_EDX); \
2491 x86_pop_reg (code, X86_EAX);
2493 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2494 #ifdef __native__client_codegen__
2495 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2498 /* benchmark and set based on cpu */
2499 #define LOOP_ALIGNMENT 8
2500 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2504 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2509 guint8 *code = cfg->native_code + cfg->code_len;
2512 if (cfg->opt & MONO_OPT_LOOP) {
2513 int pad, align = LOOP_ALIGNMENT;
2514 /* set alignment depending on cpu */
2515 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2517 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2518 x86_padding (code, pad);
2519 cfg->code_len += pad;
2520 bb->native_offset = cfg->code_len;
2523 #ifdef __native_client_codegen__
2525 /* For Native Client, all indirect call/jump targets must be */
2526 /* 32-byte aligned. Exception handler blocks are jumped to */
2527 /* indirectly as well. */
2528 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2529 (bb->flags & BB_EXCEPTION_HANDLER);
2531 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2532 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2533 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2534 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2535 cfg->code_len += pad;
2536 bb->native_offset = cfg->code_len;
2539 #endif /* __native_client_codegen__ */
2540 if (cfg->verbose_level > 2)
2541 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2543 cpos = bb->max_offset;
2545 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
2546 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2547 g_assert (!cfg->compile_aot);
2550 cov->data [bb->dfn].cil_code = bb->cil_code;
2551 /* this is not thread save, but good enough */
2552 x86_inc_mem (code, &cov->data [bb->dfn].count);
2555 offset = code - cfg->native_code;
2557 mono_debug_open_block (cfg, bb, offset);
2559 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2560 x86_breakpoint (code);
2562 MONO_BB_FOR_EACH_INS (bb, ins) {
2563 offset = code - cfg->native_code;
2565 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2567 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2569 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2570 cfg->code_size *= 2;
2571 cfg->native_code = mono_realloc_native_code(cfg);
2572 code = cfg->native_code + offset;
2573 cfg->stat_code_reallocs++;
2576 if (cfg->debug_info)
2577 mono_debug_record_line_number (cfg, ins, offset);
2579 switch (ins->opcode) {
2581 x86_mul_reg (code, ins->sreg2, TRUE);
2584 x86_mul_reg (code, ins->sreg2, FALSE);
2586 case OP_X86_SETEQ_MEMBASE:
2587 case OP_X86_SETNE_MEMBASE:
2588 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2589 ins->inst_basereg, ins->inst_offset, TRUE);
2591 case OP_STOREI1_MEMBASE_IMM:
2592 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2594 case OP_STOREI2_MEMBASE_IMM:
2595 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2597 case OP_STORE_MEMBASE_IMM:
2598 case OP_STOREI4_MEMBASE_IMM:
2599 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2601 case OP_STOREI1_MEMBASE_REG:
2602 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2604 case OP_STOREI2_MEMBASE_REG:
2605 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2607 case OP_STORE_MEMBASE_REG:
2608 case OP_STOREI4_MEMBASE_REG:
2609 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2611 case OP_STORE_MEM_IMM:
2612 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2615 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2619 /* These are created by the cprop pass so they use inst_imm as the source */
2620 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2623 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2626 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2628 case OP_LOAD_MEMBASE:
2629 case OP_LOADI4_MEMBASE:
2630 case OP_LOADU4_MEMBASE:
2631 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2633 case OP_LOADU1_MEMBASE:
2634 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2636 case OP_LOADI1_MEMBASE:
2637 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2639 case OP_LOADU2_MEMBASE:
2640 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2642 case OP_LOADI2_MEMBASE:
2643 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2645 case OP_ICONV_TO_I1:
2647 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2649 case OP_ICONV_TO_I2:
2651 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2653 case OP_ICONV_TO_U1:
2654 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2656 case OP_ICONV_TO_U2:
2657 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2661 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2663 case OP_COMPARE_IMM:
2664 case OP_ICOMPARE_IMM:
2665 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2667 case OP_X86_COMPARE_MEMBASE_REG:
2668 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2670 case OP_X86_COMPARE_MEMBASE_IMM:
2671 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2673 case OP_X86_COMPARE_MEMBASE8_IMM:
2674 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2676 case OP_X86_COMPARE_REG_MEMBASE:
2677 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2679 case OP_X86_COMPARE_MEM_IMM:
2680 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2682 case OP_X86_TEST_NULL:
2683 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2685 case OP_X86_ADD_MEMBASE_IMM:
2686 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2688 case OP_X86_ADD_REG_MEMBASE:
2689 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2691 case OP_X86_SUB_MEMBASE_IMM:
2692 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2694 case OP_X86_SUB_REG_MEMBASE:
2695 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2697 case OP_X86_AND_MEMBASE_IMM:
2698 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2700 case OP_X86_OR_MEMBASE_IMM:
2701 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2703 case OP_X86_XOR_MEMBASE_IMM:
2704 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2706 case OP_X86_ADD_MEMBASE_REG:
2707 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2709 case OP_X86_SUB_MEMBASE_REG:
2710 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2712 case OP_X86_AND_MEMBASE_REG:
2713 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2715 case OP_X86_OR_MEMBASE_REG:
2716 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2718 case OP_X86_XOR_MEMBASE_REG:
2719 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2721 case OP_X86_INC_MEMBASE:
2722 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2724 case OP_X86_INC_REG:
2725 x86_inc_reg (code, ins->dreg);
2727 case OP_X86_DEC_MEMBASE:
2728 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2730 case OP_X86_DEC_REG:
2731 x86_dec_reg (code, ins->dreg);
2733 case OP_X86_MUL_REG_MEMBASE:
2734 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2736 case OP_X86_AND_REG_MEMBASE:
2737 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2739 case OP_X86_OR_REG_MEMBASE:
2740 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2742 case OP_X86_XOR_REG_MEMBASE:
2743 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2746 x86_breakpoint (code);
2748 case OP_RELAXED_NOP:
2749 x86_prefix (code, X86_REP_PREFIX);
2757 case OP_DUMMY_STORE:
2758 case OP_DUMMY_ICONST:
2759 case OP_DUMMY_R8CONST:
2760 case OP_NOT_REACHED:
2763 case OP_IL_SEQ_POINT:
2764 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2766 case OP_SEQ_POINT: {
2769 if (cfg->compile_aot)
2772 /* Have to use ecx as a temp reg since this can occur after OP_SETRET */
2775 * We do this _before_ the breakpoint, so single stepping after
2776 * a breakpoint is hit will step to the next IL offset.
2778 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
2779 MonoInst *var = cfg->arch.ss_tramp_var;
2783 g_assert (var->opcode == OP_REGOFFSET);
2784 /* Load ss_tramp_var */
2785 /* This is equal to &ss_trampoline */
2786 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, sizeof (mgreg_t));
2787 x86_alu_membase_imm (code, X86_CMP, X86_ECX, 0, 0);
2788 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2789 x86_call_membase (code, X86_ECX, 0);
2790 x86_patch (br [0], code);
2794 * Many parts of sdb depend on the ip after the single step trampoline call to be equal to the seq point offset.
2795 * This means we have to put the loading of bp_tramp_var after the offset.
2798 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2800 MonoInst *var = cfg->arch.bp_tramp_var;
2803 g_assert (var->opcode == OP_REGOFFSET);
2804 /* Load the address of the bp trampoline */
2805 /* This needs to be constant size */
2806 guint8 *start = code;
2807 x86_mov_reg_membase (code, X86_ECX, var->inst_basereg, var->inst_offset, 4);
2808 if (code < start + OP_SEQ_POINT_BP_OFFSET) {
2809 int size = start + OP_SEQ_POINT_BP_OFFSET - code;
2810 x86_padding (code, size);
2813 * A placeholder for a possible breakpoint inserted by
2814 * mono_arch_set_breakpoint ().
2816 for (i = 0; i < 2; ++i)
2819 * Add an additional nop so skipping the bp doesn't cause the ip to point
2820 * to another IL offset.
2828 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2832 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2837 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2841 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2846 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2850 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2855 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2859 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2862 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2866 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2870 #if defined( __native_client_codegen__ )
2871 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2872 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2875 * The code is the same for div/rem, the allocator will allocate dreg
2876 * to RAX/RDX as appropriate.
2878 if (ins->sreg2 == X86_EDX) {
2879 /* cdq clobbers this */
2880 x86_push_reg (code, ins->sreg2);
2882 x86_div_membase (code, X86_ESP, 0, TRUE);
2883 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2886 x86_div_reg (code, ins->sreg2, TRUE);
2891 #if defined( __native_client_codegen__ )
2892 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2893 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2895 if (ins->sreg2 == X86_EDX) {
2896 x86_push_reg (code, ins->sreg2);
2897 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2898 x86_div_membase (code, X86_ESP, 0, FALSE);
2899 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2901 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2902 x86_div_reg (code, ins->sreg2, FALSE);
2906 #if defined( __native_client_codegen__ )
2907 if (ins->inst_imm == 0) {
2908 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2909 x86_jump32 (code, 0);
2913 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2915 x86_div_reg (code, ins->sreg2, TRUE);
2918 int power = mono_is_power_of_two (ins->inst_imm);
2920 g_assert (ins->sreg1 == X86_EAX);
2921 g_assert (ins->dreg == X86_EAX);
2922 g_assert (power >= 0);
2925 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2927 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2929 * If the divident is >= 0, this does not nothing. If it is positive, it
2930 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2932 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2933 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2934 } else if (power == 0) {
2935 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2937 /* Based on gcc code */
2939 /* Add compensation for negative dividents */
2941 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2942 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2943 /* Compute remainder */
2944 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2945 /* Remove compensation */
2946 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2951 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2955 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2958 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2962 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2965 g_assert (ins->sreg2 == X86_ECX);
2966 x86_shift_reg (code, X86_SHL, ins->dreg);
2969 g_assert (ins->sreg2 == X86_ECX);
2970 x86_shift_reg (code, X86_SAR, ins->dreg);
2974 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2977 case OP_ISHR_UN_IMM:
2978 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2981 g_assert (ins->sreg2 == X86_ECX);
2982 x86_shift_reg (code, X86_SHR, ins->dreg);
2986 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2989 guint8 *jump_to_end;
2991 /* handle shifts below 32 bits */
2992 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2993 x86_shift_reg (code, X86_SHL, ins->sreg1);
2995 x86_test_reg_imm (code, X86_ECX, 32);
2996 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2998 /* handle shift over 32 bit */
2999 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3000 x86_clear_reg (code, ins->sreg1);
3002 x86_patch (jump_to_end, code);
3006 guint8 *jump_to_end;
3008 /* handle shifts below 32 bits */
3009 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3010 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
3012 x86_test_reg_imm (code, X86_ECX, 32);
3013 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3015 /* handle shifts over 31 bits */
3016 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3017 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
3019 x86_patch (jump_to_end, code);
3023 guint8 *jump_to_end;
3025 /* handle shifts below 32 bits */
3026 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3027 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
3029 x86_test_reg_imm (code, X86_ECX, 32);
3030 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3032 /* handle shifts over 31 bits */
3033 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3034 x86_clear_reg (code, ins->backend.reg3);
3036 x86_patch (jump_to_end, code);
3040 if (ins->inst_imm >= 32) {
3041 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3042 x86_clear_reg (code, ins->sreg1);
3043 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
3045 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
3046 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
3050 if (ins->inst_imm >= 32) {
3051 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3052 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
3053 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
3055 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3056 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3059 case OP_LSHR_UN_IMM:
3060 if (ins->inst_imm >= 32) {
3061 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3062 x86_clear_reg (code, ins->backend.reg3);
3063 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3065 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3066 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3070 x86_not_reg (code, ins->sreg1);
3073 x86_neg_reg (code, ins->sreg1);
3077 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3081 switch (ins->inst_imm) {
3085 if (ins->dreg != ins->sreg1)
3086 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3087 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3090 /* LEA r1, [r2 + r2*2] */
3091 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3094 /* LEA r1, [r2 + r2*4] */
3095 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3098 /* LEA r1, [r2 + r2*2] */
3100 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3101 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3104 /* LEA r1, [r2 + r2*8] */
3105 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3108 /* LEA r1, [r2 + r2*4] */
3110 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3111 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3114 /* LEA r1, [r2 + r2*2] */
3116 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3117 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3120 /* LEA r1, [r2 + r2*4] */
3121 /* LEA r1, [r1 + r1*4] */
3122 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3123 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3126 /* LEA r1, [r2 + r2*4] */
3128 /* LEA r1, [r1 + r1*4] */
3129 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3130 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3131 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3134 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3139 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3140 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3142 case OP_IMUL_OVF_UN: {
3143 /* the mul operation and the exception check should most likely be split */
3144 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3145 /*g_assert (ins->sreg2 == X86_EAX);
3146 g_assert (ins->dreg == X86_EAX);*/
3147 if (ins->sreg2 == X86_EAX) {
3148 non_eax_reg = ins->sreg1;
3149 } else if (ins->sreg1 == X86_EAX) {
3150 non_eax_reg = ins->sreg2;
3152 /* no need to save since we're going to store to it anyway */
3153 if (ins->dreg != X86_EAX) {
3155 x86_push_reg (code, X86_EAX);
3157 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3158 non_eax_reg = ins->sreg2;
3160 if (ins->dreg == X86_EDX) {
3163 x86_push_reg (code, X86_EAX);
3167 x86_push_reg (code, X86_EDX);
3169 x86_mul_reg (code, non_eax_reg, FALSE);
3170 /* save before the check since pop and mov don't change the flags */
3171 if (ins->dreg != X86_EAX)
3172 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3174 x86_pop_reg (code, X86_EDX);
3176 x86_pop_reg (code, X86_EAX);
3177 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3181 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3184 g_assert_not_reached ();
3185 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3186 x86_mov_reg_imm (code, ins->dreg, 0);
3189 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3190 x86_mov_reg_imm (code, ins->dreg, 0);
3192 case OP_LOAD_GOTADDR:
3193 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3194 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3197 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3198 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3200 case OP_X86_PUSH_GOT_ENTRY:
3201 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3202 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3205 if (ins->dreg != ins->sreg1)
3206 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3209 MonoCallInst *call = (MonoCallInst*)ins;
3212 ins->flags |= MONO_INST_GC_CALLSITE;
3213 ins->backend.pc_offset = code - cfg->native_code;
3215 /* reset offset to make max_len work */
3216 offset = code - cfg->native_code;
3218 g_assert (!cfg->method->save_lmf);
3220 /* restore callee saved registers */
3221 for (i = 0; i < X86_NREG; ++i)
3222 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3224 if (cfg->used_int_regs & (1 << X86_ESI)) {
3225 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3228 if (cfg->used_int_regs & (1 << X86_EDI)) {
3229 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3232 if (cfg->used_int_regs & (1 << X86_EBX)) {
3233 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3237 /* Copy arguments on the stack to our argument area */
3238 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3239 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3240 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3243 /* restore ESP/EBP */
3245 offset = code - cfg->native_code;
3246 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3247 x86_jump32 (code, 0);
3249 ins->flags |= MONO_INST_GC_CALLSITE;
3250 cfg->disable_aot = TRUE;
3254 /* ensure ins->sreg1 is not NULL
3255 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3256 * cmp DWORD PTR [eax], 0
3258 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3261 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3262 x86_push_reg (code, hreg);
3263 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3264 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3265 x86_pop_reg (code, hreg);
3278 case OP_VOIDCALL_REG:
3280 case OP_FCALL_MEMBASE:
3281 case OP_LCALL_MEMBASE:
3282 case OP_VCALL_MEMBASE:
3283 case OP_VCALL2_MEMBASE:
3284 case OP_VOIDCALL_MEMBASE:
3285 case OP_CALL_MEMBASE: {
3288 call = (MonoCallInst*)ins;
3289 cinfo = (CallInfo*)call->call_info;
3291 switch (ins->opcode) {
3298 if (ins->flags & MONO_INST_HAS_METHOD)
3299 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3301 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3307 case OP_VOIDCALL_REG:
3309 x86_call_reg (code, ins->sreg1);
3311 case OP_FCALL_MEMBASE:
3312 case OP_LCALL_MEMBASE:
3313 case OP_VCALL_MEMBASE:
3314 case OP_VCALL2_MEMBASE:
3315 case OP_VOIDCALL_MEMBASE:
3316 case OP_CALL_MEMBASE:
3317 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3320 g_assert_not_reached ();
3323 ins->flags |= MONO_INST_GC_CALLSITE;
3324 ins->backend.pc_offset = code - cfg->native_code;
3325 if (cinfo->callee_stack_pop) {
3326 /* Have to compensate for the stack space popped by the callee */
3327 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3329 code = emit_move_return_value (cfg, ins, code);
3333 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3335 case OP_X86_LEA_MEMBASE:
3336 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3339 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3342 /* keep alignment */
3343 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3344 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3345 code = mono_emit_stack_alloc (cfg, code, ins);
3346 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3347 if (cfg->param_area)
3348 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3350 case OP_LOCALLOC_IMM: {
3351 guint32 size = ins->inst_imm;
3352 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3354 if (ins->flags & MONO_INST_INIT) {
3355 /* FIXME: Optimize this */
3356 x86_mov_reg_imm (code, ins->dreg, size);
3357 ins->sreg1 = ins->dreg;
3359 code = mono_emit_stack_alloc (cfg, code, ins);
3360 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3362 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3363 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3365 if (cfg->param_area)
3366 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3370 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3371 x86_push_reg (code, ins->sreg1);
3372 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3373 (gpointer)"mono_arch_throw_exception");
3374 ins->flags |= MONO_INST_GC_CALLSITE;
3375 ins->backend.pc_offset = code - cfg->native_code;
3379 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3380 x86_push_reg (code, ins->sreg1);
3381 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3382 (gpointer)"mono_arch_rethrow_exception");
3383 ins->flags |= MONO_INST_GC_CALLSITE;
3384 ins->backend.pc_offset = code - cfg->native_code;
3387 case OP_CALL_HANDLER:
3388 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3389 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3390 x86_call_imm (code, 0);
3391 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3392 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3394 case OP_START_HANDLER: {
3395 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3396 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3397 if (cfg->param_area)
3398 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3401 case OP_ENDFINALLY: {
3402 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3403 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3407 case OP_ENDFILTER: {
3408 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3409 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3410 /* The local allocator will put the result into EAX */
3415 if (ins->dreg != X86_EAX)
3416 x86_mov_reg_reg (code, ins->dreg, X86_EAX, sizeof (gpointer));
3420 ins->inst_c0 = code - cfg->native_code;
3423 if (ins->inst_target_bb->native_offset) {
3424 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3426 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3427 if ((cfg->opt & MONO_OPT_BRANCH) &&
3428 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3429 x86_jump8 (code, 0);
3431 x86_jump32 (code, 0);
3435 x86_jump_reg (code, ins->sreg1);
3454 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3455 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3457 case OP_COND_EXC_EQ:
3458 case OP_COND_EXC_NE_UN:
3459 case OP_COND_EXC_LT:
3460 case OP_COND_EXC_LT_UN:
3461 case OP_COND_EXC_GT:
3462 case OP_COND_EXC_GT_UN:
3463 case OP_COND_EXC_GE:
3464 case OP_COND_EXC_GE_UN:
3465 case OP_COND_EXC_LE:
3466 case OP_COND_EXC_LE_UN:
3467 case OP_COND_EXC_IEQ:
3468 case OP_COND_EXC_INE_UN:
3469 case OP_COND_EXC_ILT:
3470 case OP_COND_EXC_ILT_UN:
3471 case OP_COND_EXC_IGT:
3472 case OP_COND_EXC_IGT_UN:
3473 case OP_COND_EXC_IGE:
3474 case OP_COND_EXC_IGE_UN:
3475 case OP_COND_EXC_ILE:
3476 case OP_COND_EXC_ILE_UN:
3477 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3479 case OP_COND_EXC_OV:
3480 case OP_COND_EXC_NO:
3482 case OP_COND_EXC_NC:
3483 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3485 case OP_COND_EXC_IOV:
3486 case OP_COND_EXC_INO:
3487 case OP_COND_EXC_IC:
3488 case OP_COND_EXC_INC:
3489 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3501 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3509 case OP_CMOV_INE_UN:
3510 case OP_CMOV_IGE_UN:
3511 case OP_CMOV_IGT_UN:
3512 case OP_CMOV_ILE_UN:
3513 case OP_CMOV_ILT_UN:
3514 g_assert (ins->dreg == ins->sreg1);
3515 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3518 /* floating point opcodes */
3520 double d = *(double *)ins->inst_p0;
3522 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3524 } else if (d == 1.0) {
3527 if (cfg->compile_aot) {
3528 guint32 *val = (guint32*)&d;
3529 x86_push_imm (code, val [1]);
3530 x86_push_imm (code, val [0]);
3531 x86_fld_membase (code, X86_ESP, 0, TRUE);
3532 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3535 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3536 x86_fld (code, NULL, TRUE);
3542 float f = *(float *)ins->inst_p0;
3544 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3546 } else if (f == 1.0) {
3549 if (cfg->compile_aot) {
3550 guint32 val = *(guint32*)&f;
3551 x86_push_imm (code, val);
3552 x86_fld_membase (code, X86_ESP, 0, FALSE);
3553 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3556 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3557 x86_fld (code, NULL, FALSE);
3562 case OP_STORER8_MEMBASE_REG:
3563 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3565 case OP_LOADR8_MEMBASE:
3566 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3568 case OP_STORER4_MEMBASE_REG:
3569 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3571 case OP_LOADR4_MEMBASE:
3572 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3574 case OP_ICONV_TO_R4:
3575 x86_push_reg (code, ins->sreg1);
3576 x86_fild_membase (code, X86_ESP, 0, FALSE);
3577 /* Change precision */
3578 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3579 x86_fld_membase (code, X86_ESP, 0, FALSE);
3580 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3582 case OP_ICONV_TO_R8:
3583 x86_push_reg (code, ins->sreg1);
3584 x86_fild_membase (code, X86_ESP, 0, FALSE);
3585 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3587 case OP_ICONV_TO_R_UN:
3588 x86_push_imm (code, 0);
3589 x86_push_reg (code, ins->sreg1);
3590 x86_fild_membase (code, X86_ESP, 0, TRUE);
3591 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3593 case OP_X86_FP_LOAD_I8:
3594 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3596 case OP_X86_FP_LOAD_I4:
3597 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3599 case OP_FCONV_TO_R4:
3600 /* Change precision */
3601 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3602 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3603 x86_fld_membase (code, X86_ESP, 0, FALSE);
3604 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3606 case OP_FCONV_TO_I1:
3607 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3609 case OP_FCONV_TO_U1:
3610 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3612 case OP_FCONV_TO_I2:
3613 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3615 case OP_FCONV_TO_U2:
3616 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3618 case OP_FCONV_TO_I4:
3620 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3622 case OP_FCONV_TO_I8:
3623 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3624 x86_fnstcw_membase(code, X86_ESP, 0);
3625 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3626 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3627 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3628 x86_fldcw_membase (code, X86_ESP, 2);
3629 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3630 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3631 x86_pop_reg (code, ins->dreg);
3632 x86_pop_reg (code, ins->backend.reg3);
3633 x86_fldcw_membase (code, X86_ESP, 0);
3634 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3636 case OP_LCONV_TO_R8_2:
3637 x86_push_reg (code, ins->sreg2);
3638 x86_push_reg (code, ins->sreg1);
3639 x86_fild_membase (code, X86_ESP, 0, TRUE);
3640 /* Change precision */
3641 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3642 x86_fld_membase (code, X86_ESP, 0, TRUE);
3643 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3645 case OP_LCONV_TO_R4_2:
3646 x86_push_reg (code, ins->sreg2);
3647 x86_push_reg (code, ins->sreg1);
3648 x86_fild_membase (code, X86_ESP, 0, TRUE);
3649 /* Change precision */
3650 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3651 x86_fld_membase (code, X86_ESP, 0, FALSE);
3652 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3654 case OP_LCONV_TO_R_UN_2: {
3655 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3658 /* load 64bit integer to FP stack */
3659 x86_push_reg (code, ins->sreg2);
3660 x86_push_reg (code, ins->sreg1);
3661 x86_fild_membase (code, X86_ESP, 0, TRUE);
3663 /* test if lreg is negative */
3664 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3665 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3667 /* add correction constant mn */
3668 if (cfg->compile_aot) {
3669 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3670 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3671 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3672 x86_fld80_membase (code, X86_ESP, 2);
3673 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3675 x86_fld80_mem (code, mn);
3677 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3679 x86_patch (br, code);
3681 /* Change precision */
3682 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3683 x86_fld_membase (code, X86_ESP, 0, TRUE);
3685 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3689 case OP_LCONV_TO_OVF_I:
3690 case OP_LCONV_TO_OVF_I4_2: {
3691 guint8 *br [3], *label [1];
3695 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3697 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3699 /* If the low word top bit is set, see if we are negative */
3700 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3701 /* We are not negative (no top bit set, check for our top word to be zero */
3702 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3703 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3706 /* throw exception */
3707 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3709 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3710 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3711 x86_jump8 (code, 0);
3713 x86_jump32 (code, 0);
3715 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3716 x86_jump32 (code, 0);
3720 x86_patch (br [0], code);
3721 /* our top bit is set, check that top word is 0xfffffff */
3722 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3724 x86_patch (br [1], code);
3725 /* nope, emit exception */
3726 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3727 x86_patch (br [2], label [0]);
3729 if (ins->dreg != ins->sreg1)
3730 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3734 /* Not needed on the fp stack */
3736 case OP_MOVE_F_TO_I4:
3737 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
3738 x86_mov_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, 4);
3740 case OP_MOVE_I4_TO_F:
3741 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
3742 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
3745 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3748 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3751 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3754 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3762 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3767 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3774 * it really doesn't make sense to inline all this code,
3775 * it's here just to show that things may not be as simple
3778 guchar *check_pos, *end_tan, *pop_jump;
3779 x86_push_reg (code, X86_EAX);
3782 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3784 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3785 x86_fstp (code, 0); /* pop the 1.0 */
3787 x86_jump8 (code, 0);
3789 x86_fp_op (code, X86_FADD, 0);
3793 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3795 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3798 x86_patch (pop_jump, code);
3799 x86_fstp (code, 0); /* pop the 1.0 */
3800 x86_patch (check_pos, code);
3801 x86_patch (end_tan, code);
3803 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3804 x86_pop_reg (code, X86_EAX);
3811 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3820 g_assert (cfg->opt & MONO_OPT_CMOV);
3821 g_assert (ins->dreg == ins->sreg1);
3822 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3823 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3826 g_assert (cfg->opt & MONO_OPT_CMOV);
3827 g_assert (ins->dreg == ins->sreg1);
3828 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3829 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3832 g_assert (cfg->opt & MONO_OPT_CMOV);
3833 g_assert (ins->dreg == ins->sreg1);
3834 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3835 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3838 g_assert (cfg->opt & MONO_OPT_CMOV);
3839 g_assert (ins->dreg == ins->sreg1);
3840 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3841 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3847 x86_fxch (code, ins->inst_imm);
3852 x86_push_reg (code, X86_EAX);
3853 /* we need to exchange ST(0) with ST(1) */
3856 /* this requires a loop, because fprem somtimes
3857 * returns a partial remainder */
3859 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3860 /* x86_fprem1 (code); */
3863 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3865 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3871 x86_pop_reg (code, X86_EAX);
3875 if (cfg->opt & MONO_OPT_FCMOV) {
3876 x86_fcomip (code, 1);
3880 /* this overwrites EAX */
3881 EMIT_FPCOMPARE(code);
3882 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3886 if (cfg->opt & MONO_OPT_FCMOV) {
3887 /* zeroing the register at the start results in
3888 * shorter and faster code (we can also remove the widening op)
3890 guchar *unordered_check;
3891 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3892 x86_fcomip (code, 1);
3894 unordered_check = code;
3895 x86_branch8 (code, X86_CC_P, 0, FALSE);
3896 if (ins->opcode == OP_FCEQ) {
3897 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3898 x86_patch (unordered_check, code);
3900 guchar *jump_to_end;
3901 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3903 x86_jump8 (code, 0);
3904 x86_patch (unordered_check, code);
3905 x86_inc_reg (code, ins->dreg);
3906 x86_patch (jump_to_end, code);
3911 if (ins->dreg != X86_EAX)
3912 x86_push_reg (code, X86_EAX);
3914 EMIT_FPCOMPARE(code);
3915 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3916 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3917 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3918 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3920 if (ins->dreg != X86_EAX)
3921 x86_pop_reg (code, X86_EAX);
3925 if (cfg->opt & MONO_OPT_FCMOV) {
3926 /* zeroing the register at the start results in
3927 * shorter and faster code (we can also remove the widening op)
3929 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3930 x86_fcomip (code, 1);
3932 if (ins->opcode == OP_FCLT_UN) {
3933 guchar *unordered_check = code;
3934 guchar *jump_to_end;
3935 x86_branch8 (code, X86_CC_P, 0, FALSE);
3936 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3938 x86_jump8 (code, 0);
3939 x86_patch (unordered_check, code);
3940 x86_inc_reg (code, ins->dreg);
3941 x86_patch (jump_to_end, code);
3943 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3947 if (ins->dreg != X86_EAX)
3948 x86_push_reg (code, X86_EAX);
3950 EMIT_FPCOMPARE(code);
3951 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3952 if (ins->opcode == OP_FCLT_UN) {
3953 guchar *is_not_zero_check, *end_jump;
3954 is_not_zero_check = code;
3955 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3957 x86_jump8 (code, 0);
3958 x86_patch (is_not_zero_check, code);
3959 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3961 x86_patch (end_jump, code);
3963 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3964 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3966 if (ins->dreg != X86_EAX)
3967 x86_pop_reg (code, X86_EAX);
3970 guchar *unordered_check;
3971 guchar *jump_to_end;
3972 if (cfg->opt & MONO_OPT_FCMOV) {
3973 /* zeroing the register at the start results in
3974 * shorter and faster code (we can also remove the widening op)
3976 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3977 x86_fcomip (code, 1);
3979 unordered_check = code;
3980 x86_branch8 (code, X86_CC_P, 0, FALSE);
3981 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3982 x86_patch (unordered_check, code);
3985 if (ins->dreg != X86_EAX)
3986 x86_push_reg (code, X86_EAX);
3988 EMIT_FPCOMPARE(code);
3989 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3990 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3991 unordered_check = code;
3992 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3994 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3995 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3996 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3998 x86_jump8 (code, 0);
3999 x86_patch (unordered_check, code);
4000 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4001 x86_patch (jump_to_end, code);
4003 if (ins->dreg != X86_EAX)
4004 x86_pop_reg (code, X86_EAX);
4009 if (cfg->opt & MONO_OPT_FCMOV) {
4010 /* zeroing the register at the start results in
4011 * shorter and faster code (we can also remove the widening op)
4013 guchar *unordered_check;
4014 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4015 x86_fcomip (code, 1);
4017 if (ins->opcode == OP_FCGT) {
4018 unordered_check = code;
4019 x86_branch8 (code, X86_CC_P, 0, FALSE);
4020 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4021 x86_patch (unordered_check, code);
4023 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4027 if (ins->dreg != X86_EAX)
4028 x86_push_reg (code, X86_EAX);
4030 EMIT_FPCOMPARE(code);
4031 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4032 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4033 if (ins->opcode == OP_FCGT_UN) {
4034 guchar *is_not_zero_check, *end_jump;
4035 is_not_zero_check = code;
4036 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4038 x86_jump8 (code, 0);
4039 x86_patch (is_not_zero_check, code);
4040 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4042 x86_patch (end_jump, code);
4044 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4045 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4047 if (ins->dreg != X86_EAX)
4048 x86_pop_reg (code, X86_EAX);
4051 guchar *unordered_check;
4052 guchar *jump_to_end;
4053 if (cfg->opt & MONO_OPT_FCMOV) {
4054 /* zeroing the register at the start results in
4055 * shorter and faster code (we can also remove the widening op)
4057 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4058 x86_fcomip (code, 1);
4060 unordered_check = code;
4061 x86_branch8 (code, X86_CC_P, 0, FALSE);
4062 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4063 x86_patch (unordered_check, code);
4066 if (ins->dreg != X86_EAX)
4067 x86_push_reg (code, X86_EAX);
4069 EMIT_FPCOMPARE(code);
4070 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4071 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4072 unordered_check = code;
4073 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4075 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4076 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4077 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4079 x86_jump8 (code, 0);
4080 x86_patch (unordered_check, code);
4081 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4082 x86_patch (jump_to_end, code);
4084 if (ins->dreg != X86_EAX)
4085 x86_pop_reg (code, X86_EAX);
4089 if (cfg->opt & MONO_OPT_FCMOV) {
4090 guchar *jump = code;
4091 x86_branch8 (code, X86_CC_P, 0, TRUE);
4092 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4093 x86_patch (jump, code);
4096 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4097 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4100 /* Branch if C013 != 100 */
4101 if (cfg->opt & MONO_OPT_FCMOV) {
4102 /* branch if !ZF or (PF|CF) */
4103 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4104 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4105 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4108 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4109 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4112 if (cfg->opt & MONO_OPT_FCMOV) {
4113 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4116 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4119 if (cfg->opt & MONO_OPT_FCMOV) {
4120 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4121 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4124 if (ins->opcode == OP_FBLT_UN) {
4125 guchar *is_not_zero_check, *end_jump;
4126 is_not_zero_check = code;
4127 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4129 x86_jump8 (code, 0);
4130 x86_patch (is_not_zero_check, code);
4131 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4133 x86_patch (end_jump, code);
4135 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4139 if (cfg->opt & MONO_OPT_FCMOV) {
4140 if (ins->opcode == OP_FBGT) {
4143 /* skip branch if C1=1 */
4145 x86_branch8 (code, X86_CC_P, 0, FALSE);
4146 /* branch if (C0 | C3) = 1 */
4147 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4148 x86_patch (br1, code);
4150 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4154 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4155 if (ins->opcode == OP_FBGT_UN) {
4156 guchar *is_not_zero_check, *end_jump;
4157 is_not_zero_check = code;
4158 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4160 x86_jump8 (code, 0);
4161 x86_patch (is_not_zero_check, code);
4162 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4164 x86_patch (end_jump, code);
4166 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4169 /* Branch if C013 == 100 or 001 */
4170 if (cfg->opt & MONO_OPT_FCMOV) {
4173 /* skip branch if C1=1 */
4175 x86_branch8 (code, X86_CC_P, 0, FALSE);
4176 /* branch if (C0 | C3) = 1 */
4177 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4178 x86_patch (br1, code);
4181 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4182 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4183 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4184 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4187 /* Branch if C013 == 000 */
4188 if (cfg->opt & MONO_OPT_FCMOV) {
4189 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4192 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4195 /* Branch if C013=000 or 100 */
4196 if (cfg->opt & MONO_OPT_FCMOV) {
4199 /* skip branch if C1=1 */
4201 x86_branch8 (code, X86_CC_P, 0, FALSE);
4202 /* branch if C0=0 */
4203 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4204 x86_patch (br1, code);
4207 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4208 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4209 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4212 /* Branch if C013 != 001 */
4213 if (cfg->opt & MONO_OPT_FCMOV) {
4214 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4215 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4218 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4219 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4223 x86_push_reg (code, X86_EAX);
4226 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4227 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4228 x86_pop_reg (code, X86_EAX);
4230 /* Have to clean up the fp stack before throwing the exception */
4232 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4235 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
4237 x86_patch (br1, code);
4241 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4244 case OP_TLS_GET_REG: {
4245 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4249 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4252 case OP_TLS_SET_REG: {
4253 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4256 case OP_MEMORY_BARRIER: {
4257 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4258 x86_prefix (code, X86_LOCK_PREFIX);
4259 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4263 case OP_ATOMIC_ADD_I4: {
4264 int dreg = ins->dreg;
4266 g_assert (cfg->has_atomic_add_i4);
4268 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4269 if (ins->sreg2 == dreg) {
4270 if (dreg == X86_EBX) {
4272 if (ins->inst_basereg == X86_EDI)
4276 if (ins->inst_basereg == X86_EBX)
4279 } else if (ins->inst_basereg == dreg) {
4280 if (dreg == X86_EBX) {
4282 if (ins->sreg2 == X86_EDI)
4286 if (ins->sreg2 == X86_EBX)
4291 if (dreg != ins->dreg) {
4292 x86_push_reg (code, dreg);
4295 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4296 x86_prefix (code, X86_LOCK_PREFIX);
4297 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4298 /* dreg contains the old value, add with sreg2 value */
4299 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4301 if (ins->dreg != dreg) {
4302 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4303 x86_pop_reg (code, dreg);
4308 case OP_ATOMIC_EXCHANGE_I4: {
4310 int sreg2 = ins->sreg2;
4311 int breg = ins->inst_basereg;
4313 g_assert (cfg->has_atomic_exchange_i4);
4315 /* cmpxchg uses eax as comperand, need to make sure we can use it
4316 * hack to overcome limits in x86 reg allocator
4317 * (req: dreg == eax and sreg2 != eax and breg != eax)
4319 g_assert (ins->dreg == X86_EAX);
4321 /* We need the EAX reg for the cmpxchg */
4322 if (ins->sreg2 == X86_EAX) {
4323 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4324 x86_push_reg (code, sreg2);
4325 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4328 if (breg == X86_EAX) {
4329 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4330 x86_push_reg (code, breg);
4331 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4334 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4336 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4337 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4338 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4339 x86_patch (br [1], br [0]);
4341 if (breg != ins->inst_basereg)
4342 x86_pop_reg (code, breg);
4344 if (ins->sreg2 != sreg2)
4345 x86_pop_reg (code, sreg2);
4349 case OP_ATOMIC_CAS_I4: {
4350 g_assert (ins->dreg == X86_EAX);
4351 g_assert (ins->sreg3 == X86_EAX);
4352 g_assert (ins->sreg1 != X86_EAX);
4353 g_assert (ins->sreg1 != ins->sreg2);
4355 x86_prefix (code, X86_LOCK_PREFIX);
4356 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4359 case OP_ATOMIC_LOAD_I1: {
4360 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4363 case OP_ATOMIC_LOAD_U1: {
4364 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4367 case OP_ATOMIC_LOAD_I2: {
4368 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4371 case OP_ATOMIC_LOAD_U2: {
4372 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4375 case OP_ATOMIC_LOAD_I4:
4376 case OP_ATOMIC_LOAD_U4: {
4377 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4380 case OP_ATOMIC_LOAD_R4:
4381 case OP_ATOMIC_LOAD_R8: {
4382 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4385 case OP_ATOMIC_STORE_I1:
4386 case OP_ATOMIC_STORE_U1:
4387 case OP_ATOMIC_STORE_I2:
4388 case OP_ATOMIC_STORE_U2:
4389 case OP_ATOMIC_STORE_I4:
4390 case OP_ATOMIC_STORE_U4: {
4393 switch (ins->opcode) {
4394 case OP_ATOMIC_STORE_I1:
4395 case OP_ATOMIC_STORE_U1:
4398 case OP_ATOMIC_STORE_I2:
4399 case OP_ATOMIC_STORE_U2:
4402 case OP_ATOMIC_STORE_I4:
4403 case OP_ATOMIC_STORE_U4:
4408 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4410 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4414 case OP_ATOMIC_STORE_R4:
4415 case OP_ATOMIC_STORE_R8: {
4416 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4418 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4422 case OP_CARD_TABLE_WBARRIER: {
4423 int ptr = ins->sreg1;
4424 int value = ins->sreg2;
4426 int nursery_shift, card_table_shift;
4427 gpointer card_table_mask;
4428 size_t nursery_size;
4429 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4430 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4431 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4434 * We need one register we can clobber, we choose EDX and make sreg1
4435 * fixed EAX to work around limitations in the local register allocator.
4436 * sreg2 might get allocated to EDX, but that is not a problem since
4437 * we use it before clobbering EDX.
4439 g_assert (ins->sreg1 == X86_EAX);
4442 * This is the code we produce:
4445 * edx >>= nursery_shift
4446 * cmp edx, (nursery_start >> nursery_shift)
4449 * edx >>= card_table_shift
4450 * card_table[edx] = 1
4454 if (card_table_nursery_check) {
4455 if (value != X86_EDX)
4456 x86_mov_reg_reg (code, X86_EDX, value, 4);
4457 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4458 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4459 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4461 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4462 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4463 if (card_table_mask)
4464 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4465 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4466 if (card_table_nursery_check)
4467 x86_patch (br, code);
4470 #ifdef MONO_ARCH_SIMD_INTRINSICS
4472 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4475 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4478 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4481 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4484 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4487 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4490 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4491 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4494 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4497 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4500 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4503 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4506 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4509 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4512 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4515 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4518 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4521 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4524 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4527 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4530 case OP_PSHUFLEW_HIGH:
4531 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4532 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4534 case OP_PSHUFLEW_LOW:
4535 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4536 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4539 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4540 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4543 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4544 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4547 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4548 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4552 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4555 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4558 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4561 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4564 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4567 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4570 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4571 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4574 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4577 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4580 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4583 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4586 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4589 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4592 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4595 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4598 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4601 case OP_EXTRACT_MASK:
4602 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4606 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4609 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4612 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4616 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4619 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4622 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4625 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4629 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4632 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4635 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4638 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4642 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4645 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4648 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4652 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4655 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4658 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4662 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4665 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4669 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4672 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4675 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4679 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4682 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4685 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4689 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4692 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4695 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4698 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4702 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4705 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4708 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4711 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4714 case OP_PSUM_ABS_DIFF:
4715 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4718 case OP_UNPACK_LOWB:
4719 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4721 case OP_UNPACK_LOWW:
4722 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4724 case OP_UNPACK_LOWD:
4725 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4727 case OP_UNPACK_LOWQ:
4728 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4730 case OP_UNPACK_LOWPS:
4731 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4733 case OP_UNPACK_LOWPD:
4734 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4737 case OP_UNPACK_HIGHB:
4738 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4740 case OP_UNPACK_HIGHW:
4741 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4743 case OP_UNPACK_HIGHD:
4744 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4746 case OP_UNPACK_HIGHQ:
4747 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4749 case OP_UNPACK_HIGHPS:
4750 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4752 case OP_UNPACK_HIGHPD:
4753 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4757 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4760 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4763 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4766 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4769 case OP_PADDB_SAT_UN:
4770 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4772 case OP_PSUBB_SAT_UN:
4773 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4775 case OP_PADDW_SAT_UN:
4776 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4778 case OP_PSUBW_SAT_UN:
4779 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4783 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4786 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4789 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4792 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4796 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4799 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4802 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4804 case OP_PMULW_HIGH_UN:
4805 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4808 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4812 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4815 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4819 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4822 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4826 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4829 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4833 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4836 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4840 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4843 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4847 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4850 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4854 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4857 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4861 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4864 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4868 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4871 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4875 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4877 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4878 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4882 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4884 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4885 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4889 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4891 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4892 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4896 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4898 case OP_EXTRACTX_U2:
4899 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4901 case OP_INSERTX_U1_SLOW:
4902 /*sreg1 is the extracted ireg (scratch)
4903 /sreg2 is the to be inserted ireg (scratch)
4904 /dreg is the xreg to receive the value*/
4906 /*clear the bits from the extracted word*/
4907 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4908 /*shift the value to insert if needed*/
4909 if (ins->inst_c0 & 1)
4910 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4911 /*join them together*/
4912 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4913 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4915 case OP_INSERTX_I4_SLOW:
4916 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4917 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4918 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4921 case OP_INSERTX_R4_SLOW:
4922 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4923 /*TODO if inst_c0 == 0 use movss*/
4924 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4925 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4927 case OP_INSERTX_R8_SLOW:
4928 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4929 if (cfg->verbose_level)
4930 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4932 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4934 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4937 case OP_STOREX_MEMBASE_REG:
4938 case OP_STOREX_MEMBASE:
4939 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4941 case OP_LOADX_MEMBASE:
4942 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4944 case OP_LOADX_ALIGNED_MEMBASE:
4945 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4947 case OP_STOREX_ALIGNED_MEMBASE_REG:
4948 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4950 case OP_STOREX_NTA_MEMBASE_REG:
4951 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4953 case OP_PREFETCH_MEMBASE:
4954 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4958 /*FIXME the peephole pass should have killed this*/
4959 if (ins->dreg != ins->sreg1)
4960 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4963 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4966 case OP_FCONV_TO_R8_X:
4967 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4968 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4971 case OP_XCONV_R8_TO_I4:
4972 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4973 switch (ins->backend.source_opcode) {
4974 case OP_FCONV_TO_I1:
4975 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4977 case OP_FCONV_TO_U1:
4978 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4980 case OP_FCONV_TO_I2:
4981 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4983 case OP_FCONV_TO_U2:
4984 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4990 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4991 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4992 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4993 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4994 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4995 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4998 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4999 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
5000 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5003 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
5004 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5007 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
5008 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5009 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5012 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
5013 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5014 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
5018 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
5021 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
5024 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
5027 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
5030 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
5033 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
5036 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
5039 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
5043 case OP_LIVERANGE_START: {
5044 if (cfg->verbose_level > 1)
5045 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5046 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5049 case OP_LIVERANGE_END: {
5050 if (cfg->verbose_level > 1)
5051 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5052 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5055 case OP_GC_SAFE_POINT: {
5056 const char *polling_func = NULL;
5057 int compare_val = 0;
5060 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
5061 polling_func = "mono_nacl_gc";
5062 compare_val = 0xFFFFFFFF;
5064 g_assert (mono_threads_is_coop_enabled ());
5065 polling_func = "mono_threads_state_poll";
5069 x86_test_membase_imm (code, ins->sreg1, 0, compare_val);
5070 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
5071 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func);
5072 x86_patch (br [0], code);
5076 case OP_GC_LIVENESS_DEF:
5077 case OP_GC_LIVENESS_USE:
5078 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5079 ins->backend.pc_offset = code - cfg->native_code;
5081 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5082 ins->backend.pc_offset = code - cfg->native_code;
5083 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5086 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
5089 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
5092 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
5093 g_assert_not_reached ();
5096 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
5097 #ifndef __native_client_codegen__
5098 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5099 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5100 g_assert_not_reached ();
5101 #endif /* __native_client_codegen__ */
5107 cfg->code_len = code - cfg->native_code;
5110 #endif /* DISABLE_JIT */
5113 mono_arch_register_lowlevel_calls (void)
5118 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
5120 unsigned char *ip = ji->ip.i + code;
5123 case MONO_PATCH_INFO_IP:
5124 *((gconstpointer *)(ip)) = target;
5126 case MONO_PATCH_INFO_ABS:
5127 case MONO_PATCH_INFO_METHOD:
5128 case MONO_PATCH_INFO_METHOD_JUMP:
5129 case MONO_PATCH_INFO_INTERNAL_METHOD:
5130 case MONO_PATCH_INFO_BB:
5131 case MONO_PATCH_INFO_LABEL:
5132 case MONO_PATCH_INFO_RGCTX_FETCH:
5133 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5134 #if defined(__native_client_codegen__) && defined(__native_client__)
5135 if (nacl_is_code_address (code)) {
5136 /* For tail calls, code is patched after being installed */
5137 /* but not through the normal "patch callsite" method. */
5138 unsigned char buf[kNaClAlignment];
5139 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5140 unsigned char *_target = target;
5142 /* All patch targets modified in x86_patch */
5143 /* are IP relative. */
5144 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5145 memcpy (buf, aligned_code, kNaClAlignment);
5146 /* Patch a temp buffer of bundle size, */
5147 /* then install to actual location. */
5148 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5149 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5150 g_assert (ret == 0);
5153 x86_patch (ip, (unsigned char*)target);
5156 x86_patch (ip, (unsigned char*)target);
5159 case MONO_PATCH_INFO_NONE:
5161 case MONO_PATCH_INFO_R4:
5162 case MONO_PATCH_INFO_R8: {
5163 guint32 offset = mono_arch_get_patch_offset (ip);
5164 *((gconstpointer *)(ip + offset)) = target;
5168 guint32 offset = mono_arch_get_patch_offset (ip);
5169 #if !defined(__native_client__)
5170 *((gconstpointer *)(ip + offset)) = target;
5172 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5179 static G_GNUC_UNUSED void
5180 stack_unaligned (MonoMethod *m, gpointer caller)
5182 printf ("%s\n", mono_method_full_name (m, TRUE));
5183 g_assert_not_reached ();
5187 mono_arch_emit_prolog (MonoCompile *cfg)
5189 MonoMethod *method = cfg->method;
5191 MonoMethodSignature *sig;
5193 int alloc_size, pos, max_offset, i, cfa_offset;
5195 gboolean need_stack_frame;
5196 #ifdef __native_client_codegen__
5197 guint alignment_check;
5200 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5202 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5203 cfg->code_size += 512;
5205 #if defined(__default_codegen__)
5206 code = cfg->native_code = g_malloc (cfg->code_size);
5207 #elif defined(__native_client_codegen__)
5208 /* native_code_alloc is not 32-byte aligned, native_code is. */
5209 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5210 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5212 /* Align native_code to next nearest kNaclAlignment byte. */
5213 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5214 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5216 code = cfg->native_code;
5218 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5219 g_assert(alignment_check == 0);
5226 /* Check that the stack is aligned on osx */
5227 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5228 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5229 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5231 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5232 x86_push_membase (code, X86_ESP, 0);
5233 x86_push_imm (code, cfg->method);
5234 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5235 x86_call_reg (code, X86_EAX);
5236 x86_patch (br [0], code);
5240 /* Offset between RSP and the CFA */
5244 cfa_offset = sizeof (gpointer);
5245 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5246 // IP saved at CFA - 4
5247 /* There is no IP reg on x86 */
5248 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5249 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5251 need_stack_frame = needs_stack_frame (cfg);
5253 if (need_stack_frame) {
5254 x86_push_reg (code, X86_EBP);
5255 cfa_offset += sizeof (gpointer);
5256 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5257 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5258 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5259 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5260 /* These are handled automatically by the stack marking code */
5261 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5263 cfg->frame_reg = X86_ESP;
5266 cfg->stack_offset += cfg->param_area;
5267 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5269 alloc_size = cfg->stack_offset;
5272 if (!method->save_lmf) {
5273 if (cfg->used_int_regs & (1 << X86_EBX)) {
5274 x86_push_reg (code, X86_EBX);
5276 cfa_offset += sizeof (gpointer);
5277 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5278 /* These are handled automatically by the stack marking code */
5279 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5282 if (cfg->used_int_regs & (1 << X86_EDI)) {
5283 x86_push_reg (code, X86_EDI);
5285 cfa_offset += sizeof (gpointer);
5286 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5287 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5290 if (cfg->used_int_regs & (1 << X86_ESI)) {
5291 x86_push_reg (code, X86_ESI);
5293 cfa_offset += sizeof (gpointer);
5294 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5295 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5301 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5302 if (mono_do_x86_stack_align && need_stack_frame) {
5303 int tot = alloc_size + pos + 4; /* ret ip */
5304 if (need_stack_frame)
5306 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5308 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5309 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5310 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5314 cfg->arch.sp_fp_offset = alloc_size + pos;
5317 /* See mono_emit_stack_alloc */
5318 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5319 guint32 remaining_size = alloc_size;
5320 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5321 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5322 guint32 offset = code - cfg->native_code;
5323 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5324 while (required_code_size >= (cfg->code_size - offset))
5325 cfg->code_size *= 2;
5326 cfg->native_code = mono_realloc_native_code(cfg);
5327 code = cfg->native_code + offset;
5328 cfg->stat_code_reallocs++;
5330 while (remaining_size >= 0x1000) {
5331 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5332 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5333 remaining_size -= 0x1000;
5336 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5338 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5341 g_assert (need_stack_frame);
5344 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5345 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5346 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5349 #if DEBUG_STACK_ALIGNMENT
5350 /* check the stack is aligned */
5351 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5352 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5353 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5354 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5355 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5356 x86_breakpoint (code);
5360 /* compute max_offset in order to use short forward jumps */
5362 if (cfg->opt & MONO_OPT_BRANCH) {
5363 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5365 bb->max_offset = max_offset;
5367 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5369 /* max alignment for loops */
5370 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5371 max_offset += LOOP_ALIGNMENT;
5372 #ifdef __native_client_codegen__
5373 /* max alignment for native client */
5374 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5375 max_offset += kNaClAlignment;
5377 MONO_BB_FOR_EACH_INS (bb, ins) {
5378 if (ins->opcode == OP_LABEL)
5379 ins->inst_c1 = max_offset;
5380 #ifdef __native_client_codegen__
5381 switch (ins->opcode)
5393 case OP_VOIDCALL_REG:
5395 case OP_FCALL_MEMBASE:
5396 case OP_LCALL_MEMBASE:
5397 case OP_VCALL_MEMBASE:
5398 case OP_VCALL2_MEMBASE:
5399 case OP_VOIDCALL_MEMBASE:
5400 case OP_CALL_MEMBASE:
5401 max_offset += kNaClAlignment;
5404 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5407 #endif /* __native_client_codegen__ */
5408 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5413 /* store runtime generic context */
5414 if (cfg->rgctx_var) {
5415 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5417 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5420 if (method->save_lmf)
5421 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5423 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5424 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5429 if (cfg->arch.ss_tramp_var) {
5430 /* Initialize ss_tramp_var */
5431 ins = cfg->arch.ss_tramp_var;
5432 g_assert (ins->opcode == OP_REGOFFSET);
5434 g_assert (!cfg->compile_aot);
5435 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&ss_trampoline, 4);
5438 if (cfg->arch.bp_tramp_var) {
5439 /* Initialize bp_tramp_var */
5440 ins = cfg->arch.bp_tramp_var;
5441 g_assert (ins->opcode == OP_REGOFFSET);
5443 g_assert (!cfg->compile_aot);
5444 x86_mov_membase_imm (code, ins->inst_basereg, ins->inst_offset, (guint32)&bp_trampoline, 4);
5448 /* load arguments allocated to register from the stack */
5449 sig = mono_method_signature (method);
5452 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5453 inst = cfg->args [pos];
5454 if (inst->opcode == OP_REGVAR) {
5455 g_assert (need_stack_frame);
5456 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5457 if (cfg->verbose_level > 2)
5458 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5463 cfg->code_len = code - cfg->native_code;
5465 g_assert (cfg->code_len < cfg->code_size);
5471 mono_arch_emit_epilog (MonoCompile *cfg)
5473 MonoMethod *method = cfg->method;
5474 MonoMethodSignature *sig = mono_method_signature (method);
5476 guint32 stack_to_pop;
5478 int max_epilog_size = 16;
5480 gboolean need_stack_frame = needs_stack_frame (cfg);
5482 if (cfg->method->save_lmf)
5483 max_epilog_size += 128;
5485 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5486 cfg->code_size *= 2;
5487 cfg->native_code = mono_realloc_native_code(cfg);
5488 cfg->stat_code_reallocs++;
5491 code = cfg->native_code + cfg->code_len;
5493 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5494 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5496 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5499 if (method->save_lmf) {
5500 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5502 gboolean supported = FALSE;
5504 if (cfg->compile_aot) {
5505 #if defined(MONO_HAVE_FAST_TLS)
5508 } else if (mono_get_jit_tls_offset () != -1) {
5512 /* check if we need to restore protection of the stack after a stack overflow */
5514 if (cfg->compile_aot) {
5515 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5517 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5519 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5522 /* we load the value in a separate instruction: this mechanism may be
5523 * used later as a safer way to do thread interruption
5525 x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5526 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5528 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5529 /* note that the call trampoline will preserve eax/edx */
5530 x86_call_reg (code, X86_ECX);
5531 x86_patch (patch, code);
5533 /* FIXME: maybe save the jit tls in the prolog */
5536 /* restore caller saved regs */
5537 if (cfg->used_int_regs & (1 << X86_EBX)) {
5538 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5541 if (cfg->used_int_regs & (1 << X86_EDI)) {
5542 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5544 if (cfg->used_int_regs & (1 << X86_ESI)) {
5545 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5548 /* EBP is restored by LEAVE */
5550 for (i = 0; i < X86_NREG; ++i) {
5551 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5557 g_assert (need_stack_frame);
5558 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5562 g_assert (need_stack_frame);
5563 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5566 if (cfg->used_int_regs & (1 << X86_ESI)) {
5567 x86_pop_reg (code, X86_ESI);
5569 if (cfg->used_int_regs & (1 << X86_EDI)) {
5570 x86_pop_reg (code, X86_EDI);
5572 if (cfg->used_int_regs & (1 << X86_EBX)) {
5573 x86_pop_reg (code, X86_EBX);
5577 /* Load returned vtypes into registers if needed */
5578 cinfo = get_call_info (cfg->mempool, sig);
5579 if (cinfo->ret.storage == ArgValuetypeInReg) {
5580 for (quad = 0; quad < 2; quad ++) {
5581 switch (cinfo->ret.pair_storage [quad]) {
5583 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5585 case ArgOnFloatFpStack:
5586 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5588 case ArgOnDoubleFpStack:
5589 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5594 g_assert_not_reached ();
5599 if (need_stack_frame)
5602 if (CALLCONV_IS_STDCALL (sig)) {
5603 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5605 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
5606 } else if (cinfo->callee_stack_pop)
5607 stack_to_pop = cinfo->callee_stack_pop;
5612 g_assert (need_stack_frame);
5613 x86_ret_imm (code, stack_to_pop);
5618 cfg->code_len = code - cfg->native_code;
5620 g_assert (cfg->code_len < cfg->code_size);
5624 mono_arch_emit_exceptions (MonoCompile *cfg)
5626 MonoJumpInfo *patch_info;
5629 MonoClass *exc_classes [16];
5630 guint8 *exc_throw_start [16], *exc_throw_end [16];
5634 /* Compute needed space */
5635 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5636 if (patch_info->type == MONO_PATCH_INFO_EXC)
5641 * make sure we have enough space for exceptions
5642 * 16 is the size of two push_imm instructions and a call
5644 if (cfg->compile_aot)
5645 code_size = exc_count * 32;
5647 code_size = exc_count * 16;
5649 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5650 cfg->code_size *= 2;
5651 cfg->native_code = mono_realloc_native_code(cfg);
5652 cfg->stat_code_reallocs++;
5655 code = cfg->native_code + cfg->code_len;
5658 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5659 switch (patch_info->type) {
5660 case MONO_PATCH_INFO_EXC: {
5661 MonoClass *exc_class;
5665 x86_patch (patch_info->ip.i + cfg->native_code, code);
5667 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5668 throw_ip = patch_info->ip.i;
5670 /* Find a throw sequence for the same exception class */
5671 for (i = 0; i < nthrows; ++i)
5672 if (exc_classes [i] == exc_class)
5675 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5676 x86_jump_code (code, exc_throw_start [i]);
5677 patch_info->type = MONO_PATCH_INFO_NONE;
5682 /* Compute size of code following the push <OFFSET> */
5683 #if defined(__default_codegen__)
5685 #elif defined(__native_client_codegen__)
5686 code = mono_nacl_align (code);
5687 size = kNaClAlignment;
5689 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5691 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5692 /* Use the shorter form */
5694 x86_push_imm (code, 0);
5698 x86_push_imm (code, 0xf0f0f0f0);
5703 exc_classes [nthrows] = exc_class;
5704 exc_throw_start [nthrows] = code;
5707 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5708 patch_info->data.name = "mono_arch_throw_corlib_exception";
5709 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5710 patch_info->ip.i = code - cfg->native_code;
5711 x86_call_code (code, 0);
5712 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5717 exc_throw_end [nthrows] = code;
5729 cfg->code_len = code - cfg->native_code;
5731 g_assert (cfg->code_len < cfg->code_size);
5735 mono_arch_flush_icache (guint8 *code, gint size)
5741 mono_arch_flush_register_windows (void)
5746 mono_arch_is_inst_imm (gint64 imm)
5752 mono_arch_finish_init (void)
5754 if (!g_getenv ("MONO_NO_TLS")) {
5755 #ifndef TARGET_WIN32
5757 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5764 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5768 // Linear handler, the bsearch head compare is shorter
5769 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5770 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5771 // x86_patch(ins,target)
5772 //[1 + 5] x86_jump_mem(inst,mem)
5775 #if defined(__default_codegen__)
5776 #define BR_SMALL_SIZE 2
5777 #define BR_LARGE_SIZE 5
5778 #elif defined(__native_client_codegen__)
5779 /* I suspect the size calculation below is actually incorrect. */
5780 /* TODO: fix the calculation that uses these sizes. */
5781 #define BR_SMALL_SIZE 16
5782 #define BR_LARGE_SIZE 12
5783 #endif /*__native_client_codegen__*/
5784 #define JUMP_IMM_SIZE 6
5785 #define ENABLE_WRONG_METHOD_CHECK 0
5789 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5791 int i, distance = 0;
5792 for (i = start; i < target; ++i)
5793 distance += imt_entries [i]->chunk_size;
5798 * LOCKING: called with the domain lock held
5801 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5802 gpointer fail_tramp)
5806 guint8 *code, *start;
5809 for (i = 0; i < count; ++i) {
5810 MonoIMTCheckItem *item = imt_entries [i];
5811 if (item->is_equals) {
5812 if (item->check_target_idx) {
5813 if (!item->compare_done)
5814 item->chunk_size += CMP_SIZE;
5815 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5818 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5820 item->chunk_size += JUMP_IMM_SIZE;
5821 #if ENABLE_WRONG_METHOD_CHECK
5822 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5827 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5828 imt_entries [item->check_target_idx]->compare_done = TRUE;
5830 size += item->chunk_size;
5832 #if defined(__native_client__) && defined(__native_client_codegen__)
5833 /* In Native Client, we don't re-use thunks, allocate from the */
5834 /* normal code manager paths. */
5835 size = NACL_BUNDLE_ALIGN_UP (size);
5836 code = mono_domain_code_reserve (domain, size);
5839 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5841 code = mono_domain_code_reserve (domain, size);
5845 unwind_ops = mono_arch_get_cie_program ();
5847 for (i = 0; i < count; ++i) {
5848 MonoIMTCheckItem *item = imt_entries [i];
5849 item->code_target = code;
5850 if (item->is_equals) {
5851 if (item->check_target_idx) {
5852 if (!item->compare_done)
5853 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5854 item->jmp_code = code;
5855 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5856 if (item->has_target_code)
5857 x86_jump_code (code, item->value.target_code);
5859 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5862 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5863 item->jmp_code = code;
5864 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5865 if (item->has_target_code)
5866 x86_jump_code (code, item->value.target_code);
5868 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5869 x86_patch (item->jmp_code, code);
5870 x86_jump_code (code, fail_tramp);
5871 item->jmp_code = NULL;
5873 /* enable the commented code to assert on wrong method */
5874 #if ENABLE_WRONG_METHOD_CHECK
5875 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5876 item->jmp_code = code;
5877 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5879 if (item->has_target_code)
5880 x86_jump_code (code, item->value.target_code);
5882 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5883 #if ENABLE_WRONG_METHOD_CHECK
5884 x86_patch (item->jmp_code, code);
5885 x86_breakpoint (code);
5886 item->jmp_code = NULL;
5891 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5892 item->jmp_code = code;
5893 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5894 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5896 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5899 /* patch the branches to get to the target items */
5900 for (i = 0; i < count; ++i) {
5901 MonoIMTCheckItem *item = imt_entries [i];
5902 if (item->jmp_code) {
5903 if (item->check_target_idx) {
5904 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5910 mono_stats.imt_thunks_size += code - start;
5911 g_assert (code - start <= size);
5915 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5916 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5920 if (mono_jit_map_is_enabled ()) {
5923 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5925 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5926 mono_emit_jit_tramp (start, code - start, buff);
5930 nacl_domain_code_validate (domain, &start, size, &code);
5931 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
5933 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
5939 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5941 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5945 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5947 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5951 mono_arch_get_cie_program (void)
5955 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5956 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5962 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5964 MonoInst *ins = NULL;
5967 if (cmethod->klass == mono_defaults.math_class) {
5968 if (strcmp (cmethod->name, "Sin") == 0) {
5970 } else if (strcmp (cmethod->name, "Cos") == 0) {
5972 } else if (strcmp (cmethod->name, "Tan") == 0) {
5974 } else if (strcmp (cmethod->name, "Atan") == 0) {
5976 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5978 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5980 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5984 if (opcode && fsig->param_count == 1) {
5985 MONO_INST_NEW (cfg, ins, opcode);
5986 ins->type = STACK_R8;
5987 ins->dreg = mono_alloc_freg (cfg);
5988 ins->sreg1 = args [0]->dreg;
5989 MONO_ADD_INS (cfg->cbb, ins);
5992 if (cfg->opt & MONO_OPT_CMOV) {
5995 if (strcmp (cmethod->name, "Min") == 0) {
5996 if (fsig->params [0]->type == MONO_TYPE_I4)
5998 } else if (strcmp (cmethod->name, "Max") == 0) {
5999 if (fsig->params [0]->type == MONO_TYPE_I4)
6003 if (opcode && fsig->param_count == 2) {
6004 MONO_INST_NEW (cfg, ins, opcode);
6005 ins->type = STACK_I4;
6006 ins->dreg = mono_alloc_ireg (cfg);
6007 ins->sreg1 = args [0]->dreg;
6008 ins->sreg2 = args [1]->dreg;
6009 MONO_ADD_INS (cfg->cbb, ins);
6014 /* OP_FREM is not IEEE compatible */
6015 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
6016 MONO_INST_NEW (cfg, ins, OP_FREM);
6017 ins->inst_i0 = args [0];
6018 ins->inst_i1 = args [1];
6027 mono_arch_print_tree (MonoInst *tree, int arity)
6033 mono_arch_get_patch_offset (guint8 *code)
6035 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
6037 else if (code [0] == 0xba)
6039 else if (code [0] == 0x68)
6042 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
6043 /* push <OFFSET>(<REG>) */
6045 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
6046 /* call *<OFFSET>(<REG>) */
6048 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
6051 else if ((code [0] == 0x58) && (code [1] == 0x05))
6052 /* pop %eax; add <OFFSET>, %eax */
6054 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6055 /* pop <REG>; add <OFFSET>, <REG> */
6057 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6058 /* mov <REG>, imm */
6061 g_assert_not_reached ();
6067 * mono_breakpoint_clean_code:
6069 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6070 * breakpoints in the original code, they are removed in the copy.
6072 * Returns TRUE if no sw breakpoint was present.
6075 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6078 * If method_start is non-NULL we need to perform bound checks, since we access memory
6079 * at code - offset we could go before the start of the method and end up in a different
6080 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6083 if (!method_start || code - offset >= method_start) {
6084 memcpy (buf, code - offset, size);
6086 int diff = code - method_start;
6087 memset (buf, 0, size);
6088 memcpy (buf + offset - diff, method_start, diff + size - offset);
6094 * mono_x86_get_this_arg_offset:
6096 * Return the offset of the stack location where this is passed during a virtual
6100 mono_x86_get_this_arg_offset (MonoMethodSignature *sig)
6106 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6108 guint32 esp = regs [X86_ESP];
6115 * The stack looks like:
6119 res = ((MonoObject**)esp) [0];
6123 #define MAX_ARCH_DELEGATE_PARAMS 10
6126 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
6128 guint8 *code, *start;
6129 int code_reserve = 64;
6132 unwind_ops = mono_arch_get_cie_program ();
6135 * The stack contains:
6141 start = code = mono_global_codeman_reserve (code_reserve);
6143 /* Replace the this argument with the target */
6144 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6145 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6146 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6147 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6149 g_assert ((code - start) < code_reserve);
6152 /* 8 for mov_reg and jump, plus 8 for each parameter */
6153 #ifdef __native_client_codegen__
6154 /* TODO: calculate this size correctly */
6155 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6157 code_reserve = 8 + (param_count * 8);
6158 #endif /* __native_client_codegen__ */
6160 * The stack contains:
6161 * <args in reverse order>
6166 * <args in reverse order>
6169 * without unbalancing the stack.
6170 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6171 * and leaving original spot of first arg as placeholder in stack so
6172 * when callee pops stack everything works.
6175 start = code = mono_global_codeman_reserve (code_reserve);
6177 /* store delegate for access to method_ptr */
6178 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6181 for (i = 0; i < param_count; ++i) {
6182 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6183 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6186 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6188 g_assert ((code - start) < code_reserve);
6191 nacl_global_codeman_validate (&start, code_reserve, &code);
6194 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
6196 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
6197 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
6201 if (mono_jit_map_is_enabled ()) {
6204 buff = (char*)"delegate_invoke_has_target";
6206 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6207 mono_emit_jit_tramp (start, code - start, buff);
6211 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6216 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
6219 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
6221 guint8 *code, *start;
6226 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
6230 * The stack contains:
6234 start = code = mono_global_codeman_reserve (size);
6236 unwind_ops = mono_arch_get_cie_program ();
6238 /* Replace the this argument with the target */
6239 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6240 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6241 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6244 /* Load the IMT reg */
6245 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
6248 /* Load the vtable */
6249 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
6250 x86_jump_membase (code, X86_EAX, offset);
6251 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6254 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
6256 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
6257 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
6258 g_free (tramp_name);
6265 mono_arch_get_delegate_invoke_impls (void)
6268 MonoTrampInfo *info;
6271 get_delegate_invoke_impl (&info, TRUE, 0);
6272 res = g_slist_prepend (res, info);
6274 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
6275 get_delegate_invoke_impl (&info, FALSE, i);
6276 res = g_slist_prepend (res, info);
6279 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
6280 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
6281 res = g_slist_prepend (res, info);
6283 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
6284 res = g_slist_prepend (res, info);
6291 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6293 guint8 *code, *start;
6295 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6298 /* FIXME: Support more cases */
6299 if (MONO_TYPE_ISSTRUCT (sig->ret))
6303 * The stack contains:
6309 static guint8* cached = NULL;
6313 if (mono_aot_only) {
6314 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6316 MonoTrampInfo *info;
6317 start = get_delegate_invoke_impl (&info, TRUE, 0);
6318 mono_tramp_info_register (info, NULL);
6321 mono_memory_barrier ();
6325 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6328 for (i = 0; i < sig->param_count; ++i)
6329 if (!mono_is_regsize_var (sig->params [i]))
6332 code = cache [sig->param_count];
6336 if (mono_aot_only) {
6337 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6338 start = mono_aot_get_trampoline (name);
6341 MonoTrampInfo *info;
6342 start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
6343 mono_tramp_info_register (info, NULL);
6346 mono_memory_barrier ();
6348 cache [sig->param_count] = start;
6355 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
6357 MonoTrampInfo *info;
6360 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
6362 mono_tramp_info_register (info, NULL);
6367 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6370 case X86_EAX: return ctx->eax;
6371 case X86_EBX: return ctx->ebx;
6372 case X86_ECX: return ctx->ecx;
6373 case X86_EDX: return ctx->edx;
6374 case X86_ESP: return ctx->esp;
6375 case X86_EBP: return ctx->ebp;
6376 case X86_ESI: return ctx->esi;
6377 case X86_EDI: return ctx->edi;
6379 g_assert_not_reached ();
6385 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6413 g_assert_not_reached ();
6417 #ifdef MONO_ARCH_SIMD_INTRINSICS
6420 get_float_to_x_spill_area (MonoCompile *cfg)
6422 if (!cfg->fconv_to_r8_x_var) {
6423 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6424 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6426 return cfg->fconv_to_r8_x_var;
6430 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6433 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6436 int dreg, src_opcode;
6438 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6441 switch (src_opcode = ins->opcode) {
6442 case OP_FCONV_TO_I1:
6443 case OP_FCONV_TO_U1:
6444 case OP_FCONV_TO_I2:
6445 case OP_FCONV_TO_U2:
6446 case OP_FCONV_TO_I4:
6453 /* dreg is the IREG and sreg1 is the FREG */
6454 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6455 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6456 fconv->sreg1 = ins->sreg1;
6457 fconv->dreg = mono_alloc_ireg (cfg);
6458 fconv->type = STACK_VTYPE;
6459 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6461 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6465 ins->opcode = OP_XCONV_R8_TO_I4;
6467 ins->klass = mono_defaults.int32_class;
6468 ins->sreg1 = fconv->dreg;
6470 ins->type = STACK_I4;
6471 ins->backend.source_opcode = src_opcode;
6474 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6477 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6482 if (long_ins->opcode == OP_LNEG) {
6484 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_LS (ins->dreg), MONO_LVREG_LS (ins->sreg1));
6485 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->sreg1), 0);
6486 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, MONO_LVREG_MS (ins->dreg), MONO_LVREG_MS (ins->dreg));
6491 #ifdef MONO_ARCH_SIMD_INTRINSICS
6493 if (!(cfg->opt & MONO_OPT_SIMD))
6496 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6497 switch (long_ins->opcode) {
6499 vreg = long_ins->sreg1;
6501 if (long_ins->inst_c0) {
6502 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6503 ins->klass = long_ins->klass;
6504 ins->sreg1 = long_ins->sreg1;
6506 ins->type = STACK_VTYPE;
6507 ins->dreg = vreg = alloc_ireg (cfg);
6508 MONO_ADD_INS (cfg->cbb, ins);
6511 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6512 ins->klass = mono_defaults.int32_class;
6514 ins->type = STACK_I4;
6515 ins->dreg = MONO_LVREG_LS (long_ins->dreg);
6516 MONO_ADD_INS (cfg->cbb, ins);
6518 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6519 ins->klass = long_ins->klass;
6520 ins->sreg1 = long_ins->sreg1;
6521 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6522 ins->type = STACK_VTYPE;
6523 ins->dreg = vreg = alloc_ireg (cfg);
6524 MONO_ADD_INS (cfg->cbb, ins);
6526 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6527 ins->klass = mono_defaults.int32_class;
6529 ins->type = STACK_I4;
6530 ins->dreg = MONO_LVREG_MS (long_ins->dreg);
6531 MONO_ADD_INS (cfg->cbb, ins);
6533 long_ins->opcode = OP_NOP;
6535 case OP_INSERTX_I8_SLOW:
6536 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6537 ins->dreg = long_ins->dreg;
6538 ins->sreg1 = long_ins->dreg;
6539 ins->sreg2 = MONO_LVREG_LS (long_ins->sreg2);
6540 ins->inst_c0 = long_ins->inst_c0 * 2;
6541 MONO_ADD_INS (cfg->cbb, ins);
6543 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6544 ins->dreg = long_ins->dreg;
6545 ins->sreg1 = long_ins->dreg;
6546 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg2);
6547 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6548 MONO_ADD_INS (cfg->cbb, ins);
6550 long_ins->opcode = OP_NOP;
6553 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6554 ins->dreg = long_ins->dreg;
6555 ins->sreg1 = MONO_LVREG_LS (long_ins->sreg1);
6556 ins->klass = long_ins->klass;
6557 ins->type = STACK_VTYPE;
6558 MONO_ADD_INS (cfg->cbb, ins);
6560 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6561 ins->dreg = long_ins->dreg;
6562 ins->sreg1 = long_ins->dreg;
6563 ins->sreg2 = MONO_LVREG_MS (long_ins->sreg1);
6565 ins->klass = long_ins->klass;
6566 ins->type = STACK_VTYPE;
6567 MONO_ADD_INS (cfg->cbb, ins);
6569 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6570 ins->dreg = long_ins->dreg;
6571 ins->sreg1 = long_ins->dreg;;
6572 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6573 ins->klass = long_ins->klass;
6574 ins->type = STACK_VTYPE;
6575 MONO_ADD_INS (cfg->cbb, ins);
6577 long_ins->opcode = OP_NOP;
6580 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6583 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6585 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6588 gpointer *sp, old_value;
6591 offset = clause->exvar_offset;
6594 bp = MONO_CONTEXT_GET_BP (ctx);
6595 sp = *(gpointer*)(bp + offset);
6598 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6607 * mono_aot_emit_load_got_addr:
6609 * Emit code to load the got address.
6610 * On x86, the result is placed into EBX.
6613 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6615 x86_call_imm (code, 0);
6617 * The patch needs to point to the pop, since the GOT offset needs
6618 * to be added to that address.
6621 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6623 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6624 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6625 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6631 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6634 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6636 g_assert_not_reached ();
6637 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6642 * mono_arch_emit_load_aotconst:
6644 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6645 * TARGET from the mscorlib GOT in full-aot code.
6646 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6650 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
6652 /* Load the mscorlib got address */
6653 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6654 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6655 /* arch_emit_got_access () patches this */
6656 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6661 /* Can't put this into mini-x86.h */
6663 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6666 mono_arch_get_trampolines (gboolean aot)
6668 MonoTrampInfo *info;
6669 GSList *tramps = NULL;
6671 mono_x86_get_signal_exception_trampoline (&info, aot);
6673 tramps = g_slist_append (tramps, info);
6678 /* Soft Debug support */
6679 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6682 * mono_arch_set_breakpoint:
6684 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6685 * The location should contain code emitted by OP_SEQ_POINT.
6688 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6690 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6692 g_assert (code [0] == 0x90);
6693 x86_call_membase (code, X86_ECX, 0);
6697 * mono_arch_clear_breakpoint:
6699 * Clear the breakpoint at IP.
6702 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6704 guint8 *code = ip + OP_SEQ_POINT_BP_OFFSET;
6707 for (i = 0; i < 2; ++i)
6712 * mono_arch_start_single_stepping:
6714 * Start single stepping.
6717 mono_arch_start_single_stepping (void)
6719 ss_trampoline = mini_get_single_step_trampoline ();
6723 * mono_arch_stop_single_stepping:
6725 * Stop single stepping.
6728 mono_arch_stop_single_stepping (void)
6730 ss_trampoline = NULL;
6734 * mono_arch_is_single_step_event:
6736 * Return whenever the machine state in SIGCTX corresponds to a single
6740 mono_arch_is_single_step_event (void *info, void *sigctx)
6742 /* We use soft breakpoints */
6747 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6749 /* We use soft breakpoints */
6753 #define BREAKPOINT_SIZE 2
6756 * mono_arch_skip_breakpoint:
6758 * See mini-amd64.c for docs.
6761 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6763 g_assert_not_reached ();
6767 * mono_arch_skip_single_step:
6769 * See mini-amd64.c for docs.
6772 mono_arch_skip_single_step (MonoContext *ctx)
6774 g_assert_not_reached ();
6778 * mono_arch_get_seq_point_info:
6780 * See mini-amd64.c for docs.
6783 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6790 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6792 ext->lmf.previous_lmf = (gsize)prev_lmf;
6793 /* Mark that this is a MonoLMFExt */
6794 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6795 ext->lmf.ebp = (gssize)ext;
6801 mono_arch_opcode_supported (int opcode)
6804 case OP_ATOMIC_ADD_I4:
6805 case OP_ATOMIC_EXCHANGE_I4:
6806 case OP_ATOMIC_CAS_I4:
6807 case OP_ATOMIC_LOAD_I1:
6808 case OP_ATOMIC_LOAD_I2:
6809 case OP_ATOMIC_LOAD_I4:
6810 case OP_ATOMIC_LOAD_U1:
6811 case OP_ATOMIC_LOAD_U2:
6812 case OP_ATOMIC_LOAD_U4:
6813 case OP_ATOMIC_LOAD_R4:
6814 case OP_ATOMIC_LOAD_R8:
6815 case OP_ATOMIC_STORE_I1:
6816 case OP_ATOMIC_STORE_I2:
6817 case OP_ATOMIC_STORE_I4:
6818 case OP_ATOMIC_STORE_U1:
6819 case OP_ATOMIC_STORE_U2:
6820 case OP_ATOMIC_STORE_U4:
6821 case OP_ATOMIC_STORE_R4:
6822 case OP_ATOMIC_STORE_R8:
6829 #if defined(ENABLE_GSHAREDVT)
6831 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6833 #endif /* !MONOTOUCH */