mono/mini/mini-x86.c

   1 /*
   2  * mini-x86.c: x86 backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Paolo Molaro (lupus@ximian.com)
   6  *   Dietmar Maurer (dietmar@ximian.com)
   7  *   Patrik Torstensson
   8  *
   9  * (C) 2003 Ximian, Inc.
  10  */
  11 #include "mini.h"
  12 #include <string.h>
  13 #include <math.h>
  14
  15 #include <mono/metadata/appdomain.h>
  16 #include <mono/metadata/debug-helpers.h>
  17 #include <mono/metadata/profiler-private.h>
  18 #include <mono/utils/mono-math.h>
  19
  20 #include "trace.h"
  21 #include "mini-x86.h"
  22 #include "inssel.h"
  23 #include "cpu-pentium.h"
  24
  25 static gint lmf_tls_offset = -1;
  26
  27 #ifdef PLATFORM_WIN32
  28 /* Under windows, the default pinvoke calling convention is stdcall */
  29 #define CALLCONV_IS_STDCALL(call_conv) (((call_conv) == MONO_CALL_STDCALL) || ((call_conv) == MONO_CALL_DEFAULT))
  30 #else
  31 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  32 #endif
  33
  34 #define SIGNAL_STACK_SIZE (64 * 1024)
  35
  36 static gpointer mono_arch_get_lmf_addr (void);
  37
  38 const char*
  39 mono_arch_regname (int reg) {
  40         switch (reg) {
  41         case X86_EAX: return "%eax";
  42         case X86_EBX: return "%ebx";
  43         case X86_ECX: return "%ecx";
  44         case X86_EDX: return "%edx";
  45         case X86_ESP: return "%esp";    case X86_EBP: return "%ebp";
  46         case X86_EDI: return "%edi";
  47         case X86_ESI: return "%esi";
  48         }
  49         return "unknown";
  50 }
  51
  52 /*
  53  * mono_arch_get_argument_info:
  54  * @csig:  a method signature
  55  * @param_count: the number of parameters to consider
  56  * @arg_info: an array to store the result infos
  57  *
  58  * Gathers information on parameters such as size, alignment and
  59  * padding. arg_info should be large enought to hold param_count + 1 entries.
  60  *
  61  * Returns the size of the activation frame.
  62  */
  63 int
  64 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
  65 {
  66         int k, frame_size = 0;
  67         int size, align, pad;
  68         int offset = 8;
  69
  70         if (MONO_TYPE_ISSTRUCT (csig->ret)) {
  71                 frame_size += sizeof (gpointer);
  72                 offset += 4;
  73         }
  74
  75         arg_info [0].offset = offset;
  76
  77         if (csig->hasthis) {
  78                 frame_size += sizeof (gpointer);
  79                 offset += 4;
  80         }
  81
  82         arg_info [0].size = frame_size;
  83
  84         for (k = 0; k < param_count; k++) {
  85
  86                 if (csig->pinvoke)
  87                         size = mono_type_native_stack_size (csig->params [k], &align);
  88                 else
  89                         size = mono_type_stack_size (csig->params [k], &align);
  90
  91                 /* ignore alignment for now */
  92                 align = 1;
  93
  94                 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
  95                 arg_info [k].pad = pad;
  96                 frame_size += size;
  97                 arg_info [k + 1].pad = 0;
  98                 arg_info [k + 1].size = size;
  99                 offset += pad;
 100                 arg_info [k + 1].offset = offset;
 101                 offset += size;
 102         }
 103
 104         align = MONO_ARCH_FRAME_ALIGNMENT;
 105         frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
 106         arg_info [k].pad = pad;
 107
 108         return frame_size;
 109 }
 110
 111 static const guchar cpuid_impl [] = {
 112         0x55,                           /* push   %ebp */
 113         0x89, 0xe5,                     /* mov    %esp,%ebp */
 114         0x53,                           /* push   %ebx */
 115         0x8b, 0x45, 0x08,               /* mov    0x8(%ebp),%eax */
 116         0x0f, 0xa2,                     /* cpuid   */
 117         0x50,                           /* push   %eax */
 118         0x8b, 0x45, 0x10,               /* mov    0x10(%ebp),%eax */
 119         0x89, 0x18,                     /* mov    %ebx,(%eax) */
 120         0x8b, 0x45, 0x14,               /* mov    0x14(%ebp),%eax */
 121         0x89, 0x08,                     /* mov    %ecx,(%eax) */
 122         0x8b, 0x45, 0x18,               /* mov    0x18(%ebp),%eax */
 123         0x89, 0x10,                     /* mov    %edx,(%eax) */
 124         0x58,                           /* pop    %eax */
 125         0x8b, 0x55, 0x0c,               /* mov    0xc(%ebp),%edx */
 126         0x89, 0x02,                     /* mov    %eax,(%edx) */
 127         0x5b,                           /* pop    %ebx */
 128         0xc9,                           /* leave   */
 129         0xc3,                           /* ret     */
 130 };
 131
 132 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
 133
 134 static int
 135 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 136 {
 137         int have_cpuid = 0;
 138         __asm__  __volatile__ (
 139                 "pushfl\n"
 140                 "popl %%eax\n"
 141                 "movl %%eax, %%edx\n"
 142                 "xorl $0x200000, %%eax\n"
 143                 "pushl %%eax\n"
 144                 "popfl\n"
 145                 "pushfl\n"
 146                 "popl %%eax\n"
 147                 "xorl %%edx, %%eax\n"
 148                 "andl $0x200000, %%eax\n"
 149                 "movl %%eax, %0"
 150                 : "=r" (have_cpuid)
 151                 :
 152                 : "%eax", "%edx"
 153         );
 154
 155         if (have_cpuid) {
 156                 CpuidFunc func = (CpuidFunc)cpuid_impl;
 157                 func (id, p_eax, p_ebx, p_ecx, p_edx);
 158                 /*
 159                  * We use this approach because of issues with gcc and pic code, see:
 160                  * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
 161                 __asm__ __volatile__ ("cpuid"
 162                         : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 163                         : "a" (id));
 164                 */
 165                 return 1;
 166         }
 167         return 0;
 168 }
 169
 170 /*
 171  * Initialize the cpu to execute managed code.
 172  */
 173 void
 174 mono_arch_cpu_init (void)
 175 {
 176         guint16 fpcw;
 177
 178         /* spec compliance requires running with double precision */
 179         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 180         fpcw &= ~X86_FPCW_PRECC_MASK;
 181         fpcw |= X86_FPCW_PREC_DOUBLE;
 182         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 183         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 184
 185 }
 186
 187 /*
 188  * This function returns the optimizations supported on this cpu.
 189  */
 190 guint32
 191 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 192 {
 193         int eax, ebx, ecx, edx;
 194         guint32 opts = 0;
 195
 196         *exclude_mask = 0;
 197         /* Feature Flags function, flags returned in EDX. */
 198         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 199                 if (edx & (1 << 15)) {
 200                         opts |= MONO_OPT_CMOV;
 201                         if (edx & 1)
 202                                 opts |= MONO_OPT_FCMOV;
 203                         else
 204                                 *exclude_mask |= MONO_OPT_FCMOV;
 205                 } else
 206                         *exclude_mask |= MONO_OPT_CMOV;
 207         }
 208         return opts;
 209 }
 210
 211 static gboolean
 212 is_regsize_var (MonoType *t) {
 213         if (t->byref)
 214                 return TRUE;
 215         switch (t->type) {
 216         case MONO_TYPE_I4:
 217         case MONO_TYPE_U4:
 218         case MONO_TYPE_I:
 219         case MONO_TYPE_U:
 220         case MONO_TYPE_PTR:
 221                 return TRUE;
 222         case MONO_TYPE_OBJECT:
 223         case MONO_TYPE_STRING:
 224         case MONO_TYPE_CLASS:
 225         case MONO_TYPE_SZARRAY:
 226         case MONO_TYPE_ARRAY:
 227                 return TRUE;
 228         case MONO_TYPE_VALUETYPE:
 229                 if (t->data.klass->enumtype)
 230                         return is_regsize_var (t->data.klass->enum_basetype);
 231                 return FALSE;
 232         }
 233         return FALSE;
 234 }
 235
 236 GList *
 237 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 238 {
 239         GList *vars = NULL;
 240         int i;
 241
 242         for (i = 0; i < cfg->num_varinfo; i++) {
 243                 MonoInst *ins = cfg->varinfo [i];
 244                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 245
 246                 /* unused vars */
 247                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 248                         continue;
 249
 250                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 251                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 252                         continue;
 253
 254                 /* we dont allocate I1 to registers because there is no simply way to sign extend
 255                  * 8bit quantities in caller saved registers on x86 */
 256                 if (is_regsize_var (ins->inst_vtype) || (ins->inst_vtype->type == MONO_TYPE_BOOLEAN) ||
 257                     (ins->inst_vtype->type == MONO_TYPE_U1) || (ins->inst_vtype->type == MONO_TYPE_U2)||
 258                     (ins->inst_vtype->type == MONO_TYPE_I2) || (ins->inst_vtype->type == MONO_TYPE_CHAR)) {
 259                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 260                         g_assert (i == vmv->idx);
 261                         vars = g_list_prepend (vars, vmv);
 262                 }
 263         }
 264
 265         vars = mono_varlist_sort (cfg, vars, 0);
 266
 267         return vars;
 268 }
 269
 270 GList *
 271 mono_arch_get_global_int_regs (MonoCompile *cfg)
 272 {
 273         GList *regs = NULL;
 274
 275         /* we can use 3 registers for global allocation */
 276         regs = g_list_prepend (regs, (gpointer)X86_EBX);
 277         regs = g_list_prepend (regs, (gpointer)X86_ESI);
 278         regs = g_list_prepend (regs, (gpointer)X86_EDI);
 279
 280         return regs;
 281 }
 282
 283 /*
 284  * mono_arch_regalloc_cost:
 285  *
 286  *  Return the cost, in number of memory references, of the action of
 287  * allocating the variable VMV into a register during global register
 288  * allocation.
 289  */
 290 guint32
 291 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 292 {
 293         MonoInst *ins = cfg->varinfo [vmv->idx];
 294
 295         if (cfg->method->save_lmf)
 296                 /* The register is already saved */
 297                 return (ins->opcode == OP_ARG) ? 1 : 0;
 298         else
 299                 /* push+pop+possible load if it is an argument */
 300                 return (ins->opcode == OP_ARG) ? 3 : 2;
 301 }
 302
 303 /*
 304  * Set var information according to the calling convention. X86 version.
 305  * The locals var stuff should most likely be split in another method.
 306  */
 307 void
 308 mono_arch_allocate_vars (MonoCompile *m)
 309 {
 310         MonoMethodSignature *sig;
 311         MonoMethodHeader *header;
 312         MonoInst *inst;
 313         int i, offset, size, align, curinst;
 314
 315         header = ((MonoMethodNormal *)m->method)->header;
 316
 317         sig = m->method->signature;
 318
 319         offset = 8;
 320         curinst = 0;
 321         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
 322                 m->ret->opcode = OP_REGOFFSET;
 323                 m->ret->inst_basereg = X86_EBP;
 324                 m->ret->inst_offset = offset;
 325                 offset += sizeof (gpointer);
 326         } else {
 327                 /* FIXME: handle long and FP values */
 328                 switch (sig->ret->type) {
 329                 case MONO_TYPE_VOID:
 330                         break;
 331                 default:
 332                         m->ret->opcode = OP_REGVAR;
 333                         m->ret->inst_c0 = X86_EAX;
 334                         break;
 335                 }
 336         }
 337         if (sig->hasthis) {
 338                 inst = m->varinfo [curinst];
 339                 if (inst->opcode != OP_REGVAR) {
 340                         inst->opcode = OP_REGOFFSET;
 341                         inst->inst_basereg = X86_EBP;
 342                 }
 343                 inst->inst_offset = offset;
 344                 offset += sizeof (gpointer);
 345                 curinst++;
 346         }
 347
 348         if (sig->call_convention == MONO_CALL_VARARG) {
 349                 m->sig_cookie = offset;
 350                 offset += sizeof (gpointer);
 351         }
 352
 353         for (i = 0; i < sig->param_count; ++i) {
 354                 inst = m->varinfo [curinst];
 355                 if (inst->opcode != OP_REGVAR) {
 356                         inst->opcode = OP_REGOFFSET;
 357                         inst->inst_basereg = X86_EBP;
 358                 }
 359                 inst->inst_offset = offset;
 360                 size = mono_type_size (sig->params [i], &align);
 361                 size += 4 - 1;
 362                 size &= ~(4 - 1);
 363                 offset += size;
 364                 curinst++;
 365         }
 366
 367         offset = 0;
 368
 369         /* reserve space to save LMF and caller saved registers */
 370
 371         if (m->method->save_lmf) {
 372                 offset += sizeof (MonoLMF);
 373         } else {
 374                 if (m->used_int_regs & (1 << X86_EBX)) {
 375                         offset += 4;
 376                 }
 377
 378                 if (m->used_int_regs & (1 << X86_EDI)) {
 379                         offset += 4;
 380                 }
 381
 382                 if (m->used_int_regs & (1 << X86_ESI)) {
 383                         offset += 4;
 384                 }
 385         }
 386
 387         for (i = curinst; i < m->num_varinfo; ++i) {
 388                 inst = m->varinfo [i];
 389
 390                 if ((inst->flags & MONO_INST_IS_DEAD) || inst->opcode == OP_REGVAR)
 391                         continue;
 392
 393                 /* inst->unused indicates native sized value types, this is used by the
 394                 * pinvoke wrappers when they call functions returning structure */
 395                 if (inst->unused && MONO_TYPE_ISSTRUCT (inst->inst_vtype) && inst->inst_vtype->type != MONO_TYPE_TYPEDBYREF)
 396                         size = mono_class_native_size (inst->inst_vtype->data.klass, &align);
 397                 else
 398                         size = mono_type_size (inst->inst_vtype, &align);
 399
 400                 offset += size;
 401                 offset += align - 1;
 402                 offset &= ~(align - 1);
 403                 inst->opcode = OP_REGOFFSET;
 404                 inst->inst_basereg = X86_EBP;
 405                 inst->inst_offset = -offset;
 406                 //g_print ("allocating local %d to %d\n", i, -offset);
 407         }
 408         offset += (MONO_ARCH_FRAME_ALIGNMENT - 1);
 409         offset &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
 410
 411         /* change sign? */
 412         m->stack_offset = -offset;
 413 }
 414
 415 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
 416  * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
 417  */
 418
 419 /*
 420  * take the arguments and generate the arch-specific
 421  * instructions to properly call the function in call.
 422  * This includes pushing, moving arguments to the right register
 423  * etc.
 424  * Issue: who does the spilling if needed, and when?
 425  */
 426 MonoCallInst*
 427 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
 428         MonoInst *arg, *in;
 429         MonoMethodSignature *sig;
 430         int i, n, stack_size, type;
 431         MonoType *ptype;
 432
 433         stack_size = 0;
 434         /* add the vararg cookie before the non-implicit args */
 435         if (call->signature->call_convention == MONO_CALL_VARARG) {
 436                 MonoInst *sig_arg;
 437                 /* FIXME: Add support for signature tokens to AOT */
 438                 cfg->disable_aot = TRUE;
 439                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
 440                 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
 441                 sig_arg->inst_p0 = call->signature;
 442                 arg->inst_left = sig_arg;
 443                 arg->type = STACK_PTR;
 444                 /* prepend, so they get reversed */
 445                 arg->next = call->out_args;
 446                 call->out_args = arg;
 447                 stack_size += sizeof (gpointer);
 448         }
 449         sig = call->signature;
 450         n = sig->param_count + sig->hasthis;
 451
 452         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret))
 453                 stack_size += sizeof (gpointer);
 454         for (i = 0; i < n; ++i) {
 455                 if (is_virtual && i == 0) {
 456                         /* the argument will be attached to the call instrucion */
 457                         in = call->args [i];
 458                         stack_size += 4;
 459                 } else {
 460                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
 461                         in = call->args [i];
 462                         arg->cil_code = in->cil_code;
 463                         arg->inst_left = in;
 464                         arg->type = in->type;
 465                         /* prepend, so they get reversed */
 466                         arg->next = call->out_args;
 467                         call->out_args = arg;
 468                         if (i >= sig->hasthis) {
 469                                 ptype = sig->params [i - sig->hasthis];
 470                                 if (ptype->byref)
 471                                         type = MONO_TYPE_U;
 472                                 else
 473                                         type = ptype->type;
 474 handle_enum:
 475                                 /* FIXME: validate arguments... */
 476                                 switch (type) {
 477                                 case MONO_TYPE_I:
 478                                 case MONO_TYPE_U:
 479                                 case MONO_TYPE_BOOLEAN:
 480                                 case MONO_TYPE_CHAR:
 481                                 case MONO_TYPE_I1:
 482                                 case MONO_TYPE_U1:
 483                                 case MONO_TYPE_I2:
 484                                 case MONO_TYPE_U2:
 485                                 case MONO_TYPE_I4:
 486                                 case MONO_TYPE_U4:
 487                                 case MONO_TYPE_STRING:
 488                                 case MONO_TYPE_CLASS:
 489                                 case MONO_TYPE_OBJECT:
 490                                 case MONO_TYPE_PTR:
 491                                 case MONO_TYPE_FNPTR:
 492                                 case MONO_TYPE_ARRAY:
 493                                 case MONO_TYPE_SZARRAY:
 494                                         stack_size += 4;
 495                                         break;
 496                                 case MONO_TYPE_I8:
 497                                 case MONO_TYPE_U8:
 498                                         stack_size += 8;
 499                                         break;
 500                                 case MONO_TYPE_R4:
 501                                         stack_size += 4;
 502                                         arg->opcode = OP_OUTARG_R4;
 503                                         break;
 504                                 case MONO_TYPE_R8:
 505                                         stack_size += 8;
 506                                         arg->opcode = OP_OUTARG_R8;
 507                                         break;
 508                                 case MONO_TYPE_VALUETYPE:
 509                                         if (MONO_TYPE_ISSTRUCT (ptype)) {
 510                                                 int size;
 511                                                 if (sig->pinvoke)
 512                                                         size = mono_type_native_stack_size (&in->klass->byval_arg, NULL);
 513                                                 else
 514                                                         size = mono_type_stack_size (&in->klass->byval_arg, NULL);
 515
 516                                                 stack_size += size;
 517                                                 arg->opcode = OP_OUTARG_VT;
 518                                                 arg->klass = in->klass;
 519                                                 arg->unused = sig->pinvoke;
 520                                                 arg->inst_imm = size;
 521                                         } else {
 522                                                 type = ptype->data.klass->enum_basetype->type;
 523                                                 goto handle_enum;
 524                                         }
 525                                         break;
 526                                 case MONO_TYPE_TYPEDBYREF:
 527                                         stack_size += sizeof (MonoTypedRef);
 528                                         arg->opcode = OP_OUTARG_VT;
 529                                         arg->klass = in->klass;
 530                                         arg->unused = sig->pinvoke;
 531                                         arg->inst_imm = sizeof (MonoTypedRef);
 532                                         break;
 533                                 case MONO_TYPE_GENERICINST:
 534                                         type = ptype->data.generic_inst->generic_type->type;
 535                                         goto handle_enum;
 536
 537                                 default:
 538                                         g_error ("unknown type 0x%02x in mono_arch_call_opcode\n", type);
 539                                 }
 540                         } else {
 541                                 /* the this argument */
 542                                 stack_size += 4;
 543                         }
 544                 }
 545         }
 546         /* if the function returns a struct, the called method already does a ret $0x4 */
 547         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret))
 548                 stack_size -= 4;
 549         call->stack_usage = stack_size;
 550         /*
 551          * should set more info in call, such as the stack space
 552          * used by the args that needs to be added back to esp
 553          */
 554
 555         return call;
 556 }
 557
 558 /*
 559  * Allow tracing to work with this interface (with an optional argument)
 560  */
 561
 562 /*
 563  * This may be needed on some archs or for debugging support.
 564  */
 565 void
 566 mono_arch_instrument_mem_needs (MonoMethod *method, int *stack, int *code)
 567 {
 568         /* no stack room needed now (may be needed for FASTCALL-trace support) */
 569         *stack = 0;
 570         /* split prolog-epilog requirements? */
 571         *code = 50; /* max bytes needed: check this number */
 572 }
 573
 574 void*
 575 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
 576 {
 577         guchar *code = p;
 578
 579         /* if some args are passed in registers, we need to save them here */
 580         x86_push_reg (code, X86_EBP);
 581         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
 582         x86_push_imm (code, cfg->method);
 583         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
 584         x86_call_code (code, 0);
 585         x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
 586
 587         return code;
 588 }
 589
 590 enum {
 591         SAVE_NONE,
 592         SAVE_STRUCT,
 593         SAVE_EAX,
 594         SAVE_EAX_EDX,
 595         SAVE_FP
 596 };
 597
 598 void*
 599 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
 600 {
 601         guchar *code = p;
 602         int arg_size = 0, save_mode = SAVE_NONE;
 603         MonoMethod *method = cfg->method;
 604         int rtype = method->signature->ret->type;
 605
 606 handle_enum:
 607         switch (rtype) {
 608         case MONO_TYPE_VOID:
 609                 /* special case string .ctor icall */
 610                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
 611                         save_mode = SAVE_EAX;
 612                 else
 613                         save_mode = SAVE_NONE;
 614                 break;
 615         case MONO_TYPE_I8:
 616         case MONO_TYPE_U8:
 617                 save_mode = SAVE_EAX_EDX;
 618                 break;
 619         case MONO_TYPE_R4:
 620         case MONO_TYPE_R8:
 621                 save_mode = SAVE_FP;
 622                 break;
 623         case MONO_TYPE_VALUETYPE:
 624                 if (method->signature->ret->data.klass->enumtype) {
 625                         rtype = method->signature->ret->data.klass->enum_basetype->type;
 626                         goto handle_enum;
 627                 }
 628                 save_mode = SAVE_STRUCT;
 629                 break;
 630         default:
 631                 save_mode = SAVE_EAX;
 632                 break;
 633         }
 634
 635         switch (save_mode) {
 636         case SAVE_EAX_EDX:
 637                 x86_push_reg (code, X86_EDX);
 638                 x86_push_reg (code, X86_EAX);
 639                 if (enable_arguments) {
 640                         x86_push_reg (code, X86_EDX);
 641                         x86_push_reg (code, X86_EAX);
 642                         arg_size = 8;
 643                 }
 644                 break;
 645         case SAVE_EAX:
 646                 x86_push_reg (code, X86_EAX);
 647                 if (enable_arguments) {
 648                         x86_push_reg (code, X86_EAX);
 649                         arg_size = 4;
 650                 }
 651                 break;
 652         case SAVE_FP:
 653                 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
 654                 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
 655                 if (enable_arguments) {
 656                         x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
 657                         x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
 658                         arg_size = 8;
 659                 }
 660                 break;
 661         case SAVE_STRUCT:
 662                 if (enable_arguments) {
 663                         x86_push_membase (code, X86_EBP, 8);
 664                         arg_size = 4;
 665                 }
 666                 break;
 667         case SAVE_NONE:
 668         default:
 669                 break;
 670         }
 671
 672
 673         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
 674         x86_push_imm (code, method);
 675         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
 676         x86_call_code (code, 0);
 677         x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
 678
 679         switch (save_mode) {
 680         case SAVE_EAX_EDX:
 681                 x86_pop_reg (code, X86_EAX);
 682                 x86_pop_reg (code, X86_EDX);
 683                 break;
 684         case SAVE_EAX:
 685                 x86_pop_reg (code, X86_EAX);
 686                 break;
 687         case SAVE_FP:
 688                 x86_fld_membase (code, X86_ESP, 0, TRUE);
 689                 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
 690                 break;
 691         case SAVE_NONE:
 692         default:
 693                 break;
 694         }
 695
 696         return code;
 697 }
 698
 699 #define EMIT_COND_BRANCH(ins,cond,sign) \
 700 if (ins->flags & MONO_INST_BRLABEL) { \
 701         if (ins->inst_i0->inst_c0) { \
 702                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
 703         } else { \
 704                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
 705                 x86_branch32 (code, cond, 0, sign); \
 706         } \
 707 } else { \
 708         if (ins->inst_true_bb->native_offset) { \
 709                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
 710         } else { \
 711                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
 712                 if ((cfg->opt & MONO_OPT_BRANCH) && \
 713                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
 714                         x86_branch8 (code, cond, 0, sign); \
 715                 else \
 716                         x86_branch32 (code, cond, 0, sign); \
 717         } \
 718 }
 719
 720 /* emit an exception if condition is fail */
 721 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
 722         do {                                                        \
 723                 mono_add_patch_info (cfg, code - cfg->native_code,   \
 724                                     MONO_PATCH_INFO_EXC, exc_name);  \
 725                 x86_branch32 (code, cond, 0, signed);               \
 726         } while (0);
 727
 728 #define EMIT_FPCOMPARE(code) do { \
 729         x86_fcompp (code); \
 730         x86_fnstsw (code); \
 731 } while (0);
 732
 733 /* FIXME: Add more instructions */
 734 #define INST_IGNORES_CFLAGS(ins) (((ins)->opcode == CEE_BR) || ((ins)->opcode == OP_STORE_MEMBASE_IMM))
 735
 736 static void
 737 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
 738 {
 739         MonoInst *ins, *last_ins = NULL;
 740         ins = bb->code;
 741
 742         while (ins) {
 743
 744                 switch (ins->opcode) {
 745                 case OP_ICONST:
 746                         /* reg = 0 -> XOR (reg, reg) */
 747                         /* XOR sets cflags on x86, so we cant do it always */
 748                         if (ins->inst_c0 == 0 && ins->next && INST_IGNORES_CFLAGS (ins->next)) {
 749                                 ins->opcode = CEE_XOR;
 750                                 ins->sreg1 = ins->dreg;
 751                                 ins->sreg2 = ins->dreg;
 752                         }
 753                         break;
 754                 case OP_MUL_IMM:
 755                         /* remove unnecessary multiplication with 1 */
 756                         if (ins->inst_imm == 1) {
 757                                 if (ins->dreg != ins->sreg1) {
 758                                         ins->opcode = OP_MOVE;
 759                                 } else {
 760                                         last_ins->next = ins->next;
 761                                         ins = ins->next;
 762                                         continue;
 763                                 }
 764                         }
 765                         break;
 766                 case OP_COMPARE_IMM:
 767                         /* OP_COMPARE_IMM (reg, 0)
 768                          * -->
 769                          * OP_X86_TEST_NULL (reg)
 770                          */
 771                         if (ins->inst_imm == 0 && ins->next &&
 772                             (ins->next->opcode == CEE_BEQ || ins->next->opcode == CEE_BNE_UN ||
 773                              ins->next->opcode == OP_CEQ)) {
 774                                 ins->opcode = OP_X86_TEST_NULL;
 775                         }
 776                         break;
 777                 case OP_X86_COMPARE_MEMBASE_IMM:
 778                         /*
 779                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
 780                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
 781                          * -->
 782                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
 783                          * OP_COMPARE_IMM reg, imm
 784                          *
 785                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
 786                          */
 787                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
 788                             ins->inst_basereg == last_ins->inst_destbasereg &&
 789                             ins->inst_offset == last_ins->inst_offset) {
 790                                         ins->opcode = OP_COMPARE_IMM;
 791                                         ins->sreg1 = last_ins->sreg1;
 792
 793                                         /* check if we can remove cmp reg,0 with test null */
 794                                         if (ins->inst_imm == 0 && ins->next &&
 795                                                 (ins->next->opcode == CEE_BEQ || ins->next->opcode == CEE_BNE_UN ||
 796                                                 ins->next->opcode == OP_CEQ)) {
 797                                                 ins->opcode = OP_X86_TEST_NULL;
 798                                         }
 799                                 }
 800
 801                         break;
 802                 case OP_LOAD_MEMBASE:
 803                 case OP_LOADI4_MEMBASE:
 804                         /*
 805                          * Note: if reg1 = reg2 the load op is removed
 806                          *
 807                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
 808                          * OP_LOAD_MEMBASE offset(basereg), reg2
 809                          * -->
 810                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
 811                          * OP_MOVE reg1, reg2
 812                          */
 813                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
 814                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
 815                             ins->inst_basereg == last_ins->inst_destbasereg &&
 816                             ins->inst_offset == last_ins->inst_offset) {
 817                                 if (ins->dreg == last_ins->sreg1) {
 818                                         last_ins->next = ins->next;
 819                                         ins = ins->next;
 820                                         continue;
 821                                 } else {
 822                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
 823                                         ins->opcode = OP_MOVE;
 824                                         ins->sreg1 = last_ins->sreg1;
 825                                 }
 826
 827                         /*
 828                          * Note: reg1 must be different from the basereg in the second load
 829                          * Note: if reg1 = reg2 is equal then second load is removed
 830                          *
 831                          * OP_LOAD_MEMBASE offset(basereg), reg1
 832                          * OP_LOAD_MEMBASE offset(basereg), reg2
 833                          * -->
 834                          * OP_LOAD_MEMBASE offset(basereg), reg1
 835                          * OP_MOVE reg1, reg2
 836                          */
 837                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
 838                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
 839                               ins->inst_basereg != last_ins->dreg &&
 840                               ins->inst_basereg == last_ins->inst_basereg &&
 841                               ins->inst_offset == last_ins->inst_offset) {
 842
 843                                 if (ins->dreg == last_ins->dreg) {
 844                                         last_ins->next = ins->next;
 845                                         ins = ins->next;
 846                                         continue;
 847                                 } else {
 848                                         ins->opcode = OP_MOVE;
 849                                         ins->sreg1 = last_ins->dreg;
 850                                 }
 851
 852                                 //g_assert_not_reached ();
 853
 854 #if 0
 855                         /*
 856                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
 857                          * OP_LOAD_MEMBASE offset(basereg), reg
 858                          * -->
 859                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
 860                          * OP_ICONST reg, imm
 861                          */
 862                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
 863                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
 864                                    ins->inst_basereg == last_ins->inst_destbasereg &&
 865                                    ins->inst_offset == last_ins->inst_offset) {
 866                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
 867                                 ins->opcode = OP_ICONST;
 868                                 ins->inst_c0 = last_ins->inst_imm;
 869                                 g_assert_not_reached (); // check this rule
 870 #endif
 871                         }
 872                         break;
 873                 case OP_LOADU1_MEMBASE:
 874                 case OP_LOADI1_MEMBASE:
 875                         /*
 876                          * Note: if reg1 = reg2 the load op is removed
 877                          *
 878                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
 879                          * OP_LOAD_MEMBASE offset(basereg), reg2
 880                          * -->
 881                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
 882                          * OP_MOVE reg1, reg2
 883                          */
 884                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
 885                                         ins->inst_basereg == last_ins->inst_destbasereg &&
 886                                         ins->inst_offset == last_ins->inst_offset) {
 887                                 if (ins->dreg == last_ins->sreg1) {
 888                                         last_ins->next = ins->next;
 889                                         ins = ins->next;
 890                                         continue;
 891                                 } else {
 892                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
 893                                         ins->opcode = OP_MOVE;
 894                                         ins->sreg1 = last_ins->sreg1;
 895                                 }
 896                         }
 897                         break;
 898                 case OP_LOADU2_MEMBASE:
 899                 case OP_LOADI2_MEMBASE:
 900                         /*
 901                          * Note: if reg1 = reg2 the load op is removed
 902                          *
 903                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
 904                          * OP_LOAD_MEMBASE offset(basereg), reg2
 905                          * -->
 906                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
 907                          * OP_MOVE reg1, reg2
 908                          */
 909                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
 910                                         ins->inst_basereg == last_ins->inst_destbasereg &&
 911                                         ins->inst_offset == last_ins->inst_offset) {
 912                                 if (ins->dreg == last_ins->sreg1) {
 913                                         last_ins->next = ins->next;
 914                                         ins = ins->next;
 915                                         continue;
 916                                 } else {
 917                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
 918                                         ins->opcode = OP_MOVE;
 919                                         ins->sreg1 = last_ins->sreg1;
 920                                 }
 921                         }
 922                         break;
 923                 case CEE_CONV_I4:
 924                 case CEE_CONV_U4:
 925                 case OP_MOVE:
 926                         /*
 927                          * Removes:
 928                          *
 929                          * OP_MOVE reg, reg
 930                          */
 931                         if (ins->dreg == ins->sreg1) {
 932                                 if (last_ins)
 933                                         last_ins->next = ins->next;
 934                                 ins = ins->next;
 935                                 continue;
 936                         }
 937                         /*
 938                          * Removes:
 939                          *
 940                          * OP_MOVE sreg, dreg
 941                          * OP_MOVE dreg, sreg
 942                          */
 943                         if (last_ins && last_ins->opcode == OP_MOVE &&
 944                             ins->sreg1 == last_ins->dreg &&
 945                             ins->dreg == last_ins->sreg1) {
 946                                 last_ins->next = ins->next;
 947                                 ins = ins->next;
 948                                 continue;
 949                         }
 950                         break;
 951                 }
 952                 last_ins = ins;
 953                 ins = ins->next;
 954         }
 955         bb->last_ins = last_ins;
 956 }
 957
 958 static const int
 959 branch_cc_table [] = {
 960         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
 961         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
 962         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
 963 };
 964
 965 #define DEBUG(a) if (cfg->verbose_level > 1) a
 966 //#define DEBUG(a)
 967
 968 /*
 969  * returns the offset used by spillvar. It allocates a new
 970  * spill variable if necessary.
 971  */
 972 static int
 973 mono_spillvar_offset (MonoCompile *cfg, int spillvar)
 974 {
 975         MonoSpillInfo **si, *info;
 976         int i = 0;
 977
 978         si = &cfg->spill_info;
 979
 980         while (i <= spillvar) {
 981
 982                 if (!*si) {
 983                         *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
 984                         info->next = NULL;
 985                         cfg->stack_offset -= sizeof (gpointer);
 986                         info->offset = cfg->stack_offset;
 987                 }
 988
 989                 if (i == spillvar)
 990                         return (*si)->offset;
 991
 992                 i++;
 993                 si = &(*si)->next;
 994         }
 995
 996         g_assert_not_reached ();
 997         return 0;
 998 }
 999
1000 /*
1001  * returns the offset used by spillvar. It allocates a new
1002  * spill float variable if necessary.
1003  * (same as mono_spillvar_offset but for float)
1004  */
1005 static int
1006 mono_spillvar_offset_float (MonoCompile *cfg, int spillvar)
1007 {
1008         MonoSpillInfo **si, *info;
1009         int i = 0;
1010
1011         si = &cfg->spill_info_float;
1012
1013         while (i <= spillvar) {
1014
1015                 if (!*si) {
1016                         *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
1017                         info->next = NULL;
1018                         cfg->stack_offset -= sizeof (double);
1019                         info->offset = cfg->stack_offset;
1020                 }
1021
1022                 if (i == spillvar)
1023                         return (*si)->offset;
1024
1025                 i++;
1026                 si = &(*si)->next;
1027         }
1028
1029         g_assert_not_reached ();
1030         return 0;
1031 }
1032
1033 /*
1034  * Creates a store for spilled floating point items
1035  */
1036 static MonoInst*
1037 create_spilled_store_float (MonoCompile *cfg, int spill, int reg, MonoInst *ins)
1038 {
1039         MonoInst *store;
1040         MONO_INST_NEW (cfg, store, OP_STORER8_MEMBASE_REG);
1041         store->sreg1 = reg;
1042         store->inst_destbasereg = X86_EBP;
1043         store->inst_offset = mono_spillvar_offset_float (cfg, spill);
1044
1045         DEBUG (g_print ("SPILLED FLOAT STORE (%d at 0x%08x(%%sp)) (from %d)\n", spill, store->inst_offset, reg));
1046         return store;
1047 }
1048
1049 /*
1050  * Creates a load for spilled floating point items
1051  */
1052 static MonoInst*
1053 create_spilled_load_float (MonoCompile *cfg, int spill, int reg, MonoInst *ins)
1054 {
1055         MonoInst *load;
1056         MONO_INST_NEW (cfg, load, OP_LOADR8_SPILL_MEMBASE);
1057         load->dreg = reg;
1058         load->inst_basereg = X86_EBP;
1059         load->inst_offset = mono_spillvar_offset_float (cfg, spill);
1060
1061         DEBUG (g_print ("SPILLED FLOAT LOAD (%d at 0x%08x(%%sp)) (from %d)\n", spill, load->inst_offset, reg));
1062         return load;
1063 }
1064
1065 #define reg_is_freeable(r) ((r) >= 0 && (r) <= 7 && X86_IS_CALLEE ((r)))
1066
1067 typedef struct {
1068         int born_in;
1069         int killed_in;
1070         int last_use;
1071         int prev_use;
1072         int flags;              /* used to track fp spill/load */
1073 } RegTrack;
1074
1075 static const char*const * ins_spec = pentium_desc;
1076
1077 static void
1078 print_ins (int i, MonoInst *ins)
1079 {
1080         const char *spec = ins_spec [ins->opcode];
1081         g_print ("\t%-2d %s", i, mono_inst_name (ins->opcode));
1082         if (spec [MONO_INST_DEST]) {
1083                 if (ins->dreg >= MONO_MAX_IREGS)
1084                         g_print (" R%d <-", ins->dreg);
1085                 else
1086                         g_print (" %s <-", mono_arch_regname (ins->dreg));
1087         }
1088         if (spec [MONO_INST_SRC1]) {
1089                 if (ins->sreg1 >= MONO_MAX_IREGS)
1090                         g_print (" R%d", ins->sreg1);
1091                 else
1092                         g_print (" %s", mono_arch_regname (ins->sreg1));
1093         }
1094         if (spec [MONO_INST_SRC2]) {
1095                 if (ins->sreg2 >= MONO_MAX_IREGS)
1096                         g_print (" R%d", ins->sreg2);
1097                 else
1098                         g_print (" %s", mono_arch_regname (ins->sreg2));
1099         }
1100         if (spec [MONO_INST_CLOB])
1101                 g_print (" clobbers: %c", spec [MONO_INST_CLOB]);
1102         g_print ("\n");
1103 }
1104
1105 static void
1106 print_regtrack (RegTrack *t, int num)
1107 {
1108         int i;
1109         char buf [32];
1110         const char *r;
1111
1112         for (i = 0; i < num; ++i) {
1113                 if (!t [i].born_in)
1114                         continue;
1115                 if (i >= MONO_MAX_IREGS) {
1116                         g_snprintf (buf, sizeof(buf), "R%d", i);
1117                         r = buf;
1118                 } else
1119                         r = mono_arch_regname (i);
1120                 g_print ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].last_use);
1121         }
1122 }
1123
1124 typedef struct InstList InstList;
1125
1126 struct InstList {
1127         InstList *prev;
1128         InstList *next;
1129         MonoInst *data;
1130 };
1131
1132 static inline InstList*
1133 inst_list_prepend (MonoMemPool *pool, InstList *list, MonoInst *data)
1134 {
1135         InstList *item = mono_mempool_alloc (pool, sizeof (InstList));
1136         item->data = data;
1137         item->prev = NULL;
1138         item->next = list;
1139         if (list)
1140                 list->prev = item;
1141         return item;
1142 }
1143
1144 /*
1145  * Force the spilling of the variable in the symbolic register 'reg'.
1146  */
1147 static int
1148 get_register_force_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, int reg)
1149 {
1150         MonoInst *load;
1151         int i, sel, spill;
1152
1153         sel = cfg->rs->iassign [reg];
1154         /*i = cfg->rs->isymbolic [sel];
1155         g_assert (i == reg);*/
1156         i = reg;
1157         spill = ++cfg->spill_count;
1158         cfg->rs->iassign [i] = -spill - 1;
1159         mono_regstate_free_int (cfg->rs, sel);
1160         /* we need to create a spill var and insert a load to sel after the current instruction */
1161         MONO_INST_NEW (cfg, load, OP_LOAD_MEMBASE);
1162         load->dreg = sel;
1163         load->inst_basereg = X86_EBP;
1164         load->inst_offset = mono_spillvar_offset (cfg, spill);
1165         if (item->prev) {
1166                 while (ins->next != item->prev->data)
1167                         ins = ins->next;
1168         }
1169         load->next = ins->next;
1170         ins->next = load;
1171         DEBUG (g_print ("SPILLED LOAD (%d at 0x%08x(%%ebp)) R%d (freed %s)\n", spill, load->inst_offset, i, mono_arch_regname (sel)));
1172         i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
1173         g_assert (i == sel);
1174
1175         return sel;
1176 }
1177
1178 static int
1179 get_register_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, guint32 regmask, int reg)
1180 {
1181         MonoInst *load;
1182         int i, sel, spill;
1183
1184         DEBUG (g_print ("\tstart regmask to assign R%d: 0x%08x (R%d <- R%d R%d)\n", reg, regmask, ins->dreg, ins->sreg1, ins->sreg2));
1185         /* exclude the registers in the current instruction */
1186         if (reg != ins->sreg1 && (reg_is_freeable (ins->sreg1) || (ins->sreg1 >= MONO_MAX_IREGS && cfg->rs->iassign [ins->sreg1] >= 0))) {
1187                 if (ins->sreg1 >= MONO_MAX_IREGS)
1188                         regmask &= ~ (1 << cfg->rs->iassign [ins->sreg1]);
1189                 else
1190                         regmask &= ~ (1 << ins->sreg1);
1191                 DEBUG (g_print ("\t\texcluding sreg1 %s\n", mono_arch_regname (ins->sreg1)));
1192         }
1193         if (reg != ins->sreg2 && (reg_is_freeable (ins->sreg2) || (ins->sreg2 >= MONO_MAX_IREGS && cfg->rs->iassign [ins->sreg2] >= 0))) {
1194                 if (ins->sreg2 >= MONO_MAX_IREGS)
1195                         regmask &= ~ (1 << cfg->rs->iassign [ins->sreg2]);
1196                 else
1197                         regmask &= ~ (1 << ins->sreg2);
1198                 DEBUG (g_print ("\t\texcluding sreg2 %s %d\n", mono_arch_regname (ins->sreg2), ins->sreg2));
1199         }
1200         if (reg != ins->dreg && reg_is_freeable (ins->dreg)) {
1201                 regmask &= ~ (1 << ins->dreg);
1202                 DEBUG (g_print ("\t\texcluding dreg %s\n", mono_arch_regname (ins->dreg)));
1203         }
1204
1205         DEBUG (g_print ("\t\tavailable regmask: 0x%08x\n", regmask));
1206         g_assert (regmask); /* need at least a register we can free */
1207         sel = -1;
1208         /* we should track prev_use and spill the register that's farther */
1209         for (i = 0; i < MONO_MAX_IREGS; ++i) {
1210                 if (regmask & (1 << i)) {
1211                         sel = i;
1212                         DEBUG (g_print ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), cfg->rs->iassign [sel]));
1213                         break;
1214                 }
1215         }
1216         i = cfg->rs->isymbolic [sel];
1217         spill = ++cfg->spill_count;
1218         cfg->rs->iassign [i] = -spill - 1;
1219         mono_regstate_free_int (cfg->rs, sel);
1220         /* we need to create a spill var and insert a load to sel after the current instruction */
1221         MONO_INST_NEW (cfg, load, OP_LOAD_MEMBASE);
1222         load->dreg = sel;
1223         load->inst_basereg = X86_EBP;
1224         load->inst_offset = mono_spillvar_offset (cfg, spill);
1225         if (item->prev) {
1226                 while (ins->next != item->prev->data)
1227                         ins = ins->next;
1228         }
1229         load->next = ins->next;
1230         ins->next = load;
1231         DEBUG (g_print ("\tSPILLED LOAD (%d at 0x%08x(%%ebp)) R%d (freed %s)\n", spill, load->inst_offset, i, mono_arch_regname (sel)));
1232         i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
1233         g_assert (i == sel);
1234
1235         return sel;
1236 }
1237
1238 static MonoInst*
1239 create_copy_ins (MonoCompile *cfg, int dest, int src, MonoInst *ins)
1240 {
1241         MonoInst *copy;
1242         MONO_INST_NEW (cfg, copy, OP_MOVE);
1243         copy->dreg = dest;
1244         copy->sreg1 = src;
1245         if (ins) {
1246                 copy->next = ins->next;
1247                 ins->next = copy;
1248         }
1249         DEBUG (g_print ("\tforced copy from %s to %s\n", mono_arch_regname (src), mono_arch_regname (dest)));
1250         return copy;
1251 }
1252
1253 static MonoInst*
1254 create_spilled_store (MonoCompile *cfg, int spill, int reg, int prev_reg, MonoInst *ins)
1255 {
1256         MonoInst *store;
1257         MONO_INST_NEW (cfg, store, OP_STORE_MEMBASE_REG);
1258         store->sreg1 = reg;
1259         store->inst_destbasereg = X86_EBP;
1260         store->inst_offset = mono_spillvar_offset (cfg, spill);
1261         if (ins) {
1262                 store->next = ins->next;
1263                 ins->next = store;
1264         }
1265         DEBUG (g_print ("\tSPILLED STORE (%d at 0x%08x(%%ebp)) R%d (from %s)\n", spill, store->inst_offset, prev_reg, mono_arch_regname (reg)));
1266         return store;
1267 }
1268
1269 static void
1270 insert_before_ins (MonoInst *ins, InstList *item, MonoInst* to_insert)
1271 {
1272         MonoInst *prev;
1273         if (item->next) {
1274                 prev = item->next->data;
1275
1276                 while (prev->next != ins)
1277                         prev = prev->next;
1278                 to_insert->next = ins;
1279                 prev->next = to_insert;
1280         } else {
1281                 to_insert->next = ins;
1282         }
1283         /*
1284          * needed otherwise in the next instruction we can add an ins to the
1285          * end and that would get past this instruction.
1286          */
1287         item->data = to_insert;
1288 }
1289
1290
1291 #if  0
1292 static int
1293 alloc_int_reg (MonoCompile *cfg, InstList *curinst, MonoInst *ins, int sym_reg, guint32 allow_mask)
1294 {
1295         int val = cfg->rs->iassign [sym_reg];
1296         if (val < 0) {
1297                 int spill = 0;
1298                 if (val < -1) {
1299                         /* the register gets spilled after this inst */
1300                         spill = -val -1;
1301                 }
1302                 val = mono_regstate_alloc_int (cfg->rs, allow_mask);
1303                 if (val < 0)
1304                         val = get_register_spilling (cfg, curinst, ins, allow_mask, sym_reg);
1305                 cfg->rs->iassign [sym_reg] = val;
1306                 /* add option to store before the instruction for src registers */
1307                 if (spill)
1308                         create_spilled_store (cfg, spill, val, sym_reg, ins);
1309         }
1310         cfg->rs->isymbolic [val] = sym_reg;
1311         return val;
1312 }
1313 #endif
1314
1315 /* flags used in reginfo->flags */
1316 #define MONO_X86_FP_NEEDS_LOAD_SPILL    1
1317 #define MONO_X86_FP_NEEDS_SPILL                 2
1318 #define MONO_X86_FP_NEEDS_LOAD                  4
1319
1320 /*#include "cprop.c"*/
1321
1322 /*
1323  * Local register allocation.
1324  * We first scan the list of instructions and we save the liveness info of
1325  * each register (when the register is first used, when it's value is set etc.).
1326  * We also reverse the list of instructions (in the InstList list) because assigning
1327  * registers backwards allows for more tricks to be used.
1328  */
1329 void
1330 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1331 {
1332         MonoInst *ins;
1333         MonoRegState *rs = cfg->rs;
1334         int i, val, fpcount;
1335         RegTrack *reginfo, *reginfof;
1336         RegTrack *reginfo1, *reginfo2, *reginfod;
1337         InstList *tmp, *reversed = NULL;
1338         const char *spec;
1339         guint32 src1_mask, src2_mask, dest_mask;
1340         GList *fspill_list = NULL;
1341         int fspill = 0;
1342
1343         if (!bb->code)
1344                 return;
1345         rs->next_vireg = bb->max_ireg;
1346         rs->next_vfreg = bb->max_freg;
1347         mono_regstate_assign (rs);
1348         reginfo = g_malloc0 (sizeof (RegTrack) * rs->next_vireg);
1349         reginfof = g_malloc0 (sizeof (RegTrack) * rs->next_vfreg);
1350         rs->ifree_mask = X86_CALLEE_REGS;
1351
1352         ins = bb->code;
1353
1354         /*if (cfg->opt & MONO_OPT_COPYPROP)
1355                 local_copy_prop (cfg, ins);*/
1356
1357         i = 1;
1358         fpcount = 0;
1359         DEBUG (g_print ("LOCAL regalloc: basic block: %d\n", bb->block_num));
1360         /* forward pass on the instructions to collect register liveness info */
1361         while (ins) {
1362                 spec = ins_spec [ins->opcode];
1363
1364                 DEBUG (print_ins (i, ins));
1365
1366                 if (spec [MONO_INST_SRC1]) {
1367                         if (spec [MONO_INST_SRC1] == 'f') {
1368                                 GList *spill;
1369                                 reginfo1 = reginfof;
1370
1371                                 spill = g_list_first (fspill_list);
1372                                 if (spill && fpcount < MONO_MAX_FREGS) {
1373                                         reginfo1 [ins->sreg1].flags |= MONO_X86_FP_NEEDS_LOAD;
1374                                         fspill_list = g_list_remove (fspill_list, spill->data);
1375                                 } else
1376                                         fpcount--;
1377                         }
1378                         else
1379                                 reginfo1 = reginfo;
1380                         reginfo1 [ins->sreg1].prev_use = reginfo1 [ins->sreg1].last_use;
1381                         reginfo1 [ins->sreg1].last_use = i;
1382                         if (spec [MONO_INST_SRC1] == 'L') {
1383                                 /* The virtual register is allocated sequentially */
1384                                 reginfo1 [ins->sreg1 + 1].prev_use = reginfo1 [ins->sreg1 + 1].last_use;
1385                                 reginfo1 [ins->sreg1 + 1].last_use = i;
1386                                 if (reginfo1 [ins->sreg1 + 1].born_in == 0 || reginfo1 [ins->sreg1 + 1].born_in > i)
1387                                         reginfo1 [ins->sreg1 + 1].born_in = i;
1388                         }
1389                 } else {
1390                         ins->sreg1 = -1;
1391                 }
1392                 if (spec [MONO_INST_SRC2]) {
1393                         if (spec [MONO_INST_SRC2] == 'f') {
1394                                 GList *spill;
1395                                 reginfo2 = reginfof;
1396                                 spill = g_list_first (fspill_list);
1397                                 if (spill) {
1398                                         reginfo2 [ins->sreg2].flags |= MONO_X86_FP_NEEDS_LOAD;
1399                                         fspill_list = g_list_remove (fspill_list, spill->data);
1400                                         if (fpcount >= MONO_MAX_FREGS) {
1401                                                 fspill++;
1402                                                 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1403                                                 reginfo2 [ins->sreg2].flags |= MONO_X86_FP_NEEDS_LOAD_SPILL;
1404                                         }
1405                                 } else
1406                                         fpcount--;
1407                         }
1408                         else
1409                                 reginfo2 = reginfo;
1410                         reginfo2 [ins->sreg2].prev_use = reginfo2 [ins->sreg2].last_use;
1411                         reginfo2 [ins->sreg2].last_use = i;
1412                         if (spec [MONO_INST_SRC2] == 'L') {
1413                                 /* The virtual register is allocated sequentially */
1414                                 reginfo2 [ins->sreg2 + 1].prev_use = reginfo2 [ins->sreg2 + 1].last_use;
1415                                 reginfo2 [ins->sreg2 + 1].last_use = i;
1416                                 if (reginfo2 [ins->sreg2 + 1].born_in == 0 || reginfo2 [ins->sreg2 + 1].born_in > i)
1417                                         reginfo2 [ins->sreg2 + 1].born_in = i;
1418                         }
1419                 } else {
1420                         ins->sreg2 = -1;
1421                 }
1422                 if (spec [MONO_INST_DEST]) {
1423                         if (spec [MONO_INST_DEST] == 'f') {
1424                                 reginfod = reginfof;
1425                                 if (fpcount >= MONO_MAX_FREGS) {
1426                                         reginfod [ins->dreg].flags |= MONO_X86_FP_NEEDS_SPILL;
1427                                         fspill++;
1428                                         fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1429                                         fpcount--;
1430                                 }
1431                                 fpcount++;
1432                         }
1433                         else
1434                                 reginfod = reginfo;
1435                         if (spec [MONO_INST_DEST] != 'b') /* it's not just a base register */
1436                                 reginfod [ins->dreg].killed_in = i;
1437                         reginfod [ins->dreg].prev_use = reginfod [ins->dreg].last_use;
1438                         reginfod [ins->dreg].last_use = i;
1439                         if (reginfod [ins->dreg].born_in == 0 || reginfod [ins->dreg].born_in > i)
1440                                 reginfod [ins->dreg].born_in = i;
1441                         if (spec [MONO_INST_DEST] == 'l' || spec [MONO_INST_DEST] == 'L') {
1442                                 /* The virtual register is allocated sequentially */
1443                                 reginfod [ins->dreg + 1].prev_use = reginfod [ins->dreg + 1].last_use;
1444                                 reginfod [ins->dreg + 1].last_use = i;
1445                                 if (reginfod [ins->dreg + 1].born_in == 0 || reginfod [ins->dreg + 1].born_in > i)
1446                                         reginfod [ins->dreg + 1].born_in = i;
1447                         }
1448                 } else {
1449                         ins->dreg = -1;
1450                 }
1451                 reversed = inst_list_prepend (cfg->mempool, reversed, ins);
1452                 ++i;
1453                 ins = ins->next;
1454         }
1455
1456         // todo: check if we have anything left on fp stack, in verify mode?
1457         fspill = 0;
1458
1459         DEBUG (print_regtrack (reginfo, rs->next_vireg));
1460         DEBUG (print_regtrack (reginfof, rs->next_vfreg));
1461         tmp = reversed;
1462         while (tmp) {
1463                 int prev_dreg, prev_sreg1, prev_sreg2, clob_dreg;
1464                 dest_mask = src1_mask = src2_mask = X86_CALLEE_REGS;
1465                 --i;
1466                 ins = tmp->data;
1467                 spec = ins_spec [ins->opcode];
1468                 prev_dreg = -1;
1469                 clob_dreg = -1;
1470                 DEBUG (g_print ("processing:"));
1471                 DEBUG (print_ins (i, ins));
1472                 if (spec [MONO_INST_CLOB] == 's') {
1473                         if (rs->ifree_mask & (1 << X86_ECX)) {
1474                                 DEBUG (g_print ("\tshortcut assignment of R%d to ECX\n", ins->sreg2));
1475                                 rs->iassign [ins->sreg2] = X86_ECX;
1476                                 rs->isymbolic [X86_ECX] = ins->sreg2;
1477                                 ins->sreg2 = X86_ECX;
1478                                 rs->ifree_mask &= ~ (1 << X86_ECX);
1479                         } else {
1480                                 int need_ecx_spill = TRUE;
1481                                 /*
1482                                  * we first check if src1/dreg is already assigned a register
1483                                  * and then we force a spill of the var assigned to ECX.
1484                                  */
1485                                 /* the destination register can't be ECX */
1486                                 dest_mask &= ~ (1 << X86_ECX);
1487                                 src1_mask &= ~ (1 << X86_ECX);
1488                                 val = rs->iassign [ins->dreg];
1489                                 /*
1490                                  * the destination register is already assigned to ECX:
1491                                  * we need to allocate another register for it and then
1492                                  * copy from this to ECX.
1493                                  */
1494                                 if (val == X86_ECX && ins->dreg != ins->sreg2) {
1495                                         int new_dest = mono_regstate_alloc_int (rs, dest_mask);
1496                                         if (new_dest < 0)
1497                                                 new_dest = get_register_spilling (cfg, tmp, ins, dest_mask, ins->dreg);
1498                                         g_assert (new_dest >= 0);
1499                                         DEBUG (g_print ("\tclob:s changing dreg R%d to %s from ECX\n", ins->dreg, mono_arch_regname (new_dest)));
1500
1501                                         rs->isymbolic [new_dest] = ins->dreg;
1502                                         rs->iassign [ins->dreg] = new_dest;
1503                                         clob_dreg = ins->dreg;
1504                                         ins->dreg = new_dest;
1505                                         create_copy_ins (cfg, X86_ECX, new_dest, ins);
1506                                         need_ecx_spill = FALSE;
1507                                         /*DEBUG (g_print ("\tforced spill of R%d\n", ins->dreg));
1508                                         val = get_register_force_spilling (cfg, tmp, ins, ins->dreg);
1509                                         rs->iassign [ins->dreg] = val;
1510                                         rs->isymbolic [val] = prev_dreg;
1511                                         ins->dreg = val;*/
1512                                 }
1513                                 val = rs->iassign [ins->sreg1];
1514                                 if (val == X86_ECX) {
1515                                         g_assert_not_reached ();
1516                                 } else if (val >= 0) {
1517                                         /*
1518                                          * the first src reg was already assigned to a register,
1519                                          * we need to copy it to the dest register because the
1520                                          * shift instruction clobbers the first operand.
1521                                          */
1522                                         MonoInst *copy = create_copy_ins (cfg, ins->dreg, val, NULL);
1523                                         DEBUG (g_print ("\tclob:s moved sreg1 from R%d to R%d\n", val, ins->dreg));
1524                                         insert_before_ins (ins, tmp, copy);
1525                                 }
1526                                 val = rs->iassign [ins->sreg2];
1527                                 if (val >= 0 && val != X86_ECX) {
1528                                         MonoInst *move = create_copy_ins (cfg, X86_ECX, val, NULL);
1529                                         DEBUG (g_print ("\tmoved arg from R%d (%d) to ECX\n", val, ins->sreg2));
1530                                         move->next = ins;
1531                                         g_assert_not_reached ();
1532                                         /* FIXME: where is move connected to the instruction list? */
1533                                         //tmp->prev->data->next = move;
1534                                 }
1535                                 if (need_ecx_spill && !(rs->ifree_mask & (1 << X86_ECX))) {
1536                                         DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [X86_ECX]));
1537                                         get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_ECX]);
1538                                         mono_regstate_free_int (rs, X86_ECX);
1539                                 }
1540                                 /* force-set sreg2 */
1541                                 rs->iassign [ins->sreg2] = X86_ECX;
1542                                 rs->isymbolic [X86_ECX] = ins->sreg2;
1543                                 ins->sreg2 = X86_ECX;
1544                                 rs->ifree_mask &= ~ (1 << X86_ECX);
1545                         }
1546                 } else if (spec [MONO_INST_CLOB] == 'd') { /* division */
1547                         int dest_reg = X86_EAX;
1548                         int clob_reg = X86_EDX;
1549                         if (spec [MONO_INST_DEST] == 'd') {
1550                                 dest_reg = X86_EDX; /* reminder */
1551                                 clob_reg = X86_EAX;
1552                         }
1553                         val = rs->iassign [ins->dreg];
1554                         if (0 && val >= 0 && val != dest_reg && !(rs->ifree_mask & (1 << dest_reg))) {
1555                                 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [dest_reg]));
1556                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [dest_reg]);
1557                                 mono_regstate_free_int (rs, dest_reg);
1558                         }
1559                         if (val < 0) {
1560                                 if (val < -1) {
1561                                         /* the register gets spilled after this inst */
1562                                         int spill = -val -1;
1563                                         dest_mask = 1 << clob_reg;
1564                                         prev_dreg = ins->dreg;
1565                                         val = mono_regstate_alloc_int (rs, dest_mask);
1566                                         if (val < 0)
1567                                                 val = get_register_spilling (cfg, tmp, ins, dest_mask, ins->dreg);
1568                                         rs->iassign [ins->dreg] = val;
1569                                         if (spill)
1570                                                 create_spilled_store (cfg, spill, val, prev_dreg, ins);
1571                                         DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_arch_regname (val), ins->dreg));
1572                                         rs->isymbolic [val] = prev_dreg;
1573                                         ins->dreg = val;
1574                                         if (val != dest_reg) { /* force a copy */
1575                                                 create_copy_ins (cfg, val, dest_reg, ins);
1576                                         }
1577                                 } else {
1578                                         DEBUG (g_print ("\tshortcut assignment of R%d to %s\n", ins->dreg, mono_arch_regname (dest_reg)));
1579                                         prev_dreg = ins->dreg;
1580                                         rs->iassign [ins->dreg] = dest_reg;
1581                                         rs->isymbolic [dest_reg] = ins->dreg;
1582                                         ins->dreg = dest_reg;
1583                                         rs->ifree_mask &= ~ (1 << dest_reg);
1584                                 }
1585                         } else {
1586                                 //DEBUG (g_print ("dest reg in div assigned: %s\n", mono_arch_regname (val)));
1587                                 if (val != dest_reg) { /* force a copy */
1588                                         create_copy_ins (cfg, val, dest_reg, ins);
1589                                         if (!(rs->ifree_mask & (1 << dest_reg)) && rs->isymbolic [dest_reg] >= MONO_MAX_IREGS) {
1590                                                 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [dest_reg]));
1591                                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [dest_reg]);
1592                                                 mono_regstate_free_int (rs, dest_reg);
1593                                         }
1594                                 }
1595                         }
1596                         if (!(rs->ifree_mask & (1 << clob_reg)) && (clob_reg != val) && (rs->isymbolic [clob_reg] >= 8)) {
1597                                 DEBUG (g_print ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1598                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [clob_reg]);
1599                                 mono_regstate_free_int (rs, clob_reg);
1600                         }
1601                         src1_mask = 1 << X86_EAX;
1602                         src2_mask = 1 << X86_ECX;
1603                 }
1604                 if (spec [MONO_INST_DEST] == 'l') {
1605                         if (!(rs->ifree_mask & (1 << X86_EAX))) {
1606                                 DEBUG (g_print ("\t(long-low) forced spill of R%d\n", rs->isymbolic [X86_EAX]));
1607                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_EAX]);
1608                                 mono_regstate_free_int (rs, X86_EAX);
1609                         }
1610                         if (!(rs->ifree_mask & (1 << X86_EDX))) {
1611                                 DEBUG (g_print ("\t(long-high) forced spill of R%d\n", rs->isymbolic [X86_EDX]));
1612                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_EDX]);
1613                                 mono_regstate_free_int (rs, X86_EDX);
1614                         }
1615                 }
1616
1617                 /* Track dreg */
1618                 if (spec [MONO_INST_DEST] == 'f') {
1619                         if (reginfof [ins->dreg].flags & MONO_X86_FP_NEEDS_SPILL) {
1620                                 GList *spill_node;
1621                                 MonoInst *store;
1622                                 spill_node = g_list_first (fspill_list);
1623                                 g_assert (spill_node);
1624
1625                                 store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->dreg, ins);
1626                                 insert_before_ins (ins, tmp, store);
1627                                 fspill_list = g_list_remove (fspill_list, spill_node->data);
1628                                 fspill--;
1629                         }
1630                 } else if (spec [MONO_INST_DEST] == 'L') {
1631                         int hreg;
1632                         val = rs->iassign [ins->dreg];
1633                         /* check special case when dreg have been moved from ecx (clob shift) */
1634                         if (spec [MONO_INST_CLOB] == 's' && clob_dreg != -1)
1635                                 hreg = clob_dreg + 1;
1636                         else
1637                                 hreg = ins->dreg + 1;
1638
1639                         /* base prev_dreg on fixed hreg, handle clob case */
1640                         prev_dreg = hreg - 1;
1641
1642                         if (val < 0) {
1643                                 int spill = 0;
1644                                 if (val < -1) {
1645                                         /* the register gets spilled after this inst */
1646                                         spill = -val -1;
1647                                 }
1648                                 val = mono_regstate_alloc_int (rs, dest_mask);
1649                                 if (val < 0)
1650                                         val = get_register_spilling (cfg, tmp, ins, dest_mask, prev_dreg);
1651                                 rs->iassign [prev_dreg] = val;
1652                                 if (spill)
1653                                         create_spilled_store (cfg, spill, val, prev_dreg, ins);
1654                         }
1655
1656                         DEBUG (g_print ("\tassigned dreg (long) %s to dest R%d\n", mono_arch_regname (val), prev_dreg));
1657
1658                         rs->isymbolic [val] = prev_dreg;
1659                         ins->dreg = val;
1660
1661                         val = rs->iassign [hreg];
1662                         if (val < 0) {
1663                                 int spill = 0;
1664                                 if (val < -1) {
1665                                         /* the register gets spilled after this inst */
1666                                         spill = -val -1;
1667                                 }
1668                                 val = mono_regstate_alloc_int (rs, dest_mask);
1669                                 if (val < 0)
1670                                         val = get_register_spilling (cfg, tmp, ins, dest_mask, hreg);
1671                                 rs->iassign [hreg] = val;
1672                                 if (spill)
1673                                         create_spilled_store (cfg, spill, val, hreg, ins);
1674                         }
1675
1676                         DEBUG (g_print ("\tassigned hreg (long-high) %s to dest R%d\n", mono_arch_regname (val), hreg));
1677                         rs->isymbolic [val] = hreg;
1678                         /* save reg allocating into unused */
1679                         ins->unused = val;
1680
1681                         /* Free the extra reg if possible */
1682                         if (reg_is_freeable (val) && hreg >= 0 && reginfo [hreg].born_in >= i) {
1683                                 DEBUG (g_print ("\tfreeable %s (R%d) (born in %d)\n", mono_arch_regname (val), hreg, reginfo [hreg].born_in));
1684                                 mono_regstate_free_int (rs, val);
1685                         }
1686                 }
1687                 else if (ins->dreg >= MONO_MAX_IREGS) {
1688                         int hreg;
1689                         val = rs->iassign [ins->dreg];
1690                         if (spec [MONO_INST_DEST] == 'l') {
1691                                 /* check special case when dreg have been moved from ecx (clob shift) */
1692                                 if (spec [MONO_INST_CLOB] == 's' && clob_dreg != -1)
1693                                         hreg = clob_dreg + 1;
1694                                 else
1695                                         hreg = ins->dreg + 1;
1696
1697                                 /* base prev_dreg on fixed hreg, handle clob case */
1698                                 prev_dreg = hreg - 1;
1699                         } else
1700                                 prev_dreg = ins->dreg;
1701
1702                         if (val < 0) {
1703                                 int spill = 0;
1704                                 if (val < -1) {
1705                                         /* the register gets spilled after this inst */
1706                                         spill = -val -1;
1707                                 }
1708                                 val = mono_regstate_alloc_int (rs, dest_mask);
1709                                 if (val < 0)
1710                                         val = get_register_spilling (cfg, tmp, ins, dest_mask, prev_dreg);
1711                                 rs->iassign [prev_dreg] = val;
1712                                 if (spill)
1713                                         create_spilled_store (cfg, spill, val, prev_dreg, ins);
1714                         }
1715                         DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_arch_regname (val), ins->dreg));
1716                         rs->isymbolic [val] = prev_dreg;
1717                         ins->dreg = val;
1718                         /* handle cases where lreg needs to be eax:edx */
1719                         if (spec [MONO_INST_DEST] == 'l') {
1720                                 /* check special case when dreg have been moved from ecx (clob shift) */
1721                                 int hreg = prev_dreg + 1;
1722                                 val = rs->iassign [hreg];
1723                                 if (val < 0) {
1724                                         int spill = 0;
1725                                         if (val < -1) {
1726                                                 /* the register gets spilled after this inst */
1727                                                 spill = -val -1;
1728                                         }
1729                                         val = mono_regstate_alloc_int (rs, dest_mask);
1730                                         if (val < 0)
1731                                                 val = get_register_spilling (cfg, tmp, ins, dest_mask, hreg);
1732                                         rs->iassign [hreg] = val;
1733                                         if (spill)
1734                                                 create_spilled_store (cfg, spill, val, hreg, ins);
1735                                 }
1736                                 DEBUG (g_print ("\tassigned hreg %s to dest R%d\n", mono_arch_regname (val), hreg));
1737                                 rs->isymbolic [val] = hreg;
1738                                 if (ins->dreg == X86_EAX) {
1739                                         if (val != X86_EDX)
1740                                                 create_copy_ins (cfg, val, X86_EDX, ins);
1741                                 } else if (ins->dreg == X86_EDX) {
1742                                         if (val == X86_EAX) {
1743                                                 /* swap */
1744                                                 g_assert_not_reached ();
1745                                         } else {
1746                                                 /* two forced copies */
1747                                                 create_copy_ins (cfg, val, X86_EDX, ins);
1748                                                 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1749                                         }
1750                                 } else {
1751                                         if (val == X86_EDX) {
1752                                                 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1753                                         } else {
1754                                                 /* two forced copies */
1755                                                 create_copy_ins (cfg, val, X86_EDX, ins);
1756                                                 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1757                                         }
1758                                 }
1759                                 if (reg_is_freeable (val) && hreg >= 0 && reginfo [hreg].born_in >= i) {
1760                                         DEBUG (g_print ("\tfreeable %s (R%d)\n", mono_arch_regname (val), hreg));
1761                                         mono_regstate_free_int (rs, val);
1762                                 }
1763                         } else if (spec [MONO_INST_DEST] == 'a' && ins->dreg != X86_EAX && spec [MONO_INST_CLOB] != 'd') {
1764                                 /* this instruction only outputs to EAX, need to copy */
1765                                 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1766                         } else if (spec [MONO_INST_DEST] == 'd' && ins->dreg != X86_EDX && spec [MONO_INST_CLOB] != 'd') {
1767                                 create_copy_ins (cfg, ins->dreg, X86_EDX, ins);
1768                         }
1769                 }
1770                 if (spec [MONO_INST_DEST] != 'f' && reg_is_freeable (ins->dreg) && prev_dreg >= 0 && reginfo [prev_dreg].born_in >= i) {
1771                         DEBUG (g_print ("\tfreeable %s (R%d) (born in %d)\n", mono_arch_regname (ins->dreg), prev_dreg, reginfo [prev_dreg].born_in));
1772                         mono_regstate_free_int (rs, ins->dreg);
1773                 }
1774                 /* put src1 in EAX if it needs to be */
1775                 if (spec [MONO_INST_SRC1] == 'a') {
1776                         if (!(rs->ifree_mask & (1 << X86_EAX))) {
1777                                 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [X86_EAX]));
1778                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_EAX]);
1779                                 mono_regstate_free_int (rs, X86_EAX);
1780                         }
1781                         /* force-set sreg1 */
1782                         rs->iassign [ins->sreg1] = X86_EAX;
1783                         rs->isymbolic [X86_EAX] = ins->sreg1;
1784                         ins->sreg1 = X86_EAX;
1785                         rs->ifree_mask &= ~ (1 << X86_EAX);
1786                 }
1787
1788                 /* Track sreg1 */
1789                 if (spec [MONO_INST_SRC1] == 'f') {
1790                         if (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD) {
1791                                 MonoInst *load;
1792                                 MonoInst *store = NULL;
1793
1794                                 if (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD_SPILL) {
1795                                         GList *spill_node;
1796                                         spill_node = g_list_first (fspill_list);
1797                                         g_assert (spill_node);
1798
1799                                         store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->sreg1, ins);
1800                                         fspill_list = g_list_remove (fspill_list, spill_node->data);
1801                                 }
1802
1803                                 fspill++;
1804                                 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1805                                 load = create_spilled_load_float (cfg, fspill, ins->sreg1, ins);
1806                                 insert_before_ins (ins, tmp, load);
1807                                 if (store)
1808                                         insert_before_ins (load, tmp, store);
1809                         }
1810                 } else if ((spec [MONO_INST_DEST] == 'L') && (spec [MONO_INST_SRC1] == 'L')) {
1811                         /* force source to be same as dest */
1812                         rs->iassign [ins->sreg1] = ins->dreg;
1813                         rs->iassign [ins->sreg1 + 1] = ins->unused;
1814
1815                         DEBUG (g_print ("\tassigned sreg1 (long) %s to sreg1 R%d\n", mono_arch_regname (ins->dreg), ins->sreg1));
1816                         DEBUG (g_print ("\tassigned sreg1 (long-high) %s to sreg1 R%d\n", mono_arch_regname (ins->unused), ins->sreg1 + 1));
1817
1818                         ins->sreg1 = ins->dreg;
1819                         /* no need for this, we know that src1=dest in this cases */
1820                         /*ins->inst_c0 = ins->unused;*/
1821
1822                         /* make sure that we remove them from free mask */
1823                         rs->ifree_mask &= ~ (1 << ins->dreg);
1824                         rs->ifree_mask &= ~ (1 << ins->unused);
1825                 }
1826                 else if (ins->sreg1 >= MONO_MAX_IREGS) {
1827                         val = rs->iassign [ins->sreg1];
1828                         prev_sreg1 = ins->sreg1;
1829                         if (val < 0) {
1830                                 int spill = 0;
1831                                 if (val < -1) {
1832                                         /* the register gets spilled after this inst */
1833                                         spill = -val -1;
1834                                 }
1835                                 if (0 && ins->opcode == OP_MOVE) {
1836                                         /*
1837                                          * small optimization: the dest register is already allocated
1838                                          * but the src one is not: we can simply assign the same register
1839                                          * here and peephole will get rid of the instruction later.
1840                                          * This optimization may interfere with the clobbering handling:
1841                                          * it removes a mov operation that will be added again to handle clobbering.
1842                                          * There are also some other issues that should with make testjit.
1843                                          */
1844                                         mono_regstate_alloc_int (rs, 1 << ins->dreg);
1845                                         val = rs->iassign [ins->sreg1] = ins->dreg;
1846                                         //g_assert (val >= 0);
1847                                         DEBUG (g_print ("\tfast assigned sreg1 %s to R%d\n", mono_arch_regname (val), ins->sreg1));
1848                                 } else {
1849                                         //g_assert (val == -1); /* source cannot be spilled */
1850                                         val = mono_regstate_alloc_int (rs, src1_mask);
1851                                         if (val < 0)
1852                                                 val = get_register_spilling (cfg, tmp, ins, src1_mask, ins->sreg1);
1853                                         rs->iassign [ins->sreg1] = val;
1854                                         DEBUG (g_print ("\tassigned sreg1 %s to R%d\n", mono_arch_regname (val), ins->sreg1));
1855                                 }
1856                                 if (spill) {
1857                                         MonoInst *store = create_spilled_store (cfg, spill, val, prev_sreg1, NULL);
1858                                         insert_before_ins (ins, tmp, store);
1859                                 }
1860                         }
1861                         rs->isymbolic [val] = prev_sreg1;
1862                         ins->sreg1 = val;
1863                 } else {
1864                         prev_sreg1 = -1;
1865                 }
1866                 /* handle clobbering of sreg1 */
1867                 if ((spec [MONO_INST_CLOB] == '1' || spec [MONO_INST_CLOB] == 's') && ins->dreg != ins->sreg1) {
1868                         MonoInst *copy = create_copy_ins (cfg, ins->dreg, ins->sreg1, NULL);
1869                         DEBUG (g_print ("\tneed to copy sreg1 %s to dreg %s\n", mono_arch_regname (ins->sreg1), mono_arch_regname (ins->dreg)));
1870                         if (ins->sreg2 == -1 || spec [MONO_INST_CLOB] == 's') {
1871                                 /* note: the copy is inserted before the current instruction! */
1872                                 insert_before_ins (ins, tmp, copy);
1873                                 /* we set sreg1 to dest as well */
1874                                 prev_sreg1 = ins->sreg1 = ins->dreg;
1875                         } else {
1876                                 /* inserted after the operation */
1877                                 copy->next = ins->next;
1878                                 ins->next = copy;
1879                         }
1880                 }
1881                 /* track sreg2 */
1882                 if (spec [MONO_INST_SRC2] == 'f') {
1883                         if (reginfof [ins->sreg2].flags & MONO_X86_FP_NEEDS_LOAD) {
1884                                 MonoInst *load;
1885                                 MonoInst *store = NULL;
1886
1887                                 if (reginfof [ins->sreg2].flags & MONO_X86_FP_NEEDS_LOAD_SPILL) {
1888                                         GList *spill_node;
1889
1890                                         spill_node = g_list_first (fspill_list);
1891                                         g_assert (spill_node);
1892                                         if (spec [MONO_INST_SRC1] == 'f' && (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD_SPILL))
1893                                                 spill_node = g_list_next (spill_node);
1894
1895                                         store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->sreg2, ins);
1896                                         fspill_list = g_list_remove (fspill_list, spill_node->data);
1897                                 }
1898
1899                                 fspill++;
1900                                 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1901                                 load = create_spilled_load_float (cfg, fspill, ins->sreg2, ins);
1902                                 insert_before_ins (ins, tmp, load);
1903                                 if (store)
1904                                         insert_before_ins (load, tmp, store);
1905                         }
1906                 }
1907                 else if (ins->sreg2 >= MONO_MAX_IREGS) {
1908                         val = rs->iassign [ins->sreg2];
1909                         prev_sreg2 = ins->sreg2;
1910                         if (val < 0) {
1911                                 int spill = 0;
1912                                 if (val < -1) {
1913                                         /* the register gets spilled after this inst */
1914                                         spill = -val -1;
1915                                 }
1916                                 val = mono_regstate_alloc_int (rs, src2_mask);
1917                                 if (val < 0)
1918                                         val = get_register_spilling (cfg, tmp, ins, src2_mask, ins->sreg2);
1919                                 rs->iassign [ins->sreg2] = val;
1920                                 DEBUG (g_print ("\tassigned sreg2 %s to R%d\n", mono_arch_regname (val), ins->sreg2));
1921                                 if (spill)
1922                                         create_spilled_store (cfg, spill, val, prev_sreg2, ins);
1923                         }
1924                         rs->isymbolic [val] = prev_sreg2;
1925                         ins->sreg2 = val;
1926                         if (spec [MONO_INST_CLOB] == 's' && ins->sreg2 != X86_ECX) {
1927                                 DEBUG (g_print ("\tassigned sreg2 %s to R%d, but ECX is needed (R%d)\n", mono_arch_regname (val), ins->sreg2, rs->iassign [X86_ECX]));
1928                         }
1929                 } else {
1930                         prev_sreg2 = -1;
1931                 }
1932
1933                 if (spec [MONO_INST_CLOB] == 'c') {
1934                         int j, s;
1935                         guint32 clob_mask = X86_CALLEE_REGS;
1936                         for (j = 0; j < MONO_MAX_IREGS; ++j) {
1937                                 s = 1 << j;
1938                                 if ((clob_mask & s) && !(rs->ifree_mask & s) && j != ins->sreg1) {
1939                                         //g_warning ("register %s busy at call site\n", mono_arch_regname (j));
1940                                 }
1941                         }
1942                 }
1943                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
1944                         DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg1)));
1945                         mono_regstate_free_int (rs, ins->sreg1);
1946                 }
1947                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
1948                         DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg2)));
1949                         mono_regstate_free_int (rs, ins->sreg2);
1950                 }*/
1951
1952                 //DEBUG (print_ins (i, ins));
1953                 /* this may result from a insert_before call */
1954                 if (!tmp->next)
1955                         bb->code = tmp->data;
1956                 tmp = tmp->next;
1957         }
1958
1959         g_free (reginfo);
1960         g_free (reginfof);
1961         g_list_free (fspill_list);
1962 }
1963
1964 static unsigned char*
1965 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
1966 {
1967         x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
1968         x86_fnstcw_membase(code, X86_ESP, 0);
1969         x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
1970         x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
1971         x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
1972         x86_fldcw_membase (code, X86_ESP, 2);
1973         if (size == 8) {
1974                 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1975                 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
1976                 x86_pop_reg (code, dreg);
1977                 /* FIXME: need the high register
1978                  * x86_pop_reg (code, dreg_high);
1979                  */
1980         } else {
1981                 x86_push_reg (code, X86_EAX); // SP = SP - 4
1982                 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
1983                 x86_pop_reg (code, dreg);
1984         }
1985         x86_fldcw_membase (code, X86_ESP, 0);
1986         x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
1987
1988         if (size == 1)
1989                 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
1990         else if (size == 2)
1991                 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
1992         return code;
1993 }
1994
1995 static unsigned char*
1996 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
1997 {
1998         int sreg = tree->sreg1;
1999 #ifdef PLATFORM_WIN32
2000         guint8* br[5];
2001
2002         /*
2003          * Under Windows:
2004          * If requested stack size is larger than one page,
2005          * perform stack-touch operation
2006          */
2007         /*
2008          * Generate stack probe code.
2009          * Under Windows, it is necessary to allocate one page at a time,
2010          * "touching" stack after each successful sub-allocation. This is
2011          * because of the way stack growth is implemented - there is a
2012          * guard page before the lowest stack page that is currently commited.
2013          * Stack normally grows sequentially so OS traps access to the
2014          * guard page and commits more pages when needed.
2015          */
2016         x86_test_reg_imm (code, sreg, ~0xFFF);
2017         br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2018
2019         br[2] = code; /* loop */
2020         x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2021         x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2022         x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2023         x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2024         br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2025         x86_patch (br[3], br[2]);
2026         x86_test_reg_reg (code, sreg, sreg);
2027         br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2028         x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2029
2030         br[1] = code; x86_jump8 (code, 0);
2031
2032         x86_patch (br[0], code);
2033         x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2034         x86_patch (br[1], code);
2035         x86_patch (br[4], code);
2036 #else /* PLATFORM_WIN32 */
2037         x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2038 #endif
2039         if (tree->flags & MONO_INST_INIT) {
2040                 int offset = 0;
2041                 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2042                         x86_push_reg (code, X86_EAX);
2043                         offset += 4;
2044                 }
2045                 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2046                         x86_push_reg (code, X86_ECX);
2047                         offset += 4;
2048                 }
2049                 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2050                         x86_push_reg (code, X86_EDI);
2051                         offset += 4;
2052                 }
2053
2054                 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2055                 if (sreg != X86_ECX)
2056                         x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2057                 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2058
2059                 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2060                 x86_cld (code);
2061                 x86_prefix (code, X86_REP_PREFIX);
2062                 x86_stosl (code);
2063
2064                 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2065                         x86_pop_reg (code, X86_EDI);
2066                 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2067                         x86_pop_reg (code, X86_ECX);
2068                 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2069                         x86_pop_reg (code, X86_EAX);
2070         }
2071         return code;
2072 }
2073
2074 #define REAL_PRINT_REG(text,reg) \
2075 mono_assert (reg >= 0); \
2076 x86_push_reg (code, X86_EAX); \
2077 x86_push_reg (code, X86_EDX); \
2078 x86_push_reg (code, X86_ECX); \
2079 x86_push_reg (code, reg); \
2080 x86_push_imm (code, reg); \
2081 x86_push_imm (code, text " %d %p\n"); \
2082 x86_mov_reg_imm (code, X86_EAX, printf); \
2083 x86_call_reg (code, X86_EAX); \
2084 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2085 x86_pop_reg (code, X86_ECX); \
2086 x86_pop_reg (code, X86_EDX); \
2087 x86_pop_reg (code, X86_EAX);
2088
2089 /* benchmark and set based on cpu */
2090 #define LOOP_ALIGNMENT 8
2091 #define bb_is_loop_start(bb) ((bb)->nesting && ((bb)->in_count == 1))
2092
2093 void
2094 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2095 {
2096         MonoInst *ins;
2097         MonoCallInst *call;
2098         guint offset;
2099         guint8 *code = cfg->native_code + cfg->code_len;
2100         MonoInst *last_ins = NULL;
2101         guint last_offset = 0;
2102         int max_len, cpos;
2103
2104         if (cfg->opt & MONO_OPT_PEEPHOLE)
2105                 peephole_pass (cfg, bb);
2106
2107         if (cfg->opt & MONO_OPT_LOOP) {
2108                 int pad, align = LOOP_ALIGNMENT;
2109                 /* set alignment depending on cpu */
2110                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2111                         pad = align - pad;
2112                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2113                         x86_padding (code, pad);
2114                         cfg->code_len += pad;
2115                         bb->native_offset = cfg->code_len;
2116                 }
2117         }
2118
2119         if (cfg->verbose_level > 2)
2120                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2121
2122         cpos = bb->max_offset;
2123
2124         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2125                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2126                 g_assert (!mono_compile_aot);
2127                 cpos += 6;
2128
2129                 cov->data [bb->dfn].cil_code = bb->cil_code;
2130                 /* this is not thread save, but good enough */
2131                 x86_inc_mem (code, &cov->data [bb->dfn].count);
2132         }
2133
2134         offset = code - cfg->native_code;
2135
2136         ins = bb->code;
2137         while (ins) {
2138                 offset = code - cfg->native_code;
2139
2140                 max_len = ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
2141
2142                 if (offset > (cfg->code_size - max_len - 16)) {
2143                         cfg->code_size *= 2;
2144                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2145                         code = cfg->native_code + offset;
2146                         mono_jit_stats.code_reallocs++;
2147                 }
2148
2149                 mono_debug_record_line_number (cfg, ins, offset);
2150
2151                 switch (ins->opcode) {
2152                 case OP_BIGMUL:
2153                         x86_mul_reg (code, ins->sreg2, TRUE);
2154                         break;
2155                 case OP_BIGMUL_UN:
2156                         x86_mul_reg (code, ins->sreg2, FALSE);
2157                         break;
2158                 case OP_X86_SETEQ_MEMBASE:
2159                         x86_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2160                         break;
2161                 case OP_STOREI1_MEMBASE_IMM:
2162                         x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2163                         break;
2164                 case OP_STOREI2_MEMBASE_IMM:
2165                         x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2166                         break;
2167                 case OP_STORE_MEMBASE_IMM:
2168                 case OP_STOREI4_MEMBASE_IMM:
2169                         x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2170                         break;
2171                 case OP_STOREI1_MEMBASE_REG:
2172                         x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2173                         break;
2174                 case OP_STOREI2_MEMBASE_REG:
2175                         x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2176                         break;
2177                 case OP_STORE_MEMBASE_REG:
2178                 case OP_STOREI4_MEMBASE_REG:
2179                         x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2180                         break;
2181                 case CEE_LDIND_I:
2182                 case CEE_LDIND_I4:
2183                 case CEE_LDIND_U4:
2184                         x86_mov_reg_mem (code, ins->dreg, ins->inst_p0, 4);
2185                         break;
2186                 case OP_LOADU4_MEM:
2187                         x86_mov_reg_imm (code, ins->dreg, ins->inst_p0);
2188                         x86_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2189                         break;
2190                 case OP_LOAD_MEMBASE:
2191                 case OP_LOADI4_MEMBASE:
2192                 case OP_LOADU4_MEMBASE:
2193                         x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2194                         break;
2195                 case OP_LOADU1_MEMBASE:
2196                         x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2197                         break;
2198                 case OP_LOADI1_MEMBASE:
2199                         x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2200                         break;
2201                 case OP_LOADU2_MEMBASE:
2202                         x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2203                         break;
2204                 case OP_LOADI2_MEMBASE:
2205                         x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2206                         break;
2207                 case CEE_CONV_I1:
2208                         x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2209                         break;
2210                 case CEE_CONV_I2:
2211                         x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2212                         break;
2213                 case CEE_CONV_U1:
2214                         x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2215                         break;
2216                 case CEE_CONV_U2:
2217                         x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2218                         break;
2219                 case OP_COMPARE:
2220                         x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2221                         break;
2222                 case OP_COMPARE_IMM:
2223                         x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2224                         break;
2225                 case OP_X86_COMPARE_MEMBASE_REG:
2226                         x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2227                         break;
2228                 case OP_X86_COMPARE_MEMBASE_IMM:
2229                         x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2230                         break;
2231                 case OP_X86_COMPARE_REG_MEMBASE:
2232                         x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2233                         break;
2234                 case OP_X86_TEST_NULL:
2235                         x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2236                         break;
2237                 case OP_X86_ADD_MEMBASE_IMM:
2238                         x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2239                         break;
2240                 case OP_X86_ADD_MEMBASE:
2241                         x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2242                         break;
2243                 case OP_X86_SUB_MEMBASE_IMM:
2244                         x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2245                         break;
2246                 case OP_X86_SUB_MEMBASE:
2247                         x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2248                         break;
2249                 case OP_X86_INC_MEMBASE:
2250                         x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2251                         break;
2252                 case OP_X86_INC_REG:
2253                         x86_inc_reg (code, ins->dreg);
2254                         break;
2255                 case OP_X86_DEC_MEMBASE:
2256                         x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2257                         break;
2258                 case OP_X86_DEC_REG:
2259                         x86_dec_reg (code, ins->dreg);
2260                         break;
2261                 case OP_X86_MUL_MEMBASE:
2262                         x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2263                         break;
2264                 case CEE_BREAK:
2265                         x86_breakpoint (code);
2266                         break;
2267                 case OP_ADDCC:
2268                 case CEE_ADD:
2269                         x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2270                         break;
2271                 case OP_ADC:
2272                         x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2273                         break;
2274                 case OP_ADD_IMM:
2275                         x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2276                         break;
2277                 case OP_ADC_IMM:
2278                         x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2279                         break;
2280                 case OP_SUBCC:
2281                 case CEE_SUB:
2282                         x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2283                         break;
2284                 case OP_SBB:
2285                         x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2286                         break;
2287                 case OP_SUB_IMM:
2288                         x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2289                         break;
2290                 case OP_SBB_IMM:
2291                         x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2292                         break;
2293                 case CEE_AND:
2294                         x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2295                         break;
2296                 case OP_AND_IMM:
2297                         x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2298                         break;
2299                 case CEE_DIV:
2300                         x86_cdq (code);
2301                         x86_div_reg (code, ins->sreg2, TRUE);
2302                         break;
2303                 case CEE_DIV_UN:
2304                         x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2305                         x86_div_reg (code, ins->sreg2, FALSE);
2306                         break;
2307                 case OP_DIV_IMM:
2308                         x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2309                         x86_cdq (code);
2310                         x86_div_reg (code, ins->sreg2, TRUE);
2311                         break;
2312                 case CEE_REM:
2313                         x86_cdq (code);
2314                         x86_div_reg (code, ins->sreg2, TRUE);
2315                         break;
2316                 case CEE_REM_UN:
2317                         x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2318                         x86_div_reg (code, ins->sreg2, FALSE);
2319                         break;
2320                 case OP_REM_IMM:
2321                         x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2322                         x86_cdq (code);
2323                         x86_div_reg (code, ins->sreg2, TRUE);
2324                         break;
2325                 case CEE_OR:
2326                         x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2327                         break;
2328                 case OP_OR_IMM:
2329                         x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2330                         break;
2331                 case CEE_XOR:
2332                         x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2333                         break;
2334                 case OP_XOR_IMM:
2335                         x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2336                         break;
2337                 case CEE_SHL:
2338                         g_assert (ins->sreg2 == X86_ECX);
2339                         x86_shift_reg (code, X86_SHL, ins->dreg);
2340                         break;
2341                 case CEE_SHR:
2342                         g_assert (ins->sreg2 == X86_ECX);
2343                         x86_shift_reg (code, X86_SAR, ins->dreg);
2344                         break;
2345                 case OP_SHR_IMM:
2346                         x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2347                         break;
2348                 case OP_SHR_UN_IMM:
2349                         x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2350                         break;
2351                 case CEE_SHR_UN:
2352                         g_assert (ins->sreg2 == X86_ECX);
2353                         x86_shift_reg (code, X86_SHR, ins->dreg);
2354                         break;
2355                 case OP_SHL_IMM:
2356                         x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2357                         break;
2358                 case OP_LSHL: {
2359                         guint8 *jump_to_end;
2360
2361                         /* handle shifts below 32 bits */
2362                         x86_shld_reg (code, ins->unused, ins->sreg1);
2363                         x86_shift_reg (code, X86_SHL, ins->sreg1);
2364
2365                         x86_test_reg_imm (code, X86_ECX, 32);
2366                         jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2367
2368                         /* handle shift over 32 bit */
2369                         x86_mov_reg_reg (code, ins->unused, ins->sreg1, 4);
2370                         x86_clear_reg (code, ins->sreg1);
2371
2372                         x86_patch (jump_to_end, code);
2373                         }
2374                         break;
2375                 case OP_LSHR: {
2376                         guint8 *jump_to_end;
2377
2378                         /* handle shifts below 32 bits */
2379                         x86_shrd_reg (code, ins->sreg1, ins->unused);
2380                         x86_shift_reg (code, X86_SAR, ins->unused);
2381
2382                         x86_test_reg_imm (code, X86_ECX, 32);
2383                         jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2384
2385                         /* handle shifts over 31 bits */
2386                         x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
2387                         x86_shift_reg_imm (code, X86_SAR, ins->unused, 31);
2388
2389                         x86_patch (jump_to_end, code);
2390                         }
2391                         break;
2392                 case OP_LSHR_UN: {
2393                         guint8 *jump_to_end;
2394
2395                         /* handle shifts below 32 bits */
2396                         x86_shrd_reg (code, ins->sreg1, ins->unused);
2397                         x86_shift_reg (code, X86_SHR, ins->unused);
2398
2399                         x86_test_reg_imm (code, X86_ECX, 32);
2400                         jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2401
2402                         /* handle shifts over 31 bits */
2403                         x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
2404                         x86_shift_reg_imm (code, X86_SHR, ins->unused, 31);
2405
2406                         x86_patch (jump_to_end, code);
2407                         }
2408                         break;
2409                 case OP_LSHL_IMM:
2410                         if (ins->inst_imm >= 32) {
2411                                 x86_mov_reg_reg (code, ins->unused, ins->sreg1, 4);
2412                                 x86_clear_reg (code, ins->sreg1);
2413                                 x86_shift_reg_imm (code, X86_SHL, ins->unused, ins->inst_imm - 32);
2414                         } else {
2415                                 x86_shld_reg_imm (code, ins->unused, ins->sreg1, ins->inst_imm);
2416                                 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2417                         }
2418                         break;
2419                 case OP_LSHR_IMM:
2420                         if (ins->inst_imm >= 32) {
2421                                 x86_mov_reg_reg (code, ins->sreg1, ins->unused,  4);
2422                                 x86_shift_reg_imm (code, X86_SAR, ins->unused, 0x1f);
2423                                 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2424                         } else {
2425                                 x86_shrd_reg_imm (code, ins->sreg1, ins->unused, ins->inst_imm);
2426                                 x86_shift_reg_imm (code, X86_SAR, ins->unused, ins->inst_imm);
2427                         }
2428                         break;
2429                 case OP_LSHR_UN_IMM:
2430                         if (ins->inst_imm >= 32) {
2431                                 x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
2432                                 x86_clear_reg (code, ins->unused);
2433                                 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2434                         } else {
2435                                 x86_shrd_reg_imm (code, ins->sreg1, ins->unused, ins->inst_imm);
2436                                 x86_shift_reg_imm (code, X86_SHR, ins->unused, ins->inst_imm);
2437                         }
2438                         break;
2439                 case CEE_NOT:
2440                         x86_not_reg (code, ins->sreg1);
2441                         break;
2442                 case CEE_NEG:
2443                         x86_neg_reg (code, ins->sreg1);
2444                         break;
2445                 case OP_SEXT_I1:
2446                         x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2447                         break;
2448                 case OP_SEXT_I2:
2449                         x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2450                         break;
2451                 case CEE_MUL:
2452                         x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2453                         break;
2454                 case OP_MUL_IMM:
2455                         x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2456                         break;
2457                 case CEE_MUL_OVF:
2458                         x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2459                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2460                         break;
2461                 case CEE_MUL_OVF_UN: {
2462                         /* the mul operation and the exception check should most likely be split */
2463                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2464                         /*g_assert (ins->sreg2 == X86_EAX);
2465                         g_assert (ins->dreg == X86_EAX);*/
2466                         if (ins->sreg2 == X86_EAX) {
2467                                 non_eax_reg = ins->sreg1;
2468                         } else if (ins->sreg1 == X86_EAX) {
2469                                 non_eax_reg = ins->sreg2;
2470                         } else {
2471                                 /* no need to save since we're going to store to it anyway */
2472                                 if (ins->dreg != X86_EAX) {
2473                                         saved_eax = TRUE;
2474                                         x86_push_reg (code, X86_EAX);
2475                                 }
2476                                 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
2477                                 non_eax_reg = ins->sreg2;
2478                         }
2479                         if (ins->dreg == X86_EDX) {
2480                                 if (!saved_eax) {
2481                                         saved_eax = TRUE;
2482                                         x86_push_reg (code, X86_EAX);
2483                                 }
2484                         } else if (ins->dreg != X86_EAX) {
2485                                 saved_edx = TRUE;
2486                                 x86_push_reg (code, X86_EDX);
2487                         }
2488                         x86_mul_reg (code, non_eax_reg, FALSE);
2489                         /* save before the check since pop and mov don't change the flags */
2490                         if (ins->dreg != X86_EAX)
2491                                 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2492                         if (saved_edx)
2493                                 x86_pop_reg (code, X86_EDX);
2494                         if (saved_eax)
2495                                 x86_pop_reg (code, X86_EAX);
2496                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2497                         break;
2498                 }
2499                 case OP_ICONST:
2500                         x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
2501                         break;
2502                 case OP_AOTCONST:
2503                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2504                         x86_mov_reg_imm (code, ins->dreg, 0);
2505                         break;
2506                 case CEE_CONV_I4:
2507                 case OP_MOVE:
2508                         x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2509                         break;
2510                 case CEE_CONV_U4:
2511                         g_assert_not_reached ();
2512                 case CEE_JMP: {
2513                         /*
2514                          * Note: this 'frame destruction' logic is useful for tail calls, too.
2515                          * Keep in sync with the code in emit_epilog.
2516                          */
2517                         int pos = 0;
2518
2519                         /* FIXME: no tracing support... */
2520                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2521                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2522                         /* reset offset to make max_len work */
2523                         offset = code - cfg->native_code;
2524
2525                         g_assert (!cfg->method->save_lmf);
2526
2527                         if (cfg->used_int_regs & (1 << X86_EBX))
2528                                 pos -= 4;
2529                         if (cfg->used_int_regs & (1 << X86_EDI))
2530                                 pos -= 4;
2531                         if (cfg->used_int_regs & (1 << X86_ESI))
2532                                 pos -= 4;
2533                         if (pos)
2534                                 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
2535
2536                         if (cfg->used_int_regs & (1 << X86_ESI))
2537                                 x86_pop_reg (code, X86_ESI);
2538                         if (cfg->used_int_regs & (1 << X86_EDI))
2539                                 x86_pop_reg (code, X86_EDI);
2540                         if (cfg->used_int_regs & (1 << X86_EBX))
2541                                 x86_pop_reg (code, X86_EBX);
2542
2543                         /* restore ESP/EBP */
2544                         x86_leave (code);
2545                         offset = code - cfg->native_code;
2546                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2547                         x86_jump32 (code, 0);
2548                         break;
2549                 }
2550                 case OP_CHECK_THIS:
2551                         /* ensure ins->sreg1 is not NULL */
2552                         x86_alu_membase_imm (code, X86_CMP, ins->sreg1, 0, 0);
2553                         break;
2554                 case OP_ARGLIST: {
2555                         int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
2556                         x86_push_reg (code, hreg);
2557                         x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
2558                         x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
2559                         x86_pop_reg (code, hreg);
2560                         break;
2561                 }
2562                 case OP_FCALL:
2563                 case OP_LCALL:
2564                 case OP_VCALL:
2565                 case OP_VOIDCALL:
2566                 case CEE_CALL:
2567                         call = (MonoCallInst*)ins;
2568                         if (ins->flags & MONO_INST_HAS_METHOD)
2569                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
2570                         else {
2571                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
2572                         }
2573                         x86_call_code (code, 0);
2574                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2575                                 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2576                         break;
2577                 case OP_FCALL_REG:
2578                 case OP_LCALL_REG:
2579                 case OP_VCALL_REG:
2580                 case OP_VOIDCALL_REG:
2581                 case OP_CALL_REG:
2582                         call = (MonoCallInst*)ins;
2583                         x86_call_reg (code, ins->sreg1);
2584                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2585                                 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2586                         break;
2587                 case OP_FCALL_MEMBASE:
2588                 case OP_LCALL_MEMBASE:
2589                 case OP_VCALL_MEMBASE:
2590                 case OP_VOIDCALL_MEMBASE:
2591                 case OP_CALL_MEMBASE:
2592                         call = (MonoCallInst*)ins;
2593                         x86_call_membase (code, ins->sreg1, ins->inst_offset);
2594                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2595                                 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2596                         break;
2597                 case OP_OUTARG:
2598                 case OP_X86_PUSH:
2599                         x86_push_reg (code, ins->sreg1);
2600                         break;
2601                 case OP_X86_PUSH_IMM:
2602                         x86_push_imm (code, ins->inst_imm);
2603                         break;
2604                 case OP_X86_PUSH_MEMBASE:
2605                         x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
2606                         break;
2607                 case OP_X86_PUSH_OBJ:
2608                         x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
2609                         x86_push_reg (code, X86_EDI);
2610                         x86_push_reg (code, X86_ESI);
2611                         x86_push_reg (code, X86_ECX);
2612                         if (ins->inst_offset)
2613                                 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
2614                         else
2615                                 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
2616                         x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2617                         x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
2618                         x86_cld (code);
2619                         x86_prefix (code, X86_REP_PREFIX);
2620                         x86_movsd (code);
2621                         x86_pop_reg (code, X86_ECX);
2622                         x86_pop_reg (code, X86_ESI);
2623                         x86_pop_reg (code, X86_EDI);
2624                         break;
2625                 case OP_X86_LEA:
2626                         x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->unused);
2627                         break;
2628                 case OP_X86_LEA_MEMBASE:
2629                         x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
2630                         break;
2631                 case OP_X86_XCHG:
2632                         x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
2633                         break;
2634                 case OP_LOCALLOC:
2635                         /* keep alignment */
2636                         x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
2637                         x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
2638                         code = mono_emit_stack_alloc (code, ins);
2639                         x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2640                         break;
2641                 case CEE_RET:
2642                         x86_ret (code);
2643                         break;
2644                 case CEE_THROW: {
2645                         x86_push_reg (code, ins->sreg1);
2646                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2647                                              (gpointer)"mono_arch_throw_exception");
2648                         x86_call_code (code, 0);
2649                         break;
2650                 }
2651                 case OP_CALL_HANDLER:
2652                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2653                         x86_call_imm (code, 0);
2654                         break;
2655                 case OP_LABEL:
2656                         ins->inst_c0 = code - cfg->native_code;
2657                         break;
2658                 case CEE_BR:
2659                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
2660                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
2661                         //break;
2662                         if (ins->flags & MONO_INST_BRLABEL) {
2663                                 if (ins->inst_i0->inst_c0) {
2664                                         x86_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
2665                                 } else {
2666                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
2667                                         x86_jump32 (code, 0);
2668                                 }
2669                         } else {
2670                                 if (ins->inst_target_bb->native_offset) {
2671                                         x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
2672                                 } else {
2673                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2674                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
2675                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
2676                                                 x86_jump8 (code, 0);
2677                                         else
2678                                                 x86_jump32 (code, 0);
2679                                 }
2680                         }
2681                         break;
2682                 case OP_BR_REG:
2683                         x86_jump_reg (code, ins->sreg1);
2684                         break;
2685                 case OP_CEQ:
2686                         x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
2687                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2688                         break;
2689                 case OP_CLT:
2690                         x86_set_reg (code, X86_CC_LT, ins->dreg, TRUE);
2691                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2692                         break;
2693                 case OP_CLT_UN:
2694                         x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
2695                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2696                         break;
2697                 case OP_CGT:
2698                         x86_set_reg (code, X86_CC_GT, ins->dreg, TRUE);
2699                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2700                         break;
2701                 case OP_CGT_UN:
2702                         x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
2703                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2704                         break;
2705                 case OP_COND_EXC_EQ:
2706                 case OP_COND_EXC_NE_UN:
2707                 case OP_COND_EXC_LT:
2708                 case OP_COND_EXC_LT_UN:
2709                 case OP_COND_EXC_GT:
2710                 case OP_COND_EXC_GT_UN:
2711                 case OP_COND_EXC_GE:
2712                 case OP_COND_EXC_GE_UN:
2713                 case OP_COND_EXC_LE:
2714                 case OP_COND_EXC_LE_UN:
2715                 case OP_COND_EXC_OV:
2716                 case OP_COND_EXC_NO:
2717                 case OP_COND_EXC_C:
2718                 case OP_COND_EXC_NC:
2719                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
2720                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
2721                         break;
2722                 case CEE_BEQ:
2723                 case CEE_BNE_UN:
2724                 case CEE_BLT:
2725                 case CEE_BLT_UN:
2726                 case CEE_BGT:
2727                 case CEE_BGT_UN:
2728                 case CEE_BGE:
2729                 case CEE_BGE_UN:
2730                 case CEE_BLE:
2731                 case CEE_BLE_UN:
2732                         EMIT_COND_BRANCH (ins, branch_cc_table [ins->opcode - CEE_BEQ], (ins->opcode < CEE_BNE_UN));
2733                         break;
2734
2735                 /* floating point opcodes */
2736                 case OP_R8CONST: {
2737                         double d = *(double *)ins->inst_p0;
2738
2739                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
2740                                 x86_fldz (code);
2741                         } else if (d == 1.0) {
2742                                 x86_fld1 (code);
2743                         } else {
2744                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
2745                                 x86_fld (code, NULL, TRUE);
2746                         }
2747                         break;
2748                 }
2749                 case OP_R4CONST: {
2750                         float f = *(float *)ins->inst_p0;
2751
2752                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
2753                                 x86_fldz (code);
2754                         } else if (f == 1.0) {
2755                                 x86_fld1 (code);
2756                         } else {
2757                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
2758                                 x86_fld (code, NULL, FALSE);
2759                         }
2760                         break;
2761                 }
2762                 case OP_STORER8_MEMBASE_REG:
2763                         x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
2764                         break;
2765                 case OP_LOADR8_SPILL_MEMBASE:
2766                         x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
2767                         x86_fxch (code, 1);
2768                         break;
2769                 case OP_LOADR8_MEMBASE:
2770                         x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
2771                         break;
2772                 case OP_STORER4_MEMBASE_REG:
2773                         x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
2774                         break;
2775                 case OP_LOADR4_MEMBASE:
2776                         x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
2777                         break;
2778                 case CEE_CONV_R4: /* FIXME: change precision */
2779                 case CEE_CONV_R8:
2780                         x86_push_reg (code, ins->sreg1);
2781                         x86_fild_membase (code, X86_ESP, 0, FALSE);
2782                         x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2783                         break;
2784                 case OP_X86_FP_LOAD_I8:
2785                         x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
2786                         break;
2787                 case OP_X86_FP_LOAD_I4:
2788                         x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
2789                         break;
2790                 case OP_FCONV_TO_I1:
2791                         code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
2792                         break;
2793                 case OP_FCONV_TO_U1:
2794                         code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
2795                         break;
2796                 case OP_FCONV_TO_I2:
2797                         code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
2798                         break;
2799                 case OP_FCONV_TO_U2:
2800                         code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
2801                         break;
2802                 case OP_FCONV_TO_I4:
2803                 case OP_FCONV_TO_I:
2804                         code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
2805                         break;
2806                 case OP_FCONV_TO_I8:
2807                         x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2808                         x86_fnstcw_membase(code, X86_ESP, 0);
2809                         x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
2810                         x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
2811                         x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
2812                         x86_fldcw_membase (code, X86_ESP, 2);
2813                         x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2814                         x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2815                         x86_pop_reg (code, ins->dreg);
2816                         x86_pop_reg (code, ins->unused);
2817                         x86_fldcw_membase (code, X86_ESP, 0);
2818                         x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2819                         break;
2820                 case OP_LCONV_TO_R_UN: {
2821                         static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
2822                         guint8 *br;
2823
2824                         /* load 64bit integer to FP stack */
2825                         x86_push_imm (code, 0);
2826                         x86_push_reg (code, ins->sreg2);
2827                         x86_push_reg (code, ins->sreg1);
2828                         x86_fild_membase (code, X86_ESP, 0, TRUE);
2829                         /* store as 80bit FP value */
2830                         x86_fst80_membase (code, X86_ESP, 0);
2831
2832                         /* test if lreg is negative */
2833                         x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
2834                         br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
2835
2836                         /* add correction constant mn */
2837                         x86_fld80_mem (code, mn);
2838                         x86_fld80_membase (code, X86_ESP, 0);
2839                         x86_fp_op_reg (code, X86_FADD, 1, TRUE);
2840                         x86_fst80_membase (code, X86_ESP, 0);
2841
2842                         x86_patch (br, code);
2843
2844                         x86_fld80_membase (code, X86_ESP, 0);
2845                         x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
2846
2847                         break;
2848                 }
2849                 case OP_LCONV_TO_OVF_I: {
2850                         guint8 *br [3], *label [1];
2851
2852                         /*
2853                          * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
2854                          */
2855                         x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2856
2857                         /* If the low word top bit is set, see if we are negative */
2858                         br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
2859                         /* We are not negative (no top bit set, check for our top word to be zero */
2860                         x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
2861                         br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2862                         label [0] = code;
2863
2864                         /* throw exception */
2865                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
2866                         x86_jump32 (code, 0);
2867
2868                         x86_patch (br [0], code);
2869                         /* our top bit is set, check that top word is 0xfffffff */
2870                         x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
2871
2872                         x86_patch (br [1], code);
2873                         /* nope, emit exception */
2874                         br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
2875                         x86_patch (br [2], label [0]);
2876
2877                         if (ins->dreg != ins->sreg1)
2878                                 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2879                         break;
2880                 }
2881                 case OP_FADD:
2882                         x86_fp_op_reg (code, X86_FADD, 1, TRUE);
2883                         break;
2884                 case OP_FSUB:
2885                         x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
2886                         break;
2887                 case OP_FMUL:
2888                         x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
2889                         break;
2890                 case OP_FDIV:
2891                         x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
2892                         break;
2893                 case OP_FNEG:
2894                         x86_fchs (code);
2895                         break;
2896                 case OP_SIN:
2897                         x86_fsin (code);
2898                         break;
2899                 case OP_COS:
2900                         x86_fcos (code);
2901                         break;
2902                 case OP_ABS:
2903                         x86_fabs (code);
2904                         break;
2905                 case OP_TAN: {
2906                         /*
2907                          * it really doesn't make sense to inline all this code,
2908                          * it's here just to show that things may not be as simple
2909                          * as they appear.
2910                          */
2911                         guchar *check_pos, *end_tan, *pop_jump;
2912                         x86_push_reg (code, X86_EAX);
2913                         x86_fptan (code);
2914                         x86_fnstsw (code);
2915                         x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
2916                         check_pos = code;
2917                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
2918                         x86_fstp (code, 0); /* pop the 1.0 */
2919                         end_tan = code;
2920                         x86_jump8 (code, 0);
2921                         x86_fldpi (code);
2922                         x86_fp_op (code, X86_FADD, 0);
2923                         x86_fxch (code, 1);
2924                         x86_fprem1 (code);
2925                         x86_fstsw (code);
2926                         x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
2927                         pop_jump = code;
2928                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
2929                         x86_fstp (code, 1);
2930                         x86_fptan (code);
2931                         x86_patch (pop_jump, code);
2932                         x86_fstp (code, 0); /* pop the 1.0 */
2933                         x86_patch (check_pos, code);
2934                         x86_patch (end_tan, code);
2935                         x86_pop_reg (code, X86_EAX);
2936                         break;
2937                 }
2938                 case OP_ATAN:
2939                         x86_fld1 (code);
2940                         x86_fpatan (code);
2941                         break;
2942                 case OP_SQRT:
2943                         x86_fsqrt (code);
2944                         break;
2945                 case OP_X86_FPOP:
2946                         x86_fstp (code, 0);
2947                         break;
2948                 case OP_FREM: {
2949                         guint8 *l1, *l2;
2950
2951                         x86_push_reg (code, X86_EAX);
2952                         /* we need to exchange ST(0) with ST(1) */
2953                         x86_fxch (code, 1);
2954
2955                         /* this requires a loop, because fprem somtimes
2956                          * returns a partial remainder */
2957                         l1 = code;
2958                         /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
2959                         /* x86_fprem1 (code); */
2960                         x86_fprem (code);
2961                         x86_fnstsw (code);
2962                         x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
2963                         l2 = code + 2;
2964                         x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
2965
2966                         /* pop result */
2967                         x86_fstp (code, 1);
2968
2969                         x86_pop_reg (code, X86_EAX);
2970                         break;
2971                 }
2972                 case OP_FCOMPARE:
2973                         if (cfg->opt & MONO_OPT_FCMOV) {
2974                                 x86_fcomip (code, 1);
2975                                 x86_fstp (code, 0);
2976                                 break;
2977                         }
2978                         /* this overwrites EAX */
2979                         EMIT_FPCOMPARE(code);
2980                         x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
2981                         break;
2982                 case OP_FCEQ:
2983                         if (cfg->opt & MONO_OPT_FCMOV) {
2984                                 /* zeroing the register at the start results in
2985                                  * shorter and faster code (we can also remove the widening op)
2986                                  */
2987                                 guchar *unordered_check;
2988                                 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2989                                 x86_fcomip (code, 1);
2990                                 x86_fstp (code, 0);
2991                                 unordered_check = code;
2992                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
2993                                 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
2994                                 x86_patch (unordered_check, code);
2995                                 break;
2996                         }
2997                         if (ins->dreg != X86_EAX)
2998                                 x86_push_reg (code, X86_EAX);
2999
3000                         EMIT_FPCOMPARE(code);
3001                         x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3002                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3003                         x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3004                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3005
3006                         if (ins->dreg != X86_EAX)
3007                                 x86_pop_reg (code, X86_EAX);
3008                         break;
3009                 case OP_FCLT:
3010                 case OP_FCLT_UN:
3011                         if (cfg->opt & MONO_OPT_FCMOV) {
3012                                 /* zeroing the register at the start results in
3013                                  * shorter and faster code (we can also remove the widening op)
3014                                  */
3015                                 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3016                                 x86_fcomip (code, 1);
3017                                 x86_fstp (code, 0);
3018                                 if (ins->opcode == OP_FCLT_UN) {
3019                                         guchar *unordered_check = code;
3020                                         guchar *jump_to_end;
3021                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3022                                         x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3023                                         jump_to_end = code;
3024                                         x86_jump8 (code, 0);
3025                                         x86_patch (unordered_check, code);
3026                                         x86_inc_reg (code, ins->dreg);
3027                                         x86_patch (jump_to_end, code);
3028                                 } else {
3029                                         x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3030                                 }
3031                                 break;
3032                         }
3033                         if (ins->dreg != X86_EAX)
3034                                 x86_push_reg (code, X86_EAX);
3035
3036                         EMIT_FPCOMPARE(code);
3037                         x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3038                         if (ins->opcode == OP_FCLT_UN) {
3039                                 guchar *is_not_zero_check, *end_jump;
3040                                 is_not_zero_check = code;
3041                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3042                                 end_jump = code;
3043                                 x86_jump8 (code, 0);
3044                                 x86_patch (is_not_zero_check, code);
3045                                 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3046
3047                                 x86_patch (end_jump, code);
3048                         }
3049                         x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3050                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3051
3052                         if (ins->dreg != X86_EAX)
3053                                 x86_pop_reg (code, X86_EAX);
3054                         break;
3055                 case OP_FCGT:
3056                 case OP_FCGT_UN:
3057                         if (cfg->opt & MONO_OPT_FCMOV) {
3058                                 /* zeroing the register at the start results in
3059                                  * shorter and faster code (we can also remove the widening op)
3060                                  */
3061                                 guchar *unordered_check;
3062                                 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3063                                 x86_fcomip (code, 1);
3064                                 x86_fstp (code, 0);
3065                                 if (ins->opcode == OP_FCGT) {
3066                                         unordered_check = code;
3067                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3068                                         x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3069                                         x86_patch (unordered_check, code);
3070                                 } else {
3071                                         x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3072                                 }
3073                                 break;
3074                         }
3075                         if (ins->dreg != X86_EAX)
3076                                 x86_push_reg (code, X86_EAX);
3077
3078                         EMIT_FPCOMPARE(code);
3079                         x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3080                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3081                         if (ins->opcode == OP_FCGT_UN) {
3082                                 guchar *is_not_zero_check, *end_jump;
3083                                 is_not_zero_check = code;
3084                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3085                                 end_jump = code;
3086                                 x86_jump8 (code, 0);
3087                                 x86_patch (is_not_zero_check, code);
3088                                 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3089
3090                                 x86_patch (end_jump, code);
3091                         }
3092                         x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3093                         x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3094
3095                         if (ins->dreg != X86_EAX)
3096                                 x86_pop_reg (code, X86_EAX);
3097                         break;
3098                 case OP_FBEQ:
3099                         if (cfg->opt & MONO_OPT_FCMOV) {
3100                                 guchar *jump = code;
3101                                 x86_branch8 (code, X86_CC_P, 0, TRUE);
3102                                 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3103                                 x86_patch (jump, code);
3104                                 break;
3105                         }
3106                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3107                         EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3108                         break;
3109                 case OP_FBNE_UN:
3110                         /* Branch if C013 != 100 */
3111                         if (cfg->opt & MONO_OPT_FCMOV) {
3112                                 /* branch if !ZF or (PF|CF) */
3113                                 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3114                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3115                                 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3116                                 break;
3117                         }
3118                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3119                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3120                         break;
3121                 case OP_FBLT:
3122                         if (cfg->opt & MONO_OPT_FCMOV) {
3123                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3124                                 break;
3125                         }
3126                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3127                         break;
3128                 case OP_FBLT_UN:
3129                         if (cfg->opt & MONO_OPT_FCMOV) {
3130                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3131                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3132                                 break;
3133                         }
3134                         if (ins->opcode == OP_FBLT_UN) {
3135                                 guchar *is_not_zero_check, *end_jump;
3136                                 is_not_zero_check = code;
3137                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3138                                 end_jump = code;
3139                                 x86_jump8 (code, 0);
3140                                 x86_patch (is_not_zero_check, code);
3141                                 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3142
3143                                 x86_patch (end_jump, code);
3144                         }
3145                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3146                         break;
3147                 case OP_FBGT:
3148                 case OP_FBGT_UN:
3149                         if (cfg->opt & MONO_OPT_FCMOV) {
3150                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3151                                 break;
3152                         }
3153                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3154                         if (ins->opcode == OP_FBGT_UN) {
3155                                 guchar *is_not_zero_check, *end_jump;
3156                                 is_not_zero_check = code;
3157                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3158                                 end_jump = code;
3159                                 x86_jump8 (code, 0);
3160                                 x86_patch (is_not_zero_check, code);
3161                                 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3162
3163                                 x86_patch (end_jump, code);
3164                         }
3165                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3166                         break;
3167                 case OP_FBGE:
3168                         /* Branch if C013 == 100 or 001 */
3169                         if (cfg->opt & MONO_OPT_FCMOV) {
3170                                 guchar *br1;
3171
3172                                 /* skip branch if C1=1 */
3173                                 br1 = code;
3174                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3175                                 /* branch if (C0 | C3) = 1 */
3176                                 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3177                                 x86_patch (br1, code);
3178                                 break;
3179                         }
3180                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3181                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3182                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3183                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3184                         break;
3185                 case OP_FBGE_UN:
3186                         /* Branch if C013 == 000 */
3187                         if (cfg->opt & MONO_OPT_FCMOV) {
3188                                 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3189                                 break;
3190                         }
3191                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3192                         break;
3193                 case OP_FBLE:
3194                         /* Branch if C013=000 or 100 */
3195                         if (cfg->opt & MONO_OPT_FCMOV) {
3196                                 guchar *br1;
3197
3198                                 /* skip branch if C1=1 */
3199                                 br1 = code;
3200                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3201                                 /* branch if C0=0 */
3202                                 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3203                                 x86_patch (br1, code);
3204                                 break;
3205                         }
3206                         x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
3207                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
3208                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3209                         break;
3210                 case OP_FBLE_UN:
3211                         /* Branch if C013 != 001 */
3212                         if (cfg->opt & MONO_OPT_FCMOV) {
3213                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3214                                 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3215                                 break;
3216                         }
3217                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3218                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3219                         break;
3220                 case CEE_CKFINITE: {
3221                         x86_push_reg (code, X86_EAX);
3222                         x86_fxam (code);
3223                         x86_fnstsw (code);
3224                         x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
3225                         x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3226                         x86_pop_reg (code, X86_EAX);
3227                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3228                         break;
3229                 }
3230                 default:
3231                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3232                         g_assert_not_reached ();
3233                 }
3234
3235                 if ((code - cfg->native_code - offset) > max_len) {
3236                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
3237                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
3238                         g_assert_not_reached ();
3239                 }
3240
3241                 cpos += max_len;
3242
3243                 last_ins = ins;
3244                 last_offset = offset;
3245
3246                 ins = ins->next;
3247         }
3248
3249         cfg->code_len = code - cfg->native_code;
3250 }
3251
3252 void
3253 mono_arch_register_lowlevel_calls (void)
3254 {
3255         mono_register_jit_icall (mono_arch_get_lmf_addr, "mono_arch_get_lmf_addr", NULL, TRUE);
3256 }
3257
3258 void
3259 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3260 {
3261         MonoJumpInfo *patch_info;
3262
3263         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3264                 unsigned char *ip = patch_info->ip.i + code;
3265                 const unsigned char *target;
3266
3267                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3268
3269                 switch (patch_info->type) {
3270                 case MONO_PATCH_INFO_IP:
3271                         *((gconstpointer *)(ip)) = target;
3272                         continue;
3273                 case MONO_PATCH_INFO_METHOD_REL:
3274                         *((gconstpointer *)(ip)) = target;
3275                         continue;
3276                 case MONO_PATCH_INFO_SWITCH: {
3277                         *((gconstpointer *)(ip + 2)) = target;
3278                         /* we put into the table the absolute address, no need for x86_patch in this case */
3279                         continue;
3280                 }
3281                 case MONO_PATCH_INFO_IID:
3282                         *((guint32 *)(ip + 1)) = (guint32)target;
3283                         continue;
3284                 case MONO_PATCH_INFO_CLASS_INIT: {
3285                         guint8 *code = ip;
3286                         /* Might already been changed to a nop */
3287                         x86_call_imm (code, 0);
3288                         break;
3289                 }
3290                 case MONO_PATCH_INFO_R4:
3291                 case MONO_PATCH_INFO_R8:
3292                         *((gconstpointer *)(ip + 2)) = target;
3293                         continue;
3294                 case MONO_PATCH_INFO_METHODCONST:
3295                 case MONO_PATCH_INFO_CLASS:
3296                 case MONO_PATCH_INFO_IMAGE:
3297                 case MONO_PATCH_INFO_FIELD:
3298                 case MONO_PATCH_INFO_VTABLE:
3299                 case MONO_PATCH_INFO_SFLDA:
3300                 case MONO_PATCH_INFO_EXC_NAME:
3301                 case MONO_PATCH_INFO_LDSTR:
3302                 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
3303                 case MONO_PATCH_INFO_LDTOKEN:
3304                         *((gconstpointer *)(ip + 1)) = target;
3305                         continue;
3306                 default:
3307                         break;
3308                 }
3309                 x86_patch (ip, target);
3310         }
3311 }
3312
3313 int
3314 mono_arch_max_epilog_size (MonoCompile *cfg)
3315 {
3316         int exc_count = 0, max_epilog_size = 16;
3317         MonoJumpInfo *patch_info;
3318
3319         if (cfg->method->save_lmf)
3320                 max_epilog_size += 128;
3321
3322         if (mono_jit_trace_calls != NULL)
3323                 max_epilog_size += 50;
3324
3325         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3326                 max_epilog_size += 50;
3327
3328         /* count the number of exception infos */
3329
3330         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
3331                 if (patch_info->type == MONO_PATCH_INFO_EXC)
3332                         exc_count++;
3333         }
3334
3335         /*
3336          * make sure we have enough space for exceptions
3337          * 16 is the size of two push_imm instructions and a call
3338          */
3339         max_epilog_size += exc_count*16;
3340
3341         return max_epilog_size;
3342 }
3343
3344 guint8 *
3345 mono_arch_emit_prolog (MonoCompile *cfg)
3346 {
3347         MonoMethod *method = cfg->method;
3348         MonoBasicBlock *bb;
3349         MonoMethodSignature *sig;
3350         MonoInst *inst;
3351         int alloc_size, pos, max_offset, i;
3352         guint8 *code;
3353
3354         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 256);
3355         code = cfg->native_code = g_malloc (cfg->code_size);
3356
3357         x86_push_reg (code, X86_EBP);
3358         x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
3359
3360         alloc_size = - cfg->stack_offset;
3361         pos = 0;
3362
3363         if (method->save_lmf) {
3364                 pos += sizeof (MonoLMF);
3365
3366                 /* save the current IP */
3367                 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
3368                 x86_push_imm (code, 0);
3369
3370                 /* save all caller saved regs */
3371                 x86_push_reg (code, X86_EBP);
3372                 x86_push_reg (code, X86_ESI);
3373                 x86_push_reg (code, X86_EDI);
3374                 x86_push_reg (code, X86_EBX);
3375
3376                 /* save method info */
3377                 x86_push_imm (code, method);
3378
3379                 /* get the address of lmf for the current thread */
3380                 /*
3381                  * This is performance critical so we try to use some tricks to make
3382                  * it fast.
3383                  */
3384                 if (lmf_tls_offset != -1) {
3385                         /* Load lmf quicky using the GS register */
3386                         x86_prefix (code, X86_GS_PREFIX);
3387                         x86_mov_reg_mem (code, X86_EAX, 0, 4);
3388                         x86_mov_reg_membase (code, X86_EAX, X86_EAX, lmf_tls_offset, 4);
3389                 }
3390                 else {
3391 #ifdef HAVE_KW_THREAD
3392                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3393                                                                  (gpointer)"mono_arch_get_lmf_addr");
3394 #else
3395                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3396                                                                  (gpointer)"mono_get_lmf_addr");
3397 #endif
3398                         x86_call_code (code, 0);
3399                 }
3400
3401                 /* push lmf */
3402                 x86_push_reg (code, X86_EAX);
3403                 /* push *lfm (previous_lmf) */
3404                 x86_push_membase (code, X86_EAX, 0);
3405                 /* *(lmf) = ESP */
3406                 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
3407         } else {
3408
3409                 if (cfg->used_int_regs & (1 << X86_EBX)) {
3410                         x86_push_reg (code, X86_EBX);
3411                         pos += 4;
3412                 }
3413
3414                 if (cfg->used_int_regs & (1 << X86_EDI)) {
3415                         x86_push_reg (code, X86_EDI);
3416                         pos += 4;
3417                 }
3418
3419                 if (cfg->used_int_regs & (1 << X86_ESI)) {
3420                         x86_push_reg (code, X86_ESI);
3421                         pos += 4;
3422                 }
3423         }
3424
3425         alloc_size -= pos;
3426
3427         if (alloc_size) {
3428                 /* See mono_emit_stack_alloc */
3429 #ifdef PLATFORM_WIN32
3430                 guint32 remaining_size = alloc_size;
3431                 while (remaining_size >= 0x1000) {
3432                         x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
3433                         x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
3434                         remaining_size -= 0x1000;
3435                 }
3436                 if (remaining_size)
3437                         x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
3438 #else
3439                 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
3440 #endif
3441         }
3442
3443         /* compute max_offset in order to use short forward jumps */
3444         max_offset = 0;
3445         if (cfg->opt & MONO_OPT_BRANCH) {
3446                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
3447                         MonoInst *ins = bb->code;
3448                         bb->max_offset = max_offset;
3449
3450                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
3451                                 max_offset += 6;
3452                         /* max alignment for loops */
3453                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
3454                                 max_offset += LOOP_ALIGNMENT;
3455
3456                         while (ins) {
3457                                 max_offset += ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
3458                                 ins = ins->next;
3459                         }
3460                 }
3461         }
3462
3463         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3464                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
3465
3466         /* load arguments allocated to register from the stack */
3467         sig = method->signature;
3468         pos = 0;
3469
3470         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3471                 inst = cfg->varinfo [pos];
3472                 if (inst->opcode == OP_REGVAR) {
3473                         x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
3474                         if (cfg->verbose_level > 2)
3475                                 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
3476                 }
3477                 pos++;
3478         }
3479
3480         cfg->code_len = code - cfg->native_code;
3481
3482         return code;
3483 }
3484
3485 void
3486 mono_arch_emit_epilog (MonoCompile *cfg)
3487 {
3488         MonoJumpInfo *patch_info;
3489         MonoMethod *method = cfg->method;
3490         MonoMethodSignature *sig = method->signature;
3491         int pos;
3492         guint32 stack_to_pop;
3493         guint8 *code;
3494
3495         code = cfg->native_code + cfg->code_len;
3496
3497         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3498                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
3499
3500         /* the code restoring the registers must be kept in sync with CEE_JMP */
3501         pos = 0;
3502
3503         if (method->save_lmf) {
3504                 gint32 prev_lmf_reg;
3505
3506                 /* Find a spare register */
3507                 switch (sig->ret->type) {
3508                 case MONO_TYPE_I8:
3509                 case MONO_TYPE_U8:
3510                         prev_lmf_reg = X86_EDI;
3511                         cfg->used_int_regs |= (1 << X86_EDI);
3512                         break;
3513                 default:
3514                         prev_lmf_reg = X86_EDX;
3515                         break;
3516                 }
3517
3518                 /* reg = previous_lmf */
3519                 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, -32, 4);
3520
3521                 /* ecx = lmf */
3522                 x86_mov_reg_membase (code, X86_ECX, X86_EBP, -28, 4);
3523
3524                 /* *(lmf) = previous_lmf */
3525                 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
3526
3527                 /* restore caller saved regs */
3528                 if (cfg->used_int_regs & (1 << X86_EBX)) {
3529                         x86_mov_reg_membase (code, X86_EBX, X86_EBP, -20, 4);
3530                 }
3531
3532                 if (cfg->used_int_regs & (1 << X86_EDI)) {
3533                         x86_mov_reg_membase (code, X86_EDI, X86_EBP, -16, 4);
3534                 }
3535                 if (cfg->used_int_regs & (1 << X86_ESI)) {
3536                         x86_mov_reg_membase (code, X86_ESI, X86_EBP, -12, 4);
3537                 }
3538
3539                 /* EBP is restored by LEAVE */
3540         } else {
3541                 if (cfg->used_int_regs & (1 << X86_EBX)) {
3542                         pos -= 4;
3543                 }
3544                 if (cfg->used_int_regs & (1 << X86_EDI)) {
3545                         pos -= 4;
3546                 }
3547                 if (cfg->used_int_regs & (1 << X86_ESI)) {
3548                         pos -= 4;
3549                 }
3550
3551                 if (pos)
3552                         x86_lea_membase (code, X86_ESP, X86_EBP, pos);
3553
3554                 if (cfg->used_int_regs & (1 << X86_ESI)) {
3555                         x86_pop_reg (code, X86_ESI);
3556                 }
3557                 if (cfg->used_int_regs & (1 << X86_EDI)) {
3558                         x86_pop_reg (code, X86_EDI);
3559                 }
3560                 if (cfg->used_int_regs & (1 << X86_EBX)) {
3561                         x86_pop_reg (code, X86_EBX);
3562                 }
3563         }
3564
3565         x86_leave (code);
3566
3567         if (CALLCONV_IS_STDCALL (sig->call_convention)) {
3568                 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
3569
3570                 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
3571         } else if (MONO_TYPE_ISSTRUCT (cfg->method->signature->ret))
3572                 stack_to_pop = 4;
3573         else
3574                 stack_to_pop = 0;
3575
3576         if (stack_to_pop)
3577                 x86_ret_imm (code, stack_to_pop);
3578         else
3579                 x86_ret (code);
3580
3581         /* add code to raise exceptions */
3582         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
3583                 switch (patch_info->type) {
3584                 case MONO_PATCH_INFO_EXC:
3585                         x86_patch (patch_info->ip.i + cfg->native_code, code);
3586                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC_NAME, patch_info->data.target);
3587                         x86_push_imm (code, patch_info->data.target);
3588                         mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_METHOD_REL, (gpointer)patch_info->ip.i);
3589                         x86_push_imm (code, patch_info->ip.i + cfg->native_code);
3590                         patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
3591                         patch_info->data.name = "mono_arch_throw_exception_by_name";
3592                         patch_info->ip.i = code - cfg->native_code;
3593                         x86_jump_code (code, 0);
3594                         break;
3595                 default:
3596                         /* do nothing */
3597                         break;
3598                 }
3599         }
3600
3601         cfg->code_len = code - cfg->native_code;
3602
3603         g_assert (cfg->code_len < cfg->code_size);
3604
3605 }
3606
3607 void
3608 mono_arch_flush_icache (guint8 *code, gint size)
3609 {
3610         /* not needed */
3611 }
3612
3613 void
3614 mono_arch_flush_register_windows (void)
3615 {
3616 }
3617
3618 /*
3619  * Support for fast access to the thread-local lmf structure using the GS
3620  * segment register on NPTL + kernel 2.6.x.
3621  */
3622
3623 static gboolean tls_offset_inited = FALSE;
3624
3625 #ifdef HAVE_KW_THREAD
3626 static __thread gpointer mono_lmf_addr;
3627 #endif
3628
3629 static gpointer
3630 mono_arch_get_lmf_addr (void)
3631 {
3632 #ifdef HAVE_KW_THREAD
3633         return mono_lmf_addr;
3634 #else
3635         g_assert_not_reached ();
3636         return NULL;
3637 #endif
3638 }
3639
3640 void
3641 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
3642 {
3643 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3644         pthread_t self = pthread_self();
3645         pthread_attr_t attr;
3646         void *staddr = NULL;
3647         size_t stsize = 0;
3648         struct sigaltstack sa;
3649 #endif
3650
3651         if (!tls_offset_inited) {
3652                 guint8 *code;
3653
3654                 tls_offset_inited = TRUE;
3655
3656                 if (getenv ("MONO_NPTL")) {
3657                         /*
3658                          * Determine the offset of mono_lfm_addr inside the TLS structures
3659                          * by disassembling the function above.
3660                          */
3661                         code = (guint8*)&mono_arch_get_lmf_addr;
3662
3663                         /* This is generated by gcc 3.3.2 */
3664                         if ((code [0] == 0x55) && (code [1] == 0x89) && (code [2] == 0xe5) &&
3665                                 (code [3] == 0x65) && (code [4] == 0xa1) && (code [5] == 0x00) &&
3666                                 (code [6] == 0x00) && (code [7] == 0x00) && (code [8] == 0x00) &&
3667                                 (code [9] == 0x8b) && (code [10] == 0x80)) {
3668                                 lmf_tls_offset = *(int*)&(code [11]);
3669                         }
3670                         else
3671                                 /* This is generated by gcc-3.4 */
3672                                 if ((code [0] == 0x55) && (code [1] == 0x89) && (code [2] == 0xe5) &&
3673                                         (code [3] == 0x65) && (code [4] == 0xa1)) {
3674                                         lmf_tls_offset = *(int*)&(code [5]);
3675                                 }
3676                 }
3677         }
3678
3679 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3680
3681         /* Determine stack boundaries */
3682         if (!mono_running_on_valgrind ()) {
3683 #ifdef HAVE_PTHREAD_GETATTR_NP
3684                 pthread_getattr_np( self, &attr );
3685 #else
3686 #ifdef HAVE_PTHREAD_ATTR_GET_NP
3687                 pthread_attr_get_np( self, &attr );
3688 #else
3689 #error "Not implemented"
3690 #endif
3691 #endif
3692                 pthread_attr_getstack( &attr, &staddr, &stsize );
3693         }
3694
3695         /*
3696          * staddr seems to be wrong for the main thread, so we keep the value in
3697          * tls->end_of_stack
3698          */
3699         tls->stack_size = stsize;
3700
3701         /* Setup an alternate signal stack */
3702         tls->signal_stack = g_malloc (SIGNAL_STACK_SIZE);
3703         tls->signal_stack_size = SIGNAL_STACK_SIZE;
3704
3705         sa.ss_sp = tls->signal_stack;
3706         sa.ss_size = SIGNAL_STACK_SIZE;
3707         sa.ss_flags = SS_ONSTACK;
3708         sigaltstack (&sa, NULL);
3709 #endif
3710
3711 #ifdef HAVE_KW_THREAD
3712         mono_lmf_addr = &tls->lmf;
3713 #endif
3714 }
3715
3716 void
3717 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
3718 {
3719 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3720         struct sigaltstack sa;
3721
3722         sa.ss_sp = tls->signal_stack;
3723         sa.ss_size = SIGNAL_STACK_SIZE;
3724         sa.ss_flags = SS_DISABLE;
3725         sigaltstack  (&sa, NULL);
3726
3727         if (tls->signal_stack)
3728                 g_free (tls->signal_stack);
3729 #endif
3730 }
3731
3732 void
3733 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
3734 {
3735
3736         /* add the this argument */
3737         if (this_reg != -1) {
3738                 MonoInst *this;
3739                 MONO_INST_NEW (cfg, this, OP_OUTARG);
3740                 this->type = this_type;
3741                 this->sreg1 = this_reg;
3742                 mono_bblock_add_inst (cfg->cbb, this);
3743         }
3744
3745         if (vt_reg != -1) {
3746                 MonoInst *vtarg;
3747                 MONO_INST_NEW (cfg, vtarg, OP_OUTARG);
3748                 vtarg->type = STACK_MP;
3749                 vtarg->sreg1 = vt_reg;
3750                 mono_bblock_add_inst (cfg->cbb, vtarg);
3751         }
3752 }
3753
3754
3755 gint
3756 mono_arch_get_opcode_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
3757 {
3758         if (cmethod->klass == mono_defaults.math_class) {
3759                 if (strcmp (cmethod->name, "Sin") == 0)
3760                         return OP_SIN;
3761                 else if (strcmp (cmethod->name, "Cos") == 0)
3762                         return OP_COS;
3763                 else if (strcmp (cmethod->name, "Tan") == 0)
3764                         return OP_TAN;
3765                 else if (strcmp (cmethod->name, "Atan") == 0)
3766                         return OP_ATAN;
3767                 else if (strcmp (cmethod->name, "Sqrt") == 0)
3768                         return OP_SQRT;
3769                 else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8)
3770                         return OP_ABS;
3771 #if 0
3772                 /* OP_FREM is not IEEE compatible */
3773                 else if (strcmp (cmethod->name, "IEEERemainder") == 0)
3774                         return OP_FREM;
3775 #endif
3776                 else
3777                         return -1;
3778         } else {
3779                 return -1;
3780         }
3781         return -1;
3782 }
3783
3784
3785 gboolean
3786 mono_arch_print_tree (MonoInst *tree, int arity)
3787 {
3788         return 0;
3789 }