2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/appdomain.h>
21 #include <mono/metadata/debug-helpers.h>
22 #include <mono/metadata/threads.h>
23 #include <mono/metadata/profiler-private.h>
24 #include <mono/metadata/mono-debug.h>
25 #include <mono/metadata/gc-internal.h>
26 #include <mono/utils/mono-math.h>
27 #include <mono/utils/mono-counters.h>
28 #include <mono/utils/mono-mmap.h>
29 #include <mono/utils/mono-memory-model.h>
30 #include <mono/utils/mono-hwcap-x86.h>
38 /* On windows, these hold the key returned by TlsAlloc () */
39 static gint lmf_tls_offset = -1;
41 static gint jit_tls_offset = -1;
43 static gint lmf_addr_tls_offset = -1;
47 static gboolean optimize_for_xen = TRUE;
49 #define optimize_for_xen 0
53 static gboolean is_win32 = TRUE;
55 static gboolean is_win32 = FALSE;
58 /* This mutex protects architecture specific caches */
59 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
60 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
61 static CRITICAL_SECTION mini_arch_mutex;
63 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
68 /* Under windows, the default pinvoke calling convention is stdcall */
69 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
71 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
74 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
77 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
80 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
82 #ifdef __native_client_codegen__
84 /* Default alignment for Native Client is 32-byte. */
85 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
87 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
88 /* Check that alignment doesn't cross an alignment boundary. */
90 mono_arch_nacl_pad (guint8 *code, int pad)
92 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
94 if (pad == 0) return code;
95 /* assertion: alignment cannot cross a block boundary */
96 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
97 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
98 while (pad >= kMaxPadding) {
99 x86_padding (code, kMaxPadding);
102 if (pad != 0) x86_padding (code, pad);
107 mono_arch_nacl_skip_nops (guint8 *code)
109 x86_skip_nops (code);
113 #endif /* __native_client_codegen__ */
116 * The code generated for sequence points reads from this location, which is
117 * made read-only when single stepping is enabled.
119 static gpointer ss_trigger_page;
121 /* Enabled breakpoints read from this trigger page */
122 static gpointer bp_trigger_page;
125 mono_arch_regname (int reg)
128 case X86_EAX: return "%eax";
129 case X86_EBX: return "%ebx";
130 case X86_ECX: return "%ecx";
131 case X86_EDX: return "%edx";
132 case X86_ESP: return "%esp";
133 case X86_EBP: return "%ebp";
134 case X86_EDI: return "%edi";
135 case X86_ESI: return "%esi";
141 mono_arch_fregname (int reg)
166 mono_arch_xregname (int reg)
191 mono_x86_patch (unsigned char* code, gpointer target)
193 x86_patch (code, (unsigned char*)target);
204 /* gsharedvt argument passed by addr */
216 /* Only if storage == ArgValuetypeInReg */
217 ArgStorage pair_storage [2];
226 gboolean need_stack_align;
227 guint32 stack_align_amount;
228 gboolean vtype_retaddr;
229 /* The index of the vret arg in the argument list */
237 #define FLOAT_PARAM_REGS 0
239 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
241 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
246 switch (sig->call_convention) {
247 case MONO_CALL_THISCALL:
248 return thiscall_param_regs;
254 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
255 #define SMALL_STRUCTS_IN_REGS
256 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
260 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
262 ainfo->offset = *stack_size;
264 if (!param_regs || param_regs [*gr] == X86_NREG) {
265 ainfo->storage = ArgOnStack;
267 (*stack_size) += sizeof (gpointer);
270 ainfo->storage = ArgInIReg;
271 ainfo->reg = param_regs [*gr];
277 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
279 ainfo->offset = *stack_size;
281 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
283 ainfo->storage = ArgOnStack;
284 (*stack_size) += sizeof (gpointer) * 2;
289 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
291 ainfo->offset = *stack_size;
293 if (*gr >= FLOAT_PARAM_REGS) {
294 ainfo->storage = ArgOnStack;
295 (*stack_size) += is_double ? 8 : 4;
296 ainfo->nslots = is_double ? 2 : 1;
299 /* A double register */
301 ainfo->storage = ArgInDoubleSSEReg;
303 ainfo->storage = ArgInFloatSSEReg;
311 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
313 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
318 klass = mono_class_from_mono_type (type);
319 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
321 #ifdef SMALL_STRUCTS_IN_REGS
322 if (sig->pinvoke && is_return) {
323 MonoMarshalType *info;
326 * the exact rules are not very well documented, the code below seems to work with the
327 * code generated by gcc 3.3.3 -mno-cygwin.
329 info = mono_marshal_load_type_info (klass);
332 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
334 /* Special case structs with only a float member */
335 if (info->num_fields == 1) {
336 int ftype = info->fields [0].field->type->type;
337 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
338 ainfo->storage = ArgValuetypeInReg;
339 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
342 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
343 ainfo->storage = ArgValuetypeInReg;
344 ainfo->pair_storage [0] = ArgOnFloatFpStack;
348 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
349 ainfo->storage = ArgValuetypeInReg;
350 ainfo->pair_storage [0] = ArgInIReg;
351 ainfo->pair_regs [0] = return_regs [0];
352 if (info->native_size > 4) {
353 ainfo->pair_storage [1] = ArgInIReg;
354 ainfo->pair_regs [1] = return_regs [1];
361 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
362 g_assert (size <= 4);
363 ainfo->storage = ArgValuetypeInReg;
364 ainfo->reg = param_regs [*gr];
369 ainfo->offset = *stack_size;
370 ainfo->storage = ArgOnStack;
371 *stack_size += ALIGN_TO (size, sizeof (gpointer));
372 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
378 * Obtain information about a call according to the calling convention.
379 * For x86 ELF, see the "System V Application Binary Interface Intel386
380 * Architecture Processor Supplment, Fourth Edition" document for more
382 * For x86 win32, see ???.
385 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
387 guint32 i, gr, fr, pstart;
388 const guint32 *param_regs;
390 int n = sig->hasthis + sig->param_count;
391 guint32 stack_size = 0;
392 gboolean is_pinvoke = sig->pinvoke;
398 param_regs = callconv_param_regs(sig);
402 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
403 switch (ret_type->type) {
404 case MONO_TYPE_BOOLEAN:
415 case MONO_TYPE_FNPTR:
416 case MONO_TYPE_CLASS:
417 case MONO_TYPE_OBJECT:
418 case MONO_TYPE_SZARRAY:
419 case MONO_TYPE_ARRAY:
420 case MONO_TYPE_STRING:
421 cinfo->ret.storage = ArgInIReg;
422 cinfo->ret.reg = X86_EAX;
426 cinfo->ret.storage = ArgInIReg;
427 cinfo->ret.reg = X86_EAX;
428 cinfo->ret.is_pair = TRUE;
431 cinfo->ret.storage = ArgOnFloatFpStack;
434 cinfo->ret.storage = ArgOnDoubleFpStack;
436 case MONO_TYPE_GENERICINST:
437 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
438 cinfo->ret.storage = ArgInIReg;
439 cinfo->ret.reg = X86_EAX;
442 if (mini_is_gsharedvt_type_gsctx (gsctx, ret_type)) {
443 cinfo->ret.storage = ArgOnStack;
444 cinfo->vtype_retaddr = TRUE;
448 case MONO_TYPE_VALUETYPE:
449 case MONO_TYPE_TYPEDBYREF: {
450 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
452 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
453 if (cinfo->ret.storage == ArgOnStack) {
454 cinfo->vtype_retaddr = TRUE;
455 /* The caller passes the address where the value is stored */
461 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ret_type));
462 cinfo->ret.storage = ArgOnStack;
463 cinfo->vtype_retaddr = TRUE;
466 cinfo->ret.storage = ArgNone;
469 g_error ("Can't handle as return value 0x%x", ret_type->type);
475 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
476 * the first argument, allowing 'this' to be always passed in the first arg reg.
477 * Also do this if the first argument is a reference type, since virtual calls
478 * are sometimes made using calli without sig->hasthis set, like in the delegate
481 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
483 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
485 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
488 cinfo->vret_arg_offset = stack_size;
489 add_general (&gr, NULL, &stack_size, &cinfo->ret);
490 cinfo->vret_arg_index = 1;
494 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
496 if (cinfo->vtype_retaddr)
497 add_general (&gr, NULL, &stack_size, &cinfo->ret);
500 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
501 fr = FLOAT_PARAM_REGS;
503 /* Emit the signature cookie just before the implicit arguments */
504 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
507 for (i = pstart; i < sig->param_count; ++i) {
508 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
511 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
512 /* We allways pass the sig cookie on the stack for simplicity */
514 * Prevent implicit arguments + the sig cookie from being passed
517 fr = FLOAT_PARAM_REGS;
519 /* Emit the signature cookie just before the implicit arguments */
520 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
523 if (sig->params [i]->byref) {
524 add_general (&gr, param_regs, &stack_size, ainfo);
527 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
528 switch (ptype->type) {
529 case MONO_TYPE_BOOLEAN:
532 add_general (&gr, param_regs, &stack_size, ainfo);
537 add_general (&gr, param_regs, &stack_size, ainfo);
541 add_general (&gr, param_regs, &stack_size, ainfo);
546 case MONO_TYPE_FNPTR:
547 case MONO_TYPE_CLASS:
548 case MONO_TYPE_OBJECT:
549 case MONO_TYPE_STRING:
550 case MONO_TYPE_SZARRAY:
551 case MONO_TYPE_ARRAY:
552 add_general (&gr, param_regs, &stack_size, ainfo);
554 case MONO_TYPE_GENERICINST:
555 if (!mono_type_generic_inst_is_valuetype (ptype)) {
556 add_general (&gr, param_regs, &stack_size, ainfo);
559 if (mini_is_gsharedvt_type_gsctx (gsctx, ptype)) {
560 /* gsharedvt arguments are passed by ref */
561 add_general (&gr, param_regs, &stack_size, ainfo);
562 g_assert (ainfo->storage == ArgOnStack);
563 ainfo->storage = ArgGSharedVt;
567 case MONO_TYPE_VALUETYPE:
568 case MONO_TYPE_TYPEDBYREF:
569 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
573 add_general_pair (&gr, param_regs, &stack_size, ainfo);
576 add_float (&fr, &stack_size, ainfo, FALSE);
579 add_float (&fr, &stack_size, ainfo, TRUE);
583 /* gsharedvt arguments are passed by ref */
584 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ptype));
585 add_general (&gr, param_regs, &stack_size, ainfo);
586 g_assert (ainfo->storage == ArgOnStack);
587 ainfo->storage = ArgGSharedVt;
590 g_error ("unexpected type 0x%x", ptype->type);
591 g_assert_not_reached ();
595 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
596 fr = FLOAT_PARAM_REGS;
598 /* Emit the signature cookie just before the implicit arguments */
599 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
602 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
603 cinfo->need_stack_align = TRUE;
604 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
605 stack_size += cinfo->stack_align_amount;
608 cinfo->stack_usage = stack_size;
609 cinfo->reg_usage = gr;
610 cinfo->freg_usage = fr;
615 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
617 int n = sig->hasthis + sig->param_count;
621 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
623 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
625 return get_call_info_internal (gsctx, cinfo, sig);
629 * mono_arch_get_argument_info:
630 * @csig: a method signature
631 * @param_count: the number of parameters to consider
632 * @arg_info: an array to store the result infos
634 * Gathers information on parameters such as size, alignment and
635 * padding. arg_info should be large enought to hold param_count + 1 entries.
637 * Returns the size of the argument area on the stack.
638 * This should be signal safe, since it is called from
639 * mono_arch_find_jit_info ().
640 * FIXME: The metadata calls might not be signal safe.
643 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
645 int len, k, args_size = 0;
651 /* Avoid g_malloc as it is not signal safe */
652 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
653 cinfo = (CallInfo*)g_newa (guint8*, len);
654 memset (cinfo, 0, len);
656 cinfo = get_call_info_internal (gsctx, cinfo, csig);
658 arg_info [0].offset = offset;
660 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
661 args_size += sizeof (gpointer);
666 args_size += sizeof (gpointer);
670 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
671 /* Emitted after this */
672 args_size += sizeof (gpointer);
676 arg_info [0].size = args_size;
678 for (k = 0; k < param_count; k++) {
679 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
681 /* ignore alignment for now */
684 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
685 arg_info [k].pad = pad;
687 arg_info [k + 1].pad = 0;
688 arg_info [k + 1].size = size;
690 arg_info [k + 1].offset = offset;
693 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
694 /* Emitted after the first arg */
695 args_size += sizeof (gpointer);
700 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
701 align = MONO_ARCH_FRAME_ALIGNMENT;
704 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
705 arg_info [k].pad = pad;
711 mono_arch_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
713 MonoType *callee_ret;
717 c1 = get_call_info (NULL, NULL, caller_sig);
718 c2 = get_call_info (NULL, NULL, callee_sig);
720 * Tail calls with more callee stack usage than the caller cannot be supported, since
721 * the extra stack space would be left on the stack after the tail call.
723 res = c1->stack_usage >= c2->stack_usage;
724 callee_ret = callee_sig->ret;
725 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
726 /* An address on the callee's stack is passed as the first argument */
736 * Initialize the cpu to execute managed code.
739 mono_arch_cpu_init (void)
741 /* spec compliance requires running with double precision */
745 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
746 fpcw &= ~X86_FPCW_PRECC_MASK;
747 fpcw |= X86_FPCW_PREC_DOUBLE;
748 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
749 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
751 _control87 (_PC_53, MCW_PC);
756 * Initialize architecture specific code.
759 mono_arch_init (void)
761 InitializeCriticalSection (&mini_arch_mutex);
763 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
764 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
765 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
767 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
768 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
769 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
770 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
775 * Cleanup architecture specific code.
778 mono_arch_cleanup (void)
781 mono_vfree (ss_trigger_page, mono_pagesize ());
783 mono_vfree (bp_trigger_page, mono_pagesize ());
784 DeleteCriticalSection (&mini_arch_mutex);
788 * This function returns the optimizations supported on this cpu.
791 mono_arch_cpu_optimizations (guint32 *exclude_mask)
793 #if !defined(__native_client__)
798 if (mono_hwcap_x86_has_cmov) {
799 opts |= MONO_OPT_CMOV;
801 if (mono_hwcap_x86_has_fcmov)
802 opts |= MONO_OPT_FCMOV;
804 *exclude_mask |= MONO_OPT_FCMOV;
806 *exclude_mask |= MONO_OPT_CMOV;
809 if (mono_hwcap_x86_has_sse2)
810 opts |= MONO_OPT_SSE2;
812 *exclude_mask |= MONO_OPT_SSE2;
814 #ifdef MONO_ARCH_SIMD_INTRINSICS
815 /*SIMD intrinsics require at least SSE2.*/
816 if (!mono_hwcap_x86_has_sse2)
817 *exclude_mask |= MONO_OPT_SIMD;
822 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
827 * This function test for all SSE functions supported.
829 * Returns a bitmask corresponding to all supported versions.
833 mono_arch_cpu_enumerate_simd_versions (void)
835 guint32 sse_opts = 0;
837 if (mono_hwcap_x86_has_sse1)
838 sse_opts |= SIMD_VERSION_SSE1;
840 if (mono_hwcap_x86_has_sse2)
841 sse_opts |= SIMD_VERSION_SSE2;
843 if (mono_hwcap_x86_has_sse3)
844 sse_opts |= SIMD_VERSION_SSE3;
846 if (mono_hwcap_x86_has_ssse3)
847 sse_opts |= SIMD_VERSION_SSSE3;
849 if (mono_hwcap_x86_has_sse41)
850 sse_opts |= SIMD_VERSION_SSE41;
852 if (mono_hwcap_x86_has_sse42)
853 sse_opts |= SIMD_VERSION_SSE42;
855 if (mono_hwcap_x86_has_sse4a)
856 sse_opts |= SIMD_VERSION_SSE4a;
862 * Determine whenever the trap whose info is in SIGINFO is caused by
866 mono_arch_is_int_overflow (void *sigctx, void *info)
871 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
873 ip = (guint8*)ctx.eip;
875 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
879 switch (x86_modrm_rm (ip [1])) {
899 g_assert_not_reached ();
911 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
916 for (i = 0; i < cfg->num_varinfo; i++) {
917 MonoInst *ins = cfg->varinfo [i];
918 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
921 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
924 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
925 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
928 /* we dont allocate I1 to registers because there is no simply way to sign extend
929 * 8bit quantities in caller saved registers on x86 */
930 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
931 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
932 g_assert (i == vmv->idx);
933 vars = g_list_prepend (vars, vmv);
937 vars = mono_varlist_sort (cfg, vars, 0);
943 mono_arch_get_global_int_regs (MonoCompile *cfg)
947 /* we can use 3 registers for global allocation */
948 regs = g_list_prepend (regs, (gpointer)X86_EBX);
949 regs = g_list_prepend (regs, (gpointer)X86_ESI);
950 regs = g_list_prepend (regs, (gpointer)X86_EDI);
956 * mono_arch_regalloc_cost:
958 * Return the cost, in number of memory references, of the action of
959 * allocating the variable VMV into a register during global register
963 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
965 MonoInst *ins = cfg->varinfo [vmv->idx];
967 if (cfg->method->save_lmf)
968 /* The register is already saved */
969 return (ins->opcode == OP_ARG) ? 1 : 0;
971 /* push+pop+possible load if it is an argument */
972 return (ins->opcode == OP_ARG) ? 3 : 2;
976 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
978 static int inited = FALSE;
979 static int count = 0;
981 if (cfg->arch.need_stack_frame_inited) {
982 g_assert (cfg->arch.need_stack_frame == flag);
986 cfg->arch.need_stack_frame = flag;
987 cfg->arch.need_stack_frame_inited = TRUE;
993 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
998 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
1002 needs_stack_frame (MonoCompile *cfg)
1004 MonoMethodSignature *sig;
1005 MonoMethodHeader *header;
1006 gboolean result = FALSE;
1008 #if defined(__APPLE__)
1009 /*OSX requires stack frame code to have the correct alignment. */
1013 if (cfg->arch.need_stack_frame_inited)
1014 return cfg->arch.need_stack_frame;
1016 header = cfg->header;
1017 sig = mono_method_signature (cfg->method);
1019 if (cfg->disable_omit_fp)
1021 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1023 else if (cfg->method->save_lmf)
1025 else if (cfg->stack_offset)
1027 else if (cfg->param_area)
1029 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1031 else if (header->num_clauses)
1033 else if (sig->param_count + sig->hasthis)
1035 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1037 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1038 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1041 set_needs_stack_frame (cfg, result);
1043 return cfg->arch.need_stack_frame;
1047 * Set var information according to the calling convention. X86 version.
1048 * The locals var stuff should most likely be split in another method.
1051 mono_arch_allocate_vars (MonoCompile *cfg)
1053 MonoMethodSignature *sig;
1054 MonoMethodHeader *header;
1056 guint32 locals_stack_size, locals_stack_align;
1061 header = cfg->header;
1062 sig = mono_method_signature (cfg->method);
1064 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1066 cfg->frame_reg = X86_EBP;
1069 /* Reserve space to save LMF and caller saved registers */
1071 if (cfg->method->save_lmf) {
1072 /* The LMF var is allocated normally */
1074 if (cfg->used_int_regs & (1 << X86_EBX)) {
1078 if (cfg->used_int_regs & (1 << X86_EDI)) {
1082 if (cfg->used_int_regs & (1 << X86_ESI)) {
1087 switch (cinfo->ret.storage) {
1088 case ArgValuetypeInReg:
1089 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1091 cfg->ret->opcode = OP_REGOFFSET;
1092 cfg->ret->inst_basereg = X86_EBP;
1093 cfg->ret->inst_offset = - offset;
1099 /* Allocate locals */
1100 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1101 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1102 char *mname = mono_method_full_name (cfg->method, TRUE);
1103 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1104 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1108 if (locals_stack_align) {
1109 int prev_offset = offset;
1111 offset += (locals_stack_align - 1);
1112 offset &= ~(locals_stack_align - 1);
1114 while (prev_offset < offset) {
1116 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1119 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1120 cfg->locals_max_stack_offset = - offset;
1122 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1123 * have locals larger than 8 bytes we need to make sure that
1124 * they have the appropriate offset.
1126 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1127 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1128 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1129 if (offsets [i] != -1) {
1130 MonoInst *inst = cfg->varinfo [i];
1131 inst->opcode = OP_REGOFFSET;
1132 inst->inst_basereg = X86_EBP;
1133 inst->inst_offset = - (offset + offsets [i]);
1134 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1137 offset += locals_stack_size;
1141 * Allocate arguments+return value
1144 switch (cinfo->ret.storage) {
1146 if (cfg->vret_addr) {
1148 * In the new IR, the cfg->vret_addr variable represents the
1149 * vtype return value.
1151 cfg->vret_addr->opcode = OP_REGOFFSET;
1152 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1153 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1154 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1155 printf ("vret_addr =");
1156 mono_print_ins (cfg->vret_addr);
1159 cfg->ret->opcode = OP_REGOFFSET;
1160 cfg->ret->inst_basereg = X86_EBP;
1161 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1164 case ArgValuetypeInReg:
1167 cfg->ret->opcode = OP_REGVAR;
1168 cfg->ret->inst_c0 = cinfo->ret.reg;
1169 cfg->ret->dreg = cinfo->ret.reg;
1172 case ArgOnFloatFpStack:
1173 case ArgOnDoubleFpStack:
1176 g_assert_not_reached ();
1179 if (sig->call_convention == MONO_CALL_VARARG) {
1180 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1181 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1184 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1185 ArgInfo *ainfo = &cinfo->args [i];
1186 inst = cfg->args [i];
1187 if (inst->opcode != OP_REGVAR) {
1188 inst->opcode = OP_REGOFFSET;
1189 inst->inst_basereg = X86_EBP;
1191 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1194 cfg->stack_offset = offset;
1198 mono_arch_create_vars (MonoCompile *cfg)
1201 MonoMethodSignature *sig;
1204 sig = mono_method_signature (cfg->method);
1206 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1209 if (cinfo->ret.storage == ArgValuetypeInReg)
1210 cfg->ret_var_is_local = TRUE;
1211 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (cfg, sig_ret))) {
1212 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1215 if (cfg->method->save_lmf) {
1216 cfg->create_lmf_var = TRUE;
1218 if (!optimize_for_xen) {
1220 cfg->lmf_ir_mono_lmf = TRUE;
1225 cfg->arch_eh_jit_info = 1;
1229 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1230 * so we try to do it just once when we have multiple fp arguments in a row.
1231 * We don't use this mechanism generally because for int arguments the generated code
1232 * is slightly bigger and new generation cpus optimize away the dependency chains
1233 * created by push instructions on the esp value.
1234 * fp_arg_setup is the first argument in the execution sequence where the esp register
1237 static G_GNUC_UNUSED int
1238 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1243 for (; start_arg < sig->param_count; ++start_arg) {
1244 t = mini_type_get_underlying_type (NULL, sig->params [start_arg]);
1245 if (!t->byref && t->type == MONO_TYPE_R8) {
1246 fp_space += sizeof (double);
1247 *fp_arg_setup = start_arg;
1256 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1258 MonoMethodSignature *tmp_sig;
1262 * mono_ArgIterator_Setup assumes the signature cookie is
1263 * passed first and all the arguments which were before it are
1264 * passed on the stack after the signature. So compensate by
1265 * passing a different signature.
1267 tmp_sig = mono_metadata_signature_dup (call->signature);
1268 tmp_sig->param_count -= call->signature->sentinelpos;
1269 tmp_sig->sentinelpos = 0;
1270 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1272 if (cfg->compile_aot) {
1273 sig_reg = mono_alloc_ireg (cfg);
1274 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1275 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, sig_reg);
1277 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1283 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1288 LLVMCallInfo *linfo;
1289 MonoType *t, *sig_ret;
1291 n = sig->param_count + sig->hasthis;
1293 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1296 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1299 * LLVM always uses the native ABI while we use our own ABI, the
1300 * only difference is the handling of vtypes:
1301 * - we only pass/receive them in registers in some cases, and only
1302 * in 1 or 2 integer registers.
1304 if (cinfo->ret.storage == ArgValuetypeInReg) {
1306 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1307 cfg->disable_llvm = TRUE;
1311 cfg->exception_message = g_strdup ("vtype ret in call");
1312 cfg->disable_llvm = TRUE;
1314 linfo->ret.storage = LLVMArgVtypeInReg;
1315 for (j = 0; j < 2; ++j)
1316 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1320 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage == ArgInIReg) {
1321 /* Vtype returned using a hidden argument */
1322 linfo->ret.storage = LLVMArgVtypeRetAddr;
1323 linfo->vret_arg_index = cinfo->vret_arg_index;
1326 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage != ArgInIReg) {
1328 cfg->exception_message = g_strdup ("vtype ret in call");
1329 cfg->disable_llvm = TRUE;
1332 for (i = 0; i < n; ++i) {
1333 ainfo = cinfo->args + i;
1335 if (i >= sig->hasthis)
1336 t = sig->params [i - sig->hasthis];
1338 t = &mono_defaults.int_class->byval_arg;
1340 linfo->args [i].storage = LLVMArgNone;
1342 switch (ainfo->storage) {
1344 linfo->args [i].storage = LLVMArgInIReg;
1346 case ArgInDoubleSSEReg:
1347 case ArgInFloatSSEReg:
1348 linfo->args [i].storage = LLVMArgInFPReg;
1351 if (mini_type_is_vtype (cfg, t)) {
1352 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1353 /* LLVM seems to allocate argument space for empty structures too */
1354 linfo->args [i].storage = LLVMArgNone;
1356 linfo->args [i].storage = LLVMArgVtypeByVal;
1358 linfo->args [i].storage = LLVMArgInIReg;
1360 if (t->type == MONO_TYPE_R4)
1361 linfo->args [i].storage = LLVMArgInFPReg;
1362 else if (t->type == MONO_TYPE_R8)
1363 linfo->args [i].storage = LLVMArgInFPReg;
1367 case ArgValuetypeInReg:
1369 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1370 cfg->disable_llvm = TRUE;
1374 cfg->exception_message = g_strdup ("vtype arg");
1375 cfg->disable_llvm = TRUE;
1377 linfo->args [i].storage = LLVMArgVtypeInReg;
1378 for (j = 0; j < 2; ++j)
1379 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1383 linfo->args [i].storage = LLVMArgGSharedVt;
1386 cfg->exception_message = g_strdup ("ainfo->storage");
1387 cfg->disable_llvm = TRUE;
1397 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1399 if (cfg->compute_gc_maps) {
1402 /* On x86, the offsets are from the sp value before the start of the call sequence */
1404 t = &mono_defaults.int_class->byval_arg;
1405 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1410 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1414 MonoMethodSignature *sig;
1417 int sentinelpos = 0, sp_offset = 0;
1419 sig = call->signature;
1420 n = sig->param_count + sig->hasthis;
1423 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1425 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1426 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1428 if (cinfo->need_stack_align) {
1429 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1430 arg->dreg = X86_ESP;
1431 arg->sreg1 = X86_ESP;
1432 arg->inst_imm = cinfo->stack_align_amount;
1433 MONO_ADD_INS (cfg->cbb, arg);
1434 for (i = 0; i < cinfo->stack_align_amount; i += sizeof (mgreg_t)) {
1437 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1441 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1442 if (cinfo->ret.storage == ArgValuetypeInReg) {
1444 * Tell the JIT to use a more efficient calling convention: call using
1445 * OP_CALL, compute the result location after the call, and save the
1448 call->vret_in_reg = TRUE;
1450 NULLIFY_INS (call->vret_var);
1454 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1456 /* Handle the case where there are no implicit arguments */
1457 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1458 emit_sig_cookie (cfg, call, cinfo);
1460 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1463 /* Arguments are pushed in the reverse order */
1464 for (i = n - 1; i >= 0; i --) {
1465 ArgInfo *ainfo = cinfo->args + i;
1466 MonoType *orig_type, *t;
1469 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1470 /* Push the vret arg before the first argument */
1472 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1473 vtarg->type = STACK_MP;
1474 vtarg->sreg1 = call->vret_var->dreg;
1475 MONO_ADD_INS (cfg->cbb, vtarg);
1477 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1480 if (i >= sig->hasthis)
1481 t = sig->params [i - sig->hasthis];
1483 t = &mono_defaults.int_class->byval_arg;
1485 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1487 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1489 in = call->args [i];
1490 arg->cil_code = in->cil_code;
1491 arg->sreg1 = in->dreg;
1492 arg->type = in->type;
1494 g_assert (in->dreg != -1);
1496 if (ainfo->storage == ArgGSharedVt) {
1497 arg->opcode = OP_OUTARG_VT;
1498 arg->sreg1 = in->dreg;
1499 arg->klass = in->klass;
1500 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1501 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1503 MONO_ADD_INS (cfg->cbb, arg);
1504 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1508 g_assert (in->klass);
1510 if (t->type == MONO_TYPE_TYPEDBYREF) {
1511 size = sizeof (MonoTypedRef);
1512 align = sizeof (gpointer);
1515 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1519 arg->opcode = OP_OUTARG_VT;
1520 arg->sreg1 = in->dreg;
1521 arg->klass = in->klass;
1522 arg->backend.size = size;
1523 arg->inst_p0 = call;
1524 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1525 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1527 MONO_ADD_INS (cfg->cbb, arg);
1528 if (ainfo->storage != ArgValuetypeInReg) {
1530 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1536 switch (ainfo->storage) {
1538 arg->opcode = OP_X86_PUSH;
1540 if (t->type == MONO_TYPE_R4) {
1541 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1542 arg->opcode = OP_STORER4_MEMBASE_REG;
1543 arg->inst_destbasereg = X86_ESP;
1544 arg->inst_offset = 0;
1546 } else if (t->type == MONO_TYPE_R8) {
1547 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1548 arg->opcode = OP_STORER8_MEMBASE_REG;
1549 arg->inst_destbasereg = X86_ESP;
1550 arg->inst_offset = 0;
1552 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1554 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1560 arg->opcode = OP_MOVE;
1561 arg->dreg = ainfo->reg;
1565 g_assert_not_reached ();
1568 MONO_ADD_INS (cfg->cbb, arg);
1570 sp_offset += argsize;
1572 if (cfg->compute_gc_maps) {
1574 /* FIXME: The == STACK_OBJ check might be fragile ? */
1575 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1577 if (call->need_unbox_trampoline)
1578 /* The unbox trampoline transforms this into a managed pointer */
1579 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.int_class->this_arg);
1581 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.object_class->byval_arg);
1583 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1587 for (j = 0; j < argsize; j += 4)
1588 emit_gc_param_slot_def (cfg, sp_offset - j, NULL);
1593 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1594 /* Emit the signature cookie just before the implicit arguments */
1595 emit_sig_cookie (cfg, call, cinfo);
1597 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1601 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1604 if (cinfo->ret.storage == ArgValuetypeInReg) {
1607 else if (cinfo->ret.storage == ArgInIReg) {
1609 /* The return address is passed in a register */
1610 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1611 vtarg->sreg1 = call->inst.dreg;
1612 vtarg->dreg = mono_alloc_ireg (cfg);
1613 MONO_ADD_INS (cfg->cbb, vtarg);
1615 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1616 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1618 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1619 vtarg->type = STACK_MP;
1620 vtarg->sreg1 = call->vret_var->dreg;
1621 MONO_ADD_INS (cfg->cbb, vtarg);
1623 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1626 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1627 if (cinfo->ret.storage != ArgValuetypeInReg)
1628 cinfo->stack_usage -= 4;
1631 call->stack_usage = cinfo->stack_usage;
1632 call->stack_align_amount = cinfo->stack_align_amount;
1633 cfg->arch.param_area_size = MAX (cfg->arch.param_area_size, sp_offset);
1637 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1639 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1640 ArgInfo *ainfo = ins->inst_p1;
1642 int size = ins->backend.size;
1644 if (ainfo->storage == ArgValuetypeInReg) {
1645 int dreg = mono_alloc_ireg (cfg);
1648 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1651 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1654 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1658 g_assert_not_reached ();
1660 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1663 if (cfg->gsharedvt && mini_is_gsharedvt_klass (cfg, ins->klass)) {
1665 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1666 arg->sreg1 = src->dreg;
1667 MONO_ADD_INS (cfg->cbb, arg);
1668 } else if (size <= 4) {
1669 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1670 arg->sreg1 = src->dreg;
1672 MONO_ADD_INS (cfg->cbb, arg);
1673 } else if (size <= 20) {
1674 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1675 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1677 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1678 arg->inst_basereg = src->dreg;
1679 arg->inst_offset = 0;
1680 arg->inst_imm = size;
1682 MONO_ADD_INS (cfg->cbb, arg);
1688 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1690 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1693 if (ret->type == MONO_TYPE_R4) {
1694 if (COMPILE_LLVM (cfg))
1695 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1698 } else if (ret->type == MONO_TYPE_R8) {
1699 if (COMPILE_LLVM (cfg))
1700 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1703 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1704 if (COMPILE_LLVM (cfg))
1705 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1707 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1708 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1714 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1718 * Allow tracing to work with this interface (with an optional argument)
1721 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1725 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1726 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1728 /* if some args are passed in registers, we need to save them here */
1729 x86_push_reg (code, X86_EBP);
1731 if (cfg->compile_aot) {
1732 x86_push_imm (code, cfg->method);
1733 x86_mov_reg_imm (code, X86_EAX, func);
1734 x86_call_reg (code, X86_EAX);
1736 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1737 x86_push_imm (code, cfg->method);
1738 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1739 x86_call_code (code, 0);
1741 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1755 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1758 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1759 MonoMethod *method = cfg->method;
1760 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1762 switch (ret_type->type) {
1763 case MONO_TYPE_VOID:
1764 /* special case string .ctor icall */
1765 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1766 save_mode = SAVE_EAX;
1767 stack_usage = enable_arguments ? 8 : 4;
1769 save_mode = SAVE_NONE;
1773 save_mode = SAVE_EAX_EDX;
1774 stack_usage = enable_arguments ? 16 : 8;
1778 save_mode = SAVE_FP;
1779 stack_usage = enable_arguments ? 16 : 8;
1781 case MONO_TYPE_GENERICINST:
1782 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1783 save_mode = SAVE_EAX;
1784 stack_usage = enable_arguments ? 8 : 4;
1788 case MONO_TYPE_VALUETYPE:
1789 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1790 save_mode = SAVE_STRUCT;
1791 stack_usage = enable_arguments ? 4 : 0;
1794 save_mode = SAVE_EAX;
1795 stack_usage = enable_arguments ? 8 : 4;
1799 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1801 switch (save_mode) {
1803 x86_push_reg (code, X86_EDX);
1804 x86_push_reg (code, X86_EAX);
1805 if (enable_arguments) {
1806 x86_push_reg (code, X86_EDX);
1807 x86_push_reg (code, X86_EAX);
1812 x86_push_reg (code, X86_EAX);
1813 if (enable_arguments) {
1814 x86_push_reg (code, X86_EAX);
1819 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1820 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1821 if (enable_arguments) {
1822 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1823 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1828 if (enable_arguments) {
1829 x86_push_membase (code, X86_EBP, 8);
1838 if (cfg->compile_aot) {
1839 x86_push_imm (code, method);
1840 x86_mov_reg_imm (code, X86_EAX, func);
1841 x86_call_reg (code, X86_EAX);
1843 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1844 x86_push_imm (code, method);
1845 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1846 x86_call_code (code, 0);
1849 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1851 switch (save_mode) {
1853 x86_pop_reg (code, X86_EAX);
1854 x86_pop_reg (code, X86_EDX);
1857 x86_pop_reg (code, X86_EAX);
1860 x86_fld_membase (code, X86_ESP, 0, TRUE);
1861 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1868 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1873 #define EMIT_COND_BRANCH(ins,cond,sign) \
1874 if (ins->inst_true_bb->native_offset) { \
1875 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1877 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1878 if ((cfg->opt & MONO_OPT_BRANCH) && \
1879 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1880 x86_branch8 (code, cond, 0, sign); \
1882 x86_branch32 (code, cond, 0, sign); \
1886 * Emit an exception if condition is fail and
1887 * if possible do a directly branch to target
1889 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1891 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1892 if (tins == NULL) { \
1893 mono_add_patch_info (cfg, code - cfg->native_code, \
1894 MONO_PATCH_INFO_EXC, exc_name); \
1895 x86_branch32 (code, cond, 0, signed); \
1897 EMIT_COND_BRANCH (tins, cond, signed); \
1901 #define EMIT_FPCOMPARE(code) do { \
1902 x86_fcompp (code); \
1903 x86_fnstsw (code); \
1908 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1910 gboolean needs_paddings = TRUE;
1912 MonoJumpInfo *jinfo = NULL;
1914 if (cfg->abs_patches) {
1915 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1916 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1917 needs_paddings = FALSE;
1920 if (cfg->compile_aot)
1921 needs_paddings = FALSE;
1922 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1923 This is required for code patching to be safe on SMP machines.
1925 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1926 #ifndef __native_client_codegen__
1927 if (needs_paddings && pad_size)
1928 x86_padding (code, 4 - pad_size);
1931 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1932 x86_call_code (code, 0);
1937 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1940 * mono_peephole_pass_1:
1942 * Perform peephole opts which should/can be performed before local regalloc
1945 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1949 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1950 MonoInst *last_ins = ins->prev;
1952 switch (ins->opcode) {
1955 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1957 * X86_LEA is like ADD, but doesn't have the
1958 * sreg1==dreg restriction.
1960 ins->opcode = OP_X86_LEA_MEMBASE;
1961 ins->inst_basereg = ins->sreg1;
1962 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1963 ins->opcode = OP_X86_INC_REG;
1967 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1968 ins->opcode = OP_X86_LEA_MEMBASE;
1969 ins->inst_basereg = ins->sreg1;
1970 ins->inst_imm = -ins->inst_imm;
1971 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1972 ins->opcode = OP_X86_DEC_REG;
1974 case OP_COMPARE_IMM:
1975 case OP_ICOMPARE_IMM:
1976 /* OP_COMPARE_IMM (reg, 0)
1978 * OP_X86_TEST_NULL (reg)
1981 ins->opcode = OP_X86_TEST_NULL;
1983 case OP_X86_COMPARE_MEMBASE_IMM:
1985 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1986 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1988 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1989 * OP_COMPARE_IMM reg, imm
1991 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1993 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1994 ins->inst_basereg == last_ins->inst_destbasereg &&
1995 ins->inst_offset == last_ins->inst_offset) {
1996 ins->opcode = OP_COMPARE_IMM;
1997 ins->sreg1 = last_ins->sreg1;
1999 /* check if we can remove cmp reg,0 with test null */
2001 ins->opcode = OP_X86_TEST_NULL;
2005 case OP_X86_PUSH_MEMBASE:
2006 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
2007 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2008 ins->inst_basereg == last_ins->inst_destbasereg &&
2009 ins->inst_offset == last_ins->inst_offset) {
2010 ins->opcode = OP_X86_PUSH;
2011 ins->sreg1 = last_ins->sreg1;
2016 mono_peephole_ins (bb, ins);
2021 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2025 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2026 switch (ins->opcode) {
2028 /* reg = 0 -> XOR (reg, reg) */
2029 /* XOR sets cflags on x86, so we cant do it always */
2030 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2033 ins->opcode = OP_IXOR;
2034 ins->sreg1 = ins->dreg;
2035 ins->sreg2 = ins->dreg;
2038 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2039 * since it takes 3 bytes instead of 7.
2041 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2042 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2043 ins2->opcode = OP_STORE_MEMBASE_REG;
2044 ins2->sreg1 = ins->dreg;
2046 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2047 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2048 ins2->sreg1 = ins->dreg;
2050 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2051 /* Continue iteration */
2060 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2061 ins->opcode = OP_X86_INC_REG;
2065 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2066 ins->opcode = OP_X86_DEC_REG;
2070 mono_peephole_ins (bb, ins);
2075 * mono_arch_lowering_pass:
2077 * Converts complex opcodes into simpler ones so that each IR instruction
2078 * corresponds to one machine instruction.
2081 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2083 MonoInst *ins, *next;
2086 * FIXME: Need to add more instructions, but the current machine
2087 * description can't model some parts of the composite instructions like
2090 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2091 switch (ins->opcode) {
2094 case OP_IDIV_UN_IMM:
2095 case OP_IREM_UN_IMM:
2097 * Keep the cases where we could generated optimized code, otherwise convert
2098 * to the non-imm variant.
2100 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2102 mono_decompose_op_imm (cfg, bb, ins);
2109 bb->max_vreg = cfg->next_vreg;
2113 branch_cc_table [] = {
2114 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2115 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2116 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2119 /* Maps CMP_... constants to X86_CC_... constants */
2122 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2123 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2127 cc_signed_table [] = {
2128 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2129 FALSE, FALSE, FALSE, FALSE
2132 static unsigned char*
2133 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2135 #define XMM_TEMP_REG 0
2136 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2137 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2138 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2139 /* optimize by assigning a local var for this use so we avoid
2140 * the stack manipulations */
2141 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2142 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2143 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2144 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2145 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2147 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2149 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2152 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2153 x86_fnstcw_membase(code, X86_ESP, 0);
2154 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2155 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2156 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2157 x86_fldcw_membase (code, X86_ESP, 2);
2159 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2160 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2161 x86_pop_reg (code, dreg);
2162 /* FIXME: need the high register
2163 * x86_pop_reg (code, dreg_high);
2166 x86_push_reg (code, X86_EAX); // SP = SP - 4
2167 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2168 x86_pop_reg (code, dreg);
2170 x86_fldcw_membase (code, X86_ESP, 0);
2171 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2174 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2176 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2180 static unsigned char*
2181 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2183 int sreg = tree->sreg1;
2184 int need_touch = FALSE;
2186 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2195 * If requested stack size is larger than one page,
2196 * perform stack-touch operation
2199 * Generate stack probe code.
2200 * Under Windows, it is necessary to allocate one page at a time,
2201 * "touching" stack after each successful sub-allocation. This is
2202 * because of the way stack growth is implemented - there is a
2203 * guard page before the lowest stack page that is currently commited.
2204 * Stack normally grows sequentially so OS traps access to the
2205 * guard page and commits more pages when needed.
2207 x86_test_reg_imm (code, sreg, ~0xFFF);
2208 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2210 br[2] = code; /* loop */
2211 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2212 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2215 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2216 * that follows only initializes the last part of the area.
2218 /* Same as the init code below with size==0x1000 */
2219 if (tree->flags & MONO_INST_INIT) {
2220 x86_push_reg (code, X86_EAX);
2221 x86_push_reg (code, X86_ECX);
2222 x86_push_reg (code, X86_EDI);
2223 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2224 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2225 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2227 x86_prefix (code, X86_REP_PREFIX);
2229 x86_pop_reg (code, X86_EDI);
2230 x86_pop_reg (code, X86_ECX);
2231 x86_pop_reg (code, X86_EAX);
2234 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2235 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2236 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2237 x86_patch (br[3], br[2]);
2238 x86_test_reg_reg (code, sreg, sreg);
2239 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2240 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2242 br[1] = code; x86_jump8 (code, 0);
2244 x86_patch (br[0], code);
2245 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2246 x86_patch (br[1], code);
2247 x86_patch (br[4], code);
2250 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2252 if (tree->flags & MONO_INST_INIT) {
2254 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2255 x86_push_reg (code, X86_EAX);
2258 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2259 x86_push_reg (code, X86_ECX);
2262 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2263 x86_push_reg (code, X86_EDI);
2267 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2268 if (sreg != X86_ECX)
2269 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2270 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2272 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2274 x86_prefix (code, X86_REP_PREFIX);
2277 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2278 x86_pop_reg (code, X86_EDI);
2279 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2280 x86_pop_reg (code, X86_ECX);
2281 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2282 x86_pop_reg (code, X86_EAX);
2289 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2291 /* Move return value to the target register */
2292 switch (ins->opcode) {
2295 case OP_CALL_MEMBASE:
2296 if (ins->dreg != X86_EAX)
2297 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2307 static int tls_gs_offset;
2311 mono_x86_have_tls_get (void)
2314 static gboolean have_tls_get = FALSE;
2315 static gboolean inited = FALSE;
2319 return have_tls_get;
2321 ins = (guint32*)pthread_getspecific;
2323 * We're looking for these two instructions:
2325 * mov 0x4(%esp),%eax
2326 * mov %gs:[offset](,%eax,4),%eax
2328 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2329 tls_gs_offset = ins [2];
2333 return have_tls_get;
2334 #elif defined(TARGET_ANDROID)
2342 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2344 #if defined(__APPLE__)
2345 x86_prefix (code, X86_GS_PREFIX);
2346 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2347 #elif defined(TARGET_WIN32)
2348 g_assert_not_reached ();
2350 x86_prefix (code, X86_GS_PREFIX);
2351 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2357 * mono_x86_emit_tls_get:
2358 * @code: buffer to store code to
2359 * @dreg: hard register where to place the result
2360 * @tls_offset: offset info
2362 * mono_x86_emit_tls_get emits in @code the native code that puts in
2363 * the dreg register the item in the thread local storage identified
2366 * Returns: a pointer to the end of the stored code
2369 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2371 #if defined(__APPLE__)
2372 x86_prefix (code, X86_GS_PREFIX);
2373 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2374 #elif defined(TARGET_WIN32)
2376 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2377 * Journal and/or a disassembly of the TlsGet () function.
2379 g_assert (tls_offset < 64);
2380 x86_prefix (code, X86_FS_PREFIX);
2381 x86_mov_reg_mem (code, dreg, 0x18, 4);
2382 /* Dunno what this does but TlsGetValue () contains it */
2383 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2384 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2386 if (optimize_for_xen) {
2387 x86_prefix (code, X86_GS_PREFIX);
2388 x86_mov_reg_mem (code, dreg, 0, 4);
2389 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2391 x86_prefix (code, X86_GS_PREFIX);
2392 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2399 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2401 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2402 #if defined(__APPLE__) || defined(__linux__)
2403 if (dreg != offset_reg)
2404 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2405 x86_prefix (code, X86_GS_PREFIX);
2406 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2408 g_assert_not_reached ();
2414 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2416 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2418 g_assert_not_reached ();
2419 #elif defined(__APPLE__) || defined(__linux__)
2420 x86_prefix (code, X86_GS_PREFIX);
2421 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2423 g_assert_not_reached ();
2429 * mono_arch_translate_tls_offset:
2431 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2434 mono_arch_translate_tls_offset (int offset)
2437 return tls_gs_offset + (offset * 4);
2446 * Emit code to initialize an LMF structure at LMF_OFFSET.
2449 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2451 /* save all caller saved regs */
2452 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2453 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx));
2454 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2455 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi));
2456 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2457 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi));
2458 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2460 /* save the current IP */
2461 if (cfg->compile_aot) {
2462 /* This pushes the current ip */
2463 x86_call_imm (code, 0);
2464 x86_pop_reg (code, X86_EAX);
2466 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2467 x86_mov_reg_imm (code, X86_EAX, 0);
2469 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2471 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2472 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2473 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2474 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2475 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2476 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2477 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2478 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2479 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2487 * Emit code to push an LMF structure on the LMF stack.
2490 emit_push_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
2492 if (!cfg->compile_aot && (lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
2494 * Optimized version which uses the mono_lmf TLS variable instead of indirection
2495 * through the mono_lmf_addr TLS variable.
2497 /* %eax = previous_lmf */
2498 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_tls_offset);
2499 /* set previous_lmf */
2500 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), X86_EAX, sizeof (mgreg_t));
2501 x86_lea_membase (code, X86_EAX, cfg->frame_reg, lmf_offset);
2503 code = mono_x86_emit_tls_set (code, X86_EAX, lmf_tls_offset);
2505 /* get the address of lmf for the current thread */
2507 * This is performance critical so we try to use some tricks to make
2510 gboolean have_fastpath = FALSE;
2513 if (jit_tls_offset != -1) {
2514 code = mono_x86_emit_tls_get (code, X86_EAX, jit_tls_offset);
2515 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
2516 have_fastpath = TRUE;
2519 if (!cfg->compile_aot && lmf_addr_tls_offset != -1) {
2520 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
2521 have_fastpath = TRUE;
2524 if (!have_fastpath) {
2525 if (cfg->compile_aot)
2526 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
2527 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
2531 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), X86_EAX, sizeof (mgreg_t));
2532 /* save previous_lmf */
2533 x86_mov_reg_membase (code, X86_ECX, X86_EAX, 0, sizeof (mgreg_t));
2534 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), X86_ECX, sizeof (mgreg_t));
2536 x86_lea_membase (code, X86_ECX, cfg->frame_reg, lmf_offset);
2537 x86_mov_membase_reg (code, X86_EAX, 0, X86_ECX, sizeof (mgreg_t));
2545 * Emit code to pop an LMF structure from the LMF stack.
2546 * Preserves the return registers.
2549 emit_pop_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
2551 MonoMethodSignature *sig = mono_method_signature (cfg->method);
2554 if (!cfg->compile_aot && (lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
2556 * Optimized version which uses the mono_lmf TLS variable instead of indirection
2557 * through the mono_lmf_addr TLS variable.
2559 /* reg = previous_lmf */
2560 x86_mov_reg_membase (code, X86_ECX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
2562 /* lmf = previous_lmf */
2563 code = mono_x86_emit_tls_set (code, X86_ECX, lmf_tls_offset);
2565 /* Find a spare register */
2566 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
2569 prev_lmf_reg = X86_EDI;
2570 cfg->used_int_regs |= (1 << X86_EDI);
2573 prev_lmf_reg = X86_EDX;
2577 /* reg = previous_lmf */
2578 x86_mov_reg_membase (code, prev_lmf_reg, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
2581 x86_mov_reg_membase (code, X86_ECX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
2583 /* *(lmf) = previous_lmf */
2584 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
2589 #define REAL_PRINT_REG(text,reg) \
2590 mono_assert (reg >= 0); \
2591 x86_push_reg (code, X86_EAX); \
2592 x86_push_reg (code, X86_EDX); \
2593 x86_push_reg (code, X86_ECX); \
2594 x86_push_reg (code, reg); \
2595 x86_push_imm (code, reg); \
2596 x86_push_imm (code, text " %d %p\n"); \
2597 x86_mov_reg_imm (code, X86_EAX, printf); \
2598 x86_call_reg (code, X86_EAX); \
2599 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2600 x86_pop_reg (code, X86_ECX); \
2601 x86_pop_reg (code, X86_EDX); \
2602 x86_pop_reg (code, X86_EAX);
2604 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2605 #ifdef __native__client_codegen__
2606 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2609 /* benchmark and set based on cpu */
2610 #define LOOP_ALIGNMENT 8
2611 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2615 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2620 guint8 *code = cfg->native_code + cfg->code_len;
2623 if (cfg->opt & MONO_OPT_LOOP) {
2624 int pad, align = LOOP_ALIGNMENT;
2625 /* set alignment depending on cpu */
2626 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2628 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2629 x86_padding (code, pad);
2630 cfg->code_len += pad;
2631 bb->native_offset = cfg->code_len;
2634 #ifdef __native_client_codegen__
2636 /* For Native Client, all indirect call/jump targets must be */
2637 /* 32-byte aligned. Exception handler blocks are jumped to */
2638 /* indirectly as well. */
2639 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2640 (bb->flags & BB_EXCEPTION_HANDLER);
2642 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2643 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2644 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2645 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2646 cfg->code_len += pad;
2647 bb->native_offset = cfg->code_len;
2650 #endif /* __native_client_codegen__ */
2651 if (cfg->verbose_level > 2)
2652 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2654 cpos = bb->max_offset;
2656 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2657 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2658 g_assert (!cfg->compile_aot);
2661 cov->data [bb->dfn].cil_code = bb->cil_code;
2662 /* this is not thread save, but good enough */
2663 x86_inc_mem (code, &cov->data [bb->dfn].count);
2666 offset = code - cfg->native_code;
2668 mono_debug_open_block (cfg, bb, offset);
2670 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2671 x86_breakpoint (code);
2673 MONO_BB_FOR_EACH_INS (bb, ins) {
2674 offset = code - cfg->native_code;
2676 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2678 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2680 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2681 cfg->code_size *= 2;
2682 cfg->native_code = mono_realloc_native_code(cfg);
2683 code = cfg->native_code + offset;
2684 cfg->stat_code_reallocs++;
2687 if (cfg->debug_info)
2688 mono_debug_record_line_number (cfg, ins, offset);
2690 switch (ins->opcode) {
2692 x86_mul_reg (code, ins->sreg2, TRUE);
2695 x86_mul_reg (code, ins->sreg2, FALSE);
2697 case OP_X86_SETEQ_MEMBASE:
2698 case OP_X86_SETNE_MEMBASE:
2699 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2700 ins->inst_basereg, ins->inst_offset, TRUE);
2702 case OP_STOREI1_MEMBASE_IMM:
2703 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2705 case OP_STOREI2_MEMBASE_IMM:
2706 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2708 case OP_STORE_MEMBASE_IMM:
2709 case OP_STOREI4_MEMBASE_IMM:
2710 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2712 case OP_STOREI1_MEMBASE_REG:
2713 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2715 case OP_STOREI2_MEMBASE_REG:
2716 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2718 case OP_STORE_MEMBASE_REG:
2719 case OP_STOREI4_MEMBASE_REG:
2720 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2722 case OP_STORE_MEM_IMM:
2723 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2726 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2730 /* These are created by the cprop pass so they use inst_imm as the source */
2731 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2734 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2737 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2739 case OP_LOAD_MEMBASE:
2740 case OP_LOADI4_MEMBASE:
2741 case OP_LOADU4_MEMBASE:
2742 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2744 case OP_LOADU1_MEMBASE:
2745 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2747 case OP_LOADI1_MEMBASE:
2748 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2750 case OP_LOADU2_MEMBASE:
2751 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2753 case OP_LOADI2_MEMBASE:
2754 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2756 case OP_ICONV_TO_I1:
2758 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2760 case OP_ICONV_TO_I2:
2762 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2764 case OP_ICONV_TO_U1:
2765 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2767 case OP_ICONV_TO_U2:
2768 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2772 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2774 case OP_COMPARE_IMM:
2775 case OP_ICOMPARE_IMM:
2776 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2778 case OP_X86_COMPARE_MEMBASE_REG:
2779 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2781 case OP_X86_COMPARE_MEMBASE_IMM:
2782 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2784 case OP_X86_COMPARE_MEMBASE8_IMM:
2785 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2787 case OP_X86_COMPARE_REG_MEMBASE:
2788 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2790 case OP_X86_COMPARE_MEM_IMM:
2791 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2793 case OP_X86_TEST_NULL:
2794 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2796 case OP_X86_ADD_MEMBASE_IMM:
2797 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2799 case OP_X86_ADD_REG_MEMBASE:
2800 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2802 case OP_X86_SUB_MEMBASE_IMM:
2803 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2805 case OP_X86_SUB_REG_MEMBASE:
2806 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2808 case OP_X86_AND_MEMBASE_IMM:
2809 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2811 case OP_X86_OR_MEMBASE_IMM:
2812 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2814 case OP_X86_XOR_MEMBASE_IMM:
2815 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2817 case OP_X86_ADD_MEMBASE_REG:
2818 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2820 case OP_X86_SUB_MEMBASE_REG:
2821 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2823 case OP_X86_AND_MEMBASE_REG:
2824 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2826 case OP_X86_OR_MEMBASE_REG:
2827 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2829 case OP_X86_XOR_MEMBASE_REG:
2830 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2832 case OP_X86_INC_MEMBASE:
2833 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2835 case OP_X86_INC_REG:
2836 x86_inc_reg (code, ins->dreg);
2838 case OP_X86_DEC_MEMBASE:
2839 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2841 case OP_X86_DEC_REG:
2842 x86_dec_reg (code, ins->dreg);
2844 case OP_X86_MUL_REG_MEMBASE:
2845 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2847 case OP_X86_AND_REG_MEMBASE:
2848 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2850 case OP_X86_OR_REG_MEMBASE:
2851 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2853 case OP_X86_XOR_REG_MEMBASE:
2854 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2857 x86_breakpoint (code);
2859 case OP_RELAXED_NOP:
2860 x86_prefix (code, X86_REP_PREFIX);
2868 case OP_DUMMY_STORE:
2869 case OP_NOT_REACHED:
2872 case OP_SEQ_POINT: {
2875 if (cfg->compile_aot)
2879 * Read from the single stepping trigger page. This will cause a
2880 * SIGSEGV when single stepping is enabled.
2881 * We do this _before_ the breakpoint, so single stepping after
2882 * a breakpoint is hit will step to the next IL offset.
2884 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2885 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2887 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2890 * A placeholder for a possible breakpoint inserted by
2891 * mono_arch_set_breakpoint ().
2893 for (i = 0; i < 6; ++i)
2896 * Add an additional nop so skipping the bp doesn't cause the ip to point
2897 * to another IL offset.
2905 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2909 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2914 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2918 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2923 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2927 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2932 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2936 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2939 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2943 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2947 #if defined( __native_client_codegen__ )
2948 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2949 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2952 * The code is the same for div/rem, the allocator will allocate dreg
2953 * to RAX/RDX as appropriate.
2955 if (ins->sreg2 == X86_EDX) {
2956 /* cdq clobbers this */
2957 x86_push_reg (code, ins->sreg2);
2959 x86_div_membase (code, X86_ESP, 0, TRUE);
2960 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2963 x86_div_reg (code, ins->sreg2, TRUE);
2968 #if defined( __native_client_codegen__ )
2969 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2970 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2972 if (ins->sreg2 == X86_EDX) {
2973 x86_push_reg (code, ins->sreg2);
2974 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2975 x86_div_membase (code, X86_ESP, 0, FALSE);
2976 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2978 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2979 x86_div_reg (code, ins->sreg2, FALSE);
2983 #if defined( __native_client_codegen__ )
2984 if (ins->inst_imm == 0) {
2985 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2986 x86_jump32 (code, 0);
2990 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2992 x86_div_reg (code, ins->sreg2, TRUE);
2995 int power = mono_is_power_of_two (ins->inst_imm);
2997 g_assert (ins->sreg1 == X86_EAX);
2998 g_assert (ins->dreg == X86_EAX);
2999 g_assert (power >= 0);
3002 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
3004 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
3006 * If the divident is >= 0, this does not nothing. If it is positive, it
3007 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
3009 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
3010 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
3011 } else if (power == 0) {
3012 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3014 /* Based on gcc code */
3016 /* Add compensation for negative dividents */
3018 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
3019 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
3020 /* Compute remainder */
3021 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
3022 /* Remove compensation */
3023 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
3028 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3032 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3035 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3039 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3042 g_assert (ins->sreg2 == X86_ECX);
3043 x86_shift_reg (code, X86_SHL, ins->dreg);
3046 g_assert (ins->sreg2 == X86_ECX);
3047 x86_shift_reg (code, X86_SAR, ins->dreg);
3051 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3054 case OP_ISHR_UN_IMM:
3055 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3058 g_assert (ins->sreg2 == X86_ECX);
3059 x86_shift_reg (code, X86_SHR, ins->dreg);
3063 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3066 guint8 *jump_to_end;
3068 /* handle shifts below 32 bits */
3069 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
3070 x86_shift_reg (code, X86_SHL, ins->sreg1);
3072 x86_test_reg_imm (code, X86_ECX, 32);
3073 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3075 /* handle shift over 32 bit */
3076 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3077 x86_clear_reg (code, ins->sreg1);
3079 x86_patch (jump_to_end, code);
3083 guint8 *jump_to_end;
3085 /* handle shifts below 32 bits */
3086 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3087 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
3089 x86_test_reg_imm (code, X86_ECX, 32);
3090 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3092 /* handle shifts over 31 bits */
3093 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3094 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
3096 x86_patch (jump_to_end, code);
3100 guint8 *jump_to_end;
3102 /* handle shifts below 32 bits */
3103 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3104 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
3106 x86_test_reg_imm (code, X86_ECX, 32);
3107 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3109 /* handle shifts over 31 bits */
3110 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3111 x86_clear_reg (code, ins->backend.reg3);
3113 x86_patch (jump_to_end, code);
3117 if (ins->inst_imm >= 32) {
3118 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3119 x86_clear_reg (code, ins->sreg1);
3120 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
3122 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
3123 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
3127 if (ins->inst_imm >= 32) {
3128 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3129 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
3130 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
3132 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3133 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3136 case OP_LSHR_UN_IMM:
3137 if (ins->inst_imm >= 32) {
3138 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3139 x86_clear_reg (code, ins->backend.reg3);
3140 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3142 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3143 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3147 x86_not_reg (code, ins->sreg1);
3150 x86_neg_reg (code, ins->sreg1);
3154 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3158 switch (ins->inst_imm) {
3162 if (ins->dreg != ins->sreg1)
3163 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3164 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3167 /* LEA r1, [r2 + r2*2] */
3168 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3171 /* LEA r1, [r2 + r2*4] */
3172 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3175 /* LEA r1, [r2 + r2*2] */
3177 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3178 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3181 /* LEA r1, [r2 + r2*8] */
3182 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3185 /* LEA r1, [r2 + r2*4] */
3187 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3188 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3191 /* LEA r1, [r2 + r2*2] */
3193 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3194 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3197 /* LEA r1, [r2 + r2*4] */
3198 /* LEA r1, [r1 + r1*4] */
3199 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3200 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3203 /* LEA r1, [r2 + r2*4] */
3205 /* LEA r1, [r1 + r1*4] */
3206 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3207 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3208 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3211 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3216 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3217 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3219 case OP_IMUL_OVF_UN: {
3220 /* the mul operation and the exception check should most likely be split */
3221 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3222 /*g_assert (ins->sreg2 == X86_EAX);
3223 g_assert (ins->dreg == X86_EAX);*/
3224 if (ins->sreg2 == X86_EAX) {
3225 non_eax_reg = ins->sreg1;
3226 } else if (ins->sreg1 == X86_EAX) {
3227 non_eax_reg = ins->sreg2;
3229 /* no need to save since we're going to store to it anyway */
3230 if (ins->dreg != X86_EAX) {
3232 x86_push_reg (code, X86_EAX);
3234 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3235 non_eax_reg = ins->sreg2;
3237 if (ins->dreg == X86_EDX) {
3240 x86_push_reg (code, X86_EAX);
3242 } else if (ins->dreg != X86_EAX) {
3244 x86_push_reg (code, X86_EDX);
3246 x86_mul_reg (code, non_eax_reg, FALSE);
3247 /* save before the check since pop and mov don't change the flags */
3248 if (ins->dreg != X86_EAX)
3249 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3251 x86_pop_reg (code, X86_EDX);
3253 x86_pop_reg (code, X86_EAX);
3254 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3258 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3261 g_assert_not_reached ();
3262 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3263 x86_mov_reg_imm (code, ins->dreg, 0);
3266 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3267 x86_mov_reg_imm (code, ins->dreg, 0);
3269 case OP_LOAD_GOTADDR:
3270 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3271 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3274 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3275 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3277 case OP_X86_PUSH_GOT_ENTRY:
3278 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3279 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3282 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3285 MonoCallInst *call = (MonoCallInst*)ins;
3288 ins->flags |= MONO_INST_GC_CALLSITE;
3289 ins->backend.pc_offset = code - cfg->native_code;
3291 /* FIXME: no tracing support... */
3292 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3293 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3294 /* reset offset to make max_len work */
3295 offset = code - cfg->native_code;
3297 g_assert (!cfg->method->save_lmf);
3299 /* restore callee saved registers */
3300 for (i = 0; i < X86_NREG; ++i)
3301 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3303 if (cfg->used_int_regs & (1 << X86_ESI)) {
3304 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3307 if (cfg->used_int_regs & (1 << X86_EDI)) {
3308 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3311 if (cfg->used_int_regs & (1 << X86_EBX)) {
3312 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3316 /* Copy arguments on the stack to our argument area */
3317 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3318 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3319 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3322 /* restore ESP/EBP */
3324 offset = code - cfg->native_code;
3325 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3326 x86_jump32 (code, 0);
3328 ins->flags |= MONO_INST_GC_CALLSITE;
3329 cfg->disable_aot = TRUE;
3333 /* ensure ins->sreg1 is not NULL
3334 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3335 * cmp DWORD PTR [eax], 0
3337 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3340 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3341 x86_push_reg (code, hreg);
3342 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3343 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3344 x86_pop_reg (code, hreg);
3353 call = (MonoCallInst*)ins;
3354 if (ins->flags & MONO_INST_HAS_METHOD)
3355 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3357 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3358 ins->flags |= MONO_INST_GC_CALLSITE;
3359 ins->backend.pc_offset = code - cfg->native_code;
3360 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3361 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
3362 * bytes to pop, we want to use pops. GCC does this (note it won't happen
3363 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
3364 * smart enough to do that optimization yet
3366 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
3367 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
3368 * (most likely from locality benefits). People with other processors should
3369 * check on theirs to see what happens.
3371 if (call->stack_usage == 4) {
3372 /* we want to use registers that won't get used soon, so use
3373 * ecx, as eax will get allocated first. edx is used by long calls,
3374 * so we can't use that.
3377 x86_pop_reg (code, X86_ECX);
3379 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3382 code = emit_move_return_value (cfg, ins, code);
3388 case OP_VOIDCALL_REG:
3390 call = (MonoCallInst*)ins;
3391 x86_call_reg (code, ins->sreg1);
3392 ins->flags |= MONO_INST_GC_CALLSITE;
3393 ins->backend.pc_offset = code - cfg->native_code;
3394 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3395 if (call->stack_usage == 4)
3396 x86_pop_reg (code, X86_ECX);
3398 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3400 code = emit_move_return_value (cfg, ins, code);
3402 case OP_FCALL_MEMBASE:
3403 case OP_LCALL_MEMBASE:
3404 case OP_VCALL_MEMBASE:
3405 case OP_VCALL2_MEMBASE:
3406 case OP_VOIDCALL_MEMBASE:
3407 case OP_CALL_MEMBASE:
3408 call = (MonoCallInst*)ins;
3410 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3411 ins->flags |= MONO_INST_GC_CALLSITE;
3412 ins->backend.pc_offset = code - cfg->native_code;
3413 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3414 if (call->stack_usage == 4)
3415 x86_pop_reg (code, X86_ECX);
3417 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3419 code = emit_move_return_value (cfg, ins, code);
3422 x86_push_reg (code, ins->sreg1);
3424 case OP_X86_PUSH_IMM:
3425 x86_push_imm (code, ins->inst_imm);
3427 case OP_X86_PUSH_MEMBASE:
3428 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
3430 case OP_X86_PUSH_OBJ:
3431 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
3432 x86_push_reg (code, X86_EDI);
3433 x86_push_reg (code, X86_ESI);
3434 x86_push_reg (code, X86_ECX);
3435 if (ins->inst_offset)
3436 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
3438 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
3439 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
3440 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
3442 x86_prefix (code, X86_REP_PREFIX);
3444 x86_pop_reg (code, X86_ECX);
3445 x86_pop_reg (code, X86_ESI);
3446 x86_pop_reg (code, X86_EDI);
3449 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3451 case OP_X86_LEA_MEMBASE:
3452 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3455 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3458 /* keep alignment */
3459 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3460 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3461 code = mono_emit_stack_alloc (code, ins);
3462 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3464 case OP_LOCALLOC_IMM: {
3465 guint32 size = ins->inst_imm;
3466 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3468 if (ins->flags & MONO_INST_INIT) {
3469 /* FIXME: Optimize this */
3470 x86_mov_reg_imm (code, ins->dreg, size);
3471 ins->sreg1 = ins->dreg;
3473 code = mono_emit_stack_alloc (code, ins);
3474 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3476 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3477 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3482 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3483 x86_push_reg (code, ins->sreg1);
3484 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3485 (gpointer)"mono_arch_throw_exception");
3486 ins->flags |= MONO_INST_GC_CALLSITE;
3487 ins->backend.pc_offset = code - cfg->native_code;
3491 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3492 x86_push_reg (code, ins->sreg1);
3493 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3494 (gpointer)"mono_arch_rethrow_exception");
3495 ins->flags |= MONO_INST_GC_CALLSITE;
3496 ins->backend.pc_offset = code - cfg->native_code;
3499 case OP_CALL_HANDLER:
3500 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3501 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3502 x86_call_imm (code, 0);
3503 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3504 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3506 case OP_START_HANDLER: {
3507 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3508 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3511 case OP_ENDFINALLY: {
3512 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3513 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3517 case OP_ENDFILTER: {
3518 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3519 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3520 /* The local allocator will put the result into EAX */
3526 ins->inst_c0 = code - cfg->native_code;
3529 if (ins->inst_target_bb->native_offset) {
3530 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3532 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3533 if ((cfg->opt & MONO_OPT_BRANCH) &&
3534 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3535 x86_jump8 (code, 0);
3537 x86_jump32 (code, 0);
3541 x86_jump_reg (code, ins->sreg1);
3560 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3561 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3563 case OP_COND_EXC_EQ:
3564 case OP_COND_EXC_NE_UN:
3565 case OP_COND_EXC_LT:
3566 case OP_COND_EXC_LT_UN:
3567 case OP_COND_EXC_GT:
3568 case OP_COND_EXC_GT_UN:
3569 case OP_COND_EXC_GE:
3570 case OP_COND_EXC_GE_UN:
3571 case OP_COND_EXC_LE:
3572 case OP_COND_EXC_LE_UN:
3573 case OP_COND_EXC_IEQ:
3574 case OP_COND_EXC_INE_UN:
3575 case OP_COND_EXC_ILT:
3576 case OP_COND_EXC_ILT_UN:
3577 case OP_COND_EXC_IGT:
3578 case OP_COND_EXC_IGT_UN:
3579 case OP_COND_EXC_IGE:
3580 case OP_COND_EXC_IGE_UN:
3581 case OP_COND_EXC_ILE:
3582 case OP_COND_EXC_ILE_UN:
3583 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3585 case OP_COND_EXC_OV:
3586 case OP_COND_EXC_NO:
3588 case OP_COND_EXC_NC:
3589 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3591 case OP_COND_EXC_IOV:
3592 case OP_COND_EXC_INO:
3593 case OP_COND_EXC_IC:
3594 case OP_COND_EXC_INC:
3595 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3607 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3615 case OP_CMOV_INE_UN:
3616 case OP_CMOV_IGE_UN:
3617 case OP_CMOV_IGT_UN:
3618 case OP_CMOV_ILE_UN:
3619 case OP_CMOV_ILT_UN:
3620 g_assert (ins->dreg == ins->sreg1);
3621 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3624 /* floating point opcodes */
3626 double d = *(double *)ins->inst_p0;
3628 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3630 } else if (d == 1.0) {
3633 if (cfg->compile_aot) {
3634 guint32 *val = (guint32*)&d;
3635 x86_push_imm (code, val [1]);
3636 x86_push_imm (code, val [0]);
3637 x86_fld_membase (code, X86_ESP, 0, TRUE);
3638 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3641 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3642 x86_fld (code, NULL, TRUE);
3648 float f = *(float *)ins->inst_p0;
3650 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3652 } else if (f == 1.0) {
3655 if (cfg->compile_aot) {
3656 guint32 val = *(guint32*)&f;
3657 x86_push_imm (code, val);
3658 x86_fld_membase (code, X86_ESP, 0, FALSE);
3659 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3662 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3663 x86_fld (code, NULL, FALSE);
3668 case OP_STORER8_MEMBASE_REG:
3669 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3671 case OP_LOADR8_MEMBASE:
3672 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3674 case OP_STORER4_MEMBASE_REG:
3675 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3677 case OP_LOADR4_MEMBASE:
3678 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3680 case OP_ICONV_TO_R4:
3681 x86_push_reg (code, ins->sreg1);
3682 x86_fild_membase (code, X86_ESP, 0, FALSE);
3683 /* Change precision */
3684 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3685 x86_fld_membase (code, X86_ESP, 0, FALSE);
3686 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3688 case OP_ICONV_TO_R8:
3689 x86_push_reg (code, ins->sreg1);
3690 x86_fild_membase (code, X86_ESP, 0, FALSE);
3691 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3693 case OP_ICONV_TO_R_UN:
3694 x86_push_imm (code, 0);
3695 x86_push_reg (code, ins->sreg1);
3696 x86_fild_membase (code, X86_ESP, 0, TRUE);
3697 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3699 case OP_X86_FP_LOAD_I8:
3700 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3702 case OP_X86_FP_LOAD_I4:
3703 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3705 case OP_FCONV_TO_R4:
3706 /* Change precision */
3707 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3708 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3709 x86_fld_membase (code, X86_ESP, 0, FALSE);
3710 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3712 case OP_FCONV_TO_I1:
3713 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3715 case OP_FCONV_TO_U1:
3716 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3718 case OP_FCONV_TO_I2:
3719 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3721 case OP_FCONV_TO_U2:
3722 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3724 case OP_FCONV_TO_I4:
3726 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3728 case OP_FCONV_TO_I8:
3729 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3730 x86_fnstcw_membase(code, X86_ESP, 0);
3731 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3732 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3733 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3734 x86_fldcw_membase (code, X86_ESP, 2);
3735 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3736 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3737 x86_pop_reg (code, ins->dreg);
3738 x86_pop_reg (code, ins->backend.reg3);
3739 x86_fldcw_membase (code, X86_ESP, 0);
3740 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3742 case OP_LCONV_TO_R8_2:
3743 x86_push_reg (code, ins->sreg2);
3744 x86_push_reg (code, ins->sreg1);
3745 x86_fild_membase (code, X86_ESP, 0, TRUE);
3746 /* Change precision */
3747 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3748 x86_fld_membase (code, X86_ESP, 0, TRUE);
3749 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3751 case OP_LCONV_TO_R4_2:
3752 x86_push_reg (code, ins->sreg2);
3753 x86_push_reg (code, ins->sreg1);
3754 x86_fild_membase (code, X86_ESP, 0, TRUE);
3755 /* Change precision */
3756 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3757 x86_fld_membase (code, X86_ESP, 0, FALSE);
3758 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3760 case OP_LCONV_TO_R_UN_2: {
3761 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3764 /* load 64bit integer to FP stack */
3765 x86_push_reg (code, ins->sreg2);
3766 x86_push_reg (code, ins->sreg1);
3767 x86_fild_membase (code, X86_ESP, 0, TRUE);
3769 /* test if lreg is negative */
3770 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3771 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3773 /* add correction constant mn */
3774 if (cfg->compile_aot) {
3775 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3776 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3777 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3778 x86_fld80_membase (code, X86_ESP, 2);
3779 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3781 x86_fld80_mem (code, mn);
3783 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3785 x86_patch (br, code);
3787 /* Change precision */
3788 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3789 x86_fld_membase (code, X86_ESP, 0, TRUE);
3791 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3795 case OP_LCONV_TO_OVF_I:
3796 case OP_LCONV_TO_OVF_I4_2: {
3797 guint8 *br [3], *label [1];
3801 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3803 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3805 /* If the low word top bit is set, see if we are negative */
3806 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3807 /* We are not negative (no top bit set, check for our top word to be zero */
3808 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3809 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3812 /* throw exception */
3813 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3815 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3816 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3817 x86_jump8 (code, 0);
3819 x86_jump32 (code, 0);
3821 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3822 x86_jump32 (code, 0);
3826 x86_patch (br [0], code);
3827 /* our top bit is set, check that top word is 0xfffffff */
3828 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3830 x86_patch (br [1], code);
3831 /* nope, emit exception */
3832 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3833 x86_patch (br [2], label [0]);
3835 if (ins->dreg != ins->sreg1)
3836 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3840 /* Not needed on the fp stack */
3843 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3846 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3849 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3852 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3860 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3865 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3872 * it really doesn't make sense to inline all this code,
3873 * it's here just to show that things may not be as simple
3876 guchar *check_pos, *end_tan, *pop_jump;
3877 x86_push_reg (code, X86_EAX);
3880 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3882 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3883 x86_fstp (code, 0); /* pop the 1.0 */
3885 x86_jump8 (code, 0);
3887 x86_fp_op (code, X86_FADD, 0);
3891 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3893 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3896 x86_patch (pop_jump, code);
3897 x86_fstp (code, 0); /* pop the 1.0 */
3898 x86_patch (check_pos, code);
3899 x86_patch (end_tan, code);
3901 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3902 x86_pop_reg (code, X86_EAX);
3909 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3918 g_assert (cfg->opt & MONO_OPT_CMOV);
3919 g_assert (ins->dreg == ins->sreg1);
3920 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3921 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3924 g_assert (cfg->opt & MONO_OPT_CMOV);
3925 g_assert (ins->dreg == ins->sreg1);
3926 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3927 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3930 g_assert (cfg->opt & MONO_OPT_CMOV);
3931 g_assert (ins->dreg == ins->sreg1);
3932 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3933 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3936 g_assert (cfg->opt & MONO_OPT_CMOV);
3937 g_assert (ins->dreg == ins->sreg1);
3938 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3939 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3945 x86_fxch (code, ins->inst_imm);
3950 x86_push_reg (code, X86_EAX);
3951 /* we need to exchange ST(0) with ST(1) */
3954 /* this requires a loop, because fprem somtimes
3955 * returns a partial remainder */
3957 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3958 /* x86_fprem1 (code); */
3961 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3963 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3969 x86_pop_reg (code, X86_EAX);
3973 if (cfg->opt & MONO_OPT_FCMOV) {
3974 x86_fcomip (code, 1);
3978 /* this overwrites EAX */
3979 EMIT_FPCOMPARE(code);
3980 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3984 if (cfg->opt & MONO_OPT_FCMOV) {
3985 /* zeroing the register at the start results in
3986 * shorter and faster code (we can also remove the widening op)
3988 guchar *unordered_check;
3989 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3990 x86_fcomip (code, 1);
3992 unordered_check = code;
3993 x86_branch8 (code, X86_CC_P, 0, FALSE);
3994 if (ins->opcode == OP_FCEQ) {
3995 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3996 x86_patch (unordered_check, code);
3998 guchar *jump_to_end;
3999 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
4001 x86_jump8 (code, 0);
4002 x86_patch (unordered_check, code);
4003 x86_inc_reg (code, ins->dreg);
4004 x86_patch (jump_to_end, code);
4009 if (ins->dreg != X86_EAX)
4010 x86_push_reg (code, X86_EAX);
4012 EMIT_FPCOMPARE(code);
4013 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4014 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4015 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
4016 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4018 if (ins->dreg != X86_EAX)
4019 x86_pop_reg (code, X86_EAX);
4023 if (cfg->opt & MONO_OPT_FCMOV) {
4024 /* zeroing the register at the start results in
4025 * shorter and faster code (we can also remove the widening op)
4027 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4028 x86_fcomip (code, 1);
4030 if (ins->opcode == OP_FCLT_UN) {
4031 guchar *unordered_check = code;
4032 guchar *jump_to_end;
4033 x86_branch8 (code, X86_CC_P, 0, FALSE);
4034 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4036 x86_jump8 (code, 0);
4037 x86_patch (unordered_check, code);
4038 x86_inc_reg (code, ins->dreg);
4039 x86_patch (jump_to_end, code);
4041 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4045 if (ins->dreg != X86_EAX)
4046 x86_push_reg (code, X86_EAX);
4048 EMIT_FPCOMPARE(code);
4049 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4050 if (ins->opcode == OP_FCLT_UN) {
4051 guchar *is_not_zero_check, *end_jump;
4052 is_not_zero_check = code;
4053 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4055 x86_jump8 (code, 0);
4056 x86_patch (is_not_zero_check, code);
4057 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4059 x86_patch (end_jump, code);
4061 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4062 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4064 if (ins->dreg != X86_EAX)
4065 x86_pop_reg (code, X86_EAX);
4068 guchar *unordered_check;
4069 guchar *jump_to_end;
4070 if (cfg->opt & MONO_OPT_FCMOV) {
4071 /* zeroing the register at the start results in
4072 * shorter and faster code (we can also remove the widening op)
4074 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4075 x86_fcomip (code, 1);
4077 unordered_check = code;
4078 x86_branch8 (code, X86_CC_P, 0, FALSE);
4079 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
4080 x86_patch (unordered_check, code);
4083 if (ins->dreg != X86_EAX)
4084 x86_push_reg (code, X86_EAX);
4086 EMIT_FPCOMPARE(code);
4087 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4088 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4089 unordered_check = code;
4090 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4092 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4093 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
4094 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4096 x86_jump8 (code, 0);
4097 x86_patch (unordered_check, code);
4098 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4099 x86_patch (jump_to_end, code);
4101 if (ins->dreg != X86_EAX)
4102 x86_pop_reg (code, X86_EAX);
4107 if (cfg->opt & MONO_OPT_FCMOV) {
4108 /* zeroing the register at the start results in
4109 * shorter and faster code (we can also remove the widening op)
4111 guchar *unordered_check;
4112 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4113 x86_fcomip (code, 1);
4115 if (ins->opcode == OP_FCGT) {
4116 unordered_check = code;
4117 x86_branch8 (code, X86_CC_P, 0, FALSE);
4118 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4119 x86_patch (unordered_check, code);
4121 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4125 if (ins->dreg != X86_EAX)
4126 x86_push_reg (code, X86_EAX);
4128 EMIT_FPCOMPARE(code);
4129 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4130 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4131 if (ins->opcode == OP_FCGT_UN) {
4132 guchar *is_not_zero_check, *end_jump;
4133 is_not_zero_check = code;
4134 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4136 x86_jump8 (code, 0);
4137 x86_patch (is_not_zero_check, code);
4138 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4140 x86_patch (end_jump, code);
4142 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4143 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4145 if (ins->dreg != X86_EAX)
4146 x86_pop_reg (code, X86_EAX);
4149 guchar *unordered_check;
4150 guchar *jump_to_end;
4151 if (cfg->opt & MONO_OPT_FCMOV) {
4152 /* zeroing the register at the start results in
4153 * shorter and faster code (we can also remove the widening op)
4155 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4156 x86_fcomip (code, 1);
4158 unordered_check = code;
4159 x86_branch8 (code, X86_CC_P, 0, FALSE);
4160 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4161 x86_patch (unordered_check, code);
4164 if (ins->dreg != X86_EAX)
4165 x86_push_reg (code, X86_EAX);
4167 EMIT_FPCOMPARE(code);
4168 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4169 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4170 unordered_check = code;
4171 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4173 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4174 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4175 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4177 x86_jump8 (code, 0);
4178 x86_patch (unordered_check, code);
4179 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4180 x86_patch (jump_to_end, code);
4182 if (ins->dreg != X86_EAX)
4183 x86_pop_reg (code, X86_EAX);
4187 if (cfg->opt & MONO_OPT_FCMOV) {
4188 guchar *jump = code;
4189 x86_branch8 (code, X86_CC_P, 0, TRUE);
4190 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4191 x86_patch (jump, code);
4194 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4195 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4198 /* Branch if C013 != 100 */
4199 if (cfg->opt & MONO_OPT_FCMOV) {
4200 /* branch if !ZF or (PF|CF) */
4201 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4202 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4203 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4206 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4207 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4210 if (cfg->opt & MONO_OPT_FCMOV) {
4211 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4214 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4217 if (cfg->opt & MONO_OPT_FCMOV) {
4218 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4219 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4222 if (ins->opcode == OP_FBLT_UN) {
4223 guchar *is_not_zero_check, *end_jump;
4224 is_not_zero_check = code;
4225 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4227 x86_jump8 (code, 0);
4228 x86_patch (is_not_zero_check, code);
4229 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4231 x86_patch (end_jump, code);
4233 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4237 if (cfg->opt & MONO_OPT_FCMOV) {
4238 if (ins->opcode == OP_FBGT) {
4241 /* skip branch if C1=1 */
4243 x86_branch8 (code, X86_CC_P, 0, FALSE);
4244 /* branch if (C0 | C3) = 1 */
4245 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4246 x86_patch (br1, code);
4248 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4252 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4253 if (ins->opcode == OP_FBGT_UN) {
4254 guchar *is_not_zero_check, *end_jump;
4255 is_not_zero_check = code;
4256 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4258 x86_jump8 (code, 0);
4259 x86_patch (is_not_zero_check, code);
4260 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4262 x86_patch (end_jump, code);
4264 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4267 /* Branch if C013 == 100 or 001 */
4268 if (cfg->opt & MONO_OPT_FCMOV) {
4271 /* skip branch if C1=1 */
4273 x86_branch8 (code, X86_CC_P, 0, FALSE);
4274 /* branch if (C0 | C3) = 1 */
4275 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4276 x86_patch (br1, code);
4279 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4280 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4281 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4282 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4285 /* Branch if C013 == 000 */
4286 if (cfg->opt & MONO_OPT_FCMOV) {
4287 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4290 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4293 /* Branch if C013=000 or 100 */
4294 if (cfg->opt & MONO_OPT_FCMOV) {
4297 /* skip branch if C1=1 */
4299 x86_branch8 (code, X86_CC_P, 0, FALSE);
4300 /* branch if C0=0 */
4301 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4302 x86_patch (br1, code);
4305 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4306 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4307 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4310 /* Branch if C013 != 001 */
4311 if (cfg->opt & MONO_OPT_FCMOV) {
4312 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4313 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4316 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4317 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4321 x86_push_reg (code, X86_EAX);
4324 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4325 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4326 x86_pop_reg (code, X86_EAX);
4328 /* Have to clean up the fp stack before throwing the exception */
4330 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4333 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4335 x86_patch (br1, code);
4339 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4342 case OP_TLS_GET_REG: {
4343 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4347 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4350 case OP_TLS_SET_REG: {
4351 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4354 case OP_MEMORY_BARRIER: {
4355 /* x86 only needs barrier for StoreLoad and FullBarrier */
4356 switch (ins->backend.memory_barrier_kind) {
4357 case StoreLoadBarrier:
4359 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4360 x86_prefix (code, X86_LOCK_PREFIX);
4361 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4366 case OP_ATOMIC_ADD_I4: {
4367 int dreg = ins->dreg;
4369 if (dreg == ins->inst_basereg) {
4370 x86_push_reg (code, ins->sreg2);
4374 if (dreg != ins->sreg2)
4375 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
4377 x86_prefix (code, X86_LOCK_PREFIX);
4378 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4380 if (dreg != ins->dreg) {
4381 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4382 x86_pop_reg (code, dreg);
4387 case OP_ATOMIC_ADD_NEW_I4: {
4388 int dreg = ins->dreg;
4390 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4391 if (ins->sreg2 == dreg) {
4392 if (dreg == X86_EBX) {
4394 if (ins->inst_basereg == X86_EDI)
4398 if (ins->inst_basereg == X86_EBX)
4401 } else if (ins->inst_basereg == dreg) {
4402 if (dreg == X86_EBX) {
4404 if (ins->sreg2 == X86_EDI)
4408 if (ins->sreg2 == X86_EBX)
4413 if (dreg != ins->dreg) {
4414 x86_push_reg (code, dreg);
4417 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4418 x86_prefix (code, X86_LOCK_PREFIX);
4419 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4420 /* dreg contains the old value, add with sreg2 value */
4421 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4423 if (ins->dreg != dreg) {
4424 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4425 x86_pop_reg (code, dreg);
4430 case OP_ATOMIC_EXCHANGE_I4: {
4432 int sreg2 = ins->sreg2;
4433 int breg = ins->inst_basereg;
4435 /* cmpxchg uses eax as comperand, need to make sure we can use it
4436 * hack to overcome limits in x86 reg allocator
4437 * (req: dreg == eax and sreg2 != eax and breg != eax)
4439 g_assert (ins->dreg == X86_EAX);
4441 /* We need the EAX reg for the cmpxchg */
4442 if (ins->sreg2 == X86_EAX) {
4443 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4444 x86_push_reg (code, sreg2);
4445 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4448 if (breg == X86_EAX) {
4449 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4450 x86_push_reg (code, breg);
4451 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4454 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4456 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4457 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4458 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4459 x86_patch (br [1], br [0]);
4461 if (breg != ins->inst_basereg)
4462 x86_pop_reg (code, breg);
4464 if (ins->sreg2 != sreg2)
4465 x86_pop_reg (code, sreg2);
4469 case OP_ATOMIC_CAS_I4: {
4470 g_assert (ins->dreg == X86_EAX);
4471 g_assert (ins->sreg3 == X86_EAX);
4472 g_assert (ins->sreg1 != X86_EAX);
4473 g_assert (ins->sreg1 != ins->sreg2);
4475 x86_prefix (code, X86_LOCK_PREFIX);
4476 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4479 case OP_CARD_TABLE_WBARRIER: {
4480 int ptr = ins->sreg1;
4481 int value = ins->sreg2;
4483 int nursery_shift, card_table_shift;
4484 gpointer card_table_mask;
4485 size_t nursery_size;
4486 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4487 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4488 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4491 * We need one register we can clobber, we choose EDX and make sreg1
4492 * fixed EAX to work around limitations in the local register allocator.
4493 * sreg2 might get allocated to EDX, but that is not a problem since
4494 * we use it before clobbering EDX.
4496 g_assert (ins->sreg1 == X86_EAX);
4499 * This is the code we produce:
4502 * edx >>= nursery_shift
4503 * cmp edx, (nursery_start >> nursery_shift)
4506 * edx >>= card_table_shift
4507 * card_table[edx] = 1
4511 if (card_table_nursery_check) {
4512 if (value != X86_EDX)
4513 x86_mov_reg_reg (code, X86_EDX, value, 4);
4514 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4515 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4516 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4518 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4519 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4520 if (card_table_mask)
4521 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4522 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4523 if (card_table_nursery_check)
4524 x86_patch (br, code);
4527 #ifdef MONO_ARCH_SIMD_INTRINSICS
4529 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4532 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4535 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4538 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4541 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4544 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4547 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4548 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4551 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4554 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4557 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4560 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4563 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4566 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4569 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4572 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4575 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4578 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4581 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4584 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4587 case OP_PSHUFLEW_HIGH:
4588 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4589 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4591 case OP_PSHUFLEW_LOW:
4592 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4593 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4596 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4597 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4600 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4601 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4604 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4605 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4609 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4612 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4615 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4618 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4621 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4624 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4627 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4628 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4631 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4634 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4637 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4640 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4643 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4646 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4649 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4652 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4655 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4658 case OP_EXTRACT_MASK:
4659 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4663 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4666 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4669 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4673 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4676 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4679 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4682 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4686 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4689 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4692 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4695 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4699 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4702 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4705 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4709 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4712 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4715 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4719 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4722 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4726 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4729 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4732 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4736 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4739 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4742 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4746 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4749 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4752 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4755 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4759 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4762 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4765 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4768 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4771 case OP_PSUM_ABS_DIFF:
4772 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4775 case OP_UNPACK_LOWB:
4776 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4778 case OP_UNPACK_LOWW:
4779 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4781 case OP_UNPACK_LOWD:
4782 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4784 case OP_UNPACK_LOWQ:
4785 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4787 case OP_UNPACK_LOWPS:
4788 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4790 case OP_UNPACK_LOWPD:
4791 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4794 case OP_UNPACK_HIGHB:
4795 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4797 case OP_UNPACK_HIGHW:
4798 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4800 case OP_UNPACK_HIGHD:
4801 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4803 case OP_UNPACK_HIGHQ:
4804 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4806 case OP_UNPACK_HIGHPS:
4807 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4809 case OP_UNPACK_HIGHPD:
4810 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4814 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4817 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4820 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4823 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4826 case OP_PADDB_SAT_UN:
4827 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4829 case OP_PSUBB_SAT_UN:
4830 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4832 case OP_PADDW_SAT_UN:
4833 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4835 case OP_PSUBW_SAT_UN:
4836 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4840 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4843 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4846 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4849 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4853 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4856 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4859 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4861 case OP_PMULW_HIGH_UN:
4862 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4865 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4869 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4872 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4876 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4879 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4883 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4886 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4890 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4893 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4897 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4900 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4904 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4907 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4911 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4914 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4918 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4921 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4925 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4928 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4932 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4934 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4935 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4939 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4941 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4942 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4946 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4948 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4949 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4953 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4955 case OP_EXTRACTX_U2:
4956 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4958 case OP_INSERTX_U1_SLOW:
4959 /*sreg1 is the extracted ireg (scratch)
4960 /sreg2 is the to be inserted ireg (scratch)
4961 /dreg is the xreg to receive the value*/
4963 /*clear the bits from the extracted word*/
4964 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4965 /*shift the value to insert if needed*/
4966 if (ins->inst_c0 & 1)
4967 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4968 /*join them together*/
4969 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4970 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4972 case OP_INSERTX_I4_SLOW:
4973 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4974 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4975 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4978 case OP_INSERTX_R4_SLOW:
4979 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4980 /*TODO if inst_c0 == 0 use movss*/
4981 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4982 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4984 case OP_INSERTX_R8_SLOW:
4985 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4986 if (cfg->verbose_level)
4987 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4989 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4991 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4994 case OP_STOREX_MEMBASE_REG:
4995 case OP_STOREX_MEMBASE:
4996 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4998 case OP_LOADX_MEMBASE:
4999 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5001 case OP_LOADX_ALIGNED_MEMBASE:
5002 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5004 case OP_STOREX_ALIGNED_MEMBASE_REG:
5005 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5007 case OP_STOREX_NTA_MEMBASE_REG:
5008 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
5010 case OP_PREFETCH_MEMBASE:
5011 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5015 /*FIXME the peephole pass should have killed this*/
5016 if (ins->dreg != ins->sreg1)
5017 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5020 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
5022 case OP_ICONV_TO_R8_RAW:
5023 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
5024 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
5027 case OP_FCONV_TO_R8_X:
5028 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
5029 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5032 case OP_XCONV_R8_TO_I4:
5033 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
5034 switch (ins->backend.source_opcode) {
5035 case OP_FCONV_TO_I1:
5036 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5038 case OP_FCONV_TO_U1:
5039 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5041 case OP_FCONV_TO_I2:
5042 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5044 case OP_FCONV_TO_U2:
5045 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5051 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
5052 /*The +4 is to get a mov ?h, ?l over the same reg.*/
5053 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
5054 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
5055 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
5056 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5059 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
5060 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
5061 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5064 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
5065 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5068 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
5069 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5070 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5073 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
5074 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5075 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
5079 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
5082 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
5085 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
5088 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
5091 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
5094 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
5097 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
5100 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
5104 case OP_LIVERANGE_START: {
5105 if (cfg->verbose_level > 1)
5106 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5107 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5110 case OP_LIVERANGE_END: {
5111 if (cfg->verbose_level > 1)
5112 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5113 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5116 case OP_NACL_GC_SAFE_POINT: {
5117 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
5118 if (cfg->compile_aot)
5119 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5123 x86_test_mem_imm8 (code, (gpointer)&__nacl_thread_suspension_needed, 0xFFFFFFFF);
5124 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
5125 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5126 x86_patch (br[0], code);
5131 case OP_GC_LIVENESS_DEF:
5132 case OP_GC_LIVENESS_USE:
5133 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5134 ins->backend.pc_offset = code - cfg->native_code;
5136 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5137 ins->backend.pc_offset = code - cfg->native_code;
5138 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5141 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
5142 g_assert_not_reached ();
5145 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
5146 #ifndef __native_client_codegen__
5147 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5148 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5149 g_assert_not_reached ();
5150 #endif /* __native_client_codegen__ */
5156 cfg->code_len = code - cfg->native_code;
5159 #endif /* DISABLE_JIT */
5162 mono_arch_register_lowlevel_calls (void)
5167 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
5169 MonoJumpInfo *patch_info;
5170 gboolean compile_aot = !run_cctors;
5172 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5173 unsigned char *ip = patch_info->ip.i + code;
5174 const unsigned char *target;
5177 switch (patch_info->type) {
5178 case MONO_PATCH_INFO_BB:
5179 case MONO_PATCH_INFO_LABEL:
5182 /* No need to patch these */
5187 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5189 switch (patch_info->type) {
5190 case MONO_PATCH_INFO_IP:
5191 *((gconstpointer *)(ip)) = target;
5193 case MONO_PATCH_INFO_CLASS_INIT: {
5195 /* Might already been changed to a nop */
5196 x86_call_code (code, 0);
5197 x86_patch (ip, target);
5200 case MONO_PATCH_INFO_ABS:
5201 case MONO_PATCH_INFO_METHOD:
5202 case MONO_PATCH_INFO_METHOD_JUMP:
5203 case MONO_PATCH_INFO_INTERNAL_METHOD:
5204 case MONO_PATCH_INFO_BB:
5205 case MONO_PATCH_INFO_LABEL:
5206 case MONO_PATCH_INFO_RGCTX_FETCH:
5207 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
5208 case MONO_PATCH_INFO_MONITOR_ENTER:
5209 case MONO_PATCH_INFO_MONITOR_EXIT:
5210 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5211 #if defined(__native_client_codegen__) && defined(__native_client__)
5212 if (nacl_is_code_address (code)) {
5213 /* For tail calls, code is patched after being installed */
5214 /* but not through the normal "patch callsite" method. */
5215 unsigned char buf[kNaClAlignment];
5216 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5217 unsigned char *_target = target;
5219 /* All patch targets modified in x86_patch */
5220 /* are IP relative. */
5221 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5222 memcpy (buf, aligned_code, kNaClAlignment);
5223 /* Patch a temp buffer of bundle size, */
5224 /* then install to actual location. */
5225 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5226 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5227 g_assert (ret == 0);
5230 x86_patch (ip, target);
5233 x86_patch (ip, target);
5236 case MONO_PATCH_INFO_NONE:
5238 case MONO_PATCH_INFO_R4:
5239 case MONO_PATCH_INFO_R8: {
5240 guint32 offset = mono_arch_get_patch_offset (ip);
5241 *((gconstpointer *)(ip + offset)) = target;
5245 guint32 offset = mono_arch_get_patch_offset (ip);
5246 #if !defined(__native_client__)
5247 *((gconstpointer *)(ip + offset)) = target;
5249 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5257 static G_GNUC_UNUSED void
5258 stack_unaligned (MonoMethod *m, gpointer caller)
5260 printf ("%s\n", mono_method_full_name (m, TRUE));
5261 g_assert_not_reached ();
5265 mono_arch_emit_prolog (MonoCompile *cfg)
5267 MonoMethod *method = cfg->method;
5269 MonoMethodSignature *sig;
5271 int alloc_size, pos, max_offset, i, cfa_offset;
5273 gboolean need_stack_frame;
5274 #ifdef __native_client_codegen__
5275 guint alignment_check;
5278 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5280 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5281 cfg->code_size += 512;
5283 #if defined(__default_codegen__)
5284 code = cfg->native_code = g_malloc (cfg->code_size);
5285 #elif defined(__native_client_codegen__)
5286 /* native_code_alloc is not 32-byte aligned, native_code is. */
5287 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5288 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5290 /* Align native_code to next nearest kNaclAlignment byte. */
5291 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5292 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5294 code = cfg->native_code;
5296 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5297 g_assert(alignment_check == 0);
5304 /* Check that the stack is aligned on osx */
5305 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5306 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5307 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5309 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5310 x86_push_membase (code, X86_ESP, 0);
5311 x86_push_imm (code, cfg->method);
5312 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5313 x86_call_reg (code, X86_EAX);
5314 x86_patch (br [0], code);
5318 /* Offset between RSP and the CFA */
5322 cfa_offset = sizeof (gpointer);
5323 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5324 // IP saved at CFA - 4
5325 /* There is no IP reg on x86 */
5326 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5327 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5329 need_stack_frame = needs_stack_frame (cfg);
5331 if (need_stack_frame) {
5332 x86_push_reg (code, X86_EBP);
5333 cfa_offset += sizeof (gpointer);
5334 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5335 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5336 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5337 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5338 /* These are handled automatically by the stack marking code */
5339 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5341 cfg->frame_reg = X86_ESP;
5344 alloc_size = cfg->stack_offset;
5347 if (!method->save_lmf) {
5348 if (cfg->used_int_regs & (1 << X86_EBX)) {
5349 x86_push_reg (code, X86_EBX);
5351 cfa_offset += sizeof (gpointer);
5352 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5353 /* These are handled automatically by the stack marking code */
5354 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5357 if (cfg->used_int_regs & (1 << X86_EDI)) {
5358 x86_push_reg (code, X86_EDI);
5360 cfa_offset += sizeof (gpointer);
5361 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5362 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5365 if (cfg->used_int_regs & (1 << X86_ESI)) {
5366 x86_push_reg (code, X86_ESI);
5368 cfa_offset += sizeof (gpointer);
5369 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5370 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5376 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5377 if (mono_do_x86_stack_align && need_stack_frame) {
5378 int tot = alloc_size + pos + 4; /* ret ip */
5379 if (need_stack_frame)
5381 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5383 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5384 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5385 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5389 cfg->arch.sp_fp_offset = alloc_size + pos;
5392 /* See mono_emit_stack_alloc */
5393 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5394 guint32 remaining_size = alloc_size;
5395 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5396 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5397 guint32 offset = code - cfg->native_code;
5398 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5399 while (required_code_size >= (cfg->code_size - offset))
5400 cfg->code_size *= 2;
5401 cfg->native_code = mono_realloc_native_code(cfg);
5402 code = cfg->native_code + offset;
5403 cfg->stat_code_reallocs++;
5405 while (remaining_size >= 0x1000) {
5406 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5407 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5408 remaining_size -= 0x1000;
5411 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5413 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5416 g_assert (need_stack_frame);
5419 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5420 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5421 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5424 #if DEBUG_STACK_ALIGNMENT
5425 /* check the stack is aligned */
5426 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5427 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5428 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5429 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5430 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5431 x86_breakpoint (code);
5435 /* compute max_offset in order to use short forward jumps */
5437 if (cfg->opt & MONO_OPT_BRANCH) {
5438 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5440 bb->max_offset = max_offset;
5442 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5444 /* max alignment for loops */
5445 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5446 max_offset += LOOP_ALIGNMENT;
5447 #ifdef __native_client_codegen__
5448 /* max alignment for native client */
5449 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5450 max_offset += kNaClAlignment;
5452 MONO_BB_FOR_EACH_INS (bb, ins) {
5453 if (ins->opcode == OP_LABEL)
5454 ins->inst_c1 = max_offset;
5455 #ifdef __native_client_codegen__
5456 switch (ins->opcode)
5468 case OP_VOIDCALL_REG:
5470 case OP_FCALL_MEMBASE:
5471 case OP_LCALL_MEMBASE:
5472 case OP_VCALL_MEMBASE:
5473 case OP_VCALL2_MEMBASE:
5474 case OP_VOIDCALL_MEMBASE:
5475 case OP_CALL_MEMBASE:
5476 max_offset += kNaClAlignment;
5479 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5482 #endif /* __native_client_codegen__ */
5483 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5488 /* store runtime generic context */
5489 if (cfg->rgctx_var) {
5490 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5492 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5495 if (method->save_lmf) {
5496 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5498 code = emit_push_lmf (cfg, code, cfg->lmf_var->inst_offset);
5501 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5502 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5504 /* load arguments allocated to register from the stack */
5505 sig = mono_method_signature (method);
5508 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5509 inst = cfg->args [pos];
5510 if (inst->opcode == OP_REGVAR) {
5511 g_assert (need_stack_frame);
5512 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5513 if (cfg->verbose_level > 2)
5514 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5519 cfg->code_len = code - cfg->native_code;
5521 g_assert (cfg->code_len < cfg->code_size);
5527 mono_arch_emit_epilog (MonoCompile *cfg)
5529 MonoMethod *method = cfg->method;
5530 MonoMethodSignature *sig = mono_method_signature (method);
5532 guint32 stack_to_pop;
5534 int max_epilog_size = 16;
5536 gboolean need_stack_frame = needs_stack_frame (cfg);
5538 if (cfg->method->save_lmf)
5539 max_epilog_size += 128;
5541 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5542 cfg->code_size *= 2;
5543 cfg->native_code = mono_realloc_native_code(cfg);
5544 cfg->stat_code_reallocs++;
5547 code = cfg->native_code + cfg->code_len;
5549 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5550 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5552 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5555 if (method->save_lmf) {
5556 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5558 gboolean supported = FALSE;
5560 if (cfg->compile_aot) {
5561 #if defined(__APPLE__) || defined(__linux__)
5564 } else if (mono_get_jit_tls_offset () != -1) {
5568 /* check if we need to restore protection of the stack after a stack overflow */
5570 if (cfg->compile_aot) {
5571 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5573 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5575 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5578 /* we load the value in a separate instruction: this mechanism may be
5579 * used later as a safer way to do thread interruption
5581 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5582 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5584 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5585 /* note that the call trampoline will preserve eax/edx */
5586 x86_call_reg (code, X86_ECX);
5587 x86_patch (patch, code);
5589 /* FIXME: maybe save the jit tls in the prolog */
5593 code = emit_pop_lmf (cfg, code, lmf_offset);
5595 /* restore caller saved regs */
5596 if (cfg->used_int_regs & (1 << X86_EBX)) {
5597 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
5600 if (cfg->used_int_regs & (1 << X86_EDI)) {
5601 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
5603 if (cfg->used_int_regs & (1 << X86_ESI)) {
5604 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
5607 /* EBP is restored by LEAVE */
5609 for (i = 0; i < X86_NREG; ++i) {
5610 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5616 g_assert (need_stack_frame);
5617 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5621 g_assert (need_stack_frame);
5622 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5625 if (cfg->used_int_regs & (1 << X86_ESI)) {
5626 x86_pop_reg (code, X86_ESI);
5628 if (cfg->used_int_regs & (1 << X86_EDI)) {
5629 x86_pop_reg (code, X86_EDI);
5631 if (cfg->used_int_regs & (1 << X86_EBX)) {
5632 x86_pop_reg (code, X86_EBX);
5636 /* Load returned vtypes into registers if needed */
5637 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5638 if (cinfo->ret.storage == ArgValuetypeInReg) {
5639 for (quad = 0; quad < 2; quad ++) {
5640 switch (cinfo->ret.pair_storage [quad]) {
5642 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5644 case ArgOnFloatFpStack:
5645 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5647 case ArgOnDoubleFpStack:
5648 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5653 g_assert_not_reached ();
5658 if (need_stack_frame)
5661 if (CALLCONV_IS_STDCALL (sig)) {
5662 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5664 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5665 } else if (cinfo->vtype_retaddr)
5671 g_assert (need_stack_frame);
5672 x86_ret_imm (code, stack_to_pop);
5677 cfg->code_len = code - cfg->native_code;
5679 g_assert (cfg->code_len < cfg->code_size);
5683 mono_arch_emit_exceptions (MonoCompile *cfg)
5685 MonoJumpInfo *patch_info;
5688 MonoClass *exc_classes [16];
5689 guint8 *exc_throw_start [16], *exc_throw_end [16];
5693 /* Compute needed space */
5694 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5695 if (patch_info->type == MONO_PATCH_INFO_EXC)
5700 * make sure we have enough space for exceptions
5701 * 16 is the size of two push_imm instructions and a call
5703 if (cfg->compile_aot)
5704 code_size = exc_count * 32;
5706 code_size = exc_count * 16;
5708 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5709 cfg->code_size *= 2;
5710 cfg->native_code = mono_realloc_native_code(cfg);
5711 cfg->stat_code_reallocs++;
5714 code = cfg->native_code + cfg->code_len;
5717 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5718 switch (patch_info->type) {
5719 case MONO_PATCH_INFO_EXC: {
5720 MonoClass *exc_class;
5724 x86_patch (patch_info->ip.i + cfg->native_code, code);
5726 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5727 g_assert (exc_class);
5728 throw_ip = patch_info->ip.i;
5730 /* Find a throw sequence for the same exception class */
5731 for (i = 0; i < nthrows; ++i)
5732 if (exc_classes [i] == exc_class)
5735 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5736 x86_jump_code (code, exc_throw_start [i]);
5737 patch_info->type = MONO_PATCH_INFO_NONE;
5742 /* Compute size of code following the push <OFFSET> */
5743 #if defined(__default_codegen__)
5745 #elif defined(__native_client_codegen__)
5746 code = mono_nacl_align (code);
5747 size = kNaClAlignment;
5749 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5751 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5752 /* Use the shorter form */
5754 x86_push_imm (code, 0);
5758 x86_push_imm (code, 0xf0f0f0f0);
5763 exc_classes [nthrows] = exc_class;
5764 exc_throw_start [nthrows] = code;
5767 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5768 patch_info->data.name = "mono_arch_throw_corlib_exception";
5769 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5770 patch_info->ip.i = code - cfg->native_code;
5771 x86_call_code (code, 0);
5772 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5777 exc_throw_end [nthrows] = code;
5789 cfg->code_len = code - cfg->native_code;
5791 g_assert (cfg->code_len < cfg->code_size);
5795 mono_arch_flush_icache (guint8 *code, gint size)
5801 mono_arch_flush_register_windows (void)
5806 mono_arch_is_inst_imm (gint64 imm)
5812 mono_arch_finish_init (void)
5814 if (!g_getenv ("MONO_NO_TLS")) {
5817 * We need to init this multiple times, since when we are first called, the key might not
5818 * be initialized yet.
5820 jit_tls_offset = mono_get_jit_tls_key ();
5822 /* Only 64 tls entries can be accessed using inline code */
5823 if (jit_tls_offset >= 64)
5824 jit_tls_offset = -1;
5827 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5829 lmf_tls_offset = mono_get_lmf_tls_offset ();
5830 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5836 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5840 #ifdef MONO_ARCH_HAVE_IMT
5842 // Linear handler, the bsearch head compare is shorter
5843 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5844 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5845 // x86_patch(ins,target)
5846 //[1 + 5] x86_jump_mem(inst,mem)
5849 #if defined(__default_codegen__)
5850 #define BR_SMALL_SIZE 2
5851 #define BR_LARGE_SIZE 5
5852 #elif defined(__native_client_codegen__)
5853 /* I suspect the size calculation below is actually incorrect. */
5854 /* TODO: fix the calculation that uses these sizes. */
5855 #define BR_SMALL_SIZE 16
5856 #define BR_LARGE_SIZE 12
5857 #endif /*__native_client_codegen__*/
5858 #define JUMP_IMM_SIZE 6
5859 #define ENABLE_WRONG_METHOD_CHECK 0
5863 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5865 int i, distance = 0;
5866 for (i = start; i < target; ++i)
5867 distance += imt_entries [i]->chunk_size;
5872 * LOCKING: called with the domain lock held
5875 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5876 gpointer fail_tramp)
5880 guint8 *code, *start;
5882 for (i = 0; i < count; ++i) {
5883 MonoIMTCheckItem *item = imt_entries [i];
5884 if (item->is_equals) {
5885 if (item->check_target_idx) {
5886 if (!item->compare_done)
5887 item->chunk_size += CMP_SIZE;
5888 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5891 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5893 item->chunk_size += JUMP_IMM_SIZE;
5894 #if ENABLE_WRONG_METHOD_CHECK
5895 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5900 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5901 imt_entries [item->check_target_idx]->compare_done = TRUE;
5903 size += item->chunk_size;
5905 #if defined(__native_client__) && defined(__native_client_codegen__)
5906 /* In Native Client, we don't re-use thunks, allocate from the */
5907 /* normal code manager paths. */
5908 size = NACL_BUNDLE_ALIGN_UP (size);
5909 code = mono_domain_code_reserve (domain, size);
5912 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5914 code = mono_domain_code_reserve (domain, size);
5917 for (i = 0; i < count; ++i) {
5918 MonoIMTCheckItem *item = imt_entries [i];
5919 item->code_target = code;
5920 if (item->is_equals) {
5921 if (item->check_target_idx) {
5922 if (!item->compare_done)
5923 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5924 item->jmp_code = code;
5925 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5926 if (item->has_target_code)
5927 x86_jump_code (code, item->value.target_code);
5929 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5932 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5933 item->jmp_code = code;
5934 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5935 if (item->has_target_code)
5936 x86_jump_code (code, item->value.target_code);
5938 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5939 x86_patch (item->jmp_code, code);
5940 x86_jump_code (code, fail_tramp);
5941 item->jmp_code = NULL;
5943 /* enable the commented code to assert on wrong method */
5944 #if ENABLE_WRONG_METHOD_CHECK
5945 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5946 item->jmp_code = code;
5947 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5949 if (item->has_target_code)
5950 x86_jump_code (code, item->value.target_code);
5952 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5953 #if ENABLE_WRONG_METHOD_CHECK
5954 x86_patch (item->jmp_code, code);
5955 x86_breakpoint (code);
5956 item->jmp_code = NULL;
5961 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5962 item->jmp_code = code;
5963 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5964 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5966 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5969 /* patch the branches to get to the target items */
5970 for (i = 0; i < count; ++i) {
5971 MonoIMTCheckItem *item = imt_entries [i];
5972 if (item->jmp_code) {
5973 if (item->check_target_idx) {
5974 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5980 mono_stats.imt_thunks_size += code - start;
5981 g_assert (code - start <= size);
5985 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5986 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5990 if (mono_jit_map_is_enabled ()) {
5993 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5995 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5996 mono_emit_jit_tramp (start, code - start, buff);
6000 nacl_domain_code_validate (domain, &start, size, &code);
6006 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6008 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
6013 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6015 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6019 mono_arch_get_cie_program (void)
6023 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
6024 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
6030 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6032 MonoInst *ins = NULL;
6035 if (cmethod->klass == mono_defaults.math_class) {
6036 if (strcmp (cmethod->name, "Sin") == 0) {
6038 } else if (strcmp (cmethod->name, "Cos") == 0) {
6040 } else if (strcmp (cmethod->name, "Tan") == 0) {
6042 } else if (strcmp (cmethod->name, "Atan") == 0) {
6044 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6046 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6048 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
6053 MONO_INST_NEW (cfg, ins, opcode);
6054 ins->type = STACK_R8;
6055 ins->dreg = mono_alloc_freg (cfg);
6056 ins->sreg1 = args [0]->dreg;
6057 MONO_ADD_INS (cfg->cbb, ins);
6060 if (cfg->opt & MONO_OPT_CMOV) {
6063 if (strcmp (cmethod->name, "Min") == 0) {
6064 if (fsig->params [0]->type == MONO_TYPE_I4)
6066 } else if (strcmp (cmethod->name, "Max") == 0) {
6067 if (fsig->params [0]->type == MONO_TYPE_I4)
6072 MONO_INST_NEW (cfg, ins, opcode);
6073 ins->type = STACK_I4;
6074 ins->dreg = mono_alloc_ireg (cfg);
6075 ins->sreg1 = args [0]->dreg;
6076 ins->sreg2 = args [1]->dreg;
6077 MONO_ADD_INS (cfg->cbb, ins);
6082 /* OP_FREM is not IEEE compatible */
6083 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6084 MONO_INST_NEW (cfg, ins, OP_FREM);
6085 ins->inst_i0 = args [0];
6086 ins->inst_i1 = args [1];
6095 mono_arch_print_tree (MonoInst *tree, int arity)
6101 mono_arch_get_patch_offset (guint8 *code)
6103 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
6105 else if (code [0] == 0xba)
6107 else if (code [0] == 0x68)
6110 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
6111 /* push <OFFSET>(<REG>) */
6113 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
6114 /* call *<OFFSET>(<REG>) */
6116 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
6119 else if ((code [0] == 0x58) && (code [1] == 0x05))
6120 /* pop %eax; add <OFFSET>, %eax */
6122 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6123 /* pop <REG>; add <OFFSET>, <REG> */
6125 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6126 /* mov <REG>, imm */
6129 g_assert_not_reached ();
6135 * mono_breakpoint_clean_code:
6137 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6138 * breakpoints in the original code, they are removed in the copy.
6140 * Returns TRUE if no sw breakpoint was present.
6143 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6146 gboolean can_write = TRUE;
6148 * If method_start is non-NULL we need to perform bound checks, since we access memory
6149 * at code - offset we could go before the start of the method and end up in a different
6150 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6153 if (!method_start || code - offset >= method_start) {
6154 memcpy (buf, code - offset, size);
6156 int diff = code - method_start;
6157 memset (buf, 0, size);
6158 memcpy (buf + offset - diff, method_start, diff + size - offset);
6161 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6162 int idx = mono_breakpoint_info_index [i];
6166 ptr = mono_breakpoint_info [idx].address;
6167 if (ptr >= code && ptr < code + size) {
6168 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6170 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6171 buf [ptr - code] = saved_byte;
6178 * mono_x86_get_this_arg_offset:
6180 * Return the offset of the stack location where this is passed during a virtual
6184 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6190 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6192 guint32 esp = regs [X86_ESP];
6193 CallInfo *cinfo = NULL;
6200 * The stack looks like:
6204 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
6206 res = (((MonoObject**)esp) [5 + (offset / 4)]);
6212 #define MAX_ARCH_DELEGATE_PARAMS 10
6215 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6217 guint8 *code, *start;
6218 int code_reserve = 64;
6221 * The stack contains:
6227 start = code = mono_global_codeman_reserve (code_reserve);
6229 /* Replace the this argument with the target */
6230 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6231 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
6232 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6233 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6235 g_assert ((code - start) < code_reserve);
6238 /* 8 for mov_reg and jump, plus 8 for each parameter */
6239 #ifdef __native_client_codegen__
6240 /* TODO: calculate this size correctly */
6241 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6243 code_reserve = 8 + (param_count * 8);
6244 #endif /* __native_client_codegen__ */
6246 * The stack contains:
6247 * <args in reverse order>
6252 * <args in reverse order>
6255 * without unbalancing the stack.
6256 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6257 * and leaving original spot of first arg as placeholder in stack so
6258 * when callee pops stack everything works.
6261 start = code = mono_global_codeman_reserve (code_reserve);
6263 /* store delegate for access to method_ptr */
6264 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6267 for (i = 0; i < param_count; ++i) {
6268 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6269 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6272 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6274 g_assert ((code - start) < code_reserve);
6277 nacl_global_codeman_validate(&start, code_reserve, &code);
6278 mono_debug_add_delegate_trampoline (start, code - start);
6281 *code_len = code - start;
6283 if (mono_jit_map_is_enabled ()) {
6286 buff = (char*)"delegate_invoke_has_target";
6288 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6289 mono_emit_jit_tramp (start, code - start, buff);
6298 mono_arch_get_delegate_invoke_impls (void)
6306 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6307 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
6309 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6310 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6311 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
6312 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
6313 g_free (tramp_name);
6320 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6322 guint8 *code, *start;
6324 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6327 /* FIXME: Support more cases */
6328 if (MONO_TYPE_ISSTRUCT (sig->ret))
6332 * The stack contains:
6338 static guint8* cached = NULL;
6343 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6345 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6347 mono_memory_barrier ();
6351 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6354 for (i = 0; i < sig->param_count; ++i)
6355 if (!mono_is_regsize_var (sig->params [i]))
6358 code = cache [sig->param_count];
6362 if (mono_aot_only) {
6363 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6364 start = mono_aot_get_trampoline (name);
6367 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6370 mono_memory_barrier ();
6372 cache [sig->param_count] = start;
6379 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6382 case X86_EAX: return ctx->eax;
6383 case X86_EBX: return ctx->ebx;
6384 case X86_ECX: return ctx->ecx;
6385 case X86_EDX: return ctx->edx;
6386 case X86_ESP: return ctx->esp;
6387 case X86_EBP: return ctx->ebp;
6388 case X86_ESI: return ctx->esi;
6389 case X86_EDI: return ctx->edi;
6391 g_assert_not_reached ();
6397 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6425 g_assert_not_reached ();
6429 #ifdef MONO_ARCH_SIMD_INTRINSICS
6432 get_float_to_x_spill_area (MonoCompile *cfg)
6434 if (!cfg->fconv_to_r8_x_var) {
6435 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6436 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6438 return cfg->fconv_to_r8_x_var;
6442 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6445 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6448 int dreg, src_opcode;
6450 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6453 switch (src_opcode = ins->opcode) {
6454 case OP_FCONV_TO_I1:
6455 case OP_FCONV_TO_U1:
6456 case OP_FCONV_TO_I2:
6457 case OP_FCONV_TO_U2:
6458 case OP_FCONV_TO_I4:
6465 /* dreg is the IREG and sreg1 is the FREG */
6466 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6467 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6468 fconv->sreg1 = ins->sreg1;
6469 fconv->dreg = mono_alloc_ireg (cfg);
6470 fconv->type = STACK_VTYPE;
6471 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6473 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6477 ins->opcode = OP_XCONV_R8_TO_I4;
6479 ins->klass = mono_defaults.int32_class;
6480 ins->sreg1 = fconv->dreg;
6482 ins->type = STACK_I4;
6483 ins->backend.source_opcode = src_opcode;
6486 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6489 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6494 if (long_ins->opcode == OP_LNEG) {
6496 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6497 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6498 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6503 #ifdef MONO_ARCH_SIMD_INTRINSICS
6505 if (!(cfg->opt & MONO_OPT_SIMD))
6508 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6509 switch (long_ins->opcode) {
6511 vreg = long_ins->sreg1;
6513 if (long_ins->inst_c0) {
6514 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6515 ins->klass = long_ins->klass;
6516 ins->sreg1 = long_ins->sreg1;
6518 ins->type = STACK_VTYPE;
6519 ins->dreg = vreg = alloc_ireg (cfg);
6520 MONO_ADD_INS (cfg->cbb, ins);
6523 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6524 ins->klass = mono_defaults.int32_class;
6526 ins->type = STACK_I4;
6527 ins->dreg = long_ins->dreg + 1;
6528 MONO_ADD_INS (cfg->cbb, ins);
6530 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6531 ins->klass = long_ins->klass;
6532 ins->sreg1 = long_ins->sreg1;
6533 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6534 ins->type = STACK_VTYPE;
6535 ins->dreg = vreg = alloc_ireg (cfg);
6536 MONO_ADD_INS (cfg->cbb, ins);
6538 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6539 ins->klass = mono_defaults.int32_class;
6541 ins->type = STACK_I4;
6542 ins->dreg = long_ins->dreg + 2;
6543 MONO_ADD_INS (cfg->cbb, ins);
6545 long_ins->opcode = OP_NOP;
6547 case OP_INSERTX_I8_SLOW:
6548 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6549 ins->dreg = long_ins->dreg;
6550 ins->sreg1 = long_ins->dreg;
6551 ins->sreg2 = long_ins->sreg2 + 1;
6552 ins->inst_c0 = long_ins->inst_c0 * 2;
6553 MONO_ADD_INS (cfg->cbb, ins);
6555 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6556 ins->dreg = long_ins->dreg;
6557 ins->sreg1 = long_ins->dreg;
6558 ins->sreg2 = long_ins->sreg2 + 2;
6559 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6560 MONO_ADD_INS (cfg->cbb, ins);
6562 long_ins->opcode = OP_NOP;
6565 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6566 ins->dreg = long_ins->dreg;
6567 ins->sreg1 = long_ins->sreg1 + 1;
6568 ins->klass = long_ins->klass;
6569 ins->type = STACK_VTYPE;
6570 MONO_ADD_INS (cfg->cbb, ins);
6572 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6573 ins->dreg = long_ins->dreg;
6574 ins->sreg1 = long_ins->dreg;
6575 ins->sreg2 = long_ins->sreg1 + 2;
6577 ins->klass = long_ins->klass;
6578 ins->type = STACK_VTYPE;
6579 MONO_ADD_INS (cfg->cbb, ins);
6581 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6582 ins->dreg = long_ins->dreg;
6583 ins->sreg1 = long_ins->dreg;;
6584 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6585 ins->klass = long_ins->klass;
6586 ins->type = STACK_VTYPE;
6587 MONO_ADD_INS (cfg->cbb, ins);
6589 long_ins->opcode = OP_NOP;
6592 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6595 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6597 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6600 gpointer *sp, old_value;
6602 const unsigned char *handler;
6604 /*Decode the first instruction to figure out where did we store the spvar*/
6605 /*Our jit MUST generate the following:
6607 Which is encoded as: 0x89 mod_rm.
6608 mod_rm (esp, ebp, imm) which can be: (imm will never be zero)
6609 mod (reg + imm8): 01 reg(esp): 100 rm(ebp): 101 -> 01100101 (0x65)
6610 mod (reg + imm32): 10 reg(esp): 100 rm(ebp): 101 -> 10100101 (0xA5)
6612 handler = clause->handler_start;
6614 if (*handler != 0x89)
6619 if (*handler == 0x65)
6620 offset = *(signed char*)(handler + 1);
6621 else if (*handler == 0xA5)
6622 offset = *(int*)(handler + 1);
6627 bp = MONO_CONTEXT_GET_BP (ctx);
6628 sp = *(gpointer*)(bp + offset);
6631 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6640 * mono_aot_emit_load_got_addr:
6642 * Emit code to load the got address.
6643 * On x86, the result is placed into EBX.
6646 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6648 x86_call_imm (code, 0);
6650 * The patch needs to point to the pop, since the GOT offset needs
6651 * to be added to that address.
6654 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6656 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6657 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6658 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6664 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6667 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6669 g_assert_not_reached ();
6670 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6675 * mono_arch_emit_load_aotconst:
6677 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6678 * TARGET from the mscorlib GOT in full-aot code.
6679 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6683 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6685 /* Load the mscorlib got address */
6686 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6687 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6688 /* arch_emit_got_access () patches this */
6689 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6694 /* Can't put this into mini-x86.h */
6696 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6699 mono_arch_get_trampolines (gboolean aot)
6701 MonoTrampInfo *info;
6702 GSList *tramps = NULL;
6704 mono_x86_get_signal_exception_trampoline (&info, aot);
6706 tramps = g_slist_append (tramps, info);
6713 #define DBG_SIGNAL SIGBUS
6715 #define DBG_SIGNAL SIGSEGV
6718 /* Soft Debug support */
6719 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6722 * mono_arch_set_breakpoint:
6724 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6725 * The location should contain code emitted by OP_SEQ_POINT.
6728 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6733 * In production, we will use int3 (has to fix the size in the md
6734 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6737 g_assert (code [0] == 0x90);
6738 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6742 * mono_arch_clear_breakpoint:
6744 * Clear the breakpoint at IP.
6747 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6752 for (i = 0; i < 6; ++i)
6757 * mono_arch_start_single_stepping:
6759 * Start single stepping.
6762 mono_arch_start_single_stepping (void)
6764 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6768 * mono_arch_stop_single_stepping:
6770 * Stop single stepping.
6773 mono_arch_stop_single_stepping (void)
6775 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6779 * mono_arch_is_single_step_event:
6781 * Return whenever the machine state in SIGCTX corresponds to a single
6785 mono_arch_is_single_step_event (void *info, void *sigctx)
6788 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6790 if (((gpointer)einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6795 siginfo_t* sinfo = (siginfo_t*) info;
6796 /* Sometimes the address is off by 4 */
6797 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6805 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6808 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6809 if (((gpointer)einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6814 siginfo_t* sinfo = (siginfo_t*)info;
6815 /* Sometimes the address is off by 4 */
6816 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6823 #define BREAKPOINT_SIZE 6
6826 * mono_arch_skip_breakpoint:
6828 * See mini-amd64.c for docs.
6831 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6833 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6837 * mono_arch_skip_single_step:
6839 * See mini-amd64.c for docs.
6842 mono_arch_skip_single_step (MonoContext *ctx)
6844 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6848 * mono_arch_get_seq_point_info:
6850 * See mini-amd64.c for docs.
6853 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6860 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6862 ext->lmf.previous_lmf = (gsize)prev_lmf;
6863 /* Mark that this is a MonoLMFExt */
6864 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6865 ext->lmf.ebp = (gssize)ext;
6870 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
6872 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6874 #endif /* !MONOTOUCH */