2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/appdomain.h>
21 #include <mono/metadata/debug-helpers.h>
22 #include <mono/metadata/threads.h>
23 #include <mono/metadata/profiler-private.h>
24 #include <mono/metadata/mono-debug.h>
25 #include <mono/metadata/gc-internal.h>
26 #include <mono/utils/mono-math.h>
27 #include <mono/utils/mono-counters.h>
28 #include <mono/utils/mono-mmap.h>
29 #include <mono/utils/mono-memory-model.h>
30 #include <mono/utils/mono-hwcap-x86.h>
38 /* On windows, these hold the key returned by TlsAlloc () */
40 static gint jit_tls_offset = -1;
42 static gint lmf_addr_tls_offset = -1;
46 static gboolean optimize_for_xen = TRUE;
48 #define optimize_for_xen 0
51 /* This mutex protects architecture specific caches */
52 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
53 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
54 static CRITICAL_SECTION mini_arch_mutex;
56 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
61 /* Under windows, the default pinvoke calling convention is stdcall */
62 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
64 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
67 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
70 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
73 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
75 #ifdef __native_client_codegen__
77 /* Default alignment for Native Client is 32-byte. */
78 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
80 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
81 /* Check that alignment doesn't cross an alignment boundary. */
83 mono_arch_nacl_pad (guint8 *code, int pad)
85 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
87 if (pad == 0) return code;
88 /* assertion: alignment cannot cross a block boundary */
89 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
90 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
91 while (pad >= kMaxPadding) {
92 x86_padding (code, kMaxPadding);
95 if (pad != 0) x86_padding (code, pad);
100 mono_arch_nacl_skip_nops (guint8 *code)
102 x86_skip_nops (code);
106 #endif /* __native_client_codegen__ */
109 * The code generated for sequence points reads from this location, which is
110 * made read-only when single stepping is enabled.
112 static gpointer ss_trigger_page;
114 /* Enabled breakpoints read from this trigger page */
115 static gpointer bp_trigger_page;
118 mono_arch_regname (int reg)
121 case X86_EAX: return "%eax";
122 case X86_EBX: return "%ebx";
123 case X86_ECX: return "%ecx";
124 case X86_EDX: return "%edx";
125 case X86_ESP: return "%esp";
126 case X86_EBP: return "%ebp";
127 case X86_EDI: return "%edi";
128 case X86_ESI: return "%esi";
134 mono_arch_fregname (int reg)
159 mono_arch_xregname (int reg)
184 mono_x86_patch (unsigned char* code, gpointer target)
186 x86_patch (code, (unsigned char*)target);
197 /* gsharedvt argument passed by addr */
209 /* Only if storage == ArgValuetypeInReg */
210 ArgStorage pair_storage [2];
219 gboolean need_stack_align;
220 guint32 stack_align_amount;
221 gboolean vtype_retaddr;
222 /* The index of the vret arg in the argument list */
230 #define FLOAT_PARAM_REGS 0
232 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
234 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
239 switch (sig->call_convention) {
240 case MONO_CALL_THISCALL:
241 return thiscall_param_regs;
247 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
248 #define SMALL_STRUCTS_IN_REGS
249 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
253 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
255 ainfo->offset = *stack_size;
257 if (!param_regs || param_regs [*gr] == X86_NREG) {
258 ainfo->storage = ArgOnStack;
260 (*stack_size) += sizeof (gpointer);
263 ainfo->storage = ArgInIReg;
264 ainfo->reg = param_regs [*gr];
270 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
272 ainfo->offset = *stack_size;
274 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
276 ainfo->storage = ArgOnStack;
277 (*stack_size) += sizeof (gpointer) * 2;
282 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
284 ainfo->offset = *stack_size;
286 if (*gr >= FLOAT_PARAM_REGS) {
287 ainfo->storage = ArgOnStack;
288 (*stack_size) += is_double ? 8 : 4;
289 ainfo->nslots = is_double ? 2 : 1;
292 /* A double register */
294 ainfo->storage = ArgInDoubleSSEReg;
296 ainfo->storage = ArgInFloatSSEReg;
304 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
306 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
311 klass = mono_class_from_mono_type (type);
312 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
314 #ifdef SMALL_STRUCTS_IN_REGS
315 if (sig->pinvoke && is_return) {
316 MonoMarshalType *info;
319 * the exact rules are not very well documented, the code below seems to work with the
320 * code generated by gcc 3.3.3 -mno-cygwin.
322 info = mono_marshal_load_type_info (klass);
325 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
327 /* Special case structs with only a float member */
328 if (info->num_fields == 1) {
329 int ftype = mini_replace_type (info->fields [0].field->type)->type;
330 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
331 ainfo->storage = ArgValuetypeInReg;
332 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
335 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
336 ainfo->storage = ArgValuetypeInReg;
337 ainfo->pair_storage [0] = ArgOnFloatFpStack;
341 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
342 ainfo->storage = ArgValuetypeInReg;
343 ainfo->pair_storage [0] = ArgInIReg;
344 ainfo->pair_regs [0] = return_regs [0];
345 if (info->native_size > 4) {
346 ainfo->pair_storage [1] = ArgInIReg;
347 ainfo->pair_regs [1] = return_regs [1];
354 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
355 g_assert (size <= 4);
356 ainfo->storage = ArgValuetypeInReg;
357 ainfo->reg = param_regs [*gr];
362 ainfo->offset = *stack_size;
363 ainfo->storage = ArgOnStack;
364 *stack_size += ALIGN_TO (size, sizeof (gpointer));
365 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
371 * Obtain information about a call according to the calling convention.
372 * For x86 ELF, see the "System V Application Binary Interface Intel386
373 * Architecture Processor Supplment, Fourth Edition" document for more
375 * For x86 win32, see ???.
378 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
380 guint32 i, gr, fr, pstart;
381 const guint32 *param_regs;
383 int n = sig->hasthis + sig->param_count;
384 guint32 stack_size = 0;
385 gboolean is_pinvoke = sig->pinvoke;
391 param_regs = callconv_param_regs(sig);
395 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
396 switch (ret_type->type) {
397 case MONO_TYPE_BOOLEAN:
408 case MONO_TYPE_FNPTR:
409 case MONO_TYPE_CLASS:
410 case MONO_TYPE_OBJECT:
411 case MONO_TYPE_SZARRAY:
412 case MONO_TYPE_ARRAY:
413 case MONO_TYPE_STRING:
414 cinfo->ret.storage = ArgInIReg;
415 cinfo->ret.reg = X86_EAX;
419 cinfo->ret.storage = ArgInIReg;
420 cinfo->ret.reg = X86_EAX;
421 cinfo->ret.is_pair = TRUE;
424 cinfo->ret.storage = ArgOnFloatFpStack;
427 cinfo->ret.storage = ArgOnDoubleFpStack;
429 case MONO_TYPE_GENERICINST:
430 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
431 cinfo->ret.storage = ArgInIReg;
432 cinfo->ret.reg = X86_EAX;
435 if (mini_is_gsharedvt_type_gsctx (gsctx, ret_type)) {
436 cinfo->ret.storage = ArgOnStack;
437 cinfo->vtype_retaddr = TRUE;
441 case MONO_TYPE_VALUETYPE:
442 case MONO_TYPE_TYPEDBYREF: {
443 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
445 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
446 if (cinfo->ret.storage == ArgOnStack) {
447 cinfo->vtype_retaddr = TRUE;
448 /* The caller passes the address where the value is stored */
454 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ret_type));
455 cinfo->ret.storage = ArgOnStack;
456 cinfo->vtype_retaddr = TRUE;
459 cinfo->ret.storage = ArgNone;
462 g_error ("Can't handle as return value 0x%x", ret_type->type);
468 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
469 * the first argument, allowing 'this' to be always passed in the first arg reg.
470 * Also do this if the first argument is a reference type, since virtual calls
471 * are sometimes made using calli without sig->hasthis set, like in the delegate
474 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
476 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
478 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
481 cinfo->vret_arg_offset = stack_size;
482 add_general (&gr, NULL, &stack_size, &cinfo->ret);
483 cinfo->vret_arg_index = 1;
487 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
489 if (cinfo->vtype_retaddr)
490 add_general (&gr, NULL, &stack_size, &cinfo->ret);
493 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
494 fr = FLOAT_PARAM_REGS;
496 /* Emit the signature cookie just before the implicit arguments */
497 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
500 for (i = pstart; i < sig->param_count; ++i) {
501 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
504 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
505 /* We allways pass the sig cookie on the stack for simplicity */
507 * Prevent implicit arguments + the sig cookie from being passed
510 fr = FLOAT_PARAM_REGS;
512 /* Emit the signature cookie just before the implicit arguments */
513 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
516 if (sig->params [i]->byref) {
517 add_general (&gr, param_regs, &stack_size, ainfo);
520 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
521 switch (ptype->type) {
522 case MONO_TYPE_BOOLEAN:
525 add_general (&gr, param_regs, &stack_size, ainfo);
530 add_general (&gr, param_regs, &stack_size, ainfo);
534 add_general (&gr, param_regs, &stack_size, ainfo);
539 case MONO_TYPE_FNPTR:
540 case MONO_TYPE_CLASS:
541 case MONO_TYPE_OBJECT:
542 case MONO_TYPE_STRING:
543 case MONO_TYPE_SZARRAY:
544 case MONO_TYPE_ARRAY:
545 add_general (&gr, param_regs, &stack_size, ainfo);
547 case MONO_TYPE_GENERICINST:
548 if (!mono_type_generic_inst_is_valuetype (ptype)) {
549 add_general (&gr, param_regs, &stack_size, ainfo);
552 if (mini_is_gsharedvt_type_gsctx (gsctx, ptype)) {
553 /* gsharedvt arguments are passed by ref */
554 add_general (&gr, param_regs, &stack_size, ainfo);
555 g_assert (ainfo->storage == ArgOnStack);
556 ainfo->storage = ArgGSharedVt;
560 case MONO_TYPE_VALUETYPE:
561 case MONO_TYPE_TYPEDBYREF:
562 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
566 add_general_pair (&gr, param_regs, &stack_size, ainfo);
569 add_float (&fr, &stack_size, ainfo, FALSE);
572 add_float (&fr, &stack_size, ainfo, TRUE);
576 /* gsharedvt arguments are passed by ref */
577 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ptype));
578 add_general (&gr, param_regs, &stack_size, ainfo);
579 g_assert (ainfo->storage == ArgOnStack);
580 ainfo->storage = ArgGSharedVt;
583 g_error ("unexpected type 0x%x", ptype->type);
584 g_assert_not_reached ();
588 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
589 fr = FLOAT_PARAM_REGS;
591 /* Emit the signature cookie just before the implicit arguments */
592 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
595 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
596 cinfo->need_stack_align = TRUE;
597 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
598 stack_size += cinfo->stack_align_amount;
601 cinfo->stack_usage = stack_size;
602 cinfo->reg_usage = gr;
603 cinfo->freg_usage = fr;
608 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
610 int n = sig->hasthis + sig->param_count;
614 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
616 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
618 return get_call_info_internal (gsctx, cinfo, sig);
622 * mono_arch_get_argument_info:
623 * @csig: a method signature
624 * @param_count: the number of parameters to consider
625 * @arg_info: an array to store the result infos
627 * Gathers information on parameters such as size, alignment and
628 * padding. arg_info should be large enought to hold param_count + 1 entries.
630 * Returns the size of the argument area on the stack.
631 * This should be signal safe, since it is called from
632 * mono_arch_find_jit_info ().
633 * FIXME: The metadata calls might not be signal safe.
636 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
638 int len, k, args_size = 0;
644 /* Avoid g_malloc as it is not signal safe */
645 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
646 cinfo = (CallInfo*)g_newa (guint8*, len);
647 memset (cinfo, 0, len);
649 cinfo = get_call_info_internal (gsctx, cinfo, csig);
651 arg_info [0].offset = offset;
653 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
654 args_size += sizeof (gpointer);
659 args_size += sizeof (gpointer);
663 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
664 /* Emitted after this */
665 args_size += sizeof (gpointer);
669 arg_info [0].size = args_size;
671 for (k = 0; k < param_count; k++) {
672 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
674 /* ignore alignment for now */
677 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
678 arg_info [k].pad = pad;
680 arg_info [k + 1].pad = 0;
681 arg_info [k + 1].size = size;
683 arg_info [k + 1].offset = offset;
686 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
687 /* Emitted after the first arg */
688 args_size += sizeof (gpointer);
693 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
694 align = MONO_ARCH_FRAME_ALIGNMENT;
697 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
698 arg_info [k].pad = pad;
704 mono_arch_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
706 MonoType *callee_ret;
710 c1 = get_call_info (NULL, NULL, caller_sig);
711 c2 = get_call_info (NULL, NULL, callee_sig);
713 * Tail calls with more callee stack usage than the caller cannot be supported, since
714 * the extra stack space would be left on the stack after the tail call.
716 res = c1->stack_usage >= c2->stack_usage;
717 callee_ret = mini_replace_type (callee_sig->ret);
718 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
719 /* An address on the callee's stack is passed as the first argument */
729 * Initialize the cpu to execute managed code.
732 mono_arch_cpu_init (void)
734 /* spec compliance requires running with double precision */
738 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
739 fpcw &= ~X86_FPCW_PRECC_MASK;
740 fpcw |= X86_FPCW_PREC_DOUBLE;
741 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
742 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
744 _control87 (_PC_53, MCW_PC);
749 * Initialize architecture specific code.
752 mono_arch_init (void)
754 InitializeCriticalSection (&mini_arch_mutex);
756 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
757 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
758 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
760 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
761 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
762 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
763 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
768 * Cleanup architecture specific code.
771 mono_arch_cleanup (void)
774 mono_vfree (ss_trigger_page, mono_pagesize ());
776 mono_vfree (bp_trigger_page, mono_pagesize ());
777 DeleteCriticalSection (&mini_arch_mutex);
781 * This function returns the optimizations supported on this cpu.
784 mono_arch_cpu_optimizations (guint32 *exclude_mask)
786 #if !defined(__native_client__)
791 if (mono_hwcap_x86_has_cmov) {
792 opts |= MONO_OPT_CMOV;
794 if (mono_hwcap_x86_has_fcmov)
795 opts |= MONO_OPT_FCMOV;
797 *exclude_mask |= MONO_OPT_FCMOV;
799 *exclude_mask |= MONO_OPT_CMOV;
802 if (mono_hwcap_x86_has_sse2)
803 opts |= MONO_OPT_SSE2;
805 *exclude_mask |= MONO_OPT_SSE2;
807 #ifdef MONO_ARCH_SIMD_INTRINSICS
808 /*SIMD intrinsics require at least SSE2.*/
809 if (!mono_hwcap_x86_has_sse2)
810 *exclude_mask |= MONO_OPT_SIMD;
815 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
820 * This function test for all SSE functions supported.
822 * Returns a bitmask corresponding to all supported versions.
826 mono_arch_cpu_enumerate_simd_versions (void)
828 guint32 sse_opts = 0;
830 if (mono_hwcap_x86_has_sse1)
831 sse_opts |= SIMD_VERSION_SSE1;
833 if (mono_hwcap_x86_has_sse2)
834 sse_opts |= SIMD_VERSION_SSE2;
836 if (mono_hwcap_x86_has_sse3)
837 sse_opts |= SIMD_VERSION_SSE3;
839 if (mono_hwcap_x86_has_ssse3)
840 sse_opts |= SIMD_VERSION_SSSE3;
842 if (mono_hwcap_x86_has_sse41)
843 sse_opts |= SIMD_VERSION_SSE41;
845 if (mono_hwcap_x86_has_sse42)
846 sse_opts |= SIMD_VERSION_SSE42;
848 if (mono_hwcap_x86_has_sse4a)
849 sse_opts |= SIMD_VERSION_SSE4a;
855 * Determine whenever the trap whose info is in SIGINFO is caused by
859 mono_arch_is_int_overflow (void *sigctx, void *info)
864 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
866 ip = (guint8*)ctx.eip;
868 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
872 switch (x86_modrm_rm (ip [1])) {
892 g_assert_not_reached ();
904 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
909 for (i = 0; i < cfg->num_varinfo; i++) {
910 MonoInst *ins = cfg->varinfo [i];
911 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
914 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
917 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
918 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
921 /* we dont allocate I1 to registers because there is no simply way to sign extend
922 * 8bit quantities in caller saved registers on x86 */
923 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
924 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
925 g_assert (i == vmv->idx);
926 vars = g_list_prepend (vars, vmv);
930 vars = mono_varlist_sort (cfg, vars, 0);
936 mono_arch_get_global_int_regs (MonoCompile *cfg)
940 /* we can use 3 registers for global allocation */
941 regs = g_list_prepend (regs, (gpointer)X86_EBX);
942 regs = g_list_prepend (regs, (gpointer)X86_ESI);
943 regs = g_list_prepend (regs, (gpointer)X86_EDI);
949 * mono_arch_regalloc_cost:
951 * Return the cost, in number of memory references, of the action of
952 * allocating the variable VMV into a register during global register
956 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
958 MonoInst *ins = cfg->varinfo [vmv->idx];
960 if (cfg->method->save_lmf)
961 /* The register is already saved */
962 return (ins->opcode == OP_ARG) ? 1 : 0;
964 /* push+pop+possible load if it is an argument */
965 return (ins->opcode == OP_ARG) ? 3 : 2;
969 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
971 static int inited = FALSE;
972 static int count = 0;
974 if (cfg->arch.need_stack_frame_inited) {
975 g_assert (cfg->arch.need_stack_frame == flag);
979 cfg->arch.need_stack_frame = flag;
980 cfg->arch.need_stack_frame_inited = TRUE;
986 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
991 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
995 needs_stack_frame (MonoCompile *cfg)
997 MonoMethodSignature *sig;
998 MonoMethodHeader *header;
999 gboolean result = FALSE;
1001 #if defined(__APPLE__)
1002 /*OSX requires stack frame code to have the correct alignment. */
1006 if (cfg->arch.need_stack_frame_inited)
1007 return cfg->arch.need_stack_frame;
1009 header = cfg->header;
1010 sig = mono_method_signature (cfg->method);
1012 if (cfg->disable_omit_fp)
1014 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1016 else if (cfg->method->save_lmf)
1018 else if (cfg->stack_offset)
1020 else if (cfg->param_area)
1022 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1024 else if (header->num_clauses)
1026 else if (sig->param_count + sig->hasthis)
1028 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1030 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1031 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1034 set_needs_stack_frame (cfg, result);
1036 return cfg->arch.need_stack_frame;
1040 * Set var information according to the calling convention. X86 version.
1041 * The locals var stuff should most likely be split in another method.
1044 mono_arch_allocate_vars (MonoCompile *cfg)
1046 MonoMethodSignature *sig;
1047 MonoMethodHeader *header;
1049 guint32 locals_stack_size, locals_stack_align;
1054 header = cfg->header;
1055 sig = mono_method_signature (cfg->method);
1057 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1059 cfg->frame_reg = X86_EBP;
1062 /* Reserve space to save LMF and caller saved registers */
1064 if (cfg->method->save_lmf) {
1065 /* The LMF var is allocated normally */
1067 if (cfg->used_int_regs & (1 << X86_EBX)) {
1071 if (cfg->used_int_regs & (1 << X86_EDI)) {
1075 if (cfg->used_int_regs & (1 << X86_ESI)) {
1080 switch (cinfo->ret.storage) {
1081 case ArgValuetypeInReg:
1082 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1084 cfg->ret->opcode = OP_REGOFFSET;
1085 cfg->ret->inst_basereg = X86_EBP;
1086 cfg->ret->inst_offset = - offset;
1092 /* Allocate locals */
1093 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1094 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1095 char *mname = mono_method_full_name (cfg->method, TRUE);
1096 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1097 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1101 if (locals_stack_align) {
1102 int prev_offset = offset;
1104 offset += (locals_stack_align - 1);
1105 offset &= ~(locals_stack_align - 1);
1107 while (prev_offset < offset) {
1109 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1112 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1113 cfg->locals_max_stack_offset = - offset;
1115 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1116 * have locals larger than 8 bytes we need to make sure that
1117 * they have the appropriate offset.
1119 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1120 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1121 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1122 if (offsets [i] != -1) {
1123 MonoInst *inst = cfg->varinfo [i];
1124 inst->opcode = OP_REGOFFSET;
1125 inst->inst_basereg = X86_EBP;
1126 inst->inst_offset = - (offset + offsets [i]);
1127 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1130 offset += locals_stack_size;
1134 * Allocate arguments+return value
1137 switch (cinfo->ret.storage) {
1139 if (cfg->vret_addr) {
1141 * In the new IR, the cfg->vret_addr variable represents the
1142 * vtype return value.
1144 cfg->vret_addr->opcode = OP_REGOFFSET;
1145 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1146 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1147 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1148 printf ("vret_addr =");
1149 mono_print_ins (cfg->vret_addr);
1152 cfg->ret->opcode = OP_REGOFFSET;
1153 cfg->ret->inst_basereg = X86_EBP;
1154 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1157 case ArgValuetypeInReg:
1160 cfg->ret->opcode = OP_REGVAR;
1161 cfg->ret->inst_c0 = cinfo->ret.reg;
1162 cfg->ret->dreg = cinfo->ret.reg;
1165 case ArgOnFloatFpStack:
1166 case ArgOnDoubleFpStack:
1169 g_assert_not_reached ();
1172 if (sig->call_convention == MONO_CALL_VARARG) {
1173 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1174 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1177 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1178 ArgInfo *ainfo = &cinfo->args [i];
1179 inst = cfg->args [i];
1180 if (inst->opcode != OP_REGVAR) {
1181 inst->opcode = OP_REGOFFSET;
1182 inst->inst_basereg = X86_EBP;
1184 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1187 cfg->stack_offset = offset;
1191 mono_arch_create_vars (MonoCompile *cfg)
1194 MonoMethodSignature *sig;
1197 sig = mono_method_signature (cfg->method);
1199 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1200 sig_ret = mini_replace_type (sig->ret);
1202 if (cinfo->ret.storage == ArgValuetypeInReg)
1203 cfg->ret_var_is_local = TRUE;
1204 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (cfg, sig_ret))) {
1205 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1208 if (cfg->method->save_lmf) {
1209 cfg->create_lmf_var = TRUE;
1211 if (!optimize_for_xen) {
1213 cfg->lmf_ir_mono_lmf = TRUE;
1218 cfg->arch_eh_jit_info = 1;
1222 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1223 * so we try to do it just once when we have multiple fp arguments in a row.
1224 * We don't use this mechanism generally because for int arguments the generated code
1225 * is slightly bigger and new generation cpus optimize away the dependency chains
1226 * created by push instructions on the esp value.
1227 * fp_arg_setup is the first argument in the execution sequence where the esp register
1230 static G_GNUC_UNUSED int
1231 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1236 for (; start_arg < sig->param_count; ++start_arg) {
1237 t = mini_replace_type (sig->params [start_arg]);
1238 if (!t->byref && t->type == MONO_TYPE_R8) {
1239 fp_space += sizeof (double);
1240 *fp_arg_setup = start_arg;
1249 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1251 MonoMethodSignature *tmp_sig;
1255 * mono_ArgIterator_Setup assumes the signature cookie is
1256 * passed first and all the arguments which were before it are
1257 * passed on the stack after the signature. So compensate by
1258 * passing a different signature.
1260 tmp_sig = mono_metadata_signature_dup (call->signature);
1261 tmp_sig->param_count -= call->signature->sentinelpos;
1262 tmp_sig->sentinelpos = 0;
1263 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1265 if (cfg->compile_aot) {
1266 sig_reg = mono_alloc_ireg (cfg);
1267 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1268 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, sig_reg);
1270 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1276 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1281 LLVMCallInfo *linfo;
1282 MonoType *t, *sig_ret;
1284 n = sig->param_count + sig->hasthis;
1286 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1289 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1292 * LLVM always uses the native ABI while we use our own ABI, the
1293 * only difference is the handling of vtypes:
1294 * - we only pass/receive them in registers in some cases, and only
1295 * in 1 or 2 integer registers.
1297 if (cinfo->ret.storage == ArgValuetypeInReg) {
1299 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1300 cfg->disable_llvm = TRUE;
1304 cfg->exception_message = g_strdup ("vtype ret in call");
1305 cfg->disable_llvm = TRUE;
1307 linfo->ret.storage = LLVMArgVtypeInReg;
1308 for (j = 0; j < 2; ++j)
1309 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1313 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage == ArgInIReg) {
1314 /* Vtype returned using a hidden argument */
1315 linfo->ret.storage = LLVMArgVtypeRetAddr;
1316 linfo->vret_arg_index = cinfo->vret_arg_index;
1319 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage != ArgInIReg) {
1321 cfg->exception_message = g_strdup ("vtype ret in call");
1322 cfg->disable_llvm = TRUE;
1325 for (i = 0; i < n; ++i) {
1326 ainfo = cinfo->args + i;
1328 if (i >= sig->hasthis)
1329 t = sig->params [i - sig->hasthis];
1331 t = &mono_defaults.int_class->byval_arg;
1333 linfo->args [i].storage = LLVMArgNone;
1335 switch (ainfo->storage) {
1337 linfo->args [i].storage = LLVMArgInIReg;
1339 case ArgInDoubleSSEReg:
1340 case ArgInFloatSSEReg:
1341 linfo->args [i].storage = LLVMArgInFPReg;
1344 if (mini_type_is_vtype (cfg, t)) {
1345 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1346 /* LLVM seems to allocate argument space for empty structures too */
1347 linfo->args [i].storage = LLVMArgNone;
1349 linfo->args [i].storage = LLVMArgVtypeByVal;
1351 linfo->args [i].storage = LLVMArgInIReg;
1353 if (t->type == MONO_TYPE_R4)
1354 linfo->args [i].storage = LLVMArgInFPReg;
1355 else if (t->type == MONO_TYPE_R8)
1356 linfo->args [i].storage = LLVMArgInFPReg;
1360 case ArgValuetypeInReg:
1362 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1363 cfg->disable_llvm = TRUE;
1367 cfg->exception_message = g_strdup ("vtype arg");
1368 cfg->disable_llvm = TRUE;
1370 linfo->args [i].storage = LLVMArgVtypeInReg;
1371 for (j = 0; j < 2; ++j)
1372 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1376 linfo->args [i].storage = LLVMArgGSharedVt;
1379 cfg->exception_message = g_strdup ("ainfo->storage");
1380 cfg->disable_llvm = TRUE;
1390 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1392 if (cfg->compute_gc_maps) {
1395 /* On x86, the offsets are from the sp value before the start of the call sequence */
1397 t = &mono_defaults.int_class->byval_arg;
1398 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1403 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1407 MonoMethodSignature *sig;
1410 int sentinelpos = 0, sp_offset = 0;
1412 sig = call->signature;
1413 n = sig->param_count + sig->hasthis;
1414 sig_ret = mini_replace_type (sig->ret);
1416 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1418 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1419 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1421 if (cinfo->need_stack_align) {
1422 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1423 arg->dreg = X86_ESP;
1424 arg->sreg1 = X86_ESP;
1425 arg->inst_imm = cinfo->stack_align_amount;
1426 MONO_ADD_INS (cfg->cbb, arg);
1427 for (i = 0; i < cinfo->stack_align_amount; i += sizeof (mgreg_t)) {
1430 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1434 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1435 if (cinfo->ret.storage == ArgValuetypeInReg) {
1437 * Tell the JIT to use a more efficient calling convention: call using
1438 * OP_CALL, compute the result location after the call, and save the
1441 call->vret_in_reg = TRUE;
1443 NULLIFY_INS (call->vret_var);
1447 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1449 /* Handle the case where there are no implicit arguments */
1450 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1451 emit_sig_cookie (cfg, call, cinfo);
1453 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1456 /* Arguments are pushed in the reverse order */
1457 for (i = n - 1; i >= 0; i --) {
1458 ArgInfo *ainfo = cinfo->args + i;
1459 MonoType *orig_type, *t;
1462 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1463 /* Push the vret arg before the first argument */
1465 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1466 vtarg->type = STACK_MP;
1467 vtarg->sreg1 = call->vret_var->dreg;
1468 MONO_ADD_INS (cfg->cbb, vtarg);
1470 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1473 if (i >= sig->hasthis)
1474 t = sig->params [i - sig->hasthis];
1476 t = &mono_defaults.int_class->byval_arg;
1478 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1480 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1482 in = call->args [i];
1483 arg->cil_code = in->cil_code;
1484 arg->sreg1 = in->dreg;
1485 arg->type = in->type;
1487 g_assert (in->dreg != -1);
1489 if (ainfo->storage == ArgGSharedVt) {
1490 arg->opcode = OP_OUTARG_VT;
1491 arg->sreg1 = in->dreg;
1492 arg->klass = in->klass;
1493 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1494 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1496 MONO_ADD_INS (cfg->cbb, arg);
1497 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1501 g_assert (in->klass);
1503 if (t->type == MONO_TYPE_TYPEDBYREF) {
1504 size = sizeof (MonoTypedRef);
1505 align = sizeof (gpointer);
1508 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1512 arg->opcode = OP_OUTARG_VT;
1513 arg->sreg1 = in->dreg;
1514 arg->klass = in->klass;
1515 arg->backend.size = size;
1516 arg->inst_p0 = call;
1517 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1518 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1520 MONO_ADD_INS (cfg->cbb, arg);
1521 if (ainfo->storage != ArgValuetypeInReg) {
1523 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1529 switch (ainfo->storage) {
1531 arg->opcode = OP_X86_PUSH;
1533 if (t->type == MONO_TYPE_R4) {
1534 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1535 arg->opcode = OP_STORER4_MEMBASE_REG;
1536 arg->inst_destbasereg = X86_ESP;
1537 arg->inst_offset = 0;
1539 } else if (t->type == MONO_TYPE_R8) {
1540 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1541 arg->opcode = OP_STORER8_MEMBASE_REG;
1542 arg->inst_destbasereg = X86_ESP;
1543 arg->inst_offset = 0;
1545 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1547 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1553 arg->opcode = OP_MOVE;
1554 arg->dreg = ainfo->reg;
1558 g_assert_not_reached ();
1561 MONO_ADD_INS (cfg->cbb, arg);
1563 sp_offset += argsize;
1565 if (cfg->compute_gc_maps) {
1567 /* FIXME: The == STACK_OBJ check might be fragile ? */
1568 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1570 if (call->need_unbox_trampoline)
1571 /* The unbox trampoline transforms this into a managed pointer */
1572 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.int_class->this_arg);
1574 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.object_class->byval_arg);
1576 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1580 for (j = 0; j < argsize; j += 4)
1581 emit_gc_param_slot_def (cfg, sp_offset - j, NULL);
1586 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1587 /* Emit the signature cookie just before the implicit arguments */
1588 emit_sig_cookie (cfg, call, cinfo);
1590 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1594 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1597 if (cinfo->ret.storage == ArgValuetypeInReg) {
1600 else if (cinfo->ret.storage == ArgInIReg) {
1602 /* The return address is passed in a register */
1603 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1604 vtarg->sreg1 = call->inst.dreg;
1605 vtarg->dreg = mono_alloc_ireg (cfg);
1606 MONO_ADD_INS (cfg->cbb, vtarg);
1608 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1609 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1611 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1612 vtarg->type = STACK_MP;
1613 vtarg->sreg1 = call->vret_var->dreg;
1614 MONO_ADD_INS (cfg->cbb, vtarg);
1616 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1619 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1620 if (cinfo->ret.storage != ArgValuetypeInReg)
1621 cinfo->stack_usage -= 4;
1624 call->stack_usage = cinfo->stack_usage;
1625 call->stack_align_amount = cinfo->stack_align_amount;
1626 cfg->arch.param_area_size = MAX (cfg->arch.param_area_size, sp_offset);
1630 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1632 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1633 ArgInfo *ainfo = ins->inst_p1;
1635 int size = ins->backend.size;
1637 if (ainfo->storage == ArgValuetypeInReg) {
1638 int dreg = mono_alloc_ireg (cfg);
1641 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1644 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1647 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1651 g_assert_not_reached ();
1653 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1656 if (cfg->gsharedvt && mini_is_gsharedvt_klass (cfg, ins->klass)) {
1658 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1659 arg->sreg1 = src->dreg;
1660 MONO_ADD_INS (cfg->cbb, arg);
1661 } else if (size <= 4) {
1662 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1663 arg->sreg1 = src->dreg;
1665 MONO_ADD_INS (cfg->cbb, arg);
1666 } else if (size <= 20) {
1667 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1668 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1670 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1671 arg->inst_basereg = src->dreg;
1672 arg->inst_offset = 0;
1673 arg->inst_imm = size;
1675 MONO_ADD_INS (cfg->cbb, arg);
1681 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1683 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1686 if (ret->type == MONO_TYPE_R4) {
1687 if (COMPILE_LLVM (cfg))
1688 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1691 } else if (ret->type == MONO_TYPE_R8) {
1692 if (COMPILE_LLVM (cfg))
1693 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1696 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1697 if (COMPILE_LLVM (cfg))
1698 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1700 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1701 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1707 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1711 * Allow tracing to work with this interface (with an optional argument)
1714 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1718 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1719 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1721 /* if some args are passed in registers, we need to save them here */
1722 x86_push_reg (code, X86_EBP);
1724 if (cfg->compile_aot) {
1725 x86_push_imm (code, cfg->method);
1726 x86_mov_reg_imm (code, X86_EAX, func);
1727 x86_call_reg (code, X86_EAX);
1729 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1730 x86_push_imm (code, cfg->method);
1731 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1732 x86_call_code (code, 0);
1734 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1748 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1751 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1752 MonoMethod *method = cfg->method;
1753 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1755 switch (ret_type->type) {
1756 case MONO_TYPE_VOID:
1757 /* special case string .ctor icall */
1758 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1759 save_mode = SAVE_EAX;
1760 stack_usage = enable_arguments ? 8 : 4;
1762 save_mode = SAVE_NONE;
1766 save_mode = SAVE_EAX_EDX;
1767 stack_usage = enable_arguments ? 16 : 8;
1771 save_mode = SAVE_FP;
1772 stack_usage = enable_arguments ? 16 : 8;
1774 case MONO_TYPE_GENERICINST:
1775 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1776 save_mode = SAVE_EAX;
1777 stack_usage = enable_arguments ? 8 : 4;
1781 case MONO_TYPE_VALUETYPE:
1782 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1783 save_mode = SAVE_STRUCT;
1784 stack_usage = enable_arguments ? 4 : 0;
1787 save_mode = SAVE_EAX;
1788 stack_usage = enable_arguments ? 8 : 4;
1792 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1794 switch (save_mode) {
1796 x86_push_reg (code, X86_EDX);
1797 x86_push_reg (code, X86_EAX);
1798 if (enable_arguments) {
1799 x86_push_reg (code, X86_EDX);
1800 x86_push_reg (code, X86_EAX);
1805 x86_push_reg (code, X86_EAX);
1806 if (enable_arguments) {
1807 x86_push_reg (code, X86_EAX);
1812 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1813 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1814 if (enable_arguments) {
1815 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1816 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1821 if (enable_arguments) {
1822 x86_push_membase (code, X86_EBP, 8);
1831 if (cfg->compile_aot) {
1832 x86_push_imm (code, method);
1833 x86_mov_reg_imm (code, X86_EAX, func);
1834 x86_call_reg (code, X86_EAX);
1836 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1837 x86_push_imm (code, method);
1838 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1839 x86_call_code (code, 0);
1842 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1844 switch (save_mode) {
1846 x86_pop_reg (code, X86_EAX);
1847 x86_pop_reg (code, X86_EDX);
1850 x86_pop_reg (code, X86_EAX);
1853 x86_fld_membase (code, X86_ESP, 0, TRUE);
1854 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1861 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1866 #define EMIT_COND_BRANCH(ins,cond,sign) \
1867 if (ins->inst_true_bb->native_offset) { \
1868 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1870 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1871 if ((cfg->opt & MONO_OPT_BRANCH) && \
1872 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1873 x86_branch8 (code, cond, 0, sign); \
1875 x86_branch32 (code, cond, 0, sign); \
1879 * Emit an exception if condition is fail and
1880 * if possible do a directly branch to target
1882 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1884 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1885 if (tins == NULL) { \
1886 mono_add_patch_info (cfg, code - cfg->native_code, \
1887 MONO_PATCH_INFO_EXC, exc_name); \
1888 x86_branch32 (code, cond, 0, signed); \
1890 EMIT_COND_BRANCH (tins, cond, signed); \
1894 #define EMIT_FPCOMPARE(code) do { \
1895 x86_fcompp (code); \
1896 x86_fnstsw (code); \
1901 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1903 gboolean needs_paddings = TRUE;
1905 MonoJumpInfo *jinfo = NULL;
1907 if (cfg->abs_patches) {
1908 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1909 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1910 needs_paddings = FALSE;
1913 if (cfg->compile_aot)
1914 needs_paddings = FALSE;
1915 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1916 This is required for code patching to be safe on SMP machines.
1918 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1919 #ifndef __native_client_codegen__
1920 if (needs_paddings && pad_size)
1921 x86_padding (code, 4 - pad_size);
1924 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1925 x86_call_code (code, 0);
1930 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1933 * mono_peephole_pass_1:
1935 * Perform peephole opts which should/can be performed before local regalloc
1938 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1942 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1943 MonoInst *last_ins = ins->prev;
1945 switch (ins->opcode) {
1948 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1950 * X86_LEA is like ADD, but doesn't have the
1951 * sreg1==dreg restriction.
1953 ins->opcode = OP_X86_LEA_MEMBASE;
1954 ins->inst_basereg = ins->sreg1;
1955 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1956 ins->opcode = OP_X86_INC_REG;
1960 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1961 ins->opcode = OP_X86_LEA_MEMBASE;
1962 ins->inst_basereg = ins->sreg1;
1963 ins->inst_imm = -ins->inst_imm;
1964 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1965 ins->opcode = OP_X86_DEC_REG;
1967 case OP_COMPARE_IMM:
1968 case OP_ICOMPARE_IMM:
1969 /* OP_COMPARE_IMM (reg, 0)
1971 * OP_X86_TEST_NULL (reg)
1974 ins->opcode = OP_X86_TEST_NULL;
1976 case OP_X86_COMPARE_MEMBASE_IMM:
1978 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1979 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1981 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1982 * OP_COMPARE_IMM reg, imm
1984 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1986 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1987 ins->inst_basereg == last_ins->inst_destbasereg &&
1988 ins->inst_offset == last_ins->inst_offset) {
1989 ins->opcode = OP_COMPARE_IMM;
1990 ins->sreg1 = last_ins->sreg1;
1992 /* check if we can remove cmp reg,0 with test null */
1994 ins->opcode = OP_X86_TEST_NULL;
1998 case OP_X86_PUSH_MEMBASE:
1999 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
2000 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2001 ins->inst_basereg == last_ins->inst_destbasereg &&
2002 ins->inst_offset == last_ins->inst_offset) {
2003 ins->opcode = OP_X86_PUSH;
2004 ins->sreg1 = last_ins->sreg1;
2009 mono_peephole_ins (bb, ins);
2014 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2018 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2019 switch (ins->opcode) {
2021 /* reg = 0 -> XOR (reg, reg) */
2022 /* XOR sets cflags on x86, so we cant do it always */
2023 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2026 ins->opcode = OP_IXOR;
2027 ins->sreg1 = ins->dreg;
2028 ins->sreg2 = ins->dreg;
2031 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2032 * since it takes 3 bytes instead of 7.
2034 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2035 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2036 ins2->opcode = OP_STORE_MEMBASE_REG;
2037 ins2->sreg1 = ins->dreg;
2039 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2040 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2041 ins2->sreg1 = ins->dreg;
2043 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2044 /* Continue iteration */
2053 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2054 ins->opcode = OP_X86_INC_REG;
2058 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2059 ins->opcode = OP_X86_DEC_REG;
2063 mono_peephole_ins (bb, ins);
2068 * mono_arch_lowering_pass:
2070 * Converts complex opcodes into simpler ones so that each IR instruction
2071 * corresponds to one machine instruction.
2074 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2076 MonoInst *ins, *next;
2079 * FIXME: Need to add more instructions, but the current machine
2080 * description can't model some parts of the composite instructions like
2083 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2084 switch (ins->opcode) {
2087 case OP_IDIV_UN_IMM:
2088 case OP_IREM_UN_IMM:
2090 * Keep the cases where we could generated optimized code, otherwise convert
2091 * to the non-imm variant.
2093 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2095 mono_decompose_op_imm (cfg, bb, ins);
2102 bb->max_vreg = cfg->next_vreg;
2106 branch_cc_table [] = {
2107 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2108 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2109 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2112 /* Maps CMP_... constants to X86_CC_... constants */
2115 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2116 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2120 cc_signed_table [] = {
2121 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2122 FALSE, FALSE, FALSE, FALSE
2125 static unsigned char*
2126 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2128 #define XMM_TEMP_REG 0
2129 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2130 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2131 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2132 /* optimize by assigning a local var for this use so we avoid
2133 * the stack manipulations */
2134 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2135 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2136 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2137 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2138 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2140 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2142 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2145 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2146 x86_fnstcw_membase(code, X86_ESP, 0);
2147 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2148 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2149 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2150 x86_fldcw_membase (code, X86_ESP, 2);
2152 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2153 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2154 x86_pop_reg (code, dreg);
2155 /* FIXME: need the high register
2156 * x86_pop_reg (code, dreg_high);
2159 x86_push_reg (code, X86_EAX); // SP = SP - 4
2160 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2161 x86_pop_reg (code, dreg);
2163 x86_fldcw_membase (code, X86_ESP, 0);
2164 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2167 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2169 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2173 static unsigned char*
2174 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2176 int sreg = tree->sreg1;
2177 int need_touch = FALSE;
2179 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2188 * If requested stack size is larger than one page,
2189 * perform stack-touch operation
2192 * Generate stack probe code.
2193 * Under Windows, it is necessary to allocate one page at a time,
2194 * "touching" stack after each successful sub-allocation. This is
2195 * because of the way stack growth is implemented - there is a
2196 * guard page before the lowest stack page that is currently commited.
2197 * Stack normally grows sequentially so OS traps access to the
2198 * guard page and commits more pages when needed.
2200 x86_test_reg_imm (code, sreg, ~0xFFF);
2201 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2203 br[2] = code; /* loop */
2204 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2205 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2208 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2209 * that follows only initializes the last part of the area.
2211 /* Same as the init code below with size==0x1000 */
2212 if (tree->flags & MONO_INST_INIT) {
2213 x86_push_reg (code, X86_EAX);
2214 x86_push_reg (code, X86_ECX);
2215 x86_push_reg (code, X86_EDI);
2216 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2217 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2218 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2220 x86_prefix (code, X86_REP_PREFIX);
2222 x86_pop_reg (code, X86_EDI);
2223 x86_pop_reg (code, X86_ECX);
2224 x86_pop_reg (code, X86_EAX);
2227 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2228 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2229 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2230 x86_patch (br[3], br[2]);
2231 x86_test_reg_reg (code, sreg, sreg);
2232 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2233 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2235 br[1] = code; x86_jump8 (code, 0);
2237 x86_patch (br[0], code);
2238 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2239 x86_patch (br[1], code);
2240 x86_patch (br[4], code);
2243 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2245 if (tree->flags & MONO_INST_INIT) {
2247 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2248 x86_push_reg (code, X86_EAX);
2251 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2252 x86_push_reg (code, X86_ECX);
2255 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2256 x86_push_reg (code, X86_EDI);
2260 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2261 if (sreg != X86_ECX)
2262 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2263 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2265 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2267 x86_prefix (code, X86_REP_PREFIX);
2270 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2271 x86_pop_reg (code, X86_EDI);
2272 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2273 x86_pop_reg (code, X86_ECX);
2274 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2275 x86_pop_reg (code, X86_EAX);
2282 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2284 /* Move return value to the target register */
2285 switch (ins->opcode) {
2288 case OP_CALL_MEMBASE:
2289 if (ins->dreg != X86_EAX)
2290 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2300 static int tls_gs_offset;
2304 mono_x86_have_tls_get (void)
2307 static gboolean have_tls_get = FALSE;
2308 static gboolean inited = FALSE;
2312 return have_tls_get;
2314 ins = (guint32*)pthread_getspecific;
2316 * We're looking for these two instructions:
2318 * mov 0x4(%esp),%eax
2319 * mov %gs:[offset](,%eax,4),%eax
2321 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2322 tls_gs_offset = ins [2];
2326 return have_tls_get;
2327 #elif defined(TARGET_ANDROID)
2335 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2337 #if defined(__APPLE__)
2338 x86_prefix (code, X86_GS_PREFIX);
2339 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2340 #elif defined(TARGET_WIN32)
2341 g_assert_not_reached ();
2343 x86_prefix (code, X86_GS_PREFIX);
2344 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2350 * mono_x86_emit_tls_get:
2351 * @code: buffer to store code to
2352 * @dreg: hard register where to place the result
2353 * @tls_offset: offset info
2355 * mono_x86_emit_tls_get emits in @code the native code that puts in
2356 * the dreg register the item in the thread local storage identified
2359 * Returns: a pointer to the end of the stored code
2362 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2364 #if defined(__APPLE__)
2365 x86_prefix (code, X86_GS_PREFIX);
2366 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2367 #elif defined(TARGET_WIN32)
2369 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2370 * Journal and/or a disassembly of the TlsGet () function.
2372 g_assert (tls_offset < 64);
2373 x86_prefix (code, X86_FS_PREFIX);
2374 x86_mov_reg_mem (code, dreg, 0x18, 4);
2375 /* Dunno what this does but TlsGetValue () contains it */
2376 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2377 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2379 if (optimize_for_xen) {
2380 x86_prefix (code, X86_GS_PREFIX);
2381 x86_mov_reg_mem (code, dreg, 0, 4);
2382 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2384 x86_prefix (code, X86_GS_PREFIX);
2385 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2392 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2394 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2395 #if defined(__APPLE__) || defined(__linux__)
2396 if (dreg != offset_reg)
2397 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2398 x86_prefix (code, X86_GS_PREFIX);
2399 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2401 g_assert_not_reached ();
2407 mono_x86_emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2409 return emit_tls_get_reg (code, dreg, offset_reg);
2413 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2415 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2417 g_assert_not_reached ();
2418 #elif defined(__APPLE__) || defined(__linux__)
2419 x86_prefix (code, X86_GS_PREFIX);
2420 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2422 g_assert_not_reached ();
2428 * mono_arch_translate_tls_offset:
2430 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2433 mono_arch_translate_tls_offset (int offset)
2436 return tls_gs_offset + (offset * 4);
2445 * Emit code to initialize an LMF structure at LMF_OFFSET.
2448 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2450 /* save all caller saved regs */
2451 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2452 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx));
2453 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2454 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi));
2455 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2456 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi));
2457 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2459 /* save the current IP */
2460 if (cfg->compile_aot) {
2461 /* This pushes the current ip */
2462 x86_call_imm (code, 0);
2463 x86_pop_reg (code, X86_EAX);
2465 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2466 x86_mov_reg_imm (code, X86_EAX, 0);
2468 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2470 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2471 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2472 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2473 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2474 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2475 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2476 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2477 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2478 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2486 * Emit code to push an LMF structure on the LMF stack.
2489 emit_push_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
2491 /* get the address of lmf for the current thread */
2493 * This is performance critical so we try to use some tricks to make
2496 gboolean have_fastpath = FALSE;
2499 if (jit_tls_offset != -1) {
2500 code = mono_x86_emit_tls_get (code, X86_EAX, jit_tls_offset);
2501 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
2502 have_fastpath = TRUE;
2505 if (!cfg->compile_aot && lmf_addr_tls_offset != -1) {
2506 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
2507 have_fastpath = TRUE;
2510 if (!have_fastpath) {
2511 if (cfg->compile_aot)
2512 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
2513 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
2517 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), X86_EAX, sizeof (mgreg_t));
2518 /* save previous_lmf */
2519 x86_mov_reg_membase (code, X86_ECX, X86_EAX, 0, sizeof (mgreg_t));
2520 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), X86_ECX, sizeof (mgreg_t));
2522 x86_lea_membase (code, X86_ECX, cfg->frame_reg, lmf_offset);
2523 x86_mov_membase_reg (code, X86_EAX, 0, X86_ECX, sizeof (mgreg_t));
2531 * Emit code to pop an LMF structure from the LMF stack.
2532 * Preserves the return registers.
2535 emit_pop_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
2537 MonoMethodSignature *sig = mono_method_signature (cfg->method);
2540 /* Find a spare register */
2541 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
2544 prev_lmf_reg = X86_EDI;
2545 cfg->used_int_regs |= (1 << X86_EDI);
2548 prev_lmf_reg = X86_EDX;
2552 /* reg = previous_lmf */
2553 x86_mov_reg_membase (code, prev_lmf_reg, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
2556 x86_mov_reg_membase (code, X86_ECX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
2558 /* *(lmf) = previous_lmf */
2559 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
2564 #define REAL_PRINT_REG(text,reg) \
2565 mono_assert (reg >= 0); \
2566 x86_push_reg (code, X86_EAX); \
2567 x86_push_reg (code, X86_EDX); \
2568 x86_push_reg (code, X86_ECX); \
2569 x86_push_reg (code, reg); \
2570 x86_push_imm (code, reg); \
2571 x86_push_imm (code, text " %d %p\n"); \
2572 x86_mov_reg_imm (code, X86_EAX, printf); \
2573 x86_call_reg (code, X86_EAX); \
2574 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2575 x86_pop_reg (code, X86_ECX); \
2576 x86_pop_reg (code, X86_EDX); \
2577 x86_pop_reg (code, X86_EAX);
2579 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2580 #ifdef __native__client_codegen__
2581 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2584 /* benchmark and set based on cpu */
2585 #define LOOP_ALIGNMENT 8
2586 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2590 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2595 guint8 *code = cfg->native_code + cfg->code_len;
2598 if (cfg->opt & MONO_OPT_LOOP) {
2599 int pad, align = LOOP_ALIGNMENT;
2600 /* set alignment depending on cpu */
2601 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2603 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2604 x86_padding (code, pad);
2605 cfg->code_len += pad;
2606 bb->native_offset = cfg->code_len;
2609 #ifdef __native_client_codegen__
2611 /* For Native Client, all indirect call/jump targets must be */
2612 /* 32-byte aligned. Exception handler blocks are jumped to */
2613 /* indirectly as well. */
2614 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2615 (bb->flags & BB_EXCEPTION_HANDLER);
2617 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2618 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2619 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2620 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2621 cfg->code_len += pad;
2622 bb->native_offset = cfg->code_len;
2625 #endif /* __native_client_codegen__ */
2626 if (cfg->verbose_level > 2)
2627 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2629 cpos = bb->max_offset;
2631 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2632 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2633 g_assert (!cfg->compile_aot);
2636 cov->data [bb->dfn].cil_code = bb->cil_code;
2637 /* this is not thread save, but good enough */
2638 x86_inc_mem (code, &cov->data [bb->dfn].count);
2641 offset = code - cfg->native_code;
2643 mono_debug_open_block (cfg, bb, offset);
2645 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2646 x86_breakpoint (code);
2648 MONO_BB_FOR_EACH_INS (bb, ins) {
2649 offset = code - cfg->native_code;
2651 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2653 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2655 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2656 cfg->code_size *= 2;
2657 cfg->native_code = mono_realloc_native_code(cfg);
2658 code = cfg->native_code + offset;
2659 cfg->stat_code_reallocs++;
2662 if (cfg->debug_info)
2663 mono_debug_record_line_number (cfg, ins, offset);
2665 switch (ins->opcode) {
2667 x86_mul_reg (code, ins->sreg2, TRUE);
2670 x86_mul_reg (code, ins->sreg2, FALSE);
2672 case OP_X86_SETEQ_MEMBASE:
2673 case OP_X86_SETNE_MEMBASE:
2674 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2675 ins->inst_basereg, ins->inst_offset, TRUE);
2677 case OP_STOREI1_MEMBASE_IMM:
2678 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2680 case OP_STOREI2_MEMBASE_IMM:
2681 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2683 case OP_STORE_MEMBASE_IMM:
2684 case OP_STOREI4_MEMBASE_IMM:
2685 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2687 case OP_STOREI1_MEMBASE_REG:
2688 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2690 case OP_STOREI2_MEMBASE_REG:
2691 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2693 case OP_STORE_MEMBASE_REG:
2694 case OP_STOREI4_MEMBASE_REG:
2695 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2697 case OP_STORE_MEM_IMM:
2698 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2701 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2705 /* These are created by the cprop pass so they use inst_imm as the source */
2706 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2709 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2712 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2714 case OP_LOAD_MEMBASE:
2715 case OP_LOADI4_MEMBASE:
2716 case OP_LOADU4_MEMBASE:
2717 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2719 case OP_LOADU1_MEMBASE:
2720 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2722 case OP_LOADI1_MEMBASE:
2723 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2725 case OP_LOADU2_MEMBASE:
2726 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2728 case OP_LOADI2_MEMBASE:
2729 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2731 case OP_ICONV_TO_I1:
2733 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2735 case OP_ICONV_TO_I2:
2737 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2739 case OP_ICONV_TO_U1:
2740 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2742 case OP_ICONV_TO_U2:
2743 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2747 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2749 case OP_COMPARE_IMM:
2750 case OP_ICOMPARE_IMM:
2751 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2753 case OP_X86_COMPARE_MEMBASE_REG:
2754 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2756 case OP_X86_COMPARE_MEMBASE_IMM:
2757 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2759 case OP_X86_COMPARE_MEMBASE8_IMM:
2760 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2762 case OP_X86_COMPARE_REG_MEMBASE:
2763 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2765 case OP_X86_COMPARE_MEM_IMM:
2766 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2768 case OP_X86_TEST_NULL:
2769 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2771 case OP_X86_ADD_MEMBASE_IMM:
2772 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2774 case OP_X86_ADD_REG_MEMBASE:
2775 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2777 case OP_X86_SUB_MEMBASE_IMM:
2778 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2780 case OP_X86_SUB_REG_MEMBASE:
2781 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2783 case OP_X86_AND_MEMBASE_IMM:
2784 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2786 case OP_X86_OR_MEMBASE_IMM:
2787 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2789 case OP_X86_XOR_MEMBASE_IMM:
2790 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2792 case OP_X86_ADD_MEMBASE_REG:
2793 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2795 case OP_X86_SUB_MEMBASE_REG:
2796 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2798 case OP_X86_AND_MEMBASE_REG:
2799 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2801 case OP_X86_OR_MEMBASE_REG:
2802 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2804 case OP_X86_XOR_MEMBASE_REG:
2805 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2807 case OP_X86_INC_MEMBASE:
2808 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2810 case OP_X86_INC_REG:
2811 x86_inc_reg (code, ins->dreg);
2813 case OP_X86_DEC_MEMBASE:
2814 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2816 case OP_X86_DEC_REG:
2817 x86_dec_reg (code, ins->dreg);
2819 case OP_X86_MUL_REG_MEMBASE:
2820 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2822 case OP_X86_AND_REG_MEMBASE:
2823 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2825 case OP_X86_OR_REG_MEMBASE:
2826 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2828 case OP_X86_XOR_REG_MEMBASE:
2829 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2832 x86_breakpoint (code);
2834 case OP_RELAXED_NOP:
2835 x86_prefix (code, X86_REP_PREFIX);
2843 case OP_DUMMY_STORE:
2844 case OP_NOT_REACHED:
2847 case OP_SEQ_POINT: {
2850 if (cfg->compile_aot)
2854 * Read from the single stepping trigger page. This will cause a
2855 * SIGSEGV when single stepping is enabled.
2856 * We do this _before_ the breakpoint, so single stepping after
2857 * a breakpoint is hit will step to the next IL offset.
2859 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2860 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2862 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2865 * A placeholder for a possible breakpoint inserted by
2866 * mono_arch_set_breakpoint ().
2868 for (i = 0; i < 6; ++i)
2871 * Add an additional nop so skipping the bp doesn't cause the ip to point
2872 * to another IL offset.
2880 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2884 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2889 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2893 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2898 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2902 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2907 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2911 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2914 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2918 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2922 #if defined( __native_client_codegen__ )
2923 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2924 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2927 * The code is the same for div/rem, the allocator will allocate dreg
2928 * to RAX/RDX as appropriate.
2930 if (ins->sreg2 == X86_EDX) {
2931 /* cdq clobbers this */
2932 x86_push_reg (code, ins->sreg2);
2934 x86_div_membase (code, X86_ESP, 0, TRUE);
2935 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2938 x86_div_reg (code, ins->sreg2, TRUE);
2943 #if defined( __native_client_codegen__ )
2944 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2945 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2947 if (ins->sreg2 == X86_EDX) {
2948 x86_push_reg (code, ins->sreg2);
2949 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2950 x86_div_membase (code, X86_ESP, 0, FALSE);
2951 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2953 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2954 x86_div_reg (code, ins->sreg2, FALSE);
2958 #if defined( __native_client_codegen__ )
2959 if (ins->inst_imm == 0) {
2960 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2961 x86_jump32 (code, 0);
2965 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2967 x86_div_reg (code, ins->sreg2, TRUE);
2970 int power = mono_is_power_of_two (ins->inst_imm);
2972 g_assert (ins->sreg1 == X86_EAX);
2973 g_assert (ins->dreg == X86_EAX);
2974 g_assert (power >= 0);
2977 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2979 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2981 * If the divident is >= 0, this does not nothing. If it is positive, it
2982 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2984 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2985 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2986 } else if (power == 0) {
2987 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2989 /* Based on gcc code */
2991 /* Add compensation for negative dividents */
2993 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2994 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2995 /* Compute remainder */
2996 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2997 /* Remove compensation */
2998 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
3003 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3007 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3010 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3014 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3017 g_assert (ins->sreg2 == X86_ECX);
3018 x86_shift_reg (code, X86_SHL, ins->dreg);
3021 g_assert (ins->sreg2 == X86_ECX);
3022 x86_shift_reg (code, X86_SAR, ins->dreg);
3026 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3029 case OP_ISHR_UN_IMM:
3030 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3033 g_assert (ins->sreg2 == X86_ECX);
3034 x86_shift_reg (code, X86_SHR, ins->dreg);
3038 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3041 guint8 *jump_to_end;
3043 /* handle shifts below 32 bits */
3044 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
3045 x86_shift_reg (code, X86_SHL, ins->sreg1);
3047 x86_test_reg_imm (code, X86_ECX, 32);
3048 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3050 /* handle shift over 32 bit */
3051 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3052 x86_clear_reg (code, ins->sreg1);
3054 x86_patch (jump_to_end, code);
3058 guint8 *jump_to_end;
3060 /* handle shifts below 32 bits */
3061 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3062 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
3064 x86_test_reg_imm (code, X86_ECX, 32);
3065 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3067 /* handle shifts over 31 bits */
3068 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3069 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
3071 x86_patch (jump_to_end, code);
3075 guint8 *jump_to_end;
3077 /* handle shifts below 32 bits */
3078 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3079 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
3081 x86_test_reg_imm (code, X86_ECX, 32);
3082 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3084 /* handle shifts over 31 bits */
3085 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3086 x86_clear_reg (code, ins->backend.reg3);
3088 x86_patch (jump_to_end, code);
3092 if (ins->inst_imm >= 32) {
3093 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3094 x86_clear_reg (code, ins->sreg1);
3095 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
3097 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
3098 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
3102 if (ins->inst_imm >= 32) {
3103 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3104 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
3105 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
3107 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3108 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3111 case OP_LSHR_UN_IMM:
3112 if (ins->inst_imm >= 32) {
3113 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3114 x86_clear_reg (code, ins->backend.reg3);
3115 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3117 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3118 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3122 x86_not_reg (code, ins->sreg1);
3125 x86_neg_reg (code, ins->sreg1);
3129 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3133 switch (ins->inst_imm) {
3137 if (ins->dreg != ins->sreg1)
3138 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3139 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3142 /* LEA r1, [r2 + r2*2] */
3143 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3146 /* LEA r1, [r2 + r2*4] */
3147 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3150 /* LEA r1, [r2 + r2*2] */
3152 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3153 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3156 /* LEA r1, [r2 + r2*8] */
3157 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3160 /* LEA r1, [r2 + r2*4] */
3162 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3163 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3166 /* LEA r1, [r2 + r2*2] */
3168 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3169 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3172 /* LEA r1, [r2 + r2*4] */
3173 /* LEA r1, [r1 + r1*4] */
3174 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3175 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3178 /* LEA r1, [r2 + r2*4] */
3180 /* LEA r1, [r1 + r1*4] */
3181 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3182 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3183 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3186 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3191 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3192 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3194 case OP_IMUL_OVF_UN: {
3195 /* the mul operation and the exception check should most likely be split */
3196 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3197 /*g_assert (ins->sreg2 == X86_EAX);
3198 g_assert (ins->dreg == X86_EAX);*/
3199 if (ins->sreg2 == X86_EAX) {
3200 non_eax_reg = ins->sreg1;
3201 } else if (ins->sreg1 == X86_EAX) {
3202 non_eax_reg = ins->sreg2;
3204 /* no need to save since we're going to store to it anyway */
3205 if (ins->dreg != X86_EAX) {
3207 x86_push_reg (code, X86_EAX);
3209 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3210 non_eax_reg = ins->sreg2;
3212 if (ins->dreg == X86_EDX) {
3215 x86_push_reg (code, X86_EAX);
3217 } else if (ins->dreg != X86_EAX) {
3219 x86_push_reg (code, X86_EDX);
3221 x86_mul_reg (code, non_eax_reg, FALSE);
3222 /* save before the check since pop and mov don't change the flags */
3223 if (ins->dreg != X86_EAX)
3224 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3226 x86_pop_reg (code, X86_EDX);
3228 x86_pop_reg (code, X86_EAX);
3229 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3233 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3236 g_assert_not_reached ();
3237 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3238 x86_mov_reg_imm (code, ins->dreg, 0);
3241 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3242 x86_mov_reg_imm (code, ins->dreg, 0);
3244 case OP_LOAD_GOTADDR:
3245 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3246 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3249 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3250 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3252 case OP_X86_PUSH_GOT_ENTRY:
3253 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3254 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3257 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3260 MonoCallInst *call = (MonoCallInst*)ins;
3263 ins->flags |= MONO_INST_GC_CALLSITE;
3264 ins->backend.pc_offset = code - cfg->native_code;
3266 /* FIXME: no tracing support... */
3267 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3268 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3269 /* reset offset to make max_len work */
3270 offset = code - cfg->native_code;
3272 g_assert (!cfg->method->save_lmf);
3274 /* restore callee saved registers */
3275 for (i = 0; i < X86_NREG; ++i)
3276 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3278 if (cfg->used_int_regs & (1 << X86_ESI)) {
3279 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3282 if (cfg->used_int_regs & (1 << X86_EDI)) {
3283 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3286 if (cfg->used_int_regs & (1 << X86_EBX)) {
3287 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3291 /* Copy arguments on the stack to our argument area */
3292 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3293 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3294 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3297 /* restore ESP/EBP */
3299 offset = code - cfg->native_code;
3300 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3301 x86_jump32 (code, 0);
3303 ins->flags |= MONO_INST_GC_CALLSITE;
3304 cfg->disable_aot = TRUE;
3308 /* ensure ins->sreg1 is not NULL
3309 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3310 * cmp DWORD PTR [eax], 0
3312 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3315 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3316 x86_push_reg (code, hreg);
3317 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3318 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3319 x86_pop_reg (code, hreg);
3328 call = (MonoCallInst*)ins;
3329 if (ins->flags & MONO_INST_HAS_METHOD)
3330 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3332 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3333 ins->flags |= MONO_INST_GC_CALLSITE;
3334 ins->backend.pc_offset = code - cfg->native_code;
3335 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3336 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
3337 * bytes to pop, we want to use pops. GCC does this (note it won't happen
3338 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
3339 * smart enough to do that optimization yet
3341 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
3342 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
3343 * (most likely from locality benefits). People with other processors should
3344 * check on theirs to see what happens.
3346 if (call->stack_usage == 4) {
3347 /* we want to use registers that won't get used soon, so use
3348 * ecx, as eax will get allocated first. edx is used by long calls,
3349 * so we can't use that.
3352 x86_pop_reg (code, X86_ECX);
3354 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3357 code = emit_move_return_value (cfg, ins, code);
3363 case OP_VOIDCALL_REG:
3365 call = (MonoCallInst*)ins;
3366 x86_call_reg (code, ins->sreg1);
3367 ins->flags |= MONO_INST_GC_CALLSITE;
3368 ins->backend.pc_offset = code - cfg->native_code;
3369 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3370 if (call->stack_usage == 4)
3371 x86_pop_reg (code, X86_ECX);
3373 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3375 code = emit_move_return_value (cfg, ins, code);
3377 case OP_FCALL_MEMBASE:
3378 case OP_LCALL_MEMBASE:
3379 case OP_VCALL_MEMBASE:
3380 case OP_VCALL2_MEMBASE:
3381 case OP_VOIDCALL_MEMBASE:
3382 case OP_CALL_MEMBASE:
3383 call = (MonoCallInst*)ins;
3385 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3386 ins->flags |= MONO_INST_GC_CALLSITE;
3387 ins->backend.pc_offset = code - cfg->native_code;
3388 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3389 if (call->stack_usage == 4)
3390 x86_pop_reg (code, X86_ECX);
3392 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3394 code = emit_move_return_value (cfg, ins, code);
3397 x86_push_reg (code, ins->sreg1);
3399 case OP_X86_PUSH_IMM:
3400 x86_push_imm (code, ins->inst_imm);
3402 case OP_X86_PUSH_MEMBASE:
3403 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
3405 case OP_X86_PUSH_OBJ:
3406 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
3407 x86_push_reg (code, X86_EDI);
3408 x86_push_reg (code, X86_ESI);
3409 x86_push_reg (code, X86_ECX);
3410 if (ins->inst_offset)
3411 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
3413 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
3414 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
3415 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
3417 x86_prefix (code, X86_REP_PREFIX);
3419 x86_pop_reg (code, X86_ECX);
3420 x86_pop_reg (code, X86_ESI);
3421 x86_pop_reg (code, X86_EDI);
3424 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3426 case OP_X86_LEA_MEMBASE:
3427 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3430 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3433 /* keep alignment */
3434 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3435 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3436 code = mono_emit_stack_alloc (code, ins);
3437 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3439 case OP_LOCALLOC_IMM: {
3440 guint32 size = ins->inst_imm;
3441 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3443 if (ins->flags & MONO_INST_INIT) {
3444 /* FIXME: Optimize this */
3445 x86_mov_reg_imm (code, ins->dreg, size);
3446 ins->sreg1 = ins->dreg;
3448 code = mono_emit_stack_alloc (code, ins);
3449 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3451 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3452 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3457 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3458 x86_push_reg (code, ins->sreg1);
3459 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3460 (gpointer)"mono_arch_throw_exception");
3461 ins->flags |= MONO_INST_GC_CALLSITE;
3462 ins->backend.pc_offset = code - cfg->native_code;
3466 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3467 x86_push_reg (code, ins->sreg1);
3468 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3469 (gpointer)"mono_arch_rethrow_exception");
3470 ins->flags |= MONO_INST_GC_CALLSITE;
3471 ins->backend.pc_offset = code - cfg->native_code;
3474 case OP_CALL_HANDLER:
3475 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3476 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3477 x86_call_imm (code, 0);
3478 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3479 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3481 case OP_START_HANDLER: {
3482 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3483 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3486 case OP_ENDFINALLY: {
3487 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3488 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3492 case OP_ENDFILTER: {
3493 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3494 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3495 /* The local allocator will put the result into EAX */
3501 ins->inst_c0 = code - cfg->native_code;
3504 if (ins->inst_target_bb->native_offset) {
3505 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3507 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3508 if ((cfg->opt & MONO_OPT_BRANCH) &&
3509 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3510 x86_jump8 (code, 0);
3512 x86_jump32 (code, 0);
3516 x86_jump_reg (code, ins->sreg1);
3535 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3536 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3538 case OP_COND_EXC_EQ:
3539 case OP_COND_EXC_NE_UN:
3540 case OP_COND_EXC_LT:
3541 case OP_COND_EXC_LT_UN:
3542 case OP_COND_EXC_GT:
3543 case OP_COND_EXC_GT_UN:
3544 case OP_COND_EXC_GE:
3545 case OP_COND_EXC_GE_UN:
3546 case OP_COND_EXC_LE:
3547 case OP_COND_EXC_LE_UN:
3548 case OP_COND_EXC_IEQ:
3549 case OP_COND_EXC_INE_UN:
3550 case OP_COND_EXC_ILT:
3551 case OP_COND_EXC_ILT_UN:
3552 case OP_COND_EXC_IGT:
3553 case OP_COND_EXC_IGT_UN:
3554 case OP_COND_EXC_IGE:
3555 case OP_COND_EXC_IGE_UN:
3556 case OP_COND_EXC_ILE:
3557 case OP_COND_EXC_ILE_UN:
3558 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3560 case OP_COND_EXC_OV:
3561 case OP_COND_EXC_NO:
3563 case OP_COND_EXC_NC:
3564 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3566 case OP_COND_EXC_IOV:
3567 case OP_COND_EXC_INO:
3568 case OP_COND_EXC_IC:
3569 case OP_COND_EXC_INC:
3570 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3582 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3590 case OP_CMOV_INE_UN:
3591 case OP_CMOV_IGE_UN:
3592 case OP_CMOV_IGT_UN:
3593 case OP_CMOV_ILE_UN:
3594 case OP_CMOV_ILT_UN:
3595 g_assert (ins->dreg == ins->sreg1);
3596 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3599 /* floating point opcodes */
3601 double d = *(double *)ins->inst_p0;
3603 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3605 } else if (d == 1.0) {
3608 if (cfg->compile_aot) {
3609 guint32 *val = (guint32*)&d;
3610 x86_push_imm (code, val [1]);
3611 x86_push_imm (code, val [0]);
3612 x86_fld_membase (code, X86_ESP, 0, TRUE);
3613 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3616 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3617 x86_fld (code, NULL, TRUE);
3623 float f = *(float *)ins->inst_p0;
3625 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3627 } else if (f == 1.0) {
3630 if (cfg->compile_aot) {
3631 guint32 val = *(guint32*)&f;
3632 x86_push_imm (code, val);
3633 x86_fld_membase (code, X86_ESP, 0, FALSE);
3634 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3637 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3638 x86_fld (code, NULL, FALSE);
3643 case OP_STORER8_MEMBASE_REG:
3644 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3646 case OP_LOADR8_MEMBASE:
3647 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3649 case OP_STORER4_MEMBASE_REG:
3650 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3652 case OP_LOADR4_MEMBASE:
3653 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3655 case OP_ICONV_TO_R4:
3656 x86_push_reg (code, ins->sreg1);
3657 x86_fild_membase (code, X86_ESP, 0, FALSE);
3658 /* Change precision */
3659 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3660 x86_fld_membase (code, X86_ESP, 0, FALSE);
3661 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3663 case OP_ICONV_TO_R8:
3664 x86_push_reg (code, ins->sreg1);
3665 x86_fild_membase (code, X86_ESP, 0, FALSE);
3666 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3668 case OP_ICONV_TO_R_UN:
3669 x86_push_imm (code, 0);
3670 x86_push_reg (code, ins->sreg1);
3671 x86_fild_membase (code, X86_ESP, 0, TRUE);
3672 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3674 case OP_X86_FP_LOAD_I8:
3675 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3677 case OP_X86_FP_LOAD_I4:
3678 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3680 case OP_FCONV_TO_R4:
3681 /* Change precision */
3682 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3683 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3684 x86_fld_membase (code, X86_ESP, 0, FALSE);
3685 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3687 case OP_FCONV_TO_I1:
3688 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3690 case OP_FCONV_TO_U1:
3691 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3693 case OP_FCONV_TO_I2:
3694 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3696 case OP_FCONV_TO_U2:
3697 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3699 case OP_FCONV_TO_I4:
3701 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3703 case OP_FCONV_TO_I8:
3704 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3705 x86_fnstcw_membase(code, X86_ESP, 0);
3706 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3707 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3708 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3709 x86_fldcw_membase (code, X86_ESP, 2);
3710 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3711 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3712 x86_pop_reg (code, ins->dreg);
3713 x86_pop_reg (code, ins->backend.reg3);
3714 x86_fldcw_membase (code, X86_ESP, 0);
3715 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3717 case OP_LCONV_TO_R8_2:
3718 x86_push_reg (code, ins->sreg2);
3719 x86_push_reg (code, ins->sreg1);
3720 x86_fild_membase (code, X86_ESP, 0, TRUE);
3721 /* Change precision */
3722 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3723 x86_fld_membase (code, X86_ESP, 0, TRUE);
3724 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3726 case OP_LCONV_TO_R4_2:
3727 x86_push_reg (code, ins->sreg2);
3728 x86_push_reg (code, ins->sreg1);
3729 x86_fild_membase (code, X86_ESP, 0, TRUE);
3730 /* Change precision */
3731 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3732 x86_fld_membase (code, X86_ESP, 0, FALSE);
3733 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3735 case OP_LCONV_TO_R_UN_2: {
3736 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3739 /* load 64bit integer to FP stack */
3740 x86_push_reg (code, ins->sreg2);
3741 x86_push_reg (code, ins->sreg1);
3742 x86_fild_membase (code, X86_ESP, 0, TRUE);
3744 /* test if lreg is negative */
3745 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3746 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3748 /* add correction constant mn */
3749 if (cfg->compile_aot) {
3750 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3751 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3752 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3753 x86_fld80_membase (code, X86_ESP, 2);
3754 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3756 x86_fld80_mem (code, mn);
3758 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3760 x86_patch (br, code);
3762 /* Change precision */
3763 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3764 x86_fld_membase (code, X86_ESP, 0, TRUE);
3766 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3770 case OP_LCONV_TO_OVF_I:
3771 case OP_LCONV_TO_OVF_I4_2: {
3772 guint8 *br [3], *label [1];
3776 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3778 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3780 /* If the low word top bit is set, see if we are negative */
3781 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3782 /* We are not negative (no top bit set, check for our top word to be zero */
3783 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3784 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3787 /* throw exception */
3788 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3790 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3791 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3792 x86_jump8 (code, 0);
3794 x86_jump32 (code, 0);
3796 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3797 x86_jump32 (code, 0);
3801 x86_patch (br [0], code);
3802 /* our top bit is set, check that top word is 0xfffffff */
3803 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3805 x86_patch (br [1], code);
3806 /* nope, emit exception */
3807 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3808 x86_patch (br [2], label [0]);
3810 if (ins->dreg != ins->sreg1)
3811 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3815 /* Not needed on the fp stack */
3818 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3821 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3824 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3827 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3835 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3840 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3847 * it really doesn't make sense to inline all this code,
3848 * it's here just to show that things may not be as simple
3851 guchar *check_pos, *end_tan, *pop_jump;
3852 x86_push_reg (code, X86_EAX);
3855 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3857 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3858 x86_fstp (code, 0); /* pop the 1.0 */
3860 x86_jump8 (code, 0);
3862 x86_fp_op (code, X86_FADD, 0);
3866 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3868 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3871 x86_patch (pop_jump, code);
3872 x86_fstp (code, 0); /* pop the 1.0 */
3873 x86_patch (check_pos, code);
3874 x86_patch (end_tan, code);
3876 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3877 x86_pop_reg (code, X86_EAX);
3884 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3893 g_assert (cfg->opt & MONO_OPT_CMOV);
3894 g_assert (ins->dreg == ins->sreg1);
3895 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3896 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3899 g_assert (cfg->opt & MONO_OPT_CMOV);
3900 g_assert (ins->dreg == ins->sreg1);
3901 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3902 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3905 g_assert (cfg->opt & MONO_OPT_CMOV);
3906 g_assert (ins->dreg == ins->sreg1);
3907 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3908 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3911 g_assert (cfg->opt & MONO_OPT_CMOV);
3912 g_assert (ins->dreg == ins->sreg1);
3913 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3914 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3920 x86_fxch (code, ins->inst_imm);
3925 x86_push_reg (code, X86_EAX);
3926 /* we need to exchange ST(0) with ST(1) */
3929 /* this requires a loop, because fprem somtimes
3930 * returns a partial remainder */
3932 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3933 /* x86_fprem1 (code); */
3936 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3938 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3944 x86_pop_reg (code, X86_EAX);
3948 if (cfg->opt & MONO_OPT_FCMOV) {
3949 x86_fcomip (code, 1);
3953 /* this overwrites EAX */
3954 EMIT_FPCOMPARE(code);
3955 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3959 if (cfg->opt & MONO_OPT_FCMOV) {
3960 /* zeroing the register at the start results in
3961 * shorter and faster code (we can also remove the widening op)
3963 guchar *unordered_check;
3964 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3965 x86_fcomip (code, 1);
3967 unordered_check = code;
3968 x86_branch8 (code, X86_CC_P, 0, FALSE);
3969 if (ins->opcode == OP_FCEQ) {
3970 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3971 x86_patch (unordered_check, code);
3973 guchar *jump_to_end;
3974 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3976 x86_jump8 (code, 0);
3977 x86_patch (unordered_check, code);
3978 x86_inc_reg (code, ins->dreg);
3979 x86_patch (jump_to_end, code);
3984 if (ins->dreg != X86_EAX)
3985 x86_push_reg (code, X86_EAX);
3987 EMIT_FPCOMPARE(code);
3988 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3989 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3990 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3991 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3993 if (ins->dreg != X86_EAX)
3994 x86_pop_reg (code, X86_EAX);
3998 if (cfg->opt & MONO_OPT_FCMOV) {
3999 /* zeroing the register at the start results in
4000 * shorter and faster code (we can also remove the widening op)
4002 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4003 x86_fcomip (code, 1);
4005 if (ins->opcode == OP_FCLT_UN) {
4006 guchar *unordered_check = code;
4007 guchar *jump_to_end;
4008 x86_branch8 (code, X86_CC_P, 0, FALSE);
4009 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4011 x86_jump8 (code, 0);
4012 x86_patch (unordered_check, code);
4013 x86_inc_reg (code, ins->dreg);
4014 x86_patch (jump_to_end, code);
4016 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4020 if (ins->dreg != X86_EAX)
4021 x86_push_reg (code, X86_EAX);
4023 EMIT_FPCOMPARE(code);
4024 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4025 if (ins->opcode == OP_FCLT_UN) {
4026 guchar *is_not_zero_check, *end_jump;
4027 is_not_zero_check = code;
4028 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4030 x86_jump8 (code, 0);
4031 x86_patch (is_not_zero_check, code);
4032 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4034 x86_patch (end_jump, code);
4036 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4037 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4039 if (ins->dreg != X86_EAX)
4040 x86_pop_reg (code, X86_EAX);
4043 guchar *unordered_check;
4044 guchar *jump_to_end;
4045 if (cfg->opt & MONO_OPT_FCMOV) {
4046 /* zeroing the register at the start results in
4047 * shorter and faster code (we can also remove the widening op)
4049 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4050 x86_fcomip (code, 1);
4052 unordered_check = code;
4053 x86_branch8 (code, X86_CC_P, 0, FALSE);
4054 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
4055 x86_patch (unordered_check, code);
4058 if (ins->dreg != X86_EAX)
4059 x86_push_reg (code, X86_EAX);
4061 EMIT_FPCOMPARE(code);
4062 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4063 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4064 unordered_check = code;
4065 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4067 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4068 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
4069 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4071 x86_jump8 (code, 0);
4072 x86_patch (unordered_check, code);
4073 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4074 x86_patch (jump_to_end, code);
4076 if (ins->dreg != X86_EAX)
4077 x86_pop_reg (code, X86_EAX);
4082 if (cfg->opt & MONO_OPT_FCMOV) {
4083 /* zeroing the register at the start results in
4084 * shorter and faster code (we can also remove the widening op)
4086 guchar *unordered_check;
4087 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4088 x86_fcomip (code, 1);
4090 if (ins->opcode == OP_FCGT) {
4091 unordered_check = code;
4092 x86_branch8 (code, X86_CC_P, 0, FALSE);
4093 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4094 x86_patch (unordered_check, code);
4096 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4100 if (ins->dreg != X86_EAX)
4101 x86_push_reg (code, X86_EAX);
4103 EMIT_FPCOMPARE(code);
4104 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4105 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4106 if (ins->opcode == OP_FCGT_UN) {
4107 guchar *is_not_zero_check, *end_jump;
4108 is_not_zero_check = code;
4109 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4111 x86_jump8 (code, 0);
4112 x86_patch (is_not_zero_check, code);
4113 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4115 x86_patch (end_jump, code);
4117 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4118 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4120 if (ins->dreg != X86_EAX)
4121 x86_pop_reg (code, X86_EAX);
4124 guchar *unordered_check;
4125 guchar *jump_to_end;
4126 if (cfg->opt & MONO_OPT_FCMOV) {
4127 /* zeroing the register at the start results in
4128 * shorter and faster code (we can also remove the widening op)
4130 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4131 x86_fcomip (code, 1);
4133 unordered_check = code;
4134 x86_branch8 (code, X86_CC_P, 0, FALSE);
4135 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4136 x86_patch (unordered_check, code);
4139 if (ins->dreg != X86_EAX)
4140 x86_push_reg (code, X86_EAX);
4142 EMIT_FPCOMPARE(code);
4143 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4144 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4145 unordered_check = code;
4146 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4148 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4149 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4150 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4152 x86_jump8 (code, 0);
4153 x86_patch (unordered_check, code);
4154 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4155 x86_patch (jump_to_end, code);
4157 if (ins->dreg != X86_EAX)
4158 x86_pop_reg (code, X86_EAX);
4162 if (cfg->opt & MONO_OPT_FCMOV) {
4163 guchar *jump = code;
4164 x86_branch8 (code, X86_CC_P, 0, TRUE);
4165 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4166 x86_patch (jump, code);
4169 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4170 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4173 /* Branch if C013 != 100 */
4174 if (cfg->opt & MONO_OPT_FCMOV) {
4175 /* branch if !ZF or (PF|CF) */
4176 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4177 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4178 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4181 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4182 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4185 if (cfg->opt & MONO_OPT_FCMOV) {
4186 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4189 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4192 if (cfg->opt & MONO_OPT_FCMOV) {
4193 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4194 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4197 if (ins->opcode == OP_FBLT_UN) {
4198 guchar *is_not_zero_check, *end_jump;
4199 is_not_zero_check = code;
4200 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4202 x86_jump8 (code, 0);
4203 x86_patch (is_not_zero_check, code);
4204 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4206 x86_patch (end_jump, code);
4208 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4212 if (cfg->opt & MONO_OPT_FCMOV) {
4213 if (ins->opcode == OP_FBGT) {
4216 /* skip branch if C1=1 */
4218 x86_branch8 (code, X86_CC_P, 0, FALSE);
4219 /* branch if (C0 | C3) = 1 */
4220 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4221 x86_patch (br1, code);
4223 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4227 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4228 if (ins->opcode == OP_FBGT_UN) {
4229 guchar *is_not_zero_check, *end_jump;
4230 is_not_zero_check = code;
4231 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4233 x86_jump8 (code, 0);
4234 x86_patch (is_not_zero_check, code);
4235 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4237 x86_patch (end_jump, code);
4239 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4242 /* Branch if C013 == 100 or 001 */
4243 if (cfg->opt & MONO_OPT_FCMOV) {
4246 /* skip branch if C1=1 */
4248 x86_branch8 (code, X86_CC_P, 0, FALSE);
4249 /* branch if (C0 | C3) = 1 */
4250 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4251 x86_patch (br1, code);
4254 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4255 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4256 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4257 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4260 /* Branch if C013 == 000 */
4261 if (cfg->opt & MONO_OPT_FCMOV) {
4262 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4265 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4268 /* Branch if C013=000 or 100 */
4269 if (cfg->opt & MONO_OPT_FCMOV) {
4272 /* skip branch if C1=1 */
4274 x86_branch8 (code, X86_CC_P, 0, FALSE);
4275 /* branch if C0=0 */
4276 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4277 x86_patch (br1, code);
4280 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4281 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4282 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4285 /* Branch if C013 != 001 */
4286 if (cfg->opt & MONO_OPT_FCMOV) {
4287 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4288 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4291 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4292 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4296 x86_push_reg (code, X86_EAX);
4299 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4300 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4301 x86_pop_reg (code, X86_EAX);
4303 /* Have to clean up the fp stack before throwing the exception */
4305 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4308 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4310 x86_patch (br1, code);
4314 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4317 case OP_TLS_GET_REG: {
4318 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4322 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4325 case OP_TLS_SET_REG: {
4326 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4329 case OP_MEMORY_BARRIER: {
4330 /* x86 only needs barrier for StoreLoad and FullBarrier */
4331 switch (ins->backend.memory_barrier_kind) {
4332 case StoreLoadBarrier:
4334 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4335 x86_prefix (code, X86_LOCK_PREFIX);
4336 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4341 case OP_ATOMIC_ADD_I4: {
4342 int dreg = ins->dreg;
4344 if (dreg == ins->inst_basereg) {
4345 x86_push_reg (code, ins->sreg2);
4349 if (dreg != ins->sreg2)
4350 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
4352 x86_prefix (code, X86_LOCK_PREFIX);
4353 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4355 if (dreg != ins->dreg) {
4356 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4357 x86_pop_reg (code, dreg);
4362 case OP_ATOMIC_ADD_NEW_I4: {
4363 int dreg = ins->dreg;
4365 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4366 if (ins->sreg2 == dreg) {
4367 if (dreg == X86_EBX) {
4369 if (ins->inst_basereg == X86_EDI)
4373 if (ins->inst_basereg == X86_EBX)
4376 } else if (ins->inst_basereg == dreg) {
4377 if (dreg == X86_EBX) {
4379 if (ins->sreg2 == X86_EDI)
4383 if (ins->sreg2 == X86_EBX)
4388 if (dreg != ins->dreg) {
4389 x86_push_reg (code, dreg);
4392 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4393 x86_prefix (code, X86_LOCK_PREFIX);
4394 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4395 /* dreg contains the old value, add with sreg2 value */
4396 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4398 if (ins->dreg != dreg) {
4399 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4400 x86_pop_reg (code, dreg);
4405 case OP_ATOMIC_EXCHANGE_I4: {
4407 int sreg2 = ins->sreg2;
4408 int breg = ins->inst_basereg;
4410 /* cmpxchg uses eax as comperand, need to make sure we can use it
4411 * hack to overcome limits in x86 reg allocator
4412 * (req: dreg == eax and sreg2 != eax and breg != eax)
4414 g_assert (ins->dreg == X86_EAX);
4416 /* We need the EAX reg for the cmpxchg */
4417 if (ins->sreg2 == X86_EAX) {
4418 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4419 x86_push_reg (code, sreg2);
4420 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4423 if (breg == X86_EAX) {
4424 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4425 x86_push_reg (code, breg);
4426 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4429 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4431 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4432 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4433 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4434 x86_patch (br [1], br [0]);
4436 if (breg != ins->inst_basereg)
4437 x86_pop_reg (code, breg);
4439 if (ins->sreg2 != sreg2)
4440 x86_pop_reg (code, sreg2);
4444 case OP_ATOMIC_CAS_I4: {
4445 g_assert (ins->dreg == X86_EAX);
4446 g_assert (ins->sreg3 == X86_EAX);
4447 g_assert (ins->sreg1 != X86_EAX);
4448 g_assert (ins->sreg1 != ins->sreg2);
4450 x86_prefix (code, X86_LOCK_PREFIX);
4451 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4454 case OP_CARD_TABLE_WBARRIER: {
4455 int ptr = ins->sreg1;
4456 int value = ins->sreg2;
4458 int nursery_shift, card_table_shift;
4459 gpointer card_table_mask;
4460 size_t nursery_size;
4461 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4462 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4463 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4466 * We need one register we can clobber, we choose EDX and make sreg1
4467 * fixed EAX to work around limitations in the local register allocator.
4468 * sreg2 might get allocated to EDX, but that is not a problem since
4469 * we use it before clobbering EDX.
4471 g_assert (ins->sreg1 == X86_EAX);
4474 * This is the code we produce:
4477 * edx >>= nursery_shift
4478 * cmp edx, (nursery_start >> nursery_shift)
4481 * edx >>= card_table_shift
4482 * card_table[edx] = 1
4486 if (card_table_nursery_check) {
4487 if (value != X86_EDX)
4488 x86_mov_reg_reg (code, X86_EDX, value, 4);
4489 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4490 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4491 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4493 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4494 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4495 if (card_table_mask)
4496 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4497 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4498 if (card_table_nursery_check)
4499 x86_patch (br, code);
4502 #ifdef MONO_ARCH_SIMD_INTRINSICS
4504 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4507 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4510 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4513 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4516 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4519 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4522 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4523 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4526 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4529 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4532 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4535 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4538 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4541 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4544 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4547 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4550 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4553 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4556 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4559 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4562 case OP_PSHUFLEW_HIGH:
4563 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4564 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4566 case OP_PSHUFLEW_LOW:
4567 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4568 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4571 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4572 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4575 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4576 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4579 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4580 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4584 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4587 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4590 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4593 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4596 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4599 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4602 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4603 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4606 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4609 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4612 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4615 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4618 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4621 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4624 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4627 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4630 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4633 case OP_EXTRACT_MASK:
4634 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4638 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4641 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4644 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4648 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4651 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4654 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4657 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4661 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4664 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4667 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4670 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4674 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4677 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4680 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4684 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4687 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4690 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4694 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4697 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4701 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4704 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4707 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4711 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4714 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4717 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4721 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4724 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4727 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4730 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4734 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4737 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4740 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4743 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4746 case OP_PSUM_ABS_DIFF:
4747 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4750 case OP_UNPACK_LOWB:
4751 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4753 case OP_UNPACK_LOWW:
4754 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4756 case OP_UNPACK_LOWD:
4757 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4759 case OP_UNPACK_LOWQ:
4760 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4762 case OP_UNPACK_LOWPS:
4763 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4765 case OP_UNPACK_LOWPD:
4766 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4769 case OP_UNPACK_HIGHB:
4770 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4772 case OP_UNPACK_HIGHW:
4773 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4775 case OP_UNPACK_HIGHD:
4776 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4778 case OP_UNPACK_HIGHQ:
4779 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4781 case OP_UNPACK_HIGHPS:
4782 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4784 case OP_UNPACK_HIGHPD:
4785 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4789 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4792 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4795 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4798 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4801 case OP_PADDB_SAT_UN:
4802 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4804 case OP_PSUBB_SAT_UN:
4805 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4807 case OP_PADDW_SAT_UN:
4808 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4810 case OP_PSUBW_SAT_UN:
4811 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4815 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4818 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4821 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4824 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4828 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4831 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4834 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4836 case OP_PMULW_HIGH_UN:
4837 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4840 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4844 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4847 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4851 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4854 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4858 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4861 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4865 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4868 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4872 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4875 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4879 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4882 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4886 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4889 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4893 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4896 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4900 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4903 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4907 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4909 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4910 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4914 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4916 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4917 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4921 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4923 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4924 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4928 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4930 case OP_EXTRACTX_U2:
4931 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4933 case OP_INSERTX_U1_SLOW:
4934 /*sreg1 is the extracted ireg (scratch)
4935 /sreg2 is the to be inserted ireg (scratch)
4936 /dreg is the xreg to receive the value*/
4938 /*clear the bits from the extracted word*/
4939 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4940 /*shift the value to insert if needed*/
4941 if (ins->inst_c0 & 1)
4942 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4943 /*join them together*/
4944 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4945 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4947 case OP_INSERTX_I4_SLOW:
4948 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4949 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4950 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4953 case OP_INSERTX_R4_SLOW:
4954 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4955 /*TODO if inst_c0 == 0 use movss*/
4956 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4957 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4959 case OP_INSERTX_R8_SLOW:
4960 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4961 if (cfg->verbose_level)
4962 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4964 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4966 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4969 case OP_STOREX_MEMBASE_REG:
4970 case OP_STOREX_MEMBASE:
4971 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4973 case OP_LOADX_MEMBASE:
4974 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4976 case OP_LOADX_ALIGNED_MEMBASE:
4977 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4979 case OP_STOREX_ALIGNED_MEMBASE_REG:
4980 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4982 case OP_STOREX_NTA_MEMBASE_REG:
4983 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4985 case OP_PREFETCH_MEMBASE:
4986 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4990 /*FIXME the peephole pass should have killed this*/
4991 if (ins->dreg != ins->sreg1)
4992 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4995 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4997 case OP_ICONV_TO_R8_RAW:
4998 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4999 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
5002 case OP_FCONV_TO_R8_X:
5003 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
5004 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5007 case OP_XCONV_R8_TO_I4:
5008 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
5009 switch (ins->backend.source_opcode) {
5010 case OP_FCONV_TO_I1:
5011 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5013 case OP_FCONV_TO_U1:
5014 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5016 case OP_FCONV_TO_I2:
5017 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5019 case OP_FCONV_TO_U2:
5020 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5026 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
5027 /*The +4 is to get a mov ?h, ?l over the same reg.*/
5028 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
5029 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
5030 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
5031 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5034 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
5035 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
5036 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5039 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
5040 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5043 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
5044 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5045 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5048 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
5049 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5050 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
5054 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
5057 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
5060 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
5063 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
5066 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
5069 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
5072 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
5075 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
5079 case OP_LIVERANGE_START: {
5080 if (cfg->verbose_level > 1)
5081 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5082 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5085 case OP_LIVERANGE_END: {
5086 if (cfg->verbose_level > 1)
5087 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5088 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5091 case OP_NACL_GC_SAFE_POINT: {
5092 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
5093 if (cfg->compile_aot)
5094 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5098 x86_test_mem_imm8 (code, (gpointer)&__nacl_thread_suspension_needed, 0xFFFFFFFF);
5099 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
5100 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5101 x86_patch (br[0], code);
5106 case OP_GC_LIVENESS_DEF:
5107 case OP_GC_LIVENESS_USE:
5108 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5109 ins->backend.pc_offset = code - cfg->native_code;
5111 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5112 ins->backend.pc_offset = code - cfg->native_code;
5113 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5116 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
5117 g_assert_not_reached ();
5120 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
5121 #ifndef __native_client_codegen__
5122 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5123 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5124 g_assert_not_reached ();
5125 #endif /* __native_client_codegen__ */
5131 cfg->code_len = code - cfg->native_code;
5134 #endif /* DISABLE_JIT */
5137 mono_arch_register_lowlevel_calls (void)
5142 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
5144 MonoJumpInfo *patch_info;
5145 gboolean compile_aot = !run_cctors;
5147 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5148 unsigned char *ip = patch_info->ip.i + code;
5149 const unsigned char *target;
5152 switch (patch_info->type) {
5153 case MONO_PATCH_INFO_BB:
5154 case MONO_PATCH_INFO_LABEL:
5157 /* No need to patch these */
5162 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5164 switch (patch_info->type) {
5165 case MONO_PATCH_INFO_IP:
5166 *((gconstpointer *)(ip)) = target;
5168 case MONO_PATCH_INFO_CLASS_INIT: {
5170 /* Might already been changed to a nop */
5171 x86_call_code (code, 0);
5172 x86_patch (ip, target);
5175 case MONO_PATCH_INFO_ABS:
5176 case MONO_PATCH_INFO_METHOD:
5177 case MONO_PATCH_INFO_METHOD_JUMP:
5178 case MONO_PATCH_INFO_INTERNAL_METHOD:
5179 case MONO_PATCH_INFO_BB:
5180 case MONO_PATCH_INFO_LABEL:
5181 case MONO_PATCH_INFO_RGCTX_FETCH:
5182 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
5183 case MONO_PATCH_INFO_MONITOR_ENTER:
5184 case MONO_PATCH_INFO_MONITOR_EXIT:
5185 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5186 #if defined(__native_client_codegen__) && defined(__native_client__)
5187 if (nacl_is_code_address (code)) {
5188 /* For tail calls, code is patched after being installed */
5189 /* but not through the normal "patch callsite" method. */
5190 unsigned char buf[kNaClAlignment];
5191 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5192 unsigned char *_target = target;
5194 /* All patch targets modified in x86_patch */
5195 /* are IP relative. */
5196 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5197 memcpy (buf, aligned_code, kNaClAlignment);
5198 /* Patch a temp buffer of bundle size, */
5199 /* then install to actual location. */
5200 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5201 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5202 g_assert (ret == 0);
5205 x86_patch (ip, target);
5208 x86_patch (ip, target);
5211 case MONO_PATCH_INFO_NONE:
5213 case MONO_PATCH_INFO_R4:
5214 case MONO_PATCH_INFO_R8: {
5215 guint32 offset = mono_arch_get_patch_offset (ip);
5216 *((gconstpointer *)(ip + offset)) = target;
5220 guint32 offset = mono_arch_get_patch_offset (ip);
5221 #if !defined(__native_client__)
5222 *((gconstpointer *)(ip + offset)) = target;
5224 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5232 static G_GNUC_UNUSED void
5233 stack_unaligned (MonoMethod *m, gpointer caller)
5235 printf ("%s\n", mono_method_full_name (m, TRUE));
5236 g_assert_not_reached ();
5240 mono_arch_emit_prolog (MonoCompile *cfg)
5242 MonoMethod *method = cfg->method;
5244 MonoMethodSignature *sig;
5246 int alloc_size, pos, max_offset, i, cfa_offset;
5248 gboolean need_stack_frame;
5249 #ifdef __native_client_codegen__
5250 guint alignment_check;
5253 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5255 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5256 cfg->code_size += 512;
5258 #if defined(__default_codegen__)
5259 code = cfg->native_code = g_malloc (cfg->code_size);
5260 #elif defined(__native_client_codegen__)
5261 /* native_code_alloc is not 32-byte aligned, native_code is. */
5262 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5263 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5265 /* Align native_code to next nearest kNaclAlignment byte. */
5266 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5267 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5269 code = cfg->native_code;
5271 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5272 g_assert(alignment_check == 0);
5279 /* Check that the stack is aligned on osx */
5280 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5281 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5282 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5284 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5285 x86_push_membase (code, X86_ESP, 0);
5286 x86_push_imm (code, cfg->method);
5287 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5288 x86_call_reg (code, X86_EAX);
5289 x86_patch (br [0], code);
5293 /* Offset between RSP and the CFA */
5297 cfa_offset = sizeof (gpointer);
5298 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5299 // IP saved at CFA - 4
5300 /* There is no IP reg on x86 */
5301 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5302 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5304 need_stack_frame = needs_stack_frame (cfg);
5306 if (need_stack_frame) {
5307 x86_push_reg (code, X86_EBP);
5308 cfa_offset += sizeof (gpointer);
5309 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5310 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5311 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5312 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5313 /* These are handled automatically by the stack marking code */
5314 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5316 cfg->frame_reg = X86_ESP;
5319 alloc_size = cfg->stack_offset;
5322 if (!method->save_lmf) {
5323 if (cfg->used_int_regs & (1 << X86_EBX)) {
5324 x86_push_reg (code, X86_EBX);
5326 cfa_offset += sizeof (gpointer);
5327 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5328 /* These are handled automatically by the stack marking code */
5329 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5332 if (cfg->used_int_regs & (1 << X86_EDI)) {
5333 x86_push_reg (code, X86_EDI);
5335 cfa_offset += sizeof (gpointer);
5336 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5337 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5340 if (cfg->used_int_regs & (1 << X86_ESI)) {
5341 x86_push_reg (code, X86_ESI);
5343 cfa_offset += sizeof (gpointer);
5344 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5345 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5351 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5352 if (mono_do_x86_stack_align && need_stack_frame) {
5353 int tot = alloc_size + pos + 4; /* ret ip */
5354 if (need_stack_frame)
5356 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5358 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5359 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5360 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5364 cfg->arch.sp_fp_offset = alloc_size + pos;
5367 /* See mono_emit_stack_alloc */
5368 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5369 guint32 remaining_size = alloc_size;
5370 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5371 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5372 guint32 offset = code - cfg->native_code;
5373 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5374 while (required_code_size >= (cfg->code_size - offset))
5375 cfg->code_size *= 2;
5376 cfg->native_code = mono_realloc_native_code(cfg);
5377 code = cfg->native_code + offset;
5378 cfg->stat_code_reallocs++;
5380 while (remaining_size >= 0x1000) {
5381 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5382 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5383 remaining_size -= 0x1000;
5386 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5388 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5391 g_assert (need_stack_frame);
5394 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5395 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5396 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5399 #if DEBUG_STACK_ALIGNMENT
5400 /* check the stack is aligned */
5401 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5402 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5403 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5404 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5405 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5406 x86_breakpoint (code);
5410 /* compute max_offset in order to use short forward jumps */
5412 if (cfg->opt & MONO_OPT_BRANCH) {
5413 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5415 bb->max_offset = max_offset;
5417 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5419 /* max alignment for loops */
5420 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5421 max_offset += LOOP_ALIGNMENT;
5422 #ifdef __native_client_codegen__
5423 /* max alignment for native client */
5424 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5425 max_offset += kNaClAlignment;
5427 MONO_BB_FOR_EACH_INS (bb, ins) {
5428 if (ins->opcode == OP_LABEL)
5429 ins->inst_c1 = max_offset;
5430 #ifdef __native_client_codegen__
5431 switch (ins->opcode)
5443 case OP_VOIDCALL_REG:
5445 case OP_FCALL_MEMBASE:
5446 case OP_LCALL_MEMBASE:
5447 case OP_VCALL_MEMBASE:
5448 case OP_VCALL2_MEMBASE:
5449 case OP_VOIDCALL_MEMBASE:
5450 case OP_CALL_MEMBASE:
5451 max_offset += kNaClAlignment;
5454 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5457 #endif /* __native_client_codegen__ */
5458 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5463 /* store runtime generic context */
5464 if (cfg->rgctx_var) {
5465 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5467 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5470 if (method->save_lmf) {
5471 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5473 code = emit_push_lmf (cfg, code, cfg->lmf_var->inst_offset);
5476 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5477 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5479 /* load arguments allocated to register from the stack */
5480 sig = mono_method_signature (method);
5483 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5484 inst = cfg->args [pos];
5485 if (inst->opcode == OP_REGVAR) {
5486 g_assert (need_stack_frame);
5487 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5488 if (cfg->verbose_level > 2)
5489 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5494 cfg->code_len = code - cfg->native_code;
5496 g_assert (cfg->code_len < cfg->code_size);
5502 mono_arch_emit_epilog (MonoCompile *cfg)
5504 MonoMethod *method = cfg->method;
5505 MonoMethodSignature *sig = mono_method_signature (method);
5507 guint32 stack_to_pop;
5509 int max_epilog_size = 16;
5511 gboolean need_stack_frame = needs_stack_frame (cfg);
5513 if (cfg->method->save_lmf)
5514 max_epilog_size += 128;
5516 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5517 cfg->code_size *= 2;
5518 cfg->native_code = mono_realloc_native_code(cfg);
5519 cfg->stat_code_reallocs++;
5522 code = cfg->native_code + cfg->code_len;
5524 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5525 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5527 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5530 if (method->save_lmf) {
5531 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5533 gboolean supported = FALSE;
5535 if (cfg->compile_aot) {
5536 #if defined(__APPLE__) || defined(__linux__)
5539 } else if (mono_get_jit_tls_offset () != -1) {
5543 /* check if we need to restore protection of the stack after a stack overflow */
5545 if (cfg->compile_aot) {
5546 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5548 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5550 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5553 /* we load the value in a separate instruction: this mechanism may be
5554 * used later as a safer way to do thread interruption
5556 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5557 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5559 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5560 /* note that the call trampoline will preserve eax/edx */
5561 x86_call_reg (code, X86_ECX);
5562 x86_patch (patch, code);
5564 /* FIXME: maybe save the jit tls in the prolog */
5568 code = emit_pop_lmf (cfg, code, lmf_offset);
5570 /* restore caller saved regs */
5571 if (cfg->used_int_regs & (1 << X86_EBX)) {
5572 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
5575 if (cfg->used_int_regs & (1 << X86_EDI)) {
5576 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
5578 if (cfg->used_int_regs & (1 << X86_ESI)) {
5579 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
5582 /* EBP is restored by LEAVE */
5584 for (i = 0; i < X86_NREG; ++i) {
5585 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5591 g_assert (need_stack_frame);
5592 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5596 g_assert (need_stack_frame);
5597 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5600 if (cfg->used_int_regs & (1 << X86_ESI)) {
5601 x86_pop_reg (code, X86_ESI);
5603 if (cfg->used_int_regs & (1 << X86_EDI)) {
5604 x86_pop_reg (code, X86_EDI);
5606 if (cfg->used_int_regs & (1 << X86_EBX)) {
5607 x86_pop_reg (code, X86_EBX);
5611 /* Load returned vtypes into registers if needed */
5612 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5613 if (cinfo->ret.storage == ArgValuetypeInReg) {
5614 for (quad = 0; quad < 2; quad ++) {
5615 switch (cinfo->ret.pair_storage [quad]) {
5617 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5619 case ArgOnFloatFpStack:
5620 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5622 case ArgOnDoubleFpStack:
5623 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5628 g_assert_not_reached ();
5633 if (need_stack_frame)
5636 if (CALLCONV_IS_STDCALL (sig)) {
5637 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5639 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5640 } else if (cinfo->vtype_retaddr)
5646 g_assert (need_stack_frame);
5647 x86_ret_imm (code, stack_to_pop);
5652 cfg->code_len = code - cfg->native_code;
5654 g_assert (cfg->code_len < cfg->code_size);
5658 mono_arch_emit_exceptions (MonoCompile *cfg)
5660 MonoJumpInfo *patch_info;
5663 MonoClass *exc_classes [16];
5664 guint8 *exc_throw_start [16], *exc_throw_end [16];
5668 /* Compute needed space */
5669 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5670 if (patch_info->type == MONO_PATCH_INFO_EXC)
5675 * make sure we have enough space for exceptions
5676 * 16 is the size of two push_imm instructions and a call
5678 if (cfg->compile_aot)
5679 code_size = exc_count * 32;
5681 code_size = exc_count * 16;
5683 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5684 cfg->code_size *= 2;
5685 cfg->native_code = mono_realloc_native_code(cfg);
5686 cfg->stat_code_reallocs++;
5689 code = cfg->native_code + cfg->code_len;
5692 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5693 switch (patch_info->type) {
5694 case MONO_PATCH_INFO_EXC: {
5695 MonoClass *exc_class;
5699 x86_patch (patch_info->ip.i + cfg->native_code, code);
5701 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5702 g_assert (exc_class);
5703 throw_ip = patch_info->ip.i;
5705 /* Find a throw sequence for the same exception class */
5706 for (i = 0; i < nthrows; ++i)
5707 if (exc_classes [i] == exc_class)
5710 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5711 x86_jump_code (code, exc_throw_start [i]);
5712 patch_info->type = MONO_PATCH_INFO_NONE;
5717 /* Compute size of code following the push <OFFSET> */
5718 #if defined(__default_codegen__)
5720 #elif defined(__native_client_codegen__)
5721 code = mono_nacl_align (code);
5722 size = kNaClAlignment;
5724 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5726 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5727 /* Use the shorter form */
5729 x86_push_imm (code, 0);
5733 x86_push_imm (code, 0xf0f0f0f0);
5738 exc_classes [nthrows] = exc_class;
5739 exc_throw_start [nthrows] = code;
5742 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5743 patch_info->data.name = "mono_arch_throw_corlib_exception";
5744 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5745 patch_info->ip.i = code - cfg->native_code;
5746 x86_call_code (code, 0);
5747 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5752 exc_throw_end [nthrows] = code;
5764 cfg->code_len = code - cfg->native_code;
5766 g_assert (cfg->code_len < cfg->code_size);
5770 mono_arch_flush_icache (guint8 *code, gint size)
5776 mono_arch_flush_register_windows (void)
5781 mono_arch_is_inst_imm (gint64 imm)
5787 mono_arch_finish_init (void)
5789 if (!g_getenv ("MONO_NO_TLS")) {
5792 * We need to init this multiple times, since when we are first called, the key might not
5793 * be initialized yet.
5795 jit_tls_offset = mono_get_jit_tls_key ();
5797 /* Only 64 tls entries can be accessed using inline code */
5798 if (jit_tls_offset >= 64)
5799 jit_tls_offset = -1;
5802 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5804 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5810 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5814 #ifdef MONO_ARCH_HAVE_IMT
5816 // Linear handler, the bsearch head compare is shorter
5817 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5818 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5819 // x86_patch(ins,target)
5820 //[1 + 5] x86_jump_mem(inst,mem)
5823 #if defined(__default_codegen__)
5824 #define BR_SMALL_SIZE 2
5825 #define BR_LARGE_SIZE 5
5826 #elif defined(__native_client_codegen__)
5827 /* I suspect the size calculation below is actually incorrect. */
5828 /* TODO: fix the calculation that uses these sizes. */
5829 #define BR_SMALL_SIZE 16
5830 #define BR_LARGE_SIZE 12
5831 #endif /*__native_client_codegen__*/
5832 #define JUMP_IMM_SIZE 6
5833 #define ENABLE_WRONG_METHOD_CHECK 0
5837 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5839 int i, distance = 0;
5840 for (i = start; i < target; ++i)
5841 distance += imt_entries [i]->chunk_size;
5846 * LOCKING: called with the domain lock held
5849 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5850 gpointer fail_tramp)
5854 guint8 *code, *start;
5856 for (i = 0; i < count; ++i) {
5857 MonoIMTCheckItem *item = imt_entries [i];
5858 if (item->is_equals) {
5859 if (item->check_target_idx) {
5860 if (!item->compare_done)
5861 item->chunk_size += CMP_SIZE;
5862 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5865 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5867 item->chunk_size += JUMP_IMM_SIZE;
5868 #if ENABLE_WRONG_METHOD_CHECK
5869 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5874 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5875 imt_entries [item->check_target_idx]->compare_done = TRUE;
5877 size += item->chunk_size;
5879 #if defined(__native_client__) && defined(__native_client_codegen__)
5880 /* In Native Client, we don't re-use thunks, allocate from the */
5881 /* normal code manager paths. */
5882 size = NACL_BUNDLE_ALIGN_UP (size);
5883 code = mono_domain_code_reserve (domain, size);
5886 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5888 code = mono_domain_code_reserve (domain, size);
5891 for (i = 0; i < count; ++i) {
5892 MonoIMTCheckItem *item = imt_entries [i];
5893 item->code_target = code;
5894 if (item->is_equals) {
5895 if (item->check_target_idx) {
5896 if (!item->compare_done)
5897 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5898 item->jmp_code = code;
5899 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5900 if (item->has_target_code)
5901 x86_jump_code (code, item->value.target_code);
5903 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5906 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5907 item->jmp_code = code;
5908 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5909 if (item->has_target_code)
5910 x86_jump_code (code, item->value.target_code);
5912 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5913 x86_patch (item->jmp_code, code);
5914 x86_jump_code (code, fail_tramp);
5915 item->jmp_code = NULL;
5917 /* enable the commented code to assert on wrong method */
5918 #if ENABLE_WRONG_METHOD_CHECK
5919 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5920 item->jmp_code = code;
5921 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5923 if (item->has_target_code)
5924 x86_jump_code (code, item->value.target_code);
5926 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5927 #if ENABLE_WRONG_METHOD_CHECK
5928 x86_patch (item->jmp_code, code);
5929 x86_breakpoint (code);
5930 item->jmp_code = NULL;
5935 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5936 item->jmp_code = code;
5937 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5938 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5940 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5943 /* patch the branches to get to the target items */
5944 for (i = 0; i < count; ++i) {
5945 MonoIMTCheckItem *item = imt_entries [i];
5946 if (item->jmp_code) {
5947 if (item->check_target_idx) {
5948 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5954 mono_stats.imt_thunks_size += code - start;
5955 g_assert (code - start <= size);
5959 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5960 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5964 if (mono_jit_map_is_enabled ()) {
5967 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5969 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5970 mono_emit_jit_tramp (start, code - start, buff);
5974 nacl_domain_code_validate (domain, &start, size, &code);
5980 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5982 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5987 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5989 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5993 mono_arch_get_cie_program (void)
5997 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5998 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
6004 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6006 MonoInst *ins = NULL;
6009 if (cmethod->klass == mono_defaults.math_class) {
6010 if (strcmp (cmethod->name, "Sin") == 0) {
6012 } else if (strcmp (cmethod->name, "Cos") == 0) {
6014 } else if (strcmp (cmethod->name, "Tan") == 0) {
6016 } else if (strcmp (cmethod->name, "Atan") == 0) {
6018 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6020 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6022 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
6027 MONO_INST_NEW (cfg, ins, opcode);
6028 ins->type = STACK_R8;
6029 ins->dreg = mono_alloc_freg (cfg);
6030 ins->sreg1 = args [0]->dreg;
6031 MONO_ADD_INS (cfg->cbb, ins);
6034 if (cfg->opt & MONO_OPT_CMOV) {
6037 if (strcmp (cmethod->name, "Min") == 0) {
6038 if (fsig->params [0]->type == MONO_TYPE_I4)
6040 } else if (strcmp (cmethod->name, "Max") == 0) {
6041 if (fsig->params [0]->type == MONO_TYPE_I4)
6046 MONO_INST_NEW (cfg, ins, opcode);
6047 ins->type = STACK_I4;
6048 ins->dreg = mono_alloc_ireg (cfg);
6049 ins->sreg1 = args [0]->dreg;
6050 ins->sreg2 = args [1]->dreg;
6051 MONO_ADD_INS (cfg->cbb, ins);
6056 /* OP_FREM is not IEEE compatible */
6057 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6058 MONO_INST_NEW (cfg, ins, OP_FREM);
6059 ins->inst_i0 = args [0];
6060 ins->inst_i1 = args [1];
6069 mono_arch_print_tree (MonoInst *tree, int arity)
6075 mono_arch_get_patch_offset (guint8 *code)
6077 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
6079 else if (code [0] == 0xba)
6081 else if (code [0] == 0x68)
6084 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
6085 /* push <OFFSET>(<REG>) */
6087 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
6088 /* call *<OFFSET>(<REG>) */
6090 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
6093 else if ((code [0] == 0x58) && (code [1] == 0x05))
6094 /* pop %eax; add <OFFSET>, %eax */
6096 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6097 /* pop <REG>; add <OFFSET>, <REG> */
6099 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6100 /* mov <REG>, imm */
6103 g_assert_not_reached ();
6109 * mono_breakpoint_clean_code:
6111 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6112 * breakpoints in the original code, they are removed in the copy.
6114 * Returns TRUE if no sw breakpoint was present.
6117 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6120 gboolean can_write = TRUE;
6122 * If method_start is non-NULL we need to perform bound checks, since we access memory
6123 * at code - offset we could go before the start of the method and end up in a different
6124 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6127 if (!method_start || code - offset >= method_start) {
6128 memcpy (buf, code - offset, size);
6130 int diff = code - method_start;
6131 memset (buf, 0, size);
6132 memcpy (buf + offset - diff, method_start, diff + size - offset);
6135 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6136 int idx = mono_breakpoint_info_index [i];
6140 ptr = mono_breakpoint_info [idx].address;
6141 if (ptr >= code && ptr < code + size) {
6142 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6144 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6145 buf [ptr - code] = saved_byte;
6152 * mono_x86_get_this_arg_offset:
6154 * Return the offset of the stack location where this is passed during a virtual
6158 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6164 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6166 guint32 esp = regs [X86_ESP];
6167 CallInfo *cinfo = NULL;
6174 * The stack looks like:
6178 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
6180 res = (((MonoObject**)esp) [5 + (offset / 4)]);
6186 #define MAX_ARCH_DELEGATE_PARAMS 10
6189 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6191 guint8 *code, *start;
6192 int code_reserve = 64;
6195 * The stack contains:
6201 start = code = mono_global_codeman_reserve (code_reserve);
6203 /* Replace the this argument with the target */
6204 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6205 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
6206 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6207 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6209 g_assert ((code - start) < code_reserve);
6212 /* 8 for mov_reg and jump, plus 8 for each parameter */
6213 #ifdef __native_client_codegen__
6214 /* TODO: calculate this size correctly */
6215 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6217 code_reserve = 8 + (param_count * 8);
6218 #endif /* __native_client_codegen__ */
6220 * The stack contains:
6221 * <args in reverse order>
6226 * <args in reverse order>
6229 * without unbalancing the stack.
6230 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6231 * and leaving original spot of first arg as placeholder in stack so
6232 * when callee pops stack everything works.
6235 start = code = mono_global_codeman_reserve (code_reserve);
6237 /* store delegate for access to method_ptr */
6238 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6241 for (i = 0; i < param_count; ++i) {
6242 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6243 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6246 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6248 g_assert ((code - start) < code_reserve);
6251 nacl_global_codeman_validate(&start, code_reserve, &code);
6252 mono_debug_add_delegate_trampoline (start, code - start);
6255 *code_len = code - start;
6257 if (mono_jit_map_is_enabled ()) {
6260 buff = (char*)"delegate_invoke_has_target";
6262 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6263 mono_emit_jit_tramp (start, code - start, buff);
6272 mono_arch_get_delegate_invoke_impls (void)
6280 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6281 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
6283 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6284 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6285 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
6286 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
6287 g_free (tramp_name);
6294 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6296 guint8 *code, *start;
6298 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6301 /* FIXME: Support more cases */
6302 if (MONO_TYPE_ISSTRUCT (sig->ret))
6306 * The stack contains:
6312 static guint8* cached = NULL;
6317 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6319 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6321 mono_memory_barrier ();
6325 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6328 for (i = 0; i < sig->param_count; ++i)
6329 if (!mono_is_regsize_var (sig->params [i]))
6332 code = cache [sig->param_count];
6336 if (mono_aot_only) {
6337 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6338 start = mono_aot_get_trampoline (name);
6341 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6344 mono_memory_barrier ();
6346 cache [sig->param_count] = start;
6353 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6356 case X86_EAX: return ctx->eax;
6357 case X86_EBX: return ctx->ebx;
6358 case X86_ECX: return ctx->ecx;
6359 case X86_EDX: return ctx->edx;
6360 case X86_ESP: return ctx->esp;
6361 case X86_EBP: return ctx->ebp;
6362 case X86_ESI: return ctx->esi;
6363 case X86_EDI: return ctx->edi;
6365 g_assert_not_reached ();
6371 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6399 g_assert_not_reached ();
6403 #ifdef MONO_ARCH_SIMD_INTRINSICS
6406 get_float_to_x_spill_area (MonoCompile *cfg)
6408 if (!cfg->fconv_to_r8_x_var) {
6409 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6410 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6412 return cfg->fconv_to_r8_x_var;
6416 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6419 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6422 int dreg, src_opcode;
6424 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6427 switch (src_opcode = ins->opcode) {
6428 case OP_FCONV_TO_I1:
6429 case OP_FCONV_TO_U1:
6430 case OP_FCONV_TO_I2:
6431 case OP_FCONV_TO_U2:
6432 case OP_FCONV_TO_I4:
6439 /* dreg is the IREG and sreg1 is the FREG */
6440 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6441 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6442 fconv->sreg1 = ins->sreg1;
6443 fconv->dreg = mono_alloc_ireg (cfg);
6444 fconv->type = STACK_VTYPE;
6445 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6447 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6451 ins->opcode = OP_XCONV_R8_TO_I4;
6453 ins->klass = mono_defaults.int32_class;
6454 ins->sreg1 = fconv->dreg;
6456 ins->type = STACK_I4;
6457 ins->backend.source_opcode = src_opcode;
6460 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6463 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6468 if (long_ins->opcode == OP_LNEG) {
6470 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6471 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6472 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6477 #ifdef MONO_ARCH_SIMD_INTRINSICS
6479 if (!(cfg->opt & MONO_OPT_SIMD))
6482 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6483 switch (long_ins->opcode) {
6485 vreg = long_ins->sreg1;
6487 if (long_ins->inst_c0) {
6488 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6489 ins->klass = long_ins->klass;
6490 ins->sreg1 = long_ins->sreg1;
6492 ins->type = STACK_VTYPE;
6493 ins->dreg = vreg = alloc_ireg (cfg);
6494 MONO_ADD_INS (cfg->cbb, ins);
6497 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6498 ins->klass = mono_defaults.int32_class;
6500 ins->type = STACK_I4;
6501 ins->dreg = long_ins->dreg + 1;
6502 MONO_ADD_INS (cfg->cbb, ins);
6504 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6505 ins->klass = long_ins->klass;
6506 ins->sreg1 = long_ins->sreg1;
6507 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6508 ins->type = STACK_VTYPE;
6509 ins->dreg = vreg = alloc_ireg (cfg);
6510 MONO_ADD_INS (cfg->cbb, ins);
6512 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6513 ins->klass = mono_defaults.int32_class;
6515 ins->type = STACK_I4;
6516 ins->dreg = long_ins->dreg + 2;
6517 MONO_ADD_INS (cfg->cbb, ins);
6519 long_ins->opcode = OP_NOP;
6521 case OP_INSERTX_I8_SLOW:
6522 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6523 ins->dreg = long_ins->dreg;
6524 ins->sreg1 = long_ins->dreg;
6525 ins->sreg2 = long_ins->sreg2 + 1;
6526 ins->inst_c0 = long_ins->inst_c0 * 2;
6527 MONO_ADD_INS (cfg->cbb, ins);
6529 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6530 ins->dreg = long_ins->dreg;
6531 ins->sreg1 = long_ins->dreg;
6532 ins->sreg2 = long_ins->sreg2 + 2;
6533 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6534 MONO_ADD_INS (cfg->cbb, ins);
6536 long_ins->opcode = OP_NOP;
6539 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6540 ins->dreg = long_ins->dreg;
6541 ins->sreg1 = long_ins->sreg1 + 1;
6542 ins->klass = long_ins->klass;
6543 ins->type = STACK_VTYPE;
6544 MONO_ADD_INS (cfg->cbb, ins);
6546 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6547 ins->dreg = long_ins->dreg;
6548 ins->sreg1 = long_ins->dreg;
6549 ins->sreg2 = long_ins->sreg1 + 2;
6551 ins->klass = long_ins->klass;
6552 ins->type = STACK_VTYPE;
6553 MONO_ADD_INS (cfg->cbb, ins);
6555 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6556 ins->dreg = long_ins->dreg;
6557 ins->sreg1 = long_ins->dreg;;
6558 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6559 ins->klass = long_ins->klass;
6560 ins->type = STACK_VTYPE;
6561 MONO_ADD_INS (cfg->cbb, ins);
6563 long_ins->opcode = OP_NOP;
6566 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6569 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6571 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6574 gpointer *sp, old_value;
6576 const unsigned char *handler;
6578 /*Decode the first instruction to figure out where did we store the spvar*/
6579 /*Our jit MUST generate the following:
6581 Which is encoded as: 0x89 mod_rm.
6582 mod_rm (esp, ebp, imm) which can be: (imm will never be zero)
6583 mod (reg + imm8): 01 reg(esp): 100 rm(ebp): 101 -> 01100101 (0x65)
6584 mod (reg + imm32): 10 reg(esp): 100 rm(ebp): 101 -> 10100101 (0xA5)
6586 handler = clause->handler_start;
6588 if (*handler != 0x89)
6593 if (*handler == 0x65)
6594 offset = *(signed char*)(handler + 1);
6595 else if (*handler == 0xA5)
6596 offset = *(int*)(handler + 1);
6601 bp = MONO_CONTEXT_GET_BP (ctx);
6602 sp = *(gpointer*)(bp + offset);
6605 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6614 * mono_aot_emit_load_got_addr:
6616 * Emit code to load the got address.
6617 * On x86, the result is placed into EBX.
6620 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6622 x86_call_imm (code, 0);
6624 * The patch needs to point to the pop, since the GOT offset needs
6625 * to be added to that address.
6628 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6630 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6631 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6632 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6638 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6641 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6643 g_assert_not_reached ();
6644 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6649 * mono_arch_emit_load_aotconst:
6651 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6652 * TARGET from the mscorlib GOT in full-aot code.
6653 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6657 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6659 /* Load the mscorlib got address */
6660 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6661 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6662 /* arch_emit_got_access () patches this */
6663 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6668 /* Can't put this into mini-x86.h */
6670 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6673 mono_arch_get_trampolines (gboolean aot)
6675 MonoTrampInfo *info;
6676 GSList *tramps = NULL;
6678 mono_x86_get_signal_exception_trampoline (&info, aot);
6680 tramps = g_slist_append (tramps, info);
6687 #define DBG_SIGNAL SIGBUS
6689 #define DBG_SIGNAL SIGSEGV
6692 /* Soft Debug support */
6693 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6696 * mono_arch_set_breakpoint:
6698 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6699 * The location should contain code emitted by OP_SEQ_POINT.
6702 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6707 * In production, we will use int3 (has to fix the size in the md
6708 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6711 g_assert (code [0] == 0x90);
6712 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6716 * mono_arch_clear_breakpoint:
6718 * Clear the breakpoint at IP.
6721 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6726 for (i = 0; i < 6; ++i)
6731 * mono_arch_start_single_stepping:
6733 * Start single stepping.
6736 mono_arch_start_single_stepping (void)
6738 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6742 * mono_arch_stop_single_stepping:
6744 * Stop single stepping.
6747 mono_arch_stop_single_stepping (void)
6749 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6753 * mono_arch_is_single_step_event:
6755 * Return whenever the machine state in SIGCTX corresponds to a single
6759 mono_arch_is_single_step_event (void *info, void *sigctx)
6762 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6764 if (((gpointer)einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6769 siginfo_t* sinfo = (siginfo_t*) info;
6770 /* Sometimes the address is off by 4 */
6771 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6779 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6782 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6783 if (((gpointer)einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6788 siginfo_t* sinfo = (siginfo_t*)info;
6789 /* Sometimes the address is off by 4 */
6790 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6797 #define BREAKPOINT_SIZE 6
6800 * mono_arch_skip_breakpoint:
6802 * See mini-amd64.c for docs.
6805 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6807 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6811 * mono_arch_skip_single_step:
6813 * See mini-amd64.c for docs.
6816 mono_arch_skip_single_step (MonoContext *ctx)
6818 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6822 * mono_arch_get_seq_point_info:
6824 * See mini-amd64.c for docs.
6827 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6834 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6836 ext->lmf.previous_lmf = (gsize)prev_lmf;
6837 /* Mark that this is a MonoLMFExt */
6838 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6839 ext->lmf.ebp = (gssize)ext;
6844 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
6846 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6848 #endif /* !MONOTOUCH */