2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * (C) 2003 Ximian, Inc.
15 #include <mono/metadata/appdomain.h>
16 #include <mono/metadata/debug-helpers.h>
17 #include <mono/metadata/threads.h>
18 #include <mono/metadata/profiler-private.h>
19 #include <mono/utils/mono-math.h>
24 #include "cpu-pentium.h"
26 static gint lmf_tls_offset = -1;
27 static gint appdomain_tls_offset = -1;
28 static gint thread_tls_offset = -1;
31 /* Under windows, the default pinvoke calling convention is stdcall */
32 #define CALLCONV_IS_STDCALL(call_conv) (((call_conv) == MONO_CALL_STDCALL) || ((call_conv) == MONO_CALL_DEFAULT))
34 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
37 #define SIGNAL_STACK_SIZE (64 * 1024)
40 mono_arch_regname (int reg) {
42 case X86_EAX: return "%eax";
43 case X86_EBX: return "%ebx";
44 case X86_ECX: return "%ecx";
45 case X86_EDX: return "%edx";
46 case X86_ESP: return "%esp"; case X86_EBP: return "%ebp";
47 case X86_EDI: return "%edi";
48 case X86_ESI: return "%esi";
54 * mono_arch_get_argument_info:
55 * @csig: a method signature
56 * @param_count: the number of parameters to consider
57 * @arg_info: an array to store the result infos
59 * Gathers information on parameters such as size, alignment and
60 * padding. arg_info should be large enought to hold param_count + 1 entries.
62 * Returns the size of the activation frame.
65 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
67 int k, frame_size = 0;
71 if (MONO_TYPE_ISSTRUCT (csig->ret)) {
72 frame_size += sizeof (gpointer);
76 arg_info [0].offset = offset;
79 frame_size += sizeof (gpointer);
83 arg_info [0].size = frame_size;
85 for (k = 0; k < param_count; k++) {
88 size = mono_type_native_stack_size (csig->params [k], &align);
90 size = mono_type_stack_size (csig->params [k], &align);
92 /* ignore alignment for now */
95 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
96 arg_info [k].pad = pad;
98 arg_info [k + 1].pad = 0;
99 arg_info [k + 1].size = size;
101 arg_info [k + 1].offset = offset;
105 align = MONO_ARCH_FRAME_ALIGNMENT;
106 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
107 arg_info [k].pad = pad;
112 static const guchar cpuid_impl [] = {
113 0x55, /* push %ebp */
114 0x89, 0xe5, /* mov %esp,%ebp */
115 0x53, /* push %ebx */
116 0x8b, 0x45, 0x08, /* mov 0x8(%ebp),%eax */
117 0x0f, 0xa2, /* cpuid */
118 0x50, /* push %eax */
119 0x8b, 0x45, 0x10, /* mov 0x10(%ebp),%eax */
120 0x89, 0x18, /* mov %ebx,(%eax) */
121 0x8b, 0x45, 0x14, /* mov 0x14(%ebp),%eax */
122 0x89, 0x08, /* mov %ecx,(%eax) */
123 0x8b, 0x45, 0x18, /* mov 0x18(%ebp),%eax */
124 0x89, 0x10, /* mov %edx,(%eax) */
126 0x8b, 0x55, 0x0c, /* mov 0xc(%ebp),%edx */
127 0x89, 0x02, /* mov %eax,(%edx) */
133 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
136 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
139 __asm__ __volatile__ (
142 "movl %%eax, %%edx\n"
143 "xorl $0x200000, %%eax\n"
148 "xorl %%edx, %%eax\n"
149 "andl $0x200000, %%eax\n"
157 CpuidFunc func = (CpuidFunc)cpuid_impl;
158 func (id, p_eax, p_ebx, p_ecx, p_edx);
160 * We use this approach because of issues with gcc and pic code, see:
161 * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
162 __asm__ __volatile__ ("cpuid"
163 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
172 * Initialize the cpu to execute managed code.
175 mono_arch_cpu_init (void)
179 /* spec compliance requires running with double precision */
180 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
181 fpcw &= ~X86_FPCW_PRECC_MASK;
182 fpcw |= X86_FPCW_PREC_DOUBLE;
183 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
184 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
189 * This function returns the optimizations supported on this cpu.
192 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
194 int eax, ebx, ecx, edx;
198 /* Feature Flags function, flags returned in EDX. */
199 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
200 if (edx & (1 << 15)) {
201 opts |= MONO_OPT_CMOV;
203 opts |= MONO_OPT_FCMOV;
205 *exclude_mask |= MONO_OPT_FCMOV;
207 *exclude_mask |= MONO_OPT_CMOV;
213 * Determine whenever the trap whose info is in SIGINFO is caused by
217 mono_arch_is_int_overflow (void *sigctx)
219 struct sigcontext *ctx = (struct sigcontext*)sigctx;
222 ip = (guint8*)ctx->SC_EIP;
224 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
228 switch (x86_modrm_rm (ip [1])) {
236 g_assert_not_reached ();
248 is_regsize_var (MonoType *t) {
258 case MONO_TYPE_OBJECT:
259 case MONO_TYPE_STRING:
260 case MONO_TYPE_CLASS:
261 case MONO_TYPE_SZARRAY:
262 case MONO_TYPE_ARRAY:
264 case MONO_TYPE_VALUETYPE:
265 if (t->data.klass->enumtype)
266 return is_regsize_var (t->data.klass->enum_basetype);
273 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
278 for (i = 0; i < cfg->num_varinfo; i++) {
279 MonoInst *ins = cfg->varinfo [i];
280 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
283 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
286 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
287 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
290 /* we dont allocate I1 to registers because there is no simply way to sign extend
291 * 8bit quantities in caller saved registers on x86 */
292 if (is_regsize_var (ins->inst_vtype) || (ins->inst_vtype->type == MONO_TYPE_BOOLEAN) ||
293 (ins->inst_vtype->type == MONO_TYPE_U1) || (ins->inst_vtype->type == MONO_TYPE_U2)||
294 (ins->inst_vtype->type == MONO_TYPE_I2) || (ins->inst_vtype->type == MONO_TYPE_CHAR)) {
295 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
296 g_assert (i == vmv->idx);
297 vars = g_list_prepend (vars, vmv);
301 vars = mono_varlist_sort (cfg, vars, 0);
307 mono_arch_get_global_int_regs (MonoCompile *cfg)
311 /* we can use 3 registers for global allocation */
312 regs = g_list_prepend (regs, (gpointer)X86_EBX);
313 regs = g_list_prepend (regs, (gpointer)X86_ESI);
314 regs = g_list_prepend (regs, (gpointer)X86_EDI);
320 * mono_arch_regalloc_cost:
322 * Return the cost, in number of memory references, of the action of
323 * allocating the variable VMV into a register during global register
327 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
329 MonoInst *ins = cfg->varinfo [vmv->idx];
331 if (cfg->method->save_lmf)
332 /* The register is already saved */
333 return (ins->opcode == OP_ARG) ? 1 : 0;
335 /* push+pop+possible load if it is an argument */
336 return (ins->opcode == OP_ARG) ? 3 : 2;
340 * Set var information according to the calling convention. X86 version.
341 * The locals var stuff should most likely be split in another method.
344 mono_arch_allocate_vars (MonoCompile *m)
346 MonoMethodSignature *sig;
347 MonoMethodHeader *header;
349 int i, offset, size, align, curinst;
351 header = ((MonoMethodNormal *)m->method)->header;
353 sig = m->method->signature;
357 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
358 m->ret->opcode = OP_REGOFFSET;
359 m->ret->inst_basereg = X86_EBP;
360 m->ret->inst_offset = offset;
361 offset += sizeof (gpointer);
363 /* FIXME: handle long and FP values */
364 switch (sig->ret->type) {
368 m->ret->opcode = OP_REGVAR;
369 m->ret->inst_c0 = X86_EAX;
374 inst = m->varinfo [curinst];
375 if (inst->opcode != OP_REGVAR) {
376 inst->opcode = OP_REGOFFSET;
377 inst->inst_basereg = X86_EBP;
379 inst->inst_offset = offset;
380 offset += sizeof (gpointer);
384 if (sig->call_convention == MONO_CALL_VARARG) {
385 m->sig_cookie = offset;
386 offset += sizeof (gpointer);
389 for (i = 0; i < sig->param_count; ++i) {
390 inst = m->varinfo [curinst];
391 if (inst->opcode != OP_REGVAR) {
392 inst->opcode = OP_REGOFFSET;
393 inst->inst_basereg = X86_EBP;
395 inst->inst_offset = offset;
396 size = mono_type_size (sig->params [i], &align);
405 /* reserve space to save LMF and caller saved registers */
407 if (m->method->save_lmf) {
408 offset += sizeof (MonoLMF);
410 if (m->used_int_regs & (1 << X86_EBX)) {
414 if (m->used_int_regs & (1 << X86_EDI)) {
418 if (m->used_int_regs & (1 << X86_ESI)) {
423 for (i = curinst; i < m->num_varinfo; ++i) {
424 inst = m->varinfo [i];
426 if ((inst->flags & MONO_INST_IS_DEAD) || inst->opcode == OP_REGVAR)
429 /* inst->unused indicates native sized value types, this is used by the
430 * pinvoke wrappers when they call functions returning structure */
431 if (inst->unused && MONO_TYPE_ISSTRUCT (inst->inst_vtype) && inst->inst_vtype->type != MONO_TYPE_TYPEDBYREF)
432 size = mono_class_native_size (inst->inst_vtype->data.klass, &align);
434 size = mono_type_size (inst->inst_vtype, &align);
438 offset &= ~(align - 1);
439 inst->opcode = OP_REGOFFSET;
440 inst->inst_basereg = X86_EBP;
441 inst->inst_offset = -offset;
442 //g_print ("allocating local %d to %d\n", i, -offset);
444 offset += (MONO_ARCH_FRAME_ALIGNMENT - 1);
445 offset &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
448 m->stack_offset = -offset;
451 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
452 * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
456 * take the arguments and generate the arch-specific
457 * instructions to properly call the function in call.
458 * This includes pushing, moving arguments to the right register
460 * Issue: who does the spilling if needed, and when?
463 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
465 MonoMethodSignature *sig;
466 int i, n, stack_size, type;
470 /* add the vararg cookie before the non-implicit args */
471 if (call->signature->call_convention == MONO_CALL_VARARG) {
473 /* FIXME: Add support for signature tokens to AOT */
474 cfg->disable_aot = TRUE;
475 MONO_INST_NEW (cfg, arg, OP_OUTARG);
476 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
477 sig_arg->inst_p0 = call->signature;
478 arg->inst_left = sig_arg;
479 arg->type = STACK_PTR;
480 /* prepend, so they get reversed */
481 arg->next = call->out_args;
482 call->out_args = arg;
483 stack_size += sizeof (gpointer);
485 sig = call->signature;
486 n = sig->param_count + sig->hasthis;
488 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret))
489 stack_size += sizeof (gpointer);
490 for (i = 0; i < n; ++i) {
491 if (is_virtual && i == 0) {
492 /* the argument will be attached to the call instrucion */
496 MONO_INST_NEW (cfg, arg, OP_OUTARG);
498 arg->cil_code = in->cil_code;
500 arg->type = in->type;
501 /* prepend, so they get reversed */
502 arg->next = call->out_args;
503 call->out_args = arg;
504 if (i >= sig->hasthis) {
505 ptype = sig->params [i - sig->hasthis];
511 /* FIXME: validate arguments... */
515 case MONO_TYPE_BOOLEAN:
523 case MONO_TYPE_STRING:
524 case MONO_TYPE_CLASS:
525 case MONO_TYPE_OBJECT:
527 case MONO_TYPE_FNPTR:
528 case MONO_TYPE_ARRAY:
529 case MONO_TYPE_SZARRAY:
538 arg->opcode = OP_OUTARG_R4;
542 arg->opcode = OP_OUTARG_R8;
544 case MONO_TYPE_VALUETYPE:
545 if (MONO_TYPE_ISSTRUCT (ptype)) {
548 size = mono_type_native_stack_size (&in->klass->byval_arg, NULL);
550 size = mono_type_stack_size (&in->klass->byval_arg, NULL);
553 arg->opcode = OP_OUTARG_VT;
554 arg->klass = in->klass;
555 arg->unused = sig->pinvoke;
556 arg->inst_imm = size;
558 ptype = ptype->data.klass->enum_basetype;
563 case MONO_TYPE_TYPEDBYREF:
564 stack_size += sizeof (MonoTypedRef);
565 arg->opcode = OP_OUTARG_VT;
566 arg->klass = in->klass;
567 arg->unused = sig->pinvoke;
568 arg->inst_imm = sizeof (MonoTypedRef);
570 case MONO_TYPE_GENERICINST:
571 ptype = ptype->data.generic_inst->generic_type;
576 g_error ("unknown type 0x%02x in mono_arch_call_opcode\n", type);
579 /* the this argument */
584 /* if the function returns a struct, the called method already does a ret $0x4 */
585 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret))
587 call->stack_usage = stack_size;
589 * should set more info in call, such as the stack space
590 * used by the args that needs to be added back to esp
597 * Allow tracing to work with this interface (with an optional argument)
601 * This may be needed on some archs or for debugging support.
604 mono_arch_instrument_mem_needs (MonoMethod *method, int *stack, int *code)
606 /* no stack room needed now (may be needed for FASTCALL-trace support) */
608 /* split prolog-epilog requirements? */
609 *code = 50; /* max bytes needed: check this number */
613 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
617 /* if some args are passed in registers, we need to save them here */
618 x86_push_reg (code, X86_EBP);
619 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
620 x86_push_imm (code, cfg->method);
621 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
622 x86_call_code (code, 0);
623 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
637 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
640 int arg_size = 0, save_mode = SAVE_NONE;
641 MonoMethod *method = cfg->method;
642 int rtype = method->signature->ret->type;
647 /* special case string .ctor icall */
648 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
649 save_mode = SAVE_EAX;
651 save_mode = SAVE_NONE;
655 save_mode = SAVE_EAX_EDX;
661 case MONO_TYPE_VALUETYPE:
662 if (method->signature->ret->data.klass->enumtype) {
663 rtype = method->signature->ret->data.klass->enum_basetype->type;
666 save_mode = SAVE_STRUCT;
669 save_mode = SAVE_EAX;
675 x86_push_reg (code, X86_EDX);
676 x86_push_reg (code, X86_EAX);
677 if (enable_arguments) {
678 x86_push_reg (code, X86_EDX);
679 x86_push_reg (code, X86_EAX);
684 x86_push_reg (code, X86_EAX);
685 if (enable_arguments) {
686 x86_push_reg (code, X86_EAX);
691 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
692 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
693 if (enable_arguments) {
694 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
695 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
700 if (enable_arguments) {
701 x86_push_membase (code, X86_EBP, 8);
711 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
712 x86_push_imm (code, method);
713 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
714 x86_call_code (code, 0);
715 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
719 x86_pop_reg (code, X86_EAX);
720 x86_pop_reg (code, X86_EDX);
723 x86_pop_reg (code, X86_EAX);
726 x86_fld_membase (code, X86_ESP, 0, TRUE);
727 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
737 #define EMIT_COND_BRANCH(ins,cond,sign) \
738 if (ins->flags & MONO_INST_BRLABEL) { \
739 if (ins->inst_i0->inst_c0) { \
740 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
742 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
743 if ((cfg->opt & MONO_OPT_BRANCH) && \
744 x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
745 x86_branch8 (code, cond, 0, sign); \
747 x86_branch32 (code, cond, 0, sign); \
750 if (ins->inst_true_bb->native_offset) { \
751 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
753 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
754 if ((cfg->opt & MONO_OPT_BRANCH) && \
755 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
756 x86_branch8 (code, cond, 0, sign); \
758 x86_branch32 (code, cond, 0, sign); \
762 /* emit an exception if condition is fail */
763 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
765 mono_add_patch_info (cfg, code - cfg->native_code, \
766 MONO_PATCH_INFO_EXC, exc_name); \
767 x86_branch32 (code, cond, 0, signed); \
770 #define EMIT_FPCOMPARE(code) do { \
775 /* FIXME: Add more instructions */
776 #define INST_IGNORES_CFLAGS(ins) (((ins)->opcode == CEE_BR) || ((ins)->opcode == OP_STORE_MEMBASE_IMM))
779 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
781 MonoInst *ins, *last_ins = NULL;
786 switch (ins->opcode) {
788 /* reg = 0 -> XOR (reg, reg) */
789 /* XOR sets cflags on x86, so we cant do it always */
790 if (ins->inst_c0 == 0 && ins->next && INST_IGNORES_CFLAGS (ins->next)) {
791 ins->opcode = CEE_XOR;
792 ins->sreg1 = ins->dreg;
793 ins->sreg2 = ins->dreg;
797 /* remove unnecessary multiplication with 1 */
798 if (ins->inst_imm == 1) {
799 if (ins->dreg != ins->sreg1) {
800 ins->opcode = OP_MOVE;
802 last_ins->next = ins->next;
809 /* OP_COMPARE_IMM (reg, 0)
811 * OP_X86_TEST_NULL (reg)
814 ins->opcode = OP_X86_TEST_NULL;
816 case OP_X86_COMPARE_MEMBASE_IMM:
818 * OP_STORE_MEMBASE_REG reg, offset(basereg)
819 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
821 * OP_STORE_MEMBASE_REG reg, offset(basereg)
822 * OP_COMPARE_IMM reg, imm
824 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
826 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
827 ins->inst_basereg == last_ins->inst_destbasereg &&
828 ins->inst_offset == last_ins->inst_offset) {
829 ins->opcode = OP_COMPARE_IMM;
830 ins->sreg1 = last_ins->sreg1;
832 /* check if we can remove cmp reg,0 with test null */
834 ins->opcode = OP_X86_TEST_NULL;
838 case OP_LOAD_MEMBASE:
839 case OP_LOADI4_MEMBASE:
841 * Note: if reg1 = reg2 the load op is removed
843 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
844 * OP_LOAD_MEMBASE offset(basereg), reg2
846 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
849 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
850 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
851 ins->inst_basereg == last_ins->inst_destbasereg &&
852 ins->inst_offset == last_ins->inst_offset) {
853 if (ins->dreg == last_ins->sreg1) {
854 last_ins->next = ins->next;
858 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
859 ins->opcode = OP_MOVE;
860 ins->sreg1 = last_ins->sreg1;
864 * Note: reg1 must be different from the basereg in the second load
865 * Note: if reg1 = reg2 is equal then second load is removed
867 * OP_LOAD_MEMBASE offset(basereg), reg1
868 * OP_LOAD_MEMBASE offset(basereg), reg2
870 * OP_LOAD_MEMBASE offset(basereg), reg1
873 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
874 || last_ins->opcode == OP_LOAD_MEMBASE) &&
875 ins->inst_basereg != last_ins->dreg &&
876 ins->inst_basereg == last_ins->inst_basereg &&
877 ins->inst_offset == last_ins->inst_offset) {
879 if (ins->dreg == last_ins->dreg) {
880 last_ins->next = ins->next;
884 ins->opcode = OP_MOVE;
885 ins->sreg1 = last_ins->dreg;
888 //g_assert_not_reached ();
892 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
893 * OP_LOAD_MEMBASE offset(basereg), reg
895 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
898 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
899 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
900 ins->inst_basereg == last_ins->inst_destbasereg &&
901 ins->inst_offset == last_ins->inst_offset) {
902 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
903 ins->opcode = OP_ICONST;
904 ins->inst_c0 = last_ins->inst_imm;
905 g_assert_not_reached (); // check this rule
909 case OP_LOADU1_MEMBASE:
910 case OP_LOADI1_MEMBASE:
912 * Note: if reg1 = reg2 the load op is removed
914 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
915 * OP_LOAD_MEMBASE offset(basereg), reg2
917 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
920 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
921 ins->inst_basereg == last_ins->inst_destbasereg &&
922 ins->inst_offset == last_ins->inst_offset) {
923 if (ins->dreg == last_ins->sreg1) {
924 last_ins->next = ins->next;
928 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
929 ins->opcode = OP_MOVE;
930 ins->sreg1 = last_ins->sreg1;
934 case OP_LOADU2_MEMBASE:
935 case OP_LOADI2_MEMBASE:
937 * Note: if reg1 = reg2 the load op is removed
939 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
940 * OP_LOAD_MEMBASE offset(basereg), reg2
942 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
945 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
946 ins->inst_basereg == last_ins->inst_destbasereg &&
947 ins->inst_offset == last_ins->inst_offset) {
948 if (ins->dreg == last_ins->sreg1) {
949 last_ins->next = ins->next;
953 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
954 ins->opcode = OP_MOVE;
955 ins->sreg1 = last_ins->sreg1;
967 if (ins->dreg == ins->sreg1) {
969 last_ins->next = ins->next;
979 if (last_ins && last_ins->opcode == OP_MOVE &&
980 ins->sreg1 == last_ins->dreg &&
981 ins->dreg == last_ins->sreg1) {
982 last_ins->next = ins->next;
991 bb->last_ins = last_ins;
995 branch_cc_table [] = {
996 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
997 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
998 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1001 #define DEBUG(a) if (cfg->verbose_level > 1) a
1005 * returns the offset used by spillvar. It allocates a new
1006 * spill variable if necessary.
1009 mono_spillvar_offset (MonoCompile *cfg, int spillvar)
1011 MonoSpillInfo **si, *info;
1014 si = &cfg->spill_info;
1016 while (i <= spillvar) {
1019 *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
1021 cfg->stack_offset -= sizeof (gpointer);
1022 info->offset = cfg->stack_offset;
1026 return (*si)->offset;
1032 g_assert_not_reached ();
1037 * returns the offset used by spillvar. It allocates a new
1038 * spill float variable if necessary.
1039 * (same as mono_spillvar_offset but for float)
1042 mono_spillvar_offset_float (MonoCompile *cfg, int spillvar)
1044 MonoSpillInfo **si, *info;
1047 si = &cfg->spill_info_float;
1049 while (i <= spillvar) {
1052 *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
1054 cfg->stack_offset -= sizeof (double);
1055 info->offset = cfg->stack_offset;
1059 return (*si)->offset;
1065 g_assert_not_reached ();
1070 * Creates a store for spilled floating point items
1073 create_spilled_store_float (MonoCompile *cfg, int spill, int reg, MonoInst *ins)
1076 MONO_INST_NEW (cfg, store, OP_STORER8_MEMBASE_REG);
1078 store->inst_destbasereg = X86_EBP;
1079 store->inst_offset = mono_spillvar_offset_float (cfg, spill);
1081 DEBUG (g_print ("SPILLED FLOAT STORE (%d at 0x%08x(%%sp)) (from %d)\n", spill, store->inst_offset, reg));
1086 * Creates a load for spilled floating point items
1089 create_spilled_load_float (MonoCompile *cfg, int spill, int reg, MonoInst *ins)
1092 MONO_INST_NEW (cfg, load, OP_LOADR8_SPILL_MEMBASE);
1094 load->inst_basereg = X86_EBP;
1095 load->inst_offset = mono_spillvar_offset_float (cfg, spill);
1097 DEBUG (g_print ("SPILLED FLOAT LOAD (%d at 0x%08x(%%sp)) (from %d)\n", spill, load->inst_offset, reg));
1101 #define reg_is_freeable(r) ((r) >= 0 && (r) <= 7 && X86_IS_CALLEE ((r)))
1108 int flags; /* used to track fp spill/load */
1111 static const char*const * ins_spec = pentium_desc;
1114 print_ins (int i, MonoInst *ins)
1116 const char *spec = ins_spec [ins->opcode];
1117 g_print ("\t%-2d %s", i, mono_inst_name (ins->opcode));
1118 if (spec [MONO_INST_DEST]) {
1119 if (ins->dreg >= MONO_MAX_IREGS)
1120 g_print (" R%d <-", ins->dreg);
1122 g_print (" %s <-", mono_arch_regname (ins->dreg));
1124 if (spec [MONO_INST_SRC1]) {
1125 if (ins->sreg1 >= MONO_MAX_IREGS)
1126 g_print (" R%d", ins->sreg1);
1128 g_print (" %s", mono_arch_regname (ins->sreg1));
1130 if (spec [MONO_INST_SRC2]) {
1131 if (ins->sreg2 >= MONO_MAX_IREGS)
1132 g_print (" R%d", ins->sreg2);
1134 g_print (" %s", mono_arch_regname (ins->sreg2));
1136 if (spec [MONO_INST_CLOB])
1137 g_print (" clobbers: %c", spec [MONO_INST_CLOB]);
1142 print_regtrack (RegTrack *t, int num)
1148 for (i = 0; i < num; ++i) {
1151 if (i >= MONO_MAX_IREGS) {
1152 g_snprintf (buf, sizeof(buf), "R%d", i);
1155 r = mono_arch_regname (i);
1156 g_print ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].last_use);
1160 typedef struct InstList InstList;
1168 static inline InstList*
1169 inst_list_prepend (MonoMemPool *pool, InstList *list, MonoInst *data)
1171 InstList *item = mono_mempool_alloc (pool, sizeof (InstList));
1181 * Force the spilling of the variable in the symbolic register 'reg'.
1184 get_register_force_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, int reg)
1189 sel = cfg->rs->iassign [reg];
1190 /*i = cfg->rs->isymbolic [sel];
1191 g_assert (i == reg);*/
1193 spill = ++cfg->spill_count;
1194 cfg->rs->iassign [i] = -spill - 1;
1195 mono_regstate_free_int (cfg->rs, sel);
1196 /* we need to create a spill var and insert a load to sel after the current instruction */
1197 MONO_INST_NEW (cfg, load, OP_LOAD_MEMBASE);
1199 load->inst_basereg = X86_EBP;
1200 load->inst_offset = mono_spillvar_offset (cfg, spill);
1202 while (ins->next != item->prev->data)
1205 load->next = ins->next;
1207 DEBUG (g_print ("SPILLED LOAD (%d at 0x%08x(%%ebp)) R%d (freed %s)\n", spill, load->inst_offset, i, mono_arch_regname (sel)));
1208 i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
1209 g_assert (i == sel);
1215 get_register_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, guint32 regmask, int reg)
1220 DEBUG (g_print ("\tstart regmask to assign R%d: 0x%08x (R%d <- R%d R%d)\n", reg, regmask, ins->dreg, ins->sreg1, ins->sreg2));
1221 /* exclude the registers in the current instruction */
1222 if (reg != ins->sreg1 && (reg_is_freeable (ins->sreg1) || (ins->sreg1 >= MONO_MAX_IREGS && cfg->rs->iassign [ins->sreg1] >= 0))) {
1223 if (ins->sreg1 >= MONO_MAX_IREGS)
1224 regmask &= ~ (1 << cfg->rs->iassign [ins->sreg1]);
1226 regmask &= ~ (1 << ins->sreg1);
1227 DEBUG (g_print ("\t\texcluding sreg1 %s\n", mono_arch_regname (ins->sreg1)));
1229 if (reg != ins->sreg2 && (reg_is_freeable (ins->sreg2) || (ins->sreg2 >= MONO_MAX_IREGS && cfg->rs->iassign [ins->sreg2] >= 0))) {
1230 if (ins->sreg2 >= MONO_MAX_IREGS)
1231 regmask &= ~ (1 << cfg->rs->iassign [ins->sreg2]);
1233 regmask &= ~ (1 << ins->sreg2);
1234 DEBUG (g_print ("\t\texcluding sreg2 %s %d\n", mono_arch_regname (ins->sreg2), ins->sreg2));
1236 if (reg != ins->dreg && reg_is_freeable (ins->dreg)) {
1237 regmask &= ~ (1 << ins->dreg);
1238 DEBUG (g_print ("\t\texcluding dreg %s\n", mono_arch_regname (ins->dreg)));
1241 DEBUG (g_print ("\t\tavailable regmask: 0x%08x\n", regmask));
1242 g_assert (regmask); /* need at least a register we can free */
1244 /* we should track prev_use and spill the register that's farther */
1245 for (i = 0; i < MONO_MAX_IREGS; ++i) {
1246 if (regmask & (1 << i)) {
1248 DEBUG (g_print ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), cfg->rs->iassign [sel]));
1252 i = cfg->rs->isymbolic [sel];
1253 spill = ++cfg->spill_count;
1254 cfg->rs->iassign [i] = -spill - 1;
1255 mono_regstate_free_int (cfg->rs, sel);
1256 /* we need to create a spill var and insert a load to sel after the current instruction */
1257 MONO_INST_NEW (cfg, load, OP_LOAD_MEMBASE);
1259 load->inst_basereg = X86_EBP;
1260 load->inst_offset = mono_spillvar_offset (cfg, spill);
1262 while (ins->next != item->prev->data)
1265 load->next = ins->next;
1267 DEBUG (g_print ("\tSPILLED LOAD (%d at 0x%08x(%%ebp)) R%d (freed %s)\n", spill, load->inst_offset, i, mono_arch_regname (sel)));
1268 i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
1269 g_assert (i == sel);
1275 create_copy_ins (MonoCompile *cfg, int dest, int src, MonoInst *ins)
1278 MONO_INST_NEW (cfg, copy, OP_MOVE);
1282 copy->next = ins->next;
1285 DEBUG (g_print ("\tforced copy from %s to %s\n", mono_arch_regname (src), mono_arch_regname (dest)));
1290 create_spilled_store (MonoCompile *cfg, int spill, int reg, int prev_reg, MonoInst *ins)
1293 MONO_INST_NEW (cfg, store, OP_STORE_MEMBASE_REG);
1295 store->inst_destbasereg = X86_EBP;
1296 store->inst_offset = mono_spillvar_offset (cfg, spill);
1298 store->next = ins->next;
1301 DEBUG (g_print ("\tSPILLED STORE (%d at 0x%08x(%%ebp)) R%d (from %s)\n", spill, store->inst_offset, prev_reg, mono_arch_regname (reg)));
1306 insert_before_ins (MonoInst *ins, InstList *item, MonoInst* to_insert)
1310 prev = item->next->data;
1312 while (prev->next != ins)
1314 to_insert->next = ins;
1315 prev->next = to_insert;
1317 to_insert->next = ins;
1320 * needed otherwise in the next instruction we can add an ins to the
1321 * end and that would get past this instruction.
1323 item->data = to_insert;
1329 alloc_int_reg (MonoCompile *cfg, InstList *curinst, MonoInst *ins, int sym_reg, guint32 allow_mask)
1331 int val = cfg->rs->iassign [sym_reg];
1335 /* the register gets spilled after this inst */
1338 val = mono_regstate_alloc_int (cfg->rs, allow_mask);
1340 val = get_register_spilling (cfg, curinst, ins, allow_mask, sym_reg);
1341 cfg->rs->iassign [sym_reg] = val;
1342 /* add option to store before the instruction for src registers */
1344 create_spilled_store (cfg, spill, val, sym_reg, ins);
1346 cfg->rs->isymbolic [val] = sym_reg;
1351 /* flags used in reginfo->flags */
1353 MONO_X86_FP_NEEDS_LOAD_SPILL = 1 << 0,
1354 MONO_X86_FP_NEEDS_SPILL = 1 << 1,
1355 MONO_X86_FP_NEEDS_LOAD = 1 << 2,
1356 MONO_X86_REG_NOT_ECX = 1 << 3,
1357 MONO_X86_REG_EAX = 1 << 4,
1358 MONO_X86_REG_EDX = 1 << 5,
1359 MONO_X86_REG_ECX = 1 << 6
1363 mono_x86_alloc_int_reg (MonoCompile *cfg, InstList *tmp, MonoInst *ins, guint32 dest_mask, int sym_reg, int flags)
1366 int test_mask = dest_mask;
1368 if (flags & MONO_X86_REG_EAX)
1369 test_mask &= (1 << X86_EAX);
1370 else if (flags & MONO_X86_REG_EDX)
1371 test_mask &= (1 << X86_EDX);
1372 else if (flags & MONO_X86_REG_ECX)
1373 test_mask &= (1 << X86_ECX);
1374 else if (flags & MONO_X86_REG_NOT_ECX)
1375 test_mask &= ~ (1 << X86_ECX);
1377 val = mono_regstate_alloc_int (cfg->rs, test_mask);
1378 if (val >= 0 && test_mask != dest_mask)
1379 DEBUG(g_print ("\tUsed flag to allocate reg %s for R%u\n", mono_arch_regname (val), sym_reg));
1381 if (val < 0 && (flags & MONO_X86_REG_NOT_ECX)) {
1382 DEBUG(g_print ("\tFailed to allocate flag suggested mask (%u) but exluding ECX\n", test_mask));
1383 val = mono_regstate_alloc_int (cfg->rs, (dest_mask & (~1 << X86_ECX)));
1387 val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1389 val = get_register_spilling (cfg, tmp, ins, dest_mask, sym_reg);
1396 /*#include "cprop.c"*/
1399 * Local register allocation.
1400 * We first scan the list of instructions and we save the liveness info of
1401 * each register (when the register is first used, when it's value is set etc.).
1402 * We also reverse the list of instructions (in the InstList list) because assigning
1403 * registers backwards allows for more tricks to be used.
1406 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1409 MonoRegState *rs = cfg->rs;
1410 int i, val, fpcount;
1411 RegTrack *reginfo, *reginfof;
1412 RegTrack *reginfo1, *reginfo2, *reginfod;
1413 InstList *tmp, *reversed = NULL;
1415 guint32 src1_mask, src2_mask, dest_mask;
1416 GList *fspill_list = NULL;
1421 rs->next_vireg = bb->max_ireg;
1422 rs->next_vfreg = bb->max_freg;
1423 mono_regstate_assign (rs);
1424 reginfo = g_malloc0 (sizeof (RegTrack) * rs->next_vireg);
1425 reginfof = g_malloc0 (sizeof (RegTrack) * rs->next_vfreg);
1426 rs->ifree_mask = X86_CALLEE_REGS;
1430 /*if (cfg->opt & MONO_OPT_COPYPROP)
1431 local_copy_prop (cfg, ins);*/
1435 DEBUG (g_print ("LOCAL regalloc: basic block: %d\n", bb->block_num));
1436 /* forward pass on the instructions to collect register liveness info */
1438 spec = ins_spec [ins->opcode];
1440 DEBUG (print_ins (i, ins));
1442 if (spec [MONO_INST_SRC1]) {
1443 if (spec [MONO_INST_SRC1] == 'f') {
1445 reginfo1 = reginfof;
1447 spill = g_list_first (fspill_list);
1448 if (spill && fpcount < MONO_MAX_FREGS) {
1449 reginfo1 [ins->sreg1].flags |= MONO_X86_FP_NEEDS_LOAD;
1450 fspill_list = g_list_remove (fspill_list, spill->data);
1456 reginfo1 [ins->sreg1].prev_use = reginfo1 [ins->sreg1].last_use;
1457 reginfo1 [ins->sreg1].last_use = i;
1458 if (spec [MONO_INST_SRC1] == 'L') {
1459 /* The virtual register is allocated sequentially */
1460 reginfo1 [ins->sreg1 + 1].prev_use = reginfo1 [ins->sreg1 + 1].last_use;
1461 reginfo1 [ins->sreg1 + 1].last_use = i;
1462 if (reginfo1 [ins->sreg1 + 1].born_in == 0 || reginfo1 [ins->sreg1 + 1].born_in > i)
1463 reginfo1 [ins->sreg1 + 1].born_in = i;
1465 reginfo1 [ins->sreg1].flags |= MONO_X86_REG_EAX;
1466 reginfo1 [ins->sreg1 + 1].flags |= MONO_X86_REG_EDX;
1471 if (spec [MONO_INST_SRC2]) {
1472 if (spec [MONO_INST_SRC2] == 'f') {
1474 reginfo2 = reginfof;
1475 spill = g_list_first (fspill_list);
1477 reginfo2 [ins->sreg2].flags |= MONO_X86_FP_NEEDS_LOAD;
1478 fspill_list = g_list_remove (fspill_list, spill->data);
1479 if (fpcount >= MONO_MAX_FREGS) {
1481 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1482 reginfo2 [ins->sreg2].flags |= MONO_X86_FP_NEEDS_LOAD_SPILL;
1489 reginfo2 [ins->sreg2].prev_use = reginfo2 [ins->sreg2].last_use;
1490 reginfo2 [ins->sreg2].last_use = i;
1491 if (spec [MONO_INST_SRC2] == 'L') {
1492 /* The virtual register is allocated sequentially */
1493 reginfo2 [ins->sreg2 + 1].prev_use = reginfo2 [ins->sreg2 + 1].last_use;
1494 reginfo2 [ins->sreg2 + 1].last_use = i;
1495 if (reginfo2 [ins->sreg2 + 1].born_in == 0 || reginfo2 [ins->sreg2 + 1].born_in > i)
1496 reginfo2 [ins->sreg2 + 1].born_in = i;
1498 if (spec [MONO_INST_CLOB] == 's') {
1499 reginfo2 [ins->sreg1].flags |= MONO_X86_REG_NOT_ECX;
1500 reginfo2 [ins->sreg2].flags |= MONO_X86_REG_ECX;
1505 if (spec [MONO_INST_DEST]) {
1506 if (spec [MONO_INST_DEST] == 'f') {
1507 reginfod = reginfof;
1508 if (fpcount >= MONO_MAX_FREGS) {
1509 reginfod [ins->dreg].flags |= MONO_X86_FP_NEEDS_SPILL;
1511 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1518 if (spec [MONO_INST_DEST] != 'b') /* it's not just a base register */
1519 reginfod [ins->dreg].killed_in = i;
1520 reginfod [ins->dreg].prev_use = reginfod [ins->dreg].last_use;
1521 reginfod [ins->dreg].last_use = i;
1522 if (reginfod [ins->dreg].born_in == 0 || reginfod [ins->dreg].born_in > i)
1523 reginfod [ins->dreg].born_in = i;
1524 if (spec [MONO_INST_DEST] == 'l' || spec [MONO_INST_DEST] == 'L') {
1525 /* The virtual register is allocated sequentially */
1526 reginfod [ins->dreg + 1].prev_use = reginfod [ins->dreg + 1].last_use;
1527 reginfod [ins->dreg + 1].last_use = i;
1528 if (reginfod [ins->dreg + 1].born_in == 0 || reginfod [ins->dreg + 1].born_in > i)
1529 reginfod [ins->dreg + 1].born_in = i;
1531 reginfod [ins->dreg].flags |= MONO_X86_REG_EAX;
1532 reginfod [ins->dreg + 1].flags |= MONO_X86_REG_EDX;
1538 reversed = inst_list_prepend (cfg->mempool, reversed, ins);
1543 // todo: check if we have anything left on fp stack, in verify mode?
1546 DEBUG (print_regtrack (reginfo, rs->next_vireg));
1547 DEBUG (print_regtrack (reginfof, rs->next_vfreg));
1550 int prev_dreg, prev_sreg1, prev_sreg2, clob_dreg;
1551 dest_mask = src1_mask = src2_mask = X86_CALLEE_REGS;
1554 spec = ins_spec [ins->opcode];
1557 DEBUG (g_print ("processing:"));
1558 DEBUG (print_ins (i, ins));
1559 if (spec [MONO_INST_CLOB] == 's') {
1560 if (rs->ifree_mask & (1 << X86_ECX)) {
1561 DEBUG (g_print ("\tshortcut assignment of R%d to ECX\n", ins->sreg2));
1562 rs->iassign [ins->sreg2] = X86_ECX;
1563 rs->isymbolic [X86_ECX] = ins->sreg2;
1564 ins->sreg2 = X86_ECX;
1565 rs->ifree_mask &= ~ (1 << X86_ECX);
1567 int need_ecx_spill = TRUE;
1569 * we first check if src1/dreg is already assigned a register
1570 * and then we force a spill of the var assigned to ECX.
1572 /* the destination register can't be ECX */
1573 dest_mask &= ~ (1 << X86_ECX);
1574 src1_mask &= ~ (1 << X86_ECX);
1575 val = rs->iassign [ins->dreg];
1577 * the destination register is already assigned to ECX:
1578 * we need to allocate another register for it and then
1579 * copy from this to ECX.
1581 if (val == X86_ECX && ins->dreg != ins->sreg2) {
1583 new_dest = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, ins->dreg, reginfo [ins->dreg].flags);
1584 g_assert (new_dest >= 0);
1585 DEBUG (g_print ("\tclob:s changing dreg R%d to %s from ECX\n", ins->dreg, mono_arch_regname (new_dest)));
1587 rs->isymbolic [new_dest] = ins->dreg;
1588 rs->iassign [ins->dreg] = new_dest;
1589 clob_dreg = ins->dreg;
1590 ins->dreg = new_dest;
1591 create_copy_ins (cfg, X86_ECX, new_dest, ins);
1592 need_ecx_spill = FALSE;
1593 /*DEBUG (g_print ("\tforced spill of R%d\n", ins->dreg));
1594 val = get_register_force_spilling (cfg, tmp, ins, ins->dreg);
1595 rs->iassign [ins->dreg] = val;
1596 rs->isymbolic [val] = prev_dreg;
1599 val = rs->iassign [ins->sreg1];
1600 if (val == X86_ECX) {
1601 g_assert_not_reached ();
1602 } else if (val >= 0) {
1604 * the first src reg was already assigned to a register,
1605 * we need to copy it to the dest register because the
1606 * shift instruction clobbers the first operand.
1608 MonoInst *copy = create_copy_ins (cfg, ins->dreg, val, NULL);
1609 DEBUG (g_print ("\tclob:s moved sreg1 from R%d to R%d\n", val, ins->dreg));
1610 insert_before_ins (ins, tmp, copy);
1612 val = rs->iassign [ins->sreg2];
1613 if (val >= 0 && val != X86_ECX) {
1614 MonoInst *move = create_copy_ins (cfg, X86_ECX, val, NULL);
1615 DEBUG (g_print ("\tmoved arg from R%d (%d) to ECX\n", val, ins->sreg2));
1617 g_assert_not_reached ();
1618 /* FIXME: where is move connected to the instruction list? */
1619 //tmp->prev->data->next = move;
1621 if (need_ecx_spill && !(rs->ifree_mask & (1 << X86_ECX))) {
1622 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [X86_ECX]));
1623 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_ECX]);
1624 mono_regstate_free_int (rs, X86_ECX);
1626 /* force-set sreg2 */
1627 rs->iassign [ins->sreg2] = X86_ECX;
1628 rs->isymbolic [X86_ECX] = ins->sreg2;
1629 ins->sreg2 = X86_ECX;
1630 rs->ifree_mask &= ~ (1 << X86_ECX);
1632 } else if (spec [MONO_INST_CLOB] == 'd') { /* division */
1633 int dest_reg = X86_EAX;
1634 int clob_reg = X86_EDX;
1635 if (spec [MONO_INST_DEST] == 'd') {
1636 dest_reg = X86_EDX; /* reminder */
1639 val = rs->iassign [ins->dreg];
1640 if (0 && val >= 0 && val != dest_reg && !(rs->ifree_mask & (1 << dest_reg))) {
1641 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [dest_reg]));
1642 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [dest_reg]);
1643 mono_regstate_free_int (rs, dest_reg);
1647 /* the register gets spilled after this inst */
1648 int spill = -val -1;
1649 dest_mask = 1 << clob_reg;
1650 prev_dreg = ins->dreg;
1651 val = mono_regstate_alloc_int (rs, dest_mask);
1653 val = get_register_spilling (cfg, tmp, ins, dest_mask, ins->dreg);
1654 rs->iassign [ins->dreg] = val;
1656 create_spilled_store (cfg, spill, val, prev_dreg, ins);
1657 DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_arch_regname (val), ins->dreg));
1658 rs->isymbolic [val] = prev_dreg;
1660 if (val != dest_reg) { /* force a copy */
1661 create_copy_ins (cfg, val, dest_reg, ins);
1664 DEBUG (g_print ("\tshortcut assignment of R%d to %s\n", ins->dreg, mono_arch_regname (dest_reg)));
1665 prev_dreg = ins->dreg;
1666 rs->iassign [ins->dreg] = dest_reg;
1667 rs->isymbolic [dest_reg] = ins->dreg;
1668 ins->dreg = dest_reg;
1669 rs->ifree_mask &= ~ (1 << dest_reg);
1672 //DEBUG (g_print ("dest reg in div assigned: %s\n", mono_arch_regname (val)));
1673 if (val != dest_reg) { /* force a copy */
1674 create_copy_ins (cfg, val, dest_reg, ins);
1675 if (!(rs->ifree_mask & (1 << dest_reg)) && rs->isymbolic [dest_reg] >= MONO_MAX_IREGS) {
1676 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [dest_reg]));
1677 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [dest_reg]);
1678 mono_regstate_free_int (rs, dest_reg);
1682 if (!(rs->ifree_mask & (1 << clob_reg)) && (clob_reg != val) && (rs->isymbolic [clob_reg] >= 8)) {
1683 DEBUG (g_print ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1684 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [clob_reg]);
1685 mono_regstate_free_int (rs, clob_reg);
1687 src1_mask = 1 << X86_EAX;
1688 src2_mask = 1 << X86_ECX;
1690 if (spec [MONO_INST_DEST] == 'l') {
1692 val = rs->iassign [ins->dreg];
1693 /* check special case when dreg have been moved from ecx (clob shift) */
1694 if (spec [MONO_INST_CLOB] == 's' && clob_dreg != -1)
1695 hreg = clob_dreg + 1;
1697 hreg = ins->dreg + 1;
1699 /* base prev_dreg on fixed hreg, handle clob case */
1702 if (val != rs->isymbolic [X86_EAX] && !(rs->ifree_mask & (1 << X86_EAX))) {
1703 DEBUG (g_print ("\t(long-low) forced spill of R%d\n", rs->isymbolic [X86_EAX]));
1704 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_EAX]);
1705 mono_regstate_free_int (rs, X86_EAX);
1707 if (hreg != rs->isymbolic [X86_EDX] && !(rs->ifree_mask & (1 << X86_EDX))) {
1708 DEBUG (g_print ("\t(long-high) forced spill of R%d\n", rs->isymbolic [X86_EDX]));
1709 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_EDX]);
1710 mono_regstate_free_int (rs, X86_EDX);
1715 if (spec [MONO_INST_DEST] == 'f') {
1716 if (reginfof [ins->dreg].flags & MONO_X86_FP_NEEDS_SPILL) {
1719 spill_node = g_list_first (fspill_list);
1720 g_assert (spill_node);
1722 store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->dreg, ins);
1723 insert_before_ins (ins, tmp, store);
1724 fspill_list = g_list_remove (fspill_list, spill_node->data);
1727 } else if (spec [MONO_INST_DEST] == 'L') {
1729 val = rs->iassign [ins->dreg];
1730 /* check special case when dreg have been moved from ecx (clob shift) */
1731 if (spec [MONO_INST_CLOB] == 's' && clob_dreg != -1)
1732 hreg = clob_dreg + 1;
1734 hreg = ins->dreg + 1;
1736 /* base prev_dreg on fixed hreg, handle clob case */
1737 prev_dreg = hreg - 1;
1742 /* the register gets spilled after this inst */
1745 val = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, ins->dreg, reginfo [ins->dreg].flags);
1746 rs->iassign [ins->dreg] = val;
1748 create_spilled_store (cfg, spill, val, prev_dreg, ins);
1751 DEBUG (g_print ("\tassigned dreg (long) %s to dest R%d\n", mono_arch_regname (val), hreg - 1));
1753 rs->isymbolic [val] = hreg - 1;
1756 val = rs->iassign [hreg];
1760 /* the register gets spilled after this inst */
1763 val = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, hreg, reginfo [hreg].flags);
1764 rs->iassign [hreg] = val;
1766 create_spilled_store (cfg, spill, val, hreg, ins);
1769 DEBUG (g_print ("\tassigned hreg (long-high) %s to dest R%d\n", mono_arch_regname (val), hreg));
1770 rs->isymbolic [val] = hreg;
1771 /* save reg allocating into unused */
1774 /* check if we can free our long reg */
1775 if (reg_is_freeable (val) && hreg >= 0 && reginfo [hreg].born_in >= i) {
1776 DEBUG (g_print ("\tfreeable %s (R%d) (born in %d)\n", mono_arch_regname (val), hreg, reginfo [hreg].born_in));
1777 mono_regstate_free_int (rs, val);
1780 else if (ins->dreg >= MONO_MAX_IREGS) {
1782 val = rs->iassign [ins->dreg];
1783 if (spec [MONO_INST_DEST] == 'l') {
1784 /* check special case when dreg have been moved from ecx (clob shift) */
1785 if (spec [MONO_INST_CLOB] == 's' && clob_dreg != -1)
1786 hreg = clob_dreg + 1;
1788 hreg = ins->dreg + 1;
1790 /* base prev_dreg on fixed hreg, handle clob case */
1791 prev_dreg = hreg - 1;
1793 prev_dreg = ins->dreg;
1798 /* the register gets spilled after this inst */
1801 val = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, ins->dreg, reginfo [ins->dreg].flags);
1802 rs->iassign [ins->dreg] = val;
1804 create_spilled_store (cfg, spill, val, prev_dreg, ins);
1806 DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_arch_regname (val), ins->dreg));
1807 rs->isymbolic [val] = prev_dreg;
1809 /* handle cases where lreg needs to be eax:edx */
1810 if (spec [MONO_INST_DEST] == 'l') {
1811 /* check special case when dreg have been moved from ecx (clob shift) */
1812 int hreg = prev_dreg + 1;
1813 val = rs->iassign [hreg];
1817 /* the register gets spilled after this inst */
1820 val = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, hreg, reginfo [hreg].flags);
1821 rs->iassign [hreg] = val;
1823 create_spilled_store (cfg, spill, val, hreg, ins);
1825 DEBUG (g_print ("\tassigned hreg %s to dest R%d\n", mono_arch_regname (val), hreg));
1826 rs->isymbolic [val] = hreg;
1827 if (ins->dreg == X86_EAX) {
1829 create_copy_ins (cfg, val, X86_EDX, ins);
1830 } else if (ins->dreg == X86_EDX) {
1831 if (val == X86_EAX) {
1833 g_assert_not_reached ();
1835 /* two forced copies */
1836 create_copy_ins (cfg, val, X86_EDX, ins);
1837 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1840 if (val == X86_EDX) {
1841 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1843 /* two forced copies */
1844 create_copy_ins (cfg, val, X86_EDX, ins);
1845 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1848 if (reg_is_freeable (val) && hreg >= 0 && reginfo [hreg].born_in >= i) {
1849 DEBUG (g_print ("\tfreeable %s (R%d)\n", mono_arch_regname (val), hreg));
1850 mono_regstate_free_int (rs, val);
1852 } else if (spec [MONO_INST_DEST] == 'a' && ins->dreg != X86_EAX && spec [MONO_INST_CLOB] != 'd') {
1853 /* this instruction only outputs to EAX, need to copy */
1854 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1855 } else if (spec [MONO_INST_DEST] == 'd' && ins->dreg != X86_EDX && spec [MONO_INST_CLOB] != 'd') {
1856 create_copy_ins (cfg, ins->dreg, X86_EDX, ins);
1859 if (spec [MONO_INST_DEST] != 'f' && reg_is_freeable (ins->dreg) && prev_dreg >= 0 && reginfo [prev_dreg].born_in >= i) {
1860 DEBUG (g_print ("\tfreeable %s (R%d) (born in %d)\n", mono_arch_regname (ins->dreg), prev_dreg, reginfo [prev_dreg].born_in));
1861 mono_regstate_free_int (rs, ins->dreg);
1863 /* put src1 in EAX if it needs to be */
1864 if (spec [MONO_INST_SRC1] == 'a') {
1865 if (!(rs->ifree_mask & (1 << X86_EAX))) {
1866 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [X86_EAX]));
1867 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_EAX]);
1868 mono_regstate_free_int (rs, X86_EAX);
1870 /* force-set sreg1 */
1871 rs->iassign [ins->sreg1] = X86_EAX;
1872 rs->isymbolic [X86_EAX] = ins->sreg1;
1873 ins->sreg1 = X86_EAX;
1874 rs->ifree_mask &= ~ (1 << X86_EAX);
1878 if (spec [MONO_INST_SRC1] == 'f') {
1879 if (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD) {
1881 MonoInst *store = NULL;
1883 if (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD_SPILL) {
1885 spill_node = g_list_first (fspill_list);
1886 g_assert (spill_node);
1888 store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->sreg1, ins);
1889 fspill_list = g_list_remove (fspill_list, spill_node->data);
1893 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1894 load = create_spilled_load_float (cfg, fspill, ins->sreg1, ins);
1895 insert_before_ins (ins, tmp, load);
1897 insert_before_ins (load, tmp, store);
1899 } else if ((spec [MONO_INST_DEST] == 'L') && (spec [MONO_INST_SRC1] == 'L')) {
1900 /* force source to be same as dest */
1901 rs->iassign [ins->sreg1] = ins->dreg;
1902 rs->iassign [ins->sreg1 + 1] = ins->unused;
1903 rs->isymbolic [ins->dreg] = ins->sreg1;
1904 rs->isymbolic [ins->unused] = ins->sreg1 + 1;
1906 DEBUG (g_print ("\tassigned sreg1 (long) %s to sreg1 R%d\n", mono_arch_regname (ins->dreg), ins->sreg1));
1907 DEBUG (g_print ("\tassigned sreg1 (long-high) %s to sreg1 R%d\n", mono_arch_regname (ins->unused), ins->sreg1 + 1));
1909 ins->sreg1 = ins->dreg;
1911 * No need for saving the reg, we know that src1=dest in this cases
1912 * ins->inst_c0 = ins->unused;
1915 /* make sure that we remove them from free mask */
1916 rs->ifree_mask &= ~ (1 << ins->dreg);
1917 rs->ifree_mask &= ~ (1 << ins->unused);
1919 else if (ins->sreg1 >= MONO_MAX_IREGS) {
1920 val = rs->iassign [ins->sreg1];
1921 prev_sreg1 = ins->sreg1;
1925 /* the register gets spilled after this inst */
1928 if (0 && ins->opcode == OP_MOVE) {
1930 * small optimization: the dest register is already allocated
1931 * but the src one is not: we can simply assign the same register
1932 * here and peephole will get rid of the instruction later.
1933 * This optimization may interfere with the clobbering handling:
1934 * it removes a mov operation that will be added again to handle clobbering.
1935 * There are also some other issues that should with make testjit.
1937 mono_regstate_alloc_int (rs, 1 << ins->dreg);
1938 val = rs->iassign [ins->sreg1] = ins->dreg;
1939 //g_assert (val >= 0);
1940 DEBUG (g_print ("\tfast assigned sreg1 %s to R%d\n", mono_arch_regname (val), ins->sreg1));
1942 //g_assert (val == -1); /* source cannot be spilled */
1943 val = mono_x86_alloc_int_reg (cfg, tmp, ins, src1_mask, ins->sreg1, reginfo [ins->sreg1].flags);
1944 rs->iassign [ins->sreg1] = val;
1945 DEBUG (g_print ("\tassigned sreg1 %s to R%d\n", mono_arch_regname (val), ins->sreg1));
1948 MonoInst *store = create_spilled_store (cfg, spill, val, prev_sreg1, NULL);
1949 insert_before_ins (ins, tmp, store);
1952 rs->isymbolic [val] = prev_sreg1;
1957 /* handle clobbering of sreg1 */
1958 if ((spec [MONO_INST_CLOB] == '1' || spec [MONO_INST_CLOB] == 's') && ins->dreg != ins->sreg1) {
1959 MonoInst *copy = create_copy_ins (cfg, ins->dreg, ins->sreg1, NULL);
1960 DEBUG (g_print ("\tneed to copy sreg1 %s to dreg %s\n", mono_arch_regname (ins->sreg1), mono_arch_regname (ins->dreg)));
1961 if (ins->sreg2 == -1 || spec [MONO_INST_CLOB] == 's') {
1962 /* note: the copy is inserted before the current instruction! */
1963 insert_before_ins (ins, tmp, copy);
1964 /* we set sreg1 to dest as well */
1965 prev_sreg1 = ins->sreg1 = ins->dreg;
1967 /* inserted after the operation */
1968 copy->next = ins->next;
1973 if (spec [MONO_INST_SRC2] == 'f') {
1974 if (reginfof [ins->sreg2].flags & MONO_X86_FP_NEEDS_LOAD) {
1976 MonoInst *store = NULL;
1978 if (reginfof [ins->sreg2].flags & MONO_X86_FP_NEEDS_LOAD_SPILL) {
1981 spill_node = g_list_first (fspill_list);
1982 g_assert (spill_node);
1983 if (spec [MONO_INST_SRC1] == 'f' && (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD_SPILL))
1984 spill_node = g_list_next (spill_node);
1986 store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->sreg2, ins);
1987 fspill_list = g_list_remove (fspill_list, spill_node->data);
1991 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1992 load = create_spilled_load_float (cfg, fspill, ins->sreg2, ins);
1993 insert_before_ins (ins, tmp, load);
1995 insert_before_ins (load, tmp, store);
1998 else if (ins->sreg2 >= MONO_MAX_IREGS) {
1999 val = rs->iassign [ins->sreg2];
2000 prev_sreg2 = ins->sreg2;
2004 /* the register gets spilled after this inst */
2007 val = mono_x86_alloc_int_reg (cfg, tmp, ins, src2_mask, ins->sreg2, reginfo [ins->sreg2].flags);
2008 rs->iassign [ins->sreg2] = val;
2009 DEBUG (g_print ("\tassigned sreg2 %s to R%d\n", mono_arch_regname (val), ins->sreg2));
2011 create_spilled_store (cfg, spill, val, prev_sreg2, ins);
2013 rs->isymbolic [val] = prev_sreg2;
2015 if (spec [MONO_INST_CLOB] == 's' && ins->sreg2 != X86_ECX) {
2016 DEBUG (g_print ("\tassigned sreg2 %s to R%d, but ECX is needed (R%d)\n", mono_arch_regname (val), ins->sreg2, rs->iassign [X86_ECX]));
2022 if (spec [MONO_INST_CLOB] == 'c') {
2024 guint32 clob_mask = X86_CALLEE_REGS;
2025 for (j = 0; j < MONO_MAX_IREGS; ++j) {
2027 if ((clob_mask & s) && !(rs->ifree_mask & s) && j != ins->sreg1) {
2028 //g_warning ("register %s busy at call site\n", mono_arch_regname (j));
2032 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2033 DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2034 mono_regstate_free_int (rs, ins->sreg1);
2036 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2037 DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2038 mono_regstate_free_int (rs, ins->sreg2);
2041 //DEBUG (print_ins (i, ins));
2042 /* this may result from a insert_before call */
2044 bb->code = tmp->data;
2050 g_list_free (fspill_list);
2053 static unsigned char*
2054 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2056 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2057 x86_fnstcw_membase(code, X86_ESP, 0);
2058 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2059 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2060 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2061 x86_fldcw_membase (code, X86_ESP, 2);
2063 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2064 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2065 x86_pop_reg (code, dreg);
2066 /* FIXME: need the high register
2067 * x86_pop_reg (code, dreg_high);
2070 x86_push_reg (code, X86_EAX); // SP = SP - 4
2071 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2072 x86_pop_reg (code, dreg);
2074 x86_fldcw_membase (code, X86_ESP, 0);
2075 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2078 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2080 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2084 static unsigned char*
2085 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2087 int sreg = tree->sreg1;
2088 #ifdef PLATFORM_WIN32
2093 * If requested stack size is larger than one page,
2094 * perform stack-touch operation
2097 * Generate stack probe code.
2098 * Under Windows, it is necessary to allocate one page at a time,
2099 * "touching" stack after each successful sub-allocation. This is
2100 * because of the way stack growth is implemented - there is a
2101 * guard page before the lowest stack page that is currently commited.
2102 * Stack normally grows sequentially so OS traps access to the
2103 * guard page and commits more pages when needed.
2105 x86_test_reg_imm (code, sreg, ~0xFFF);
2106 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2108 br[2] = code; /* loop */
2109 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2110 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2111 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2112 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2113 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2114 x86_patch (br[3], br[2]);
2115 x86_test_reg_reg (code, sreg, sreg);
2116 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2117 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2119 br[1] = code; x86_jump8 (code, 0);
2121 x86_patch (br[0], code);
2122 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2123 x86_patch (br[1], code);
2124 x86_patch (br[4], code);
2125 #else /* PLATFORM_WIN32 */
2126 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2128 if (tree->flags & MONO_INST_INIT) {
2130 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2131 x86_push_reg (code, X86_EAX);
2134 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2135 x86_push_reg (code, X86_ECX);
2138 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2139 x86_push_reg (code, X86_EDI);
2143 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2144 if (sreg != X86_ECX)
2145 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2146 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2148 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2150 x86_prefix (code, X86_REP_PREFIX);
2153 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2154 x86_pop_reg (code, X86_EDI);
2155 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2156 x86_pop_reg (code, X86_ECX);
2157 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2158 x86_pop_reg (code, X86_EAX);
2163 #define REAL_PRINT_REG(text,reg) \
2164 mono_assert (reg >= 0); \
2165 x86_push_reg (code, X86_EAX); \
2166 x86_push_reg (code, X86_EDX); \
2167 x86_push_reg (code, X86_ECX); \
2168 x86_push_reg (code, reg); \
2169 x86_push_imm (code, reg); \
2170 x86_push_imm (code, text " %d %p\n"); \
2171 x86_mov_reg_imm (code, X86_EAX, printf); \
2172 x86_call_reg (code, X86_EAX); \
2173 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2174 x86_pop_reg (code, X86_ECX); \
2175 x86_pop_reg (code, X86_EDX); \
2176 x86_pop_reg (code, X86_EAX);
2178 /* benchmark and set based on cpu */
2179 #define LOOP_ALIGNMENT 8
2180 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2183 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2188 guint8 *code = cfg->native_code + cfg->code_len;
2189 MonoInst *last_ins = NULL;
2190 guint last_offset = 0;
2193 if (cfg->opt & MONO_OPT_PEEPHOLE)
2194 peephole_pass (cfg, bb);
2196 if (cfg->opt & MONO_OPT_LOOP) {
2197 int pad, align = LOOP_ALIGNMENT;
2198 /* set alignment depending on cpu */
2199 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2201 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2202 x86_padding (code, pad);
2203 cfg->code_len += pad;
2204 bb->native_offset = cfg->code_len;
2208 if (cfg->verbose_level > 2)
2209 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2211 cpos = bb->max_offset;
2213 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2214 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2215 g_assert (!mono_compile_aot);
2218 cov->data [bb->dfn].cil_code = bb->cil_code;
2219 /* this is not thread save, but good enough */
2220 x86_inc_mem (code, &cov->data [bb->dfn].count);
2223 offset = code - cfg->native_code;
2227 offset = code - cfg->native_code;
2229 max_len = ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
2231 if (offset > (cfg->code_size - max_len - 16)) {
2232 cfg->code_size *= 2;
2233 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2234 code = cfg->native_code + offset;
2235 mono_jit_stats.code_reallocs++;
2238 mono_debug_record_line_number (cfg, ins, offset);
2240 switch (ins->opcode) {
2242 x86_mul_reg (code, ins->sreg2, TRUE);
2245 x86_mul_reg (code, ins->sreg2, FALSE);
2247 case OP_X86_SETEQ_MEMBASE:
2248 case OP_X86_SETNE_MEMBASE:
2249 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2250 ins->inst_basereg, ins->inst_offset, TRUE);
2252 case OP_STOREI1_MEMBASE_IMM:
2253 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2255 case OP_STOREI2_MEMBASE_IMM:
2256 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2258 case OP_STORE_MEMBASE_IMM:
2259 case OP_STOREI4_MEMBASE_IMM:
2260 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2262 case OP_STOREI1_MEMBASE_REG:
2263 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2265 case OP_STOREI2_MEMBASE_REG:
2266 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2268 case OP_STORE_MEMBASE_REG:
2269 case OP_STOREI4_MEMBASE_REG:
2270 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2275 x86_mov_reg_mem (code, ins->dreg, ins->inst_p0, 4);
2278 x86_mov_reg_imm (code, ins->dreg, ins->inst_p0);
2279 x86_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2281 case OP_LOAD_MEMBASE:
2282 case OP_LOADI4_MEMBASE:
2283 case OP_LOADU4_MEMBASE:
2284 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2286 case OP_LOADU1_MEMBASE:
2287 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2289 case OP_LOADI1_MEMBASE:
2290 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2292 case OP_LOADU2_MEMBASE:
2293 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2295 case OP_LOADI2_MEMBASE:
2296 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2299 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2302 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2305 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2308 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2311 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2313 case OP_COMPARE_IMM:
2314 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2316 case OP_X86_COMPARE_MEMBASE_REG:
2317 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2319 case OP_X86_COMPARE_MEMBASE_IMM:
2320 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2322 case OP_X86_COMPARE_MEMBASE8_IMM:
2323 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2325 case OP_X86_COMPARE_REG_MEMBASE:
2326 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2328 case OP_X86_TEST_NULL:
2329 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2331 case OP_X86_ADD_MEMBASE_IMM:
2332 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2334 case OP_X86_ADD_MEMBASE:
2335 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2337 case OP_X86_SUB_MEMBASE_IMM:
2338 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2340 case OP_X86_SUB_MEMBASE:
2341 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2343 case OP_X86_INC_MEMBASE:
2344 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2346 case OP_X86_INC_REG:
2347 x86_inc_reg (code, ins->dreg);
2349 case OP_X86_DEC_MEMBASE:
2350 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2352 case OP_X86_DEC_REG:
2353 x86_dec_reg (code, ins->dreg);
2355 case OP_X86_MUL_MEMBASE:
2356 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2359 x86_breakpoint (code);
2363 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2366 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2369 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2372 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2376 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2379 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2382 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2385 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2388 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2391 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2395 x86_div_reg (code, ins->sreg2, TRUE);
2398 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2399 x86_div_reg (code, ins->sreg2, FALSE);
2402 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2404 x86_div_reg (code, ins->sreg2, TRUE);
2408 x86_div_reg (code, ins->sreg2, TRUE);
2411 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2412 x86_div_reg (code, ins->sreg2, FALSE);
2415 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2417 x86_div_reg (code, ins->sreg2, TRUE);
2420 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2423 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2426 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2429 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2432 g_assert (ins->sreg2 == X86_ECX);
2433 x86_shift_reg (code, X86_SHL, ins->dreg);
2436 g_assert (ins->sreg2 == X86_ECX);
2437 x86_shift_reg (code, X86_SAR, ins->dreg);
2440 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2443 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2446 g_assert (ins->sreg2 == X86_ECX);
2447 x86_shift_reg (code, X86_SHR, ins->dreg);
2450 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2453 guint8 *jump_to_end;
2455 /* handle shifts below 32 bits */
2456 x86_shld_reg (code, ins->unused, ins->sreg1);
2457 x86_shift_reg (code, X86_SHL, ins->sreg1);
2459 x86_test_reg_imm (code, X86_ECX, 32);
2460 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2462 /* handle shift over 32 bit */
2463 x86_mov_reg_reg (code, ins->unused, ins->sreg1, 4);
2464 x86_clear_reg (code, ins->sreg1);
2466 x86_patch (jump_to_end, code);
2470 guint8 *jump_to_end;
2472 /* handle shifts below 32 bits */
2473 x86_shrd_reg (code, ins->sreg1, ins->unused);
2474 x86_shift_reg (code, X86_SAR, ins->unused);
2476 x86_test_reg_imm (code, X86_ECX, 32);
2477 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2479 /* handle shifts over 31 bits */
2480 x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
2481 x86_shift_reg_imm (code, X86_SAR, ins->unused, 31);
2483 x86_patch (jump_to_end, code);
2487 guint8 *jump_to_end;
2489 /* handle shifts below 32 bits */
2490 x86_shrd_reg (code, ins->sreg1, ins->unused);
2491 x86_shift_reg (code, X86_SHR, ins->unused);
2493 x86_test_reg_imm (code, X86_ECX, 32);
2494 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2496 /* handle shifts over 31 bits */
2497 x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
2498 x86_shift_reg_imm (code, X86_SHR, ins->unused, 31);
2500 x86_patch (jump_to_end, code);
2504 if (ins->inst_imm >= 32) {
2505 x86_mov_reg_reg (code, ins->unused, ins->sreg1, 4);
2506 x86_clear_reg (code, ins->sreg1);
2507 x86_shift_reg_imm (code, X86_SHL, ins->unused, ins->inst_imm - 32);
2509 x86_shld_reg_imm (code, ins->unused, ins->sreg1, ins->inst_imm);
2510 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2514 if (ins->inst_imm >= 32) {
2515 x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
2516 x86_shift_reg_imm (code, X86_SAR, ins->unused, 0x1f);
2517 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2519 x86_shrd_reg_imm (code, ins->sreg1, ins->unused, ins->inst_imm);
2520 x86_shift_reg_imm (code, X86_SAR, ins->unused, ins->inst_imm);
2523 case OP_LSHR_UN_IMM:
2524 if (ins->inst_imm >= 32) {
2525 x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
2526 x86_clear_reg (code, ins->unused);
2527 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2529 x86_shrd_reg_imm (code, ins->sreg1, ins->unused, ins->inst_imm);
2530 x86_shift_reg_imm (code, X86_SHR, ins->unused, ins->inst_imm);
2534 x86_not_reg (code, ins->sreg1);
2537 x86_neg_reg (code, ins->sreg1);
2540 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2543 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2546 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2549 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2552 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2553 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2555 case CEE_MUL_OVF_UN: {
2556 /* the mul operation and the exception check should most likely be split */
2557 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2558 /*g_assert (ins->sreg2 == X86_EAX);
2559 g_assert (ins->dreg == X86_EAX);*/
2560 if (ins->sreg2 == X86_EAX) {
2561 non_eax_reg = ins->sreg1;
2562 } else if (ins->sreg1 == X86_EAX) {
2563 non_eax_reg = ins->sreg2;
2565 /* no need to save since we're going to store to it anyway */
2566 if (ins->dreg != X86_EAX) {
2568 x86_push_reg (code, X86_EAX);
2570 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
2571 non_eax_reg = ins->sreg2;
2573 if (ins->dreg == X86_EDX) {
2576 x86_push_reg (code, X86_EAX);
2578 } else if (ins->dreg != X86_EAX) {
2580 x86_push_reg (code, X86_EDX);
2582 x86_mul_reg (code, non_eax_reg, FALSE);
2583 /* save before the check since pop and mov don't change the flags */
2584 if (ins->dreg != X86_EAX)
2585 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2587 x86_pop_reg (code, X86_EDX);
2589 x86_pop_reg (code, X86_EAX);
2590 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2594 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
2597 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2598 x86_mov_reg_imm (code, ins->dreg, 0);
2602 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2605 g_assert_not_reached ();
2608 * Note: this 'frame destruction' logic is useful for tail calls, too.
2609 * Keep in sync with the code in emit_epilog.
2613 /* FIXME: no tracing support... */
2614 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2615 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2616 /* reset offset to make max_len work */
2617 offset = code - cfg->native_code;
2619 g_assert (!cfg->method->save_lmf);
2621 if (cfg->used_int_regs & (1 << X86_EBX))
2623 if (cfg->used_int_regs & (1 << X86_EDI))
2625 if (cfg->used_int_regs & (1 << X86_ESI))
2628 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
2630 if (cfg->used_int_regs & (1 << X86_ESI))
2631 x86_pop_reg (code, X86_ESI);
2632 if (cfg->used_int_regs & (1 << X86_EDI))
2633 x86_pop_reg (code, X86_EDI);
2634 if (cfg->used_int_regs & (1 << X86_EBX))
2635 x86_pop_reg (code, X86_EBX);
2637 /* restore ESP/EBP */
2639 offset = code - cfg->native_code;
2640 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2641 x86_jump32 (code, 0);
2645 /* ensure ins->sreg1 is not NULL
2646 * note that cmp DWORD PTR [eax], eax is one byte shorter than
2647 * cmp DWORD PTR [eax], 0
2649 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
2652 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
2653 x86_push_reg (code, hreg);
2654 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
2655 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
2656 x86_pop_reg (code, hreg);
2664 call = (MonoCallInst*)ins;
2665 if (ins->flags & MONO_INST_HAS_METHOD)
2666 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
2668 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
2670 x86_call_code (code, 0);
2671 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2672 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2677 case OP_VOIDCALL_REG:
2679 call = (MonoCallInst*)ins;
2680 x86_call_reg (code, ins->sreg1);
2681 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2682 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2684 case OP_FCALL_MEMBASE:
2685 case OP_LCALL_MEMBASE:
2686 case OP_VCALL_MEMBASE:
2687 case OP_VOIDCALL_MEMBASE:
2688 case OP_CALL_MEMBASE:
2689 call = (MonoCallInst*)ins;
2690 x86_call_membase (code, ins->sreg1, ins->inst_offset);
2691 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2692 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2696 x86_push_reg (code, ins->sreg1);
2698 case OP_X86_PUSH_IMM:
2699 x86_push_imm (code, ins->inst_imm);
2701 case OP_X86_PUSH_MEMBASE:
2702 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
2704 case OP_X86_PUSH_OBJ:
2705 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
2706 x86_push_reg (code, X86_EDI);
2707 x86_push_reg (code, X86_ESI);
2708 x86_push_reg (code, X86_ECX);
2709 if (ins->inst_offset)
2710 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
2712 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
2713 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2714 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
2716 x86_prefix (code, X86_REP_PREFIX);
2718 x86_pop_reg (code, X86_ECX);
2719 x86_pop_reg (code, X86_ESI);
2720 x86_pop_reg (code, X86_EDI);
2723 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->unused);
2725 case OP_X86_LEA_MEMBASE:
2726 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
2729 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
2732 /* keep alignment */
2733 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
2734 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
2735 code = mono_emit_stack_alloc (code, ins);
2736 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2742 x86_push_reg (code, ins->sreg1);
2743 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2744 (gpointer)"mono_arch_throw_exception");
2745 x86_call_code (code, 0);
2748 case OP_CALL_HANDLER:
2749 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2750 x86_call_imm (code, 0);
2753 ins->inst_c0 = code - cfg->native_code;
2756 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
2757 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
2759 if (ins->flags & MONO_INST_BRLABEL) {
2760 if (ins->inst_i0->inst_c0) {
2761 x86_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
2763 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
2764 if ((cfg->opt & MONO_OPT_BRANCH) &&
2765 x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
2766 x86_jump8 (code, 0);
2768 x86_jump32 (code, 0);
2771 if (ins->inst_target_bb->native_offset) {
2772 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
2774 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2775 if ((cfg->opt & MONO_OPT_BRANCH) &&
2776 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
2777 x86_jump8 (code, 0);
2779 x86_jump32 (code, 0);
2784 x86_jump_reg (code, ins->sreg1);
2787 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
2788 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2791 x86_set_reg (code, X86_CC_LT, ins->dreg, TRUE);
2792 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2795 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
2796 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2799 x86_set_reg (code, X86_CC_GT, ins->dreg, TRUE);
2800 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2803 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
2804 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2807 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
2808 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2810 case OP_COND_EXC_EQ:
2811 case OP_COND_EXC_NE_UN:
2812 case OP_COND_EXC_LT:
2813 case OP_COND_EXC_LT_UN:
2814 case OP_COND_EXC_GT:
2815 case OP_COND_EXC_GT_UN:
2816 case OP_COND_EXC_GE:
2817 case OP_COND_EXC_GE_UN:
2818 case OP_COND_EXC_LE:
2819 case OP_COND_EXC_LE_UN:
2820 case OP_COND_EXC_OV:
2821 case OP_COND_EXC_NO:
2823 case OP_COND_EXC_NC:
2824 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
2825 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
2837 EMIT_COND_BRANCH (ins, branch_cc_table [ins->opcode - CEE_BEQ], (ins->opcode < CEE_BNE_UN));
2840 /* floating point opcodes */
2842 double d = *(double *)ins->inst_p0;
2844 if ((d == 0.0) && (mono_signbit (d) == 0)) {
2846 } else if (d == 1.0) {
2849 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
2850 x86_fld (code, NULL, TRUE);
2855 float f = *(float *)ins->inst_p0;
2857 if ((f == 0.0) && (mono_signbit (f) == 0)) {
2859 } else if (f == 1.0) {
2862 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
2863 x86_fld (code, NULL, FALSE);
2867 case OP_STORER8_MEMBASE_REG:
2868 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
2870 case OP_LOADR8_SPILL_MEMBASE:
2871 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
2874 case OP_LOADR8_MEMBASE:
2875 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
2877 case OP_STORER4_MEMBASE_REG:
2878 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
2880 case OP_LOADR4_MEMBASE:
2881 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
2883 case CEE_CONV_R4: /* FIXME: change precision */
2885 x86_push_reg (code, ins->sreg1);
2886 x86_fild_membase (code, X86_ESP, 0, FALSE);
2887 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2889 case OP_X86_FP_LOAD_I8:
2890 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
2892 case OP_X86_FP_LOAD_I4:
2893 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
2895 case OP_FCONV_TO_I1:
2896 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
2898 case OP_FCONV_TO_U1:
2899 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
2901 case OP_FCONV_TO_I2:
2902 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
2904 case OP_FCONV_TO_U2:
2905 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
2907 case OP_FCONV_TO_I4:
2909 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
2911 case OP_FCONV_TO_I8:
2912 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2913 x86_fnstcw_membase(code, X86_ESP, 0);
2914 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
2915 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
2916 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
2917 x86_fldcw_membase (code, X86_ESP, 2);
2918 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2919 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2920 x86_pop_reg (code, ins->dreg);
2921 x86_pop_reg (code, ins->unused);
2922 x86_fldcw_membase (code, X86_ESP, 0);
2923 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2925 case OP_LCONV_TO_R_UN: {
2926 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
2929 /* load 64bit integer to FP stack */
2930 x86_push_imm (code, 0);
2931 x86_push_reg (code, ins->sreg2);
2932 x86_push_reg (code, ins->sreg1);
2933 x86_fild_membase (code, X86_ESP, 0, TRUE);
2934 /* store as 80bit FP value */
2935 x86_fst80_membase (code, X86_ESP, 0);
2937 /* test if lreg is negative */
2938 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
2939 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
2941 /* add correction constant mn */
2942 x86_fld80_mem (code, mn);
2943 x86_fld80_membase (code, X86_ESP, 0);
2944 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
2945 x86_fst80_membase (code, X86_ESP, 0);
2947 x86_patch (br, code);
2949 x86_fld80_membase (code, X86_ESP, 0);
2950 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
2954 case OP_LCONV_TO_OVF_I: {
2955 guint8 *br [3], *label [1];
2958 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
2960 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2962 /* If the low word top bit is set, see if we are negative */
2963 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
2964 /* We are not negative (no top bit set, check for our top word to be zero */
2965 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
2966 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2969 /* throw exception */
2970 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
2971 x86_jump32 (code, 0);
2973 x86_patch (br [0], code);
2974 /* our top bit is set, check that top word is 0xfffffff */
2975 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
2977 x86_patch (br [1], code);
2978 /* nope, emit exception */
2979 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
2980 x86_patch (br [2], label [0]);
2982 if (ins->dreg != ins->sreg1)
2983 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2987 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
2990 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
2993 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
2996 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3004 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3009 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3016 * it really doesn't make sense to inline all this code,
3017 * it's here just to show that things may not be as simple
3020 guchar *check_pos, *end_tan, *pop_jump;
3021 x86_push_reg (code, X86_EAX);
3024 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3026 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3027 x86_fstp (code, 0); /* pop the 1.0 */
3029 x86_jump8 (code, 0);
3031 x86_fp_op (code, X86_FADD, 0);
3035 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3037 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3040 x86_patch (pop_jump, code);
3041 x86_fstp (code, 0); /* pop the 1.0 */
3042 x86_patch (check_pos, code);
3043 x86_patch (end_tan, code);
3045 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3046 x86_pop_reg (code, X86_EAX);
3053 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3064 x86_push_reg (code, X86_EAX);
3065 /* we need to exchange ST(0) with ST(1) */
3068 /* this requires a loop, because fprem somtimes
3069 * returns a partial remainder */
3071 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3072 /* x86_fprem1 (code); */
3075 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3077 x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3082 x86_pop_reg (code, X86_EAX);
3086 if (cfg->opt & MONO_OPT_FCMOV) {
3087 x86_fcomip (code, 1);
3091 /* this overwrites EAX */
3092 EMIT_FPCOMPARE(code);
3093 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3096 if (cfg->opt & MONO_OPT_FCMOV) {
3097 /* zeroing the register at the start results in
3098 * shorter and faster code (we can also remove the widening op)
3100 guchar *unordered_check;
3101 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3102 x86_fcomip (code, 1);
3104 unordered_check = code;
3105 x86_branch8 (code, X86_CC_P, 0, FALSE);
3106 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3107 x86_patch (unordered_check, code);
3110 if (ins->dreg != X86_EAX)
3111 x86_push_reg (code, X86_EAX);
3113 EMIT_FPCOMPARE(code);
3114 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3115 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3116 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3117 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3119 if (ins->dreg != X86_EAX)
3120 x86_pop_reg (code, X86_EAX);
3124 if (cfg->opt & MONO_OPT_FCMOV) {
3125 /* zeroing the register at the start results in
3126 * shorter and faster code (we can also remove the widening op)
3128 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3129 x86_fcomip (code, 1);
3131 if (ins->opcode == OP_FCLT_UN) {
3132 guchar *unordered_check = code;
3133 guchar *jump_to_end;
3134 x86_branch8 (code, X86_CC_P, 0, FALSE);
3135 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3137 x86_jump8 (code, 0);
3138 x86_patch (unordered_check, code);
3139 x86_inc_reg (code, ins->dreg);
3140 x86_patch (jump_to_end, code);
3142 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3146 if (ins->dreg != X86_EAX)
3147 x86_push_reg (code, X86_EAX);
3149 EMIT_FPCOMPARE(code);
3150 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3151 if (ins->opcode == OP_FCLT_UN) {
3152 guchar *is_not_zero_check, *end_jump;
3153 is_not_zero_check = code;
3154 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3156 x86_jump8 (code, 0);
3157 x86_patch (is_not_zero_check, code);
3158 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3160 x86_patch (end_jump, code);
3162 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3163 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3165 if (ins->dreg != X86_EAX)
3166 x86_pop_reg (code, X86_EAX);
3170 if (cfg->opt & MONO_OPT_FCMOV) {
3171 /* zeroing the register at the start results in
3172 * shorter and faster code (we can also remove the widening op)
3174 guchar *unordered_check;
3175 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3176 x86_fcomip (code, 1);
3178 if (ins->opcode == OP_FCGT) {
3179 unordered_check = code;
3180 x86_branch8 (code, X86_CC_P, 0, FALSE);
3181 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3182 x86_patch (unordered_check, code);
3184 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3188 if (ins->dreg != X86_EAX)
3189 x86_push_reg (code, X86_EAX);
3191 EMIT_FPCOMPARE(code);
3192 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3193 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3194 if (ins->opcode == OP_FCGT_UN) {
3195 guchar *is_not_zero_check, *end_jump;
3196 is_not_zero_check = code;
3197 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3199 x86_jump8 (code, 0);
3200 x86_patch (is_not_zero_check, code);
3201 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3203 x86_patch (end_jump, code);
3205 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3206 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3208 if (ins->dreg != X86_EAX)
3209 x86_pop_reg (code, X86_EAX);
3212 if (cfg->opt & MONO_OPT_FCMOV) {
3213 guchar *jump = code;
3214 x86_branch8 (code, X86_CC_P, 0, TRUE);
3215 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3216 x86_patch (jump, code);
3219 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3220 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3223 /* Branch if C013 != 100 */
3224 if (cfg->opt & MONO_OPT_FCMOV) {
3225 /* branch if !ZF or (PF|CF) */
3226 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3227 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3228 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3231 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3232 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3235 if (cfg->opt & MONO_OPT_FCMOV) {
3236 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3239 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3242 if (cfg->opt & MONO_OPT_FCMOV) {
3243 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3244 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3247 if (ins->opcode == OP_FBLT_UN) {
3248 guchar *is_not_zero_check, *end_jump;
3249 is_not_zero_check = code;
3250 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3252 x86_jump8 (code, 0);
3253 x86_patch (is_not_zero_check, code);
3254 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3256 x86_patch (end_jump, code);
3258 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3262 if (cfg->opt & MONO_OPT_FCMOV) {
3263 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3266 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3267 if (ins->opcode == OP_FBGT_UN) {
3268 guchar *is_not_zero_check, *end_jump;
3269 is_not_zero_check = code;
3270 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3272 x86_jump8 (code, 0);
3273 x86_patch (is_not_zero_check, code);
3274 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3276 x86_patch (end_jump, code);
3278 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3281 /* Branch if C013 == 100 or 001 */
3282 if (cfg->opt & MONO_OPT_FCMOV) {
3285 /* skip branch if C1=1 */
3287 x86_branch8 (code, X86_CC_P, 0, FALSE);
3288 /* branch if (C0 | C3) = 1 */
3289 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3290 x86_patch (br1, code);
3293 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3294 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3295 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3296 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3299 /* Branch if C013 == 000 */
3300 if (cfg->opt & MONO_OPT_FCMOV) {
3301 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3304 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3307 /* Branch if C013=000 or 100 */
3308 if (cfg->opt & MONO_OPT_FCMOV) {
3311 /* skip branch if C1=1 */
3313 x86_branch8 (code, X86_CC_P, 0, FALSE);
3314 /* branch if C0=0 */
3315 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3316 x86_patch (br1, code);
3319 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
3320 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
3321 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3324 /* Branch if C013 != 001 */
3325 if (cfg->opt & MONO_OPT_FCMOV) {
3326 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3327 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3330 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3331 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3333 case CEE_CKFINITE: {
3334 x86_push_reg (code, X86_EAX);
3337 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
3338 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3339 x86_pop_reg (code, X86_EAX);
3340 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3344 case OP_X86_TLS_GET: {
3345 x86_prefix (code, X86_GS_PREFIX);
3346 x86_mov_reg_mem (code, ins->dreg, ins->inst_offset, 4);
3350 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3351 g_assert_not_reached ();
3354 if ((code - cfg->native_code - offset) > max_len) {
3355 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
3356 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
3357 g_assert_not_reached ();
3363 last_offset = offset;
3368 cfg->code_len = code - cfg->native_code;
3372 mono_arch_register_lowlevel_calls (void)
3377 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3379 MonoJumpInfo *patch_info;
3381 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3382 unsigned char *ip = patch_info->ip.i + code;
3383 const unsigned char *target;
3385 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3387 switch (patch_info->type) {
3388 case MONO_PATCH_INFO_IP:
3389 *((gconstpointer *)(ip)) = target;
3391 case MONO_PATCH_INFO_METHOD_REL:
3392 *((gconstpointer *)(ip)) = target;
3394 case MONO_PATCH_INFO_SWITCH: {
3395 *((gconstpointer *)(ip + 2)) = target;
3396 /* we put into the table the absolute address, no need for x86_patch in this case */
3399 case MONO_PATCH_INFO_IID:
3400 *((guint32 *)(ip + 1)) = (guint32)target;
3402 case MONO_PATCH_INFO_CLASS_INIT: {
3404 /* Might already been changed to a nop */
3405 x86_call_imm (code, 0);
3408 case MONO_PATCH_INFO_R4:
3409 case MONO_PATCH_INFO_R8:
3410 *((gconstpointer *)(ip + 2)) = target;
3412 case MONO_PATCH_INFO_METHODCONST:
3413 case MONO_PATCH_INFO_CLASS:
3414 case MONO_PATCH_INFO_IMAGE:
3415 case MONO_PATCH_INFO_FIELD:
3416 case MONO_PATCH_INFO_VTABLE:
3417 case MONO_PATCH_INFO_SFLDA:
3418 case MONO_PATCH_INFO_EXC_NAME:
3419 case MONO_PATCH_INFO_LDSTR:
3420 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
3421 case MONO_PATCH_INFO_LDTOKEN:
3422 *((gconstpointer *)(ip + 1)) = target;
3427 x86_patch (ip, target);
3432 mono_arch_max_epilog_size (MonoCompile *cfg)
3434 int exc_count = 0, max_epilog_size = 16;
3435 MonoJumpInfo *patch_info;
3437 if (cfg->method->save_lmf)
3438 max_epilog_size += 128;
3440 if (mono_jit_trace_calls != NULL)
3441 max_epilog_size += 50;
3443 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3444 max_epilog_size += 50;
3446 /* count the number of exception infos */
3448 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
3449 if (patch_info->type == MONO_PATCH_INFO_EXC)
3454 * make sure we have enough space for exceptions
3455 * 16 is the size of two push_imm instructions and a call
3457 max_epilog_size += exc_count*16;
3459 return max_epilog_size;
3463 mono_arch_emit_prolog (MonoCompile *cfg)
3465 MonoMethod *method = cfg->method;
3467 MonoMethodSignature *sig;
3469 int alloc_size, pos, max_offset, i;
3472 cfg->code_size = MAX (((MonoMethodNormal *)method)->header->code_size * 4, 256);
3473 code = cfg->native_code = g_malloc (cfg->code_size);
3475 x86_push_reg (code, X86_EBP);
3476 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
3478 alloc_size = - cfg->stack_offset;
3481 if (method->save_lmf) {
3482 pos += sizeof (MonoLMF);
3484 /* save the current IP */
3485 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
3486 x86_push_imm (code, 0);
3488 /* save all caller saved regs */
3489 x86_push_reg (code, X86_EBP);
3490 x86_push_reg (code, X86_ESI);
3491 x86_push_reg (code, X86_EDI);
3492 x86_push_reg (code, X86_EBX);
3494 /* save method info */
3495 x86_push_imm (code, method);
3497 /* get the address of lmf for the current thread */
3499 * This is performance critical so we try to use some tricks to make
3502 if (lmf_tls_offset != -1) {
3503 /* Load lmf quicky using the GS register */
3504 x86_prefix (code, X86_GS_PREFIX);
3505 x86_mov_reg_mem (code, X86_EAX, lmf_tls_offset, 4);
3508 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3509 (gpointer)"mono_get_lmf_addr");
3510 x86_call_code (code, 0);
3514 x86_push_reg (code, X86_EAX);
3515 /* push *lfm (previous_lmf) */
3516 x86_push_membase (code, X86_EAX, 0);
3518 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
3521 if (cfg->used_int_regs & (1 << X86_EBX)) {
3522 x86_push_reg (code, X86_EBX);
3526 if (cfg->used_int_regs & (1 << X86_EDI)) {
3527 x86_push_reg (code, X86_EDI);
3531 if (cfg->used_int_regs & (1 << X86_ESI)) {
3532 x86_push_reg (code, X86_ESI);
3540 /* See mono_emit_stack_alloc */
3541 #ifdef PLATFORM_WIN32
3542 guint32 remaining_size = alloc_size;
3543 while (remaining_size >= 0x1000) {
3544 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
3545 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
3546 remaining_size -= 0x1000;
3549 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
3551 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
3555 /* compute max_offset in order to use short forward jumps */
3557 if (cfg->opt & MONO_OPT_BRANCH) {
3558 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
3559 MonoInst *ins = bb->code;
3560 bb->max_offset = max_offset;
3562 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
3564 /* max alignment for loops */
3565 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
3566 max_offset += LOOP_ALIGNMENT;
3569 if (ins->opcode == OP_LABEL)
3570 ins->inst_c1 = max_offset;
3572 max_offset += ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
3578 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3579 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
3581 /* load arguments allocated to register from the stack */
3582 sig = method->signature;
3585 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3586 inst = cfg->varinfo [pos];
3587 if (inst->opcode == OP_REGVAR) {
3588 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
3589 if (cfg->verbose_level > 2)
3590 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
3595 cfg->code_len = code - cfg->native_code;
3601 mono_arch_emit_epilog (MonoCompile *cfg)
3603 MonoJumpInfo *patch_info;
3604 MonoMethod *method = cfg->method;
3605 MonoMethodSignature *sig = method->signature;
3607 guint32 stack_to_pop;
3610 code = cfg->native_code + cfg->code_len;
3612 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3613 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
3615 /* the code restoring the registers must be kept in sync with CEE_JMP */
3618 if (method->save_lmf) {
3619 gint32 prev_lmf_reg;
3621 /* Find a spare register */
3622 switch (sig->ret->type) {
3625 prev_lmf_reg = X86_EDI;
3626 cfg->used_int_regs |= (1 << X86_EDI);
3629 prev_lmf_reg = X86_EDX;
3633 /* reg = previous_lmf */
3634 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, -32, 4);
3637 x86_mov_reg_membase (code, X86_ECX, X86_EBP, -28, 4);
3639 /* *(lmf) = previous_lmf */
3640 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
3642 /* restore caller saved regs */
3643 if (cfg->used_int_regs & (1 << X86_EBX)) {
3644 x86_mov_reg_membase (code, X86_EBX, X86_EBP, -20, 4);
3647 if (cfg->used_int_regs & (1 << X86_EDI)) {
3648 x86_mov_reg_membase (code, X86_EDI, X86_EBP, -16, 4);
3650 if (cfg->used_int_regs & (1 << X86_ESI)) {
3651 x86_mov_reg_membase (code, X86_ESI, X86_EBP, -12, 4);
3654 /* EBP is restored by LEAVE */
3656 if (cfg->used_int_regs & (1 << X86_EBX)) {
3659 if (cfg->used_int_regs & (1 << X86_EDI)) {
3662 if (cfg->used_int_regs & (1 << X86_ESI)) {
3667 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
3669 if (cfg->used_int_regs & (1 << X86_ESI)) {
3670 x86_pop_reg (code, X86_ESI);
3672 if (cfg->used_int_regs & (1 << X86_EDI)) {
3673 x86_pop_reg (code, X86_EDI);
3675 if (cfg->used_int_regs & (1 << X86_EBX)) {
3676 x86_pop_reg (code, X86_EBX);
3682 if (CALLCONV_IS_STDCALL (sig->call_convention)) {
3683 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
3685 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
3686 } else if (MONO_TYPE_ISSTRUCT (cfg->method->signature->ret))
3692 x86_ret_imm (code, stack_to_pop);
3696 /* add code to raise exceptions */
3697 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
3698 switch (patch_info->type) {
3699 case MONO_PATCH_INFO_EXC:
3700 x86_patch (patch_info->ip.i + cfg->native_code, code);
3701 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC_NAME, patch_info->data.target);
3702 x86_push_imm (code, patch_info->data.target);
3703 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_METHOD_REL, (gpointer)patch_info->ip.i);
3704 x86_push_imm (code, patch_info->ip.i + cfg->native_code);
3705 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
3706 patch_info->data.name = "mono_arch_throw_exception_by_name";
3707 patch_info->ip.i = code - cfg->native_code;
3708 x86_jump_code (code, 0);
3716 cfg->code_len = code - cfg->native_code;
3718 g_assert (cfg->code_len < cfg->code_size);
3723 mono_arch_flush_icache (guint8 *code, gint size)
3729 mono_arch_flush_register_windows (void)
3734 * Support for fast access to the thread-local lmf structure using the GS
3735 * segment register on NPTL + kernel 2.6.x.
3738 static gboolean tls_offset_inited = FALSE;
3740 /* code should be simply return <tls var>; */
3741 static int read_tls_offset_from_method (void* method)
3743 guint8* code = (guint8*) method;
3745 * Determine the offset of the variable inside the TLS structures
3746 * by disassembling the function.
3754 * mov eax, DWORD PTR [eax+<offset>]
3757 (code [0] == 0x55) && (code [1] == 0x89) && (code [2] == 0xe5) &&
3758 (code [3] == 0x65) && (code [4] == 0xa1) && (code [5] == 0x00) &&
3759 (code [6] == 0x00) && (code [7] == 0x00) && (code [8] == 0x00) &&
3760 (code [9] == 0x8b) && (code [10] == 0x80)) {
3761 return *(int*)&(code [11]);
3768 * mov eax, gs:<offset>
3771 (code [0] == 0x55) && (code [1] == 0x89) && (code [2] == 0xe5) &&
3772 (code [3] == 0x65) && (code [4] == 0xa1)) {
3773 return *(int*)&(code [5]);
3776 /* 3.2.2 with -march=athlon
3779 * mov eax, gs:<offset>
3783 (code [0] == 0x55) && (code [1] == 0x65) && (code [2] == 0xa1)) {
3784 return *(int*)&(code [3]);
3790 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
3792 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3793 pthread_t self = pthread_self();
3794 pthread_attr_t attr;
3795 void *staddr = NULL;
3797 struct sigaltstack sa;
3800 if (!tls_offset_inited) {
3801 tls_offset_inited = TRUE;
3802 if (getenv ("MONO_NPTL")) {
3803 lmf_tls_offset = read_tls_offset_from_method (mono_get_lmf_addr);
3804 appdomain_tls_offset = read_tls_offset_from_method (mono_domain_get);
3805 thread_tls_offset = read_tls_offset_from_method (mono_thread_current);
3809 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3811 /* Determine stack boundaries */
3812 if (!mono_running_on_valgrind ()) {
3813 #ifdef HAVE_PTHREAD_GETATTR_NP
3814 pthread_getattr_np( self, &attr );
3816 #ifdef HAVE_PTHREAD_ATTR_GET_NP
3817 pthread_attr_get_np( self, &attr );
3819 pthread_attr_init( &attr );
3820 pthread_attr_getstacksize( &attr, &stsize );
3822 #error "Not implemented"
3826 pthread_attr_getstack( &attr, &staddr, &stsize );
3831 * staddr seems to be wrong for the main thread, so we keep the value in
3834 tls->stack_size = stsize;
3836 /* Setup an alternate signal stack */
3837 tls->signal_stack = g_malloc (SIGNAL_STACK_SIZE);
3838 tls->signal_stack_size = SIGNAL_STACK_SIZE;
3840 sa.ss_sp = tls->signal_stack;
3841 sa.ss_size = SIGNAL_STACK_SIZE;
3842 sa.ss_flags = SS_ONSTACK;
3843 sigaltstack (&sa, NULL);
3848 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
3850 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3851 struct sigaltstack sa;
3853 sa.ss_sp = tls->signal_stack;
3854 sa.ss_size = SIGNAL_STACK_SIZE;
3855 sa.ss_flags = SS_DISABLE;
3856 sigaltstack (&sa, NULL);
3858 if (tls->signal_stack)
3859 g_free (tls->signal_stack);
3864 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
3867 /* add the this argument */
3868 if (this_reg != -1) {
3870 MONO_INST_NEW (cfg, this, OP_OUTARG);
3871 this->type = this_type;
3872 this->sreg1 = this_reg;
3873 mono_bblock_add_inst (cfg->cbb, this);
3878 MONO_INST_NEW (cfg, vtarg, OP_OUTARG);
3879 vtarg->type = STACK_MP;
3880 vtarg->sreg1 = vt_reg;
3881 mono_bblock_add_inst (cfg->cbb, vtarg);
3887 mono_arch_get_opcode_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
3889 if (cmethod->klass == mono_defaults.math_class) {
3890 if (strcmp (cmethod->name, "Sin") == 0)
3892 else if (strcmp (cmethod->name, "Cos") == 0)
3894 else if (strcmp (cmethod->name, "Tan") == 0)
3896 else if (strcmp (cmethod->name, "Atan") == 0)
3898 else if (strcmp (cmethod->name, "Sqrt") == 0)
3900 else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8)
3903 /* OP_FREM is not IEEE compatible */
3904 else if (strcmp (cmethod->name, "IEEERemainder") == 0)
3917 mono_arch_print_tree (MonoInst *tree, int arity)
3922 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
3926 if (appdomain_tls_offset == -1)
3929 MONO_INST_NEW (cfg, ins, OP_X86_TLS_GET);
3930 ins->inst_offset = appdomain_tls_offset;
3934 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
3938 if (thread_tls_offset == -1)
3941 MONO_INST_NEW (cfg, ins, OP_X86_TLS_GET);
3942 ins->inst_offset = thread_tls_offset;