2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * (C) 2003 Ximian, Inc.
15 #include <mono/metadata/appdomain.h>
16 #include <mono/metadata/debug-helpers.h>
17 #include <mono/metadata/profiler-private.h>
18 #include <mono/utils/mono-math.h>
23 #include "cpu-pentium.h"
25 static gint lmf_tls_offset = -1;
28 /* Under windows, the default pinvoke calling convention is stdcall */
29 #define CALLCONV_IS_STDCALL(call_conv) (((call_conv) == MONO_CALL_STDCALL) || ((call_conv) == MONO_CALL_DEFAULT))
31 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
34 #define SIGNAL_STACK_SIZE (64 * 1024)
37 mono_arch_regname (int reg) {
39 case X86_EAX: return "%eax";
40 case X86_EBX: return "%ebx";
41 case X86_ECX: return "%ecx";
42 case X86_EDX: return "%edx";
43 case X86_ESP: return "%esp"; case X86_EBP: return "%ebp";
44 case X86_EDI: return "%edi";
45 case X86_ESI: return "%esi";
51 * mono_arch_get_argument_info:
52 * @csig: a method signature
53 * @param_count: the number of parameters to consider
54 * @arg_info: an array to store the result infos
56 * Gathers information on parameters such as size, alignment and
57 * padding. arg_info should be large enought to hold param_count + 1 entries.
59 * Returns the size of the activation frame.
62 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
64 int k, frame_size = 0;
68 if (MONO_TYPE_ISSTRUCT (csig->ret)) {
69 frame_size += sizeof (gpointer);
73 arg_info [0].offset = offset;
76 frame_size += sizeof (gpointer);
80 arg_info [0].size = frame_size;
82 for (k = 0; k < param_count; k++) {
85 size = mono_type_native_stack_size (csig->params [k], &align);
87 size = mono_type_stack_size (csig->params [k], &align);
89 /* ignore alignment for now */
92 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
93 arg_info [k].pad = pad;
95 arg_info [k + 1].pad = 0;
96 arg_info [k + 1].size = size;
98 arg_info [k + 1].offset = offset;
102 align = MONO_ARCH_FRAME_ALIGNMENT;
103 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
104 arg_info [k].pad = pad;
109 static const guchar cpuid_impl [] = {
110 0x55, /* push %ebp */
111 0x89, 0xe5, /* mov %esp,%ebp */
112 0x53, /* push %ebx */
113 0x8b, 0x45, 0x08, /* mov 0x8(%ebp),%eax */
114 0x0f, 0xa2, /* cpuid */
115 0x50, /* push %eax */
116 0x8b, 0x45, 0x10, /* mov 0x10(%ebp),%eax */
117 0x89, 0x18, /* mov %ebx,(%eax) */
118 0x8b, 0x45, 0x14, /* mov 0x14(%ebp),%eax */
119 0x89, 0x08, /* mov %ecx,(%eax) */
120 0x8b, 0x45, 0x18, /* mov 0x18(%ebp),%eax */
121 0x89, 0x10, /* mov %edx,(%eax) */
123 0x8b, 0x55, 0x0c, /* mov 0xc(%ebp),%edx */
124 0x89, 0x02, /* mov %eax,(%edx) */
130 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
133 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
136 __asm__ __volatile__ (
139 "movl %%eax, %%edx\n"
140 "xorl $0x200000, %%eax\n"
145 "xorl %%edx, %%eax\n"
146 "andl $0x200000, %%eax\n"
154 CpuidFunc func = (CpuidFunc)cpuid_impl;
155 func (id, p_eax, p_ebx, p_ecx, p_edx);
157 * We use this approach because of issues with gcc and pic code, see:
158 * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
159 __asm__ __volatile__ ("cpuid"
160 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
169 * Initialize the cpu to execute managed code.
172 mono_arch_cpu_init (void)
176 /* spec compliance requires running with double precision */
177 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
178 fpcw &= ~X86_FPCW_PRECC_MASK;
179 fpcw |= X86_FPCW_PREC_DOUBLE;
180 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
181 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
186 * This function returns the optimizations supported on this cpu.
189 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
191 int eax, ebx, ecx, edx;
195 /* Feature Flags function, flags returned in EDX. */
196 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
197 if (edx & (1 << 15)) {
198 opts |= MONO_OPT_CMOV;
200 opts |= MONO_OPT_FCMOV;
202 *exclude_mask |= MONO_OPT_FCMOV;
204 *exclude_mask |= MONO_OPT_CMOV;
210 is_regsize_var (MonoType *t) {
220 case MONO_TYPE_OBJECT:
221 case MONO_TYPE_STRING:
222 case MONO_TYPE_CLASS:
223 case MONO_TYPE_SZARRAY:
224 case MONO_TYPE_ARRAY:
226 case MONO_TYPE_VALUETYPE:
227 if (t->data.klass->enumtype)
228 return is_regsize_var (t->data.klass->enum_basetype);
235 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
240 for (i = 0; i < cfg->num_varinfo; i++) {
241 MonoInst *ins = cfg->varinfo [i];
242 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
245 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
248 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
249 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
252 /* we dont allocate I1 to registers because there is no simply way to sign extend
253 * 8bit quantities in caller saved registers on x86 */
254 if (is_regsize_var (ins->inst_vtype) || (ins->inst_vtype->type == MONO_TYPE_BOOLEAN) ||
255 (ins->inst_vtype->type == MONO_TYPE_U1) || (ins->inst_vtype->type == MONO_TYPE_U2)||
256 (ins->inst_vtype->type == MONO_TYPE_I2) || (ins->inst_vtype->type == MONO_TYPE_CHAR)) {
257 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
258 g_assert (i == vmv->idx);
259 vars = g_list_prepend (vars, vmv);
263 vars = mono_varlist_sort (cfg, vars, 0);
269 mono_arch_get_global_int_regs (MonoCompile *cfg)
273 /* we can use 3 registers for global allocation */
274 regs = g_list_prepend (regs, (gpointer)X86_EBX);
275 regs = g_list_prepend (regs, (gpointer)X86_ESI);
276 regs = g_list_prepend (regs, (gpointer)X86_EDI);
282 * mono_arch_regalloc_cost:
284 * Return the cost, in number of memory references, of the action of
285 * allocating the variable VMV into a register during global register
289 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
291 MonoInst *ins = cfg->varinfo [vmv->idx];
293 if (cfg->method->save_lmf)
294 /* The register is already saved */
295 return (ins->opcode == OP_ARG) ? 1 : 0;
297 /* push+pop+possible load if it is an argument */
298 return (ins->opcode == OP_ARG) ? 3 : 2;
302 * Set var information according to the calling convention. X86 version.
303 * The locals var stuff should most likely be split in another method.
306 mono_arch_allocate_vars (MonoCompile *m)
308 MonoMethodSignature *sig;
309 MonoMethodHeader *header;
311 int i, offset, size, align, curinst;
313 header = ((MonoMethodNormal *)m->method)->header;
315 sig = m->method->signature;
319 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
320 m->ret->opcode = OP_REGOFFSET;
321 m->ret->inst_basereg = X86_EBP;
322 m->ret->inst_offset = offset;
323 offset += sizeof (gpointer);
325 /* FIXME: handle long and FP values */
326 switch (sig->ret->type) {
330 m->ret->opcode = OP_REGVAR;
331 m->ret->inst_c0 = X86_EAX;
336 inst = m->varinfo [curinst];
337 if (inst->opcode != OP_REGVAR) {
338 inst->opcode = OP_REGOFFSET;
339 inst->inst_basereg = X86_EBP;
341 inst->inst_offset = offset;
342 offset += sizeof (gpointer);
346 if (sig->call_convention == MONO_CALL_VARARG) {
347 m->sig_cookie = offset;
348 offset += sizeof (gpointer);
351 for (i = 0; i < sig->param_count; ++i) {
352 inst = m->varinfo [curinst];
353 if (inst->opcode != OP_REGVAR) {
354 inst->opcode = OP_REGOFFSET;
355 inst->inst_basereg = X86_EBP;
357 inst->inst_offset = offset;
358 size = mono_type_size (sig->params [i], &align);
367 /* reserve space to save LMF and caller saved registers */
369 if (m->method->save_lmf) {
370 offset += sizeof (MonoLMF);
372 if (m->used_int_regs & (1 << X86_EBX)) {
376 if (m->used_int_regs & (1 << X86_EDI)) {
380 if (m->used_int_regs & (1 << X86_ESI)) {
385 for (i = curinst; i < m->num_varinfo; ++i) {
386 inst = m->varinfo [i];
388 if ((inst->flags & MONO_INST_IS_DEAD) || inst->opcode == OP_REGVAR)
391 /* inst->unused indicates native sized value types, this is used by the
392 * pinvoke wrappers when they call functions returning structure */
393 if (inst->unused && MONO_TYPE_ISSTRUCT (inst->inst_vtype) && inst->inst_vtype->type != MONO_TYPE_TYPEDBYREF)
394 size = mono_class_native_size (inst->inst_vtype->data.klass, &align);
396 size = mono_type_size (inst->inst_vtype, &align);
400 offset &= ~(align - 1);
401 inst->opcode = OP_REGOFFSET;
402 inst->inst_basereg = X86_EBP;
403 inst->inst_offset = -offset;
404 //g_print ("allocating local %d to %d\n", i, -offset);
406 offset += (MONO_ARCH_FRAME_ALIGNMENT - 1);
407 offset &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
410 m->stack_offset = -offset;
413 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
414 * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
418 * take the arguments and generate the arch-specific
419 * instructions to properly call the function in call.
420 * This includes pushing, moving arguments to the right register
422 * Issue: who does the spilling if needed, and when?
425 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
427 MonoMethodSignature *sig;
428 int i, n, stack_size, type;
432 /* add the vararg cookie before the non-implicit args */
433 if (call->signature->call_convention == MONO_CALL_VARARG) {
435 /* FIXME: Add support for signature tokens to AOT */
436 cfg->disable_aot = TRUE;
437 MONO_INST_NEW (cfg, arg, OP_OUTARG);
438 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
439 sig_arg->inst_p0 = call->signature;
440 arg->inst_left = sig_arg;
441 arg->type = STACK_PTR;
442 /* prepend, so they get reversed */
443 arg->next = call->out_args;
444 call->out_args = arg;
445 stack_size += sizeof (gpointer);
447 sig = call->signature;
448 n = sig->param_count + sig->hasthis;
450 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret))
451 stack_size += sizeof (gpointer);
452 for (i = 0; i < n; ++i) {
453 if (is_virtual && i == 0) {
454 /* the argument will be attached to the call instrucion */
458 MONO_INST_NEW (cfg, arg, OP_OUTARG);
460 arg->cil_code = in->cil_code;
462 arg->type = in->type;
463 /* prepend, so they get reversed */
464 arg->next = call->out_args;
465 call->out_args = arg;
466 if (i >= sig->hasthis) {
467 ptype = sig->params [i - sig->hasthis];
473 /* FIXME: validate arguments... */
477 case MONO_TYPE_BOOLEAN:
485 case MONO_TYPE_STRING:
486 case MONO_TYPE_CLASS:
487 case MONO_TYPE_OBJECT:
489 case MONO_TYPE_FNPTR:
490 case MONO_TYPE_ARRAY:
491 case MONO_TYPE_SZARRAY:
500 arg->opcode = OP_OUTARG_R4;
504 arg->opcode = OP_OUTARG_R8;
506 case MONO_TYPE_VALUETYPE:
507 if (MONO_TYPE_ISSTRUCT (ptype)) {
510 size = mono_type_native_stack_size (&in->klass->byval_arg, NULL);
512 size = mono_type_stack_size (&in->klass->byval_arg, NULL);
515 arg->opcode = OP_OUTARG_VT;
516 arg->klass = in->klass;
517 arg->unused = sig->pinvoke;
518 arg->inst_imm = size;
520 type = ptype->data.klass->enum_basetype->type;
524 case MONO_TYPE_TYPEDBYREF:
525 stack_size += sizeof (MonoTypedRef);
526 arg->opcode = OP_OUTARG_VT;
527 arg->klass = in->klass;
528 arg->unused = sig->pinvoke;
529 arg->inst_imm = sizeof (MonoTypedRef);
531 case MONO_TYPE_GENERICINST:
532 type = ptype->data.generic_inst->generic_type->type;
536 g_error ("unknown type 0x%02x in mono_arch_call_opcode\n", type);
539 /* the this argument */
544 /* if the function returns a struct, the called method already does a ret $0x4 */
545 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret))
547 call->stack_usage = stack_size;
549 * should set more info in call, such as the stack space
550 * used by the args that needs to be added back to esp
557 * Allow tracing to work with this interface (with an optional argument)
561 * This may be needed on some archs or for debugging support.
564 mono_arch_instrument_mem_needs (MonoMethod *method, int *stack, int *code)
566 /* no stack room needed now (may be needed for FASTCALL-trace support) */
568 /* split prolog-epilog requirements? */
569 *code = 50; /* max bytes needed: check this number */
573 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
577 /* if some args are passed in registers, we need to save them here */
578 x86_push_reg (code, X86_EBP);
579 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
580 x86_push_imm (code, cfg->method);
581 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
582 x86_call_code (code, 0);
583 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
597 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
600 int arg_size = 0, save_mode = SAVE_NONE;
601 MonoMethod *method = cfg->method;
602 int rtype = method->signature->ret->type;
607 /* special case string .ctor icall */
608 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
609 save_mode = SAVE_EAX;
611 save_mode = SAVE_NONE;
615 save_mode = SAVE_EAX_EDX;
621 case MONO_TYPE_VALUETYPE:
622 if (method->signature->ret->data.klass->enumtype) {
623 rtype = method->signature->ret->data.klass->enum_basetype->type;
626 save_mode = SAVE_STRUCT;
629 save_mode = SAVE_EAX;
635 x86_push_reg (code, X86_EDX);
636 x86_push_reg (code, X86_EAX);
637 if (enable_arguments) {
638 x86_push_reg (code, X86_EDX);
639 x86_push_reg (code, X86_EAX);
644 x86_push_reg (code, X86_EAX);
645 if (enable_arguments) {
646 x86_push_reg (code, X86_EAX);
651 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
652 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
653 if (enable_arguments) {
654 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
655 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
660 if (enable_arguments) {
661 x86_push_membase (code, X86_EBP, 8);
671 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
672 x86_push_imm (code, method);
673 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
674 x86_call_code (code, 0);
675 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
679 x86_pop_reg (code, X86_EAX);
680 x86_pop_reg (code, X86_EDX);
683 x86_pop_reg (code, X86_EAX);
686 x86_fld_membase (code, X86_ESP, 0, TRUE);
687 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
697 #define EMIT_COND_BRANCH(ins,cond,sign) \
698 if (ins->flags & MONO_INST_BRLABEL) { \
699 if (ins->inst_i0->inst_c0) { \
700 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
702 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
703 if ((cfg->opt & MONO_OPT_BRANCH) && \
704 x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
705 x86_branch8 (code, cond, 0, sign); \
707 x86_branch32 (code, cond, 0, sign); \
710 if (ins->inst_true_bb->native_offset) { \
711 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
713 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
714 if ((cfg->opt & MONO_OPT_BRANCH) && \
715 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
716 x86_branch8 (code, cond, 0, sign); \
718 x86_branch32 (code, cond, 0, sign); \
722 /* emit an exception if condition is fail */
723 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
725 mono_add_patch_info (cfg, code - cfg->native_code, \
726 MONO_PATCH_INFO_EXC, exc_name); \
727 x86_branch32 (code, cond, 0, signed); \
730 #define EMIT_FPCOMPARE(code) do { \
735 /* FIXME: Add more instructions */
736 #define INST_IGNORES_CFLAGS(ins) (((ins)->opcode == CEE_BR) || ((ins)->opcode == OP_STORE_MEMBASE_IMM))
739 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
741 MonoInst *ins, *last_ins = NULL;
746 switch (ins->opcode) {
748 /* reg = 0 -> XOR (reg, reg) */
749 /* XOR sets cflags on x86, so we cant do it always */
750 if (ins->inst_c0 == 0 && ins->next && INST_IGNORES_CFLAGS (ins->next)) {
751 ins->opcode = CEE_XOR;
752 ins->sreg1 = ins->dreg;
753 ins->sreg2 = ins->dreg;
757 /* remove unnecessary multiplication with 1 */
758 if (ins->inst_imm == 1) {
759 if (ins->dreg != ins->sreg1) {
760 ins->opcode = OP_MOVE;
762 last_ins->next = ins->next;
769 /* OP_COMPARE_IMM (reg, 0)
771 * OP_X86_TEST_NULL (reg)
773 if (ins->inst_imm == 0 && ins->next &&
774 (ins->next->opcode == CEE_BEQ || ins->next->opcode == CEE_BNE_UN ||
775 ins->next->opcode == OP_CEQ)) {
776 ins->opcode = OP_X86_TEST_NULL;
779 case OP_X86_COMPARE_MEMBASE_IMM:
781 * OP_STORE_MEMBASE_REG reg, offset(basereg)
782 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
784 * OP_STORE_MEMBASE_REG reg, offset(basereg)
785 * OP_COMPARE_IMM reg, imm
787 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
789 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
790 ins->inst_basereg == last_ins->inst_destbasereg &&
791 ins->inst_offset == last_ins->inst_offset) {
792 ins->opcode = OP_COMPARE_IMM;
793 ins->sreg1 = last_ins->sreg1;
795 /* check if we can remove cmp reg,0 with test null */
796 if (ins->inst_imm == 0 && ins->next &&
797 (ins->next->opcode == CEE_BEQ || ins->next->opcode == CEE_BNE_UN ||
798 ins->next->opcode == OP_CEQ)) {
799 ins->opcode = OP_X86_TEST_NULL;
804 case OP_LOAD_MEMBASE:
805 case OP_LOADI4_MEMBASE:
807 * Note: if reg1 = reg2 the load op is removed
809 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
810 * OP_LOAD_MEMBASE offset(basereg), reg2
812 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
815 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
816 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
817 ins->inst_basereg == last_ins->inst_destbasereg &&
818 ins->inst_offset == last_ins->inst_offset) {
819 if (ins->dreg == last_ins->sreg1) {
820 last_ins->next = ins->next;
824 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
825 ins->opcode = OP_MOVE;
826 ins->sreg1 = last_ins->sreg1;
830 * Note: reg1 must be different from the basereg in the second load
831 * Note: if reg1 = reg2 is equal then second load is removed
833 * OP_LOAD_MEMBASE offset(basereg), reg1
834 * OP_LOAD_MEMBASE offset(basereg), reg2
836 * OP_LOAD_MEMBASE offset(basereg), reg1
839 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
840 || last_ins->opcode == OP_LOAD_MEMBASE) &&
841 ins->inst_basereg != last_ins->dreg &&
842 ins->inst_basereg == last_ins->inst_basereg &&
843 ins->inst_offset == last_ins->inst_offset) {
845 if (ins->dreg == last_ins->dreg) {
846 last_ins->next = ins->next;
850 ins->opcode = OP_MOVE;
851 ins->sreg1 = last_ins->dreg;
854 //g_assert_not_reached ();
858 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
859 * OP_LOAD_MEMBASE offset(basereg), reg
861 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
864 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
865 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
866 ins->inst_basereg == last_ins->inst_destbasereg &&
867 ins->inst_offset == last_ins->inst_offset) {
868 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
869 ins->opcode = OP_ICONST;
870 ins->inst_c0 = last_ins->inst_imm;
871 g_assert_not_reached (); // check this rule
875 case OP_LOADU1_MEMBASE:
876 case OP_LOADI1_MEMBASE:
878 * Note: if reg1 = reg2 the load op is removed
880 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
881 * OP_LOAD_MEMBASE offset(basereg), reg2
883 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
886 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
887 ins->inst_basereg == last_ins->inst_destbasereg &&
888 ins->inst_offset == last_ins->inst_offset) {
889 if (ins->dreg == last_ins->sreg1) {
890 last_ins->next = ins->next;
894 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
895 ins->opcode = OP_MOVE;
896 ins->sreg1 = last_ins->sreg1;
900 case OP_LOADU2_MEMBASE:
901 case OP_LOADI2_MEMBASE:
903 * Note: if reg1 = reg2 the load op is removed
905 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
906 * OP_LOAD_MEMBASE offset(basereg), reg2
908 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
911 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
912 ins->inst_basereg == last_ins->inst_destbasereg &&
913 ins->inst_offset == last_ins->inst_offset) {
914 if (ins->dreg == last_ins->sreg1) {
915 last_ins->next = ins->next;
919 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
920 ins->opcode = OP_MOVE;
921 ins->sreg1 = last_ins->sreg1;
933 if (ins->dreg == ins->sreg1) {
935 last_ins->next = ins->next;
945 if (last_ins && last_ins->opcode == OP_MOVE &&
946 ins->sreg1 == last_ins->dreg &&
947 ins->dreg == last_ins->sreg1) {
948 last_ins->next = ins->next;
957 bb->last_ins = last_ins;
961 branch_cc_table [] = {
962 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
963 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
964 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
967 #define DEBUG(a) if (cfg->verbose_level > 1) a
971 * returns the offset used by spillvar. It allocates a new
972 * spill variable if necessary.
975 mono_spillvar_offset (MonoCompile *cfg, int spillvar)
977 MonoSpillInfo **si, *info;
980 si = &cfg->spill_info;
982 while (i <= spillvar) {
985 *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
987 cfg->stack_offset -= sizeof (gpointer);
988 info->offset = cfg->stack_offset;
992 return (*si)->offset;
998 g_assert_not_reached ();
1003 * returns the offset used by spillvar. It allocates a new
1004 * spill float variable if necessary.
1005 * (same as mono_spillvar_offset but for float)
1008 mono_spillvar_offset_float (MonoCompile *cfg, int spillvar)
1010 MonoSpillInfo **si, *info;
1013 si = &cfg->spill_info_float;
1015 while (i <= spillvar) {
1018 *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
1020 cfg->stack_offset -= sizeof (double);
1021 info->offset = cfg->stack_offset;
1025 return (*si)->offset;
1031 g_assert_not_reached ();
1036 * Creates a store for spilled floating point items
1039 create_spilled_store_float (MonoCompile *cfg, int spill, int reg, MonoInst *ins)
1042 MONO_INST_NEW (cfg, store, OP_STORER8_MEMBASE_REG);
1044 store->inst_destbasereg = X86_EBP;
1045 store->inst_offset = mono_spillvar_offset_float (cfg, spill);
1047 DEBUG (g_print ("SPILLED FLOAT STORE (%d at 0x%08x(%%sp)) (from %d)\n", spill, store->inst_offset, reg));
1052 * Creates a load for spilled floating point items
1055 create_spilled_load_float (MonoCompile *cfg, int spill, int reg, MonoInst *ins)
1058 MONO_INST_NEW (cfg, load, OP_LOADR8_SPILL_MEMBASE);
1060 load->inst_basereg = X86_EBP;
1061 load->inst_offset = mono_spillvar_offset_float (cfg, spill);
1063 DEBUG (g_print ("SPILLED FLOAT LOAD (%d at 0x%08x(%%sp)) (from %d)\n", spill, load->inst_offset, reg));
1067 #define reg_is_freeable(r) ((r) >= 0 && (r) <= 7 && X86_IS_CALLEE ((r)))
1074 int flags; /* used to track fp spill/load */
1077 static const char*const * ins_spec = pentium_desc;
1080 print_ins (int i, MonoInst *ins)
1082 const char *spec = ins_spec [ins->opcode];
1083 g_print ("\t%-2d %s", i, mono_inst_name (ins->opcode));
1084 if (spec [MONO_INST_DEST]) {
1085 if (ins->dreg >= MONO_MAX_IREGS)
1086 g_print (" R%d <-", ins->dreg);
1088 g_print (" %s <-", mono_arch_regname (ins->dreg));
1090 if (spec [MONO_INST_SRC1]) {
1091 if (ins->sreg1 >= MONO_MAX_IREGS)
1092 g_print (" R%d", ins->sreg1);
1094 g_print (" %s", mono_arch_regname (ins->sreg1));
1096 if (spec [MONO_INST_SRC2]) {
1097 if (ins->sreg2 >= MONO_MAX_IREGS)
1098 g_print (" R%d", ins->sreg2);
1100 g_print (" %s", mono_arch_regname (ins->sreg2));
1102 if (spec [MONO_INST_CLOB])
1103 g_print (" clobbers: %c", spec [MONO_INST_CLOB]);
1108 print_regtrack (RegTrack *t, int num)
1114 for (i = 0; i < num; ++i) {
1117 if (i >= MONO_MAX_IREGS) {
1118 g_snprintf (buf, sizeof(buf), "R%d", i);
1121 r = mono_arch_regname (i);
1122 g_print ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].last_use);
1126 typedef struct InstList InstList;
1134 static inline InstList*
1135 inst_list_prepend (MonoMemPool *pool, InstList *list, MonoInst *data)
1137 InstList *item = mono_mempool_alloc (pool, sizeof (InstList));
1147 * Force the spilling of the variable in the symbolic register 'reg'.
1150 get_register_force_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, int reg)
1155 sel = cfg->rs->iassign [reg];
1156 /*i = cfg->rs->isymbolic [sel];
1157 g_assert (i == reg);*/
1159 spill = ++cfg->spill_count;
1160 cfg->rs->iassign [i] = -spill - 1;
1161 mono_regstate_free_int (cfg->rs, sel);
1162 /* we need to create a spill var and insert a load to sel after the current instruction */
1163 MONO_INST_NEW (cfg, load, OP_LOAD_MEMBASE);
1165 load->inst_basereg = X86_EBP;
1166 load->inst_offset = mono_spillvar_offset (cfg, spill);
1168 while (ins->next != item->prev->data)
1171 load->next = ins->next;
1173 DEBUG (g_print ("SPILLED LOAD (%d at 0x%08x(%%ebp)) R%d (freed %s)\n", spill, load->inst_offset, i, mono_arch_regname (sel)));
1174 i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
1175 g_assert (i == sel);
1181 get_register_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, guint32 regmask, int reg)
1186 DEBUG (g_print ("\tstart regmask to assign R%d: 0x%08x (R%d <- R%d R%d)\n", reg, regmask, ins->dreg, ins->sreg1, ins->sreg2));
1187 /* exclude the registers in the current instruction */
1188 if (reg != ins->sreg1 && (reg_is_freeable (ins->sreg1) || (ins->sreg1 >= MONO_MAX_IREGS && cfg->rs->iassign [ins->sreg1] >= 0))) {
1189 if (ins->sreg1 >= MONO_MAX_IREGS)
1190 regmask &= ~ (1 << cfg->rs->iassign [ins->sreg1]);
1192 regmask &= ~ (1 << ins->sreg1);
1193 DEBUG (g_print ("\t\texcluding sreg1 %s\n", mono_arch_regname (ins->sreg1)));
1195 if (reg != ins->sreg2 && (reg_is_freeable (ins->sreg2) || (ins->sreg2 >= MONO_MAX_IREGS && cfg->rs->iassign [ins->sreg2] >= 0))) {
1196 if (ins->sreg2 >= MONO_MAX_IREGS)
1197 regmask &= ~ (1 << cfg->rs->iassign [ins->sreg2]);
1199 regmask &= ~ (1 << ins->sreg2);
1200 DEBUG (g_print ("\t\texcluding sreg2 %s %d\n", mono_arch_regname (ins->sreg2), ins->sreg2));
1202 if (reg != ins->dreg && reg_is_freeable (ins->dreg)) {
1203 regmask &= ~ (1 << ins->dreg);
1204 DEBUG (g_print ("\t\texcluding dreg %s\n", mono_arch_regname (ins->dreg)));
1207 DEBUG (g_print ("\t\tavailable regmask: 0x%08x\n", regmask));
1208 g_assert (regmask); /* need at least a register we can free */
1210 /* we should track prev_use and spill the register that's farther */
1211 for (i = 0; i < MONO_MAX_IREGS; ++i) {
1212 if (regmask & (1 << i)) {
1214 DEBUG (g_print ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), cfg->rs->iassign [sel]));
1218 i = cfg->rs->isymbolic [sel];
1219 spill = ++cfg->spill_count;
1220 cfg->rs->iassign [i] = -spill - 1;
1221 mono_regstate_free_int (cfg->rs, sel);
1222 /* we need to create a spill var and insert a load to sel after the current instruction */
1223 MONO_INST_NEW (cfg, load, OP_LOAD_MEMBASE);
1225 load->inst_basereg = X86_EBP;
1226 load->inst_offset = mono_spillvar_offset (cfg, spill);
1228 while (ins->next != item->prev->data)
1231 load->next = ins->next;
1233 DEBUG (g_print ("\tSPILLED LOAD (%d at 0x%08x(%%ebp)) R%d (freed %s)\n", spill, load->inst_offset, i, mono_arch_regname (sel)));
1234 i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
1235 g_assert (i == sel);
1241 create_copy_ins (MonoCompile *cfg, int dest, int src, MonoInst *ins)
1244 MONO_INST_NEW (cfg, copy, OP_MOVE);
1248 copy->next = ins->next;
1251 DEBUG (g_print ("\tforced copy from %s to %s\n", mono_arch_regname (src), mono_arch_regname (dest)));
1256 create_spilled_store (MonoCompile *cfg, int spill, int reg, int prev_reg, MonoInst *ins)
1259 MONO_INST_NEW (cfg, store, OP_STORE_MEMBASE_REG);
1261 store->inst_destbasereg = X86_EBP;
1262 store->inst_offset = mono_spillvar_offset (cfg, spill);
1264 store->next = ins->next;
1267 DEBUG (g_print ("\tSPILLED STORE (%d at 0x%08x(%%ebp)) R%d (from %s)\n", spill, store->inst_offset, prev_reg, mono_arch_regname (reg)));
1272 insert_before_ins (MonoInst *ins, InstList *item, MonoInst* to_insert)
1276 prev = item->next->data;
1278 while (prev->next != ins)
1280 to_insert->next = ins;
1281 prev->next = to_insert;
1283 to_insert->next = ins;
1286 * needed otherwise in the next instruction we can add an ins to the
1287 * end and that would get past this instruction.
1289 item->data = to_insert;
1295 alloc_int_reg (MonoCompile *cfg, InstList *curinst, MonoInst *ins, int sym_reg, guint32 allow_mask)
1297 int val = cfg->rs->iassign [sym_reg];
1301 /* the register gets spilled after this inst */
1304 val = mono_regstate_alloc_int (cfg->rs, allow_mask);
1306 val = get_register_spilling (cfg, curinst, ins, allow_mask, sym_reg);
1307 cfg->rs->iassign [sym_reg] = val;
1308 /* add option to store before the instruction for src registers */
1310 create_spilled_store (cfg, spill, val, sym_reg, ins);
1312 cfg->rs->isymbolic [val] = sym_reg;
1317 /* flags used in reginfo->flags */
1319 MONO_X86_FP_NEEDS_LOAD_SPILL = 1 << 0,
1320 MONO_X86_FP_NEEDS_SPILL = 1 << 1,
1321 MONO_X86_FP_NEEDS_LOAD = 1 << 2,
1322 MONO_X86_REG_NOT_ECX = 1 << 3,
1323 MONO_X86_REG_EAX = 1 << 4,
1324 MONO_X86_REG_EDX = 1 << 5,
1325 MONO_X86_REG_ECX = 1 << 6
1329 mono_x86_alloc_int_reg (MonoCompile *cfg, InstList *tmp, MonoInst *ins, guint32 dest_mask, int sym_reg, int flags)
1332 int test_mask = dest_mask;
1334 if (flags & MONO_X86_REG_EAX)
1335 test_mask &= (1 << X86_EAX);
1336 else if (flags & MONO_X86_REG_EDX)
1337 test_mask &= (1 << X86_EDX);
1338 else if (flags & MONO_X86_REG_ECX)
1339 test_mask &= (1 << X86_ECX);
1340 else if (flags & MONO_X86_REG_NOT_ECX)
1341 test_mask &= ~ (1 << X86_ECX);
1343 val = mono_regstate_alloc_int (cfg->rs, test_mask);
1344 if (val >= 0 && test_mask != dest_mask)
1345 DEBUG(g_print ("\tUsed flag to allocate reg %s for R%u\n", mono_arch_regname (val), sym_reg));
1347 if (val < 0 && (flags & MONO_X86_REG_NOT_ECX)) {
1348 DEBUG(g_print ("\tFailed to allocate flag suggested mask (%u) but exluding ECX\n", test_mask));
1349 val = mono_regstate_alloc_int (cfg->rs, (dest_mask & (~1 << X86_ECX)));
1353 val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1355 val = get_register_spilling (cfg, tmp, ins, dest_mask, sym_reg);
1362 /*#include "cprop.c"*/
1365 * Local register allocation.
1366 * We first scan the list of instructions and we save the liveness info of
1367 * each register (when the register is first used, when it's value is set etc.).
1368 * We also reverse the list of instructions (in the InstList list) because assigning
1369 * registers backwards allows for more tricks to be used.
1372 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1375 MonoRegState *rs = cfg->rs;
1376 int i, val, fpcount;
1377 RegTrack *reginfo, *reginfof;
1378 RegTrack *reginfo1, *reginfo2, *reginfod;
1379 InstList *tmp, *reversed = NULL;
1381 guint32 src1_mask, src2_mask, dest_mask;
1382 GList *fspill_list = NULL;
1387 rs->next_vireg = bb->max_ireg;
1388 rs->next_vfreg = bb->max_freg;
1389 mono_regstate_assign (rs);
1390 reginfo = g_malloc0 (sizeof (RegTrack) * rs->next_vireg);
1391 reginfof = g_malloc0 (sizeof (RegTrack) * rs->next_vfreg);
1392 rs->ifree_mask = X86_CALLEE_REGS;
1396 /*if (cfg->opt & MONO_OPT_COPYPROP)
1397 local_copy_prop (cfg, ins);*/
1401 DEBUG (g_print ("LOCAL regalloc: basic block: %d\n", bb->block_num));
1402 /* forward pass on the instructions to collect register liveness info */
1404 spec = ins_spec [ins->opcode];
1406 DEBUG (print_ins (i, ins));
1408 if (spec [MONO_INST_SRC1]) {
1409 if (spec [MONO_INST_SRC1] == 'f') {
1411 reginfo1 = reginfof;
1413 spill = g_list_first (fspill_list);
1414 if (spill && fpcount < MONO_MAX_FREGS) {
1415 reginfo1 [ins->sreg1].flags |= MONO_X86_FP_NEEDS_LOAD;
1416 fspill_list = g_list_remove (fspill_list, spill->data);
1422 reginfo1 [ins->sreg1].prev_use = reginfo1 [ins->sreg1].last_use;
1423 reginfo1 [ins->sreg1].last_use = i;
1424 if (spec [MONO_INST_SRC1] == 'L') {
1425 /* The virtual register is allocated sequentially */
1426 reginfo1 [ins->sreg1 + 1].prev_use = reginfo1 [ins->sreg1 + 1].last_use;
1427 reginfo1 [ins->sreg1 + 1].last_use = i;
1428 if (reginfo1 [ins->sreg1 + 1].born_in == 0 || reginfo1 [ins->sreg1 + 1].born_in > i)
1429 reginfo1 [ins->sreg1 + 1].born_in = i;
1431 reginfo1 [ins->sreg1].flags |= MONO_X86_REG_EAX;
1432 reginfo1 [ins->sreg1 + 1].flags |= MONO_X86_REG_EDX;
1437 if (spec [MONO_INST_SRC2]) {
1438 if (spec [MONO_INST_SRC2] == 'f') {
1440 reginfo2 = reginfof;
1441 spill = g_list_first (fspill_list);
1443 reginfo2 [ins->sreg2].flags |= MONO_X86_FP_NEEDS_LOAD;
1444 fspill_list = g_list_remove (fspill_list, spill->data);
1445 if (fpcount >= MONO_MAX_FREGS) {
1447 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1448 reginfo2 [ins->sreg2].flags |= MONO_X86_FP_NEEDS_LOAD_SPILL;
1455 reginfo2 [ins->sreg2].prev_use = reginfo2 [ins->sreg2].last_use;
1456 reginfo2 [ins->sreg2].last_use = i;
1457 if (spec [MONO_INST_SRC2] == 'L') {
1458 /* The virtual register is allocated sequentially */
1459 reginfo2 [ins->sreg2 + 1].prev_use = reginfo2 [ins->sreg2 + 1].last_use;
1460 reginfo2 [ins->sreg2 + 1].last_use = i;
1461 if (reginfo2 [ins->sreg2 + 1].born_in == 0 || reginfo2 [ins->sreg2 + 1].born_in > i)
1462 reginfo2 [ins->sreg2 + 1].born_in = i;
1464 if (spec [MONO_INST_CLOB] == 's') {
1465 reginfo2 [ins->sreg1].flags |= MONO_X86_REG_NOT_ECX;
1466 reginfo2 [ins->sreg2].flags |= MONO_X86_REG_ECX;
1471 if (spec [MONO_INST_DEST]) {
1472 if (spec [MONO_INST_DEST] == 'f') {
1473 reginfod = reginfof;
1474 if (fpcount >= MONO_MAX_FREGS) {
1475 reginfod [ins->dreg].flags |= MONO_X86_FP_NEEDS_SPILL;
1477 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1484 if (spec [MONO_INST_DEST] != 'b') /* it's not just a base register */
1485 reginfod [ins->dreg].killed_in = i;
1486 reginfod [ins->dreg].prev_use = reginfod [ins->dreg].last_use;
1487 reginfod [ins->dreg].last_use = i;
1488 if (reginfod [ins->dreg].born_in == 0 || reginfod [ins->dreg].born_in > i)
1489 reginfod [ins->dreg].born_in = i;
1490 if (spec [MONO_INST_DEST] == 'l' || spec [MONO_INST_DEST] == 'L') {
1491 /* The virtual register is allocated sequentially */
1492 reginfod [ins->dreg + 1].prev_use = reginfod [ins->dreg + 1].last_use;
1493 reginfod [ins->dreg + 1].last_use = i;
1494 if (reginfod [ins->dreg + 1].born_in == 0 || reginfod [ins->dreg + 1].born_in > i)
1495 reginfod [ins->dreg + 1].born_in = i;
1497 reginfod [ins->dreg].flags |= MONO_X86_REG_EAX;
1498 reginfod [ins->dreg + 1].flags |= MONO_X86_REG_EDX;
1504 reversed = inst_list_prepend (cfg->mempool, reversed, ins);
1509 // todo: check if we have anything left on fp stack, in verify mode?
1512 DEBUG (print_regtrack (reginfo, rs->next_vireg));
1513 DEBUG (print_regtrack (reginfof, rs->next_vfreg));
1516 int prev_dreg, prev_sreg1, prev_sreg2, clob_dreg;
1517 dest_mask = src1_mask = src2_mask = X86_CALLEE_REGS;
1520 spec = ins_spec [ins->opcode];
1523 DEBUG (g_print ("processing:"));
1524 DEBUG (print_ins (i, ins));
1525 if (spec [MONO_INST_CLOB] == 's') {
1526 if (rs->ifree_mask & (1 << X86_ECX)) {
1527 DEBUG (g_print ("\tshortcut assignment of R%d to ECX\n", ins->sreg2));
1528 rs->iassign [ins->sreg2] = X86_ECX;
1529 rs->isymbolic [X86_ECX] = ins->sreg2;
1530 ins->sreg2 = X86_ECX;
1531 rs->ifree_mask &= ~ (1 << X86_ECX);
1533 int need_ecx_spill = TRUE;
1535 * we first check if src1/dreg is already assigned a register
1536 * and then we force a spill of the var assigned to ECX.
1538 /* the destination register can't be ECX */
1539 dest_mask &= ~ (1 << X86_ECX);
1540 src1_mask &= ~ (1 << X86_ECX);
1541 val = rs->iassign [ins->dreg];
1543 * the destination register is already assigned to ECX:
1544 * we need to allocate another register for it and then
1545 * copy from this to ECX.
1547 if (val == X86_ECX && ins->dreg != ins->sreg2) {
1549 new_dest = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, ins->dreg, reginfo [ins->dreg].flags);
1550 g_assert (new_dest >= 0);
1551 DEBUG (g_print ("\tclob:s changing dreg R%d to %s from ECX\n", ins->dreg, mono_arch_regname (new_dest)));
1553 rs->isymbolic [new_dest] = ins->dreg;
1554 rs->iassign [ins->dreg] = new_dest;
1555 clob_dreg = ins->dreg;
1556 ins->dreg = new_dest;
1557 create_copy_ins (cfg, X86_ECX, new_dest, ins);
1558 need_ecx_spill = FALSE;
1559 /*DEBUG (g_print ("\tforced spill of R%d\n", ins->dreg));
1560 val = get_register_force_spilling (cfg, tmp, ins, ins->dreg);
1561 rs->iassign [ins->dreg] = val;
1562 rs->isymbolic [val] = prev_dreg;
1565 val = rs->iassign [ins->sreg1];
1566 if (val == X86_ECX) {
1567 g_assert_not_reached ();
1568 } else if (val >= 0) {
1570 * the first src reg was already assigned to a register,
1571 * we need to copy it to the dest register because the
1572 * shift instruction clobbers the first operand.
1574 MonoInst *copy = create_copy_ins (cfg, ins->dreg, val, NULL);
1575 DEBUG (g_print ("\tclob:s moved sreg1 from R%d to R%d\n", val, ins->dreg));
1576 insert_before_ins (ins, tmp, copy);
1578 val = rs->iassign [ins->sreg2];
1579 if (val >= 0 && val != X86_ECX) {
1580 MonoInst *move = create_copy_ins (cfg, X86_ECX, val, NULL);
1581 DEBUG (g_print ("\tmoved arg from R%d (%d) to ECX\n", val, ins->sreg2));
1583 g_assert_not_reached ();
1584 /* FIXME: where is move connected to the instruction list? */
1585 //tmp->prev->data->next = move;
1587 if (need_ecx_spill && !(rs->ifree_mask & (1 << X86_ECX))) {
1588 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [X86_ECX]));
1589 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_ECX]);
1590 mono_regstate_free_int (rs, X86_ECX);
1592 /* force-set sreg2 */
1593 rs->iassign [ins->sreg2] = X86_ECX;
1594 rs->isymbolic [X86_ECX] = ins->sreg2;
1595 ins->sreg2 = X86_ECX;
1596 rs->ifree_mask &= ~ (1 << X86_ECX);
1598 } else if (spec [MONO_INST_CLOB] == 'd') { /* division */
1599 int dest_reg = X86_EAX;
1600 int clob_reg = X86_EDX;
1601 if (spec [MONO_INST_DEST] == 'd') {
1602 dest_reg = X86_EDX; /* reminder */
1605 val = rs->iassign [ins->dreg];
1606 if (0 && val >= 0 && val != dest_reg && !(rs->ifree_mask & (1 << dest_reg))) {
1607 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [dest_reg]));
1608 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [dest_reg]);
1609 mono_regstate_free_int (rs, dest_reg);
1613 /* the register gets spilled after this inst */
1614 int spill = -val -1;
1615 dest_mask = 1 << clob_reg;
1616 prev_dreg = ins->dreg;
1617 val = mono_regstate_alloc_int (rs, dest_mask);
1619 val = get_register_spilling (cfg, tmp, ins, dest_mask, ins->dreg);
1620 rs->iassign [ins->dreg] = val;
1622 create_spilled_store (cfg, spill, val, prev_dreg, ins);
1623 DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_arch_regname (val), ins->dreg));
1624 rs->isymbolic [val] = prev_dreg;
1626 if (val != dest_reg) { /* force a copy */
1627 create_copy_ins (cfg, val, dest_reg, ins);
1630 DEBUG (g_print ("\tshortcut assignment of R%d to %s\n", ins->dreg, mono_arch_regname (dest_reg)));
1631 prev_dreg = ins->dreg;
1632 rs->iassign [ins->dreg] = dest_reg;
1633 rs->isymbolic [dest_reg] = ins->dreg;
1634 ins->dreg = dest_reg;
1635 rs->ifree_mask &= ~ (1 << dest_reg);
1638 //DEBUG (g_print ("dest reg in div assigned: %s\n", mono_arch_regname (val)));
1639 if (val != dest_reg) { /* force a copy */
1640 create_copy_ins (cfg, val, dest_reg, ins);
1641 if (!(rs->ifree_mask & (1 << dest_reg)) && rs->isymbolic [dest_reg] >= MONO_MAX_IREGS) {
1642 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [dest_reg]));
1643 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [dest_reg]);
1644 mono_regstate_free_int (rs, dest_reg);
1648 if (!(rs->ifree_mask & (1 << clob_reg)) && (clob_reg != val) && (rs->isymbolic [clob_reg] >= 8)) {
1649 DEBUG (g_print ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1650 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [clob_reg]);
1651 mono_regstate_free_int (rs, clob_reg);
1653 src1_mask = 1 << X86_EAX;
1654 src2_mask = 1 << X86_ECX;
1656 if (spec [MONO_INST_DEST] == 'l') {
1658 val = rs->iassign [ins->dreg];
1659 /* check special case when dreg have been moved from ecx (clob shift) */
1660 if (spec [MONO_INST_CLOB] == 's' && clob_dreg != -1)
1661 hreg = clob_dreg + 1;
1663 hreg = ins->dreg + 1;
1665 /* base prev_dreg on fixed hreg, handle clob case */
1668 if (val != rs->isymbolic [X86_EAX] && !(rs->ifree_mask & (1 << X86_EAX))) {
1669 DEBUG (g_print ("\t(long-low) forced spill of R%d\n", rs->isymbolic [X86_EAX]));
1670 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_EAX]);
1671 mono_regstate_free_int (rs, X86_EAX);
1673 if (hreg != rs->isymbolic [X86_EDX] && !(rs->ifree_mask & (1 << X86_EDX))) {
1674 DEBUG (g_print ("\t(long-high) forced spill of R%d\n", rs->isymbolic [X86_EDX]));
1675 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_EDX]);
1676 mono_regstate_free_int (rs, X86_EDX);
1681 if (spec [MONO_INST_DEST] == 'f') {
1682 if (reginfof [ins->dreg].flags & MONO_X86_FP_NEEDS_SPILL) {
1685 spill_node = g_list_first (fspill_list);
1686 g_assert (spill_node);
1688 store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->dreg, ins);
1689 insert_before_ins (ins, tmp, store);
1690 fspill_list = g_list_remove (fspill_list, spill_node->data);
1693 } else if (spec [MONO_INST_DEST] == 'L') {
1695 val = rs->iassign [ins->dreg];
1696 /* check special case when dreg have been moved from ecx (clob shift) */
1697 if (spec [MONO_INST_CLOB] == 's' && clob_dreg != -1)
1698 hreg = clob_dreg + 1;
1700 hreg = ins->dreg + 1;
1702 /* base prev_dreg on fixed hreg, handle clob case */
1703 prev_dreg = hreg - 1;
1708 /* the register gets spilled after this inst */
1711 val = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, ins->dreg, reginfo [ins->dreg].flags);
1712 rs->iassign [ins->dreg] = val;
1714 create_spilled_store (cfg, spill, val, prev_dreg, ins);
1717 DEBUG (g_print ("\tassigned dreg (long) %s to dest R%d\n", mono_arch_regname (val), hreg - 1));
1719 rs->isymbolic [val] = hreg - 1;
1722 val = rs->iassign [hreg];
1726 /* the register gets spilled after this inst */
1729 val = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, hreg, reginfo [hreg].flags);
1730 rs->iassign [hreg] = val;
1732 create_spilled_store (cfg, spill, val, hreg, ins);
1735 DEBUG (g_print ("\tassigned hreg (long-high) %s to dest R%d\n", mono_arch_regname (val), hreg));
1736 rs->isymbolic [val] = hreg;
1737 /* save reg allocating into unused */
1740 /* check if we can free our long reg */
1741 if (reg_is_freeable (val) && hreg >= 0 && reginfo [hreg].born_in >= i) {
1742 DEBUG (g_print ("\tfreeable %s (R%d) (born in %d)\n", mono_arch_regname (val), hreg, reginfo [hreg].born_in));
1743 mono_regstate_free_int (rs, val);
1746 else if (ins->dreg >= MONO_MAX_IREGS) {
1748 val = rs->iassign [ins->dreg];
1749 if (spec [MONO_INST_DEST] == 'l') {
1750 /* check special case when dreg have been moved from ecx (clob shift) */
1751 if (spec [MONO_INST_CLOB] == 's' && clob_dreg != -1)
1752 hreg = clob_dreg + 1;
1754 hreg = ins->dreg + 1;
1756 /* base prev_dreg on fixed hreg, handle clob case */
1757 prev_dreg = hreg - 1;
1759 prev_dreg = ins->dreg;
1764 /* the register gets spilled after this inst */
1767 val = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, ins->dreg, reginfo [ins->dreg].flags);
1768 rs->iassign [ins->dreg] = val;
1770 create_spilled_store (cfg, spill, val, prev_dreg, ins);
1772 DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_arch_regname (val), ins->dreg));
1773 rs->isymbolic [val] = prev_dreg;
1775 /* handle cases where lreg needs to be eax:edx */
1776 if (spec [MONO_INST_DEST] == 'l') {
1777 /* check special case when dreg have been moved from ecx (clob shift) */
1778 int hreg = prev_dreg + 1;
1779 val = rs->iassign [hreg];
1783 /* the register gets spilled after this inst */
1786 val = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, hreg, reginfo [hreg].flags);
1787 rs->iassign [hreg] = val;
1789 create_spilled_store (cfg, spill, val, hreg, ins);
1791 DEBUG (g_print ("\tassigned hreg %s to dest R%d\n", mono_arch_regname (val), hreg));
1792 rs->isymbolic [val] = hreg;
1793 if (ins->dreg == X86_EAX) {
1795 create_copy_ins (cfg, val, X86_EDX, ins);
1796 } else if (ins->dreg == X86_EDX) {
1797 if (val == X86_EAX) {
1799 g_assert_not_reached ();
1801 /* two forced copies */
1802 create_copy_ins (cfg, val, X86_EDX, ins);
1803 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1806 if (val == X86_EDX) {
1807 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1809 /* two forced copies */
1810 create_copy_ins (cfg, val, X86_EDX, ins);
1811 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1814 if (reg_is_freeable (val) && hreg >= 0 && reginfo [hreg].born_in >= i) {
1815 DEBUG (g_print ("\tfreeable %s (R%d)\n", mono_arch_regname (val), hreg));
1816 mono_regstate_free_int (rs, val);
1818 } else if (spec [MONO_INST_DEST] == 'a' && ins->dreg != X86_EAX && spec [MONO_INST_CLOB] != 'd') {
1819 /* this instruction only outputs to EAX, need to copy */
1820 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1821 } else if (spec [MONO_INST_DEST] == 'd' && ins->dreg != X86_EDX && spec [MONO_INST_CLOB] != 'd') {
1822 create_copy_ins (cfg, ins->dreg, X86_EDX, ins);
1825 if (spec [MONO_INST_DEST] != 'f' && reg_is_freeable (ins->dreg) && prev_dreg >= 0 && reginfo [prev_dreg].born_in >= i) {
1826 DEBUG (g_print ("\tfreeable %s (R%d) (born in %d)\n", mono_arch_regname (ins->dreg), prev_dreg, reginfo [prev_dreg].born_in));
1827 mono_regstate_free_int (rs, ins->dreg);
1829 /* put src1 in EAX if it needs to be */
1830 if (spec [MONO_INST_SRC1] == 'a') {
1831 if (!(rs->ifree_mask & (1 << X86_EAX))) {
1832 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [X86_EAX]));
1833 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_EAX]);
1834 mono_regstate_free_int (rs, X86_EAX);
1836 /* force-set sreg1 */
1837 rs->iassign [ins->sreg1] = X86_EAX;
1838 rs->isymbolic [X86_EAX] = ins->sreg1;
1839 ins->sreg1 = X86_EAX;
1840 rs->ifree_mask &= ~ (1 << X86_EAX);
1844 if (spec [MONO_INST_SRC1] == 'f') {
1845 if (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD) {
1847 MonoInst *store = NULL;
1849 if (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD_SPILL) {
1851 spill_node = g_list_first (fspill_list);
1852 g_assert (spill_node);
1854 store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->sreg1, ins);
1855 fspill_list = g_list_remove (fspill_list, spill_node->data);
1859 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1860 load = create_spilled_load_float (cfg, fspill, ins->sreg1, ins);
1861 insert_before_ins (ins, tmp, load);
1863 insert_before_ins (load, tmp, store);
1865 } else if ((spec [MONO_INST_DEST] == 'L') && (spec [MONO_INST_SRC1] == 'L')) {
1866 /* force source to be same as dest */
1867 rs->iassign [ins->sreg1] = ins->dreg;
1868 rs->iassign [ins->sreg1 + 1] = ins->unused;
1870 DEBUG (g_print ("\tassigned sreg1 (long) %s to sreg1 R%d\n", mono_arch_regname (ins->dreg), ins->sreg1));
1871 DEBUG (g_print ("\tassigned sreg1 (long-high) %s to sreg1 R%d\n", mono_arch_regname (ins->unused), ins->sreg1 + 1));
1873 ins->sreg1 = ins->dreg;
1875 * No need for saving the reg, we know that src1=dest in this cases
1876 * ins->inst_c0 = ins->unused;
1879 /* make sure that we remove them from free mask */
1880 rs->ifree_mask &= ~ (1 << ins->dreg);
1881 rs->ifree_mask &= ~ (1 << ins->unused);
1883 else if (ins->sreg1 >= MONO_MAX_IREGS) {
1884 val = rs->iassign [ins->sreg1];
1885 prev_sreg1 = ins->sreg1;
1889 /* the register gets spilled after this inst */
1892 if (0 && ins->opcode == OP_MOVE) {
1894 * small optimization: the dest register is already allocated
1895 * but the src one is not: we can simply assign the same register
1896 * here and peephole will get rid of the instruction later.
1897 * This optimization may interfere with the clobbering handling:
1898 * it removes a mov operation that will be added again to handle clobbering.
1899 * There are also some other issues that should with make testjit.
1901 mono_regstate_alloc_int (rs, 1 << ins->dreg);
1902 val = rs->iassign [ins->sreg1] = ins->dreg;
1903 //g_assert (val >= 0);
1904 DEBUG (g_print ("\tfast assigned sreg1 %s to R%d\n", mono_arch_regname (val), ins->sreg1));
1906 //g_assert (val == -1); /* source cannot be spilled */
1907 val = mono_x86_alloc_int_reg (cfg, tmp, ins, src1_mask, ins->sreg1, reginfo [ins->sreg1].flags);
1908 rs->iassign [ins->sreg1] = val;
1909 DEBUG (g_print ("\tassigned sreg1 %s to R%d\n", mono_arch_regname (val), ins->sreg1));
1912 MonoInst *store = create_spilled_store (cfg, spill, val, prev_sreg1, NULL);
1913 insert_before_ins (ins, tmp, store);
1916 rs->isymbolic [val] = prev_sreg1;
1921 /* handle clobbering of sreg1 */
1922 if ((spec [MONO_INST_CLOB] == '1' || spec [MONO_INST_CLOB] == 's') && ins->dreg != ins->sreg1) {
1923 MonoInst *copy = create_copy_ins (cfg, ins->dreg, ins->sreg1, NULL);
1924 DEBUG (g_print ("\tneed to copy sreg1 %s to dreg %s\n", mono_arch_regname (ins->sreg1), mono_arch_regname (ins->dreg)));
1925 if (ins->sreg2 == -1 || spec [MONO_INST_CLOB] == 's') {
1926 /* note: the copy is inserted before the current instruction! */
1927 insert_before_ins (ins, tmp, copy);
1928 /* we set sreg1 to dest as well */
1929 prev_sreg1 = ins->sreg1 = ins->dreg;
1931 /* inserted after the operation */
1932 copy->next = ins->next;
1937 if (spec [MONO_INST_SRC2] == 'f') {
1938 if (reginfof [ins->sreg2].flags & MONO_X86_FP_NEEDS_LOAD) {
1940 MonoInst *store = NULL;
1942 if (reginfof [ins->sreg2].flags & MONO_X86_FP_NEEDS_LOAD_SPILL) {
1945 spill_node = g_list_first (fspill_list);
1946 g_assert (spill_node);
1947 if (spec [MONO_INST_SRC1] == 'f' && (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD_SPILL))
1948 spill_node = g_list_next (spill_node);
1950 store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->sreg2, ins);
1951 fspill_list = g_list_remove (fspill_list, spill_node->data);
1955 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1956 load = create_spilled_load_float (cfg, fspill, ins->sreg2, ins);
1957 insert_before_ins (ins, tmp, load);
1959 insert_before_ins (load, tmp, store);
1962 else if (ins->sreg2 >= MONO_MAX_IREGS) {
1963 val = rs->iassign [ins->sreg2];
1964 prev_sreg2 = ins->sreg2;
1968 /* the register gets spilled after this inst */
1971 val = mono_x86_alloc_int_reg (cfg, tmp, ins, src2_mask, ins->sreg2, reginfo [ins->sreg2].flags);
1972 rs->iassign [ins->sreg2] = val;
1973 DEBUG (g_print ("\tassigned sreg2 %s to R%d\n", mono_arch_regname (val), ins->sreg2));
1975 create_spilled_store (cfg, spill, val, prev_sreg2, ins);
1977 rs->isymbolic [val] = prev_sreg2;
1979 if (spec [MONO_INST_CLOB] == 's' && ins->sreg2 != X86_ECX) {
1980 DEBUG (g_print ("\tassigned sreg2 %s to R%d, but ECX is needed (R%d)\n", mono_arch_regname (val), ins->sreg2, rs->iassign [X86_ECX]));
1986 if (spec [MONO_INST_CLOB] == 'c') {
1988 guint32 clob_mask = X86_CALLEE_REGS;
1989 for (j = 0; j < MONO_MAX_IREGS; ++j) {
1991 if ((clob_mask & s) && !(rs->ifree_mask & s) && j != ins->sreg1) {
1992 //g_warning ("register %s busy at call site\n", mono_arch_regname (j));
1996 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
1997 DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg1)));
1998 mono_regstate_free_int (rs, ins->sreg1);
2000 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2001 DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2002 mono_regstate_free_int (rs, ins->sreg2);
2005 //DEBUG (print_ins (i, ins));
2006 /* this may result from a insert_before call */
2008 bb->code = tmp->data;
2014 g_list_free (fspill_list);
2017 static unsigned char*
2018 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2020 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2021 x86_fnstcw_membase(code, X86_ESP, 0);
2022 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2023 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2024 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2025 x86_fldcw_membase (code, X86_ESP, 2);
2027 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2028 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2029 x86_pop_reg (code, dreg);
2030 /* FIXME: need the high register
2031 * x86_pop_reg (code, dreg_high);
2034 x86_push_reg (code, X86_EAX); // SP = SP - 4
2035 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2036 x86_pop_reg (code, dreg);
2038 x86_fldcw_membase (code, X86_ESP, 0);
2039 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2042 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2044 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2048 static unsigned char*
2049 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2051 int sreg = tree->sreg1;
2052 #ifdef PLATFORM_WIN32
2057 * If requested stack size is larger than one page,
2058 * perform stack-touch operation
2061 * Generate stack probe code.
2062 * Under Windows, it is necessary to allocate one page at a time,
2063 * "touching" stack after each successful sub-allocation. This is
2064 * because of the way stack growth is implemented - there is a
2065 * guard page before the lowest stack page that is currently commited.
2066 * Stack normally grows sequentially so OS traps access to the
2067 * guard page and commits more pages when needed.
2069 x86_test_reg_imm (code, sreg, ~0xFFF);
2070 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2072 br[2] = code; /* loop */
2073 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2074 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2075 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2076 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2077 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2078 x86_patch (br[3], br[2]);
2079 x86_test_reg_reg (code, sreg, sreg);
2080 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2081 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2083 br[1] = code; x86_jump8 (code, 0);
2085 x86_patch (br[0], code);
2086 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2087 x86_patch (br[1], code);
2088 x86_patch (br[4], code);
2089 #else /* PLATFORM_WIN32 */
2090 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2092 if (tree->flags & MONO_INST_INIT) {
2094 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2095 x86_push_reg (code, X86_EAX);
2098 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2099 x86_push_reg (code, X86_ECX);
2102 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2103 x86_push_reg (code, X86_EDI);
2107 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2108 if (sreg != X86_ECX)
2109 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2110 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2112 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2114 x86_prefix (code, X86_REP_PREFIX);
2117 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2118 x86_pop_reg (code, X86_EDI);
2119 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2120 x86_pop_reg (code, X86_ECX);
2121 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2122 x86_pop_reg (code, X86_EAX);
2127 #define REAL_PRINT_REG(text,reg) \
2128 mono_assert (reg >= 0); \
2129 x86_push_reg (code, X86_EAX); \
2130 x86_push_reg (code, X86_EDX); \
2131 x86_push_reg (code, X86_ECX); \
2132 x86_push_reg (code, reg); \
2133 x86_push_imm (code, reg); \
2134 x86_push_imm (code, text " %d %p\n"); \
2135 x86_mov_reg_imm (code, X86_EAX, printf); \
2136 x86_call_reg (code, X86_EAX); \
2137 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2138 x86_pop_reg (code, X86_ECX); \
2139 x86_pop_reg (code, X86_EDX); \
2140 x86_pop_reg (code, X86_EAX);
2142 /* benchmark and set based on cpu */
2143 #define LOOP_ALIGNMENT 8
2144 #define bb_is_loop_start(bb) ((bb)->nesting && ((bb)->in_count == 1))
2147 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2152 guint8 *code = cfg->native_code + cfg->code_len;
2153 MonoInst *last_ins = NULL;
2154 guint last_offset = 0;
2157 if (cfg->opt & MONO_OPT_PEEPHOLE)
2158 peephole_pass (cfg, bb);
2160 if (cfg->opt & MONO_OPT_LOOP) {
2161 int pad, align = LOOP_ALIGNMENT;
2162 /* set alignment depending on cpu */
2163 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2165 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2166 x86_padding (code, pad);
2167 cfg->code_len += pad;
2168 bb->native_offset = cfg->code_len;
2172 if (cfg->verbose_level > 2)
2173 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2175 cpos = bb->max_offset;
2177 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2178 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2179 g_assert (!mono_compile_aot);
2182 cov->data [bb->dfn].cil_code = bb->cil_code;
2183 /* this is not thread save, but good enough */
2184 x86_inc_mem (code, &cov->data [bb->dfn].count);
2187 offset = code - cfg->native_code;
2191 offset = code - cfg->native_code;
2193 max_len = ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
2195 if (offset > (cfg->code_size - max_len - 16)) {
2196 cfg->code_size *= 2;
2197 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2198 code = cfg->native_code + offset;
2199 mono_jit_stats.code_reallocs++;
2202 mono_debug_record_line_number (cfg, ins, offset);
2204 switch (ins->opcode) {
2206 x86_mul_reg (code, ins->sreg2, TRUE);
2209 x86_mul_reg (code, ins->sreg2, FALSE);
2211 case OP_X86_SETEQ_MEMBASE:
2212 x86_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2214 case OP_STOREI1_MEMBASE_IMM:
2215 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2217 case OP_STOREI2_MEMBASE_IMM:
2218 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2220 case OP_STORE_MEMBASE_IMM:
2221 case OP_STOREI4_MEMBASE_IMM:
2222 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2224 case OP_STOREI1_MEMBASE_REG:
2225 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2227 case OP_STOREI2_MEMBASE_REG:
2228 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2230 case OP_STORE_MEMBASE_REG:
2231 case OP_STOREI4_MEMBASE_REG:
2232 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2237 x86_mov_reg_mem (code, ins->dreg, ins->inst_p0, 4);
2240 x86_mov_reg_imm (code, ins->dreg, ins->inst_p0);
2241 x86_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2243 case OP_LOAD_MEMBASE:
2244 case OP_LOADI4_MEMBASE:
2245 case OP_LOADU4_MEMBASE:
2246 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2248 case OP_LOADU1_MEMBASE:
2249 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2251 case OP_LOADI1_MEMBASE:
2252 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2254 case OP_LOADU2_MEMBASE:
2255 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2257 case OP_LOADI2_MEMBASE:
2258 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2261 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2264 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2267 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2270 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2273 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2275 case OP_COMPARE_IMM:
2276 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2278 case OP_X86_COMPARE_MEMBASE_REG:
2279 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2281 case OP_X86_COMPARE_MEMBASE_IMM:
2282 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2284 case OP_X86_COMPARE_REG_MEMBASE:
2285 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2287 case OP_X86_TEST_NULL:
2288 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2290 case OP_X86_ADD_MEMBASE_IMM:
2291 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2293 case OP_X86_ADD_MEMBASE:
2294 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2296 case OP_X86_SUB_MEMBASE_IMM:
2297 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2299 case OP_X86_SUB_MEMBASE:
2300 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2302 case OP_X86_INC_MEMBASE:
2303 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2305 case OP_X86_INC_REG:
2306 x86_inc_reg (code, ins->dreg);
2308 case OP_X86_DEC_MEMBASE:
2309 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2311 case OP_X86_DEC_REG:
2312 x86_dec_reg (code, ins->dreg);
2314 case OP_X86_MUL_MEMBASE:
2315 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2318 x86_breakpoint (code);
2322 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2325 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2328 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2331 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2335 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2338 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2341 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2344 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2347 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2350 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2354 x86_div_reg (code, ins->sreg2, TRUE);
2357 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2358 x86_div_reg (code, ins->sreg2, FALSE);
2361 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2363 x86_div_reg (code, ins->sreg2, TRUE);
2367 x86_div_reg (code, ins->sreg2, TRUE);
2370 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2371 x86_div_reg (code, ins->sreg2, FALSE);
2374 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2376 x86_div_reg (code, ins->sreg2, TRUE);
2379 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2382 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2385 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2388 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2391 g_assert (ins->sreg2 == X86_ECX);
2392 x86_shift_reg (code, X86_SHL, ins->dreg);
2395 g_assert (ins->sreg2 == X86_ECX);
2396 x86_shift_reg (code, X86_SAR, ins->dreg);
2399 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2402 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2405 g_assert (ins->sreg2 == X86_ECX);
2406 x86_shift_reg (code, X86_SHR, ins->dreg);
2409 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2412 guint8 *jump_to_end;
2414 /* handle shifts below 32 bits */
2415 x86_shld_reg (code, ins->unused, ins->sreg1);
2416 x86_shift_reg (code, X86_SHL, ins->sreg1);
2418 x86_test_reg_imm (code, X86_ECX, 32);
2419 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2421 /* handle shift over 32 bit */
2422 x86_mov_reg_reg (code, ins->unused, ins->sreg1, 4);
2423 x86_clear_reg (code, ins->sreg1);
2425 x86_patch (jump_to_end, code);
2429 guint8 *jump_to_end;
2431 /* handle shifts below 32 bits */
2432 x86_shrd_reg (code, ins->sreg1, ins->unused);
2433 x86_shift_reg (code, X86_SAR, ins->unused);
2435 x86_test_reg_imm (code, X86_ECX, 32);
2436 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2438 /* handle shifts over 31 bits */
2439 x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
2440 x86_shift_reg_imm (code, X86_SAR, ins->unused, 31);
2442 x86_patch (jump_to_end, code);
2446 guint8 *jump_to_end;
2448 /* handle shifts below 32 bits */
2449 x86_shrd_reg (code, ins->sreg1, ins->unused);
2450 x86_shift_reg (code, X86_SHR, ins->unused);
2452 x86_test_reg_imm (code, X86_ECX, 32);
2453 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2455 /* handle shifts over 31 bits */
2456 x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
2457 x86_shift_reg_imm (code, X86_SHR, ins->unused, 31);
2459 x86_patch (jump_to_end, code);
2463 if (ins->inst_imm >= 32) {
2464 x86_mov_reg_reg (code, ins->unused, ins->sreg1, 4);
2465 x86_clear_reg (code, ins->sreg1);
2466 x86_shift_reg_imm (code, X86_SHL, ins->unused, ins->inst_imm - 32);
2468 x86_shld_reg_imm (code, ins->unused, ins->sreg1, ins->inst_imm);
2469 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2473 if (ins->inst_imm >= 32) {
2474 x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
2475 x86_shift_reg_imm (code, X86_SAR, ins->unused, 0x1f);
2476 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2478 x86_shrd_reg_imm (code, ins->sreg1, ins->unused, ins->inst_imm);
2479 x86_shift_reg_imm (code, X86_SAR, ins->unused, ins->inst_imm);
2482 case OP_LSHR_UN_IMM:
2483 if (ins->inst_imm >= 32) {
2484 x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
2485 x86_clear_reg (code, ins->unused);
2486 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2488 x86_shrd_reg_imm (code, ins->sreg1, ins->unused, ins->inst_imm);
2489 x86_shift_reg_imm (code, X86_SHR, ins->unused, ins->inst_imm);
2493 x86_not_reg (code, ins->sreg1);
2496 x86_neg_reg (code, ins->sreg1);
2499 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2502 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2505 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2508 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2511 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2512 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2514 case CEE_MUL_OVF_UN: {
2515 /* the mul operation and the exception check should most likely be split */
2516 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2517 /*g_assert (ins->sreg2 == X86_EAX);
2518 g_assert (ins->dreg == X86_EAX);*/
2519 if (ins->sreg2 == X86_EAX) {
2520 non_eax_reg = ins->sreg1;
2521 } else if (ins->sreg1 == X86_EAX) {
2522 non_eax_reg = ins->sreg2;
2524 /* no need to save since we're going to store to it anyway */
2525 if (ins->dreg != X86_EAX) {
2527 x86_push_reg (code, X86_EAX);
2529 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
2530 non_eax_reg = ins->sreg2;
2532 if (ins->dreg == X86_EDX) {
2535 x86_push_reg (code, X86_EAX);
2537 } else if (ins->dreg != X86_EAX) {
2539 x86_push_reg (code, X86_EDX);
2541 x86_mul_reg (code, non_eax_reg, FALSE);
2542 /* save before the check since pop and mov don't change the flags */
2543 if (ins->dreg != X86_EAX)
2544 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2546 x86_pop_reg (code, X86_EDX);
2548 x86_pop_reg (code, X86_EAX);
2549 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2553 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
2556 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2557 x86_mov_reg_imm (code, ins->dreg, 0);
2561 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2564 g_assert_not_reached ();
2567 * Note: this 'frame destruction' logic is useful for tail calls, too.
2568 * Keep in sync with the code in emit_epilog.
2572 /* FIXME: no tracing support... */
2573 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2574 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2575 /* reset offset to make max_len work */
2576 offset = code - cfg->native_code;
2578 g_assert (!cfg->method->save_lmf);
2580 if (cfg->used_int_regs & (1 << X86_EBX))
2582 if (cfg->used_int_regs & (1 << X86_EDI))
2584 if (cfg->used_int_regs & (1 << X86_ESI))
2587 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
2589 if (cfg->used_int_regs & (1 << X86_ESI))
2590 x86_pop_reg (code, X86_ESI);
2591 if (cfg->used_int_regs & (1 << X86_EDI))
2592 x86_pop_reg (code, X86_EDI);
2593 if (cfg->used_int_regs & (1 << X86_EBX))
2594 x86_pop_reg (code, X86_EBX);
2596 /* restore ESP/EBP */
2598 offset = code - cfg->native_code;
2599 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2600 x86_jump32 (code, 0);
2604 /* ensure ins->sreg1 is not NULL */
2605 x86_alu_membase_imm (code, X86_CMP, ins->sreg1, 0, 0);
2608 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
2609 x86_push_reg (code, hreg);
2610 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
2611 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
2612 x86_pop_reg (code, hreg);
2620 call = (MonoCallInst*)ins;
2621 if (ins->flags & MONO_INST_HAS_METHOD)
2622 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
2624 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
2626 x86_call_code (code, 0);
2627 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2628 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2633 case OP_VOIDCALL_REG:
2635 call = (MonoCallInst*)ins;
2636 x86_call_reg (code, ins->sreg1);
2637 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2638 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2640 case OP_FCALL_MEMBASE:
2641 case OP_LCALL_MEMBASE:
2642 case OP_VCALL_MEMBASE:
2643 case OP_VOIDCALL_MEMBASE:
2644 case OP_CALL_MEMBASE:
2645 call = (MonoCallInst*)ins;
2646 x86_call_membase (code, ins->sreg1, ins->inst_offset);
2647 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2648 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2652 x86_push_reg (code, ins->sreg1);
2654 case OP_X86_PUSH_IMM:
2655 x86_push_imm (code, ins->inst_imm);
2657 case OP_X86_PUSH_MEMBASE:
2658 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
2660 case OP_X86_PUSH_OBJ:
2661 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
2662 x86_push_reg (code, X86_EDI);
2663 x86_push_reg (code, X86_ESI);
2664 x86_push_reg (code, X86_ECX);
2665 if (ins->inst_offset)
2666 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
2668 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
2669 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2670 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
2672 x86_prefix (code, X86_REP_PREFIX);
2674 x86_pop_reg (code, X86_ECX);
2675 x86_pop_reg (code, X86_ESI);
2676 x86_pop_reg (code, X86_EDI);
2679 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->unused);
2681 case OP_X86_LEA_MEMBASE:
2682 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
2685 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
2688 /* keep alignment */
2689 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
2690 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
2691 code = mono_emit_stack_alloc (code, ins);
2692 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2698 x86_push_reg (code, ins->sreg1);
2699 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2700 (gpointer)"mono_arch_throw_exception");
2701 x86_call_code (code, 0);
2704 case OP_CALL_HANDLER:
2705 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2706 x86_call_imm (code, 0);
2709 ins->inst_c0 = code - cfg->native_code;
2712 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
2713 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
2715 if (ins->flags & MONO_INST_BRLABEL) {
2716 if (ins->inst_i0->inst_c0) {
2717 x86_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
2719 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
2720 if ((cfg->opt & MONO_OPT_BRANCH) &&
2721 x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
2722 x86_jump8 (code, 0);
2724 x86_jump32 (code, 0);
2727 if (ins->inst_target_bb->native_offset) {
2728 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
2730 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2731 if ((cfg->opt & MONO_OPT_BRANCH) &&
2732 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
2733 x86_jump8 (code, 0);
2735 x86_jump32 (code, 0);
2740 x86_jump_reg (code, ins->sreg1);
2743 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
2744 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2747 x86_set_reg (code, X86_CC_LT, ins->dreg, TRUE);
2748 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2751 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
2752 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2755 x86_set_reg (code, X86_CC_GT, ins->dreg, TRUE);
2756 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2759 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
2760 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2762 case OP_COND_EXC_EQ:
2763 case OP_COND_EXC_NE_UN:
2764 case OP_COND_EXC_LT:
2765 case OP_COND_EXC_LT_UN:
2766 case OP_COND_EXC_GT:
2767 case OP_COND_EXC_GT_UN:
2768 case OP_COND_EXC_GE:
2769 case OP_COND_EXC_GE_UN:
2770 case OP_COND_EXC_LE:
2771 case OP_COND_EXC_LE_UN:
2772 case OP_COND_EXC_OV:
2773 case OP_COND_EXC_NO:
2775 case OP_COND_EXC_NC:
2776 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
2777 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
2789 EMIT_COND_BRANCH (ins, branch_cc_table [ins->opcode - CEE_BEQ], (ins->opcode < CEE_BNE_UN));
2792 /* floating point opcodes */
2794 double d = *(double *)ins->inst_p0;
2796 if ((d == 0.0) && (mono_signbit (d) == 0)) {
2798 } else if (d == 1.0) {
2801 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
2802 x86_fld (code, NULL, TRUE);
2807 float f = *(float *)ins->inst_p0;
2809 if ((f == 0.0) && (mono_signbit (f) == 0)) {
2811 } else if (f == 1.0) {
2814 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
2815 x86_fld (code, NULL, FALSE);
2819 case OP_STORER8_MEMBASE_REG:
2820 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
2822 case OP_LOADR8_SPILL_MEMBASE:
2823 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
2826 case OP_LOADR8_MEMBASE:
2827 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
2829 case OP_STORER4_MEMBASE_REG:
2830 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
2832 case OP_LOADR4_MEMBASE:
2833 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
2835 case CEE_CONV_R4: /* FIXME: change precision */
2837 x86_push_reg (code, ins->sreg1);
2838 x86_fild_membase (code, X86_ESP, 0, FALSE);
2839 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2841 case OP_X86_FP_LOAD_I8:
2842 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
2844 case OP_X86_FP_LOAD_I4:
2845 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
2847 case OP_FCONV_TO_I1:
2848 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
2850 case OP_FCONV_TO_U1:
2851 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
2853 case OP_FCONV_TO_I2:
2854 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
2856 case OP_FCONV_TO_U2:
2857 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
2859 case OP_FCONV_TO_I4:
2861 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
2863 case OP_FCONV_TO_I8:
2864 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2865 x86_fnstcw_membase(code, X86_ESP, 0);
2866 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
2867 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
2868 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
2869 x86_fldcw_membase (code, X86_ESP, 2);
2870 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2871 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2872 x86_pop_reg (code, ins->dreg);
2873 x86_pop_reg (code, ins->unused);
2874 x86_fldcw_membase (code, X86_ESP, 0);
2875 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2877 case OP_LCONV_TO_R_UN: {
2878 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
2881 /* load 64bit integer to FP stack */
2882 x86_push_imm (code, 0);
2883 x86_push_reg (code, ins->sreg2);
2884 x86_push_reg (code, ins->sreg1);
2885 x86_fild_membase (code, X86_ESP, 0, TRUE);
2886 /* store as 80bit FP value */
2887 x86_fst80_membase (code, X86_ESP, 0);
2889 /* test if lreg is negative */
2890 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
2891 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
2893 /* add correction constant mn */
2894 x86_fld80_mem (code, mn);
2895 x86_fld80_membase (code, X86_ESP, 0);
2896 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
2897 x86_fst80_membase (code, X86_ESP, 0);
2899 x86_patch (br, code);
2901 x86_fld80_membase (code, X86_ESP, 0);
2902 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
2906 case OP_LCONV_TO_OVF_I: {
2907 guint8 *br [3], *label [1];
2910 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
2912 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2914 /* If the low word top bit is set, see if we are negative */
2915 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
2916 /* We are not negative (no top bit set, check for our top word to be zero */
2917 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
2918 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2921 /* throw exception */
2922 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
2923 x86_jump32 (code, 0);
2925 x86_patch (br [0], code);
2926 /* our top bit is set, check that top word is 0xfffffff */
2927 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
2929 x86_patch (br [1], code);
2930 /* nope, emit exception */
2931 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
2932 x86_patch (br [2], label [0]);
2934 if (ins->dreg != ins->sreg1)
2935 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2939 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
2942 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
2945 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
2948 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
2956 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
2961 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
2968 * it really doesn't make sense to inline all this code,
2969 * it's here just to show that things may not be as simple
2972 guchar *check_pos, *end_tan, *pop_jump;
2973 x86_push_reg (code, X86_EAX);
2976 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
2978 x86_branch8 (code, X86_CC_NE, 0, FALSE);
2979 x86_fstp (code, 0); /* pop the 1.0 */
2981 x86_jump8 (code, 0);
2983 x86_fp_op (code, X86_FADD, 0);
2987 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
2989 x86_branch8 (code, X86_CC_NE, 0, FALSE);
2992 x86_patch (pop_jump, code);
2993 x86_fstp (code, 0); /* pop the 1.0 */
2994 x86_patch (check_pos, code);
2995 x86_patch (end_tan, code);
2997 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
2998 x86_pop_reg (code, X86_EAX);
3005 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3016 x86_push_reg (code, X86_EAX);
3017 /* we need to exchange ST(0) with ST(1) */
3020 /* this requires a loop, because fprem somtimes
3021 * returns a partial remainder */
3023 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3024 /* x86_fprem1 (code); */
3027 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3029 x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3034 x86_pop_reg (code, X86_EAX);
3038 if (cfg->opt & MONO_OPT_FCMOV) {
3039 x86_fcomip (code, 1);
3043 /* this overwrites EAX */
3044 EMIT_FPCOMPARE(code);
3045 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3048 if (cfg->opt & MONO_OPT_FCMOV) {
3049 /* zeroing the register at the start results in
3050 * shorter and faster code (we can also remove the widening op)
3052 guchar *unordered_check;
3053 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3054 x86_fcomip (code, 1);
3056 unordered_check = code;
3057 x86_branch8 (code, X86_CC_P, 0, FALSE);
3058 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3059 x86_patch (unordered_check, code);
3062 if (ins->dreg != X86_EAX)
3063 x86_push_reg (code, X86_EAX);
3065 EMIT_FPCOMPARE(code);
3066 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3067 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3068 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3069 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3071 if (ins->dreg != X86_EAX)
3072 x86_pop_reg (code, X86_EAX);
3076 if (cfg->opt & MONO_OPT_FCMOV) {
3077 /* zeroing the register at the start results in
3078 * shorter and faster code (we can also remove the widening op)
3080 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3081 x86_fcomip (code, 1);
3083 if (ins->opcode == OP_FCLT_UN) {
3084 guchar *unordered_check = code;
3085 guchar *jump_to_end;
3086 x86_branch8 (code, X86_CC_P, 0, FALSE);
3087 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3089 x86_jump8 (code, 0);
3090 x86_patch (unordered_check, code);
3091 x86_inc_reg (code, ins->dreg);
3092 x86_patch (jump_to_end, code);
3094 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3098 if (ins->dreg != X86_EAX)
3099 x86_push_reg (code, X86_EAX);
3101 EMIT_FPCOMPARE(code);
3102 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3103 if (ins->opcode == OP_FCLT_UN) {
3104 guchar *is_not_zero_check, *end_jump;
3105 is_not_zero_check = code;
3106 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3108 x86_jump8 (code, 0);
3109 x86_patch (is_not_zero_check, code);
3110 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3112 x86_patch (end_jump, code);
3114 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3115 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3117 if (ins->dreg != X86_EAX)
3118 x86_pop_reg (code, X86_EAX);
3122 if (cfg->opt & MONO_OPT_FCMOV) {
3123 /* zeroing the register at the start results in
3124 * shorter and faster code (we can also remove the widening op)
3126 guchar *unordered_check;
3127 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3128 x86_fcomip (code, 1);
3130 if (ins->opcode == OP_FCGT) {
3131 unordered_check = code;
3132 x86_branch8 (code, X86_CC_P, 0, FALSE);
3133 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3134 x86_patch (unordered_check, code);
3136 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3140 if (ins->dreg != X86_EAX)
3141 x86_push_reg (code, X86_EAX);
3143 EMIT_FPCOMPARE(code);
3144 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3145 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3146 if (ins->opcode == OP_FCGT_UN) {
3147 guchar *is_not_zero_check, *end_jump;
3148 is_not_zero_check = code;
3149 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3151 x86_jump8 (code, 0);
3152 x86_patch (is_not_zero_check, code);
3153 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3155 x86_patch (end_jump, code);
3157 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3158 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3160 if (ins->dreg != X86_EAX)
3161 x86_pop_reg (code, X86_EAX);
3164 if (cfg->opt & MONO_OPT_FCMOV) {
3165 guchar *jump = code;
3166 x86_branch8 (code, X86_CC_P, 0, TRUE);
3167 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3168 x86_patch (jump, code);
3171 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3172 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3175 /* Branch if C013 != 100 */
3176 if (cfg->opt & MONO_OPT_FCMOV) {
3177 /* branch if !ZF or (PF|CF) */
3178 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3179 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3180 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3183 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3184 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3187 if (cfg->opt & MONO_OPT_FCMOV) {
3188 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3191 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3194 if (cfg->opt & MONO_OPT_FCMOV) {
3195 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3196 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3199 if (ins->opcode == OP_FBLT_UN) {
3200 guchar *is_not_zero_check, *end_jump;
3201 is_not_zero_check = code;
3202 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3204 x86_jump8 (code, 0);
3205 x86_patch (is_not_zero_check, code);
3206 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3208 x86_patch (end_jump, code);
3210 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3214 if (cfg->opt & MONO_OPT_FCMOV) {
3215 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3218 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3219 if (ins->opcode == OP_FBGT_UN) {
3220 guchar *is_not_zero_check, *end_jump;
3221 is_not_zero_check = code;
3222 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3224 x86_jump8 (code, 0);
3225 x86_patch (is_not_zero_check, code);
3226 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3228 x86_patch (end_jump, code);
3230 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3233 /* Branch if C013 == 100 or 001 */
3234 if (cfg->opt & MONO_OPT_FCMOV) {
3237 /* skip branch if C1=1 */
3239 x86_branch8 (code, X86_CC_P, 0, FALSE);
3240 /* branch if (C0 | C3) = 1 */
3241 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3242 x86_patch (br1, code);
3245 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3246 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3247 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3248 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3251 /* Branch if C013 == 000 */
3252 if (cfg->opt & MONO_OPT_FCMOV) {
3253 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3256 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3259 /* Branch if C013=000 or 100 */
3260 if (cfg->opt & MONO_OPT_FCMOV) {
3263 /* skip branch if C1=1 */
3265 x86_branch8 (code, X86_CC_P, 0, FALSE);
3266 /* branch if C0=0 */
3267 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3268 x86_patch (br1, code);
3271 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
3272 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
3273 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3276 /* Branch if C013 != 001 */
3277 if (cfg->opt & MONO_OPT_FCMOV) {
3278 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3279 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3282 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3283 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3285 case CEE_CKFINITE: {
3286 x86_push_reg (code, X86_EAX);
3289 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
3290 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3291 x86_pop_reg (code, X86_EAX);
3292 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3296 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3297 g_assert_not_reached ();
3300 if ((code - cfg->native_code - offset) > max_len) {
3301 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
3302 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
3303 g_assert_not_reached ();
3309 last_offset = offset;
3314 cfg->code_len = code - cfg->native_code;
3318 mono_arch_register_lowlevel_calls (void)
3323 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3325 MonoJumpInfo *patch_info;
3327 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3328 unsigned char *ip = patch_info->ip.i + code;
3329 const unsigned char *target;
3331 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3333 switch (patch_info->type) {
3334 case MONO_PATCH_INFO_IP:
3335 *((gconstpointer *)(ip)) = target;
3337 case MONO_PATCH_INFO_METHOD_REL:
3338 *((gconstpointer *)(ip)) = target;
3340 case MONO_PATCH_INFO_SWITCH: {
3341 *((gconstpointer *)(ip + 2)) = target;
3342 /* we put into the table the absolute address, no need for x86_patch in this case */
3345 case MONO_PATCH_INFO_IID:
3346 *((guint32 *)(ip + 1)) = (guint32)target;
3348 case MONO_PATCH_INFO_CLASS_INIT: {
3350 /* Might already been changed to a nop */
3351 x86_call_imm (code, 0);
3354 case MONO_PATCH_INFO_R4:
3355 case MONO_PATCH_INFO_R8:
3356 *((gconstpointer *)(ip + 2)) = target;
3358 case MONO_PATCH_INFO_METHODCONST:
3359 case MONO_PATCH_INFO_CLASS:
3360 case MONO_PATCH_INFO_IMAGE:
3361 case MONO_PATCH_INFO_FIELD:
3362 case MONO_PATCH_INFO_VTABLE:
3363 case MONO_PATCH_INFO_SFLDA:
3364 case MONO_PATCH_INFO_EXC_NAME:
3365 case MONO_PATCH_INFO_LDSTR:
3366 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
3367 case MONO_PATCH_INFO_LDTOKEN:
3368 *((gconstpointer *)(ip + 1)) = target;
3373 x86_patch (ip, target);
3378 mono_arch_max_epilog_size (MonoCompile *cfg)
3380 int exc_count = 0, max_epilog_size = 16;
3381 MonoJumpInfo *patch_info;
3383 if (cfg->method->save_lmf)
3384 max_epilog_size += 128;
3386 if (mono_jit_trace_calls != NULL)
3387 max_epilog_size += 50;
3389 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3390 max_epilog_size += 50;
3392 /* count the number of exception infos */
3394 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
3395 if (patch_info->type == MONO_PATCH_INFO_EXC)
3400 * make sure we have enough space for exceptions
3401 * 16 is the size of two push_imm instructions and a call
3403 max_epilog_size += exc_count*16;
3405 return max_epilog_size;
3409 mono_arch_emit_prolog (MonoCompile *cfg)
3411 MonoMethod *method = cfg->method;
3413 MonoMethodSignature *sig;
3415 int alloc_size, pos, max_offset, i;
3418 cfg->code_size = MAX (((MonoMethodNormal *)method)->header->code_size * 4, 256);
3419 code = cfg->native_code = g_malloc (cfg->code_size);
3421 x86_push_reg (code, X86_EBP);
3422 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
3424 alloc_size = - cfg->stack_offset;
3427 if (method->save_lmf) {
3428 pos += sizeof (MonoLMF);
3430 /* save the current IP */
3431 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
3432 x86_push_imm (code, 0);
3434 /* save all caller saved regs */
3435 x86_push_reg (code, X86_EBP);
3436 x86_push_reg (code, X86_ESI);
3437 x86_push_reg (code, X86_EDI);
3438 x86_push_reg (code, X86_EBX);
3440 /* save method info */
3441 x86_push_imm (code, method);
3443 /* get the address of lmf for the current thread */
3445 * This is performance critical so we try to use some tricks to make
3448 if (lmf_tls_offset != -1) {
3449 /* Load lmf quicky using the GS register */
3450 x86_prefix (code, X86_GS_PREFIX);
3451 x86_mov_reg_mem (code, X86_EAX, 0, 4);
3452 x86_mov_reg_membase (code, X86_EAX, X86_EAX, lmf_tls_offset, 4);
3455 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3456 (gpointer)"mono_get_lmf_addr");
3457 x86_call_code (code, 0);
3461 x86_push_reg (code, X86_EAX);
3462 /* push *lfm (previous_lmf) */
3463 x86_push_membase (code, X86_EAX, 0);
3465 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
3468 if (cfg->used_int_regs & (1 << X86_EBX)) {
3469 x86_push_reg (code, X86_EBX);
3473 if (cfg->used_int_regs & (1 << X86_EDI)) {
3474 x86_push_reg (code, X86_EDI);
3478 if (cfg->used_int_regs & (1 << X86_ESI)) {
3479 x86_push_reg (code, X86_ESI);
3487 /* See mono_emit_stack_alloc */
3488 #ifdef PLATFORM_WIN32
3489 guint32 remaining_size = alloc_size;
3490 while (remaining_size >= 0x1000) {
3491 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
3492 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
3493 remaining_size -= 0x1000;
3496 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
3498 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
3502 /* compute max_offset in order to use short forward jumps */
3504 if (cfg->opt & MONO_OPT_BRANCH) {
3505 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
3506 MonoInst *ins = bb->code;
3507 bb->max_offset = max_offset;
3509 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
3511 /* max alignment for loops */
3512 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
3513 max_offset += LOOP_ALIGNMENT;
3516 if (ins->opcode == OP_LABEL)
3517 ins->inst_c1 = max_offset;
3519 max_offset += ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
3525 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3526 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
3528 /* load arguments allocated to register from the stack */
3529 sig = method->signature;
3532 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3533 inst = cfg->varinfo [pos];
3534 if (inst->opcode == OP_REGVAR) {
3535 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
3536 if (cfg->verbose_level > 2)
3537 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
3542 cfg->code_len = code - cfg->native_code;
3548 mono_arch_emit_epilog (MonoCompile *cfg)
3550 MonoJumpInfo *patch_info;
3551 MonoMethod *method = cfg->method;
3552 MonoMethodSignature *sig = method->signature;
3554 guint32 stack_to_pop;
3557 code = cfg->native_code + cfg->code_len;
3559 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3560 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
3562 /* the code restoring the registers must be kept in sync with CEE_JMP */
3565 if (method->save_lmf) {
3566 gint32 prev_lmf_reg;
3568 /* Find a spare register */
3569 switch (sig->ret->type) {
3572 prev_lmf_reg = X86_EDI;
3573 cfg->used_int_regs |= (1 << X86_EDI);
3576 prev_lmf_reg = X86_EDX;
3580 /* reg = previous_lmf */
3581 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, -32, 4);
3584 x86_mov_reg_membase (code, X86_ECX, X86_EBP, -28, 4);
3586 /* *(lmf) = previous_lmf */
3587 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
3589 /* restore caller saved regs */
3590 if (cfg->used_int_regs & (1 << X86_EBX)) {
3591 x86_mov_reg_membase (code, X86_EBX, X86_EBP, -20, 4);
3594 if (cfg->used_int_regs & (1 << X86_EDI)) {
3595 x86_mov_reg_membase (code, X86_EDI, X86_EBP, -16, 4);
3597 if (cfg->used_int_regs & (1 << X86_ESI)) {
3598 x86_mov_reg_membase (code, X86_ESI, X86_EBP, -12, 4);
3601 /* EBP is restored by LEAVE */
3603 if (cfg->used_int_regs & (1 << X86_EBX)) {
3606 if (cfg->used_int_regs & (1 << X86_EDI)) {
3609 if (cfg->used_int_regs & (1 << X86_ESI)) {
3614 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
3616 if (cfg->used_int_regs & (1 << X86_ESI)) {
3617 x86_pop_reg (code, X86_ESI);
3619 if (cfg->used_int_regs & (1 << X86_EDI)) {
3620 x86_pop_reg (code, X86_EDI);
3622 if (cfg->used_int_regs & (1 << X86_EBX)) {
3623 x86_pop_reg (code, X86_EBX);
3629 if (CALLCONV_IS_STDCALL (sig->call_convention)) {
3630 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
3632 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
3633 } else if (MONO_TYPE_ISSTRUCT (cfg->method->signature->ret))
3639 x86_ret_imm (code, stack_to_pop);
3643 /* add code to raise exceptions */
3644 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
3645 switch (patch_info->type) {
3646 case MONO_PATCH_INFO_EXC:
3647 x86_patch (patch_info->ip.i + cfg->native_code, code);
3648 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC_NAME, patch_info->data.target);
3649 x86_push_imm (code, patch_info->data.target);
3650 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_METHOD_REL, (gpointer)patch_info->ip.i);
3651 x86_push_imm (code, patch_info->ip.i + cfg->native_code);
3652 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
3653 patch_info->data.name = "mono_arch_throw_exception_by_name";
3654 patch_info->ip.i = code - cfg->native_code;
3655 x86_jump_code (code, 0);
3663 cfg->code_len = code - cfg->native_code;
3665 g_assert (cfg->code_len < cfg->code_size);
3670 mono_arch_flush_icache (guint8 *code, gint size)
3676 mono_arch_flush_register_windows (void)
3681 * Support for fast access to the thread-local lmf structure using the GS
3682 * segment register on NPTL + kernel 2.6.x.
3685 static gboolean tls_offset_inited = FALSE;
3688 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
3690 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3691 pthread_t self = pthread_self();
3692 pthread_attr_t attr;
3693 void *staddr = NULL;
3695 struct sigaltstack sa;
3698 if (!tls_offset_inited) {
3701 tls_offset_inited = TRUE;
3703 code = (guint8*)mono_get_lmf_addr;
3705 if (getenv ("MONO_NPTL")) {
3707 * Determine the offset of mono_lfm_addr inside the TLS structures
3708 * by disassembling the function above.
3711 /* This is generated by gcc 3.3.2 */
3712 if ((code [0] == 0x55) && (code [1] == 0x89) && (code [2] == 0xe5) &&
3713 (code [3] == 0x65) && (code [4] == 0xa1) && (code [5] == 0x00) &&
3714 (code [6] == 0x00) && (code [7] == 0x00) && (code [8] == 0x00) &&
3715 (code [9] == 0x8b) && (code [10] == 0x80)) {
3716 lmf_tls_offset = *(int*)&(code [11]);
3719 /* This is generated by gcc-3.4 */
3720 if ((code [0] == 0x55) && (code [1] == 0x89) && (code [2] == 0xe5) &&
3721 (code [3] == 0x65) && (code [4] == 0xa1)) {
3722 lmf_tls_offset = *(int*)&(code [5]);
3727 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3729 /* Determine stack boundaries */
3730 if (!mono_running_on_valgrind ()) {
3731 #ifdef HAVE_PTHREAD_GETATTR_NP
3732 pthread_getattr_np( self, &attr );
3734 #ifdef HAVE_PTHREAD_ATTR_GET_NP
3735 pthread_attr_get_np( self, &attr );
3737 #error "Not implemented"
3740 pthread_attr_getstack( &attr, &staddr, &stsize );
3744 * staddr seems to be wrong for the main thread, so we keep the value in
3747 tls->stack_size = stsize;
3749 /* Setup an alternate signal stack */
3750 tls->signal_stack = g_malloc (SIGNAL_STACK_SIZE);
3751 tls->signal_stack_size = SIGNAL_STACK_SIZE;
3753 sa.ss_sp = tls->signal_stack;
3754 sa.ss_size = SIGNAL_STACK_SIZE;
3755 sa.ss_flags = SS_ONSTACK;
3756 sigaltstack (&sa, NULL);
3761 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
3763 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3764 struct sigaltstack sa;
3766 sa.ss_sp = tls->signal_stack;
3767 sa.ss_size = SIGNAL_STACK_SIZE;
3768 sa.ss_flags = SS_DISABLE;
3769 sigaltstack (&sa, NULL);
3771 if (tls->signal_stack)
3772 g_free (tls->signal_stack);
3777 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
3780 /* add the this argument */
3781 if (this_reg != -1) {
3783 MONO_INST_NEW (cfg, this, OP_OUTARG);
3784 this->type = this_type;
3785 this->sreg1 = this_reg;
3786 mono_bblock_add_inst (cfg->cbb, this);
3791 MONO_INST_NEW (cfg, vtarg, OP_OUTARG);
3792 vtarg->type = STACK_MP;
3793 vtarg->sreg1 = vt_reg;
3794 mono_bblock_add_inst (cfg->cbb, vtarg);
3800 mono_arch_get_opcode_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
3802 if (cmethod->klass == mono_defaults.math_class) {
3803 if (strcmp (cmethod->name, "Sin") == 0)
3805 else if (strcmp (cmethod->name, "Cos") == 0)
3807 else if (strcmp (cmethod->name, "Tan") == 0)
3809 else if (strcmp (cmethod->name, "Atan") == 0)
3811 else if (strcmp (cmethod->name, "Sqrt") == 0)
3813 else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8)
3816 /* OP_FREM is not IEEE compatible */
3817 else if (strcmp (cmethod->name, "IEEERemainder") == 0)
3830 mono_arch_print_tree (MonoInst *tree, int arity)