2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/abi-details.h>
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/metadata/gc-internal.h>
27 #include <mono/utils/mono-math.h>
28 #include <mono/utils/mono-counters.h>
29 #include <mono/utils/mono-mmap.h>
30 #include <mono/utils/mono-memory-model.h>
31 #include <mono/utils/mono-hwcap-x86.h>
41 static gboolean optimize_for_xen = TRUE;
43 #define optimize_for_xen 0
47 /* This mutex protects architecture specific caches */
48 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
49 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
50 static mono_mutex_t mini_arch_mutex;
52 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
57 /* Under windows, the default pinvoke calling convention is stdcall */
58 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
60 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
63 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
66 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
69 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
71 #ifdef __native_client_codegen__
73 /* Default alignment for Native Client is 32-byte. */
74 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
76 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
77 /* Check that alignment doesn't cross an alignment boundary. */
79 mono_arch_nacl_pad (guint8 *code, int pad)
81 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
83 if (pad == 0) return code;
84 /* assertion: alignment cannot cross a block boundary */
85 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
86 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
87 while (pad >= kMaxPadding) {
88 x86_padding (code, kMaxPadding);
91 if (pad != 0) x86_padding (code, pad);
96 mono_arch_nacl_skip_nops (guint8 *code)
102 #endif /* __native_client_codegen__ */
105 * The code generated for sequence points reads from this location, which is
106 * made read-only when single stepping is enabled.
108 static gpointer ss_trigger_page;
110 /* Enabled breakpoints read from this trigger page */
111 static gpointer bp_trigger_page;
114 mono_arch_regname (int reg)
117 case X86_EAX: return "%eax";
118 case X86_EBX: return "%ebx";
119 case X86_ECX: return "%ecx";
120 case X86_EDX: return "%edx";
121 case X86_ESP: return "%esp";
122 case X86_EBP: return "%ebp";
123 case X86_EDI: return "%edi";
124 case X86_ESI: return "%esi";
130 mono_arch_fregname (int reg)
155 mono_arch_xregname (int reg)
180 mono_x86_patch (unsigned char* code, gpointer target)
182 x86_patch (code, (unsigned char*)target);
193 /* gsharedvt argument passed by addr */
205 /* Only if storage == ArgValuetypeInReg */
206 ArgStorage pair_storage [2];
215 gboolean need_stack_align;
216 guint32 stack_align_amount;
217 gboolean vtype_retaddr;
218 /* The index of the vret arg in the argument list */
221 /* Argument space popped by the callee */
222 int callee_stack_pop;
228 #define FLOAT_PARAM_REGS 0
230 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
232 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
237 switch (sig->call_convention) {
238 case MONO_CALL_THISCALL:
239 return thiscall_param_regs;
245 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
246 #define SMALL_STRUCTS_IN_REGS
247 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
251 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
253 ainfo->offset = *stack_size;
255 if (!param_regs || param_regs [*gr] == X86_NREG) {
256 ainfo->storage = ArgOnStack;
258 (*stack_size) += sizeof (gpointer);
261 ainfo->storage = ArgInIReg;
262 ainfo->reg = param_regs [*gr];
268 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
270 ainfo->offset = *stack_size;
272 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
274 ainfo->storage = ArgOnStack;
275 (*stack_size) += sizeof (gpointer) * 2;
280 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
282 ainfo->offset = *stack_size;
284 if (*gr >= FLOAT_PARAM_REGS) {
285 ainfo->storage = ArgOnStack;
286 (*stack_size) += is_double ? 8 : 4;
287 ainfo->nslots = is_double ? 2 : 1;
290 /* A double register */
292 ainfo->storage = ArgInDoubleSSEReg;
294 ainfo->storage = ArgInFloatSSEReg;
302 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
304 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
309 klass = mono_class_from_mono_type (type);
310 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
312 #ifdef SMALL_STRUCTS_IN_REGS
313 if (sig->pinvoke && is_return) {
314 MonoMarshalType *info;
317 * the exact rules are not very well documented, the code below seems to work with the
318 * code generated by gcc 3.3.3 -mno-cygwin.
320 info = mono_marshal_load_type_info (klass);
323 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
325 /* Special case structs with only a float member */
326 if (info->num_fields == 1) {
327 int ftype = mini_type_get_underlying_type (gsctx, info->fields [0].field->type)->type;
328 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
329 ainfo->storage = ArgValuetypeInReg;
330 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
333 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
334 ainfo->storage = ArgValuetypeInReg;
335 ainfo->pair_storage [0] = ArgOnFloatFpStack;
339 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
340 ainfo->storage = ArgValuetypeInReg;
341 ainfo->pair_storage [0] = ArgInIReg;
342 ainfo->pair_regs [0] = return_regs [0];
343 if (info->native_size > 4) {
344 ainfo->pair_storage [1] = ArgInIReg;
345 ainfo->pair_regs [1] = return_regs [1];
352 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
353 g_assert (size <= 4);
354 ainfo->storage = ArgValuetypeInReg;
355 ainfo->reg = param_regs [*gr];
360 ainfo->offset = *stack_size;
361 ainfo->storage = ArgOnStack;
362 *stack_size += ALIGN_TO (size, sizeof (gpointer));
363 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
369 * Obtain information about a call according to the calling convention.
370 * For x86 ELF, see the "System V Application Binary Interface Intel386
371 * Architecture Processor Supplment, Fourth Edition" document for more
373 * For x86 win32, see ???.
376 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
378 guint32 i, gr, fr, pstart;
379 const guint32 *param_regs;
381 int n = sig->hasthis + sig->param_count;
382 guint32 stack_size = 0;
383 gboolean is_pinvoke = sig->pinvoke;
389 param_regs = callconv_param_regs(sig);
393 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
394 switch (ret_type->type) {
404 case MONO_TYPE_FNPTR:
405 case MONO_TYPE_CLASS:
406 case MONO_TYPE_OBJECT:
407 case MONO_TYPE_SZARRAY:
408 case MONO_TYPE_ARRAY:
409 case MONO_TYPE_STRING:
410 cinfo->ret.storage = ArgInIReg;
411 cinfo->ret.reg = X86_EAX;
415 cinfo->ret.storage = ArgInIReg;
416 cinfo->ret.reg = X86_EAX;
417 cinfo->ret.is_pair = TRUE;
420 cinfo->ret.storage = ArgOnFloatFpStack;
423 cinfo->ret.storage = ArgOnDoubleFpStack;
425 case MONO_TYPE_GENERICINST:
426 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
427 cinfo->ret.storage = ArgInIReg;
428 cinfo->ret.reg = X86_EAX;
431 if (mini_is_gsharedvt_type_gsctx (gsctx, ret_type)) {
432 cinfo->ret.storage = ArgOnStack;
433 cinfo->vtype_retaddr = TRUE;
437 case MONO_TYPE_VALUETYPE:
438 case MONO_TYPE_TYPEDBYREF: {
439 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
441 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
442 if (cinfo->ret.storage == ArgOnStack) {
443 cinfo->vtype_retaddr = TRUE;
444 /* The caller passes the address where the value is stored */
450 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ret_type));
451 cinfo->ret.storage = ArgOnStack;
452 cinfo->vtype_retaddr = TRUE;
455 cinfo->ret.storage = ArgNone;
458 g_error ("Can't handle as return value 0x%x", ret_type->type);
464 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
465 * the first argument, allowing 'this' to be always passed in the first arg reg.
466 * Also do this if the first argument is a reference type, since virtual calls
467 * are sometimes made using calli without sig->hasthis set, like in the delegate
470 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
472 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
474 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
477 cinfo->vret_arg_offset = stack_size;
478 add_general (&gr, NULL, &stack_size, &cinfo->ret);
479 cinfo->vret_arg_index = 1;
483 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
485 if (cinfo->vtype_retaddr)
486 add_general (&gr, NULL, &stack_size, &cinfo->ret);
489 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
490 fr = FLOAT_PARAM_REGS;
492 /* Emit the signature cookie just before the implicit arguments */
493 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
496 for (i = pstart; i < sig->param_count; ++i) {
497 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
500 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
501 /* We allways pass the sig cookie on the stack for simplicity */
503 * Prevent implicit arguments + the sig cookie from being passed
506 fr = FLOAT_PARAM_REGS;
508 /* Emit the signature cookie just before the implicit arguments */
509 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
512 if (sig->params [i]->byref) {
513 add_general (&gr, param_regs, &stack_size, ainfo);
516 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
517 switch (ptype->type) {
520 add_general (&gr, param_regs, &stack_size, ainfo);
524 add_general (&gr, param_regs, &stack_size, ainfo);
528 add_general (&gr, param_regs, &stack_size, ainfo);
533 case MONO_TYPE_FNPTR:
534 case MONO_TYPE_CLASS:
535 case MONO_TYPE_OBJECT:
536 case MONO_TYPE_STRING:
537 case MONO_TYPE_SZARRAY:
538 case MONO_TYPE_ARRAY:
539 add_general (&gr, param_regs, &stack_size, ainfo);
541 case MONO_TYPE_GENERICINST:
542 if (!mono_type_generic_inst_is_valuetype (ptype)) {
543 add_general (&gr, param_regs, &stack_size, ainfo);
546 if (mini_is_gsharedvt_type_gsctx (gsctx, ptype)) {
547 /* gsharedvt arguments are passed by ref */
548 add_general (&gr, param_regs, &stack_size, ainfo);
549 g_assert (ainfo->storage == ArgOnStack);
550 ainfo->storage = ArgGSharedVt;
554 case MONO_TYPE_VALUETYPE:
555 case MONO_TYPE_TYPEDBYREF:
556 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
560 add_general_pair (&gr, param_regs, &stack_size, ainfo);
563 add_float (&fr, &stack_size, ainfo, FALSE);
566 add_float (&fr, &stack_size, ainfo, TRUE);
570 /* gsharedvt arguments are passed by ref */
571 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ptype));
572 add_general (&gr, param_regs, &stack_size, ainfo);
573 g_assert (ainfo->storage == ArgOnStack);
574 ainfo->storage = ArgGSharedVt;
577 g_error ("unexpected type 0x%x", ptype->type);
578 g_assert_not_reached ();
582 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
583 fr = FLOAT_PARAM_REGS;
585 /* Emit the signature cookie just before the implicit arguments */
586 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
589 if (cinfo->vtype_retaddr) {
590 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
591 cinfo->callee_stack_pop = 4;
592 } else if (CALLCONV_IS_STDCALL (sig) && sig->pinvoke) {
593 /* Have to compensate for the stack space popped by the native callee */
594 cinfo->callee_stack_pop = stack_size;
597 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
598 cinfo->need_stack_align = TRUE;
599 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
600 stack_size += cinfo->stack_align_amount;
603 cinfo->stack_usage = stack_size;
604 cinfo->reg_usage = gr;
605 cinfo->freg_usage = fr;
610 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
612 int n = sig->hasthis + sig->param_count;
616 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
618 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
620 return get_call_info_internal (gsctx, cinfo, sig);
624 * mono_arch_get_argument_info:
625 * @csig: a method signature
626 * @param_count: the number of parameters to consider
627 * @arg_info: an array to store the result infos
629 * Gathers information on parameters such as size, alignment and
630 * padding. arg_info should be large enought to hold param_count + 1 entries.
632 * Returns the size of the argument area on the stack.
633 * This should be signal safe, since it is called from
634 * mono_arch_find_jit_info ().
635 * FIXME: The metadata calls might not be signal safe.
638 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
640 int len, k, args_size = 0;
646 /* Avoid g_malloc as it is not signal safe */
647 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
648 cinfo = (CallInfo*)g_newa (guint8*, len);
649 memset (cinfo, 0, len);
651 cinfo = get_call_info_internal (gsctx, cinfo, csig);
653 arg_info [0].offset = offset;
655 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
656 args_size += sizeof (gpointer);
661 args_size += sizeof (gpointer);
665 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
666 /* Emitted after this */
667 args_size += sizeof (gpointer);
671 arg_info [0].size = args_size;
673 for (k = 0; k < param_count; k++) {
674 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
676 /* ignore alignment for now */
679 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
680 arg_info [k].pad = pad;
682 arg_info [k + 1].pad = 0;
683 arg_info [k + 1].size = size;
685 arg_info [k + 1].offset = offset;
688 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
689 /* Emitted after the first arg */
690 args_size += sizeof (gpointer);
695 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
696 align = MONO_ARCH_FRAME_ALIGNMENT;
699 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
700 arg_info [k].pad = pad;
706 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
708 MonoType *callee_ret;
712 if (cfg->compile_aot && !cfg->full_aot)
713 /* OP_TAILCALL doesn't work with AOT */
716 c1 = get_call_info (NULL, NULL, caller_sig);
717 c2 = get_call_info (NULL, NULL, callee_sig);
719 * Tail calls with more callee stack usage than the caller cannot be supported, since
720 * the extra stack space would be left on the stack after the tail call.
722 res = c1->stack_usage >= c2->stack_usage;
723 callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
724 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
725 /* An address on the callee's stack is passed as the first argument */
735 * Initialize the cpu to execute managed code.
738 mono_arch_cpu_init (void)
740 /* spec compliance requires running with double precision */
744 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
745 fpcw &= ~X86_FPCW_PRECC_MASK;
746 fpcw |= X86_FPCW_PREC_DOUBLE;
747 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
748 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
750 _control87 (_PC_53, MCW_PC);
755 * Initialize architecture specific code.
758 mono_arch_init (void)
760 mono_mutex_init_recursive (&mini_arch_mutex);
762 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
763 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
764 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
766 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
767 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
768 #if defined(ENABLE_GSHAREDVT)
769 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
774 * Cleanup architecture specific code.
777 mono_arch_cleanup (void)
780 mono_vfree (ss_trigger_page, mono_pagesize ());
782 mono_vfree (bp_trigger_page, mono_pagesize ());
783 mono_mutex_destroy (&mini_arch_mutex);
787 * This function returns the optimizations supported on this cpu.
790 mono_arch_cpu_optimizations (guint32 *exclude_mask)
792 #if !defined(__native_client__)
797 if (mono_hwcap_x86_has_cmov) {
798 opts |= MONO_OPT_CMOV;
800 if (mono_hwcap_x86_has_fcmov)
801 opts |= MONO_OPT_FCMOV;
803 *exclude_mask |= MONO_OPT_FCMOV;
805 *exclude_mask |= MONO_OPT_CMOV;
808 if (mono_hwcap_x86_has_sse2)
809 opts |= MONO_OPT_SSE2;
811 *exclude_mask |= MONO_OPT_SSE2;
813 #ifdef MONO_ARCH_SIMD_INTRINSICS
814 /*SIMD intrinsics require at least SSE2.*/
815 if (!mono_hwcap_x86_has_sse2)
816 *exclude_mask |= MONO_OPT_SIMD;
821 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
826 * This function test for all SSE functions supported.
828 * Returns a bitmask corresponding to all supported versions.
832 mono_arch_cpu_enumerate_simd_versions (void)
834 guint32 sse_opts = 0;
836 if (mono_hwcap_x86_has_sse1)
837 sse_opts |= SIMD_VERSION_SSE1;
839 if (mono_hwcap_x86_has_sse2)
840 sse_opts |= SIMD_VERSION_SSE2;
842 if (mono_hwcap_x86_has_sse3)
843 sse_opts |= SIMD_VERSION_SSE3;
845 if (mono_hwcap_x86_has_ssse3)
846 sse_opts |= SIMD_VERSION_SSSE3;
848 if (mono_hwcap_x86_has_sse41)
849 sse_opts |= SIMD_VERSION_SSE41;
851 if (mono_hwcap_x86_has_sse42)
852 sse_opts |= SIMD_VERSION_SSE42;
854 if (mono_hwcap_x86_has_sse4a)
855 sse_opts |= SIMD_VERSION_SSE4a;
861 * Determine whenever the trap whose info is in SIGINFO is caused by
865 mono_arch_is_int_overflow (void *sigctx, void *info)
870 mono_sigctx_to_monoctx (sigctx, &ctx);
872 ip = (guint8*)ctx.eip;
874 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
878 switch (x86_modrm_rm (ip [1])) {
898 g_assert_not_reached ();
910 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
915 for (i = 0; i < cfg->num_varinfo; i++) {
916 MonoInst *ins = cfg->varinfo [i];
917 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
920 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
923 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
924 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
927 /* we dont allocate I1 to registers because there is no simply way to sign extend
928 * 8bit quantities in caller saved registers on x86 */
929 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
930 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
931 g_assert (i == vmv->idx);
932 vars = g_list_prepend (vars, vmv);
936 vars = mono_varlist_sort (cfg, vars, 0);
942 mono_arch_get_global_int_regs (MonoCompile *cfg)
946 /* we can use 3 registers for global allocation */
947 regs = g_list_prepend (regs, (gpointer)X86_EBX);
948 regs = g_list_prepend (regs, (gpointer)X86_ESI);
949 regs = g_list_prepend (regs, (gpointer)X86_EDI);
955 * mono_arch_regalloc_cost:
957 * Return the cost, in number of memory references, of the action of
958 * allocating the variable VMV into a register during global register
962 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
964 MonoInst *ins = cfg->varinfo [vmv->idx];
966 if (cfg->method->save_lmf)
967 /* The register is already saved */
968 return (ins->opcode == OP_ARG) ? 1 : 0;
970 /* push+pop+possible load if it is an argument */
971 return (ins->opcode == OP_ARG) ? 3 : 2;
975 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
977 static int inited = FALSE;
978 static int count = 0;
980 if (cfg->arch.need_stack_frame_inited) {
981 g_assert (cfg->arch.need_stack_frame == flag);
985 cfg->arch.need_stack_frame = flag;
986 cfg->arch.need_stack_frame_inited = TRUE;
992 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
997 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
1001 needs_stack_frame (MonoCompile *cfg)
1003 MonoMethodSignature *sig;
1004 MonoMethodHeader *header;
1005 gboolean result = FALSE;
1007 #if defined(__APPLE__)
1008 /*OSX requires stack frame code to have the correct alignment. */
1012 if (cfg->arch.need_stack_frame_inited)
1013 return cfg->arch.need_stack_frame;
1015 header = cfg->header;
1016 sig = mono_method_signature (cfg->method);
1018 if (cfg->disable_omit_fp)
1020 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1022 else if (cfg->method->save_lmf)
1024 else if (cfg->stack_offset)
1026 else if (cfg->param_area)
1028 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1030 else if (header->num_clauses)
1032 else if (sig->param_count + sig->hasthis)
1034 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1036 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1037 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1040 set_needs_stack_frame (cfg, result);
1042 return cfg->arch.need_stack_frame;
1046 * Set var information according to the calling convention. X86 version.
1047 * The locals var stuff should most likely be split in another method.
1050 mono_arch_allocate_vars (MonoCompile *cfg)
1052 MonoMethodSignature *sig;
1053 MonoMethodHeader *header;
1055 guint32 locals_stack_size, locals_stack_align;
1060 header = cfg->header;
1061 sig = mono_method_signature (cfg->method);
1063 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1065 cfg->frame_reg = X86_EBP;
1068 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1069 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1070 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1073 /* Reserve space to save LMF and caller saved registers */
1075 if (cfg->method->save_lmf) {
1076 /* The LMF var is allocated normally */
1078 if (cfg->used_int_regs & (1 << X86_EBX)) {
1082 if (cfg->used_int_regs & (1 << X86_EDI)) {
1086 if (cfg->used_int_regs & (1 << X86_ESI)) {
1091 switch (cinfo->ret.storage) {
1092 case ArgValuetypeInReg:
1093 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1095 cfg->ret->opcode = OP_REGOFFSET;
1096 cfg->ret->inst_basereg = X86_EBP;
1097 cfg->ret->inst_offset = - offset;
1103 /* Allocate locals */
1104 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1105 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1106 char *mname = mono_method_full_name (cfg->method, TRUE);
1107 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1108 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1112 if (locals_stack_align) {
1113 int prev_offset = offset;
1115 offset += (locals_stack_align - 1);
1116 offset &= ~(locals_stack_align - 1);
1118 while (prev_offset < offset) {
1120 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1123 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1124 cfg->locals_max_stack_offset = - offset;
1126 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1127 * have locals larger than 8 bytes we need to make sure that
1128 * they have the appropriate offset.
1130 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1131 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1132 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1133 if (offsets [i] != -1) {
1134 MonoInst *inst = cfg->varinfo [i];
1135 inst->opcode = OP_REGOFFSET;
1136 inst->inst_basereg = X86_EBP;
1137 inst->inst_offset = - (offset + offsets [i]);
1138 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1141 offset += locals_stack_size;
1145 * Allocate arguments+return value
1148 switch (cinfo->ret.storage) {
1150 if (cfg->vret_addr) {
1152 * In the new IR, the cfg->vret_addr variable represents the
1153 * vtype return value.
1155 cfg->vret_addr->opcode = OP_REGOFFSET;
1156 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1157 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1158 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1159 printf ("vret_addr =");
1160 mono_print_ins (cfg->vret_addr);
1163 cfg->ret->opcode = OP_REGOFFSET;
1164 cfg->ret->inst_basereg = X86_EBP;
1165 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1168 case ArgValuetypeInReg:
1171 cfg->ret->opcode = OP_REGVAR;
1172 cfg->ret->inst_c0 = cinfo->ret.reg;
1173 cfg->ret->dreg = cinfo->ret.reg;
1176 case ArgOnFloatFpStack:
1177 case ArgOnDoubleFpStack:
1180 g_assert_not_reached ();
1183 if (sig->call_convention == MONO_CALL_VARARG) {
1184 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1185 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1188 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1189 ArgInfo *ainfo = &cinfo->args [i];
1190 inst = cfg->args [i];
1191 if (inst->opcode != OP_REGVAR) {
1192 inst->opcode = OP_REGOFFSET;
1193 inst->inst_basereg = X86_EBP;
1195 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1198 cfg->stack_offset = offset;
1202 mono_arch_create_vars (MonoCompile *cfg)
1205 MonoMethodSignature *sig;
1208 sig = mono_method_signature (cfg->method);
1210 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1211 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1213 if (cinfo->ret.storage == ArgValuetypeInReg)
1214 cfg->ret_var_is_local = TRUE;
1215 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (cfg, sig_ret))) {
1216 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1219 if (cfg->method->save_lmf) {
1220 cfg->create_lmf_var = TRUE;
1223 cfg->lmf_ir_mono_lmf = TRUE;
1227 cfg->arch_eh_jit_info = 1;
1231 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1232 * so we try to do it just once when we have multiple fp arguments in a row.
1233 * We don't use this mechanism generally because for int arguments the generated code
1234 * is slightly bigger and new generation cpus optimize away the dependency chains
1235 * created by push instructions on the esp value.
1236 * fp_arg_setup is the first argument in the execution sequence where the esp register
1239 static G_GNUC_UNUSED int
1240 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1245 for (; start_arg < sig->param_count; ++start_arg) {
1246 t = mini_replace_type (sig->params [start_arg]);
1247 if (!t->byref && t->type == MONO_TYPE_R8) {
1248 fp_space += sizeof (double);
1249 *fp_arg_setup = start_arg;
1258 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1260 MonoMethodSignature *tmp_sig;
1264 * mono_ArgIterator_Setup assumes the signature cookie is
1265 * passed first and all the arguments which were before it are
1266 * passed on the stack after the signature. So compensate by
1267 * passing a different signature.
1269 tmp_sig = mono_metadata_signature_dup (call->signature);
1270 tmp_sig->param_count -= call->signature->sentinelpos;
1271 tmp_sig->sentinelpos = 0;
1272 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1274 if (cfg->compile_aot) {
1275 sig_reg = mono_alloc_ireg (cfg);
1276 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1277 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1279 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1285 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1290 LLVMCallInfo *linfo;
1291 MonoType *t, *sig_ret;
1293 n = sig->param_count + sig->hasthis;
1295 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1298 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1301 * LLVM always uses the native ABI while we use our own ABI, the
1302 * only difference is the handling of vtypes:
1303 * - we only pass/receive them in registers in some cases, and only
1304 * in 1 or 2 integer registers.
1306 if (cinfo->ret.storage == ArgValuetypeInReg) {
1308 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1309 cfg->disable_llvm = TRUE;
1313 cfg->exception_message = g_strdup ("vtype ret in call");
1314 cfg->disable_llvm = TRUE;
1316 linfo->ret.storage = LLVMArgVtypeInReg;
1317 for (j = 0; j < 2; ++j)
1318 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1322 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage == ArgInIReg) {
1323 /* Vtype returned using a hidden argument */
1324 linfo->ret.storage = LLVMArgVtypeRetAddr;
1325 linfo->vret_arg_index = cinfo->vret_arg_index;
1328 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage != ArgInIReg) {
1330 cfg->exception_message = g_strdup ("vtype ret in call");
1331 cfg->disable_llvm = TRUE;
1334 for (i = 0; i < n; ++i) {
1335 ainfo = cinfo->args + i;
1337 if (i >= sig->hasthis)
1338 t = sig->params [i - sig->hasthis];
1340 t = &mono_defaults.int_class->byval_arg;
1342 linfo->args [i].storage = LLVMArgNone;
1344 switch (ainfo->storage) {
1346 linfo->args [i].storage = LLVMArgInIReg;
1348 case ArgInDoubleSSEReg:
1349 case ArgInFloatSSEReg:
1350 linfo->args [i].storage = LLVMArgInFPReg;
1353 if (mini_type_is_vtype (cfg, t)) {
1354 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1355 /* LLVM seems to allocate argument space for empty structures too */
1356 linfo->args [i].storage = LLVMArgNone;
1358 linfo->args [i].storage = LLVMArgVtypeByVal;
1360 linfo->args [i].storage = LLVMArgInIReg;
1362 if (t->type == MONO_TYPE_R4)
1363 linfo->args [i].storage = LLVMArgInFPReg;
1364 else if (t->type == MONO_TYPE_R8)
1365 linfo->args [i].storage = LLVMArgInFPReg;
1369 case ArgValuetypeInReg:
1371 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1372 cfg->disable_llvm = TRUE;
1376 cfg->exception_message = g_strdup ("vtype arg");
1377 cfg->disable_llvm = TRUE;
1379 linfo->args [i].storage = LLVMArgVtypeInReg;
1380 for (j = 0; j < 2; ++j)
1381 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1385 linfo->args [i].storage = LLVMArgGSharedVt;
1388 cfg->exception_message = g_strdup ("ainfo->storage");
1389 cfg->disable_llvm = TRUE;
1399 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1401 if (cfg->compute_gc_maps) {
1404 /* Needs checking if the feature will be enabled again */
1405 g_assert_not_reached ();
1407 /* On x86, the offsets are from the sp value before the start of the call sequence */
1409 t = &mono_defaults.int_class->byval_arg;
1410 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1415 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1419 MonoMethodSignature *sig;
1422 int sentinelpos = 0, sp_offset = 0;
1424 sig = call->signature;
1425 n = sig->param_count + sig->hasthis;
1426 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1428 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1429 call->call_info = cinfo;
1431 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1432 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1434 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1435 if (cinfo->ret.storage == ArgValuetypeInReg) {
1437 * Tell the JIT to use a more efficient calling convention: call using
1438 * OP_CALL, compute the result location after the call, and save the
1441 call->vret_in_reg = TRUE;
1442 #if defined(__APPLE__)
1443 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1444 call->vret_in_reg_fp = TRUE;
1447 NULLIFY_INS (call->vret_var);
1451 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1453 /* Handle the case where there are no implicit arguments */
1454 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1455 emit_sig_cookie (cfg, call, cinfo);
1456 sp_offset = cinfo->sig_cookie.offset;
1457 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1460 /* Arguments are pushed in the reverse order */
1461 for (i = n - 1; i >= 0; i --) {
1462 ArgInfo *ainfo = cinfo->args + i;
1463 MonoType *orig_type, *t;
1466 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1469 /* Push the vret arg before the first argument */
1470 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1471 vtarg->type = STACK_MP;
1472 vtarg->inst_destbasereg = X86_ESP;
1473 vtarg->sreg1 = call->vret_var->dreg;
1474 vtarg->inst_offset = cinfo->ret.offset;
1475 MONO_ADD_INS (cfg->cbb, vtarg);
1476 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1479 if (i >= sig->hasthis)
1480 t = sig->params [i - sig->hasthis];
1482 t = &mono_defaults.int_class->byval_arg;
1484 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1486 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1488 in = call->args [i];
1489 arg->cil_code = in->cil_code;
1490 arg->sreg1 = in->dreg;
1491 arg->type = in->type;
1493 g_assert (in->dreg != -1);
1495 if (ainfo->storage == ArgGSharedVt) {
1496 arg->opcode = OP_OUTARG_VT;
1497 arg->sreg1 = in->dreg;
1498 arg->klass = in->klass;
1499 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1500 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1502 MONO_ADD_INS (cfg->cbb, arg);
1503 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1507 g_assert (in->klass);
1509 if (t->type == MONO_TYPE_TYPEDBYREF) {
1510 size = sizeof (MonoTypedRef);
1511 align = sizeof (gpointer);
1514 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1518 arg->opcode = OP_OUTARG_VT;
1519 arg->sreg1 = in->dreg;
1520 arg->klass = in->klass;
1521 arg->backend.size = size;
1522 arg->inst_p0 = call;
1523 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1524 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1526 MONO_ADD_INS (cfg->cbb, arg);
1527 if (ainfo->storage != ArgValuetypeInReg) {
1528 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1532 switch (ainfo->storage) {
1535 if (t->type == MONO_TYPE_R4) {
1536 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1538 } else if (t->type == MONO_TYPE_R8) {
1539 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1541 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1542 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, in->dreg + 2);
1543 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg + 1);
1546 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1550 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1555 arg->opcode = OP_MOVE;
1556 arg->dreg = ainfo->reg;
1557 MONO_ADD_INS (cfg->cbb, arg);
1561 g_assert_not_reached ();
1564 if (cfg->compute_gc_maps) {
1566 /* FIXME: The == STACK_OBJ check might be fragile ? */
1567 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1569 if (call->need_unbox_trampoline)
1570 /* The unbox trampoline transforms this into a managed pointer */
1571 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.int_class->this_arg);
1573 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.object_class->byval_arg);
1575 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1579 for (j = 0; j < argsize; j += 4)
1580 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1585 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1586 /* Emit the signature cookie just before the implicit arguments */
1587 emit_sig_cookie (cfg, call, cinfo);
1588 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1592 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1595 if (cinfo->ret.storage == ArgValuetypeInReg) {
1598 else if (cinfo->ret.storage == ArgInIReg) {
1600 /* The return address is passed in a register */
1601 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1602 vtarg->sreg1 = call->inst.dreg;
1603 vtarg->dreg = mono_alloc_ireg (cfg);
1604 MONO_ADD_INS (cfg->cbb, vtarg);
1606 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1607 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1608 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1609 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1613 call->stack_usage = cinfo->stack_usage;
1614 call->stack_align_amount = cinfo->stack_align_amount;
1618 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1620 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1621 ArgInfo *ainfo = ins->inst_p1;
1622 int size = ins->backend.size;
1624 if (ainfo->storage == ArgValuetypeInReg) {
1625 int dreg = mono_alloc_ireg (cfg);
1628 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1631 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1634 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1638 g_assert_not_reached ();
1640 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1643 if (cfg->gsharedvt && mini_is_gsharedvt_klass (cfg, ins->klass)) {
1645 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1646 } else if (size <= 4) {
1647 int dreg = mono_alloc_ireg (cfg);
1648 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1649 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1650 } else if (size <= 20) {
1651 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1653 // FIXME: Code growth
1654 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1660 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1662 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1665 if (ret->type == MONO_TYPE_R4) {
1666 if (COMPILE_LLVM (cfg))
1667 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1670 } else if (ret->type == MONO_TYPE_R8) {
1671 if (COMPILE_LLVM (cfg))
1672 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1675 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1676 if (COMPILE_LLVM (cfg))
1677 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1679 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1680 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1686 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1690 * Allow tracing to work with this interface (with an optional argument)
1693 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1697 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1698 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1700 /* if some args are passed in registers, we need to save them here */
1701 x86_push_reg (code, X86_EBP);
1703 if (cfg->compile_aot) {
1704 x86_push_imm (code, cfg->method);
1705 x86_mov_reg_imm (code, X86_EAX, func);
1706 x86_call_reg (code, X86_EAX);
1708 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1709 x86_push_imm (code, cfg->method);
1710 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1711 x86_call_code (code, 0);
1713 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1727 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1730 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1731 MonoMethod *method = cfg->method;
1732 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1734 switch (ret_type->type) {
1735 case MONO_TYPE_VOID:
1736 /* special case string .ctor icall */
1737 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1738 save_mode = SAVE_EAX;
1739 stack_usage = enable_arguments ? 8 : 4;
1741 save_mode = SAVE_NONE;
1745 save_mode = SAVE_EAX_EDX;
1746 stack_usage = enable_arguments ? 16 : 8;
1750 save_mode = SAVE_FP;
1751 stack_usage = enable_arguments ? 16 : 8;
1753 case MONO_TYPE_GENERICINST:
1754 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1755 save_mode = SAVE_EAX;
1756 stack_usage = enable_arguments ? 8 : 4;
1760 case MONO_TYPE_VALUETYPE:
1761 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1762 save_mode = SAVE_STRUCT;
1763 stack_usage = enable_arguments ? 4 : 0;
1766 save_mode = SAVE_EAX;
1767 stack_usage = enable_arguments ? 8 : 4;
1771 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1773 switch (save_mode) {
1775 x86_push_reg (code, X86_EDX);
1776 x86_push_reg (code, X86_EAX);
1777 if (enable_arguments) {
1778 x86_push_reg (code, X86_EDX);
1779 x86_push_reg (code, X86_EAX);
1784 x86_push_reg (code, X86_EAX);
1785 if (enable_arguments) {
1786 x86_push_reg (code, X86_EAX);
1791 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1792 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1793 if (enable_arguments) {
1794 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1795 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1800 if (enable_arguments) {
1801 x86_push_membase (code, X86_EBP, 8);
1810 if (cfg->compile_aot) {
1811 x86_push_imm (code, method);
1812 x86_mov_reg_imm (code, X86_EAX, func);
1813 x86_call_reg (code, X86_EAX);
1815 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1816 x86_push_imm (code, method);
1817 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1818 x86_call_code (code, 0);
1821 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1823 switch (save_mode) {
1825 x86_pop_reg (code, X86_EAX);
1826 x86_pop_reg (code, X86_EDX);
1829 x86_pop_reg (code, X86_EAX);
1832 x86_fld_membase (code, X86_ESP, 0, TRUE);
1833 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1840 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1845 #define EMIT_COND_BRANCH(ins,cond,sign) \
1846 if (ins->inst_true_bb->native_offset) { \
1847 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1849 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1850 if ((cfg->opt & MONO_OPT_BRANCH) && \
1851 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1852 x86_branch8 (code, cond, 0, sign); \
1854 x86_branch32 (code, cond, 0, sign); \
1858 * Emit an exception if condition is fail and
1859 * if possible do a directly branch to target
1861 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1863 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1864 if (tins == NULL) { \
1865 mono_add_patch_info (cfg, code - cfg->native_code, \
1866 MONO_PATCH_INFO_EXC, exc_name); \
1867 x86_branch32 (code, cond, 0, signed); \
1869 EMIT_COND_BRANCH (tins, cond, signed); \
1873 #define EMIT_FPCOMPARE(code) do { \
1874 x86_fcompp (code); \
1875 x86_fnstsw (code); \
1880 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1882 gboolean needs_paddings = TRUE;
1884 MonoJumpInfo *jinfo = NULL;
1886 if (cfg->abs_patches) {
1887 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1888 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1889 needs_paddings = FALSE;
1892 if (cfg->compile_aot)
1893 needs_paddings = FALSE;
1894 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1895 This is required for code patching to be safe on SMP machines.
1897 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1898 #ifndef __native_client_codegen__
1899 if (needs_paddings && pad_size)
1900 x86_padding (code, 4 - pad_size);
1903 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1904 x86_call_code (code, 0);
1909 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1912 * mono_peephole_pass_1:
1914 * Perform peephole opts which should/can be performed before local regalloc
1917 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1921 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1922 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1924 switch (ins->opcode) {
1927 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1929 * X86_LEA is like ADD, but doesn't have the
1930 * sreg1==dreg restriction.
1932 ins->opcode = OP_X86_LEA_MEMBASE;
1933 ins->inst_basereg = ins->sreg1;
1934 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1935 ins->opcode = OP_X86_INC_REG;
1939 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1940 ins->opcode = OP_X86_LEA_MEMBASE;
1941 ins->inst_basereg = ins->sreg1;
1942 ins->inst_imm = -ins->inst_imm;
1943 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1944 ins->opcode = OP_X86_DEC_REG;
1946 case OP_COMPARE_IMM:
1947 case OP_ICOMPARE_IMM:
1948 /* OP_COMPARE_IMM (reg, 0)
1950 * OP_X86_TEST_NULL (reg)
1953 ins->opcode = OP_X86_TEST_NULL;
1955 case OP_X86_COMPARE_MEMBASE_IMM:
1957 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1958 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1960 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1961 * OP_COMPARE_IMM reg, imm
1963 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1965 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1966 ins->inst_basereg == last_ins->inst_destbasereg &&
1967 ins->inst_offset == last_ins->inst_offset) {
1968 ins->opcode = OP_COMPARE_IMM;
1969 ins->sreg1 = last_ins->sreg1;
1971 /* check if we can remove cmp reg,0 with test null */
1973 ins->opcode = OP_X86_TEST_NULL;
1977 case OP_X86_PUSH_MEMBASE:
1978 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1979 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1980 ins->inst_basereg == last_ins->inst_destbasereg &&
1981 ins->inst_offset == last_ins->inst_offset) {
1982 ins->opcode = OP_X86_PUSH;
1983 ins->sreg1 = last_ins->sreg1;
1988 mono_peephole_ins (bb, ins);
1993 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1997 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1998 switch (ins->opcode) {
2000 /* reg = 0 -> XOR (reg, reg) */
2001 /* XOR sets cflags on x86, so we cant do it always */
2002 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2005 ins->opcode = OP_IXOR;
2006 ins->sreg1 = ins->dreg;
2007 ins->sreg2 = ins->dreg;
2010 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2011 * since it takes 3 bytes instead of 7.
2013 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
2014 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2015 ins2->opcode = OP_STORE_MEMBASE_REG;
2016 ins2->sreg1 = ins->dreg;
2018 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2019 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2020 ins2->sreg1 = ins->dreg;
2022 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2023 /* Continue iteration */
2032 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2033 ins->opcode = OP_X86_INC_REG;
2037 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2038 ins->opcode = OP_X86_DEC_REG;
2042 mono_peephole_ins (bb, ins);
2047 * mono_arch_lowering_pass:
2049 * Converts complex opcodes into simpler ones so that each IR instruction
2050 * corresponds to one machine instruction.
2053 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2055 MonoInst *ins, *next;
2058 * FIXME: Need to add more instructions, but the current machine
2059 * description can't model some parts of the composite instructions like
2062 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2063 switch (ins->opcode) {
2066 case OP_IDIV_UN_IMM:
2067 case OP_IREM_UN_IMM:
2069 * Keep the cases where we could generated optimized code, otherwise convert
2070 * to the non-imm variant.
2072 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2074 mono_decompose_op_imm (cfg, bb, ins);
2081 bb->max_vreg = cfg->next_vreg;
2085 branch_cc_table [] = {
2086 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2087 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2088 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2091 /* Maps CMP_... constants to X86_CC_... constants */
2094 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2095 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2099 cc_signed_table [] = {
2100 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2101 FALSE, FALSE, FALSE, FALSE
2104 static unsigned char*
2105 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2107 #define XMM_TEMP_REG 0
2108 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2109 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2110 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2111 /* optimize by assigning a local var for this use so we avoid
2112 * the stack manipulations */
2113 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2114 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2115 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2116 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2117 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2119 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2121 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2124 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2125 x86_fnstcw_membase(code, X86_ESP, 0);
2126 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2127 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2128 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2129 x86_fldcw_membase (code, X86_ESP, 2);
2131 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2132 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2133 x86_pop_reg (code, dreg);
2134 /* FIXME: need the high register
2135 * x86_pop_reg (code, dreg_high);
2138 x86_push_reg (code, X86_EAX); // SP = SP - 4
2139 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2140 x86_pop_reg (code, dreg);
2142 x86_fldcw_membase (code, X86_ESP, 0);
2143 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2146 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2148 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2152 static unsigned char*
2153 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2155 int sreg = tree->sreg1;
2156 int need_touch = FALSE;
2158 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2167 * If requested stack size is larger than one page,
2168 * perform stack-touch operation
2171 * Generate stack probe code.
2172 * Under Windows, it is necessary to allocate one page at a time,
2173 * "touching" stack after each successful sub-allocation. This is
2174 * because of the way stack growth is implemented - there is a
2175 * guard page before the lowest stack page that is currently commited.
2176 * Stack normally grows sequentially so OS traps access to the
2177 * guard page and commits more pages when needed.
2179 x86_test_reg_imm (code, sreg, ~0xFFF);
2180 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2182 br[2] = code; /* loop */
2183 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2184 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2187 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2188 * that follows only initializes the last part of the area.
2190 /* Same as the init code below with size==0x1000 */
2191 if (tree->flags & MONO_INST_INIT) {
2192 x86_push_reg (code, X86_EAX);
2193 x86_push_reg (code, X86_ECX);
2194 x86_push_reg (code, X86_EDI);
2195 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2196 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2197 if (cfg->param_area)
2198 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2200 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2202 x86_prefix (code, X86_REP_PREFIX);
2204 x86_pop_reg (code, X86_EDI);
2205 x86_pop_reg (code, X86_ECX);
2206 x86_pop_reg (code, X86_EAX);
2209 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2210 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2211 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2212 x86_patch (br[3], br[2]);
2213 x86_test_reg_reg (code, sreg, sreg);
2214 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2215 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2217 br[1] = code; x86_jump8 (code, 0);
2219 x86_patch (br[0], code);
2220 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2221 x86_patch (br[1], code);
2222 x86_patch (br[4], code);
2225 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2227 if (tree->flags & MONO_INST_INIT) {
2229 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2230 x86_push_reg (code, X86_EAX);
2233 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2234 x86_push_reg (code, X86_ECX);
2237 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2238 x86_push_reg (code, X86_EDI);
2242 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2243 if (sreg != X86_ECX)
2244 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2245 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2247 if (cfg->param_area)
2248 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2250 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2252 x86_prefix (code, X86_REP_PREFIX);
2255 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2256 x86_pop_reg (code, X86_EDI);
2257 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2258 x86_pop_reg (code, X86_ECX);
2259 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2260 x86_pop_reg (code, X86_EAX);
2267 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2269 /* Move return value to the target register */
2270 switch (ins->opcode) {
2273 case OP_CALL_MEMBASE:
2274 if (ins->dreg != X86_EAX)
2275 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2285 static int tls_gs_offset;
2289 mono_x86_have_tls_get (void)
2292 static gboolean have_tls_get = FALSE;
2293 static gboolean inited = FALSE;
2297 return have_tls_get;
2299 ins = (guint32*)pthread_getspecific;
2301 * We're looking for these two instructions:
2303 * mov 0x4(%esp),%eax
2304 * mov %gs:[offset](,%eax,4),%eax
2306 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2307 tls_gs_offset = ins [2];
2311 return have_tls_get;
2312 #elif defined(TARGET_ANDROID)
2320 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2322 #if defined(__APPLE__)
2323 x86_prefix (code, X86_GS_PREFIX);
2324 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2325 #elif defined(TARGET_WIN32)
2326 g_assert_not_reached ();
2328 x86_prefix (code, X86_GS_PREFIX);
2329 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2335 * mono_x86_emit_tls_get:
2336 * @code: buffer to store code to
2337 * @dreg: hard register where to place the result
2338 * @tls_offset: offset info
2340 * mono_x86_emit_tls_get emits in @code the native code that puts in
2341 * the dreg register the item in the thread local storage identified
2344 * Returns: a pointer to the end of the stored code
2347 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2349 #if defined(__APPLE__)
2350 x86_prefix (code, X86_GS_PREFIX);
2351 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2352 #elif defined(TARGET_WIN32)
2354 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2355 * Journal and/or a disassembly of the TlsGet () function.
2357 x86_prefix (code, X86_FS_PREFIX);
2358 x86_mov_reg_mem (code, dreg, 0x18, 4);
2359 if (tls_offset < 64) {
2360 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2364 g_assert (tls_offset < 0x440);
2365 /* Load TEB->TlsExpansionSlots */
2366 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2367 x86_test_reg_reg (code, dreg, dreg);
2369 x86_branch (code, X86_CC_EQ, code, TRUE);
2370 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2371 x86_patch (buf [0], code);
2374 if (optimize_for_xen) {
2375 x86_prefix (code, X86_GS_PREFIX);
2376 x86_mov_reg_mem (code, dreg, 0, 4);
2377 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2379 x86_prefix (code, X86_GS_PREFIX);
2380 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2387 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2389 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2390 #if defined(__APPLE__) || defined(__linux__)
2391 if (dreg != offset_reg)
2392 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2393 x86_prefix (code, X86_GS_PREFIX);
2394 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2396 g_assert_not_reached ();
2402 mono_x86_emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2404 return emit_tls_get_reg (code, dreg, offset_reg);
2408 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2410 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2412 g_assert_not_reached ();
2413 #elif defined(__APPLE__) || defined(__linux__)
2414 x86_prefix (code, X86_GS_PREFIX);
2415 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2417 g_assert_not_reached ();
2423 * mono_arch_translate_tls_offset:
2425 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2428 mono_arch_translate_tls_offset (int offset)
2431 return tls_gs_offset + (offset * 4);
2440 * Emit code to initialize an LMF structure at LMF_OFFSET.
2443 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2445 /* save all caller saved regs */
2446 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2447 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2448 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2449 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2450 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2451 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2452 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2454 /* save the current IP */
2455 if (cfg->compile_aot) {
2456 /* This pushes the current ip */
2457 x86_call_imm (code, 0);
2458 x86_pop_reg (code, X86_EAX);
2460 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2461 x86_mov_reg_imm (code, X86_EAX, 0);
2463 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2465 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2466 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2467 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2468 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2469 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2470 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2471 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2472 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2473 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2478 #define REAL_PRINT_REG(text,reg) \
2479 mono_assert (reg >= 0); \
2480 x86_push_reg (code, X86_EAX); \
2481 x86_push_reg (code, X86_EDX); \
2482 x86_push_reg (code, X86_ECX); \
2483 x86_push_reg (code, reg); \
2484 x86_push_imm (code, reg); \
2485 x86_push_imm (code, text " %d %p\n"); \
2486 x86_mov_reg_imm (code, X86_EAX, printf); \
2487 x86_call_reg (code, X86_EAX); \
2488 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2489 x86_pop_reg (code, X86_ECX); \
2490 x86_pop_reg (code, X86_EDX); \
2491 x86_pop_reg (code, X86_EAX);
2493 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2494 #ifdef __native__client_codegen__
2495 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2498 /* benchmark and set based on cpu */
2499 #define LOOP_ALIGNMENT 8
2500 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2504 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2509 guint8 *code = cfg->native_code + cfg->code_len;
2512 if (cfg->opt & MONO_OPT_LOOP) {
2513 int pad, align = LOOP_ALIGNMENT;
2514 /* set alignment depending on cpu */
2515 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2517 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2518 x86_padding (code, pad);
2519 cfg->code_len += pad;
2520 bb->native_offset = cfg->code_len;
2523 #ifdef __native_client_codegen__
2525 /* For Native Client, all indirect call/jump targets must be */
2526 /* 32-byte aligned. Exception handler blocks are jumped to */
2527 /* indirectly as well. */
2528 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2529 (bb->flags & BB_EXCEPTION_HANDLER);
2531 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2532 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2533 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2534 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2535 cfg->code_len += pad;
2536 bb->native_offset = cfg->code_len;
2539 #endif /* __native_client_codegen__ */
2540 if (cfg->verbose_level > 2)
2541 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2543 cpos = bb->max_offset;
2545 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
2546 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2547 g_assert (!cfg->compile_aot);
2550 cov->data [bb->dfn].cil_code = bb->cil_code;
2551 /* this is not thread save, but good enough */
2552 x86_inc_mem (code, &cov->data [bb->dfn].count);
2555 offset = code - cfg->native_code;
2557 mono_debug_open_block (cfg, bb, offset);
2559 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2560 x86_breakpoint (code);
2562 MONO_BB_FOR_EACH_INS (bb, ins) {
2563 offset = code - cfg->native_code;
2565 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2567 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2569 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2570 cfg->code_size *= 2;
2571 cfg->native_code = mono_realloc_native_code(cfg);
2572 code = cfg->native_code + offset;
2573 cfg->stat_code_reallocs++;
2576 if (cfg->debug_info)
2577 mono_debug_record_line_number (cfg, ins, offset);
2579 switch (ins->opcode) {
2581 x86_mul_reg (code, ins->sreg2, TRUE);
2584 x86_mul_reg (code, ins->sreg2, FALSE);
2586 case OP_X86_SETEQ_MEMBASE:
2587 case OP_X86_SETNE_MEMBASE:
2588 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2589 ins->inst_basereg, ins->inst_offset, TRUE);
2591 case OP_STOREI1_MEMBASE_IMM:
2592 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2594 case OP_STOREI2_MEMBASE_IMM:
2595 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2597 case OP_STORE_MEMBASE_IMM:
2598 case OP_STOREI4_MEMBASE_IMM:
2599 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2601 case OP_STOREI1_MEMBASE_REG:
2602 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2604 case OP_STOREI2_MEMBASE_REG:
2605 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2607 case OP_STORE_MEMBASE_REG:
2608 case OP_STOREI4_MEMBASE_REG:
2609 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2611 case OP_STORE_MEM_IMM:
2612 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2615 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2619 /* These are created by the cprop pass so they use inst_imm as the source */
2620 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2623 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2626 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2628 case OP_LOAD_MEMBASE:
2629 case OP_LOADI4_MEMBASE:
2630 case OP_LOADU4_MEMBASE:
2631 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2633 case OP_LOADU1_MEMBASE:
2634 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2636 case OP_LOADI1_MEMBASE:
2637 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2639 case OP_LOADU2_MEMBASE:
2640 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2642 case OP_LOADI2_MEMBASE:
2643 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2645 case OP_ICONV_TO_I1:
2647 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2649 case OP_ICONV_TO_I2:
2651 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2653 case OP_ICONV_TO_U1:
2654 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2656 case OP_ICONV_TO_U2:
2657 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2661 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2663 case OP_COMPARE_IMM:
2664 case OP_ICOMPARE_IMM:
2665 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2667 case OP_X86_COMPARE_MEMBASE_REG:
2668 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2670 case OP_X86_COMPARE_MEMBASE_IMM:
2671 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2673 case OP_X86_COMPARE_MEMBASE8_IMM:
2674 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2676 case OP_X86_COMPARE_REG_MEMBASE:
2677 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2679 case OP_X86_COMPARE_MEM_IMM:
2680 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2682 case OP_X86_TEST_NULL:
2683 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2685 case OP_X86_ADD_MEMBASE_IMM:
2686 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2688 case OP_X86_ADD_REG_MEMBASE:
2689 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2691 case OP_X86_SUB_MEMBASE_IMM:
2692 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2694 case OP_X86_SUB_REG_MEMBASE:
2695 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2697 case OP_X86_AND_MEMBASE_IMM:
2698 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2700 case OP_X86_OR_MEMBASE_IMM:
2701 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2703 case OP_X86_XOR_MEMBASE_IMM:
2704 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2706 case OP_X86_ADD_MEMBASE_REG:
2707 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2709 case OP_X86_SUB_MEMBASE_REG:
2710 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2712 case OP_X86_AND_MEMBASE_REG:
2713 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2715 case OP_X86_OR_MEMBASE_REG:
2716 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2718 case OP_X86_XOR_MEMBASE_REG:
2719 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2721 case OP_X86_INC_MEMBASE:
2722 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2724 case OP_X86_INC_REG:
2725 x86_inc_reg (code, ins->dreg);
2727 case OP_X86_DEC_MEMBASE:
2728 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2730 case OP_X86_DEC_REG:
2731 x86_dec_reg (code, ins->dreg);
2733 case OP_X86_MUL_REG_MEMBASE:
2734 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2736 case OP_X86_AND_REG_MEMBASE:
2737 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2739 case OP_X86_OR_REG_MEMBASE:
2740 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2742 case OP_X86_XOR_REG_MEMBASE:
2743 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2746 x86_breakpoint (code);
2748 case OP_RELAXED_NOP:
2749 x86_prefix (code, X86_REP_PREFIX);
2757 case OP_DUMMY_STORE:
2758 case OP_DUMMY_ICONST:
2759 case OP_DUMMY_R8CONST:
2760 case OP_NOT_REACHED:
2763 case OP_IL_SEQ_POINT:
2764 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2766 case OP_SEQ_POINT: {
2769 if (cfg->compile_aot)
2773 * Read from the single stepping trigger page. This will cause a
2774 * SIGSEGV when single stepping is enabled.
2775 * We do this _before_ the breakpoint, so single stepping after
2776 * a breakpoint is hit will step to the next IL offset.
2778 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2779 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2781 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2784 * A placeholder for a possible breakpoint inserted by
2785 * mono_arch_set_breakpoint ().
2787 for (i = 0; i < 6; ++i)
2790 * Add an additional nop so skipping the bp doesn't cause the ip to point
2791 * to another IL offset.
2799 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2803 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2808 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2812 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2817 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2821 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2826 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2830 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2833 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2837 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2841 #if defined( __native_client_codegen__ )
2842 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2843 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2846 * The code is the same for div/rem, the allocator will allocate dreg
2847 * to RAX/RDX as appropriate.
2849 if (ins->sreg2 == X86_EDX) {
2850 /* cdq clobbers this */
2851 x86_push_reg (code, ins->sreg2);
2853 x86_div_membase (code, X86_ESP, 0, TRUE);
2854 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2857 x86_div_reg (code, ins->sreg2, TRUE);
2862 #if defined( __native_client_codegen__ )
2863 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2864 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2866 if (ins->sreg2 == X86_EDX) {
2867 x86_push_reg (code, ins->sreg2);
2868 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2869 x86_div_membase (code, X86_ESP, 0, FALSE);
2870 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2872 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2873 x86_div_reg (code, ins->sreg2, FALSE);
2877 #if defined( __native_client_codegen__ )
2878 if (ins->inst_imm == 0) {
2879 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2880 x86_jump32 (code, 0);
2884 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2886 x86_div_reg (code, ins->sreg2, TRUE);
2889 int power = mono_is_power_of_two (ins->inst_imm);
2891 g_assert (ins->sreg1 == X86_EAX);
2892 g_assert (ins->dreg == X86_EAX);
2893 g_assert (power >= 0);
2896 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2898 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2900 * If the divident is >= 0, this does not nothing. If it is positive, it
2901 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2903 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2904 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2905 } else if (power == 0) {
2906 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2908 /* Based on gcc code */
2910 /* Add compensation for negative dividents */
2912 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2913 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2914 /* Compute remainder */
2915 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2916 /* Remove compensation */
2917 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2922 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2926 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2929 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2933 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2936 g_assert (ins->sreg2 == X86_ECX);
2937 x86_shift_reg (code, X86_SHL, ins->dreg);
2940 g_assert (ins->sreg2 == X86_ECX);
2941 x86_shift_reg (code, X86_SAR, ins->dreg);
2945 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2948 case OP_ISHR_UN_IMM:
2949 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2952 g_assert (ins->sreg2 == X86_ECX);
2953 x86_shift_reg (code, X86_SHR, ins->dreg);
2957 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2960 guint8 *jump_to_end;
2962 /* handle shifts below 32 bits */
2963 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2964 x86_shift_reg (code, X86_SHL, ins->sreg1);
2966 x86_test_reg_imm (code, X86_ECX, 32);
2967 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2969 /* handle shift over 32 bit */
2970 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2971 x86_clear_reg (code, ins->sreg1);
2973 x86_patch (jump_to_end, code);
2977 guint8 *jump_to_end;
2979 /* handle shifts below 32 bits */
2980 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2981 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2983 x86_test_reg_imm (code, X86_ECX, 32);
2984 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2986 /* handle shifts over 31 bits */
2987 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2988 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2990 x86_patch (jump_to_end, code);
2994 guint8 *jump_to_end;
2996 /* handle shifts below 32 bits */
2997 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2998 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
3000 x86_test_reg_imm (code, X86_ECX, 32);
3001 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3003 /* handle shifts over 31 bits */
3004 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3005 x86_clear_reg (code, ins->backend.reg3);
3007 x86_patch (jump_to_end, code);
3011 if (ins->inst_imm >= 32) {
3012 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3013 x86_clear_reg (code, ins->sreg1);
3014 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
3016 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
3017 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
3021 if (ins->inst_imm >= 32) {
3022 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3023 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
3024 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
3026 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3027 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3030 case OP_LSHR_UN_IMM:
3031 if (ins->inst_imm >= 32) {
3032 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3033 x86_clear_reg (code, ins->backend.reg3);
3034 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3036 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3037 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3041 x86_not_reg (code, ins->sreg1);
3044 x86_neg_reg (code, ins->sreg1);
3048 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3052 switch (ins->inst_imm) {
3056 if (ins->dreg != ins->sreg1)
3057 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3058 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3061 /* LEA r1, [r2 + r2*2] */
3062 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3065 /* LEA r1, [r2 + r2*4] */
3066 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3069 /* LEA r1, [r2 + r2*2] */
3071 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3072 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3075 /* LEA r1, [r2 + r2*8] */
3076 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3079 /* LEA r1, [r2 + r2*4] */
3081 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3082 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3085 /* LEA r1, [r2 + r2*2] */
3087 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3088 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3091 /* LEA r1, [r2 + r2*4] */
3092 /* LEA r1, [r1 + r1*4] */
3093 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3094 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3097 /* LEA r1, [r2 + r2*4] */
3099 /* LEA r1, [r1 + r1*4] */
3100 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3101 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3102 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3105 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3110 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3111 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3113 case OP_IMUL_OVF_UN: {
3114 /* the mul operation and the exception check should most likely be split */
3115 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3116 /*g_assert (ins->sreg2 == X86_EAX);
3117 g_assert (ins->dreg == X86_EAX);*/
3118 if (ins->sreg2 == X86_EAX) {
3119 non_eax_reg = ins->sreg1;
3120 } else if (ins->sreg1 == X86_EAX) {
3121 non_eax_reg = ins->sreg2;
3123 /* no need to save since we're going to store to it anyway */
3124 if (ins->dreg != X86_EAX) {
3126 x86_push_reg (code, X86_EAX);
3128 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3129 non_eax_reg = ins->sreg2;
3131 if (ins->dreg == X86_EDX) {
3134 x86_push_reg (code, X86_EAX);
3136 } else if (ins->dreg != X86_EAX) {
3138 x86_push_reg (code, X86_EDX);
3140 x86_mul_reg (code, non_eax_reg, FALSE);
3141 /* save before the check since pop and mov don't change the flags */
3142 if (ins->dreg != X86_EAX)
3143 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3145 x86_pop_reg (code, X86_EDX);
3147 x86_pop_reg (code, X86_EAX);
3148 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3152 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3155 g_assert_not_reached ();
3156 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3157 x86_mov_reg_imm (code, ins->dreg, 0);
3160 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3161 x86_mov_reg_imm (code, ins->dreg, 0);
3163 case OP_LOAD_GOTADDR:
3164 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3165 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3168 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3169 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3171 case OP_X86_PUSH_GOT_ENTRY:
3172 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3173 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3176 if (ins->dreg != ins->sreg1)
3177 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3180 MonoCallInst *call = (MonoCallInst*)ins;
3183 ins->flags |= MONO_INST_GC_CALLSITE;
3184 ins->backend.pc_offset = code - cfg->native_code;
3186 /* reset offset to make max_len work */
3187 offset = code - cfg->native_code;
3189 g_assert (!cfg->method->save_lmf);
3191 /* restore callee saved registers */
3192 for (i = 0; i < X86_NREG; ++i)
3193 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3195 if (cfg->used_int_regs & (1 << X86_ESI)) {
3196 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3199 if (cfg->used_int_regs & (1 << X86_EDI)) {
3200 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3203 if (cfg->used_int_regs & (1 << X86_EBX)) {
3204 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3208 /* Copy arguments on the stack to our argument area */
3209 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3210 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3211 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3214 /* restore ESP/EBP */
3216 offset = code - cfg->native_code;
3217 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3218 x86_jump32 (code, 0);
3220 ins->flags |= MONO_INST_GC_CALLSITE;
3221 cfg->disable_aot = TRUE;
3225 /* ensure ins->sreg1 is not NULL
3226 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3227 * cmp DWORD PTR [eax], 0
3229 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3232 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3233 x86_push_reg (code, hreg);
3234 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3235 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3236 x86_pop_reg (code, hreg);
3249 case OP_VOIDCALL_REG:
3251 case OP_FCALL_MEMBASE:
3252 case OP_LCALL_MEMBASE:
3253 case OP_VCALL_MEMBASE:
3254 case OP_VCALL2_MEMBASE:
3255 case OP_VOIDCALL_MEMBASE:
3256 case OP_CALL_MEMBASE: {
3259 call = (MonoCallInst*)ins;
3260 cinfo = (CallInfo*)call->call_info;
3262 switch (ins->opcode) {
3269 if (ins->flags & MONO_INST_HAS_METHOD)
3270 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3272 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3278 case OP_VOIDCALL_REG:
3280 x86_call_reg (code, ins->sreg1);
3282 case OP_FCALL_MEMBASE:
3283 case OP_LCALL_MEMBASE:
3284 case OP_VCALL_MEMBASE:
3285 case OP_VCALL2_MEMBASE:
3286 case OP_VOIDCALL_MEMBASE:
3287 case OP_CALL_MEMBASE:
3288 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3291 g_assert_not_reached ();
3294 ins->flags |= MONO_INST_GC_CALLSITE;
3295 ins->backend.pc_offset = code - cfg->native_code;
3296 if (cinfo->callee_stack_pop) {
3297 /* Have to compensate for the stack space popped by the callee */
3298 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3300 code = emit_move_return_value (cfg, ins, code);
3304 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3306 case OP_X86_LEA_MEMBASE:
3307 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3310 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3313 /* keep alignment */
3314 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3315 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3316 code = mono_emit_stack_alloc (cfg, code, ins);
3317 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3318 if (cfg->param_area)
3319 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3321 case OP_LOCALLOC_IMM: {
3322 guint32 size = ins->inst_imm;
3323 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3325 if (ins->flags & MONO_INST_INIT) {
3326 /* FIXME: Optimize this */
3327 x86_mov_reg_imm (code, ins->dreg, size);
3328 ins->sreg1 = ins->dreg;
3330 code = mono_emit_stack_alloc (cfg, code, ins);
3331 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3333 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3334 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3336 if (cfg->param_area)
3337 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3341 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3342 x86_push_reg (code, ins->sreg1);
3343 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3344 (gpointer)"mono_arch_throw_exception");
3345 ins->flags |= MONO_INST_GC_CALLSITE;
3346 ins->backend.pc_offset = code - cfg->native_code;
3350 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3351 x86_push_reg (code, ins->sreg1);
3352 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3353 (gpointer)"mono_arch_rethrow_exception");
3354 ins->flags |= MONO_INST_GC_CALLSITE;
3355 ins->backend.pc_offset = code - cfg->native_code;
3358 case OP_CALL_HANDLER:
3359 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3360 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3361 x86_call_imm (code, 0);
3362 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3363 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3365 case OP_START_HANDLER: {
3366 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3367 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3368 if (cfg->param_area)
3369 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3372 case OP_ENDFINALLY: {
3373 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3374 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3378 case OP_ENDFILTER: {
3379 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3380 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3381 /* The local allocator will put the result into EAX */
3387 ins->inst_c0 = code - cfg->native_code;
3390 if (ins->inst_target_bb->native_offset) {
3391 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3393 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3394 if ((cfg->opt & MONO_OPT_BRANCH) &&
3395 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3396 x86_jump8 (code, 0);
3398 x86_jump32 (code, 0);
3402 x86_jump_reg (code, ins->sreg1);
3421 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3422 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3424 case OP_COND_EXC_EQ:
3425 case OP_COND_EXC_NE_UN:
3426 case OP_COND_EXC_LT:
3427 case OP_COND_EXC_LT_UN:
3428 case OP_COND_EXC_GT:
3429 case OP_COND_EXC_GT_UN:
3430 case OP_COND_EXC_GE:
3431 case OP_COND_EXC_GE_UN:
3432 case OP_COND_EXC_LE:
3433 case OP_COND_EXC_LE_UN:
3434 case OP_COND_EXC_IEQ:
3435 case OP_COND_EXC_INE_UN:
3436 case OP_COND_EXC_ILT:
3437 case OP_COND_EXC_ILT_UN:
3438 case OP_COND_EXC_IGT:
3439 case OP_COND_EXC_IGT_UN:
3440 case OP_COND_EXC_IGE:
3441 case OP_COND_EXC_IGE_UN:
3442 case OP_COND_EXC_ILE:
3443 case OP_COND_EXC_ILE_UN:
3444 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3446 case OP_COND_EXC_OV:
3447 case OP_COND_EXC_NO:
3449 case OP_COND_EXC_NC:
3450 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3452 case OP_COND_EXC_IOV:
3453 case OP_COND_EXC_INO:
3454 case OP_COND_EXC_IC:
3455 case OP_COND_EXC_INC:
3456 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3468 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3476 case OP_CMOV_INE_UN:
3477 case OP_CMOV_IGE_UN:
3478 case OP_CMOV_IGT_UN:
3479 case OP_CMOV_ILE_UN:
3480 case OP_CMOV_ILT_UN:
3481 g_assert (ins->dreg == ins->sreg1);
3482 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3485 /* floating point opcodes */
3487 double d = *(double *)ins->inst_p0;
3489 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3491 } else if (d == 1.0) {
3494 if (cfg->compile_aot) {
3495 guint32 *val = (guint32*)&d;
3496 x86_push_imm (code, val [1]);
3497 x86_push_imm (code, val [0]);
3498 x86_fld_membase (code, X86_ESP, 0, TRUE);
3499 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3502 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3503 x86_fld (code, NULL, TRUE);
3509 float f = *(float *)ins->inst_p0;
3511 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3513 } else if (f == 1.0) {
3516 if (cfg->compile_aot) {
3517 guint32 val = *(guint32*)&f;
3518 x86_push_imm (code, val);
3519 x86_fld_membase (code, X86_ESP, 0, FALSE);
3520 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3523 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3524 x86_fld (code, NULL, FALSE);
3529 case OP_STORER8_MEMBASE_REG:
3530 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3532 case OP_LOADR8_MEMBASE:
3533 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3535 case OP_STORER4_MEMBASE_REG:
3536 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3538 case OP_LOADR4_MEMBASE:
3539 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3541 case OP_ICONV_TO_R4:
3542 x86_push_reg (code, ins->sreg1);
3543 x86_fild_membase (code, X86_ESP, 0, FALSE);
3544 /* Change precision */
3545 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3546 x86_fld_membase (code, X86_ESP, 0, FALSE);
3547 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3549 case OP_ICONV_TO_R8:
3550 x86_push_reg (code, ins->sreg1);
3551 x86_fild_membase (code, X86_ESP, 0, FALSE);
3552 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3554 case OP_ICONV_TO_R_UN:
3555 x86_push_imm (code, 0);
3556 x86_push_reg (code, ins->sreg1);
3557 x86_fild_membase (code, X86_ESP, 0, TRUE);
3558 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3560 case OP_X86_FP_LOAD_I8:
3561 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3563 case OP_X86_FP_LOAD_I4:
3564 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3566 case OP_FCONV_TO_R4:
3567 /* Change precision */
3568 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3569 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3570 x86_fld_membase (code, X86_ESP, 0, FALSE);
3571 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3573 case OP_FCONV_TO_I1:
3574 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3576 case OP_FCONV_TO_U1:
3577 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3579 case OP_FCONV_TO_I2:
3580 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3582 case OP_FCONV_TO_U2:
3583 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3585 case OP_FCONV_TO_I4:
3587 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3589 case OP_FCONV_TO_I8:
3590 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3591 x86_fnstcw_membase(code, X86_ESP, 0);
3592 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3593 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3594 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3595 x86_fldcw_membase (code, X86_ESP, 2);
3596 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3597 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3598 x86_pop_reg (code, ins->dreg);
3599 x86_pop_reg (code, ins->backend.reg3);
3600 x86_fldcw_membase (code, X86_ESP, 0);
3601 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3603 case OP_LCONV_TO_R8_2:
3604 x86_push_reg (code, ins->sreg2);
3605 x86_push_reg (code, ins->sreg1);
3606 x86_fild_membase (code, X86_ESP, 0, TRUE);
3607 /* Change precision */
3608 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3609 x86_fld_membase (code, X86_ESP, 0, TRUE);
3610 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3612 case OP_LCONV_TO_R4_2:
3613 x86_push_reg (code, ins->sreg2);
3614 x86_push_reg (code, ins->sreg1);
3615 x86_fild_membase (code, X86_ESP, 0, TRUE);
3616 /* Change precision */
3617 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3618 x86_fld_membase (code, X86_ESP, 0, FALSE);
3619 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3621 case OP_LCONV_TO_R_UN_2: {
3622 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3625 /* load 64bit integer to FP stack */
3626 x86_push_reg (code, ins->sreg2);
3627 x86_push_reg (code, ins->sreg1);
3628 x86_fild_membase (code, X86_ESP, 0, TRUE);
3630 /* test if lreg is negative */
3631 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3632 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3634 /* add correction constant mn */
3635 if (cfg->compile_aot) {
3636 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3637 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3638 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3639 x86_fld80_membase (code, X86_ESP, 2);
3640 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3642 x86_fld80_mem (code, mn);
3644 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3646 x86_patch (br, code);
3648 /* Change precision */
3649 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3650 x86_fld_membase (code, X86_ESP, 0, TRUE);
3652 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3656 case OP_LCONV_TO_OVF_I:
3657 case OP_LCONV_TO_OVF_I4_2: {
3658 guint8 *br [3], *label [1];
3662 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3664 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3666 /* If the low word top bit is set, see if we are negative */
3667 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3668 /* We are not negative (no top bit set, check for our top word to be zero */
3669 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3670 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3673 /* throw exception */
3674 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3676 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3677 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3678 x86_jump8 (code, 0);
3680 x86_jump32 (code, 0);
3682 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3683 x86_jump32 (code, 0);
3687 x86_patch (br [0], code);
3688 /* our top bit is set, check that top word is 0xfffffff */
3689 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3691 x86_patch (br [1], code);
3692 /* nope, emit exception */
3693 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3694 x86_patch (br [2], label [0]);
3696 if (ins->dreg != ins->sreg1)
3697 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3701 /* Not needed on the fp stack */
3703 case OP_MOVE_F_TO_I4:
3704 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
3705 x86_mov_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, 4);
3707 case OP_MOVE_I4_TO_F:
3708 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
3709 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
3712 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3715 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3718 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3721 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3729 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3734 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3741 * it really doesn't make sense to inline all this code,
3742 * it's here just to show that things may not be as simple
3745 guchar *check_pos, *end_tan, *pop_jump;
3746 x86_push_reg (code, X86_EAX);
3749 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3751 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3752 x86_fstp (code, 0); /* pop the 1.0 */
3754 x86_jump8 (code, 0);
3756 x86_fp_op (code, X86_FADD, 0);
3760 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3762 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3765 x86_patch (pop_jump, code);
3766 x86_fstp (code, 0); /* pop the 1.0 */
3767 x86_patch (check_pos, code);
3768 x86_patch (end_tan, code);
3770 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3771 x86_pop_reg (code, X86_EAX);
3778 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3787 g_assert (cfg->opt & MONO_OPT_CMOV);
3788 g_assert (ins->dreg == ins->sreg1);
3789 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3790 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3793 g_assert (cfg->opt & MONO_OPT_CMOV);
3794 g_assert (ins->dreg == ins->sreg1);
3795 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3796 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3799 g_assert (cfg->opt & MONO_OPT_CMOV);
3800 g_assert (ins->dreg == ins->sreg1);
3801 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3802 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3805 g_assert (cfg->opt & MONO_OPT_CMOV);
3806 g_assert (ins->dreg == ins->sreg1);
3807 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3808 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3814 x86_fxch (code, ins->inst_imm);
3819 x86_push_reg (code, X86_EAX);
3820 /* we need to exchange ST(0) with ST(1) */
3823 /* this requires a loop, because fprem somtimes
3824 * returns a partial remainder */
3826 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3827 /* x86_fprem1 (code); */
3830 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3832 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3838 x86_pop_reg (code, X86_EAX);
3842 if (cfg->opt & MONO_OPT_FCMOV) {
3843 x86_fcomip (code, 1);
3847 /* this overwrites EAX */
3848 EMIT_FPCOMPARE(code);
3849 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3853 if (cfg->opt & MONO_OPT_FCMOV) {
3854 /* zeroing the register at the start results in
3855 * shorter and faster code (we can also remove the widening op)
3857 guchar *unordered_check;
3858 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3859 x86_fcomip (code, 1);
3861 unordered_check = code;
3862 x86_branch8 (code, X86_CC_P, 0, FALSE);
3863 if (ins->opcode == OP_FCEQ) {
3864 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3865 x86_patch (unordered_check, code);
3867 guchar *jump_to_end;
3868 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3870 x86_jump8 (code, 0);
3871 x86_patch (unordered_check, code);
3872 x86_inc_reg (code, ins->dreg);
3873 x86_patch (jump_to_end, code);
3878 if (ins->dreg != X86_EAX)
3879 x86_push_reg (code, X86_EAX);
3881 EMIT_FPCOMPARE(code);
3882 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3883 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3884 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3885 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3887 if (ins->dreg != X86_EAX)
3888 x86_pop_reg (code, X86_EAX);
3892 if (cfg->opt & MONO_OPT_FCMOV) {
3893 /* zeroing the register at the start results in
3894 * shorter and faster code (we can also remove the widening op)
3896 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3897 x86_fcomip (code, 1);
3899 if (ins->opcode == OP_FCLT_UN) {
3900 guchar *unordered_check = code;
3901 guchar *jump_to_end;
3902 x86_branch8 (code, X86_CC_P, 0, FALSE);
3903 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3905 x86_jump8 (code, 0);
3906 x86_patch (unordered_check, code);
3907 x86_inc_reg (code, ins->dreg);
3908 x86_patch (jump_to_end, code);
3910 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3914 if (ins->dreg != X86_EAX)
3915 x86_push_reg (code, X86_EAX);
3917 EMIT_FPCOMPARE(code);
3918 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3919 if (ins->opcode == OP_FCLT_UN) {
3920 guchar *is_not_zero_check, *end_jump;
3921 is_not_zero_check = code;
3922 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3924 x86_jump8 (code, 0);
3925 x86_patch (is_not_zero_check, code);
3926 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3928 x86_patch (end_jump, code);
3930 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3931 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3933 if (ins->dreg != X86_EAX)
3934 x86_pop_reg (code, X86_EAX);
3937 guchar *unordered_check;
3938 guchar *jump_to_end;
3939 if (cfg->opt & MONO_OPT_FCMOV) {
3940 /* zeroing the register at the start results in
3941 * shorter and faster code (we can also remove the widening op)
3943 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3944 x86_fcomip (code, 1);
3946 unordered_check = code;
3947 x86_branch8 (code, X86_CC_P, 0, FALSE);
3948 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3949 x86_patch (unordered_check, code);
3952 if (ins->dreg != X86_EAX)
3953 x86_push_reg (code, X86_EAX);
3955 EMIT_FPCOMPARE(code);
3956 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3957 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3958 unordered_check = code;
3959 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3961 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3962 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3963 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3965 x86_jump8 (code, 0);
3966 x86_patch (unordered_check, code);
3967 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3968 x86_patch (jump_to_end, code);
3970 if (ins->dreg != X86_EAX)
3971 x86_pop_reg (code, X86_EAX);
3976 if (cfg->opt & MONO_OPT_FCMOV) {
3977 /* zeroing the register at the start results in
3978 * shorter and faster code (we can also remove the widening op)
3980 guchar *unordered_check;
3981 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3982 x86_fcomip (code, 1);
3984 if (ins->opcode == OP_FCGT) {
3985 unordered_check = code;
3986 x86_branch8 (code, X86_CC_P, 0, FALSE);
3987 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3988 x86_patch (unordered_check, code);
3990 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3994 if (ins->dreg != X86_EAX)
3995 x86_push_reg (code, X86_EAX);
3997 EMIT_FPCOMPARE(code);
3998 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3999 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4000 if (ins->opcode == OP_FCGT_UN) {
4001 guchar *is_not_zero_check, *end_jump;
4002 is_not_zero_check = code;
4003 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4005 x86_jump8 (code, 0);
4006 x86_patch (is_not_zero_check, code);
4007 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4009 x86_patch (end_jump, code);
4011 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4012 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4014 if (ins->dreg != X86_EAX)
4015 x86_pop_reg (code, X86_EAX);
4018 guchar *unordered_check;
4019 guchar *jump_to_end;
4020 if (cfg->opt & MONO_OPT_FCMOV) {
4021 /* zeroing the register at the start results in
4022 * shorter and faster code (we can also remove the widening op)
4024 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4025 x86_fcomip (code, 1);
4027 unordered_check = code;
4028 x86_branch8 (code, X86_CC_P, 0, FALSE);
4029 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4030 x86_patch (unordered_check, code);
4033 if (ins->dreg != X86_EAX)
4034 x86_push_reg (code, X86_EAX);
4036 EMIT_FPCOMPARE(code);
4037 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4038 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4039 unordered_check = code;
4040 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4042 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4043 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4044 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4046 x86_jump8 (code, 0);
4047 x86_patch (unordered_check, code);
4048 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4049 x86_patch (jump_to_end, code);
4051 if (ins->dreg != X86_EAX)
4052 x86_pop_reg (code, X86_EAX);
4056 if (cfg->opt & MONO_OPT_FCMOV) {
4057 guchar *jump = code;
4058 x86_branch8 (code, X86_CC_P, 0, TRUE);
4059 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4060 x86_patch (jump, code);
4063 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4064 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4067 /* Branch if C013 != 100 */
4068 if (cfg->opt & MONO_OPT_FCMOV) {
4069 /* branch if !ZF or (PF|CF) */
4070 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4071 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4072 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4075 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4076 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4079 if (cfg->opt & MONO_OPT_FCMOV) {
4080 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4083 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4086 if (cfg->opt & MONO_OPT_FCMOV) {
4087 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4088 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4091 if (ins->opcode == OP_FBLT_UN) {
4092 guchar *is_not_zero_check, *end_jump;
4093 is_not_zero_check = code;
4094 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4096 x86_jump8 (code, 0);
4097 x86_patch (is_not_zero_check, code);
4098 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4100 x86_patch (end_jump, code);
4102 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4106 if (cfg->opt & MONO_OPT_FCMOV) {
4107 if (ins->opcode == OP_FBGT) {
4110 /* skip branch if C1=1 */
4112 x86_branch8 (code, X86_CC_P, 0, FALSE);
4113 /* branch if (C0 | C3) = 1 */
4114 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4115 x86_patch (br1, code);
4117 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4121 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4122 if (ins->opcode == OP_FBGT_UN) {
4123 guchar *is_not_zero_check, *end_jump;
4124 is_not_zero_check = code;
4125 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4127 x86_jump8 (code, 0);
4128 x86_patch (is_not_zero_check, code);
4129 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4131 x86_patch (end_jump, code);
4133 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4136 /* Branch if C013 == 100 or 001 */
4137 if (cfg->opt & MONO_OPT_FCMOV) {
4140 /* skip branch if C1=1 */
4142 x86_branch8 (code, X86_CC_P, 0, FALSE);
4143 /* branch if (C0 | C3) = 1 */
4144 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4145 x86_patch (br1, code);
4148 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4149 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4150 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4151 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4154 /* Branch if C013 == 000 */
4155 if (cfg->opt & MONO_OPT_FCMOV) {
4156 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4159 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4162 /* Branch if C013=000 or 100 */
4163 if (cfg->opt & MONO_OPT_FCMOV) {
4166 /* skip branch if C1=1 */
4168 x86_branch8 (code, X86_CC_P, 0, FALSE);
4169 /* branch if C0=0 */
4170 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4171 x86_patch (br1, code);
4174 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4175 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4176 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4179 /* Branch if C013 != 001 */
4180 if (cfg->opt & MONO_OPT_FCMOV) {
4181 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4182 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4185 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4186 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4190 x86_push_reg (code, X86_EAX);
4193 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4194 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4195 x86_pop_reg (code, X86_EAX);
4197 /* Have to clean up the fp stack before throwing the exception */
4199 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4202 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4204 x86_patch (br1, code);
4208 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4211 case OP_TLS_GET_REG: {
4212 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4216 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4219 case OP_TLS_SET_REG: {
4220 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4223 case OP_MEMORY_BARRIER: {
4224 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4225 x86_prefix (code, X86_LOCK_PREFIX);
4226 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4230 case OP_ATOMIC_ADD_I4: {
4231 int dreg = ins->dreg;
4233 g_assert (cfg->has_atomic_add_i4);
4235 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4236 if (ins->sreg2 == dreg) {
4237 if (dreg == X86_EBX) {
4239 if (ins->inst_basereg == X86_EDI)
4243 if (ins->inst_basereg == X86_EBX)
4246 } else if (ins->inst_basereg == dreg) {
4247 if (dreg == X86_EBX) {
4249 if (ins->sreg2 == X86_EDI)
4253 if (ins->sreg2 == X86_EBX)
4258 if (dreg != ins->dreg) {
4259 x86_push_reg (code, dreg);
4262 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4263 x86_prefix (code, X86_LOCK_PREFIX);
4264 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4265 /* dreg contains the old value, add with sreg2 value */
4266 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4268 if (ins->dreg != dreg) {
4269 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4270 x86_pop_reg (code, dreg);
4275 case OP_ATOMIC_EXCHANGE_I4: {
4277 int sreg2 = ins->sreg2;
4278 int breg = ins->inst_basereg;
4280 g_assert (cfg->has_atomic_exchange_i4);
4282 /* cmpxchg uses eax as comperand, need to make sure we can use it
4283 * hack to overcome limits in x86 reg allocator
4284 * (req: dreg == eax and sreg2 != eax and breg != eax)
4286 g_assert (ins->dreg == X86_EAX);
4288 /* We need the EAX reg for the cmpxchg */
4289 if (ins->sreg2 == X86_EAX) {
4290 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4291 x86_push_reg (code, sreg2);
4292 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4295 if (breg == X86_EAX) {
4296 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4297 x86_push_reg (code, breg);
4298 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4301 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4303 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4304 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4305 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4306 x86_patch (br [1], br [0]);
4308 if (breg != ins->inst_basereg)
4309 x86_pop_reg (code, breg);
4311 if (ins->sreg2 != sreg2)
4312 x86_pop_reg (code, sreg2);
4316 case OP_ATOMIC_CAS_I4: {
4317 g_assert (ins->dreg == X86_EAX);
4318 g_assert (ins->sreg3 == X86_EAX);
4319 g_assert (ins->sreg1 != X86_EAX);
4320 g_assert (ins->sreg1 != ins->sreg2);
4322 x86_prefix (code, X86_LOCK_PREFIX);
4323 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4326 case OP_ATOMIC_LOAD_I1: {
4327 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4330 case OP_ATOMIC_LOAD_U1: {
4331 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4334 case OP_ATOMIC_LOAD_I2: {
4335 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4338 case OP_ATOMIC_LOAD_U2: {
4339 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4342 case OP_ATOMIC_LOAD_I4:
4343 case OP_ATOMIC_LOAD_U4: {
4344 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4347 case OP_ATOMIC_LOAD_R4:
4348 case OP_ATOMIC_LOAD_R8: {
4349 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4352 case OP_ATOMIC_STORE_I1:
4353 case OP_ATOMIC_STORE_U1:
4354 case OP_ATOMIC_STORE_I2:
4355 case OP_ATOMIC_STORE_U2:
4356 case OP_ATOMIC_STORE_I4:
4357 case OP_ATOMIC_STORE_U4: {
4360 switch (ins->opcode) {
4361 case OP_ATOMIC_STORE_I1:
4362 case OP_ATOMIC_STORE_U1:
4365 case OP_ATOMIC_STORE_I2:
4366 case OP_ATOMIC_STORE_U2:
4369 case OP_ATOMIC_STORE_I4:
4370 case OP_ATOMIC_STORE_U4:
4375 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4377 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4381 case OP_ATOMIC_STORE_R4:
4382 case OP_ATOMIC_STORE_R8: {
4383 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4385 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4389 case OP_CARD_TABLE_WBARRIER: {
4390 int ptr = ins->sreg1;
4391 int value = ins->sreg2;
4393 int nursery_shift, card_table_shift;
4394 gpointer card_table_mask;
4395 size_t nursery_size;
4396 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4397 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4398 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4401 * We need one register we can clobber, we choose EDX and make sreg1
4402 * fixed EAX to work around limitations in the local register allocator.
4403 * sreg2 might get allocated to EDX, but that is not a problem since
4404 * we use it before clobbering EDX.
4406 g_assert (ins->sreg1 == X86_EAX);
4409 * This is the code we produce:
4412 * edx >>= nursery_shift
4413 * cmp edx, (nursery_start >> nursery_shift)
4416 * edx >>= card_table_shift
4417 * card_table[edx] = 1
4421 if (card_table_nursery_check) {
4422 if (value != X86_EDX)
4423 x86_mov_reg_reg (code, X86_EDX, value, 4);
4424 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4425 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4426 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4428 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4429 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4430 if (card_table_mask)
4431 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4432 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4433 if (card_table_nursery_check)
4434 x86_patch (br, code);
4437 #ifdef MONO_ARCH_SIMD_INTRINSICS
4439 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4442 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4445 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4448 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4451 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4454 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4457 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4458 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4461 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4464 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4467 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4470 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4473 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4476 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4479 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4482 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4485 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4488 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4491 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4494 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4497 case OP_PSHUFLEW_HIGH:
4498 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4499 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4501 case OP_PSHUFLEW_LOW:
4502 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4503 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4506 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4507 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4510 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4511 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4514 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4515 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4519 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4522 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4525 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4528 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4531 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4534 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4537 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4538 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4541 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4544 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4547 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4550 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4553 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4556 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4559 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4562 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4565 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4568 case OP_EXTRACT_MASK:
4569 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4573 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4576 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4579 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4583 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4586 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4589 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4592 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4596 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4599 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4602 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4605 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4609 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4612 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4615 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4619 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4622 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4625 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4629 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4632 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4636 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4639 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4642 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4646 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4649 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4652 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4656 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4659 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4662 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4665 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4669 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4672 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4675 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4678 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4681 case OP_PSUM_ABS_DIFF:
4682 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4685 case OP_UNPACK_LOWB:
4686 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4688 case OP_UNPACK_LOWW:
4689 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4691 case OP_UNPACK_LOWD:
4692 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4694 case OP_UNPACK_LOWQ:
4695 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4697 case OP_UNPACK_LOWPS:
4698 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4700 case OP_UNPACK_LOWPD:
4701 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4704 case OP_UNPACK_HIGHB:
4705 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4707 case OP_UNPACK_HIGHW:
4708 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4710 case OP_UNPACK_HIGHD:
4711 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4713 case OP_UNPACK_HIGHQ:
4714 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4716 case OP_UNPACK_HIGHPS:
4717 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4719 case OP_UNPACK_HIGHPD:
4720 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4724 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4727 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4730 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4733 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4736 case OP_PADDB_SAT_UN:
4737 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4739 case OP_PSUBB_SAT_UN:
4740 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4742 case OP_PADDW_SAT_UN:
4743 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4745 case OP_PSUBW_SAT_UN:
4746 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4750 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4753 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4756 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4759 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4763 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4766 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4769 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4771 case OP_PMULW_HIGH_UN:
4772 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4775 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4779 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4782 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4786 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4789 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4793 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4796 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4800 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4803 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4807 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4810 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4814 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4817 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4821 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4824 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4828 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4831 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4835 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4838 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4842 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4844 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4845 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4849 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4851 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4852 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4856 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4858 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4859 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4863 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4865 case OP_EXTRACTX_U2:
4866 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4868 case OP_INSERTX_U1_SLOW:
4869 /*sreg1 is the extracted ireg (scratch)
4870 /sreg2 is the to be inserted ireg (scratch)
4871 /dreg is the xreg to receive the value*/
4873 /*clear the bits from the extracted word*/
4874 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4875 /*shift the value to insert if needed*/
4876 if (ins->inst_c0 & 1)
4877 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4878 /*join them together*/
4879 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4880 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4882 case OP_INSERTX_I4_SLOW:
4883 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4884 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4885 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4888 case OP_INSERTX_R4_SLOW:
4889 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4890 /*TODO if inst_c0 == 0 use movss*/
4891 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4892 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4894 case OP_INSERTX_R8_SLOW:
4895 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4896 if (cfg->verbose_level)
4897 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4899 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4901 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4904 case OP_STOREX_MEMBASE_REG:
4905 case OP_STOREX_MEMBASE:
4906 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4908 case OP_LOADX_MEMBASE:
4909 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4911 case OP_LOADX_ALIGNED_MEMBASE:
4912 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4914 case OP_STOREX_ALIGNED_MEMBASE_REG:
4915 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4917 case OP_STOREX_NTA_MEMBASE_REG:
4918 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4920 case OP_PREFETCH_MEMBASE:
4921 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4925 /*FIXME the peephole pass should have killed this*/
4926 if (ins->dreg != ins->sreg1)
4927 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4930 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4933 case OP_FCONV_TO_R8_X:
4934 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4935 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4938 case OP_XCONV_R8_TO_I4:
4939 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4940 switch (ins->backend.source_opcode) {
4941 case OP_FCONV_TO_I1:
4942 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4944 case OP_FCONV_TO_U1:
4945 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4947 case OP_FCONV_TO_I2:
4948 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4950 case OP_FCONV_TO_U2:
4951 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4957 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4958 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4959 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4960 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4961 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4962 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4965 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4966 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4967 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4970 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4971 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4974 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4975 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4976 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4979 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4980 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4981 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4985 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4988 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4991 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4994 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4997 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
5000 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
5003 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
5006 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
5010 case OP_LIVERANGE_START: {
5011 if (cfg->verbose_level > 1)
5012 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5013 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5016 case OP_LIVERANGE_END: {
5017 if (cfg->verbose_level > 1)
5018 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5019 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5022 case OP_NACL_GC_SAFE_POINT: {
5023 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
5024 if (cfg->compile_aot)
5025 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5029 x86_test_mem_imm8 (code, (gpointer)&__nacl_thread_suspension_needed, 0xFFFFFFFF);
5030 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
5031 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5032 x86_patch (br[0], code);
5037 case OP_GC_LIVENESS_DEF:
5038 case OP_GC_LIVENESS_USE:
5039 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5040 ins->backend.pc_offset = code - cfg->native_code;
5042 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5043 ins->backend.pc_offset = code - cfg->native_code;
5044 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5047 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
5050 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
5053 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
5054 g_assert_not_reached ();
5057 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
5058 #ifndef __native_client_codegen__
5059 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5060 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5061 g_assert_not_reached ();
5062 #endif /* __native_client_codegen__ */
5068 cfg->code_len = code - cfg->native_code;
5071 #endif /* DISABLE_JIT */
5074 mono_arch_register_lowlevel_calls (void)
5079 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
5081 MonoJumpInfo *patch_info;
5082 gboolean compile_aot = !run_cctors;
5084 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5085 unsigned char *ip = patch_info->ip.i + code;
5086 const unsigned char *target;
5089 switch (patch_info->type) {
5090 case MONO_PATCH_INFO_BB:
5091 case MONO_PATCH_INFO_LABEL:
5094 /* No need to patch these */
5099 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5101 switch (patch_info->type) {
5102 case MONO_PATCH_INFO_IP:
5103 *((gconstpointer *)(ip)) = target;
5105 case MONO_PATCH_INFO_CLASS_INIT: {
5107 /* Might already been changed to a nop */
5108 x86_call_code (code, 0);
5109 x86_patch (ip, target);
5112 case MONO_PATCH_INFO_ABS:
5113 case MONO_PATCH_INFO_METHOD:
5114 case MONO_PATCH_INFO_METHOD_JUMP:
5115 case MONO_PATCH_INFO_INTERNAL_METHOD:
5116 case MONO_PATCH_INFO_BB:
5117 case MONO_PATCH_INFO_LABEL:
5118 case MONO_PATCH_INFO_RGCTX_FETCH:
5119 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
5120 case MONO_PATCH_INFO_MONITOR_ENTER:
5121 case MONO_PATCH_INFO_MONITOR_ENTER_V4:
5122 case MONO_PATCH_INFO_MONITOR_EXIT:
5123 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5124 #if defined(__native_client_codegen__) && defined(__native_client__)
5125 if (nacl_is_code_address (code)) {
5126 /* For tail calls, code is patched after being installed */
5127 /* but not through the normal "patch callsite" method. */
5128 unsigned char buf[kNaClAlignment];
5129 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5130 unsigned char *_target = target;
5132 /* All patch targets modified in x86_patch */
5133 /* are IP relative. */
5134 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5135 memcpy (buf, aligned_code, kNaClAlignment);
5136 /* Patch a temp buffer of bundle size, */
5137 /* then install to actual location. */
5138 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5139 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5140 g_assert (ret == 0);
5143 x86_patch (ip, target);
5146 x86_patch (ip, target);
5149 case MONO_PATCH_INFO_NONE:
5151 case MONO_PATCH_INFO_R4:
5152 case MONO_PATCH_INFO_R8: {
5153 guint32 offset = mono_arch_get_patch_offset (ip);
5154 *((gconstpointer *)(ip + offset)) = target;
5158 guint32 offset = mono_arch_get_patch_offset (ip);
5159 #if !defined(__native_client__)
5160 *((gconstpointer *)(ip + offset)) = target;
5162 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5170 static G_GNUC_UNUSED void
5171 stack_unaligned (MonoMethod *m, gpointer caller)
5173 printf ("%s\n", mono_method_full_name (m, TRUE));
5174 g_assert_not_reached ();
5178 mono_arch_emit_prolog (MonoCompile *cfg)
5180 MonoMethod *method = cfg->method;
5182 MonoMethodSignature *sig;
5184 int alloc_size, pos, max_offset, i, cfa_offset;
5186 gboolean need_stack_frame;
5187 #ifdef __native_client_codegen__
5188 guint alignment_check;
5191 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5193 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5194 cfg->code_size += 512;
5196 #if defined(__default_codegen__)
5197 code = cfg->native_code = g_malloc (cfg->code_size);
5198 #elif defined(__native_client_codegen__)
5199 /* native_code_alloc is not 32-byte aligned, native_code is. */
5200 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5201 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5203 /* Align native_code to next nearest kNaclAlignment byte. */
5204 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5205 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5207 code = cfg->native_code;
5209 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5210 g_assert(alignment_check == 0);
5217 /* Check that the stack is aligned on osx */
5218 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5219 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5220 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5222 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5223 x86_push_membase (code, X86_ESP, 0);
5224 x86_push_imm (code, cfg->method);
5225 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5226 x86_call_reg (code, X86_EAX);
5227 x86_patch (br [0], code);
5231 /* Offset between RSP and the CFA */
5235 cfa_offset = sizeof (gpointer);
5236 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5237 // IP saved at CFA - 4
5238 /* There is no IP reg on x86 */
5239 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5240 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5242 need_stack_frame = needs_stack_frame (cfg);
5244 if (need_stack_frame) {
5245 x86_push_reg (code, X86_EBP);
5246 cfa_offset += sizeof (gpointer);
5247 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5248 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5249 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5250 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5251 /* These are handled automatically by the stack marking code */
5252 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5254 cfg->frame_reg = X86_ESP;
5257 cfg->stack_offset += cfg->param_area;
5258 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5260 alloc_size = cfg->stack_offset;
5263 if (!method->save_lmf) {
5264 if (cfg->used_int_regs & (1 << X86_EBX)) {
5265 x86_push_reg (code, X86_EBX);
5267 cfa_offset += sizeof (gpointer);
5268 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5269 /* These are handled automatically by the stack marking code */
5270 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5273 if (cfg->used_int_regs & (1 << X86_EDI)) {
5274 x86_push_reg (code, X86_EDI);
5276 cfa_offset += sizeof (gpointer);
5277 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5278 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5281 if (cfg->used_int_regs & (1 << X86_ESI)) {
5282 x86_push_reg (code, X86_ESI);
5284 cfa_offset += sizeof (gpointer);
5285 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5286 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5292 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5293 if (mono_do_x86_stack_align && need_stack_frame) {
5294 int tot = alloc_size + pos + 4; /* ret ip */
5295 if (need_stack_frame)
5297 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5299 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5300 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5301 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5305 cfg->arch.sp_fp_offset = alloc_size + pos;
5308 /* See mono_emit_stack_alloc */
5309 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5310 guint32 remaining_size = alloc_size;
5311 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5312 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5313 guint32 offset = code - cfg->native_code;
5314 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5315 while (required_code_size >= (cfg->code_size - offset))
5316 cfg->code_size *= 2;
5317 cfg->native_code = mono_realloc_native_code(cfg);
5318 code = cfg->native_code + offset;
5319 cfg->stat_code_reallocs++;
5321 while (remaining_size >= 0x1000) {
5322 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5323 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5324 remaining_size -= 0x1000;
5327 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5329 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5332 g_assert (need_stack_frame);
5335 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5336 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5337 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5340 #if DEBUG_STACK_ALIGNMENT
5341 /* check the stack is aligned */
5342 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5343 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5344 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5345 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5346 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5347 x86_breakpoint (code);
5351 /* compute max_offset in order to use short forward jumps */
5353 if (cfg->opt & MONO_OPT_BRANCH) {
5354 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5356 bb->max_offset = max_offset;
5358 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5360 /* max alignment for loops */
5361 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5362 max_offset += LOOP_ALIGNMENT;
5363 #ifdef __native_client_codegen__
5364 /* max alignment for native client */
5365 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5366 max_offset += kNaClAlignment;
5368 MONO_BB_FOR_EACH_INS (bb, ins) {
5369 if (ins->opcode == OP_LABEL)
5370 ins->inst_c1 = max_offset;
5371 #ifdef __native_client_codegen__
5372 switch (ins->opcode)
5384 case OP_VOIDCALL_REG:
5386 case OP_FCALL_MEMBASE:
5387 case OP_LCALL_MEMBASE:
5388 case OP_VCALL_MEMBASE:
5389 case OP_VCALL2_MEMBASE:
5390 case OP_VOIDCALL_MEMBASE:
5391 case OP_CALL_MEMBASE:
5392 max_offset += kNaClAlignment;
5395 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5398 #endif /* __native_client_codegen__ */
5399 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5404 /* store runtime generic context */
5405 if (cfg->rgctx_var) {
5406 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5408 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5411 if (method->save_lmf)
5412 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5414 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5415 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5417 /* load arguments allocated to register from the stack */
5418 sig = mono_method_signature (method);
5421 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5422 inst = cfg->args [pos];
5423 if (inst->opcode == OP_REGVAR) {
5424 g_assert (need_stack_frame);
5425 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5426 if (cfg->verbose_level > 2)
5427 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5432 cfg->code_len = code - cfg->native_code;
5434 g_assert (cfg->code_len < cfg->code_size);
5440 mono_arch_emit_epilog (MonoCompile *cfg)
5442 MonoMethod *method = cfg->method;
5443 MonoMethodSignature *sig = mono_method_signature (method);
5445 guint32 stack_to_pop;
5447 int max_epilog_size = 16;
5449 gboolean need_stack_frame = needs_stack_frame (cfg);
5451 if (cfg->method->save_lmf)
5452 max_epilog_size += 128;
5454 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5455 cfg->code_size *= 2;
5456 cfg->native_code = mono_realloc_native_code(cfg);
5457 cfg->stat_code_reallocs++;
5460 code = cfg->native_code + cfg->code_len;
5462 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5463 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5465 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5468 if (method->save_lmf) {
5469 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5471 gboolean supported = FALSE;
5473 if (cfg->compile_aot) {
5474 #if defined(__APPLE__) || defined(__linux__)
5477 } else if (mono_get_jit_tls_offset () != -1) {
5481 /* check if we need to restore protection of the stack after a stack overflow */
5483 if (cfg->compile_aot) {
5484 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5486 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5488 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5491 /* we load the value in a separate instruction: this mechanism may be
5492 * used later as a safer way to do thread interruption
5494 x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5495 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5497 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5498 /* note that the call trampoline will preserve eax/edx */
5499 x86_call_reg (code, X86_ECX);
5500 x86_patch (patch, code);
5502 /* FIXME: maybe save the jit tls in the prolog */
5505 /* restore caller saved regs */
5506 if (cfg->used_int_regs & (1 << X86_EBX)) {
5507 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5510 if (cfg->used_int_regs & (1 << X86_EDI)) {
5511 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5513 if (cfg->used_int_regs & (1 << X86_ESI)) {
5514 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5517 /* EBP is restored by LEAVE */
5519 for (i = 0; i < X86_NREG; ++i) {
5520 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5526 g_assert (need_stack_frame);
5527 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5531 g_assert (need_stack_frame);
5532 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5535 if (cfg->used_int_regs & (1 << X86_ESI)) {
5536 x86_pop_reg (code, X86_ESI);
5538 if (cfg->used_int_regs & (1 << X86_EDI)) {
5539 x86_pop_reg (code, X86_EDI);
5541 if (cfg->used_int_regs & (1 << X86_EBX)) {
5542 x86_pop_reg (code, X86_EBX);
5546 /* Load returned vtypes into registers if needed */
5547 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5548 if (cinfo->ret.storage == ArgValuetypeInReg) {
5549 for (quad = 0; quad < 2; quad ++) {
5550 switch (cinfo->ret.pair_storage [quad]) {
5552 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5554 case ArgOnFloatFpStack:
5555 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5557 case ArgOnDoubleFpStack:
5558 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5563 g_assert_not_reached ();
5568 if (need_stack_frame)
5571 if (CALLCONV_IS_STDCALL (sig)) {
5572 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5574 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5575 } else if (cinfo->callee_stack_pop)
5576 stack_to_pop = cinfo->callee_stack_pop;
5581 g_assert (need_stack_frame);
5582 x86_ret_imm (code, stack_to_pop);
5587 cfg->code_len = code - cfg->native_code;
5589 g_assert (cfg->code_len < cfg->code_size);
5593 mono_arch_emit_exceptions (MonoCompile *cfg)
5595 MonoJumpInfo *patch_info;
5598 MonoClass *exc_classes [16];
5599 guint8 *exc_throw_start [16], *exc_throw_end [16];
5603 /* Compute needed space */
5604 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5605 if (patch_info->type == MONO_PATCH_INFO_EXC)
5610 * make sure we have enough space for exceptions
5611 * 16 is the size of two push_imm instructions and a call
5613 if (cfg->compile_aot)
5614 code_size = exc_count * 32;
5616 code_size = exc_count * 16;
5618 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5619 cfg->code_size *= 2;
5620 cfg->native_code = mono_realloc_native_code(cfg);
5621 cfg->stat_code_reallocs++;
5624 code = cfg->native_code + cfg->code_len;
5627 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5628 switch (patch_info->type) {
5629 case MONO_PATCH_INFO_EXC: {
5630 MonoClass *exc_class;
5634 x86_patch (patch_info->ip.i + cfg->native_code, code);
5636 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5637 g_assert (exc_class);
5638 throw_ip = patch_info->ip.i;
5640 /* Find a throw sequence for the same exception class */
5641 for (i = 0; i < nthrows; ++i)
5642 if (exc_classes [i] == exc_class)
5645 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5646 x86_jump_code (code, exc_throw_start [i]);
5647 patch_info->type = MONO_PATCH_INFO_NONE;
5652 /* Compute size of code following the push <OFFSET> */
5653 #if defined(__default_codegen__)
5655 #elif defined(__native_client_codegen__)
5656 code = mono_nacl_align (code);
5657 size = kNaClAlignment;
5659 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5661 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5662 /* Use the shorter form */
5664 x86_push_imm (code, 0);
5668 x86_push_imm (code, 0xf0f0f0f0);
5673 exc_classes [nthrows] = exc_class;
5674 exc_throw_start [nthrows] = code;
5677 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5678 patch_info->data.name = "mono_arch_throw_corlib_exception";
5679 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5680 patch_info->ip.i = code - cfg->native_code;
5681 x86_call_code (code, 0);
5682 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5687 exc_throw_end [nthrows] = code;
5699 cfg->code_len = code - cfg->native_code;
5701 g_assert (cfg->code_len < cfg->code_size);
5705 mono_arch_flush_icache (guint8 *code, gint size)
5711 mono_arch_flush_register_windows (void)
5716 mono_arch_is_inst_imm (gint64 imm)
5722 mono_arch_finish_init (void)
5724 if (!g_getenv ("MONO_NO_TLS")) {
5725 #ifndef TARGET_WIN32
5727 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5734 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5738 // Linear handler, the bsearch head compare is shorter
5739 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5740 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5741 // x86_patch(ins,target)
5742 //[1 + 5] x86_jump_mem(inst,mem)
5745 #if defined(__default_codegen__)
5746 #define BR_SMALL_SIZE 2
5747 #define BR_LARGE_SIZE 5
5748 #elif defined(__native_client_codegen__)
5749 /* I suspect the size calculation below is actually incorrect. */
5750 /* TODO: fix the calculation that uses these sizes. */
5751 #define BR_SMALL_SIZE 16
5752 #define BR_LARGE_SIZE 12
5753 #endif /*__native_client_codegen__*/
5754 #define JUMP_IMM_SIZE 6
5755 #define ENABLE_WRONG_METHOD_CHECK 0
5759 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5761 int i, distance = 0;
5762 for (i = start; i < target; ++i)
5763 distance += imt_entries [i]->chunk_size;
5768 * LOCKING: called with the domain lock held
5771 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5772 gpointer fail_tramp)
5776 guint8 *code, *start;
5778 for (i = 0; i < count; ++i) {
5779 MonoIMTCheckItem *item = imt_entries [i];
5780 if (item->is_equals) {
5781 if (item->check_target_idx) {
5782 if (!item->compare_done)
5783 item->chunk_size += CMP_SIZE;
5784 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5787 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5789 item->chunk_size += JUMP_IMM_SIZE;
5790 #if ENABLE_WRONG_METHOD_CHECK
5791 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5796 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5797 imt_entries [item->check_target_idx]->compare_done = TRUE;
5799 size += item->chunk_size;
5801 #if defined(__native_client__) && defined(__native_client_codegen__)
5802 /* In Native Client, we don't re-use thunks, allocate from the */
5803 /* normal code manager paths. */
5804 size = NACL_BUNDLE_ALIGN_UP (size);
5805 code = mono_domain_code_reserve (domain, size);
5808 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5810 code = mono_domain_code_reserve (domain, size);
5813 for (i = 0; i < count; ++i) {
5814 MonoIMTCheckItem *item = imt_entries [i];
5815 item->code_target = code;
5816 if (item->is_equals) {
5817 if (item->check_target_idx) {
5818 if (!item->compare_done)
5819 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5820 item->jmp_code = code;
5821 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5822 if (item->has_target_code)
5823 x86_jump_code (code, item->value.target_code);
5825 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5828 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5829 item->jmp_code = code;
5830 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5831 if (item->has_target_code)
5832 x86_jump_code (code, item->value.target_code);
5834 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5835 x86_patch (item->jmp_code, code);
5836 x86_jump_code (code, fail_tramp);
5837 item->jmp_code = NULL;
5839 /* enable the commented code to assert on wrong method */
5840 #if ENABLE_WRONG_METHOD_CHECK
5841 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5842 item->jmp_code = code;
5843 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5845 if (item->has_target_code)
5846 x86_jump_code (code, item->value.target_code);
5848 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5849 #if ENABLE_WRONG_METHOD_CHECK
5850 x86_patch (item->jmp_code, code);
5851 x86_breakpoint (code);
5852 item->jmp_code = NULL;
5857 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5858 item->jmp_code = code;
5859 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5860 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5862 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5865 /* patch the branches to get to the target items */
5866 for (i = 0; i < count; ++i) {
5867 MonoIMTCheckItem *item = imt_entries [i];
5868 if (item->jmp_code) {
5869 if (item->check_target_idx) {
5870 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5876 mono_stats.imt_thunks_size += code - start;
5877 g_assert (code - start <= size);
5881 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5882 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5886 if (mono_jit_map_is_enabled ()) {
5889 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5891 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5892 mono_emit_jit_tramp (start, code - start, buff);
5896 nacl_domain_code_validate (domain, &start, size, &code);
5897 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
5903 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5905 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5909 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5911 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5915 mono_arch_get_cie_program (void)
5919 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5920 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5926 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5928 MonoInst *ins = NULL;
5931 if (cmethod->klass == mono_defaults.math_class) {
5932 if (strcmp (cmethod->name, "Sin") == 0) {
5934 } else if (strcmp (cmethod->name, "Cos") == 0) {
5936 } else if (strcmp (cmethod->name, "Tan") == 0) {
5938 } else if (strcmp (cmethod->name, "Atan") == 0) {
5940 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5942 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5944 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5948 if (opcode && fsig->param_count == 1) {
5949 MONO_INST_NEW (cfg, ins, opcode);
5950 ins->type = STACK_R8;
5951 ins->dreg = mono_alloc_freg (cfg);
5952 ins->sreg1 = args [0]->dreg;
5953 MONO_ADD_INS (cfg->cbb, ins);
5956 if (cfg->opt & MONO_OPT_CMOV) {
5959 if (strcmp (cmethod->name, "Min") == 0) {
5960 if (fsig->params [0]->type == MONO_TYPE_I4)
5962 } else if (strcmp (cmethod->name, "Max") == 0) {
5963 if (fsig->params [0]->type == MONO_TYPE_I4)
5967 if (opcode && fsig->param_count == 2) {
5968 MONO_INST_NEW (cfg, ins, opcode);
5969 ins->type = STACK_I4;
5970 ins->dreg = mono_alloc_ireg (cfg);
5971 ins->sreg1 = args [0]->dreg;
5972 ins->sreg2 = args [1]->dreg;
5973 MONO_ADD_INS (cfg->cbb, ins);
5978 /* OP_FREM is not IEEE compatible */
5979 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
5980 MONO_INST_NEW (cfg, ins, OP_FREM);
5981 ins->inst_i0 = args [0];
5982 ins->inst_i1 = args [1];
5991 mono_arch_print_tree (MonoInst *tree, int arity)
5997 mono_arch_get_patch_offset (guint8 *code)
5999 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
6001 else if (code [0] == 0xba)
6003 else if (code [0] == 0x68)
6006 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
6007 /* push <OFFSET>(<REG>) */
6009 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
6010 /* call *<OFFSET>(<REG>) */
6012 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
6015 else if ((code [0] == 0x58) && (code [1] == 0x05))
6016 /* pop %eax; add <OFFSET>, %eax */
6018 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6019 /* pop <REG>; add <OFFSET>, <REG> */
6021 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6022 /* mov <REG>, imm */
6025 g_assert_not_reached ();
6031 * mono_breakpoint_clean_code:
6033 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6034 * breakpoints in the original code, they are removed in the copy.
6036 * Returns TRUE if no sw breakpoint was present.
6039 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6042 * If method_start is non-NULL we need to perform bound checks, since we access memory
6043 * at code - offset we could go before the start of the method and end up in a different
6044 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6047 if (!method_start || code - offset >= method_start) {
6048 memcpy (buf, code - offset, size);
6050 int diff = code - method_start;
6051 memset (buf, 0, size);
6052 memcpy (buf + offset - diff, method_start, diff + size - offset);
6058 * mono_x86_get_this_arg_offset:
6060 * Return the offset of the stack location where this is passed during a virtual
6064 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6070 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6072 guint32 esp = regs [X86_ESP];
6079 * The stack looks like:
6083 res = ((MonoObject**)esp) [0];
6087 #define MAX_ARCH_DELEGATE_PARAMS 10
6090 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6092 guint8 *code, *start;
6093 int code_reserve = 64;
6096 * The stack contains:
6102 start = code = mono_global_codeman_reserve (code_reserve);
6104 /* Replace the this argument with the target */
6105 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6106 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6107 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6108 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6110 g_assert ((code - start) < code_reserve);
6113 /* 8 for mov_reg and jump, plus 8 for each parameter */
6114 #ifdef __native_client_codegen__
6115 /* TODO: calculate this size correctly */
6116 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6118 code_reserve = 8 + (param_count * 8);
6119 #endif /* __native_client_codegen__ */
6121 * The stack contains:
6122 * <args in reverse order>
6127 * <args in reverse order>
6130 * without unbalancing the stack.
6131 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6132 * and leaving original spot of first arg as placeholder in stack so
6133 * when callee pops stack everything works.
6136 start = code = mono_global_codeman_reserve (code_reserve);
6138 /* store delegate for access to method_ptr */
6139 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6142 for (i = 0; i < param_count; ++i) {
6143 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6144 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6147 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6149 g_assert ((code - start) < code_reserve);
6152 nacl_global_codeman_validate (&start, code_reserve, &code);
6155 *code_len = code - start;
6157 if (mono_jit_map_is_enabled ()) {
6160 buff = (char*)"delegate_invoke_has_target";
6162 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6163 mono_emit_jit_tramp (start, code - start, buff);
6167 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6173 mono_arch_get_delegate_invoke_impls (void)
6181 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6182 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
6184 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6185 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6186 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
6187 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
6188 g_free (tramp_name);
6195 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6197 guint8 *code, *start;
6199 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6202 /* FIXME: Support more cases */
6203 if (MONO_TYPE_ISSTRUCT (sig->ret))
6207 * The stack contains:
6213 static guint8* cached = NULL;
6218 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6220 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6222 mono_memory_barrier ();
6226 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6229 for (i = 0; i < sig->param_count; ++i)
6230 if (!mono_is_regsize_var (sig->params [i]))
6233 code = cache [sig->param_count];
6237 if (mono_aot_only) {
6238 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6239 start = mono_aot_get_trampoline (name);
6242 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6245 mono_memory_barrier ();
6247 cache [sig->param_count] = start;
6254 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
6256 guint8 *code, *start;
6260 * The stack contains:
6264 start = code = mono_global_codeman_reserve (size);
6266 /* Replace the this argument with the target */
6267 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6268 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6269 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6272 /* Load the IMT reg */
6273 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
6276 /* Load the vtable */
6277 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
6278 x86_jump_membase (code, X86_EAX, offset);
6279 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6285 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6288 case X86_EAX: return ctx->eax;
6289 case X86_EBX: return ctx->ebx;
6290 case X86_ECX: return ctx->ecx;
6291 case X86_EDX: return ctx->edx;
6292 case X86_ESP: return ctx->esp;
6293 case X86_EBP: return ctx->ebp;
6294 case X86_ESI: return ctx->esi;
6295 case X86_EDI: return ctx->edi;
6297 g_assert_not_reached ();
6303 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6331 g_assert_not_reached ();
6335 #ifdef MONO_ARCH_SIMD_INTRINSICS
6338 get_float_to_x_spill_area (MonoCompile *cfg)
6340 if (!cfg->fconv_to_r8_x_var) {
6341 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6342 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6344 return cfg->fconv_to_r8_x_var;
6348 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6351 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6354 int dreg, src_opcode;
6356 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6359 switch (src_opcode = ins->opcode) {
6360 case OP_FCONV_TO_I1:
6361 case OP_FCONV_TO_U1:
6362 case OP_FCONV_TO_I2:
6363 case OP_FCONV_TO_U2:
6364 case OP_FCONV_TO_I4:
6371 /* dreg is the IREG and sreg1 is the FREG */
6372 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6373 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6374 fconv->sreg1 = ins->sreg1;
6375 fconv->dreg = mono_alloc_ireg (cfg);
6376 fconv->type = STACK_VTYPE;
6377 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6379 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6383 ins->opcode = OP_XCONV_R8_TO_I4;
6385 ins->klass = mono_defaults.int32_class;
6386 ins->sreg1 = fconv->dreg;
6388 ins->type = STACK_I4;
6389 ins->backend.source_opcode = src_opcode;
6392 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6395 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6400 if (long_ins->opcode == OP_LNEG) {
6402 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6403 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6404 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6409 #ifdef MONO_ARCH_SIMD_INTRINSICS
6411 if (!(cfg->opt & MONO_OPT_SIMD))
6414 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6415 switch (long_ins->opcode) {
6417 vreg = long_ins->sreg1;
6419 if (long_ins->inst_c0) {
6420 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6421 ins->klass = long_ins->klass;
6422 ins->sreg1 = long_ins->sreg1;
6424 ins->type = STACK_VTYPE;
6425 ins->dreg = vreg = alloc_ireg (cfg);
6426 MONO_ADD_INS (cfg->cbb, ins);
6429 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6430 ins->klass = mono_defaults.int32_class;
6432 ins->type = STACK_I4;
6433 ins->dreg = long_ins->dreg + 1;
6434 MONO_ADD_INS (cfg->cbb, ins);
6436 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6437 ins->klass = long_ins->klass;
6438 ins->sreg1 = long_ins->sreg1;
6439 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6440 ins->type = STACK_VTYPE;
6441 ins->dreg = vreg = alloc_ireg (cfg);
6442 MONO_ADD_INS (cfg->cbb, ins);
6444 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6445 ins->klass = mono_defaults.int32_class;
6447 ins->type = STACK_I4;
6448 ins->dreg = long_ins->dreg + 2;
6449 MONO_ADD_INS (cfg->cbb, ins);
6451 long_ins->opcode = OP_NOP;
6453 case OP_INSERTX_I8_SLOW:
6454 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6455 ins->dreg = long_ins->dreg;
6456 ins->sreg1 = long_ins->dreg;
6457 ins->sreg2 = long_ins->sreg2 + 1;
6458 ins->inst_c0 = long_ins->inst_c0 * 2;
6459 MONO_ADD_INS (cfg->cbb, ins);
6461 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6462 ins->dreg = long_ins->dreg;
6463 ins->sreg1 = long_ins->dreg;
6464 ins->sreg2 = long_ins->sreg2 + 2;
6465 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6466 MONO_ADD_INS (cfg->cbb, ins);
6468 long_ins->opcode = OP_NOP;
6471 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6472 ins->dreg = long_ins->dreg;
6473 ins->sreg1 = long_ins->sreg1 + 1;
6474 ins->klass = long_ins->klass;
6475 ins->type = STACK_VTYPE;
6476 MONO_ADD_INS (cfg->cbb, ins);
6478 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6479 ins->dreg = long_ins->dreg;
6480 ins->sreg1 = long_ins->dreg;
6481 ins->sreg2 = long_ins->sreg1 + 2;
6483 ins->klass = long_ins->klass;
6484 ins->type = STACK_VTYPE;
6485 MONO_ADD_INS (cfg->cbb, ins);
6487 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6488 ins->dreg = long_ins->dreg;
6489 ins->sreg1 = long_ins->dreg;;
6490 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6491 ins->klass = long_ins->klass;
6492 ins->type = STACK_VTYPE;
6493 MONO_ADD_INS (cfg->cbb, ins);
6495 long_ins->opcode = OP_NOP;
6498 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6501 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6503 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6506 gpointer *sp, old_value;
6509 offset = clause->exvar_offset;
6512 bp = MONO_CONTEXT_GET_BP (ctx);
6513 sp = *(gpointer*)(bp + offset);
6516 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6525 * mono_aot_emit_load_got_addr:
6527 * Emit code to load the got address.
6528 * On x86, the result is placed into EBX.
6531 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6533 x86_call_imm (code, 0);
6535 * The patch needs to point to the pop, since the GOT offset needs
6536 * to be added to that address.
6539 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6541 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6542 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6543 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6549 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6552 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6554 g_assert_not_reached ();
6555 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6560 * mono_arch_emit_load_aotconst:
6562 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6563 * TARGET from the mscorlib GOT in full-aot code.
6564 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6568 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6570 /* Load the mscorlib got address */
6571 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6572 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6573 /* arch_emit_got_access () patches this */
6574 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6579 /* Can't put this into mini-x86.h */
6581 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6584 mono_arch_get_trampolines (gboolean aot)
6586 MonoTrampInfo *info;
6587 GSList *tramps = NULL;
6589 mono_x86_get_signal_exception_trampoline (&info, aot);
6591 tramps = g_slist_append (tramps, info);
6598 #define DBG_SIGNAL SIGBUS
6600 #define DBG_SIGNAL SIGSEGV
6603 /* Soft Debug support */
6604 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6607 * mono_arch_set_breakpoint:
6609 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6610 * The location should contain code emitted by OP_SEQ_POINT.
6613 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6618 * In production, we will use int3 (has to fix the size in the md
6619 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6622 g_assert (code [0] == 0x90);
6623 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6627 * mono_arch_clear_breakpoint:
6629 * Clear the breakpoint at IP.
6632 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6637 for (i = 0; i < 6; ++i)
6642 * mono_arch_start_single_stepping:
6644 * Start single stepping.
6647 mono_arch_start_single_stepping (void)
6649 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6653 * mono_arch_stop_single_stepping:
6655 * Stop single stepping.
6658 mono_arch_stop_single_stepping (void)
6660 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6664 * mono_arch_is_single_step_event:
6666 * Return whenever the machine state in SIGCTX corresponds to a single
6670 mono_arch_is_single_step_event (void *info, void *sigctx)
6673 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6675 if (((gpointer)einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6680 siginfo_t* sinfo = (siginfo_t*) info;
6681 /* Sometimes the address is off by 4 */
6682 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6690 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6693 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6694 if (((gpointer)einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6699 siginfo_t* sinfo = (siginfo_t*)info;
6700 /* Sometimes the address is off by 4 */
6701 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6708 #define BREAKPOINT_SIZE 6
6711 * mono_arch_skip_breakpoint:
6713 * See mini-amd64.c for docs.
6716 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6718 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6722 * mono_arch_skip_single_step:
6724 * See mini-amd64.c for docs.
6727 mono_arch_skip_single_step (MonoContext *ctx)
6729 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6733 * mono_arch_get_seq_point_info:
6735 * See mini-amd64.c for docs.
6738 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6745 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6747 ext->lmf.previous_lmf = (gsize)prev_lmf;
6748 /* Mark that this is a MonoLMFExt */
6749 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6750 ext->lmf.ebp = (gssize)ext;
6756 mono_arch_opcode_supported (int opcode)
6759 case OP_ATOMIC_ADD_I4:
6760 case OP_ATOMIC_EXCHANGE_I4:
6761 case OP_ATOMIC_CAS_I4:
6762 case OP_ATOMIC_LOAD_I1:
6763 case OP_ATOMIC_LOAD_I2:
6764 case OP_ATOMIC_LOAD_I4:
6765 case OP_ATOMIC_LOAD_U1:
6766 case OP_ATOMIC_LOAD_U2:
6767 case OP_ATOMIC_LOAD_U4:
6768 case OP_ATOMIC_LOAD_R4:
6769 case OP_ATOMIC_LOAD_R8:
6770 case OP_ATOMIC_STORE_I1:
6771 case OP_ATOMIC_STORE_I2:
6772 case OP_ATOMIC_STORE_I4:
6773 case OP_ATOMIC_STORE_U1:
6774 case OP_ATOMIC_STORE_U2:
6775 case OP_ATOMIC_STORE_U4:
6776 case OP_ATOMIC_STORE_R4:
6777 case OP_ATOMIC_STORE_R8:
6784 #if defined(ENABLE_GSHAREDVT)
6786 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6788 #endif /* !MONOTOUCH */