2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/appdomain.h>
21 #include <mono/metadata/debug-helpers.h>
22 #include <mono/metadata/threads.h>
23 #include <mono/metadata/profiler-private.h>
24 #include <mono/metadata/mono-debug.h>
25 #include <mono/metadata/gc-internal.h>
26 #include <mono/utils/mono-math.h>
27 #include <mono/utils/mono-counters.h>
28 #include <mono/utils/mono-mmap.h>
29 #include <mono/utils/mono-memory-model.h>
37 /* On windows, these hold the key returned by TlsAlloc () */
38 static gint lmf_tls_offset = -1;
39 static gint lmf_addr_tls_offset = -1;
40 static gint appdomain_tls_offset = -1;
43 static gboolean optimize_for_xen = TRUE;
45 #define optimize_for_xen 0
49 static gboolean is_win32 = TRUE;
51 static gboolean is_win32 = FALSE;
54 /* This mutex protects architecture specific caches */
55 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
56 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
57 static CRITICAL_SECTION mini_arch_mutex;
59 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
64 /* Under windows, the default pinvoke calling convention is stdcall */
65 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT))
67 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL)
70 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
73 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
76 #ifdef __native_client_codegen__
77 const guint kNaClAlignment = kNaClAlignmentX86;
78 const guint kNaClAlignmentMask = kNaClAlignmentMaskX86;
80 /* Default alignment for Native Client is 32-byte. */
81 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
83 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
84 /* Check that alignment doesn't cross an alignment boundary. */
86 mono_arch_nacl_pad (guint8 *code, int pad)
88 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
90 if (pad == 0) return code;
91 /* assertion: alignment cannot cross a block boundary */
92 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
93 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
94 while (pad >= kMaxPadding) {
95 x86_padding (code, kMaxPadding);
98 if (pad != 0) x86_padding (code, pad);
103 mono_arch_nacl_skip_nops (guint8 *code)
105 x86_skip_nops (code);
109 #endif /* __native_client_codegen__ */
112 * The code generated for sequence points reads from this location, which is
113 * made read-only when single stepping is enabled.
115 static gpointer ss_trigger_page;
117 /* Enabled breakpoints read from this trigger page */
118 static gpointer bp_trigger_page;
121 mono_arch_regname (int reg)
124 case X86_EAX: return "%eax";
125 case X86_EBX: return "%ebx";
126 case X86_ECX: return "%ecx";
127 case X86_EDX: return "%edx";
128 case X86_ESP: return "%esp";
129 case X86_EBP: return "%ebp";
130 case X86_EDI: return "%edi";
131 case X86_ESI: return "%esi";
137 mono_arch_fregname (int reg)
162 mono_arch_xregname (int reg)
187 mono_x86_patch (unsigned char* code, gpointer target)
189 x86_patch (code, (unsigned char*)target);
210 /* Only if storage == ArgValuetypeInReg */
211 ArgStorage pair_storage [2];
220 gboolean need_stack_align;
221 guint32 stack_align_amount;
222 gboolean vtype_retaddr;
223 /* The index of the vret arg in the argument list */
233 #define FLOAT_PARAM_REGS 0
235 static X86_Reg_No param_regs [] = { 0 };
237 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
238 #define SMALL_STRUCTS_IN_REGS
239 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
243 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
245 ainfo->offset = *stack_size;
247 if (*gr >= PARAM_REGS) {
248 ainfo->storage = ArgOnStack;
249 (*stack_size) += sizeof (gpointer);
252 ainfo->storage = ArgInIReg;
253 ainfo->reg = param_regs [*gr];
259 add_general_pair (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
261 ainfo->offset = *stack_size;
263 g_assert (PARAM_REGS == 0);
265 ainfo->storage = ArgOnStack;
266 (*stack_size) += sizeof (gpointer) * 2;
271 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
273 ainfo->offset = *stack_size;
275 if (*gr >= FLOAT_PARAM_REGS) {
276 ainfo->storage = ArgOnStack;
277 (*stack_size) += is_double ? 8 : 4;
278 ainfo->nslots = is_double ? 2 : 1;
281 /* A double register */
283 ainfo->storage = ArgInDoubleSSEReg;
285 ainfo->storage = ArgInFloatSSEReg;
293 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
295 guint32 *gr, guint32 *fr, guint32 *stack_size)
300 klass = mono_class_from_mono_type (type);
301 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
303 #ifdef SMALL_STRUCTS_IN_REGS
304 if (sig->pinvoke && is_return) {
305 MonoMarshalType *info;
308 * the exact rules are not very well documented, the code below seems to work with the
309 * code generated by gcc 3.3.3 -mno-cygwin.
311 info = mono_marshal_load_type_info (klass);
314 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
316 /* Special case structs with only a float member */
317 if ((info->native_size == 8) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R8)) {
318 ainfo->storage = ArgValuetypeInReg;
319 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
322 if ((info->native_size == 4) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R4)) {
323 ainfo->storage = ArgValuetypeInReg;
324 ainfo->pair_storage [0] = ArgOnFloatFpStack;
327 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
328 ainfo->storage = ArgValuetypeInReg;
329 ainfo->pair_storage [0] = ArgInIReg;
330 ainfo->pair_regs [0] = return_regs [0];
331 if (info->native_size > 4) {
332 ainfo->pair_storage [1] = ArgInIReg;
333 ainfo->pair_regs [1] = return_regs [1];
340 ainfo->offset = *stack_size;
341 ainfo->storage = ArgOnStack;
342 *stack_size += ALIGN_TO (size, sizeof (gpointer));
343 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
349 * Obtain information about a call according to the calling convention.
350 * For x86 ELF, see the "System V Application Binary Interface Intel386
351 * Architecture Processor Supplment, Fourth Edition" document for more
353 * For x86 win32, see ???.
356 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
358 guint32 i, gr, fr, pstart;
360 int n = sig->hasthis + sig->param_count;
361 guint32 stack_size = 0;
362 gboolean is_pinvoke = sig->pinvoke;
370 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
371 switch (ret_type->type) {
372 case MONO_TYPE_BOOLEAN:
383 case MONO_TYPE_FNPTR:
384 case MONO_TYPE_CLASS:
385 case MONO_TYPE_OBJECT:
386 case MONO_TYPE_SZARRAY:
387 case MONO_TYPE_ARRAY:
388 case MONO_TYPE_STRING:
389 cinfo->ret.storage = ArgInIReg;
390 cinfo->ret.reg = X86_EAX;
394 cinfo->ret.storage = ArgInIReg;
395 cinfo->ret.reg = X86_EAX;
396 cinfo->ret.is_pair = TRUE;
399 cinfo->ret.storage = ArgOnFloatFpStack;
402 cinfo->ret.storage = ArgOnDoubleFpStack;
404 case MONO_TYPE_GENERICINST:
405 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
406 cinfo->ret.storage = ArgInIReg;
407 cinfo->ret.reg = X86_EAX;
411 case MONO_TYPE_VALUETYPE:
412 case MONO_TYPE_TYPEDBYREF: {
413 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
415 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
416 if (cinfo->ret.storage == ArgOnStack) {
417 cinfo->vtype_retaddr = TRUE;
418 /* The caller passes the address where the value is stored */
423 cinfo->ret.storage = ArgNone;
426 g_error ("Can't handle as return value 0x%x", sig->ret->type);
432 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
433 * the first argument, allowing 'this' to be always passed in the first arg reg.
434 * Also do this if the first argument is a reference type, since virtual calls
435 * are sometimes made using calli without sig->hasthis set, like in the delegate
438 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
440 add_general (&gr, &stack_size, cinfo->args + 0);
442 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
445 cinfo->vret_arg_offset = stack_size;
446 add_general (&gr, &stack_size, &cinfo->ret);
447 cinfo->vret_arg_index = 1;
451 add_general (&gr, &stack_size, cinfo->args + 0);
453 if (cinfo->vtype_retaddr)
454 add_general (&gr, &stack_size, &cinfo->ret);
457 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
459 fr = FLOAT_PARAM_REGS;
461 /* Emit the signature cookie just before the implicit arguments */
462 add_general (&gr, &stack_size, &cinfo->sig_cookie);
465 for (i = pstart; i < sig->param_count; ++i) {
466 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
469 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
470 /* We allways pass the sig cookie on the stack for simplicity */
472 * Prevent implicit arguments + the sig cookie from being passed
476 fr = FLOAT_PARAM_REGS;
478 /* Emit the signature cookie just before the implicit arguments */
479 add_general (&gr, &stack_size, &cinfo->sig_cookie);
482 if (sig->params [i]->byref) {
483 add_general (&gr, &stack_size, ainfo);
486 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
487 switch (ptype->type) {
488 case MONO_TYPE_BOOLEAN:
491 add_general (&gr, &stack_size, ainfo);
496 add_general (&gr, &stack_size, ainfo);
500 add_general (&gr, &stack_size, ainfo);
505 case MONO_TYPE_FNPTR:
506 case MONO_TYPE_CLASS:
507 case MONO_TYPE_OBJECT:
508 case MONO_TYPE_STRING:
509 case MONO_TYPE_SZARRAY:
510 case MONO_TYPE_ARRAY:
511 add_general (&gr, &stack_size, ainfo);
513 case MONO_TYPE_GENERICINST:
514 if (!mono_type_generic_inst_is_valuetype (ptype)) {
515 add_general (&gr, &stack_size, ainfo);
519 case MONO_TYPE_VALUETYPE:
520 case MONO_TYPE_TYPEDBYREF:
521 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
525 add_general_pair (&gr, &stack_size, ainfo);
528 add_float (&fr, &stack_size, ainfo, FALSE);
531 add_float (&fr, &stack_size, ainfo, TRUE);
534 g_error ("unexpected type 0x%x", ptype->type);
535 g_assert_not_reached ();
539 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
541 fr = FLOAT_PARAM_REGS;
543 /* Emit the signature cookie just before the implicit arguments */
544 add_general (&gr, &stack_size, &cinfo->sig_cookie);
547 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
548 cinfo->need_stack_align = TRUE;
549 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
550 stack_size += cinfo->stack_align_amount;
553 cinfo->stack_usage = stack_size;
554 cinfo->reg_usage = gr;
555 cinfo->freg_usage = fr;
560 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
562 int n = sig->hasthis + sig->param_count;
566 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
568 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
570 return get_call_info_internal (gsctx, cinfo, sig);
574 * mono_arch_get_argument_info:
575 * @csig: a method signature
576 * @param_count: the number of parameters to consider
577 * @arg_info: an array to store the result infos
579 * Gathers information on parameters such as size, alignment and
580 * padding. arg_info should be large enought to hold param_count + 1 entries.
582 * Returns the size of the argument area on the stack.
583 * This should be signal safe, since it is called from
584 * mono_arch_find_jit_info ().
585 * FIXME: The metadata calls might not be signal safe.
588 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
590 int len, k, args_size = 0;
596 /* Avoid g_malloc as it is not signal safe */
597 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
598 cinfo = (CallInfo*)g_newa (guint8*, len);
599 memset (cinfo, 0, len);
601 cinfo = get_call_info_internal (gsctx, cinfo, csig);
603 arg_info [0].offset = offset;
605 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
606 args_size += sizeof (gpointer);
611 args_size += sizeof (gpointer);
615 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
616 /* Emitted after this */
617 args_size += sizeof (gpointer);
621 arg_info [0].size = args_size;
623 for (k = 0; k < param_count; k++) {
624 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
626 /* ignore alignment for now */
629 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
630 arg_info [k].pad = pad;
632 arg_info [k + 1].pad = 0;
633 arg_info [k + 1].size = size;
635 arg_info [k + 1].offset = offset;
638 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
639 /* Emitted after the first arg */
640 args_size += sizeof (gpointer);
645 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
646 align = MONO_ARCH_FRAME_ALIGNMENT;
649 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
650 arg_info [k].pad = pad;
656 mono_x86_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
661 c1 = get_call_info (NULL, NULL, caller_sig);
662 c2 = get_call_info (NULL, NULL, callee_sig);
663 res = c1->stack_usage >= c2->stack_usage;
664 if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
665 /* An address on the callee's stack is passed as the first argument */
674 static const guchar cpuid_impl [] = {
675 0x55, /* push %ebp */
676 0x89, 0xe5, /* mov %esp,%ebp */
677 0x53, /* push %ebx */
678 0x8b, 0x45, 0x08, /* mov 0x8(%ebp),%eax */
679 0x0f, 0xa2, /* cpuid */
680 0x50, /* push %eax */
681 0x8b, 0x45, 0x10, /* mov 0x10(%ebp),%eax */
682 0x89, 0x18, /* mov %ebx,(%eax) */
683 0x8b, 0x45, 0x14, /* mov 0x14(%ebp),%eax */
684 0x89, 0x08, /* mov %ecx,(%eax) */
685 0x8b, 0x45, 0x18, /* mov 0x18(%ebp),%eax */
686 0x89, 0x10, /* mov %edx,(%eax) */
688 0x8b, 0x55, 0x0c, /* mov 0xc(%ebp),%edx */
689 0x89, 0x02, /* mov %eax,(%edx) */
695 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
698 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
700 #if defined(__native_client__)
701 /* Taken from below, the bug listed in the comment is */
702 /* only valid for non-static cases. */
703 __asm__ __volatile__ ("cpuid"
704 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
710 __asm__ __volatile__ (
713 "movl %%eax, %%edx\n"
714 "xorl $0x200000, %%eax\n"
719 "xorl %%edx, %%eax\n"
720 "andl $0x200000, %%eax\n"
742 /* Have to use the code manager to get around WinXP DEP */
743 static CpuidFunc func = NULL;
746 ptr = mono_global_codeman_reserve (sizeof (cpuid_impl));
747 memcpy (ptr, cpuid_impl, sizeof (cpuid_impl));
748 func = (CpuidFunc)ptr;
750 func (id, p_eax, p_ebx, p_ecx, p_edx);
753 * We use this approach because of issues with gcc and pic code, see:
754 * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
755 __asm__ __volatile__ ("cpuid"
756 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
766 * Initialize the cpu to execute managed code.
769 mono_arch_cpu_init (void)
771 /* spec compliance requires running with double precision */
775 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
776 fpcw &= ~X86_FPCW_PRECC_MASK;
777 fpcw |= X86_FPCW_PREC_DOUBLE;
778 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
779 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
781 _control87 (_PC_53, MCW_PC);
786 * Initialize architecture specific code.
789 mono_arch_init (void)
791 InitializeCriticalSection (&mini_arch_mutex);
793 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
794 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
795 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
797 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
798 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
799 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
800 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
805 * Cleanup architecture specific code.
808 mono_arch_cleanup (void)
811 mono_vfree (ss_trigger_page, mono_pagesize ());
813 mono_vfree (bp_trigger_page, mono_pagesize ());
814 DeleteCriticalSection (&mini_arch_mutex);
818 * This function returns the optimizations supported on this cpu.
821 mono_arch_cpu_optimizations (guint32 *exclude_mask)
823 #if !defined(__native_client__)
824 int eax, ebx, ecx, edx;
830 /* The cpuid function allocates from the global codeman */
833 /* Feature Flags function, flags returned in EDX. */
834 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
835 if (edx & (1 << 15)) {
836 opts |= MONO_OPT_CMOV;
838 opts |= MONO_OPT_FCMOV;
840 *exclude_mask |= MONO_OPT_FCMOV;
842 *exclude_mask |= MONO_OPT_CMOV;
844 opts |= MONO_OPT_SSE2;
846 *exclude_mask |= MONO_OPT_SSE2;
848 #ifdef MONO_ARCH_SIMD_INTRINSICS
849 /*SIMD intrinsics require at least SSE2.*/
850 if (!(opts & MONO_OPT_SSE2))
851 *exclude_mask |= MONO_OPT_SIMD;
856 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
861 * This function test for all SSE functions supported.
863 * Returns a bitmask corresponding to all supported versions.
867 mono_arch_cpu_enumerate_simd_versions (void)
869 int eax, ebx, ecx, edx;
870 guint32 sse_opts = 0;
873 /* The cpuid function allocates from the global codeman */
876 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
878 sse_opts |= SIMD_VERSION_SSE1;
880 sse_opts |= SIMD_VERSION_SSE2;
882 sse_opts |= SIMD_VERSION_SSE3;
884 sse_opts |= SIMD_VERSION_SSSE3;
886 sse_opts |= SIMD_VERSION_SSE41;
888 sse_opts |= SIMD_VERSION_SSE42;
891 /* Yes, all this needs to be done to check for sse4a.
892 See: "Amd: CPUID Specification"
894 if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
895 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
896 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
897 cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
899 sse_opts |= SIMD_VERSION_SSE4a;
908 * Determine whenever the trap whose info is in SIGINFO is caused by
912 mono_arch_is_int_overflow (void *sigctx, void *info)
917 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
919 ip = (guint8*)ctx.eip;
921 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
925 switch (x86_modrm_rm (ip [1])) {
945 g_assert_not_reached ();
957 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
962 for (i = 0; i < cfg->num_varinfo; i++) {
963 MonoInst *ins = cfg->varinfo [i];
964 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
967 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
970 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
971 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
974 /* we dont allocate I1 to registers because there is no simply way to sign extend
975 * 8bit quantities in caller saved registers on x86 */
976 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
977 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
978 g_assert (i == vmv->idx);
979 vars = g_list_prepend (vars, vmv);
983 vars = mono_varlist_sort (cfg, vars, 0);
989 mono_arch_get_global_int_regs (MonoCompile *cfg)
993 /* we can use 3 registers for global allocation */
994 regs = g_list_prepend (regs, (gpointer)X86_EBX);
995 regs = g_list_prepend (regs, (gpointer)X86_ESI);
996 regs = g_list_prepend (regs, (gpointer)X86_EDI);
1002 * mono_arch_regalloc_cost:
1004 * Return the cost, in number of memory references, of the action of
1005 * allocating the variable VMV into a register during global register
1009 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1011 MonoInst *ins = cfg->varinfo [vmv->idx];
1013 if (cfg->method->save_lmf)
1014 /* The register is already saved */
1015 return (ins->opcode == OP_ARG) ? 1 : 0;
1017 /* push+pop+possible load if it is an argument */
1018 return (ins->opcode == OP_ARG) ? 3 : 2;
1022 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
1024 static int inited = FALSE;
1025 static int count = 0;
1027 if (cfg->arch.need_stack_frame_inited) {
1028 g_assert (cfg->arch.need_stack_frame == flag);
1032 cfg->arch.need_stack_frame = flag;
1033 cfg->arch.need_stack_frame_inited = TRUE;
1039 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
1044 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
1048 needs_stack_frame (MonoCompile *cfg)
1050 MonoMethodSignature *sig;
1051 MonoMethodHeader *header;
1052 gboolean result = FALSE;
1054 #if defined(__APPLE__)
1055 /*OSX requires stack frame code to have the correct alignment. */
1059 if (cfg->arch.need_stack_frame_inited)
1060 return cfg->arch.need_stack_frame;
1062 header = cfg->header;
1063 sig = mono_method_signature (cfg->method);
1065 if (cfg->disable_omit_fp)
1067 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1069 else if (cfg->method->save_lmf)
1071 else if (cfg->stack_offset)
1073 else if (cfg->param_area)
1075 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1077 else if (header->num_clauses)
1079 else if (sig->param_count + sig->hasthis)
1081 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1083 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1084 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1087 set_needs_stack_frame (cfg, result);
1089 return cfg->arch.need_stack_frame;
1093 * Set var information according to the calling convention. X86 version.
1094 * The locals var stuff should most likely be split in another method.
1097 mono_arch_allocate_vars (MonoCompile *cfg)
1099 MonoMethodSignature *sig;
1100 MonoMethodHeader *header;
1102 guint32 locals_stack_size, locals_stack_align;
1107 header = cfg->header;
1108 sig = mono_method_signature (cfg->method);
1110 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1112 cfg->frame_reg = X86_EBP;
1115 /* Reserve space to save LMF and caller saved registers */
1117 if (cfg->method->save_lmf) {
1118 offset += sizeof (MonoLMF);
1120 if (cfg->used_int_regs & (1 << X86_EBX)) {
1124 if (cfg->used_int_regs & (1 << X86_EDI)) {
1128 if (cfg->used_int_regs & (1 << X86_ESI)) {
1133 switch (cinfo->ret.storage) {
1134 case ArgValuetypeInReg:
1135 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1137 cfg->ret->opcode = OP_REGOFFSET;
1138 cfg->ret->inst_basereg = X86_EBP;
1139 cfg->ret->inst_offset = - offset;
1145 /* Allocate locals */
1146 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1147 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1148 char *mname = mono_method_full_name (cfg->method, TRUE);
1149 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1150 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1154 if (locals_stack_align) {
1155 int prev_offset = offset;
1157 offset += (locals_stack_align - 1);
1158 offset &= ~(locals_stack_align - 1);
1160 while (prev_offset < offset) {
1162 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1165 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1166 cfg->locals_max_stack_offset = - offset;
1168 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1169 * have locals larger than 8 bytes we need to make sure that
1170 * they have the appropriate offset.
1172 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1173 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1174 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1175 if (offsets [i] != -1) {
1176 MonoInst *inst = cfg->varinfo [i];
1177 inst->opcode = OP_REGOFFSET;
1178 inst->inst_basereg = X86_EBP;
1179 inst->inst_offset = - (offset + offsets [i]);
1180 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1183 offset += locals_stack_size;
1187 * Allocate arguments+return value
1190 switch (cinfo->ret.storage) {
1192 if (cfg->vret_addr) {
1194 * In the new IR, the cfg->vret_addr variable represents the
1195 * vtype return value.
1197 cfg->vret_addr->opcode = OP_REGOFFSET;
1198 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1199 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1200 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1201 printf ("vret_addr =");
1202 mono_print_ins (cfg->vret_addr);
1205 cfg->ret->opcode = OP_REGOFFSET;
1206 cfg->ret->inst_basereg = X86_EBP;
1207 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1210 case ArgValuetypeInReg:
1213 cfg->ret->opcode = OP_REGVAR;
1214 cfg->ret->inst_c0 = cinfo->ret.reg;
1215 cfg->ret->dreg = cinfo->ret.reg;
1218 case ArgOnFloatFpStack:
1219 case ArgOnDoubleFpStack:
1222 g_assert_not_reached ();
1225 if (sig->call_convention == MONO_CALL_VARARG) {
1226 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1227 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1230 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1231 ArgInfo *ainfo = &cinfo->args [i];
1232 inst = cfg->args [i];
1233 if (inst->opcode != OP_REGVAR) {
1234 inst->opcode = OP_REGOFFSET;
1235 inst->inst_basereg = X86_EBP;
1237 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1240 cfg->stack_offset = offset;
1244 mono_arch_create_vars (MonoCompile *cfg)
1246 MonoMethodSignature *sig;
1249 sig = mono_method_signature (cfg->method);
1251 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1253 if (cinfo->ret.storage == ArgValuetypeInReg)
1254 cfg->ret_var_is_local = TRUE;
1255 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig->ret) || mini_is_gsharedvt_variable_type (cfg, sig->ret))) {
1256 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1259 cfg->arch_eh_jit_info = 1;
1263 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1264 * so we try to do it just once when we have multiple fp arguments in a row.
1265 * We don't use this mechanism generally because for int arguments the generated code
1266 * is slightly bigger and new generation cpus optimize away the dependency chains
1267 * created by push instructions on the esp value.
1268 * fp_arg_setup is the first argument in the execution sequence where the esp register
1271 static G_GNUC_UNUSED int
1272 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1277 for (; start_arg < sig->param_count; ++start_arg) {
1278 t = mini_type_get_underlying_type (NULL, sig->params [start_arg]);
1279 if (!t->byref && t->type == MONO_TYPE_R8) {
1280 fp_space += sizeof (double);
1281 *fp_arg_setup = start_arg;
1290 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1292 MonoMethodSignature *tmp_sig;
1296 * mono_ArgIterator_Setup assumes the signature cookie is
1297 * passed first and all the arguments which were before it are
1298 * passed on the stack after the signature. So compensate by
1299 * passing a different signature.
1301 tmp_sig = mono_metadata_signature_dup (call->signature);
1302 tmp_sig->param_count -= call->signature->sentinelpos;
1303 tmp_sig->sentinelpos = 0;
1304 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1306 if (cfg->compile_aot) {
1307 sig_reg = mono_alloc_ireg (cfg);
1308 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1309 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, sig_reg);
1311 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1317 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1322 LLVMCallInfo *linfo;
1325 n = sig->param_count + sig->hasthis;
1327 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1329 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1332 * LLVM always uses the native ABI while we use our own ABI, the
1333 * only difference is the handling of vtypes:
1334 * - we only pass/receive them in registers in some cases, and only
1335 * in 1 or 2 integer registers.
1337 if (cinfo->ret.storage == ArgValuetypeInReg) {
1339 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1340 cfg->disable_llvm = TRUE;
1344 cfg->exception_message = g_strdup ("vtype ret in call");
1345 cfg->disable_llvm = TRUE;
1347 linfo->ret.storage = LLVMArgVtypeInReg;
1348 for (j = 0; j < 2; ++j)
1349 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1353 if (mini_type_is_vtype (cfg, sig->ret) && cinfo->ret.storage == ArgInIReg) {
1354 /* Vtype returned using a hidden argument */
1355 linfo->ret.storage = LLVMArgVtypeRetAddr;
1356 linfo->vret_arg_index = cinfo->vret_arg_index;
1359 if (mini_type_is_vtype (cfg, sig->ret) && cinfo->ret.storage != ArgInIReg) {
1361 cfg->exception_message = g_strdup ("vtype ret in call");
1362 cfg->disable_llvm = TRUE;
1365 for (i = 0; i < n; ++i) {
1366 ainfo = cinfo->args + i;
1368 if (i >= sig->hasthis)
1369 t = sig->params [i - sig->hasthis];
1371 t = &mono_defaults.int_class->byval_arg;
1373 linfo->args [i].storage = LLVMArgNone;
1375 switch (ainfo->storage) {
1377 linfo->args [i].storage = LLVMArgInIReg;
1379 case ArgInDoubleSSEReg:
1380 case ArgInFloatSSEReg:
1381 linfo->args [i].storage = LLVMArgInFPReg;
1384 if (mini_type_is_vtype (cfg, t)) {
1385 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1386 /* LLVM seems to allocate argument space for empty structures too */
1387 linfo->args [i].storage = LLVMArgNone;
1389 linfo->args [i].storage = LLVMArgVtypeByVal;
1391 linfo->args [i].storage = LLVMArgInIReg;
1393 if (t->type == MONO_TYPE_R4)
1394 linfo->args [i].storage = LLVMArgInFPReg;
1395 else if (t->type == MONO_TYPE_R8)
1396 linfo->args [i].storage = LLVMArgInFPReg;
1400 case ArgValuetypeInReg:
1402 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1403 cfg->disable_llvm = TRUE;
1407 cfg->exception_message = g_strdup ("vtype arg");
1408 cfg->disable_llvm = TRUE;
1410 linfo->args [i].storage = LLVMArgVtypeInReg;
1411 for (j = 0; j < 2; ++j)
1412 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1416 cfg->exception_message = g_strdup ("ainfo->storage");
1417 cfg->disable_llvm = TRUE;
1427 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1429 if (cfg->compute_gc_maps) {
1432 /* On x86, the offsets are from the sp value before the start of the call sequence */
1434 t = &mono_defaults.int_class->byval_arg;
1435 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1440 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1443 MonoMethodSignature *sig;
1446 int sentinelpos = 0, sp_offset = 0;
1448 sig = call->signature;
1449 n = sig->param_count + sig->hasthis;
1451 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1453 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1454 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1456 if (cinfo->need_stack_align) {
1457 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1458 arg->dreg = X86_ESP;
1459 arg->sreg1 = X86_ESP;
1460 arg->inst_imm = cinfo->stack_align_amount;
1461 MONO_ADD_INS (cfg->cbb, arg);
1462 for (i = 0; i < cinfo->stack_align_amount; i += sizeof (mgreg_t)) {
1465 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1469 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1470 if (cinfo->ret.storage == ArgValuetypeInReg) {
1472 * Tell the JIT to use a more efficient calling convention: call using
1473 * OP_CALL, compute the result location after the call, and save the
1476 call->vret_in_reg = TRUE;
1478 NULLIFY_INS (call->vret_var);
1482 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1484 /* Handle the case where there are no implicit arguments */
1485 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1486 emit_sig_cookie (cfg, call, cinfo);
1488 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1491 /* Arguments are pushed in the reverse order */
1492 for (i = n - 1; i >= 0; i --) {
1493 ArgInfo *ainfo = cinfo->args + i;
1494 MonoType *orig_type, *t;
1497 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1498 /* Push the vret arg before the first argument */
1500 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1501 vtarg->type = STACK_MP;
1502 vtarg->sreg1 = call->vret_var->dreg;
1503 MONO_ADD_INS (cfg->cbb, vtarg);
1505 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1508 if (i >= sig->hasthis)
1509 t = sig->params [i - sig->hasthis];
1511 t = &mono_defaults.int_class->byval_arg;
1513 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1515 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1517 in = call->args [i];
1518 arg->cil_code = in->cil_code;
1519 arg->sreg1 = in->dreg;
1520 arg->type = in->type;
1522 g_assert (in->dreg != -1);
1524 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1528 g_assert (in->klass);
1530 if (t->type == MONO_TYPE_TYPEDBYREF) {
1531 size = sizeof (MonoTypedRef);
1532 align = sizeof (gpointer);
1535 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1539 arg->opcode = OP_OUTARG_VT;
1540 arg->sreg1 = in->dreg;
1541 arg->klass = in->klass;
1542 arg->backend.size = size;
1544 MONO_ADD_INS (cfg->cbb, arg);
1546 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1551 switch (ainfo->storage) {
1553 arg->opcode = OP_X86_PUSH;
1555 if (t->type == MONO_TYPE_R4) {
1556 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1557 arg->opcode = OP_STORER4_MEMBASE_REG;
1558 arg->inst_destbasereg = X86_ESP;
1559 arg->inst_offset = 0;
1561 } else if (t->type == MONO_TYPE_R8) {
1562 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1563 arg->opcode = OP_STORER8_MEMBASE_REG;
1564 arg->inst_destbasereg = X86_ESP;
1565 arg->inst_offset = 0;
1567 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1569 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1575 g_assert_not_reached ();
1578 MONO_ADD_INS (cfg->cbb, arg);
1580 sp_offset += argsize;
1582 if (cfg->compute_gc_maps) {
1584 /* FIXME: The == STACK_OBJ check might be fragile ? */
1585 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1587 if (call->need_unbox_trampoline)
1588 /* The unbox trampoline transforms this into a managed pointer */
1589 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.int_class->this_arg);
1591 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.object_class->byval_arg);
1593 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1597 for (j = 0; j < argsize; j += 4)
1598 emit_gc_param_slot_def (cfg, sp_offset - j, NULL);
1603 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1604 /* Emit the signature cookie just before the implicit arguments */
1605 emit_sig_cookie (cfg, call, cinfo);
1607 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1611 if (sig->ret && (MONO_TYPE_ISSTRUCT (sig->ret) || cinfo->vtype_retaddr)) {
1614 if (cinfo->ret.storage == ArgValuetypeInReg) {
1617 else if (cinfo->ret.storage == ArgInIReg) {
1619 /* The return address is passed in a register */
1620 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1621 vtarg->sreg1 = call->inst.dreg;
1622 vtarg->dreg = mono_alloc_ireg (cfg);
1623 MONO_ADD_INS (cfg->cbb, vtarg);
1625 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1626 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1628 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1629 vtarg->type = STACK_MP;
1630 vtarg->sreg1 = call->vret_var->dreg;
1631 MONO_ADD_INS (cfg->cbb, vtarg);
1633 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1636 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1637 if (cinfo->ret.storage != ArgValuetypeInReg)
1638 cinfo->stack_usage -= 4;
1641 call->stack_usage = cinfo->stack_usage;
1642 call->stack_align_amount = cinfo->stack_align_amount;
1643 cfg->arch.param_area_size = MAX (cfg->arch.param_area_size, sp_offset);
1647 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1650 int size = ins->backend.size;
1653 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1654 arg->sreg1 = src->dreg;
1656 MONO_ADD_INS (cfg->cbb, arg);
1657 } else if (size <= 20) {
1658 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1659 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1661 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1662 arg->inst_basereg = src->dreg;
1663 arg->inst_offset = 0;
1664 arg->inst_imm = size;
1666 MONO_ADD_INS (cfg->cbb, arg);
1671 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1673 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1676 if (ret->type == MONO_TYPE_R4) {
1677 if (COMPILE_LLVM (cfg))
1678 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1681 } else if (ret->type == MONO_TYPE_R8) {
1682 if (COMPILE_LLVM (cfg))
1683 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1686 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1687 if (COMPILE_LLVM (cfg))
1688 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1690 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1691 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1697 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1701 * Allow tracing to work with this interface (with an optional argument)
1704 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1708 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1709 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1711 /* if some args are passed in registers, we need to save them here */
1712 x86_push_reg (code, X86_EBP);
1714 if (cfg->compile_aot) {
1715 x86_push_imm (code, cfg->method);
1716 x86_mov_reg_imm (code, X86_EAX, func);
1717 x86_call_reg (code, X86_EAX);
1719 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1720 x86_push_imm (code, cfg->method);
1721 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1722 x86_call_code (code, 0);
1724 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1738 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1741 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1742 MonoMethod *method = cfg->method;
1743 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1745 switch (ret_type->type) {
1746 case MONO_TYPE_VOID:
1747 /* special case string .ctor icall */
1748 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1749 save_mode = SAVE_EAX;
1750 stack_usage = enable_arguments ? 8 : 4;
1752 save_mode = SAVE_NONE;
1756 save_mode = SAVE_EAX_EDX;
1757 stack_usage = enable_arguments ? 16 : 8;
1761 save_mode = SAVE_FP;
1762 stack_usage = enable_arguments ? 16 : 8;
1764 case MONO_TYPE_GENERICINST:
1765 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1766 save_mode = SAVE_EAX;
1767 stack_usage = enable_arguments ? 8 : 4;
1771 case MONO_TYPE_VALUETYPE:
1772 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1773 save_mode = SAVE_STRUCT;
1774 stack_usage = enable_arguments ? 4 : 0;
1777 save_mode = SAVE_EAX;
1778 stack_usage = enable_arguments ? 8 : 4;
1782 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1784 switch (save_mode) {
1786 x86_push_reg (code, X86_EDX);
1787 x86_push_reg (code, X86_EAX);
1788 if (enable_arguments) {
1789 x86_push_reg (code, X86_EDX);
1790 x86_push_reg (code, X86_EAX);
1795 x86_push_reg (code, X86_EAX);
1796 if (enable_arguments) {
1797 x86_push_reg (code, X86_EAX);
1802 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1803 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1804 if (enable_arguments) {
1805 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1806 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1811 if (enable_arguments) {
1812 x86_push_membase (code, X86_EBP, 8);
1821 if (cfg->compile_aot) {
1822 x86_push_imm (code, method);
1823 x86_mov_reg_imm (code, X86_EAX, func);
1824 x86_call_reg (code, X86_EAX);
1826 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1827 x86_push_imm (code, method);
1828 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1829 x86_call_code (code, 0);
1832 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1834 switch (save_mode) {
1836 x86_pop_reg (code, X86_EAX);
1837 x86_pop_reg (code, X86_EDX);
1840 x86_pop_reg (code, X86_EAX);
1843 x86_fld_membase (code, X86_ESP, 0, TRUE);
1844 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1851 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1856 #define EMIT_COND_BRANCH(ins,cond,sign) \
1857 if (ins->inst_true_bb->native_offset) { \
1858 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1860 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1861 if ((cfg->opt & MONO_OPT_BRANCH) && \
1862 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1863 x86_branch8 (code, cond, 0, sign); \
1865 x86_branch32 (code, cond, 0, sign); \
1869 * Emit an exception if condition is fail and
1870 * if possible do a directly branch to target
1872 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1874 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1875 if (tins == NULL) { \
1876 mono_add_patch_info (cfg, code - cfg->native_code, \
1877 MONO_PATCH_INFO_EXC, exc_name); \
1878 x86_branch32 (code, cond, 0, signed); \
1880 EMIT_COND_BRANCH (tins, cond, signed); \
1884 #define EMIT_FPCOMPARE(code) do { \
1885 x86_fcompp (code); \
1886 x86_fnstsw (code); \
1891 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1893 gboolean needs_paddings = TRUE;
1895 MonoJumpInfo *jinfo = NULL;
1897 if (cfg->abs_patches) {
1898 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1899 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1900 needs_paddings = FALSE;
1903 if (cfg->compile_aot)
1904 needs_paddings = FALSE;
1905 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1906 This is required for code patching to be safe on SMP machines.
1908 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1909 #ifndef __native_client_codegen__
1910 if (needs_paddings && pad_size)
1911 x86_padding (code, 4 - pad_size);
1914 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1915 x86_call_code (code, 0);
1920 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1923 * mono_peephole_pass_1:
1925 * Perform peephole opts which should/can be performed before local regalloc
1928 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1932 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1933 MonoInst *last_ins = ins->prev;
1935 switch (ins->opcode) {
1938 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1940 * X86_LEA is like ADD, but doesn't have the
1941 * sreg1==dreg restriction.
1943 ins->opcode = OP_X86_LEA_MEMBASE;
1944 ins->inst_basereg = ins->sreg1;
1945 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1946 ins->opcode = OP_X86_INC_REG;
1950 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1951 ins->opcode = OP_X86_LEA_MEMBASE;
1952 ins->inst_basereg = ins->sreg1;
1953 ins->inst_imm = -ins->inst_imm;
1954 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1955 ins->opcode = OP_X86_DEC_REG;
1957 case OP_COMPARE_IMM:
1958 case OP_ICOMPARE_IMM:
1959 /* OP_COMPARE_IMM (reg, 0)
1961 * OP_X86_TEST_NULL (reg)
1964 ins->opcode = OP_X86_TEST_NULL;
1966 case OP_X86_COMPARE_MEMBASE_IMM:
1968 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1969 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1971 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1972 * OP_COMPARE_IMM reg, imm
1974 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1976 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1977 ins->inst_basereg == last_ins->inst_destbasereg &&
1978 ins->inst_offset == last_ins->inst_offset) {
1979 ins->opcode = OP_COMPARE_IMM;
1980 ins->sreg1 = last_ins->sreg1;
1982 /* check if we can remove cmp reg,0 with test null */
1984 ins->opcode = OP_X86_TEST_NULL;
1988 case OP_X86_PUSH_MEMBASE:
1989 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1990 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1991 ins->inst_basereg == last_ins->inst_destbasereg &&
1992 ins->inst_offset == last_ins->inst_offset) {
1993 ins->opcode = OP_X86_PUSH;
1994 ins->sreg1 = last_ins->sreg1;
1999 mono_peephole_ins (bb, ins);
2004 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2008 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2009 switch (ins->opcode) {
2011 /* reg = 0 -> XOR (reg, reg) */
2012 /* XOR sets cflags on x86, so we cant do it always */
2013 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2016 ins->opcode = OP_IXOR;
2017 ins->sreg1 = ins->dreg;
2018 ins->sreg2 = ins->dreg;
2021 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2022 * since it takes 3 bytes instead of 7.
2024 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2025 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2026 ins2->opcode = OP_STORE_MEMBASE_REG;
2027 ins2->sreg1 = ins->dreg;
2029 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2030 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2031 ins2->sreg1 = ins->dreg;
2033 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2034 /* Continue iteration */
2043 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2044 ins->opcode = OP_X86_INC_REG;
2048 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2049 ins->opcode = OP_X86_DEC_REG;
2053 mono_peephole_ins (bb, ins);
2058 * mono_arch_lowering_pass:
2060 * Converts complex opcodes into simpler ones so that each IR instruction
2061 * corresponds to one machine instruction.
2064 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2066 MonoInst *ins, *next;
2069 * FIXME: Need to add more instructions, but the current machine
2070 * description can't model some parts of the composite instructions like
2073 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2074 switch (ins->opcode) {
2077 case OP_IDIV_UN_IMM:
2078 case OP_IREM_UN_IMM:
2080 * Keep the cases where we could generated optimized code, otherwise convert
2081 * to the non-imm variant.
2083 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2085 mono_decompose_op_imm (cfg, bb, ins);
2092 bb->max_vreg = cfg->next_vreg;
2096 branch_cc_table [] = {
2097 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2098 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2099 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2102 /* Maps CMP_... constants to X86_CC_... constants */
2105 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2106 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2110 cc_signed_table [] = {
2111 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2112 FALSE, FALSE, FALSE, FALSE
2115 static unsigned char*
2116 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2118 #define XMM_TEMP_REG 0
2119 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2120 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2121 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2122 /* optimize by assigning a local var for this use so we avoid
2123 * the stack manipulations */
2124 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2125 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2126 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2127 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2128 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2130 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2132 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2135 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2136 x86_fnstcw_membase(code, X86_ESP, 0);
2137 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2138 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2139 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2140 x86_fldcw_membase (code, X86_ESP, 2);
2142 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2143 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2144 x86_pop_reg (code, dreg);
2145 /* FIXME: need the high register
2146 * x86_pop_reg (code, dreg_high);
2149 x86_push_reg (code, X86_EAX); // SP = SP - 4
2150 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2151 x86_pop_reg (code, dreg);
2153 x86_fldcw_membase (code, X86_ESP, 0);
2154 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2157 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2159 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2163 static unsigned char*
2164 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2166 int sreg = tree->sreg1;
2167 int need_touch = FALSE;
2169 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2178 * If requested stack size is larger than one page,
2179 * perform stack-touch operation
2182 * Generate stack probe code.
2183 * Under Windows, it is necessary to allocate one page at a time,
2184 * "touching" stack after each successful sub-allocation. This is
2185 * because of the way stack growth is implemented - there is a
2186 * guard page before the lowest stack page that is currently commited.
2187 * Stack normally grows sequentially so OS traps access to the
2188 * guard page and commits more pages when needed.
2190 x86_test_reg_imm (code, sreg, ~0xFFF);
2191 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2193 br[2] = code; /* loop */
2194 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2195 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2198 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2199 * that follows only initializes the last part of the area.
2201 /* Same as the init code below with size==0x1000 */
2202 if (tree->flags & MONO_INST_INIT) {
2203 x86_push_reg (code, X86_EAX);
2204 x86_push_reg (code, X86_ECX);
2205 x86_push_reg (code, X86_EDI);
2206 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2207 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2208 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2210 x86_prefix (code, X86_REP_PREFIX);
2212 x86_pop_reg (code, X86_EDI);
2213 x86_pop_reg (code, X86_ECX);
2214 x86_pop_reg (code, X86_EAX);
2217 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2218 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2219 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2220 x86_patch (br[3], br[2]);
2221 x86_test_reg_reg (code, sreg, sreg);
2222 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2223 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2225 br[1] = code; x86_jump8 (code, 0);
2227 x86_patch (br[0], code);
2228 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2229 x86_patch (br[1], code);
2230 x86_patch (br[4], code);
2233 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2235 if (tree->flags & MONO_INST_INIT) {
2237 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2238 x86_push_reg (code, X86_EAX);
2241 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2242 x86_push_reg (code, X86_ECX);
2245 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2246 x86_push_reg (code, X86_EDI);
2250 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2251 if (sreg != X86_ECX)
2252 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2253 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2255 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2257 x86_prefix (code, X86_REP_PREFIX);
2260 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2261 x86_pop_reg (code, X86_EDI);
2262 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2263 x86_pop_reg (code, X86_ECX);
2264 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2265 x86_pop_reg (code, X86_EAX);
2272 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2274 /* Move return value to the target register */
2275 switch (ins->opcode) {
2278 case OP_CALL_MEMBASE:
2279 if (ins->dreg != X86_EAX)
2280 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2290 static int tls_gs_offset;
2294 mono_x86_have_tls_get (void)
2297 static gboolean have_tls_get = FALSE;
2298 static gboolean inited = FALSE;
2302 return have_tls_get;
2304 ins = (guint32*)pthread_getspecific;
2306 * We're looking for these two instructions:
2308 * mov 0x4(%esp),%eax
2309 * mov %gs:[offset](,%eax,4),%eax
2311 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2312 tls_gs_offset = ins [2];
2316 return have_tls_get;
2317 #elif defined(TARGET_ANDROID)
2325 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2327 #if defined(__APPLE__)
2328 x86_prefix (code, X86_GS_PREFIX);
2329 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2330 #elif defined(TARGET_WIN32)
2331 g_assert_not_reached ();
2333 x86_prefix (code, X86_GS_PREFIX);
2334 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2340 * mono_x86_emit_tls_get:
2341 * @code: buffer to store code to
2342 * @dreg: hard register where to place the result
2343 * @tls_offset: offset info
2345 * mono_x86_emit_tls_get emits in @code the native code that puts in
2346 * the dreg register the item in the thread local storage identified
2349 * Returns: a pointer to the end of the stored code
2352 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2354 #if defined(__APPLE__)
2355 x86_prefix (code, X86_GS_PREFIX);
2356 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2357 #elif defined(TARGET_WIN32)
2359 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2360 * Journal and/or a disassembly of the TlsGet () function.
2362 g_assert (tls_offset < 64);
2363 x86_prefix (code, X86_FS_PREFIX);
2364 x86_mov_reg_mem (code, dreg, 0x18, 4);
2365 /* Dunno what this does but TlsGetValue () contains it */
2366 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2367 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2369 if (optimize_for_xen) {
2370 x86_prefix (code, X86_GS_PREFIX);
2371 x86_mov_reg_mem (code, dreg, 0, 4);
2372 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2374 x86_prefix (code, X86_GS_PREFIX);
2375 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2382 * emit_load_volatile_arguments:
2384 * Load volatile arguments from the stack to the original input registers.
2385 * Required before a tail call.
2388 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2390 MonoMethod *method = cfg->method;
2391 MonoMethodSignature *sig;
2396 /* FIXME: Generate intermediate code instead */
2398 sig = mono_method_signature (method);
2400 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2402 /* This is the opposite of the code in emit_prolog */
2404 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2405 ArgInfo *ainfo = cinfo->args + i;
2407 inst = cfg->args [i];
2409 if (sig->hasthis && (i == 0))
2410 arg_type = &mono_defaults.object_class->byval_arg;
2412 arg_type = sig->params [i - sig->hasthis];
2415 * On x86, the arguments are either in their original stack locations, or in
2418 if (inst->opcode == OP_REGVAR) {
2419 g_assert (ainfo->storage == ArgOnStack);
2421 x86_mov_membase_reg (code, X86_EBP, inst->inst_offset, inst->dreg, 4);
2428 #define REAL_PRINT_REG(text,reg) \
2429 mono_assert (reg >= 0); \
2430 x86_push_reg (code, X86_EAX); \
2431 x86_push_reg (code, X86_EDX); \
2432 x86_push_reg (code, X86_ECX); \
2433 x86_push_reg (code, reg); \
2434 x86_push_imm (code, reg); \
2435 x86_push_imm (code, text " %d %p\n"); \
2436 x86_mov_reg_imm (code, X86_EAX, printf); \
2437 x86_call_reg (code, X86_EAX); \
2438 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2439 x86_pop_reg (code, X86_ECX); \
2440 x86_pop_reg (code, X86_EDX); \
2441 x86_pop_reg (code, X86_EAX);
2443 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2444 #ifdef __native__client_codegen__
2445 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2448 /* benchmark and set based on cpu */
2449 #define LOOP_ALIGNMENT 8
2450 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2454 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2459 guint8 *code = cfg->native_code + cfg->code_len;
2462 if (cfg->opt & MONO_OPT_LOOP) {
2463 int pad, align = LOOP_ALIGNMENT;
2464 /* set alignment depending on cpu */
2465 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2467 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2468 x86_padding (code, pad);
2469 cfg->code_len += pad;
2470 bb->native_offset = cfg->code_len;
2473 #ifdef __native_client_codegen__
2475 /* For Native Client, all indirect call/jump targets must be */
2476 /* 32-byte aligned. Exception handler blocks are jumped to */
2477 /* indirectly as well. */
2478 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2479 (bb->flags & BB_EXCEPTION_HANDLER);
2481 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2482 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2483 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2484 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2485 cfg->code_len += pad;
2486 bb->native_offset = cfg->code_len;
2489 #endif /* __native_client_codegen__ */
2490 if (cfg->verbose_level > 2)
2491 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2493 cpos = bb->max_offset;
2495 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2496 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2497 g_assert (!cfg->compile_aot);
2500 cov->data [bb->dfn].cil_code = bb->cil_code;
2501 /* this is not thread save, but good enough */
2502 x86_inc_mem (code, &cov->data [bb->dfn].count);
2505 offset = code - cfg->native_code;
2507 mono_debug_open_block (cfg, bb, offset);
2509 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2510 x86_breakpoint (code);
2512 MONO_BB_FOR_EACH_INS (bb, ins) {
2513 offset = code - cfg->native_code;
2515 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2517 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2519 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2520 cfg->code_size *= 2;
2521 cfg->native_code = mono_realloc_native_code(cfg);
2522 code = cfg->native_code + offset;
2523 cfg->stat_code_reallocs++;
2526 if (cfg->debug_info)
2527 mono_debug_record_line_number (cfg, ins, offset);
2529 switch (ins->opcode) {
2531 x86_mul_reg (code, ins->sreg2, TRUE);
2534 x86_mul_reg (code, ins->sreg2, FALSE);
2536 case OP_X86_SETEQ_MEMBASE:
2537 case OP_X86_SETNE_MEMBASE:
2538 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2539 ins->inst_basereg, ins->inst_offset, TRUE);
2541 case OP_STOREI1_MEMBASE_IMM:
2542 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2544 case OP_STOREI2_MEMBASE_IMM:
2545 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2547 case OP_STORE_MEMBASE_IMM:
2548 case OP_STOREI4_MEMBASE_IMM:
2549 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2551 case OP_STOREI1_MEMBASE_REG:
2552 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2554 case OP_STOREI2_MEMBASE_REG:
2555 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2557 case OP_STORE_MEMBASE_REG:
2558 case OP_STOREI4_MEMBASE_REG:
2559 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2561 case OP_STORE_MEM_IMM:
2562 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2565 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2569 /* These are created by the cprop pass so they use inst_imm as the source */
2570 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2573 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2576 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2578 case OP_LOAD_MEMBASE:
2579 case OP_LOADI4_MEMBASE:
2580 case OP_LOADU4_MEMBASE:
2581 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2583 case OP_LOADU1_MEMBASE:
2584 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2586 case OP_LOADI1_MEMBASE:
2587 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2589 case OP_LOADU2_MEMBASE:
2590 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2592 case OP_LOADI2_MEMBASE:
2593 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2595 case OP_ICONV_TO_I1:
2597 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2599 case OP_ICONV_TO_I2:
2601 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2603 case OP_ICONV_TO_U1:
2604 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2606 case OP_ICONV_TO_U2:
2607 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2611 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2613 case OP_COMPARE_IMM:
2614 case OP_ICOMPARE_IMM:
2615 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2617 case OP_X86_COMPARE_MEMBASE_REG:
2618 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2620 case OP_X86_COMPARE_MEMBASE_IMM:
2621 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2623 case OP_X86_COMPARE_MEMBASE8_IMM:
2624 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2626 case OP_X86_COMPARE_REG_MEMBASE:
2627 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2629 case OP_X86_COMPARE_MEM_IMM:
2630 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2632 case OP_X86_TEST_NULL:
2633 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2635 case OP_X86_ADD_MEMBASE_IMM:
2636 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2638 case OP_X86_ADD_REG_MEMBASE:
2639 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2641 case OP_X86_SUB_MEMBASE_IMM:
2642 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2644 case OP_X86_SUB_REG_MEMBASE:
2645 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2647 case OP_X86_AND_MEMBASE_IMM:
2648 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2650 case OP_X86_OR_MEMBASE_IMM:
2651 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2653 case OP_X86_XOR_MEMBASE_IMM:
2654 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2656 case OP_X86_ADD_MEMBASE_REG:
2657 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2659 case OP_X86_SUB_MEMBASE_REG:
2660 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2662 case OP_X86_AND_MEMBASE_REG:
2663 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2665 case OP_X86_OR_MEMBASE_REG:
2666 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2668 case OP_X86_XOR_MEMBASE_REG:
2669 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2671 case OP_X86_INC_MEMBASE:
2672 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2674 case OP_X86_INC_REG:
2675 x86_inc_reg (code, ins->dreg);
2677 case OP_X86_DEC_MEMBASE:
2678 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2680 case OP_X86_DEC_REG:
2681 x86_dec_reg (code, ins->dreg);
2683 case OP_X86_MUL_REG_MEMBASE:
2684 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2686 case OP_X86_AND_REG_MEMBASE:
2687 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2689 case OP_X86_OR_REG_MEMBASE:
2690 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2692 case OP_X86_XOR_REG_MEMBASE:
2693 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2696 x86_breakpoint (code);
2698 case OP_RELAXED_NOP:
2699 x86_prefix (code, X86_REP_PREFIX);
2707 case OP_DUMMY_STORE:
2708 case OP_NOT_REACHED:
2711 case OP_SEQ_POINT: {
2714 if (cfg->compile_aot)
2718 * Read from the single stepping trigger page. This will cause a
2719 * SIGSEGV when single stepping is enabled.
2720 * We do this _before_ the breakpoint, so single stepping after
2721 * a breakpoint is hit will step to the next IL offset.
2723 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2724 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2726 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2729 * A placeholder for a possible breakpoint inserted by
2730 * mono_arch_set_breakpoint ().
2732 for (i = 0; i < 6; ++i)
2735 * Add an additional nop so skipping the bp doesn't cause the ip to point
2736 * to another IL offset.
2744 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2748 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2753 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2757 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2762 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2766 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2771 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2775 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2778 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2782 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2787 * The code is the same for div/rem, the allocator will allocate dreg
2788 * to RAX/RDX as appropriate.
2790 if (ins->sreg2 == X86_EDX) {
2791 /* cdq clobbers this */
2792 x86_push_reg (code, ins->sreg2);
2794 x86_div_membase (code, X86_ESP, 0, TRUE);
2795 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2798 x86_div_reg (code, ins->sreg2, TRUE);
2803 if (ins->sreg2 == X86_EDX) {
2804 x86_push_reg (code, ins->sreg2);
2805 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2806 x86_div_membase (code, X86_ESP, 0, FALSE);
2807 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2809 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2810 x86_div_reg (code, ins->sreg2, FALSE);
2814 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2816 x86_div_reg (code, ins->sreg2, TRUE);
2819 int power = mono_is_power_of_two (ins->inst_imm);
2821 g_assert (ins->sreg1 == X86_EAX);
2822 g_assert (ins->dreg == X86_EAX);
2823 g_assert (power >= 0);
2826 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2828 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2830 * If the divident is >= 0, this does not nothing. If it is positive, it
2831 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2833 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2834 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2835 } else if (power == 0) {
2836 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2838 /* Based on gcc code */
2840 /* Add compensation for negative dividents */
2842 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2843 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2844 /* Compute remainder */
2845 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2846 /* Remove compensation */
2847 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2852 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2856 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2859 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2863 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2866 g_assert (ins->sreg2 == X86_ECX);
2867 x86_shift_reg (code, X86_SHL, ins->dreg);
2870 g_assert (ins->sreg2 == X86_ECX);
2871 x86_shift_reg (code, X86_SAR, ins->dreg);
2875 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2878 case OP_ISHR_UN_IMM:
2879 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2882 g_assert (ins->sreg2 == X86_ECX);
2883 x86_shift_reg (code, X86_SHR, ins->dreg);
2887 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2890 guint8 *jump_to_end;
2892 /* handle shifts below 32 bits */
2893 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2894 x86_shift_reg (code, X86_SHL, ins->sreg1);
2896 x86_test_reg_imm (code, X86_ECX, 32);
2897 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2899 /* handle shift over 32 bit */
2900 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2901 x86_clear_reg (code, ins->sreg1);
2903 x86_patch (jump_to_end, code);
2907 guint8 *jump_to_end;
2909 /* handle shifts below 32 bits */
2910 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2911 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2913 x86_test_reg_imm (code, X86_ECX, 32);
2914 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2916 /* handle shifts over 31 bits */
2917 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2918 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2920 x86_patch (jump_to_end, code);
2924 guint8 *jump_to_end;
2926 /* handle shifts below 32 bits */
2927 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2928 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2930 x86_test_reg_imm (code, X86_ECX, 32);
2931 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2933 /* handle shifts over 31 bits */
2934 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2935 x86_clear_reg (code, ins->backend.reg3);
2937 x86_patch (jump_to_end, code);
2941 if (ins->inst_imm >= 32) {
2942 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2943 x86_clear_reg (code, ins->sreg1);
2944 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2946 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2947 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2951 if (ins->inst_imm >= 32) {
2952 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2953 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2954 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2956 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2957 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2960 case OP_LSHR_UN_IMM:
2961 if (ins->inst_imm >= 32) {
2962 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2963 x86_clear_reg (code, ins->backend.reg3);
2964 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2966 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2967 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2971 x86_not_reg (code, ins->sreg1);
2974 x86_neg_reg (code, ins->sreg1);
2978 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2982 switch (ins->inst_imm) {
2986 if (ins->dreg != ins->sreg1)
2987 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2988 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2991 /* LEA r1, [r2 + r2*2] */
2992 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2995 /* LEA r1, [r2 + r2*4] */
2996 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2999 /* LEA r1, [r2 + r2*2] */
3001 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3002 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3005 /* LEA r1, [r2 + r2*8] */
3006 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3009 /* LEA r1, [r2 + r2*4] */
3011 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3012 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3015 /* LEA r1, [r2 + r2*2] */
3017 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3018 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3021 /* LEA r1, [r2 + r2*4] */
3022 /* LEA r1, [r1 + r1*4] */
3023 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3024 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3027 /* LEA r1, [r2 + r2*4] */
3029 /* LEA r1, [r1 + r1*4] */
3030 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3031 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3032 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3035 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3040 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3041 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3043 case OP_IMUL_OVF_UN: {
3044 /* the mul operation and the exception check should most likely be split */
3045 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3046 /*g_assert (ins->sreg2 == X86_EAX);
3047 g_assert (ins->dreg == X86_EAX);*/
3048 if (ins->sreg2 == X86_EAX) {
3049 non_eax_reg = ins->sreg1;
3050 } else if (ins->sreg1 == X86_EAX) {
3051 non_eax_reg = ins->sreg2;
3053 /* no need to save since we're going to store to it anyway */
3054 if (ins->dreg != X86_EAX) {
3056 x86_push_reg (code, X86_EAX);
3058 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3059 non_eax_reg = ins->sreg2;
3061 if (ins->dreg == X86_EDX) {
3064 x86_push_reg (code, X86_EAX);
3066 } else if (ins->dreg != X86_EAX) {
3068 x86_push_reg (code, X86_EDX);
3070 x86_mul_reg (code, non_eax_reg, FALSE);
3071 /* save before the check since pop and mov don't change the flags */
3072 if (ins->dreg != X86_EAX)
3073 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3075 x86_pop_reg (code, X86_EDX);
3077 x86_pop_reg (code, X86_EAX);
3078 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3082 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3085 g_assert_not_reached ();
3086 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3087 x86_mov_reg_imm (code, ins->dreg, 0);
3090 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3091 x86_mov_reg_imm (code, ins->dreg, 0);
3093 case OP_LOAD_GOTADDR:
3094 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3095 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3098 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3099 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3101 case OP_X86_PUSH_GOT_ENTRY:
3102 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3103 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3106 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3110 * Note: this 'frame destruction' logic is useful for tail calls, too.
3111 * Keep in sync with the code in emit_epilog.
3115 /* FIXME: no tracing support... */
3116 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3117 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3118 /* reset offset to make max_len work */
3119 offset = code - cfg->native_code;
3121 g_assert (!cfg->method->save_lmf);
3123 code = emit_load_volatile_arguments (cfg, code);
3125 if (cfg->used_int_regs & (1 << X86_EBX))
3127 if (cfg->used_int_regs & (1 << X86_EDI))
3129 if (cfg->used_int_regs & (1 << X86_ESI))
3132 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
3134 if (cfg->used_int_regs & (1 << X86_ESI))
3135 x86_pop_reg (code, X86_ESI);
3136 if (cfg->used_int_regs & (1 << X86_EDI))
3137 x86_pop_reg (code, X86_EDI);
3138 if (cfg->used_int_regs & (1 << X86_EBX))
3139 x86_pop_reg (code, X86_EBX);
3141 /* restore ESP/EBP */
3143 offset = code - cfg->native_code;
3144 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3145 x86_jump32 (code, 0);
3147 cfg->disable_aot = TRUE;
3151 MonoCallInst *call = (MonoCallInst*)ins;
3154 ins->flags |= MONO_INST_GC_CALLSITE;
3155 ins->backend.pc_offset = code - cfg->native_code;
3157 /* FIXME: no tracing support... */
3158 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3159 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3160 /* reset offset to make max_len work */
3161 offset = code - cfg->native_code;
3163 g_assert (!cfg->method->save_lmf);
3165 //code = emit_load_volatile_arguments (cfg, code);
3167 /* restore callee saved registers */
3168 for (i = 0; i < X86_NREG; ++i)
3169 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3171 if (cfg->used_int_regs & (1 << X86_ESI)) {
3172 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3175 if (cfg->used_int_regs & (1 << X86_EDI)) {
3176 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3179 if (cfg->used_int_regs & (1 << X86_EBX)) {
3180 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3184 /* Copy arguments on the stack to our argument area */
3185 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3186 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3187 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3190 /* restore ESP/EBP */
3192 offset = code - cfg->native_code;
3193 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3194 x86_jump32 (code, 0);
3196 ins->flags |= MONO_INST_GC_CALLSITE;
3197 cfg->disable_aot = TRUE;
3201 /* ensure ins->sreg1 is not NULL
3202 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3203 * cmp DWORD PTR [eax], 0
3205 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3208 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3209 x86_push_reg (code, hreg);
3210 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3211 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3212 x86_pop_reg (code, hreg);
3221 call = (MonoCallInst*)ins;
3222 if (ins->flags & MONO_INST_HAS_METHOD)
3223 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3225 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3226 ins->flags |= MONO_INST_GC_CALLSITE;
3227 ins->backend.pc_offset = code - cfg->native_code;
3228 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3229 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
3230 * bytes to pop, we want to use pops. GCC does this (note it won't happen
3231 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
3232 * smart enough to do that optimization yet
3234 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
3235 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
3236 * (most likely from locality benefits). People with other processors should
3237 * check on theirs to see what happens.
3239 if (call->stack_usage == 4) {
3240 /* we want to use registers that won't get used soon, so use
3241 * ecx, as eax will get allocated first. edx is used by long calls,
3242 * so we can't use that.
3245 x86_pop_reg (code, X86_ECX);
3247 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3250 code = emit_move_return_value (cfg, ins, code);
3256 case OP_VOIDCALL_REG:
3258 call = (MonoCallInst*)ins;
3259 x86_call_reg (code, ins->sreg1);
3260 ins->flags |= MONO_INST_GC_CALLSITE;
3261 ins->backend.pc_offset = code - cfg->native_code;
3262 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3263 if (call->stack_usage == 4)
3264 x86_pop_reg (code, X86_ECX);
3266 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3268 code = emit_move_return_value (cfg, ins, code);
3270 case OP_FCALL_MEMBASE:
3271 case OP_LCALL_MEMBASE:
3272 case OP_VCALL_MEMBASE:
3273 case OP_VCALL2_MEMBASE:
3274 case OP_VOIDCALL_MEMBASE:
3275 case OP_CALL_MEMBASE:
3276 call = (MonoCallInst*)ins;
3278 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3279 ins->flags |= MONO_INST_GC_CALLSITE;
3280 ins->backend.pc_offset = code - cfg->native_code;
3281 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3282 if (call->stack_usage == 4)
3283 x86_pop_reg (code, X86_ECX);
3285 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3287 code = emit_move_return_value (cfg, ins, code);
3290 x86_push_reg (code, ins->sreg1);
3292 case OP_X86_PUSH_IMM:
3293 x86_push_imm (code, ins->inst_imm);
3295 case OP_X86_PUSH_MEMBASE:
3296 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
3298 case OP_X86_PUSH_OBJ:
3299 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
3300 x86_push_reg (code, X86_EDI);
3301 x86_push_reg (code, X86_ESI);
3302 x86_push_reg (code, X86_ECX);
3303 if (ins->inst_offset)
3304 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
3306 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
3307 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
3308 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
3310 x86_prefix (code, X86_REP_PREFIX);
3312 x86_pop_reg (code, X86_ECX);
3313 x86_pop_reg (code, X86_ESI);
3314 x86_pop_reg (code, X86_EDI);
3317 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3319 case OP_X86_LEA_MEMBASE:
3320 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3323 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3326 /* keep alignment */
3327 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3328 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3329 code = mono_emit_stack_alloc (code, ins);
3330 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3332 case OP_LOCALLOC_IMM: {
3333 guint32 size = ins->inst_imm;
3334 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3336 if (ins->flags & MONO_INST_INIT) {
3337 /* FIXME: Optimize this */
3338 x86_mov_reg_imm (code, ins->dreg, size);
3339 ins->sreg1 = ins->dreg;
3341 code = mono_emit_stack_alloc (code, ins);
3342 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3344 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3345 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3350 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3351 x86_push_reg (code, ins->sreg1);
3352 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3353 (gpointer)"mono_arch_throw_exception");
3354 ins->flags |= MONO_INST_GC_CALLSITE;
3355 ins->backend.pc_offset = code - cfg->native_code;
3359 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3360 x86_push_reg (code, ins->sreg1);
3361 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3362 (gpointer)"mono_arch_rethrow_exception");
3363 ins->flags |= MONO_INST_GC_CALLSITE;
3364 ins->backend.pc_offset = code - cfg->native_code;
3367 case OP_CALL_HANDLER:
3368 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3369 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3370 x86_call_imm (code, 0);
3371 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3372 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3374 case OP_START_HANDLER: {
3375 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3376 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3379 case OP_ENDFINALLY: {
3380 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3381 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3385 case OP_ENDFILTER: {
3386 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3387 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3388 /* The local allocator will put the result into EAX */
3394 ins->inst_c0 = code - cfg->native_code;
3397 if (ins->inst_target_bb->native_offset) {
3398 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3400 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3401 if ((cfg->opt & MONO_OPT_BRANCH) &&
3402 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3403 x86_jump8 (code, 0);
3405 x86_jump32 (code, 0);
3409 x86_jump_reg (code, ins->sreg1);
3422 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3423 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3425 case OP_COND_EXC_EQ:
3426 case OP_COND_EXC_NE_UN:
3427 case OP_COND_EXC_LT:
3428 case OP_COND_EXC_LT_UN:
3429 case OP_COND_EXC_GT:
3430 case OP_COND_EXC_GT_UN:
3431 case OP_COND_EXC_GE:
3432 case OP_COND_EXC_GE_UN:
3433 case OP_COND_EXC_LE:
3434 case OP_COND_EXC_LE_UN:
3435 case OP_COND_EXC_IEQ:
3436 case OP_COND_EXC_INE_UN:
3437 case OP_COND_EXC_ILT:
3438 case OP_COND_EXC_ILT_UN:
3439 case OP_COND_EXC_IGT:
3440 case OP_COND_EXC_IGT_UN:
3441 case OP_COND_EXC_IGE:
3442 case OP_COND_EXC_IGE_UN:
3443 case OP_COND_EXC_ILE:
3444 case OP_COND_EXC_ILE_UN:
3445 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3447 case OP_COND_EXC_OV:
3448 case OP_COND_EXC_NO:
3450 case OP_COND_EXC_NC:
3451 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3453 case OP_COND_EXC_IOV:
3454 case OP_COND_EXC_INO:
3455 case OP_COND_EXC_IC:
3456 case OP_COND_EXC_INC:
3457 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3469 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3477 case OP_CMOV_INE_UN:
3478 case OP_CMOV_IGE_UN:
3479 case OP_CMOV_IGT_UN:
3480 case OP_CMOV_ILE_UN:
3481 case OP_CMOV_ILT_UN:
3482 g_assert (ins->dreg == ins->sreg1);
3483 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3486 /* floating point opcodes */
3488 double d = *(double *)ins->inst_p0;
3490 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3492 } else if (d == 1.0) {
3495 if (cfg->compile_aot) {
3496 guint32 *val = (guint32*)&d;
3497 x86_push_imm (code, val [1]);
3498 x86_push_imm (code, val [0]);
3499 x86_fld_membase (code, X86_ESP, 0, TRUE);
3500 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3503 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3504 x86_fld (code, NULL, TRUE);
3510 float f = *(float *)ins->inst_p0;
3512 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3514 } else if (f == 1.0) {
3517 if (cfg->compile_aot) {
3518 guint32 val = *(guint32*)&f;
3519 x86_push_imm (code, val);
3520 x86_fld_membase (code, X86_ESP, 0, FALSE);
3521 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3524 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3525 x86_fld (code, NULL, FALSE);
3530 case OP_STORER8_MEMBASE_REG:
3531 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3533 case OP_LOADR8_MEMBASE:
3534 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3536 case OP_STORER4_MEMBASE_REG:
3537 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3539 case OP_LOADR4_MEMBASE:
3540 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3542 case OP_ICONV_TO_R4:
3543 x86_push_reg (code, ins->sreg1);
3544 x86_fild_membase (code, X86_ESP, 0, FALSE);
3545 /* Change precision */
3546 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3547 x86_fld_membase (code, X86_ESP, 0, FALSE);
3548 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3550 case OP_ICONV_TO_R8:
3551 x86_push_reg (code, ins->sreg1);
3552 x86_fild_membase (code, X86_ESP, 0, FALSE);
3553 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3555 case OP_ICONV_TO_R_UN:
3556 x86_push_imm (code, 0);
3557 x86_push_reg (code, ins->sreg1);
3558 x86_fild_membase (code, X86_ESP, 0, TRUE);
3559 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3561 case OP_X86_FP_LOAD_I8:
3562 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3564 case OP_X86_FP_LOAD_I4:
3565 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3567 case OP_FCONV_TO_R4:
3568 /* Change precision */
3569 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3570 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3571 x86_fld_membase (code, X86_ESP, 0, FALSE);
3572 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3574 case OP_FCONV_TO_I1:
3575 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3577 case OP_FCONV_TO_U1:
3578 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3580 case OP_FCONV_TO_I2:
3581 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3583 case OP_FCONV_TO_U2:
3584 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3586 case OP_FCONV_TO_I4:
3588 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3590 case OP_FCONV_TO_I8:
3591 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3592 x86_fnstcw_membase(code, X86_ESP, 0);
3593 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3594 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3595 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3596 x86_fldcw_membase (code, X86_ESP, 2);
3597 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3598 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3599 x86_pop_reg (code, ins->dreg);
3600 x86_pop_reg (code, ins->backend.reg3);
3601 x86_fldcw_membase (code, X86_ESP, 0);
3602 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3604 case OP_LCONV_TO_R8_2:
3605 x86_push_reg (code, ins->sreg2);
3606 x86_push_reg (code, ins->sreg1);
3607 x86_fild_membase (code, X86_ESP, 0, TRUE);
3608 /* Change precision */
3609 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3610 x86_fld_membase (code, X86_ESP, 0, TRUE);
3611 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3613 case OP_LCONV_TO_R4_2:
3614 x86_push_reg (code, ins->sreg2);
3615 x86_push_reg (code, ins->sreg1);
3616 x86_fild_membase (code, X86_ESP, 0, TRUE);
3617 /* Change precision */
3618 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3619 x86_fld_membase (code, X86_ESP, 0, FALSE);
3620 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3622 case OP_LCONV_TO_R_UN_2: {
3623 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3626 /* load 64bit integer to FP stack */
3627 x86_push_reg (code, ins->sreg2);
3628 x86_push_reg (code, ins->sreg1);
3629 x86_fild_membase (code, X86_ESP, 0, TRUE);
3631 /* test if lreg is negative */
3632 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3633 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3635 /* add correction constant mn */
3636 if (cfg->compile_aot) {
3637 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3638 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3639 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3640 x86_fld80_membase (code, X86_ESP, 2);
3641 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3643 x86_fld80_mem (code, mn);
3645 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3647 x86_patch (br, code);
3649 /* Change precision */
3650 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3651 x86_fld_membase (code, X86_ESP, 0, TRUE);
3653 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3657 case OP_LCONV_TO_OVF_I:
3658 case OP_LCONV_TO_OVF_I4_2: {
3659 guint8 *br [3], *label [1];
3663 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3665 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3667 /* If the low word top bit is set, see if we are negative */
3668 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3669 /* We are not negative (no top bit set, check for our top word to be zero */
3670 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3671 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3674 /* throw exception */
3675 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3677 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3678 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3679 x86_jump8 (code, 0);
3681 x86_jump32 (code, 0);
3683 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3684 x86_jump32 (code, 0);
3688 x86_patch (br [0], code);
3689 /* our top bit is set, check that top word is 0xfffffff */
3690 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3692 x86_patch (br [1], code);
3693 /* nope, emit exception */
3694 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3695 x86_patch (br [2], label [0]);
3697 if (ins->dreg != ins->sreg1)
3698 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3702 /* Not needed on the fp stack */
3705 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3708 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3711 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3714 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3722 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3727 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3734 * it really doesn't make sense to inline all this code,
3735 * it's here just to show that things may not be as simple
3738 guchar *check_pos, *end_tan, *pop_jump;
3739 x86_push_reg (code, X86_EAX);
3742 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3744 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3745 x86_fstp (code, 0); /* pop the 1.0 */
3747 x86_jump8 (code, 0);
3749 x86_fp_op (code, X86_FADD, 0);
3753 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3755 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3758 x86_patch (pop_jump, code);
3759 x86_fstp (code, 0); /* pop the 1.0 */
3760 x86_patch (check_pos, code);
3761 x86_patch (end_tan, code);
3763 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3764 x86_pop_reg (code, X86_EAX);
3771 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3780 g_assert (cfg->opt & MONO_OPT_CMOV);
3781 g_assert (ins->dreg == ins->sreg1);
3782 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3783 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3786 g_assert (cfg->opt & MONO_OPT_CMOV);
3787 g_assert (ins->dreg == ins->sreg1);
3788 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3789 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3792 g_assert (cfg->opt & MONO_OPT_CMOV);
3793 g_assert (ins->dreg == ins->sreg1);
3794 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3795 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3798 g_assert (cfg->opt & MONO_OPT_CMOV);
3799 g_assert (ins->dreg == ins->sreg1);
3800 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3801 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3807 x86_fxch (code, ins->inst_imm);
3812 x86_push_reg (code, X86_EAX);
3813 /* we need to exchange ST(0) with ST(1) */
3816 /* this requires a loop, because fprem somtimes
3817 * returns a partial remainder */
3819 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3820 /* x86_fprem1 (code); */
3823 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3825 x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3830 x86_pop_reg (code, X86_EAX);
3834 if (cfg->opt & MONO_OPT_FCMOV) {
3835 x86_fcomip (code, 1);
3839 /* this overwrites EAX */
3840 EMIT_FPCOMPARE(code);
3841 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3844 if (cfg->opt & MONO_OPT_FCMOV) {
3845 /* zeroing the register at the start results in
3846 * shorter and faster code (we can also remove the widening op)
3848 guchar *unordered_check;
3849 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3850 x86_fcomip (code, 1);
3852 unordered_check = code;
3853 x86_branch8 (code, X86_CC_P, 0, FALSE);
3854 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3855 x86_patch (unordered_check, code);
3858 if (ins->dreg != X86_EAX)
3859 x86_push_reg (code, X86_EAX);
3861 EMIT_FPCOMPARE(code);
3862 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3863 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3864 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3865 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3867 if (ins->dreg != X86_EAX)
3868 x86_pop_reg (code, X86_EAX);
3872 if (cfg->opt & MONO_OPT_FCMOV) {
3873 /* zeroing the register at the start results in
3874 * shorter and faster code (we can also remove the widening op)
3876 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3877 x86_fcomip (code, 1);
3879 if (ins->opcode == OP_FCLT_UN) {
3880 guchar *unordered_check = code;
3881 guchar *jump_to_end;
3882 x86_branch8 (code, X86_CC_P, 0, FALSE);
3883 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3885 x86_jump8 (code, 0);
3886 x86_patch (unordered_check, code);
3887 x86_inc_reg (code, ins->dreg);
3888 x86_patch (jump_to_end, code);
3890 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3894 if (ins->dreg != X86_EAX)
3895 x86_push_reg (code, X86_EAX);
3897 EMIT_FPCOMPARE(code);
3898 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3899 if (ins->opcode == OP_FCLT_UN) {
3900 guchar *is_not_zero_check, *end_jump;
3901 is_not_zero_check = code;
3902 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3904 x86_jump8 (code, 0);
3905 x86_patch (is_not_zero_check, code);
3906 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3908 x86_patch (end_jump, code);
3910 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3911 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3913 if (ins->dreg != X86_EAX)
3914 x86_pop_reg (code, X86_EAX);
3918 if (cfg->opt & MONO_OPT_FCMOV) {
3919 /* zeroing the register at the start results in
3920 * shorter and faster code (we can also remove the widening op)
3922 guchar *unordered_check;
3923 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3924 x86_fcomip (code, 1);
3926 if (ins->opcode == OP_FCGT) {
3927 unordered_check = code;
3928 x86_branch8 (code, X86_CC_P, 0, FALSE);
3929 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3930 x86_patch (unordered_check, code);
3932 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3936 if (ins->dreg != X86_EAX)
3937 x86_push_reg (code, X86_EAX);
3939 EMIT_FPCOMPARE(code);
3940 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3941 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3942 if (ins->opcode == OP_FCGT_UN) {
3943 guchar *is_not_zero_check, *end_jump;
3944 is_not_zero_check = code;
3945 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3947 x86_jump8 (code, 0);
3948 x86_patch (is_not_zero_check, code);
3949 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3951 x86_patch (end_jump, code);
3953 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3954 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3956 if (ins->dreg != X86_EAX)
3957 x86_pop_reg (code, X86_EAX);
3960 if (cfg->opt & MONO_OPT_FCMOV) {
3961 guchar *jump = code;
3962 x86_branch8 (code, X86_CC_P, 0, TRUE);
3963 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3964 x86_patch (jump, code);
3967 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3968 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3971 /* Branch if C013 != 100 */
3972 if (cfg->opt & MONO_OPT_FCMOV) {
3973 /* branch if !ZF or (PF|CF) */
3974 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3975 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3976 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3979 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3980 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3983 if (cfg->opt & MONO_OPT_FCMOV) {
3984 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3987 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3990 if (cfg->opt & MONO_OPT_FCMOV) {
3991 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3992 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3995 if (ins->opcode == OP_FBLT_UN) {
3996 guchar *is_not_zero_check, *end_jump;
3997 is_not_zero_check = code;
3998 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4000 x86_jump8 (code, 0);
4001 x86_patch (is_not_zero_check, code);
4002 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4004 x86_patch (end_jump, code);
4006 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4010 if (cfg->opt & MONO_OPT_FCMOV) {
4011 if (ins->opcode == OP_FBGT) {
4014 /* skip branch if C1=1 */
4016 x86_branch8 (code, X86_CC_P, 0, FALSE);
4017 /* branch if (C0 | C3) = 1 */
4018 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4019 x86_patch (br1, code);
4021 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4025 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4026 if (ins->opcode == OP_FBGT_UN) {
4027 guchar *is_not_zero_check, *end_jump;
4028 is_not_zero_check = code;
4029 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4031 x86_jump8 (code, 0);
4032 x86_patch (is_not_zero_check, code);
4033 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4035 x86_patch (end_jump, code);
4037 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4040 /* Branch if C013 == 100 or 001 */
4041 if (cfg->opt & MONO_OPT_FCMOV) {
4044 /* skip branch if C1=1 */
4046 x86_branch8 (code, X86_CC_P, 0, FALSE);
4047 /* branch if (C0 | C3) = 1 */
4048 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4049 x86_patch (br1, code);
4052 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4053 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4054 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4055 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4058 /* Branch if C013 == 000 */
4059 if (cfg->opt & MONO_OPT_FCMOV) {
4060 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4063 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4066 /* Branch if C013=000 or 100 */
4067 if (cfg->opt & MONO_OPT_FCMOV) {
4070 /* skip branch if C1=1 */
4072 x86_branch8 (code, X86_CC_P, 0, FALSE);
4073 /* branch if C0=0 */
4074 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4075 x86_patch (br1, code);
4078 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4079 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4080 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4083 /* Branch if C013 != 001 */
4084 if (cfg->opt & MONO_OPT_FCMOV) {
4085 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4086 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4089 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4090 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4094 x86_push_reg (code, X86_EAX);
4097 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4098 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4099 x86_pop_reg (code, X86_EAX);
4101 /* Have to clean up the fp stack before throwing the exception */
4103 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4106 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4108 x86_patch (br1, code);
4112 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4115 case OP_MEMORY_BARRIER: {
4116 /* x86 only needs barrier for StoreLoad and FullBarrier */
4117 switch (ins->backend.memory_barrier_kind) {
4118 case StoreLoadBarrier:
4120 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4121 x86_prefix (code, X86_LOCK_PREFIX);
4122 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4127 case OP_ATOMIC_ADD_I4: {
4128 int dreg = ins->dreg;
4130 if (dreg == ins->inst_basereg) {
4131 x86_push_reg (code, ins->sreg2);
4135 if (dreg != ins->sreg2)
4136 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
4138 x86_prefix (code, X86_LOCK_PREFIX);
4139 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4141 if (dreg != ins->dreg) {
4142 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4143 x86_pop_reg (code, dreg);
4148 case OP_ATOMIC_ADD_NEW_I4: {
4149 int dreg = ins->dreg;
4151 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4152 if (ins->sreg2 == dreg) {
4153 if (dreg == X86_EBX) {
4155 if (ins->inst_basereg == X86_EDI)
4159 if (ins->inst_basereg == X86_EBX)
4162 } else if (ins->inst_basereg == dreg) {
4163 if (dreg == X86_EBX) {
4165 if (ins->sreg2 == X86_EDI)
4169 if (ins->sreg2 == X86_EBX)
4174 if (dreg != ins->dreg) {
4175 x86_push_reg (code, dreg);
4178 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4179 x86_prefix (code, X86_LOCK_PREFIX);
4180 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4181 /* dreg contains the old value, add with sreg2 value */
4182 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4184 if (ins->dreg != dreg) {
4185 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4186 x86_pop_reg (code, dreg);
4191 case OP_ATOMIC_EXCHANGE_I4: {
4193 int sreg2 = ins->sreg2;
4194 int breg = ins->inst_basereg;
4196 /* cmpxchg uses eax as comperand, need to make sure we can use it
4197 * hack to overcome limits in x86 reg allocator
4198 * (req: dreg == eax and sreg2 != eax and breg != eax)
4200 g_assert (ins->dreg == X86_EAX);
4202 /* We need the EAX reg for the cmpxchg */
4203 if (ins->sreg2 == X86_EAX) {
4204 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4205 x86_push_reg (code, sreg2);
4206 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4209 if (breg == X86_EAX) {
4210 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4211 x86_push_reg (code, breg);
4212 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4215 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4217 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4218 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4219 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4220 x86_patch (br [1], br [0]);
4222 if (breg != ins->inst_basereg)
4223 x86_pop_reg (code, breg);
4225 if (ins->sreg2 != sreg2)
4226 x86_pop_reg (code, sreg2);
4230 case OP_ATOMIC_CAS_I4: {
4231 g_assert (ins->dreg == X86_EAX);
4232 g_assert (ins->sreg3 == X86_EAX);
4233 g_assert (ins->sreg1 != X86_EAX);
4234 g_assert (ins->sreg1 != ins->sreg2);
4236 x86_prefix (code, X86_LOCK_PREFIX);
4237 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4240 case OP_CARD_TABLE_WBARRIER: {
4241 int ptr = ins->sreg1;
4242 int value = ins->sreg2;
4244 int nursery_shift, card_table_shift;
4245 gpointer card_table_mask;
4246 size_t nursery_size;
4247 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4248 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4249 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4252 * We need one register we can clobber, we choose EDX and make sreg1
4253 * fixed EAX to work around limitations in the local register allocator.
4254 * sreg2 might get allocated to EDX, but that is not a problem since
4255 * we use it before clobbering EDX.
4257 g_assert (ins->sreg1 == X86_EAX);
4260 * This is the code we produce:
4263 * edx >>= nursery_shift
4264 * cmp edx, (nursery_start >> nursery_shift)
4267 * edx >>= card_table_shift
4268 * card_table[edx] = 1
4272 if (card_table_nursery_check) {
4273 if (value != X86_EDX)
4274 x86_mov_reg_reg (code, X86_EDX, value, 4);
4275 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4276 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4277 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4279 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4280 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4281 if (card_table_mask)
4282 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4283 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4284 if (card_table_nursery_check)
4285 x86_patch (br, code);
4288 #ifdef MONO_ARCH_SIMD_INTRINSICS
4290 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4293 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4296 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4299 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4302 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4305 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4308 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4309 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4312 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4315 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4318 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4321 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4324 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4327 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4330 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4333 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4336 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4339 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4342 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4345 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4348 case OP_PSHUFLEW_HIGH:
4349 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4350 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4352 case OP_PSHUFLEW_LOW:
4353 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4354 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4357 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4358 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4361 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4362 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4365 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4366 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4370 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4373 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4376 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4379 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4382 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4385 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4388 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4389 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4392 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4395 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4398 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4401 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4404 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4407 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4410 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4413 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4416 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4419 case OP_EXTRACT_MASK:
4420 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4424 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4427 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4430 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4434 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4437 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4440 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4443 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4447 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4450 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4453 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4456 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4460 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4463 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4466 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4470 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4473 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4476 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4480 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4483 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4487 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4490 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4493 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4497 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4500 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4503 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4507 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4510 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4513 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4516 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4520 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4523 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4526 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4529 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4532 case OP_PSUM_ABS_DIFF:
4533 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4536 case OP_UNPACK_LOWB:
4537 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4539 case OP_UNPACK_LOWW:
4540 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4542 case OP_UNPACK_LOWD:
4543 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4545 case OP_UNPACK_LOWQ:
4546 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4548 case OP_UNPACK_LOWPS:
4549 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4551 case OP_UNPACK_LOWPD:
4552 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4555 case OP_UNPACK_HIGHB:
4556 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4558 case OP_UNPACK_HIGHW:
4559 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4561 case OP_UNPACK_HIGHD:
4562 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4564 case OP_UNPACK_HIGHQ:
4565 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4567 case OP_UNPACK_HIGHPS:
4568 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4570 case OP_UNPACK_HIGHPD:
4571 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4575 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4578 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4581 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4584 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4587 case OP_PADDB_SAT_UN:
4588 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4590 case OP_PSUBB_SAT_UN:
4591 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4593 case OP_PADDW_SAT_UN:
4594 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4596 case OP_PSUBW_SAT_UN:
4597 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4601 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4604 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4607 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4610 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4614 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4617 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4620 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4622 case OP_PMULW_HIGH_UN:
4623 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4626 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4630 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4633 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4637 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4640 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4644 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4647 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4651 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4654 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4658 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4661 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4665 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4668 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4672 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4675 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4679 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4682 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4686 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4689 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4693 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4695 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4696 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4700 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4702 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4703 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4707 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4709 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4710 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4714 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4716 case OP_EXTRACTX_U2:
4717 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4719 case OP_INSERTX_U1_SLOW:
4720 /*sreg1 is the extracted ireg (scratch)
4721 /sreg2 is the to be inserted ireg (scratch)
4722 /dreg is the xreg to receive the value*/
4724 /*clear the bits from the extracted word*/
4725 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4726 /*shift the value to insert if needed*/
4727 if (ins->inst_c0 & 1)
4728 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4729 /*join them together*/
4730 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4731 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4733 case OP_INSERTX_I4_SLOW:
4734 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4735 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4736 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4739 case OP_INSERTX_R4_SLOW:
4740 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4741 /*TODO if inst_c0 == 0 use movss*/
4742 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4743 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4745 case OP_INSERTX_R8_SLOW:
4746 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4747 if (cfg->verbose_level)
4748 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4750 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4752 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4755 case OP_STOREX_MEMBASE_REG:
4756 case OP_STOREX_MEMBASE:
4757 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4759 case OP_LOADX_MEMBASE:
4760 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4762 case OP_LOADX_ALIGNED_MEMBASE:
4763 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4765 case OP_STOREX_ALIGNED_MEMBASE_REG:
4766 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4768 case OP_STOREX_NTA_MEMBASE_REG:
4769 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4771 case OP_PREFETCH_MEMBASE:
4772 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4776 /*FIXME the peephole pass should have killed this*/
4777 if (ins->dreg != ins->sreg1)
4778 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4781 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4783 case OP_ICONV_TO_R8_RAW:
4784 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4785 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4788 case OP_FCONV_TO_R8_X:
4789 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4790 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4793 case OP_XCONV_R8_TO_I4:
4794 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4795 switch (ins->backend.source_opcode) {
4796 case OP_FCONV_TO_I1:
4797 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4799 case OP_FCONV_TO_U1:
4800 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4802 case OP_FCONV_TO_I2:
4803 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4805 case OP_FCONV_TO_U2:
4806 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4812 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4813 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4814 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4815 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4816 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4817 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4820 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4821 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4822 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4825 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4826 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4829 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4830 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4831 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4834 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4835 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4836 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4840 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4843 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4846 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4849 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4852 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4855 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4858 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4861 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4865 case OP_LIVERANGE_START: {
4866 if (cfg->verbose_level > 1)
4867 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4868 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4871 case OP_LIVERANGE_END: {
4872 if (cfg->verbose_level > 1)
4873 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4874 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4877 case OP_NACL_GC_SAFE_POINT: {
4878 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
4879 if (cfg->compile_aot)
4880 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
4884 x86_test_mem_imm8 (code, (gpointer)&__nacl_thread_suspension_needed, 0xFFFFFFFF);
4885 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4886 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
4887 x86_patch (br[0], code);
4892 case OP_GC_LIVENESS_DEF:
4893 case OP_GC_LIVENESS_USE:
4894 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4895 ins->backend.pc_offset = code - cfg->native_code;
4897 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4898 ins->backend.pc_offset = code - cfg->native_code;
4899 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4902 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4903 g_assert_not_reached ();
4906 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4907 #ifndef __native_client_codegen__
4908 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4909 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4910 g_assert_not_reached ();
4911 #endif /* __native_client_codegen__ */
4917 cfg->code_len = code - cfg->native_code;
4920 #endif /* DISABLE_JIT */
4923 mono_arch_register_lowlevel_calls (void)
4928 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4930 MonoJumpInfo *patch_info;
4931 gboolean compile_aot = !run_cctors;
4933 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4934 unsigned char *ip = patch_info->ip.i + code;
4935 const unsigned char *target;
4937 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4940 switch (patch_info->type) {
4941 case MONO_PATCH_INFO_BB:
4942 case MONO_PATCH_INFO_LABEL:
4945 /* No need to patch these */
4950 switch (patch_info->type) {
4951 case MONO_PATCH_INFO_IP:
4952 *((gconstpointer *)(ip)) = target;
4954 case MONO_PATCH_INFO_CLASS_INIT: {
4956 /* Might already been changed to a nop */
4957 x86_call_code (code, 0);
4958 x86_patch (ip, target);
4961 case MONO_PATCH_INFO_ABS:
4962 case MONO_PATCH_INFO_METHOD:
4963 case MONO_PATCH_INFO_METHOD_JUMP:
4964 case MONO_PATCH_INFO_INTERNAL_METHOD:
4965 case MONO_PATCH_INFO_BB:
4966 case MONO_PATCH_INFO_LABEL:
4967 case MONO_PATCH_INFO_RGCTX_FETCH:
4968 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
4969 case MONO_PATCH_INFO_MONITOR_ENTER:
4970 case MONO_PATCH_INFO_MONITOR_EXIT:
4971 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
4972 #if defined(__native_client_codegen__) && defined(__native_client__)
4973 if (nacl_is_code_address (code)) {
4974 /* For tail calls, code is patched after being installed */
4975 /* but not through the normal "patch callsite" method. */
4976 unsigned char buf[kNaClAlignment];
4977 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
4978 unsigned char *_target = target;
4980 /* All patch targets modified in x86_patch */
4981 /* are IP relative. */
4982 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
4983 memcpy (buf, aligned_code, kNaClAlignment);
4984 /* Patch a temp buffer of bundle size, */
4985 /* then install to actual location. */
4986 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
4987 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
4988 g_assert (ret == 0);
4991 x86_patch (ip, target);
4994 x86_patch (ip, target);
4997 case MONO_PATCH_INFO_NONE:
4999 case MONO_PATCH_INFO_R4:
5000 case MONO_PATCH_INFO_R8: {
5001 guint32 offset = mono_arch_get_patch_offset (ip);
5002 *((gconstpointer *)(ip + offset)) = target;
5006 guint32 offset = mono_arch_get_patch_offset (ip);
5007 #if !defined(__native_client__)
5008 *((gconstpointer *)(ip + offset)) = target;
5010 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5018 static G_GNUC_UNUSED void
5019 stack_unaligned (MonoMethod *m, gpointer caller)
5021 printf ("%s\n", mono_method_full_name (m, TRUE));
5022 g_assert_not_reached ();
5026 mono_arch_emit_prolog (MonoCompile *cfg)
5028 MonoMethod *method = cfg->method;
5030 MonoMethodSignature *sig;
5032 int alloc_size, pos, max_offset, i, cfa_offset;
5034 gboolean need_stack_frame;
5035 #ifdef __native_client_codegen__
5036 guint alignment_check;
5039 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5041 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5042 cfg->code_size += 512;
5044 #if defined(__default_codegen__)
5045 code = cfg->native_code = g_malloc (cfg->code_size);
5046 #elif defined(__native_client_codegen__)
5047 /* native_code_alloc is not 32-byte aligned, native_code is. */
5048 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5050 /* Align native_code to next nearest kNaclAlignment byte. */
5051 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5052 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5054 code = cfg->native_code;
5056 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5057 g_assert(alignment_check == 0);
5064 /* Check that the stack is aligned on osx */
5065 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5066 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5067 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5069 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5070 x86_push_membase (code, X86_ESP, 0);
5071 x86_push_imm (code, cfg->method);
5072 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5073 x86_call_reg (code, X86_EAX);
5074 x86_patch (br [0], code);
5078 /* Offset between RSP and the CFA */
5082 cfa_offset = sizeof (gpointer);
5083 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5084 // IP saved at CFA - 4
5085 /* There is no IP reg on x86 */
5086 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5087 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5089 need_stack_frame = needs_stack_frame (cfg);
5091 if (need_stack_frame) {
5092 x86_push_reg (code, X86_EBP);
5093 cfa_offset += sizeof (gpointer);
5094 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5095 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5096 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5097 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5098 /* These are handled automatically by the stack marking code */
5099 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5101 cfg->frame_reg = X86_ESP;
5104 alloc_size = cfg->stack_offset;
5107 if (method->save_lmf) {
5108 pos += sizeof (MonoLMF);
5110 /* save the current IP */
5111 if (cfg->compile_aot) {
5112 /* This pushes the current ip */
5113 x86_call_imm (code, 0);
5115 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
5116 x86_push_imm_template (code);
5118 cfa_offset += sizeof (gpointer);
5119 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5121 /* save all caller saved regs */
5122 x86_push_reg (code, X86_EBP);
5123 cfa_offset += sizeof (gpointer);
5124 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5125 x86_push_reg (code, X86_ESI);
5126 cfa_offset += sizeof (gpointer);
5127 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5128 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5129 x86_push_reg (code, X86_EDI);
5130 cfa_offset += sizeof (gpointer);
5131 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5132 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5133 x86_push_reg (code, X86_EBX);
5134 cfa_offset += sizeof (gpointer);
5135 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5136 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5138 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5140 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5141 * through the mono_lmf_addr TLS variable.
5143 /* %eax = previous_lmf */
5144 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_tls_offset);
5145 /* skip esp + method_info + lmf */
5146 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 12);
5148 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5149 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + 4, SLOT_NOREF);
5150 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + 8, SLOT_NOREF);
5151 /* push previous_lmf */
5152 x86_push_reg (code, X86_EAX);
5154 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5156 code = mono_x86_emit_tls_set (code, X86_ESP, lmf_tls_offset);
5158 /* get the address of lmf for the current thread */
5160 * This is performance critical so we try to use some tricks to make
5164 if (lmf_addr_tls_offset != -1) {
5165 /* Load lmf quicky using the GS register */
5166 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
5168 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5169 /* FIXME: Add a separate key for LMF to avoid this */
5170 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5173 if (cfg->compile_aot)
5174 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
5175 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
5178 /* Skip esp + method info */
5179 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
5182 x86_push_reg (code, X86_EAX);
5183 /* push *lfm (previous_lmf) */
5184 x86_push_membase (code, X86_EAX, 0);
5186 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
5190 if (cfg->used_int_regs & (1 << X86_EBX)) {
5191 x86_push_reg (code, X86_EBX);
5193 cfa_offset += sizeof (gpointer);
5194 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5195 /* These are handled automatically by the stack marking code */
5196 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5199 if (cfg->used_int_regs & (1 << X86_EDI)) {
5200 x86_push_reg (code, X86_EDI);
5202 cfa_offset += sizeof (gpointer);
5203 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5204 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5207 if (cfg->used_int_regs & (1 << X86_ESI)) {
5208 x86_push_reg (code, X86_ESI);
5210 cfa_offset += sizeof (gpointer);
5211 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5212 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5218 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5219 if (mono_do_x86_stack_align && need_stack_frame) {
5220 int tot = alloc_size + pos + 4; /* ret ip */
5221 if (need_stack_frame)
5223 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5225 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5226 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5227 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5231 cfg->arch.sp_fp_offset = alloc_size + pos;
5234 /* See mono_emit_stack_alloc */
5235 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5236 guint32 remaining_size = alloc_size;
5237 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5238 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5239 guint32 offset = code - cfg->native_code;
5240 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5241 while (required_code_size >= (cfg->code_size - offset))
5242 cfg->code_size *= 2;
5243 cfg->native_code = mono_realloc_native_code(cfg);
5244 code = cfg->native_code + offset;
5245 cfg->stat_code_reallocs++;
5247 while (remaining_size >= 0x1000) {
5248 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5249 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5250 remaining_size -= 0x1000;
5253 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5255 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5258 g_assert (need_stack_frame);
5261 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5262 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5263 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5266 #if DEBUG_STACK_ALIGNMENT
5267 /* check the stack is aligned */
5268 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5269 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5270 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5271 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5272 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5273 x86_breakpoint (code);
5277 /* compute max_offset in order to use short forward jumps */
5279 if (cfg->opt & MONO_OPT_BRANCH) {
5280 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5282 bb->max_offset = max_offset;
5284 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5286 /* max alignment for loops */
5287 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5288 max_offset += LOOP_ALIGNMENT;
5289 #ifdef __native_client_codegen__
5290 /* max alignment for native client */
5291 max_offset += kNaClAlignment;
5293 MONO_BB_FOR_EACH_INS (bb, ins) {
5294 if (ins->opcode == OP_LABEL)
5295 ins->inst_c1 = max_offset;
5296 #ifdef __native_client_codegen__
5298 int space_in_block = kNaClAlignment -
5299 ((max_offset + cfg->code_len) & kNaClAlignmentMask);
5300 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5301 if (space_in_block < max_len && max_len < kNaClAlignment) {
5302 max_offset += space_in_block;
5305 #endif /* __native_client_codegen__ */
5306 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5311 /* store runtime generic context */
5312 if (cfg->rgctx_var) {
5313 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5315 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5318 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5319 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5321 /* load arguments allocated to register from the stack */
5322 sig = mono_method_signature (method);
5325 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5326 inst = cfg->args [pos];
5327 if (inst->opcode == OP_REGVAR) {
5328 g_assert (need_stack_frame);
5329 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5330 if (cfg->verbose_level > 2)
5331 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5336 cfg->code_len = code - cfg->native_code;
5338 g_assert (cfg->code_len < cfg->code_size);
5344 mono_arch_emit_epilog (MonoCompile *cfg)
5346 MonoMethod *method = cfg->method;
5347 MonoMethodSignature *sig = mono_method_signature (method);
5349 guint32 stack_to_pop;
5351 int max_epilog_size = 16;
5353 gboolean need_stack_frame = needs_stack_frame (cfg);
5355 if (cfg->method->save_lmf)
5356 max_epilog_size += 128;
5358 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5359 cfg->code_size *= 2;
5360 cfg->native_code = mono_realloc_native_code(cfg);
5361 cfg->stat_code_reallocs++;
5364 code = cfg->native_code + cfg->code_len;
5366 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5367 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5369 /* the code restoring the registers must be kept in sync with OP_JMP */
5372 if (method->save_lmf) {
5373 gint32 prev_lmf_reg;
5374 gint32 lmf_offset = -sizeof (MonoLMF);
5376 /* check if we need to restore protection of the stack after a stack overflow */
5377 if (mono_get_jit_tls_offset () != -1) {
5379 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5380 /* we load the value in a separate instruction: this mechanism may be
5381 * used later as a safer way to do thread interruption
5383 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5384 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5386 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5387 /* note that the call trampoline will preserve eax/edx */
5388 x86_call_reg (code, X86_ECX);
5389 x86_patch (patch, code);
5391 /* FIXME: maybe save the jit tls in the prolog */
5393 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5395 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5396 * through the mono_lmf_addr TLS variable.
5398 /* reg = previous_lmf */
5399 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5401 /* lmf = previous_lmf */
5402 code = mono_x86_emit_tls_set (code, X86_ECX, lmf_tls_offset);
5404 /* Find a spare register */
5405 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
5408 prev_lmf_reg = X86_EDI;
5409 cfg->used_int_regs |= (1 << X86_EDI);
5412 prev_lmf_reg = X86_EDX;
5416 /* reg = previous_lmf */
5417 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5420 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
5422 /* *(lmf) = previous_lmf */
5423 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
5426 /* restore caller saved regs */
5427 if (cfg->used_int_regs & (1 << X86_EBX)) {
5428 x86_mov_reg_membase (code, X86_EBX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
5431 if (cfg->used_int_regs & (1 << X86_EDI)) {
5432 x86_mov_reg_membase (code, X86_EDI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
5434 if (cfg->used_int_regs & (1 << X86_ESI)) {
5435 x86_mov_reg_membase (code, X86_ESI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
5438 /* EBP is restored by LEAVE */
5440 if (cfg->used_int_regs & (1 << X86_EBX)) {
5443 if (cfg->used_int_regs & (1 << X86_EDI)) {
5446 if (cfg->used_int_regs & (1 << X86_ESI)) {
5451 g_assert (need_stack_frame);
5452 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5455 if (cfg->used_int_regs & (1 << X86_ESI)) {
5456 x86_pop_reg (code, X86_ESI);
5458 if (cfg->used_int_regs & (1 << X86_EDI)) {
5459 x86_pop_reg (code, X86_EDI);
5461 if (cfg->used_int_regs & (1 << X86_EBX)) {
5462 x86_pop_reg (code, X86_EBX);
5466 /* Load returned vtypes into registers if needed */
5467 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5468 if (cinfo->ret.storage == ArgValuetypeInReg) {
5469 for (quad = 0; quad < 2; quad ++) {
5470 switch (cinfo->ret.pair_storage [quad]) {
5472 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5474 case ArgOnFloatFpStack:
5475 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5477 case ArgOnDoubleFpStack:
5478 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5483 g_assert_not_reached ();
5488 if (need_stack_frame)
5491 if (CALLCONV_IS_STDCALL (sig)) {
5492 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5494 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5495 } else if (cinfo->vtype_retaddr)
5501 g_assert (need_stack_frame);
5502 x86_ret_imm (code, stack_to_pop);
5507 cfg->code_len = code - cfg->native_code;
5509 g_assert (cfg->code_len < cfg->code_size);
5513 mono_arch_emit_exceptions (MonoCompile *cfg)
5515 MonoJumpInfo *patch_info;
5518 MonoClass *exc_classes [16];
5519 guint8 *exc_throw_start [16], *exc_throw_end [16];
5523 /* Compute needed space */
5524 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5525 if (patch_info->type == MONO_PATCH_INFO_EXC)
5530 * make sure we have enough space for exceptions
5531 * 16 is the size of two push_imm instructions and a call
5533 if (cfg->compile_aot)
5534 code_size = exc_count * 32;
5536 code_size = exc_count * 16;
5538 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5539 cfg->code_size *= 2;
5540 cfg->native_code = mono_realloc_native_code(cfg);
5541 cfg->stat_code_reallocs++;
5544 code = cfg->native_code + cfg->code_len;
5547 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5548 switch (patch_info->type) {
5549 case MONO_PATCH_INFO_EXC: {
5550 MonoClass *exc_class;
5554 x86_patch (patch_info->ip.i + cfg->native_code, code);
5556 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5557 g_assert (exc_class);
5558 throw_ip = patch_info->ip.i;
5560 /* Find a throw sequence for the same exception class */
5561 for (i = 0; i < nthrows; ++i)
5562 if (exc_classes [i] == exc_class)
5565 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5566 x86_jump_code (code, exc_throw_start [i]);
5567 patch_info->type = MONO_PATCH_INFO_NONE;
5572 /* Compute size of code following the push <OFFSET> */
5573 #if defined(__default_codegen__)
5575 #elif defined(__native_client_codegen__)
5576 code = mono_nacl_align (code);
5577 size = kNaClAlignment;
5579 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5581 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5582 /* Use the shorter form */
5584 x86_push_imm (code, 0);
5588 x86_push_imm (code, 0xf0f0f0f0);
5593 exc_classes [nthrows] = exc_class;
5594 exc_throw_start [nthrows] = code;
5597 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5598 patch_info->data.name = "mono_arch_throw_corlib_exception";
5599 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5600 patch_info->ip.i = code - cfg->native_code;
5601 x86_call_code (code, 0);
5602 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5607 exc_throw_end [nthrows] = code;
5619 cfg->code_len = code - cfg->native_code;
5621 g_assert (cfg->code_len < cfg->code_size);
5625 mono_arch_flush_icache (guint8 *code, gint size)
5631 mono_arch_flush_register_windows (void)
5636 mono_arch_is_inst_imm (gint64 imm)
5642 mono_arch_finish_init (void)
5644 if (!getenv ("MONO_NO_TLS")) {
5647 * We need to init this multiple times, since when we are first called, the key might not
5648 * be initialized yet.
5650 appdomain_tls_offset = mono_domain_get_tls_key ();
5651 lmf_tls_offset = mono_get_jit_tls_key ();
5653 /* Only 64 tls entries can be accessed using inline code */
5654 if (appdomain_tls_offset >= 64)
5655 appdomain_tls_offset = -1;
5656 if (lmf_tls_offset >= 64)
5657 lmf_tls_offset = -1;
5660 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5662 appdomain_tls_offset = mono_domain_get_tls_offset ();
5663 lmf_tls_offset = mono_get_lmf_tls_offset ();
5664 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5670 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5674 #ifdef MONO_ARCH_HAVE_IMT
5676 // Linear handler, the bsearch head compare is shorter
5677 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5678 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5679 // x86_patch(ins,target)
5680 //[1 + 5] x86_jump_mem(inst,mem)
5683 #if defined(__default_codegen__)
5684 #define BR_SMALL_SIZE 2
5685 #define BR_LARGE_SIZE 5
5686 #elif defined(__native_client_codegen__)
5687 /* I suspect the size calculation below is actually incorrect. */
5688 /* TODO: fix the calculation that uses these sizes. */
5689 #define BR_SMALL_SIZE 16
5690 #define BR_LARGE_SIZE 12
5691 #endif /*__native_client_codegen__*/
5692 #define JUMP_IMM_SIZE 6
5693 #define ENABLE_WRONG_METHOD_CHECK 0
5697 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5699 int i, distance = 0;
5700 for (i = start; i < target; ++i)
5701 distance += imt_entries [i]->chunk_size;
5706 * LOCKING: called with the domain lock held
5709 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5710 gpointer fail_tramp)
5714 guint8 *code, *start;
5716 for (i = 0; i < count; ++i) {
5717 MonoIMTCheckItem *item = imt_entries [i];
5718 if (item->is_equals) {
5719 if (item->check_target_idx) {
5720 if (!item->compare_done)
5721 item->chunk_size += CMP_SIZE;
5722 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5725 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5727 item->chunk_size += JUMP_IMM_SIZE;
5728 #if ENABLE_WRONG_METHOD_CHECK
5729 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5734 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5735 imt_entries [item->check_target_idx]->compare_done = TRUE;
5737 size += item->chunk_size;
5739 #if defined(__native_client__) && defined(__native_client_codegen__)
5740 /* In Native Client, we don't re-use thunks, allocate from the */
5741 /* normal code manager paths. */
5742 code = mono_domain_code_reserve (domain, size);
5745 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5747 code = mono_domain_code_reserve (domain, size);
5750 for (i = 0; i < count; ++i) {
5751 MonoIMTCheckItem *item = imt_entries [i];
5752 item->code_target = code;
5753 if (item->is_equals) {
5754 if (item->check_target_idx) {
5755 if (!item->compare_done)
5756 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5757 item->jmp_code = code;
5758 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5759 if (item->has_target_code)
5760 x86_jump_code (code, item->value.target_code);
5762 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5765 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5766 item->jmp_code = code;
5767 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5768 if (item->has_target_code)
5769 x86_jump_code (code, item->value.target_code);
5771 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5772 x86_patch (item->jmp_code, code);
5773 x86_jump_code (code, fail_tramp);
5774 item->jmp_code = NULL;
5776 /* enable the commented code to assert on wrong method */
5777 #if ENABLE_WRONG_METHOD_CHECK
5778 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5779 item->jmp_code = code;
5780 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5782 if (item->has_target_code)
5783 x86_jump_code (code, item->value.target_code);
5785 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5786 #if ENABLE_WRONG_METHOD_CHECK
5787 x86_patch (item->jmp_code, code);
5788 x86_breakpoint (code);
5789 item->jmp_code = NULL;
5794 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5795 item->jmp_code = code;
5796 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5797 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5799 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5802 /* patch the branches to get to the target items */
5803 for (i = 0; i < count; ++i) {
5804 MonoIMTCheckItem *item = imt_entries [i];
5805 if (item->jmp_code) {
5806 if (item->check_target_idx) {
5807 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5813 mono_stats.imt_thunks_size += code - start;
5814 g_assert (code - start <= size);
5818 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5819 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5823 if (mono_jit_map_is_enabled ()) {
5826 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5828 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5829 mono_emit_jit_tramp (start, code - start, buff);
5833 nacl_domain_code_validate (domain, &start, size, &code);
5839 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5841 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5846 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5848 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5852 mono_arch_get_cie_program (void)
5856 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5857 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5863 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5865 MonoInst *ins = NULL;
5868 if (cmethod->klass == mono_defaults.math_class) {
5869 if (strcmp (cmethod->name, "Sin") == 0) {
5871 } else if (strcmp (cmethod->name, "Cos") == 0) {
5873 } else if (strcmp (cmethod->name, "Tan") == 0) {
5875 } else if (strcmp (cmethod->name, "Atan") == 0) {
5877 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5879 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5881 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5886 MONO_INST_NEW (cfg, ins, opcode);
5887 ins->type = STACK_R8;
5888 ins->dreg = mono_alloc_freg (cfg);
5889 ins->sreg1 = args [0]->dreg;
5890 MONO_ADD_INS (cfg->cbb, ins);
5893 if (cfg->opt & MONO_OPT_CMOV) {
5896 if (strcmp (cmethod->name, "Min") == 0) {
5897 if (fsig->params [0]->type == MONO_TYPE_I4)
5899 } else if (strcmp (cmethod->name, "Max") == 0) {
5900 if (fsig->params [0]->type == MONO_TYPE_I4)
5905 MONO_INST_NEW (cfg, ins, opcode);
5906 ins->type = STACK_I4;
5907 ins->dreg = mono_alloc_ireg (cfg);
5908 ins->sreg1 = args [0]->dreg;
5909 ins->sreg2 = args [1]->dreg;
5910 MONO_ADD_INS (cfg->cbb, ins);
5915 /* OP_FREM is not IEEE compatible */
5916 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5917 MONO_INST_NEW (cfg, ins, OP_FREM);
5918 ins->inst_i0 = args [0];
5919 ins->inst_i1 = args [1];
5928 mono_arch_print_tree (MonoInst *tree, int arity)
5933 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5939 if (appdomain_tls_offset == -1)
5942 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5943 ins->inst_offset = appdomain_tls_offset;
5948 mono_arch_get_patch_offset (guint8 *code)
5950 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5952 else if (code [0] == 0xba)
5954 else if (code [0] == 0x68)
5957 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5958 /* push <OFFSET>(<REG>) */
5960 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5961 /* call *<OFFSET>(<REG>) */
5963 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5966 else if ((code [0] == 0x58) && (code [1] == 0x05))
5967 /* pop %eax; add <OFFSET>, %eax */
5969 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5970 /* pop <REG>; add <OFFSET>, <REG> */
5972 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5973 /* mov <REG>, imm */
5976 g_assert_not_reached ();
5982 * mono_breakpoint_clean_code:
5984 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5985 * breakpoints in the original code, they are removed in the copy.
5987 * Returns TRUE if no sw breakpoint was present.
5990 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5993 gboolean can_write = TRUE;
5995 * If method_start is non-NULL we need to perform bound checks, since we access memory
5996 * at code - offset we could go before the start of the method and end up in a different
5997 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6000 if (!method_start || code - offset >= method_start) {
6001 memcpy (buf, code - offset, size);
6003 int diff = code - method_start;
6004 memset (buf, 0, size);
6005 memcpy (buf + offset - diff, method_start, diff + size - offset);
6008 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6009 int idx = mono_breakpoint_info_index [i];
6013 ptr = mono_breakpoint_info [idx].address;
6014 if (ptr >= code && ptr < code + size) {
6015 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6017 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6018 buf [ptr - code] = saved_byte;
6025 * mono_x86_get_this_arg_offset:
6027 * Return the offset of the stack location where this is passed during a virtual
6031 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6037 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6039 guint32 esp = regs [X86_ESP];
6040 CallInfo *cinfo = NULL;
6047 * The stack looks like:
6051 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
6053 res = (((MonoObject**)esp) [5 + (offset / 4)]);
6059 #define MAX_ARCH_DELEGATE_PARAMS 10
6062 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6064 guint8 *code, *start;
6065 int code_reserve = 64;
6068 * The stack contains:
6074 start = code = mono_global_codeman_reserve (code_reserve);
6076 /* Replace the this argument with the target */
6077 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6078 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
6079 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6080 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6082 g_assert ((code - start) < code_reserve);
6085 /* 8 for mov_reg and jump, plus 8 for each parameter */
6086 #ifdef __native_client_codegen__
6087 /* TODO: calculate this size correctly */
6088 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6090 code_reserve = 8 + (param_count * 8);
6091 #endif /* __native_client_codegen__ */
6093 * The stack contains:
6094 * <args in reverse order>
6099 * <args in reverse order>
6102 * without unbalancing the stack.
6103 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6104 * and leaving original spot of first arg as placeholder in stack so
6105 * when callee pops stack everything works.
6108 start = code = mono_global_codeman_reserve (code_reserve);
6110 /* store delegate for access to method_ptr */
6111 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6114 for (i = 0; i < param_count; ++i) {
6115 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6116 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6119 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6121 g_assert ((code - start) < code_reserve);
6124 nacl_global_codeman_validate(&start, code_reserve, &code);
6125 mono_debug_add_delegate_trampoline (start, code - start);
6128 *code_len = code - start;
6130 if (mono_jit_map_is_enabled ()) {
6133 buff = (char*)"delegate_invoke_has_target";
6135 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6136 mono_emit_jit_tramp (start, code - start, buff);
6145 mono_arch_get_delegate_invoke_impls (void)
6152 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6153 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
6155 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6156 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6157 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
6164 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6166 guint8 *code, *start;
6168 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6171 /* FIXME: Support more cases */
6172 if (MONO_TYPE_ISSTRUCT (sig->ret))
6176 * The stack contains:
6182 static guint8* cached = NULL;
6187 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6189 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6191 mono_memory_barrier ();
6195 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6198 for (i = 0; i < sig->param_count; ++i)
6199 if (!mono_is_regsize_var (sig->params [i]))
6202 code = cache [sig->param_count];
6206 if (mono_aot_only) {
6207 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6208 start = mono_aot_get_trampoline (name);
6211 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6214 mono_memory_barrier ();
6216 cache [sig->param_count] = start;
6223 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6226 case X86_EAX: return ctx->eax;
6227 case X86_EBX: return ctx->ebx;
6228 case X86_ECX: return ctx->ecx;
6229 case X86_EDX: return ctx->edx;
6230 case X86_ESP: return ctx->esp;
6231 case X86_EBP: return ctx->ebp;
6232 case X86_ESI: return ctx->esi;
6233 case X86_EDI: return ctx->edi;
6235 g_assert_not_reached ();
6241 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6269 g_assert_not_reached ();
6273 #ifdef MONO_ARCH_SIMD_INTRINSICS
6276 get_float_to_x_spill_area (MonoCompile *cfg)
6278 if (!cfg->fconv_to_r8_x_var) {
6279 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6280 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6282 return cfg->fconv_to_r8_x_var;
6286 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6289 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6292 int dreg, src_opcode;
6294 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6297 switch (src_opcode = ins->opcode) {
6298 case OP_FCONV_TO_I1:
6299 case OP_FCONV_TO_U1:
6300 case OP_FCONV_TO_I2:
6301 case OP_FCONV_TO_U2:
6302 case OP_FCONV_TO_I4:
6309 /* dreg is the IREG and sreg1 is the FREG */
6310 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6311 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6312 fconv->sreg1 = ins->sreg1;
6313 fconv->dreg = mono_alloc_ireg (cfg);
6314 fconv->type = STACK_VTYPE;
6315 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6317 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6321 ins->opcode = OP_XCONV_R8_TO_I4;
6323 ins->klass = mono_defaults.int32_class;
6324 ins->sreg1 = fconv->dreg;
6326 ins->type = STACK_I4;
6327 ins->backend.source_opcode = src_opcode;
6330 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6333 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6338 if (long_ins->opcode == OP_LNEG) {
6340 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6341 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6342 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6347 #ifdef MONO_ARCH_SIMD_INTRINSICS
6349 if (!(cfg->opt & MONO_OPT_SIMD))
6352 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6353 switch (long_ins->opcode) {
6355 vreg = long_ins->sreg1;
6357 if (long_ins->inst_c0) {
6358 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6359 ins->klass = long_ins->klass;
6360 ins->sreg1 = long_ins->sreg1;
6362 ins->type = STACK_VTYPE;
6363 ins->dreg = vreg = alloc_ireg (cfg);
6364 MONO_ADD_INS (cfg->cbb, ins);
6367 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6368 ins->klass = mono_defaults.int32_class;
6370 ins->type = STACK_I4;
6371 ins->dreg = long_ins->dreg + 1;
6372 MONO_ADD_INS (cfg->cbb, ins);
6374 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6375 ins->klass = long_ins->klass;
6376 ins->sreg1 = long_ins->sreg1;
6377 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6378 ins->type = STACK_VTYPE;
6379 ins->dreg = vreg = alloc_ireg (cfg);
6380 MONO_ADD_INS (cfg->cbb, ins);
6382 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6383 ins->klass = mono_defaults.int32_class;
6385 ins->type = STACK_I4;
6386 ins->dreg = long_ins->dreg + 2;
6387 MONO_ADD_INS (cfg->cbb, ins);
6389 long_ins->opcode = OP_NOP;
6391 case OP_INSERTX_I8_SLOW:
6392 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6393 ins->dreg = long_ins->dreg;
6394 ins->sreg1 = long_ins->dreg;
6395 ins->sreg2 = long_ins->sreg2 + 1;
6396 ins->inst_c0 = long_ins->inst_c0 * 2;
6397 MONO_ADD_INS (cfg->cbb, ins);
6399 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6400 ins->dreg = long_ins->dreg;
6401 ins->sreg1 = long_ins->dreg;
6402 ins->sreg2 = long_ins->sreg2 + 2;
6403 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6404 MONO_ADD_INS (cfg->cbb, ins);
6406 long_ins->opcode = OP_NOP;
6409 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6410 ins->dreg = long_ins->dreg;
6411 ins->sreg1 = long_ins->sreg1 + 1;
6412 ins->klass = long_ins->klass;
6413 ins->type = STACK_VTYPE;
6414 MONO_ADD_INS (cfg->cbb, ins);
6416 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6417 ins->dreg = long_ins->dreg;
6418 ins->sreg1 = long_ins->dreg;
6419 ins->sreg2 = long_ins->sreg1 + 2;
6421 ins->klass = long_ins->klass;
6422 ins->type = STACK_VTYPE;
6423 MONO_ADD_INS (cfg->cbb, ins);
6425 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6426 ins->dreg = long_ins->dreg;
6427 ins->sreg1 = long_ins->dreg;;
6428 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6429 ins->klass = long_ins->klass;
6430 ins->type = STACK_VTYPE;
6431 MONO_ADD_INS (cfg->cbb, ins);
6433 long_ins->opcode = OP_NOP;
6436 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6439 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6441 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6444 gpointer *sp, old_value;
6446 const unsigned char *handler;
6448 /*Decode the first instruction to figure out where did we store the spvar*/
6449 /*Our jit MUST generate the following:
6451 Which is encoded as: 0x89 mod_rm.
6452 mod_rm (esp, ebp, imm) which can be: (imm will never be zero)
6453 mod (reg + imm8): 01 reg(esp): 100 rm(ebp): 101 -> 01100101 (0x65)
6454 mod (reg + imm32): 10 reg(esp): 100 rm(ebp): 101 -> 10100101 (0xA5)
6456 handler = clause->handler_start;
6458 if (*handler != 0x89)
6463 if (*handler == 0x65)
6464 offset = *(signed char*)(handler + 1);
6465 else if (*handler == 0xA5)
6466 offset = *(int*)(handler + 1);
6471 bp = MONO_CONTEXT_GET_BP (ctx);
6472 sp = *(gpointer*)(bp + offset);
6475 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6484 * mono_aot_emit_load_got_addr:
6486 * Emit code to load the got address.
6487 * On x86, the result is placed into EBX.
6490 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6492 x86_call_imm (code, 0);
6494 * The patch needs to point to the pop, since the GOT offset needs
6495 * to be added to that address.
6498 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6500 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6501 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6502 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6508 * mono_ppc_emit_load_aotconst:
6510 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6511 * TARGET from the mscorlib GOT in full-aot code.
6512 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6516 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6518 /* Load the mscorlib got address */
6519 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6520 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6521 /* arch_emit_got_access () patches this */
6522 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6527 /* Can't put this into mini-x86.h */
6529 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6532 mono_arch_get_trampolines (gboolean aot)
6534 MonoTrampInfo *info;
6535 GSList *tramps = NULL;
6537 mono_x86_get_signal_exception_trampoline (&info, aot);
6539 tramps = g_slist_append (tramps, info);
6546 #define DBG_SIGNAL SIGBUS
6548 #define DBG_SIGNAL SIGSEGV
6551 /* Soft Debug support */
6552 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6555 * mono_arch_set_breakpoint:
6557 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6558 * The location should contain code emitted by OP_SEQ_POINT.
6561 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6566 * In production, we will use int3 (has to fix the size in the md
6567 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6570 g_assert (code [0] == 0x90);
6571 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6575 * mono_arch_clear_breakpoint:
6577 * Clear the breakpoint at IP.
6580 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6585 for (i = 0; i < 6; ++i)
6590 * mono_arch_start_single_stepping:
6592 * Start single stepping.
6595 mono_arch_start_single_stepping (void)
6597 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6601 * mono_arch_stop_single_stepping:
6603 * Stop single stepping.
6606 mono_arch_stop_single_stepping (void)
6608 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6612 * mono_arch_is_single_step_event:
6614 * Return whenever the machine state in SIGCTX corresponds to a single
6618 mono_arch_is_single_step_event (void *info, void *sigctx)
6621 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6623 if ((einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6628 siginfo_t* sinfo = (siginfo_t*) info;
6629 /* Sometimes the address is off by 4 */
6630 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6638 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6641 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6642 if ((einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6647 siginfo_t* sinfo = (siginfo_t*)info;
6648 /* Sometimes the address is off by 4 */
6649 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6656 #define BREAKPOINT_SIZE 6
6659 * mono_arch_skip_breakpoint:
6661 * See mini-amd64.c for docs.
6664 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6666 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6670 * mono_arch_skip_single_step:
6672 * See mini-amd64.c for docs.
6675 mono_arch_skip_single_step (MonoContext *ctx)
6677 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6681 * mono_arch_get_seq_point_info:
6683 * See mini-amd64.c for docs.
6686 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6694 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
6696 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6698 #endif /* !MONOTOUCH */