2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/appdomain.h>
21 #include <mono/metadata/debug-helpers.h>
22 #include <mono/metadata/threads.h>
23 #include <mono/metadata/profiler-private.h>
24 #include <mono/metadata/mono-debug.h>
25 #include <mono/metadata/gc-internal.h>
26 #include <mono/utils/mono-math.h>
27 #include <mono/utils/mono-counters.h>
28 #include <mono/utils/mono-mmap.h>
29 #include <mono/utils/mono-memory-model.h>
37 /* On windows, these hold the key returned by TlsAlloc () */
38 static gint lmf_tls_offset = -1;
39 static gint lmf_addr_tls_offset = -1;
40 static gint appdomain_tls_offset = -1;
43 static gboolean optimize_for_xen = TRUE;
45 #define optimize_for_xen 0
49 static gboolean is_win32 = TRUE;
51 static gboolean is_win32 = FALSE;
54 /* This mutex protects architecture specific caches */
55 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
56 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
57 static CRITICAL_SECTION mini_arch_mutex;
59 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
64 /* Under windows, the default pinvoke calling convention is stdcall */
65 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT))
67 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL)
70 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
73 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
76 #ifdef __native_client_codegen__
77 const guint kNaClAlignment = kNaClAlignmentX86;
78 const guint kNaClAlignmentMask = kNaClAlignmentMaskX86;
80 /* Default alignment for Native Client is 32-byte. */
81 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
83 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
84 /* Check that alignment doesn't cross an alignment boundary. */
86 mono_arch_nacl_pad (guint8 *code, int pad)
88 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
90 if (pad == 0) return code;
91 /* assertion: alignment cannot cross a block boundary */
92 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
93 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
94 while (pad >= kMaxPadding) {
95 x86_padding (code, kMaxPadding);
98 if (pad != 0) x86_padding (code, pad);
103 mono_arch_nacl_skip_nops (guint8 *code)
105 x86_skip_nops (code);
109 #endif /* __native_client_codegen__ */
112 * The code generated for sequence points reads from this location, which is
113 * made read-only when single stepping is enabled.
115 static gpointer ss_trigger_page;
117 /* Enabled breakpoints read from this trigger page */
118 static gpointer bp_trigger_page;
121 mono_arch_regname (int reg)
124 case X86_EAX: return "%eax";
125 case X86_EBX: return "%ebx";
126 case X86_ECX: return "%ecx";
127 case X86_EDX: return "%edx";
128 case X86_ESP: return "%esp";
129 case X86_EBP: return "%ebp";
130 case X86_EDI: return "%edi";
131 case X86_ESI: return "%esi";
137 mono_arch_fregname (int reg)
162 mono_arch_xregname (int reg)
187 mono_x86_patch (unsigned char* code, gpointer target)
189 x86_patch (code, (unsigned char*)target);
208 /* Only if storage == ArgValuetypeInReg */
209 ArgStorage pair_storage [2];
218 gboolean need_stack_align;
219 guint32 stack_align_amount;
220 gboolean vtype_retaddr;
221 /* The index of the vret arg in the argument list */
230 #define FLOAT_PARAM_REGS 0
232 static X86_Reg_No param_regs [] = { 0 };
234 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
235 #define SMALL_STRUCTS_IN_REGS
236 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
240 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
242 ainfo->offset = *stack_size;
244 if (*gr >= PARAM_REGS) {
245 ainfo->storage = ArgOnStack;
246 (*stack_size) += sizeof (gpointer);
249 ainfo->storage = ArgInIReg;
250 ainfo->reg = param_regs [*gr];
256 add_general_pair (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
258 ainfo->offset = *stack_size;
260 g_assert (PARAM_REGS == 0);
262 ainfo->storage = ArgOnStack;
263 (*stack_size) += sizeof (gpointer) * 2;
267 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
269 ainfo->offset = *stack_size;
271 if (*gr >= FLOAT_PARAM_REGS) {
272 ainfo->storage = ArgOnStack;
273 (*stack_size) += is_double ? 8 : 4;
276 /* A double register */
278 ainfo->storage = ArgInDoubleSSEReg;
280 ainfo->storage = ArgInFloatSSEReg;
288 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
290 guint32 *gr, guint32 *fr, guint32 *stack_size)
295 klass = mono_class_from_mono_type (type);
296 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
298 #ifdef SMALL_STRUCTS_IN_REGS
299 if (sig->pinvoke && is_return) {
300 MonoMarshalType *info;
303 * the exact rules are not very well documented, the code below seems to work with the
304 * code generated by gcc 3.3.3 -mno-cygwin.
306 info = mono_marshal_load_type_info (klass);
309 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
311 /* Special case structs with only a float member */
312 if ((info->native_size == 8) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R8)) {
313 ainfo->storage = ArgValuetypeInReg;
314 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
317 if ((info->native_size == 4) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R4)) {
318 ainfo->storage = ArgValuetypeInReg;
319 ainfo->pair_storage [0] = ArgOnFloatFpStack;
322 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
323 ainfo->storage = ArgValuetypeInReg;
324 ainfo->pair_storage [0] = ArgInIReg;
325 ainfo->pair_regs [0] = return_regs [0];
326 if (info->native_size > 4) {
327 ainfo->pair_storage [1] = ArgInIReg;
328 ainfo->pair_regs [1] = return_regs [1];
335 ainfo->offset = *stack_size;
336 ainfo->storage = ArgOnStack;
337 *stack_size += ALIGN_TO (size, sizeof (gpointer));
343 * Obtain information about a call according to the calling convention.
344 * For x86 ELF, see the "System V Application Binary Interface Intel386
345 * Architecture Processor Supplment, Fourth Edition" document for more
347 * For x86 win32, see ???.
350 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
352 guint32 i, gr, fr, pstart;
354 int n = sig->hasthis + sig->param_count;
355 guint32 stack_size = 0;
356 gboolean is_pinvoke = sig->pinvoke;
363 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
364 switch (ret_type->type) {
365 case MONO_TYPE_BOOLEAN:
376 case MONO_TYPE_FNPTR:
377 case MONO_TYPE_CLASS:
378 case MONO_TYPE_OBJECT:
379 case MONO_TYPE_SZARRAY:
380 case MONO_TYPE_ARRAY:
381 case MONO_TYPE_STRING:
382 cinfo->ret.storage = ArgInIReg;
383 cinfo->ret.reg = X86_EAX;
387 cinfo->ret.storage = ArgInIReg;
388 cinfo->ret.reg = X86_EAX;
391 cinfo->ret.storage = ArgOnFloatFpStack;
394 cinfo->ret.storage = ArgOnDoubleFpStack;
396 case MONO_TYPE_GENERICINST:
397 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
398 cinfo->ret.storage = ArgInIReg;
399 cinfo->ret.reg = X86_EAX;
403 case MONO_TYPE_VALUETYPE: {
404 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
406 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
407 if (cinfo->ret.storage == ArgOnStack) {
408 cinfo->vtype_retaddr = TRUE;
409 /* The caller passes the address where the value is stored */
413 case MONO_TYPE_TYPEDBYREF:
414 /* Same as a valuetype with size 12 */
415 cinfo->vtype_retaddr = TRUE;
418 cinfo->ret.storage = ArgNone;
421 g_error ("Can't handle as return value 0x%x", sig->ret->type);
427 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
428 * the first argument, allowing 'this' to be always passed in the first arg reg.
429 * Also do this if the first argument is a reference type, since virtual calls
430 * are sometimes made using calli without sig->hasthis set, like in the delegate
433 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
435 add_general (&gr, &stack_size, cinfo->args + 0);
437 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
440 add_general (&gr, &stack_size, &cinfo->ret);
441 cinfo->vret_arg_index = 1;
445 add_general (&gr, &stack_size, cinfo->args + 0);
447 if (cinfo->vtype_retaddr)
448 add_general (&gr, &stack_size, &cinfo->ret);
451 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
453 fr = FLOAT_PARAM_REGS;
455 /* Emit the signature cookie just before the implicit arguments */
456 add_general (&gr, &stack_size, &cinfo->sig_cookie);
459 for (i = pstart; i < sig->param_count; ++i) {
460 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
463 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
464 /* We allways pass the sig cookie on the stack for simplicity */
466 * Prevent implicit arguments + the sig cookie from being passed
470 fr = FLOAT_PARAM_REGS;
472 /* Emit the signature cookie just before the implicit arguments */
473 add_general (&gr, &stack_size, &cinfo->sig_cookie);
476 if (sig->params [i]->byref) {
477 add_general (&gr, &stack_size, ainfo);
480 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
481 switch (ptype->type) {
482 case MONO_TYPE_BOOLEAN:
485 add_general (&gr, &stack_size, ainfo);
490 add_general (&gr, &stack_size, ainfo);
494 add_general (&gr, &stack_size, ainfo);
499 case MONO_TYPE_FNPTR:
500 case MONO_TYPE_CLASS:
501 case MONO_TYPE_OBJECT:
502 case MONO_TYPE_STRING:
503 case MONO_TYPE_SZARRAY:
504 case MONO_TYPE_ARRAY:
505 add_general (&gr, &stack_size, ainfo);
507 case MONO_TYPE_GENERICINST:
508 if (!mono_type_generic_inst_is_valuetype (ptype)) {
509 add_general (&gr, &stack_size, ainfo);
513 case MONO_TYPE_VALUETYPE:
514 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
516 case MONO_TYPE_TYPEDBYREF:
517 stack_size += sizeof (MonoTypedRef);
518 ainfo->storage = ArgOnStack;
522 add_general_pair (&gr, &stack_size, ainfo);
525 add_float (&fr, &stack_size, ainfo, FALSE);
528 add_float (&fr, &stack_size, ainfo, TRUE);
531 g_error ("unexpected type 0x%x", ptype->type);
532 g_assert_not_reached ();
536 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
538 fr = FLOAT_PARAM_REGS;
540 /* Emit the signature cookie just before the implicit arguments */
541 add_general (&gr, &stack_size, &cinfo->sig_cookie);
544 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
545 cinfo->need_stack_align = TRUE;
546 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
547 stack_size += cinfo->stack_align_amount;
550 cinfo->stack_usage = stack_size;
551 cinfo->reg_usage = gr;
552 cinfo->freg_usage = fr;
557 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
559 int n = sig->hasthis + sig->param_count;
563 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
565 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
567 return get_call_info_internal (gsctx, cinfo, sig);
571 * mono_arch_get_argument_info:
572 * @csig: a method signature
573 * @param_count: the number of parameters to consider
574 * @arg_info: an array to store the result infos
576 * Gathers information on parameters such as size, alignment and
577 * padding. arg_info should be large enought to hold param_count + 1 entries.
579 * Returns the size of the argument area on the stack.
580 * This should be signal safe, since it is called from
581 * mono_arch_find_jit_info ().
582 * FIXME: The metadata calls might not be signal safe.
585 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
587 int len, k, args_size = 0;
593 /* Avoid g_malloc as it is not signal safe */
594 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
595 cinfo = (CallInfo*)g_newa (guint8*, len);
596 memset (cinfo, 0, len);
598 cinfo = get_call_info_internal (gsctx, cinfo, csig);
600 arg_info [0].offset = offset;
602 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
603 args_size += sizeof (gpointer);
608 args_size += sizeof (gpointer);
612 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
613 /* Emitted after this */
614 args_size += sizeof (gpointer);
618 arg_info [0].size = args_size;
620 for (k = 0; k < param_count; k++) {
621 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
623 /* ignore alignment for now */
626 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
627 arg_info [k].pad = pad;
629 arg_info [k + 1].pad = 0;
630 arg_info [k + 1].size = size;
632 arg_info [k + 1].offset = offset;
635 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
636 /* Emitted after the first arg */
637 args_size += sizeof (gpointer);
642 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
643 align = MONO_ARCH_FRAME_ALIGNMENT;
646 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
647 arg_info [k].pad = pad;
653 mono_x86_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
658 c1 = get_call_info (NULL, NULL, caller_sig);
659 c2 = get_call_info (NULL, NULL, callee_sig);
660 res = c1->stack_usage >= c2->stack_usage;
661 if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
662 /* An address on the callee's stack is passed as the first argument */
671 static const guchar cpuid_impl [] = {
672 0x55, /* push %ebp */
673 0x89, 0xe5, /* mov %esp,%ebp */
674 0x53, /* push %ebx */
675 0x8b, 0x45, 0x08, /* mov 0x8(%ebp),%eax */
676 0x0f, 0xa2, /* cpuid */
677 0x50, /* push %eax */
678 0x8b, 0x45, 0x10, /* mov 0x10(%ebp),%eax */
679 0x89, 0x18, /* mov %ebx,(%eax) */
680 0x8b, 0x45, 0x14, /* mov 0x14(%ebp),%eax */
681 0x89, 0x08, /* mov %ecx,(%eax) */
682 0x8b, 0x45, 0x18, /* mov 0x18(%ebp),%eax */
683 0x89, 0x10, /* mov %edx,(%eax) */
685 0x8b, 0x55, 0x0c, /* mov 0xc(%ebp),%edx */
686 0x89, 0x02, /* mov %eax,(%edx) */
692 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
695 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
697 #if defined(__native_client__)
698 /* Taken from below, the bug listed in the comment is */
699 /* only valid for non-static cases. */
700 __asm__ __volatile__ ("cpuid"
701 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
707 __asm__ __volatile__ (
710 "movl %%eax, %%edx\n"
711 "xorl $0x200000, %%eax\n"
716 "xorl %%edx, %%eax\n"
717 "andl $0x200000, %%eax\n"
739 /* Have to use the code manager to get around WinXP DEP */
740 static CpuidFunc func = NULL;
743 ptr = mono_global_codeman_reserve (sizeof (cpuid_impl));
744 memcpy (ptr, cpuid_impl, sizeof (cpuid_impl));
745 func = (CpuidFunc)ptr;
747 func (id, p_eax, p_ebx, p_ecx, p_edx);
750 * We use this approach because of issues with gcc and pic code, see:
751 * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
752 __asm__ __volatile__ ("cpuid"
753 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
763 * Initialize the cpu to execute managed code.
766 mono_arch_cpu_init (void)
768 /* spec compliance requires running with double precision */
772 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
773 fpcw &= ~X86_FPCW_PRECC_MASK;
774 fpcw |= X86_FPCW_PREC_DOUBLE;
775 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
776 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
778 _control87 (_PC_53, MCW_PC);
783 * Initialize architecture specific code.
786 mono_arch_init (void)
788 InitializeCriticalSection (&mini_arch_mutex);
790 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
791 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
792 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
794 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
795 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
799 * Cleanup architecture specific code.
802 mono_arch_cleanup (void)
805 mono_vfree (ss_trigger_page, mono_pagesize ());
807 mono_vfree (bp_trigger_page, mono_pagesize ());
808 DeleteCriticalSection (&mini_arch_mutex);
812 * This function returns the optimizations supported on this cpu.
815 mono_arch_cpu_optimizations (guint32 *exclude_mask)
817 #if !defined(__native_client__)
818 int eax, ebx, ecx, edx;
824 /* The cpuid function allocates from the global codeman */
827 /* Feature Flags function, flags returned in EDX. */
828 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
829 if (edx & (1 << 15)) {
830 opts |= MONO_OPT_CMOV;
832 opts |= MONO_OPT_FCMOV;
834 *exclude_mask |= MONO_OPT_FCMOV;
836 *exclude_mask |= MONO_OPT_CMOV;
838 opts |= MONO_OPT_SSE2;
840 *exclude_mask |= MONO_OPT_SSE2;
842 #ifdef MONO_ARCH_SIMD_INTRINSICS
843 /*SIMD intrinsics require at least SSE2.*/
844 if (!(opts & MONO_OPT_SSE2))
845 *exclude_mask |= MONO_OPT_SIMD;
850 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
855 * This function test for all SSE functions supported.
857 * Returns a bitmask corresponding to all supported versions.
861 mono_arch_cpu_enumerate_simd_versions (void)
863 int eax, ebx, ecx, edx;
864 guint32 sse_opts = 0;
867 /* The cpuid function allocates from the global codeman */
870 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
872 sse_opts |= SIMD_VERSION_SSE1;
874 sse_opts |= SIMD_VERSION_SSE2;
876 sse_opts |= SIMD_VERSION_SSE3;
878 sse_opts |= SIMD_VERSION_SSSE3;
880 sse_opts |= SIMD_VERSION_SSE41;
882 sse_opts |= SIMD_VERSION_SSE42;
885 /* Yes, all this needs to be done to check for sse4a.
886 See: "Amd: CPUID Specification"
888 if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
889 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
890 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
891 cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
893 sse_opts |= SIMD_VERSION_SSE4a;
902 * Determine whenever the trap whose info is in SIGINFO is caused by
906 mono_arch_is_int_overflow (void *sigctx, void *info)
911 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
913 ip = (guint8*)ctx.eip;
915 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
919 switch (x86_modrm_rm (ip [1])) {
939 g_assert_not_reached ();
951 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
956 for (i = 0; i < cfg->num_varinfo; i++) {
957 MonoInst *ins = cfg->varinfo [i];
958 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
961 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
964 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
965 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
968 /* we dont allocate I1 to registers because there is no simply way to sign extend
969 * 8bit quantities in caller saved registers on x86 */
970 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
971 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
972 g_assert (i == vmv->idx);
973 vars = g_list_prepend (vars, vmv);
977 vars = mono_varlist_sort (cfg, vars, 0);
983 mono_arch_get_global_int_regs (MonoCompile *cfg)
987 /* we can use 3 registers for global allocation */
988 regs = g_list_prepend (regs, (gpointer)X86_EBX);
989 regs = g_list_prepend (regs, (gpointer)X86_ESI);
990 regs = g_list_prepend (regs, (gpointer)X86_EDI);
996 * mono_arch_regalloc_cost:
998 * Return the cost, in number of memory references, of the action of
999 * allocating the variable VMV into a register during global register
1003 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1005 MonoInst *ins = cfg->varinfo [vmv->idx];
1007 if (cfg->method->save_lmf)
1008 /* The register is already saved */
1009 return (ins->opcode == OP_ARG) ? 1 : 0;
1011 /* push+pop+possible load if it is an argument */
1012 return (ins->opcode == OP_ARG) ? 3 : 2;
1016 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
1018 static int inited = FALSE;
1019 static int count = 0;
1021 if (cfg->arch.need_stack_frame_inited) {
1022 g_assert (cfg->arch.need_stack_frame == flag);
1026 cfg->arch.need_stack_frame = flag;
1027 cfg->arch.need_stack_frame_inited = TRUE;
1033 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
1038 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
1042 needs_stack_frame (MonoCompile *cfg)
1044 MonoMethodSignature *sig;
1045 MonoMethodHeader *header;
1046 gboolean result = FALSE;
1048 #if defined(__APPLE__)
1049 /*OSX requires stack frame code to have the correct alignment. */
1053 if (cfg->arch.need_stack_frame_inited)
1054 return cfg->arch.need_stack_frame;
1056 header = cfg->header;
1057 sig = mono_method_signature (cfg->method);
1059 if (cfg->disable_omit_fp)
1061 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1063 else if (cfg->method->save_lmf)
1065 else if (cfg->stack_offset)
1067 else if (cfg->param_area)
1069 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1071 else if (header->num_clauses)
1073 else if (sig->param_count + sig->hasthis)
1075 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1077 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1078 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1081 set_needs_stack_frame (cfg, result);
1083 return cfg->arch.need_stack_frame;
1087 * Set var information according to the calling convention. X86 version.
1088 * The locals var stuff should most likely be split in another method.
1091 mono_arch_allocate_vars (MonoCompile *cfg)
1093 MonoMethodSignature *sig;
1094 MonoMethodHeader *header;
1096 guint32 locals_stack_size, locals_stack_align;
1101 header = cfg->header;
1102 sig = mono_method_signature (cfg->method);
1104 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1106 cfg->frame_reg = X86_EBP;
1109 /* Reserve space to save LMF and caller saved registers */
1111 if (cfg->method->save_lmf) {
1112 offset += sizeof (MonoLMF);
1114 if (cfg->used_int_regs & (1 << X86_EBX)) {
1118 if (cfg->used_int_regs & (1 << X86_EDI)) {
1122 if (cfg->used_int_regs & (1 << X86_ESI)) {
1127 switch (cinfo->ret.storage) {
1128 case ArgValuetypeInReg:
1129 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1131 cfg->ret->opcode = OP_REGOFFSET;
1132 cfg->ret->inst_basereg = X86_EBP;
1133 cfg->ret->inst_offset = - offset;
1139 /* Allocate locals */
1140 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1141 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1142 char *mname = mono_method_full_name (cfg->method, TRUE);
1143 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1144 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1148 if (locals_stack_align) {
1149 int prev_offset = offset;
1151 offset += (locals_stack_align - 1);
1152 offset &= ~(locals_stack_align - 1);
1154 while (prev_offset < offset) {
1156 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1159 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1160 cfg->locals_max_stack_offset = - offset;
1162 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1163 * have locals larger than 8 bytes we need to make sure that
1164 * they have the appropriate offset.
1166 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1167 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1168 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1169 if (offsets [i] != -1) {
1170 MonoInst *inst = cfg->varinfo [i];
1171 inst->opcode = OP_REGOFFSET;
1172 inst->inst_basereg = X86_EBP;
1173 inst->inst_offset = - (offset + offsets [i]);
1174 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1177 offset += locals_stack_size;
1181 * Allocate arguments+return value
1184 switch (cinfo->ret.storage) {
1186 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
1188 * In the new IR, the cfg->vret_addr variable represents the
1189 * vtype return value.
1191 cfg->vret_addr->opcode = OP_REGOFFSET;
1192 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1193 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1194 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1195 printf ("vret_addr =");
1196 mono_print_ins (cfg->vret_addr);
1199 cfg->ret->opcode = OP_REGOFFSET;
1200 cfg->ret->inst_basereg = X86_EBP;
1201 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1204 case ArgValuetypeInReg:
1207 cfg->ret->opcode = OP_REGVAR;
1208 cfg->ret->inst_c0 = cinfo->ret.reg;
1209 cfg->ret->dreg = cinfo->ret.reg;
1212 case ArgOnFloatFpStack:
1213 case ArgOnDoubleFpStack:
1216 g_assert_not_reached ();
1219 if (sig->call_convention == MONO_CALL_VARARG) {
1220 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1221 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1224 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1225 ArgInfo *ainfo = &cinfo->args [i];
1226 inst = cfg->args [i];
1227 if (inst->opcode != OP_REGVAR) {
1228 inst->opcode = OP_REGOFFSET;
1229 inst->inst_basereg = X86_EBP;
1231 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1234 cfg->stack_offset = offset;
1238 mono_arch_create_vars (MonoCompile *cfg)
1240 MonoMethodSignature *sig;
1243 sig = mono_method_signature (cfg->method);
1245 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1247 if (cinfo->ret.storage == ArgValuetypeInReg)
1248 cfg->ret_var_is_local = TRUE;
1249 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1250 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1253 cfg->arch_eh_jit_info = 1;
1257 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1258 * so we try to do it just once when we have multiple fp arguments in a row.
1259 * We don't use this mechanism generally because for int arguments the generated code
1260 * is slightly bigger and new generation cpus optimize away the dependency chains
1261 * created by push instructions on the esp value.
1262 * fp_arg_setup is the first argument in the execution sequence where the esp register
1265 static G_GNUC_UNUSED int
1266 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1271 for (; start_arg < sig->param_count; ++start_arg) {
1272 t = mini_type_get_underlying_type (NULL, sig->params [start_arg]);
1273 if (!t->byref && t->type == MONO_TYPE_R8) {
1274 fp_space += sizeof (double);
1275 *fp_arg_setup = start_arg;
1284 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1286 MonoMethodSignature *tmp_sig;
1290 * mono_ArgIterator_Setup assumes the signature cookie is
1291 * passed first and all the arguments which were before it are
1292 * passed on the stack after the signature. So compensate by
1293 * passing a different signature.
1295 tmp_sig = mono_metadata_signature_dup (call->signature);
1296 tmp_sig->param_count -= call->signature->sentinelpos;
1297 tmp_sig->sentinelpos = 0;
1298 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1300 if (cfg->compile_aot) {
1301 sig_reg = mono_alloc_ireg (cfg);
1302 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1303 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, sig_reg);
1305 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1311 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1316 LLVMCallInfo *linfo;
1319 n = sig->param_count + sig->hasthis;
1321 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1323 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1326 * LLVM always uses the native ABI while we use our own ABI, the
1327 * only difference is the handling of vtypes:
1328 * - we only pass/receive them in registers in some cases, and only
1329 * in 1 or 2 integer registers.
1331 if (cinfo->ret.storage == ArgValuetypeInReg) {
1333 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1334 cfg->disable_llvm = TRUE;
1338 cfg->exception_message = g_strdup ("vtype ret in call");
1339 cfg->disable_llvm = TRUE;
1341 linfo->ret.storage = LLVMArgVtypeInReg;
1342 for (j = 0; j < 2; ++j)
1343 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1347 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1348 /* Vtype returned using a hidden argument */
1349 linfo->ret.storage = LLVMArgVtypeRetAddr;
1350 linfo->vret_arg_index = cinfo->vret_arg_index;
1353 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage != ArgInIReg) {
1355 cfg->exception_message = g_strdup ("vtype ret in call");
1356 cfg->disable_llvm = TRUE;
1359 for (i = 0; i < n; ++i) {
1360 ainfo = cinfo->args + i;
1362 if (i >= sig->hasthis)
1363 t = sig->params [i - sig->hasthis];
1365 t = &mono_defaults.int_class->byval_arg;
1367 linfo->args [i].storage = LLVMArgNone;
1369 switch (ainfo->storage) {
1371 linfo->args [i].storage = LLVMArgInIReg;
1373 case ArgInDoubleSSEReg:
1374 case ArgInFloatSSEReg:
1375 linfo->args [i].storage = LLVMArgInFPReg;
1378 if (MONO_TYPE_ISSTRUCT (t)) {
1379 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1380 /* LLVM seems to allocate argument space for empty structures too */
1381 linfo->args [i].storage = LLVMArgNone;
1383 linfo->args [i].storage = LLVMArgVtypeByVal;
1385 linfo->args [i].storage = LLVMArgInIReg;
1387 if (t->type == MONO_TYPE_R4)
1388 linfo->args [i].storage = LLVMArgInFPReg;
1389 else if (t->type == MONO_TYPE_R8)
1390 linfo->args [i].storage = LLVMArgInFPReg;
1394 case ArgValuetypeInReg:
1396 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1397 cfg->disable_llvm = TRUE;
1401 cfg->exception_message = g_strdup ("vtype arg");
1402 cfg->disable_llvm = TRUE;
1404 linfo->args [i].storage = LLVMArgVtypeInReg;
1405 for (j = 0; j < 2; ++j)
1406 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1410 cfg->exception_message = g_strdup ("ainfo->storage");
1411 cfg->disable_llvm = TRUE;
1421 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1423 if (cfg->compute_gc_maps) {
1426 /* On x86, the offsets are from the sp value before the start of the call sequence */
1428 t = &mono_defaults.int_class->byval_arg;
1429 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1434 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1437 MonoMethodSignature *sig;
1440 int sentinelpos = 0, sp_offset = 0;
1442 sig = call->signature;
1443 n = sig->param_count + sig->hasthis;
1445 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1447 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1448 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1450 if (cinfo->need_stack_align) {
1451 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1452 arg->dreg = X86_ESP;
1453 arg->sreg1 = X86_ESP;
1454 arg->inst_imm = cinfo->stack_align_amount;
1455 MONO_ADD_INS (cfg->cbb, arg);
1456 for (i = 0; i < cinfo->stack_align_amount; i += sizeof (mgreg_t)) {
1459 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1463 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1464 if (cinfo->ret.storage == ArgValuetypeInReg) {
1466 * Tell the JIT to use a more efficient calling convention: call using
1467 * OP_CALL, compute the result location after the call, and save the
1470 call->vret_in_reg = TRUE;
1472 NULLIFY_INS (call->vret_var);
1476 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1478 /* Handle the case where there are no implicit arguments */
1479 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1480 emit_sig_cookie (cfg, call, cinfo);
1482 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1485 /* Arguments are pushed in the reverse order */
1486 for (i = n - 1; i >= 0; i --) {
1487 ArgInfo *ainfo = cinfo->args + i;
1491 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1492 /* Push the vret arg before the first argument */
1494 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1495 vtarg->type = STACK_MP;
1496 vtarg->sreg1 = call->vret_var->dreg;
1497 MONO_ADD_INS (cfg->cbb, vtarg);
1499 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1502 if (i >= sig->hasthis)
1503 t = sig->params [i - sig->hasthis];
1505 t = &mono_defaults.int_class->byval_arg;
1506 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1508 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1510 in = call->args [i];
1511 arg->cil_code = in->cil_code;
1512 arg->sreg1 = in->dreg;
1513 arg->type = in->type;
1515 g_assert (in->dreg != -1);
1517 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1521 g_assert (in->klass);
1523 if (t->type == MONO_TYPE_TYPEDBYREF) {
1524 size = sizeof (MonoTypedRef);
1525 align = sizeof (gpointer);
1528 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1532 arg->opcode = OP_OUTARG_VT;
1533 arg->sreg1 = in->dreg;
1534 arg->klass = in->klass;
1535 arg->backend.size = size;
1537 MONO_ADD_INS (cfg->cbb, arg);
1539 emit_gc_param_slot_def (cfg, sp_offset, t);
1544 switch (ainfo->storage) {
1546 arg->opcode = OP_X86_PUSH;
1548 if (t->type == MONO_TYPE_R4) {
1549 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1550 arg->opcode = OP_STORER4_MEMBASE_REG;
1551 arg->inst_destbasereg = X86_ESP;
1552 arg->inst_offset = 0;
1554 } else if (t->type == MONO_TYPE_R8) {
1555 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1556 arg->opcode = OP_STORER8_MEMBASE_REG;
1557 arg->inst_destbasereg = X86_ESP;
1558 arg->inst_offset = 0;
1560 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1562 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1568 g_assert_not_reached ();
1571 MONO_ADD_INS (cfg->cbb, arg);
1573 sp_offset += argsize;
1575 if (cfg->compute_gc_maps) {
1577 /* FIXME: The == STACK_OBJ check might be fragile ? */
1578 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ)
1580 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.object_class->byval_arg);
1582 emit_gc_param_slot_def (cfg, sp_offset, t);
1585 for (j = 0; j < argsize; j += 4)
1586 emit_gc_param_slot_def (cfg, sp_offset - j, NULL);
1591 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1592 /* Emit the signature cookie just before the implicit arguments */
1593 emit_sig_cookie (cfg, call, cinfo);
1595 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1599 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1602 if (cinfo->ret.storage == ArgValuetypeInReg) {
1605 else if (cinfo->ret.storage == ArgInIReg) {
1607 /* The return address is passed in a register */
1608 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1609 vtarg->sreg1 = call->inst.dreg;
1610 vtarg->dreg = mono_alloc_ireg (cfg);
1611 MONO_ADD_INS (cfg->cbb, vtarg);
1613 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1614 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1616 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1617 vtarg->type = STACK_MP;
1618 vtarg->sreg1 = call->vret_var->dreg;
1619 MONO_ADD_INS (cfg->cbb, vtarg);
1621 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1624 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1625 if (cinfo->ret.storage != ArgValuetypeInReg)
1626 cinfo->stack_usage -= 4;
1629 call->stack_usage = cinfo->stack_usage;
1630 cfg->arch.param_area_size = MAX (cfg->arch.param_area_size, sp_offset);
1634 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1637 int size = ins->backend.size;
1640 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1641 arg->sreg1 = src->dreg;
1643 MONO_ADD_INS (cfg->cbb, arg);
1644 } else if (size <= 20) {
1645 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1646 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1648 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1649 arg->inst_basereg = src->dreg;
1650 arg->inst_offset = 0;
1651 arg->inst_imm = size;
1653 MONO_ADD_INS (cfg->cbb, arg);
1658 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1660 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1663 if (ret->type == MONO_TYPE_R4) {
1664 if (COMPILE_LLVM (cfg))
1665 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1668 } else if (ret->type == MONO_TYPE_R8) {
1669 if (COMPILE_LLVM (cfg))
1670 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1673 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1674 if (COMPILE_LLVM (cfg))
1675 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1677 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1678 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1684 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1688 * Allow tracing to work with this interface (with an optional argument)
1691 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1695 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1696 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1698 /* if some args are passed in registers, we need to save them here */
1699 x86_push_reg (code, X86_EBP);
1701 if (cfg->compile_aot) {
1702 x86_push_imm (code, cfg->method);
1703 x86_mov_reg_imm (code, X86_EAX, func);
1704 x86_call_reg (code, X86_EAX);
1706 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1707 x86_push_imm (code, cfg->method);
1708 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1709 x86_call_code (code, 0);
1711 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1725 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1728 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1729 MonoMethod *method = cfg->method;
1730 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1732 switch (ret_type->type) {
1733 case MONO_TYPE_VOID:
1734 /* special case string .ctor icall */
1735 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1736 save_mode = SAVE_EAX;
1737 stack_usage = enable_arguments ? 8 : 4;
1739 save_mode = SAVE_NONE;
1743 save_mode = SAVE_EAX_EDX;
1744 stack_usage = enable_arguments ? 16 : 8;
1748 save_mode = SAVE_FP;
1749 stack_usage = enable_arguments ? 16 : 8;
1751 case MONO_TYPE_GENERICINST:
1752 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1753 save_mode = SAVE_EAX;
1754 stack_usage = enable_arguments ? 8 : 4;
1758 case MONO_TYPE_VALUETYPE:
1759 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1760 save_mode = SAVE_STRUCT;
1761 stack_usage = enable_arguments ? 4 : 0;
1764 save_mode = SAVE_EAX;
1765 stack_usage = enable_arguments ? 8 : 4;
1769 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1771 switch (save_mode) {
1773 x86_push_reg (code, X86_EDX);
1774 x86_push_reg (code, X86_EAX);
1775 if (enable_arguments) {
1776 x86_push_reg (code, X86_EDX);
1777 x86_push_reg (code, X86_EAX);
1782 x86_push_reg (code, X86_EAX);
1783 if (enable_arguments) {
1784 x86_push_reg (code, X86_EAX);
1789 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1790 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1791 if (enable_arguments) {
1792 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1793 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1798 if (enable_arguments) {
1799 x86_push_membase (code, X86_EBP, 8);
1808 if (cfg->compile_aot) {
1809 x86_push_imm (code, method);
1810 x86_mov_reg_imm (code, X86_EAX, func);
1811 x86_call_reg (code, X86_EAX);
1813 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1814 x86_push_imm (code, method);
1815 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1816 x86_call_code (code, 0);
1819 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1821 switch (save_mode) {
1823 x86_pop_reg (code, X86_EAX);
1824 x86_pop_reg (code, X86_EDX);
1827 x86_pop_reg (code, X86_EAX);
1830 x86_fld_membase (code, X86_ESP, 0, TRUE);
1831 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1838 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1843 #define EMIT_COND_BRANCH(ins,cond,sign) \
1844 if (ins->inst_true_bb->native_offset) { \
1845 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1847 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1848 if ((cfg->opt & MONO_OPT_BRANCH) && \
1849 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1850 x86_branch8 (code, cond, 0, sign); \
1852 x86_branch32 (code, cond, 0, sign); \
1856 * Emit an exception if condition is fail and
1857 * if possible do a directly branch to target
1859 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1861 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1862 if (tins == NULL) { \
1863 mono_add_patch_info (cfg, code - cfg->native_code, \
1864 MONO_PATCH_INFO_EXC, exc_name); \
1865 x86_branch32 (code, cond, 0, signed); \
1867 EMIT_COND_BRANCH (tins, cond, signed); \
1871 #define EMIT_FPCOMPARE(code) do { \
1872 x86_fcompp (code); \
1873 x86_fnstsw (code); \
1878 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1880 gboolean needs_paddings = TRUE;
1883 if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
1885 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1887 if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && strstr (cfg->method->name, info->name))
1888 needs_paddings = FALSE; /* A call to the wrapped function */
1892 if (cfg->compile_aot)
1893 needs_paddings = FALSE;
1894 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1895 This is required for code patching to be safe on SMP machines.
1897 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1898 #ifndef __native_client_codegen__
1899 if (needs_paddings && pad_size)
1900 x86_padding (code, 4 - pad_size);
1903 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1904 x86_call_code (code, 0);
1909 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1912 * mono_peephole_pass_1:
1914 * Perform peephole opts which should/can be performed before local regalloc
1917 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1921 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1922 MonoInst *last_ins = ins->prev;
1924 switch (ins->opcode) {
1927 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1929 * X86_LEA is like ADD, but doesn't have the
1930 * sreg1==dreg restriction.
1932 ins->opcode = OP_X86_LEA_MEMBASE;
1933 ins->inst_basereg = ins->sreg1;
1934 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1935 ins->opcode = OP_X86_INC_REG;
1939 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1940 ins->opcode = OP_X86_LEA_MEMBASE;
1941 ins->inst_basereg = ins->sreg1;
1942 ins->inst_imm = -ins->inst_imm;
1943 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1944 ins->opcode = OP_X86_DEC_REG;
1946 case OP_COMPARE_IMM:
1947 case OP_ICOMPARE_IMM:
1948 /* OP_COMPARE_IMM (reg, 0)
1950 * OP_X86_TEST_NULL (reg)
1953 ins->opcode = OP_X86_TEST_NULL;
1955 case OP_X86_COMPARE_MEMBASE_IMM:
1957 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1958 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1960 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1961 * OP_COMPARE_IMM reg, imm
1963 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1965 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1966 ins->inst_basereg == last_ins->inst_destbasereg &&
1967 ins->inst_offset == last_ins->inst_offset) {
1968 ins->opcode = OP_COMPARE_IMM;
1969 ins->sreg1 = last_ins->sreg1;
1971 /* check if we can remove cmp reg,0 with test null */
1973 ins->opcode = OP_X86_TEST_NULL;
1977 case OP_X86_PUSH_MEMBASE:
1978 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1979 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1980 ins->inst_basereg == last_ins->inst_destbasereg &&
1981 ins->inst_offset == last_ins->inst_offset) {
1982 ins->opcode = OP_X86_PUSH;
1983 ins->sreg1 = last_ins->sreg1;
1988 mono_peephole_ins (bb, ins);
1993 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1997 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1998 switch (ins->opcode) {
2000 /* reg = 0 -> XOR (reg, reg) */
2001 /* XOR sets cflags on x86, so we cant do it always */
2002 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2005 ins->opcode = OP_IXOR;
2006 ins->sreg1 = ins->dreg;
2007 ins->sreg2 = ins->dreg;
2010 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2011 * since it takes 3 bytes instead of 7.
2013 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2014 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2015 ins2->opcode = OP_STORE_MEMBASE_REG;
2016 ins2->sreg1 = ins->dreg;
2018 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2019 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2020 ins2->sreg1 = ins->dreg;
2022 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2023 /* Continue iteration */
2032 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2033 ins->opcode = OP_X86_INC_REG;
2037 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2038 ins->opcode = OP_X86_DEC_REG;
2042 mono_peephole_ins (bb, ins);
2047 * mono_arch_lowering_pass:
2049 * Converts complex opcodes into simpler ones so that each IR instruction
2050 * corresponds to one machine instruction.
2053 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2055 MonoInst *ins, *next;
2058 * FIXME: Need to add more instructions, but the current machine
2059 * description can't model some parts of the composite instructions like
2062 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2063 switch (ins->opcode) {
2066 case OP_IDIV_UN_IMM:
2067 case OP_IREM_UN_IMM:
2069 * Keep the cases where we could generated optimized code, otherwise convert
2070 * to the non-imm variant.
2072 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2074 mono_decompose_op_imm (cfg, bb, ins);
2081 bb->max_vreg = cfg->next_vreg;
2085 branch_cc_table [] = {
2086 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2087 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2088 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2091 /* Maps CMP_... constants to X86_CC_... constants */
2094 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2095 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2099 cc_signed_table [] = {
2100 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2101 FALSE, FALSE, FALSE, FALSE
2104 static unsigned char*
2105 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2107 #define XMM_TEMP_REG 0
2108 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2109 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2110 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2111 /* optimize by assigning a local var for this use so we avoid
2112 * the stack manipulations */
2113 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2114 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2115 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2116 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2117 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2119 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2121 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2124 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2125 x86_fnstcw_membase(code, X86_ESP, 0);
2126 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2127 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2128 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2129 x86_fldcw_membase (code, X86_ESP, 2);
2131 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2132 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2133 x86_pop_reg (code, dreg);
2134 /* FIXME: need the high register
2135 * x86_pop_reg (code, dreg_high);
2138 x86_push_reg (code, X86_EAX); // SP = SP - 4
2139 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2140 x86_pop_reg (code, dreg);
2142 x86_fldcw_membase (code, X86_ESP, 0);
2143 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2146 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2148 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2152 static unsigned char*
2153 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2155 int sreg = tree->sreg1;
2156 int need_touch = FALSE;
2158 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2167 * If requested stack size is larger than one page,
2168 * perform stack-touch operation
2171 * Generate stack probe code.
2172 * Under Windows, it is necessary to allocate one page at a time,
2173 * "touching" stack after each successful sub-allocation. This is
2174 * because of the way stack growth is implemented - there is a
2175 * guard page before the lowest stack page that is currently commited.
2176 * Stack normally grows sequentially so OS traps access to the
2177 * guard page and commits more pages when needed.
2179 x86_test_reg_imm (code, sreg, ~0xFFF);
2180 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2182 br[2] = code; /* loop */
2183 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2184 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2187 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2188 * that follows only initializes the last part of the area.
2190 /* Same as the init code below with size==0x1000 */
2191 if (tree->flags & MONO_INST_INIT) {
2192 x86_push_reg (code, X86_EAX);
2193 x86_push_reg (code, X86_ECX);
2194 x86_push_reg (code, X86_EDI);
2195 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2196 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2197 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2199 x86_prefix (code, X86_REP_PREFIX);
2201 x86_pop_reg (code, X86_EDI);
2202 x86_pop_reg (code, X86_ECX);
2203 x86_pop_reg (code, X86_EAX);
2206 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2207 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2208 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2209 x86_patch (br[3], br[2]);
2210 x86_test_reg_reg (code, sreg, sreg);
2211 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2212 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2214 br[1] = code; x86_jump8 (code, 0);
2216 x86_patch (br[0], code);
2217 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2218 x86_patch (br[1], code);
2219 x86_patch (br[4], code);
2222 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2224 if (tree->flags & MONO_INST_INIT) {
2226 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2227 x86_push_reg (code, X86_EAX);
2230 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2231 x86_push_reg (code, X86_ECX);
2234 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2235 x86_push_reg (code, X86_EDI);
2239 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2240 if (sreg != X86_ECX)
2241 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2242 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2244 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2246 x86_prefix (code, X86_REP_PREFIX);
2249 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2250 x86_pop_reg (code, X86_EDI);
2251 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2252 x86_pop_reg (code, X86_ECX);
2253 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2254 x86_pop_reg (code, X86_EAX);
2261 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2263 /* Move return value to the target register */
2264 switch (ins->opcode) {
2267 case OP_CALL_MEMBASE:
2268 if (ins->dreg != X86_EAX)
2269 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2279 static int tls_gs_offset;
2283 mono_x86_have_tls_get (void)
2286 static gboolean have_tls_get = FALSE;
2287 static gboolean inited = FALSE;
2291 return have_tls_get;
2293 ins = (guint32*)pthread_getspecific;
2295 * We're looking for these two instructions:
2297 * mov 0x4(%esp),%eax
2298 * mov %gs:[offset](,%eax,4),%eax
2300 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2301 tls_gs_offset = ins [2];
2305 return have_tls_get;
2306 #elif defined(TARGET_ANDROID)
2314 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2316 #if defined(__APPLE__)
2317 x86_prefix (code, X86_GS_PREFIX);
2318 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2319 #elif defined(TARGET_WIN32)
2320 g_assert_not_reached ();
2322 x86_prefix (code, X86_GS_PREFIX);
2323 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2329 * mono_x86_emit_tls_get:
2330 * @code: buffer to store code to
2331 * @dreg: hard register where to place the result
2332 * @tls_offset: offset info
2334 * mono_x86_emit_tls_get emits in @code the native code that puts in
2335 * the dreg register the item in the thread local storage identified
2338 * Returns: a pointer to the end of the stored code
2341 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2343 #if defined(__APPLE__)
2344 x86_prefix (code, X86_GS_PREFIX);
2345 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2346 #elif defined(TARGET_WIN32)
2348 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2349 * Journal and/or a disassembly of the TlsGet () function.
2351 g_assert (tls_offset < 64);
2352 x86_prefix (code, X86_FS_PREFIX);
2353 x86_mov_reg_mem (code, dreg, 0x18, 4);
2354 /* Dunno what this does but TlsGetValue () contains it */
2355 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2356 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2358 if (optimize_for_xen) {
2359 x86_prefix (code, X86_GS_PREFIX);
2360 x86_mov_reg_mem (code, dreg, 0, 4);
2361 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2363 x86_prefix (code, X86_GS_PREFIX);
2364 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2371 * emit_load_volatile_arguments:
2373 * Load volatile arguments from the stack to the original input registers.
2374 * Required before a tail call.
2377 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2379 MonoMethod *method = cfg->method;
2380 MonoMethodSignature *sig;
2385 /* FIXME: Generate intermediate code instead */
2387 sig = mono_method_signature (method);
2389 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2391 /* This is the opposite of the code in emit_prolog */
2393 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2394 ArgInfo *ainfo = cinfo->args + i;
2396 inst = cfg->args [i];
2398 if (sig->hasthis && (i == 0))
2399 arg_type = &mono_defaults.object_class->byval_arg;
2401 arg_type = sig->params [i - sig->hasthis];
2404 * On x86, the arguments are either in their original stack locations, or in
2407 if (inst->opcode == OP_REGVAR) {
2408 g_assert (ainfo->storage == ArgOnStack);
2410 x86_mov_membase_reg (code, X86_EBP, inst->inst_offset, inst->dreg, 4);
2417 #define REAL_PRINT_REG(text,reg) \
2418 mono_assert (reg >= 0); \
2419 x86_push_reg (code, X86_EAX); \
2420 x86_push_reg (code, X86_EDX); \
2421 x86_push_reg (code, X86_ECX); \
2422 x86_push_reg (code, reg); \
2423 x86_push_imm (code, reg); \
2424 x86_push_imm (code, text " %d %p\n"); \
2425 x86_mov_reg_imm (code, X86_EAX, printf); \
2426 x86_call_reg (code, X86_EAX); \
2427 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2428 x86_pop_reg (code, X86_ECX); \
2429 x86_pop_reg (code, X86_EDX); \
2430 x86_pop_reg (code, X86_EAX);
2432 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2433 #ifdef __native__client_codegen__
2434 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2437 /* benchmark and set based on cpu */
2438 #define LOOP_ALIGNMENT 8
2439 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2443 #if defined(__native_client__) || defined(__native_client_codegen__)
2447 #ifdef __native_client_gc__
2448 __nacl_suspend_thread_if_needed();
2454 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2459 guint8 *code = cfg->native_code + cfg->code_len;
2462 if (cfg->opt & MONO_OPT_LOOP) {
2463 int pad, align = LOOP_ALIGNMENT;
2464 /* set alignment depending on cpu */
2465 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2467 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2468 x86_padding (code, pad);
2469 cfg->code_len += pad;
2470 bb->native_offset = cfg->code_len;
2473 #ifdef __native_client_codegen__
2475 /* For Native Client, all indirect call/jump targets must be */
2476 /* 32-byte aligned. Exception handler blocks are jumped to */
2477 /* indirectly as well. */
2478 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2479 (bb->flags & BB_EXCEPTION_HANDLER);
2481 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2482 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2483 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2484 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2485 cfg->code_len += pad;
2486 bb->native_offset = cfg->code_len;
2489 #endif /* __native_client_codegen__ */
2490 if (cfg->verbose_level > 2)
2491 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2493 cpos = bb->max_offset;
2495 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2496 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2497 g_assert (!cfg->compile_aot);
2500 cov->data [bb->dfn].cil_code = bb->cil_code;
2501 /* this is not thread save, but good enough */
2502 x86_inc_mem (code, &cov->data [bb->dfn].count);
2505 offset = code - cfg->native_code;
2507 mono_debug_open_block (cfg, bb, offset);
2509 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2510 x86_breakpoint (code);
2512 MONO_BB_FOR_EACH_INS (bb, ins) {
2513 offset = code - cfg->native_code;
2515 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2517 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2519 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2520 cfg->code_size *= 2;
2521 cfg->native_code = mono_realloc_native_code(cfg);
2522 code = cfg->native_code + offset;
2523 cfg->stat_code_reallocs++;
2526 if (cfg->debug_info)
2527 mono_debug_record_line_number (cfg, ins, offset);
2529 switch (ins->opcode) {
2531 x86_mul_reg (code, ins->sreg2, TRUE);
2534 x86_mul_reg (code, ins->sreg2, FALSE);
2536 case OP_X86_SETEQ_MEMBASE:
2537 case OP_X86_SETNE_MEMBASE:
2538 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2539 ins->inst_basereg, ins->inst_offset, TRUE);
2541 case OP_STOREI1_MEMBASE_IMM:
2542 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2544 case OP_STOREI2_MEMBASE_IMM:
2545 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2547 case OP_STORE_MEMBASE_IMM:
2548 case OP_STOREI4_MEMBASE_IMM:
2549 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2551 case OP_STOREI1_MEMBASE_REG:
2552 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2554 case OP_STOREI2_MEMBASE_REG:
2555 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2557 case OP_STORE_MEMBASE_REG:
2558 case OP_STOREI4_MEMBASE_REG:
2559 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2561 case OP_STORE_MEM_IMM:
2562 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2565 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2569 /* These are created by the cprop pass so they use inst_imm as the source */
2570 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2573 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2576 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2578 case OP_LOAD_MEMBASE:
2579 case OP_LOADI4_MEMBASE:
2580 case OP_LOADU4_MEMBASE:
2581 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2583 case OP_LOADU1_MEMBASE:
2584 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2586 case OP_LOADI1_MEMBASE:
2587 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2589 case OP_LOADU2_MEMBASE:
2590 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2592 case OP_LOADI2_MEMBASE:
2593 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2595 case OP_ICONV_TO_I1:
2597 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2599 case OP_ICONV_TO_I2:
2601 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2603 case OP_ICONV_TO_U1:
2604 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2606 case OP_ICONV_TO_U2:
2607 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2611 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2613 case OP_COMPARE_IMM:
2614 case OP_ICOMPARE_IMM:
2615 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2617 case OP_X86_COMPARE_MEMBASE_REG:
2618 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2620 case OP_X86_COMPARE_MEMBASE_IMM:
2621 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2623 case OP_X86_COMPARE_MEMBASE8_IMM:
2624 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2626 case OP_X86_COMPARE_REG_MEMBASE:
2627 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2629 case OP_X86_COMPARE_MEM_IMM:
2630 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2632 case OP_X86_TEST_NULL:
2633 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2635 case OP_X86_ADD_MEMBASE_IMM:
2636 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2638 case OP_X86_ADD_REG_MEMBASE:
2639 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2641 case OP_X86_SUB_MEMBASE_IMM:
2642 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2644 case OP_X86_SUB_REG_MEMBASE:
2645 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2647 case OP_X86_AND_MEMBASE_IMM:
2648 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2650 case OP_X86_OR_MEMBASE_IMM:
2651 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2653 case OP_X86_XOR_MEMBASE_IMM:
2654 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2656 case OP_X86_ADD_MEMBASE_REG:
2657 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2659 case OP_X86_SUB_MEMBASE_REG:
2660 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2662 case OP_X86_AND_MEMBASE_REG:
2663 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2665 case OP_X86_OR_MEMBASE_REG:
2666 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2668 case OP_X86_XOR_MEMBASE_REG:
2669 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2671 case OP_X86_INC_MEMBASE:
2672 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2674 case OP_X86_INC_REG:
2675 x86_inc_reg (code, ins->dreg);
2677 case OP_X86_DEC_MEMBASE:
2678 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2680 case OP_X86_DEC_REG:
2681 x86_dec_reg (code, ins->dreg);
2683 case OP_X86_MUL_REG_MEMBASE:
2684 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2686 case OP_X86_AND_REG_MEMBASE:
2687 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2689 case OP_X86_OR_REG_MEMBASE:
2690 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2692 case OP_X86_XOR_REG_MEMBASE:
2693 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2696 x86_breakpoint (code);
2698 case OP_RELAXED_NOP:
2699 x86_prefix (code, X86_REP_PREFIX);
2707 case OP_DUMMY_STORE:
2708 case OP_NOT_REACHED:
2711 case OP_SEQ_POINT: {
2714 if (cfg->compile_aot)
2718 * Read from the single stepping trigger page. This will cause a
2719 * SIGSEGV when single stepping is enabled.
2720 * We do this _before_ the breakpoint, so single stepping after
2721 * a breakpoint is hit will step to the next IL offset.
2723 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2724 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2726 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2729 * A placeholder for a possible breakpoint inserted by
2730 * mono_arch_set_breakpoint ().
2732 for (i = 0; i < 6; ++i)
2735 * Add an additional nop so skipping the bp doesn't cause the ip to point
2736 * to another IL offset.
2744 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2748 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2753 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2757 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2762 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2766 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2771 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2775 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2778 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2782 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2787 * The code is the same for div/rem, the allocator will allocate dreg
2788 * to RAX/RDX as appropriate.
2790 if (ins->sreg2 == X86_EDX) {
2791 /* cdq clobbers this */
2792 x86_push_reg (code, ins->sreg2);
2794 x86_div_membase (code, X86_ESP, 0, TRUE);
2795 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2798 x86_div_reg (code, ins->sreg2, TRUE);
2803 if (ins->sreg2 == X86_EDX) {
2804 x86_push_reg (code, ins->sreg2);
2805 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2806 x86_div_membase (code, X86_ESP, 0, FALSE);
2807 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2809 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2810 x86_div_reg (code, ins->sreg2, FALSE);
2814 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2816 x86_div_reg (code, ins->sreg2, TRUE);
2819 int power = mono_is_power_of_two (ins->inst_imm);
2821 g_assert (ins->sreg1 == X86_EAX);
2822 g_assert (ins->dreg == X86_EAX);
2823 g_assert (power >= 0);
2826 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2828 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2830 * If the divident is >= 0, this does not nothing. If it is positive, it
2831 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2833 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2834 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2835 } else if (power == 0) {
2836 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2838 /* Based on gcc code */
2840 /* Add compensation for negative dividents */
2842 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2843 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2844 /* Compute remainder */
2845 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2846 /* Remove compensation */
2847 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2852 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2856 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2859 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2863 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2866 g_assert (ins->sreg2 == X86_ECX);
2867 x86_shift_reg (code, X86_SHL, ins->dreg);
2870 g_assert (ins->sreg2 == X86_ECX);
2871 x86_shift_reg (code, X86_SAR, ins->dreg);
2875 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2878 case OP_ISHR_UN_IMM:
2879 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2882 g_assert (ins->sreg2 == X86_ECX);
2883 x86_shift_reg (code, X86_SHR, ins->dreg);
2887 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2890 guint8 *jump_to_end;
2892 /* handle shifts below 32 bits */
2893 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2894 x86_shift_reg (code, X86_SHL, ins->sreg1);
2896 x86_test_reg_imm (code, X86_ECX, 32);
2897 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2899 /* handle shift over 32 bit */
2900 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2901 x86_clear_reg (code, ins->sreg1);
2903 x86_patch (jump_to_end, code);
2907 guint8 *jump_to_end;
2909 /* handle shifts below 32 bits */
2910 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2911 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2913 x86_test_reg_imm (code, X86_ECX, 32);
2914 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2916 /* handle shifts over 31 bits */
2917 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2918 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2920 x86_patch (jump_to_end, code);
2924 guint8 *jump_to_end;
2926 /* handle shifts below 32 bits */
2927 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2928 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2930 x86_test_reg_imm (code, X86_ECX, 32);
2931 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2933 /* handle shifts over 31 bits */
2934 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2935 x86_clear_reg (code, ins->backend.reg3);
2937 x86_patch (jump_to_end, code);
2941 if (ins->inst_imm >= 32) {
2942 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2943 x86_clear_reg (code, ins->sreg1);
2944 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2946 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2947 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2951 if (ins->inst_imm >= 32) {
2952 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2953 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2954 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2956 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2957 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
2960 case OP_LSHR_UN_IMM:
2961 if (ins->inst_imm >= 32) {
2962 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2963 x86_clear_reg (code, ins->backend.reg3);
2964 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2966 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2967 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
2971 x86_not_reg (code, ins->sreg1);
2974 x86_neg_reg (code, ins->sreg1);
2978 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2982 switch (ins->inst_imm) {
2986 if (ins->dreg != ins->sreg1)
2987 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2988 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2991 /* LEA r1, [r2 + r2*2] */
2992 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2995 /* LEA r1, [r2 + r2*4] */
2996 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2999 /* LEA r1, [r2 + r2*2] */
3001 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3002 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3005 /* LEA r1, [r2 + r2*8] */
3006 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3009 /* LEA r1, [r2 + r2*4] */
3011 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3012 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3015 /* LEA r1, [r2 + r2*2] */
3017 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3018 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3021 /* LEA r1, [r2 + r2*4] */
3022 /* LEA r1, [r1 + r1*4] */
3023 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3024 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3027 /* LEA r1, [r2 + r2*4] */
3029 /* LEA r1, [r1 + r1*4] */
3030 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3031 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3032 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3035 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3040 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3041 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3043 case OP_IMUL_OVF_UN: {
3044 /* the mul operation and the exception check should most likely be split */
3045 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3046 /*g_assert (ins->sreg2 == X86_EAX);
3047 g_assert (ins->dreg == X86_EAX);*/
3048 if (ins->sreg2 == X86_EAX) {
3049 non_eax_reg = ins->sreg1;
3050 } else if (ins->sreg1 == X86_EAX) {
3051 non_eax_reg = ins->sreg2;
3053 /* no need to save since we're going to store to it anyway */
3054 if (ins->dreg != X86_EAX) {
3056 x86_push_reg (code, X86_EAX);
3058 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3059 non_eax_reg = ins->sreg2;
3061 if (ins->dreg == X86_EDX) {
3064 x86_push_reg (code, X86_EAX);
3066 } else if (ins->dreg != X86_EAX) {
3068 x86_push_reg (code, X86_EDX);
3070 x86_mul_reg (code, non_eax_reg, FALSE);
3071 /* save before the check since pop and mov don't change the flags */
3072 if (ins->dreg != X86_EAX)
3073 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3075 x86_pop_reg (code, X86_EDX);
3077 x86_pop_reg (code, X86_EAX);
3078 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3082 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3085 g_assert_not_reached ();
3086 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3087 x86_mov_reg_imm (code, ins->dreg, 0);
3090 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3091 x86_mov_reg_imm (code, ins->dreg, 0);
3093 case OP_LOAD_GOTADDR:
3094 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3095 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3098 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3099 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3101 case OP_X86_PUSH_GOT_ENTRY:
3102 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3103 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3106 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3110 * Note: this 'frame destruction' logic is useful for tail calls, too.
3111 * Keep in sync with the code in emit_epilog.
3115 /* FIXME: no tracing support... */
3116 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3117 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3118 /* reset offset to make max_len work */
3119 offset = code - cfg->native_code;
3121 g_assert (!cfg->method->save_lmf);
3123 code = emit_load_volatile_arguments (cfg, code);
3125 if (cfg->used_int_regs & (1 << X86_EBX))
3127 if (cfg->used_int_regs & (1 << X86_EDI))
3129 if (cfg->used_int_regs & (1 << X86_ESI))
3132 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
3134 if (cfg->used_int_regs & (1 << X86_ESI))
3135 x86_pop_reg (code, X86_ESI);
3136 if (cfg->used_int_regs & (1 << X86_EDI))
3137 x86_pop_reg (code, X86_EDI);
3138 if (cfg->used_int_regs & (1 << X86_EBX))
3139 x86_pop_reg (code, X86_EBX);
3141 /* restore ESP/EBP */
3143 offset = code - cfg->native_code;
3144 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3145 x86_jump32 (code, 0);
3147 cfg->disable_aot = TRUE;
3151 MonoCallInst *call = (MonoCallInst*)ins;
3154 /* FIXME: no tracing support... */
3155 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3156 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3157 /* reset offset to make max_len work */
3158 offset = code - cfg->native_code;
3160 g_assert (!cfg->method->save_lmf);
3162 //code = emit_load_volatile_arguments (cfg, code);
3164 /* restore callee saved registers */
3165 for (i = 0; i < X86_NREG; ++i)
3166 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3168 if (cfg->used_int_regs & (1 << X86_ESI)) {
3169 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3172 if (cfg->used_int_regs & (1 << X86_EDI)) {
3173 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3176 if (cfg->used_int_regs & (1 << X86_EBX)) {
3177 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3181 /* Copy arguments on the stack to our argument area */
3182 for (i = 0; i < call->stack_usage; i += 4) {
3183 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3184 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3187 /* restore ESP/EBP */
3189 offset = code - cfg->native_code;
3190 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3191 x86_jump32 (code, 0);
3193 ins->flags |= MONO_INST_GC_CALLSITE;
3194 cfg->disable_aot = TRUE;
3198 /* ensure ins->sreg1 is not NULL
3199 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3200 * cmp DWORD PTR [eax], 0
3202 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3205 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3206 x86_push_reg (code, hreg);
3207 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3208 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3209 x86_pop_reg (code, hreg);
3218 call = (MonoCallInst*)ins;
3219 if (ins->flags & MONO_INST_HAS_METHOD)
3220 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3222 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3223 ins->flags |= MONO_INST_GC_CALLSITE;
3224 ins->backend.pc_offset = code - cfg->native_code;
3225 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3226 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
3227 * bytes to pop, we want to use pops. GCC does this (note it won't happen
3228 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
3229 * smart enough to do that optimization yet
3231 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
3232 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
3233 * (most likely from locality benefits). People with other processors should
3234 * check on theirs to see what happens.
3236 if (call->stack_usage == 4) {
3237 /* we want to use registers that won't get used soon, so use
3238 * ecx, as eax will get allocated first. edx is used by long calls,
3239 * so we can't use that.
3242 x86_pop_reg (code, X86_ECX);
3244 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3247 code = emit_move_return_value (cfg, ins, code);
3253 case OP_VOIDCALL_REG:
3255 call = (MonoCallInst*)ins;
3256 x86_call_reg (code, ins->sreg1);
3257 ins->flags |= MONO_INST_GC_CALLSITE;
3258 ins->backend.pc_offset = code - cfg->native_code;
3259 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3260 if (call->stack_usage == 4)
3261 x86_pop_reg (code, X86_ECX);
3263 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3265 code = emit_move_return_value (cfg, ins, code);
3267 case OP_FCALL_MEMBASE:
3268 case OP_LCALL_MEMBASE:
3269 case OP_VCALL_MEMBASE:
3270 case OP_VCALL2_MEMBASE:
3271 case OP_VOIDCALL_MEMBASE:
3272 case OP_CALL_MEMBASE:
3273 call = (MonoCallInst*)ins;
3275 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3276 ins->flags |= MONO_INST_GC_CALLSITE;
3277 ins->backend.pc_offset = code - cfg->native_code;
3278 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3279 if (call->stack_usage == 4)
3280 x86_pop_reg (code, X86_ECX);
3282 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3284 code = emit_move_return_value (cfg, ins, code);
3287 x86_push_reg (code, ins->sreg1);
3289 case OP_X86_PUSH_IMM:
3290 x86_push_imm (code, ins->inst_imm);
3292 case OP_X86_PUSH_MEMBASE:
3293 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
3295 case OP_X86_PUSH_OBJ:
3296 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
3297 x86_push_reg (code, X86_EDI);
3298 x86_push_reg (code, X86_ESI);
3299 x86_push_reg (code, X86_ECX);
3300 if (ins->inst_offset)
3301 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
3303 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
3304 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
3305 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
3307 x86_prefix (code, X86_REP_PREFIX);
3309 x86_pop_reg (code, X86_ECX);
3310 x86_pop_reg (code, X86_ESI);
3311 x86_pop_reg (code, X86_EDI);
3314 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3316 case OP_X86_LEA_MEMBASE:
3317 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3320 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3323 /* keep alignment */
3324 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3325 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3326 code = mono_emit_stack_alloc (code, ins);
3327 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3329 case OP_LOCALLOC_IMM: {
3330 guint32 size = ins->inst_imm;
3331 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3333 if (ins->flags & MONO_INST_INIT) {
3334 /* FIXME: Optimize this */
3335 x86_mov_reg_imm (code, ins->dreg, size);
3336 ins->sreg1 = ins->dreg;
3338 code = mono_emit_stack_alloc (code, ins);
3339 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3341 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3342 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3347 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3348 x86_push_reg (code, ins->sreg1);
3349 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3350 (gpointer)"mono_arch_throw_exception");
3351 ins->flags |= MONO_INST_GC_CALLSITE;
3352 ins->backend.pc_offset = code - cfg->native_code;
3356 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3357 x86_push_reg (code, ins->sreg1);
3358 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3359 (gpointer)"mono_arch_rethrow_exception");
3360 ins->flags |= MONO_INST_GC_CALLSITE;
3361 ins->backend.pc_offset = code - cfg->native_code;
3364 case OP_CALL_HANDLER:
3365 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3366 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3367 x86_call_imm (code, 0);
3368 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3369 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3371 case OP_START_HANDLER: {
3372 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3373 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3376 case OP_ENDFINALLY: {
3377 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3378 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3382 case OP_ENDFILTER: {
3383 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3384 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3385 /* The local allocator will put the result into EAX */
3391 ins->inst_c0 = code - cfg->native_code;
3394 if (ins->inst_target_bb->native_offset) {
3395 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3397 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3398 if ((cfg->opt & MONO_OPT_BRANCH) &&
3399 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3400 x86_jump8 (code, 0);
3402 x86_jump32 (code, 0);
3406 x86_jump_reg (code, ins->sreg1);
3419 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3420 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3422 case OP_COND_EXC_EQ:
3423 case OP_COND_EXC_NE_UN:
3424 case OP_COND_EXC_LT:
3425 case OP_COND_EXC_LT_UN:
3426 case OP_COND_EXC_GT:
3427 case OP_COND_EXC_GT_UN:
3428 case OP_COND_EXC_GE:
3429 case OP_COND_EXC_GE_UN:
3430 case OP_COND_EXC_LE:
3431 case OP_COND_EXC_LE_UN:
3432 case OP_COND_EXC_IEQ:
3433 case OP_COND_EXC_INE_UN:
3434 case OP_COND_EXC_ILT:
3435 case OP_COND_EXC_ILT_UN:
3436 case OP_COND_EXC_IGT:
3437 case OP_COND_EXC_IGT_UN:
3438 case OP_COND_EXC_IGE:
3439 case OP_COND_EXC_IGE_UN:
3440 case OP_COND_EXC_ILE:
3441 case OP_COND_EXC_ILE_UN:
3442 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3444 case OP_COND_EXC_OV:
3445 case OP_COND_EXC_NO:
3447 case OP_COND_EXC_NC:
3448 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3450 case OP_COND_EXC_IOV:
3451 case OP_COND_EXC_INO:
3452 case OP_COND_EXC_IC:
3453 case OP_COND_EXC_INC:
3454 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3466 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3474 case OP_CMOV_INE_UN:
3475 case OP_CMOV_IGE_UN:
3476 case OP_CMOV_IGT_UN:
3477 case OP_CMOV_ILE_UN:
3478 case OP_CMOV_ILT_UN:
3479 g_assert (ins->dreg == ins->sreg1);
3480 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3483 /* floating point opcodes */
3485 double d = *(double *)ins->inst_p0;
3487 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3489 } else if (d == 1.0) {
3492 if (cfg->compile_aot) {
3493 guint32 *val = (guint32*)&d;
3494 x86_push_imm (code, val [1]);
3495 x86_push_imm (code, val [0]);
3496 x86_fld_membase (code, X86_ESP, 0, TRUE);
3497 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3500 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3501 x86_fld (code, NULL, TRUE);
3507 float f = *(float *)ins->inst_p0;
3509 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3511 } else if (f == 1.0) {
3514 if (cfg->compile_aot) {
3515 guint32 val = *(guint32*)&f;
3516 x86_push_imm (code, val);
3517 x86_fld_membase (code, X86_ESP, 0, FALSE);
3518 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3521 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3522 x86_fld (code, NULL, FALSE);
3527 case OP_STORER8_MEMBASE_REG:
3528 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3530 case OP_LOADR8_MEMBASE:
3531 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3533 case OP_STORER4_MEMBASE_REG:
3534 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3536 case OP_LOADR4_MEMBASE:
3537 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3539 case OP_ICONV_TO_R4:
3540 x86_push_reg (code, ins->sreg1);
3541 x86_fild_membase (code, X86_ESP, 0, FALSE);
3542 /* Change precision */
3543 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3544 x86_fld_membase (code, X86_ESP, 0, FALSE);
3545 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3547 case OP_ICONV_TO_R8:
3548 x86_push_reg (code, ins->sreg1);
3549 x86_fild_membase (code, X86_ESP, 0, FALSE);
3550 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3552 case OP_ICONV_TO_R_UN:
3553 x86_push_imm (code, 0);
3554 x86_push_reg (code, ins->sreg1);
3555 x86_fild_membase (code, X86_ESP, 0, TRUE);
3556 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3558 case OP_X86_FP_LOAD_I8:
3559 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3561 case OP_X86_FP_LOAD_I4:
3562 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3564 case OP_FCONV_TO_R4:
3565 /* Change precision */
3566 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3567 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3568 x86_fld_membase (code, X86_ESP, 0, FALSE);
3569 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3571 case OP_FCONV_TO_I1:
3572 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3574 case OP_FCONV_TO_U1:
3575 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3577 case OP_FCONV_TO_I2:
3578 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3580 case OP_FCONV_TO_U2:
3581 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3583 case OP_FCONV_TO_I4:
3585 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3587 case OP_FCONV_TO_I8:
3588 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3589 x86_fnstcw_membase(code, X86_ESP, 0);
3590 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3591 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3592 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3593 x86_fldcw_membase (code, X86_ESP, 2);
3594 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3595 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3596 x86_pop_reg (code, ins->dreg);
3597 x86_pop_reg (code, ins->backend.reg3);
3598 x86_fldcw_membase (code, X86_ESP, 0);
3599 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3601 case OP_LCONV_TO_R8_2:
3602 x86_push_reg (code, ins->sreg2);
3603 x86_push_reg (code, ins->sreg1);
3604 x86_fild_membase (code, X86_ESP, 0, TRUE);
3605 /* Change precision */
3606 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3607 x86_fld_membase (code, X86_ESP, 0, TRUE);
3608 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3610 case OP_LCONV_TO_R4_2:
3611 x86_push_reg (code, ins->sreg2);
3612 x86_push_reg (code, ins->sreg1);
3613 x86_fild_membase (code, X86_ESP, 0, TRUE);
3614 /* Change precision */
3615 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3616 x86_fld_membase (code, X86_ESP, 0, FALSE);
3617 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3619 case OP_LCONV_TO_R_UN_2: {
3620 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3623 /* load 64bit integer to FP stack */
3624 x86_push_reg (code, ins->sreg2);
3625 x86_push_reg (code, ins->sreg1);
3626 x86_fild_membase (code, X86_ESP, 0, TRUE);
3628 /* test if lreg is negative */
3629 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3630 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3632 /* add correction constant mn */
3633 x86_fld80_mem (code, mn);
3634 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3636 x86_patch (br, code);
3638 /* Change precision */
3639 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3640 x86_fld_membase (code, X86_ESP, 0, TRUE);
3642 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3646 case OP_LCONV_TO_OVF_I:
3647 case OP_LCONV_TO_OVF_I4_2: {
3648 guint8 *br [3], *label [1];
3652 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3654 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3656 /* If the low word top bit is set, see if we are negative */
3657 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3658 /* We are not negative (no top bit set, check for our top word to be zero */
3659 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3660 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3663 /* throw exception */
3664 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3666 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3667 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3668 x86_jump8 (code, 0);
3670 x86_jump32 (code, 0);
3672 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3673 x86_jump32 (code, 0);
3677 x86_patch (br [0], code);
3678 /* our top bit is set, check that top word is 0xfffffff */
3679 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3681 x86_patch (br [1], code);
3682 /* nope, emit exception */
3683 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3684 x86_patch (br [2], label [0]);
3686 if (ins->dreg != ins->sreg1)
3687 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3691 /* Not needed on the fp stack */
3694 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3697 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3700 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3703 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3711 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3716 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3723 * it really doesn't make sense to inline all this code,
3724 * it's here just to show that things may not be as simple
3727 guchar *check_pos, *end_tan, *pop_jump;
3728 x86_push_reg (code, X86_EAX);
3731 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3733 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3734 x86_fstp (code, 0); /* pop the 1.0 */
3736 x86_jump8 (code, 0);
3738 x86_fp_op (code, X86_FADD, 0);
3742 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3744 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3747 x86_patch (pop_jump, code);
3748 x86_fstp (code, 0); /* pop the 1.0 */
3749 x86_patch (check_pos, code);
3750 x86_patch (end_tan, code);
3752 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3753 x86_pop_reg (code, X86_EAX);
3760 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3769 g_assert (cfg->opt & MONO_OPT_CMOV);
3770 g_assert (ins->dreg == ins->sreg1);
3771 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3772 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3775 g_assert (cfg->opt & MONO_OPT_CMOV);
3776 g_assert (ins->dreg == ins->sreg1);
3777 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3778 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3781 g_assert (cfg->opt & MONO_OPT_CMOV);
3782 g_assert (ins->dreg == ins->sreg1);
3783 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3784 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3787 g_assert (cfg->opt & MONO_OPT_CMOV);
3788 g_assert (ins->dreg == ins->sreg1);
3789 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3790 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3796 x86_fxch (code, ins->inst_imm);
3801 x86_push_reg (code, X86_EAX);
3802 /* we need to exchange ST(0) with ST(1) */
3805 /* this requires a loop, because fprem somtimes
3806 * returns a partial remainder */
3808 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3809 /* x86_fprem1 (code); */
3812 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3814 x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3819 x86_pop_reg (code, X86_EAX);
3823 if (cfg->opt & MONO_OPT_FCMOV) {
3824 x86_fcomip (code, 1);
3828 /* this overwrites EAX */
3829 EMIT_FPCOMPARE(code);
3830 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3833 if (cfg->opt & MONO_OPT_FCMOV) {
3834 /* zeroing the register at the start results in
3835 * shorter and faster code (we can also remove the widening op)
3837 guchar *unordered_check;
3838 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3839 x86_fcomip (code, 1);
3841 unordered_check = code;
3842 x86_branch8 (code, X86_CC_P, 0, FALSE);
3843 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3844 x86_patch (unordered_check, code);
3847 if (ins->dreg != X86_EAX)
3848 x86_push_reg (code, X86_EAX);
3850 EMIT_FPCOMPARE(code);
3851 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3852 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3853 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3854 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3856 if (ins->dreg != X86_EAX)
3857 x86_pop_reg (code, X86_EAX);
3861 if (cfg->opt & MONO_OPT_FCMOV) {
3862 /* zeroing the register at the start results in
3863 * shorter and faster code (we can also remove the widening op)
3865 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3866 x86_fcomip (code, 1);
3868 if (ins->opcode == OP_FCLT_UN) {
3869 guchar *unordered_check = code;
3870 guchar *jump_to_end;
3871 x86_branch8 (code, X86_CC_P, 0, FALSE);
3872 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3874 x86_jump8 (code, 0);
3875 x86_patch (unordered_check, code);
3876 x86_inc_reg (code, ins->dreg);
3877 x86_patch (jump_to_end, code);
3879 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3883 if (ins->dreg != X86_EAX)
3884 x86_push_reg (code, X86_EAX);
3886 EMIT_FPCOMPARE(code);
3887 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3888 if (ins->opcode == OP_FCLT_UN) {
3889 guchar *is_not_zero_check, *end_jump;
3890 is_not_zero_check = code;
3891 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3893 x86_jump8 (code, 0);
3894 x86_patch (is_not_zero_check, code);
3895 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3897 x86_patch (end_jump, code);
3899 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3900 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3902 if (ins->dreg != X86_EAX)
3903 x86_pop_reg (code, X86_EAX);
3907 if (cfg->opt & MONO_OPT_FCMOV) {
3908 /* zeroing the register at the start results in
3909 * shorter and faster code (we can also remove the widening op)
3911 guchar *unordered_check;
3912 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3913 x86_fcomip (code, 1);
3915 if (ins->opcode == OP_FCGT) {
3916 unordered_check = code;
3917 x86_branch8 (code, X86_CC_P, 0, FALSE);
3918 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3919 x86_patch (unordered_check, code);
3921 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3925 if (ins->dreg != X86_EAX)
3926 x86_push_reg (code, X86_EAX);
3928 EMIT_FPCOMPARE(code);
3929 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3930 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3931 if (ins->opcode == OP_FCGT_UN) {
3932 guchar *is_not_zero_check, *end_jump;
3933 is_not_zero_check = code;
3934 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3936 x86_jump8 (code, 0);
3937 x86_patch (is_not_zero_check, code);
3938 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3940 x86_patch (end_jump, code);
3942 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3943 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3945 if (ins->dreg != X86_EAX)
3946 x86_pop_reg (code, X86_EAX);
3949 if (cfg->opt & MONO_OPT_FCMOV) {
3950 guchar *jump = code;
3951 x86_branch8 (code, X86_CC_P, 0, TRUE);
3952 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3953 x86_patch (jump, code);
3956 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3957 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3960 /* Branch if C013 != 100 */
3961 if (cfg->opt & MONO_OPT_FCMOV) {
3962 /* branch if !ZF or (PF|CF) */
3963 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3964 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3965 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3968 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3969 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3972 if (cfg->opt & MONO_OPT_FCMOV) {
3973 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3976 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3979 if (cfg->opt & MONO_OPT_FCMOV) {
3980 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3981 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3984 if (ins->opcode == OP_FBLT_UN) {
3985 guchar *is_not_zero_check, *end_jump;
3986 is_not_zero_check = code;
3987 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3989 x86_jump8 (code, 0);
3990 x86_patch (is_not_zero_check, code);
3991 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3993 x86_patch (end_jump, code);
3995 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3999 if (cfg->opt & MONO_OPT_FCMOV) {
4000 if (ins->opcode == OP_FBGT) {
4003 /* skip branch if C1=1 */
4005 x86_branch8 (code, X86_CC_P, 0, FALSE);
4006 /* branch if (C0 | C3) = 1 */
4007 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4008 x86_patch (br1, code);
4010 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4014 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4015 if (ins->opcode == OP_FBGT_UN) {
4016 guchar *is_not_zero_check, *end_jump;
4017 is_not_zero_check = code;
4018 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4020 x86_jump8 (code, 0);
4021 x86_patch (is_not_zero_check, code);
4022 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4024 x86_patch (end_jump, code);
4026 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4029 /* Branch if C013 == 100 or 001 */
4030 if (cfg->opt & MONO_OPT_FCMOV) {
4033 /* skip branch if C1=1 */
4035 x86_branch8 (code, X86_CC_P, 0, FALSE);
4036 /* branch if (C0 | C3) = 1 */
4037 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4038 x86_patch (br1, code);
4041 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4042 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4043 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4044 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4047 /* Branch if C013 == 000 */
4048 if (cfg->opt & MONO_OPT_FCMOV) {
4049 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4052 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4055 /* Branch if C013=000 or 100 */
4056 if (cfg->opt & MONO_OPT_FCMOV) {
4059 /* skip branch if C1=1 */
4061 x86_branch8 (code, X86_CC_P, 0, FALSE);
4062 /* branch if C0=0 */
4063 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4064 x86_patch (br1, code);
4067 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4068 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4069 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4072 /* Branch if C013 != 001 */
4073 if (cfg->opt & MONO_OPT_FCMOV) {
4074 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4075 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4078 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4079 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4083 x86_push_reg (code, X86_EAX);
4086 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4087 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4088 x86_pop_reg (code, X86_EAX);
4090 /* Have to clean up the fp stack before throwing the exception */
4092 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4095 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4097 x86_patch (br1, code);
4101 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4104 case OP_MEMORY_BARRIER: {
4105 /* x86 only needs barrier for StoreLoad and FullBarrier */
4106 switch (ins->backend.memory_barrier_kind) {
4107 case StoreLoadBarrier:
4109 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4110 x86_prefix (code, X86_LOCK_PREFIX);
4111 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4116 case OP_ATOMIC_ADD_I4: {
4117 int dreg = ins->dreg;
4119 if (dreg == ins->inst_basereg) {
4120 x86_push_reg (code, ins->sreg2);
4124 if (dreg != ins->sreg2)
4125 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
4127 x86_prefix (code, X86_LOCK_PREFIX);
4128 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4130 if (dreg != ins->dreg) {
4131 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4132 x86_pop_reg (code, dreg);
4137 case OP_ATOMIC_ADD_NEW_I4: {
4138 int dreg = ins->dreg;
4140 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4141 if (ins->sreg2 == dreg) {
4142 if (dreg == X86_EBX) {
4144 if (ins->inst_basereg == X86_EDI)
4148 if (ins->inst_basereg == X86_EBX)
4151 } else if (ins->inst_basereg == dreg) {
4152 if (dreg == X86_EBX) {
4154 if (ins->sreg2 == X86_EDI)
4158 if (ins->sreg2 == X86_EBX)
4163 if (dreg != ins->dreg) {
4164 x86_push_reg (code, dreg);
4167 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4168 x86_prefix (code, X86_LOCK_PREFIX);
4169 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4170 /* dreg contains the old value, add with sreg2 value */
4171 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4173 if (ins->dreg != dreg) {
4174 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4175 x86_pop_reg (code, dreg);
4180 case OP_ATOMIC_EXCHANGE_I4: {
4182 int sreg2 = ins->sreg2;
4183 int breg = ins->inst_basereg;
4185 /* cmpxchg uses eax as comperand, need to make sure we can use it
4186 * hack to overcome limits in x86 reg allocator
4187 * (req: dreg == eax and sreg2 != eax and breg != eax)
4189 g_assert (ins->dreg == X86_EAX);
4191 /* We need the EAX reg for the cmpxchg */
4192 if (ins->sreg2 == X86_EAX) {
4193 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4194 x86_push_reg (code, sreg2);
4195 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4198 if (breg == X86_EAX) {
4199 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4200 x86_push_reg (code, breg);
4201 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4204 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4206 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4207 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4208 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4209 x86_patch (br [1], br [0]);
4211 if (breg != ins->inst_basereg)
4212 x86_pop_reg (code, breg);
4214 if (ins->sreg2 != sreg2)
4215 x86_pop_reg (code, sreg2);
4219 case OP_ATOMIC_CAS_I4: {
4220 g_assert (ins->dreg == X86_EAX);
4221 g_assert (ins->sreg3 == X86_EAX);
4222 g_assert (ins->sreg1 != X86_EAX);
4223 g_assert (ins->sreg1 != ins->sreg2);
4225 x86_prefix (code, X86_LOCK_PREFIX);
4226 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4229 case OP_CARD_TABLE_WBARRIER: {
4230 int ptr = ins->sreg1;
4231 int value = ins->sreg2;
4233 int nursery_shift, card_table_shift;
4234 gpointer card_table_mask;
4235 size_t nursery_size;
4236 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4237 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4240 * We need one register we can clobber, we choose EDX and make sreg1
4241 * fixed EAX to work around limitations in the local register allocator.
4242 * sreg2 might get allocated to EDX, but that is not a problem since
4243 * we use it before clobbering EDX.
4245 g_assert (ins->sreg1 == X86_EAX);
4248 * This is the code we produce:
4251 * edx >>= nursery_shift
4252 * cmp edx, (nursery_start >> nursery_shift)
4255 * edx >>= card_table_shift
4256 * card_table[edx] = 1
4260 if (value != X86_EDX)
4261 x86_mov_reg_reg (code, X86_EDX, value, 4);
4262 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4263 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4264 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4265 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4266 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4267 if (card_table_mask)
4268 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4269 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4270 x86_patch (br, code);
4273 #ifdef MONO_ARCH_SIMD_INTRINSICS
4275 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4278 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4281 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4284 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4287 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4290 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4293 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4294 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4297 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4300 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4303 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4306 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4309 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4312 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4315 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4318 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4321 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4324 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4327 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4330 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4333 case OP_PSHUFLEW_HIGH:
4334 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4335 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4337 case OP_PSHUFLEW_LOW:
4338 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4339 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4342 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4343 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4346 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4347 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4350 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4351 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4355 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4358 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4361 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4364 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4367 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4370 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4373 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4374 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4377 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4380 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4383 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4386 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4389 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4392 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4395 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4398 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4401 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4404 case OP_EXTRACT_MASK:
4405 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4409 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4412 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4415 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4419 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4422 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4425 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4428 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4432 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4435 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4438 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4441 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4445 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4448 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4451 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4455 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4458 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4461 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4465 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4468 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4472 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4475 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4478 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4482 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4485 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4488 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4492 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4495 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4498 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4501 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4505 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4508 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4511 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4514 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4517 case OP_PSUM_ABS_DIFF:
4518 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4521 case OP_UNPACK_LOWB:
4522 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4524 case OP_UNPACK_LOWW:
4525 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4527 case OP_UNPACK_LOWD:
4528 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4530 case OP_UNPACK_LOWQ:
4531 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4533 case OP_UNPACK_LOWPS:
4534 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4536 case OP_UNPACK_LOWPD:
4537 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4540 case OP_UNPACK_HIGHB:
4541 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4543 case OP_UNPACK_HIGHW:
4544 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4546 case OP_UNPACK_HIGHD:
4547 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4549 case OP_UNPACK_HIGHQ:
4550 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4552 case OP_UNPACK_HIGHPS:
4553 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4555 case OP_UNPACK_HIGHPD:
4556 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4560 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4563 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4566 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4569 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4572 case OP_PADDB_SAT_UN:
4573 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4575 case OP_PSUBB_SAT_UN:
4576 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4578 case OP_PADDW_SAT_UN:
4579 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4581 case OP_PSUBW_SAT_UN:
4582 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4586 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4589 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4592 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4595 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4599 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4602 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4605 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4607 case OP_PMULW_HIGH_UN:
4608 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4611 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4615 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4618 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4622 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4625 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4629 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4632 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4636 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4639 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4643 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4646 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4650 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4653 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4657 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4660 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4664 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4667 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4671 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4674 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4678 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4680 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4681 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4685 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4687 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4688 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4692 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4694 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4695 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4699 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4701 case OP_EXTRACTX_U2:
4702 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4704 case OP_INSERTX_U1_SLOW:
4705 /*sreg1 is the extracted ireg (scratch)
4706 /sreg2 is the to be inserted ireg (scratch)
4707 /dreg is the xreg to receive the value*/
4709 /*clear the bits from the extracted word*/
4710 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4711 /*shift the value to insert if needed*/
4712 if (ins->inst_c0 & 1)
4713 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4714 /*join them together*/
4715 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4716 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4718 case OP_INSERTX_I4_SLOW:
4719 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4720 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4721 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4724 case OP_INSERTX_R4_SLOW:
4725 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4726 /*TODO if inst_c0 == 0 use movss*/
4727 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4728 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4730 case OP_INSERTX_R8_SLOW:
4731 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4732 if (cfg->verbose_level)
4733 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4735 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4737 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4740 case OP_STOREX_MEMBASE_REG:
4741 case OP_STOREX_MEMBASE:
4742 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4744 case OP_LOADX_MEMBASE:
4745 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4747 case OP_LOADX_ALIGNED_MEMBASE:
4748 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4750 case OP_STOREX_ALIGNED_MEMBASE_REG:
4751 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4753 case OP_STOREX_NTA_MEMBASE_REG:
4754 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4756 case OP_PREFETCH_MEMBASE:
4757 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4761 /*FIXME the peephole pass should have killed this*/
4762 if (ins->dreg != ins->sreg1)
4763 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4766 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4768 case OP_ICONV_TO_R8_RAW:
4769 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4770 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4773 case OP_FCONV_TO_R8_X:
4774 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4775 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4778 case OP_XCONV_R8_TO_I4:
4779 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4780 switch (ins->backend.source_opcode) {
4781 case OP_FCONV_TO_I1:
4782 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4784 case OP_FCONV_TO_U1:
4785 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4787 case OP_FCONV_TO_I2:
4788 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4790 case OP_FCONV_TO_U2:
4791 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4797 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4798 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4799 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4800 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4801 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4802 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4805 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4806 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4807 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4810 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4811 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4814 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4815 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4816 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4819 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4820 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4821 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4825 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4828 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4831 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4834 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4837 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4840 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4843 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4846 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4850 case OP_LIVERANGE_START: {
4851 if (cfg->verbose_level > 1)
4852 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4853 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4856 case OP_LIVERANGE_END: {
4857 if (cfg->verbose_level > 1)
4858 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4859 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4862 case OP_NACL_GC_SAFE_POINT: {
4863 #if defined(__native_client_codegen__)
4864 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
4868 case OP_GC_LIVENESS_DEF:
4869 case OP_GC_LIVENESS_USE:
4870 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4871 ins->backend.pc_offset = code - cfg->native_code;
4873 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4874 ins->backend.pc_offset = code - cfg->native_code;
4875 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4878 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4879 g_assert_not_reached ();
4882 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4883 #ifndef __native_client_codegen__
4884 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4885 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4886 g_assert_not_reached ();
4887 #endif /* __native_client_codegen__ */
4893 cfg->code_len = code - cfg->native_code;
4896 #endif /* DISABLE_JIT */
4899 mono_arch_register_lowlevel_calls (void)
4904 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4906 MonoJumpInfo *patch_info;
4907 gboolean compile_aot = !run_cctors;
4909 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4910 unsigned char *ip = patch_info->ip.i + code;
4911 const unsigned char *target;
4913 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4916 switch (patch_info->type) {
4917 case MONO_PATCH_INFO_BB:
4918 case MONO_PATCH_INFO_LABEL:
4921 /* No need to patch these */
4926 switch (patch_info->type) {
4927 case MONO_PATCH_INFO_IP:
4928 *((gconstpointer *)(ip)) = target;
4930 case MONO_PATCH_INFO_CLASS_INIT: {
4932 /* Might already been changed to a nop */
4933 x86_call_code (code, 0);
4934 x86_patch (ip, target);
4937 case MONO_PATCH_INFO_ABS:
4938 case MONO_PATCH_INFO_METHOD:
4939 case MONO_PATCH_INFO_METHOD_JUMP:
4940 case MONO_PATCH_INFO_INTERNAL_METHOD:
4941 case MONO_PATCH_INFO_BB:
4942 case MONO_PATCH_INFO_LABEL:
4943 case MONO_PATCH_INFO_RGCTX_FETCH:
4944 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
4945 case MONO_PATCH_INFO_MONITOR_ENTER:
4946 case MONO_PATCH_INFO_MONITOR_EXIT:
4947 #if defined(__native_client_codegen__) && defined(__native_client__)
4948 if (nacl_is_code_address (code)) {
4949 /* For tail calls, code is patched after being installed */
4950 /* but not through the normal "patch callsite" method. */
4951 unsigned char buf[kNaClAlignment];
4952 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
4953 unsigned char *_target = target;
4955 /* All patch targets modified in x86_patch */
4956 /* are IP relative. */
4957 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
4958 memcpy (buf, aligned_code, kNaClAlignment);
4959 /* Patch a temp buffer of bundle size, */
4960 /* then install to actual location. */
4961 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
4962 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
4963 g_assert (ret == 0);
4966 x86_patch (ip, target);
4969 x86_patch (ip, target);
4972 case MONO_PATCH_INFO_NONE:
4974 case MONO_PATCH_INFO_R4:
4975 case MONO_PATCH_INFO_R8: {
4976 guint32 offset = mono_arch_get_patch_offset (ip);
4977 *((gconstpointer *)(ip + offset)) = target;
4981 guint32 offset = mono_arch_get_patch_offset (ip);
4982 #if !defined(__native_client__)
4983 *((gconstpointer *)(ip + offset)) = target;
4985 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
4994 mono_arch_emit_prolog (MonoCompile *cfg)
4996 MonoMethod *method = cfg->method;
4998 MonoMethodSignature *sig;
5000 int alloc_size, pos, max_offset, i, cfa_offset;
5002 gboolean need_stack_frame;
5003 #ifdef __native_client_codegen__
5004 guint alignment_check;
5007 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5009 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5010 cfg->code_size += 512;
5012 #if defined(__default_codegen__)
5013 code = cfg->native_code = g_malloc (cfg->code_size);
5014 #elif defined(__native_client_codegen__)
5015 /* native_code_alloc is not 32-byte aligned, native_code is. */
5016 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5018 /* Align native_code to next nearest kNaclAlignment byte. */
5019 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5020 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5022 code = cfg->native_code;
5024 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5025 g_assert(alignment_check == 0);
5028 /* Offset between RSP and the CFA */
5032 cfa_offset = sizeof (gpointer);
5033 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5034 // IP saved at CFA - 4
5035 /* There is no IP reg on x86 */
5036 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5037 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5039 need_stack_frame = needs_stack_frame (cfg);
5041 if (need_stack_frame) {
5042 x86_push_reg (code, X86_EBP);
5043 cfa_offset += sizeof (gpointer);
5044 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5045 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5046 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5047 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5048 /* These are handled automatically by the stack marking code */
5049 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5051 cfg->frame_reg = X86_ESP;
5054 alloc_size = cfg->stack_offset;
5057 if (method->save_lmf) {
5058 pos += sizeof (MonoLMF);
5060 /* save the current IP */
5061 if (cfg->compile_aot) {
5062 /* This pushes the current ip */
5063 x86_call_imm (code, 0);
5065 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
5066 x86_push_imm_template (code);
5068 cfa_offset += sizeof (gpointer);
5069 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5071 /* save all caller saved regs */
5072 x86_push_reg (code, X86_EBP);
5073 cfa_offset += sizeof (gpointer);
5074 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5075 x86_push_reg (code, X86_ESI);
5076 cfa_offset += sizeof (gpointer);
5077 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5078 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5079 x86_push_reg (code, X86_EDI);
5080 cfa_offset += sizeof (gpointer);
5081 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5082 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5083 x86_push_reg (code, X86_EBX);
5084 cfa_offset += sizeof (gpointer);
5085 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5086 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5088 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5090 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5091 * through the mono_lmf_addr TLS variable.
5093 /* %eax = previous_lmf */
5094 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_tls_offset);
5095 /* skip esp + method_info + lmf */
5096 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 12);
5098 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5099 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + 4, SLOT_NOREF);
5100 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + 8, SLOT_NOREF);
5101 /* push previous_lmf */
5102 x86_push_reg (code, X86_EAX);
5104 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5106 code = mono_x86_emit_tls_set (code, X86_ESP, lmf_tls_offset);
5108 /* get the address of lmf for the current thread */
5110 * This is performance critical so we try to use some tricks to make
5114 if (lmf_addr_tls_offset != -1) {
5115 /* Load lmf quicky using the GS register */
5116 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
5118 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5119 /* FIXME: Add a separate key for LMF to avoid this */
5120 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5123 if (cfg->compile_aot)
5124 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
5125 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
5128 /* Skip esp + method info */
5129 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
5132 x86_push_reg (code, X86_EAX);
5133 /* push *lfm (previous_lmf) */
5134 x86_push_membase (code, X86_EAX, 0);
5136 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
5140 if (cfg->used_int_regs & (1 << X86_EBX)) {
5141 x86_push_reg (code, X86_EBX);
5143 cfa_offset += sizeof (gpointer);
5144 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5145 /* These are handled automatically by the stack marking code */
5146 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5149 if (cfg->used_int_regs & (1 << X86_EDI)) {
5150 x86_push_reg (code, X86_EDI);
5152 cfa_offset += sizeof (gpointer);
5153 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5154 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5157 if (cfg->used_int_regs & (1 << X86_ESI)) {
5158 x86_push_reg (code, X86_ESI);
5160 cfa_offset += sizeof (gpointer);
5161 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5162 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5168 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5169 if (mono_do_x86_stack_align && need_stack_frame) {
5170 int tot = alloc_size + pos + 4; /* ret ip */
5171 if (need_stack_frame)
5173 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5175 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5176 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5177 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5181 cfg->arch.sp_fp_offset = alloc_size + pos;
5184 /* See mono_emit_stack_alloc */
5185 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5186 guint32 remaining_size = alloc_size;
5187 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5188 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5189 guint32 offset = code - cfg->native_code;
5190 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5191 while (required_code_size >= (cfg->code_size - offset))
5192 cfg->code_size *= 2;
5193 cfg->native_code = mono_realloc_native_code(cfg);
5194 code = cfg->native_code + offset;
5195 cfg->stat_code_reallocs++;
5197 while (remaining_size >= 0x1000) {
5198 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5199 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5200 remaining_size -= 0x1000;
5203 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5205 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5208 g_assert (need_stack_frame);
5211 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5212 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5213 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5216 #if DEBUG_STACK_ALIGNMENT
5217 /* check the stack is aligned */
5218 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5219 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5220 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5221 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5222 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5223 x86_breakpoint (code);
5227 /* compute max_offset in order to use short forward jumps */
5229 if (cfg->opt & MONO_OPT_BRANCH) {
5230 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5232 bb->max_offset = max_offset;
5234 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5236 /* max alignment for loops */
5237 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5238 max_offset += LOOP_ALIGNMENT;
5239 #ifdef __native_client_codegen__
5240 /* max alignment for native client */
5241 max_offset += kNaClAlignment;
5243 MONO_BB_FOR_EACH_INS (bb, ins) {
5244 if (ins->opcode == OP_LABEL)
5245 ins->inst_c1 = max_offset;
5246 #ifdef __native_client_codegen__
5248 int space_in_block = kNaClAlignment -
5249 ((max_offset + cfg->code_len) & kNaClAlignmentMask);
5250 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5251 if (space_in_block < max_len && max_len < kNaClAlignment) {
5252 max_offset += space_in_block;
5255 #endif /* __native_client_codegen__ */
5256 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5261 /* store runtime generic context */
5262 if (cfg->rgctx_var) {
5263 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5265 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5268 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5269 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5271 /* load arguments allocated to register from the stack */
5272 sig = mono_method_signature (method);
5275 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5276 inst = cfg->args [pos];
5277 if (inst->opcode == OP_REGVAR) {
5278 g_assert (need_stack_frame);
5279 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5280 if (cfg->verbose_level > 2)
5281 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5286 cfg->code_len = code - cfg->native_code;
5288 g_assert (cfg->code_len < cfg->code_size);
5294 mono_arch_emit_epilog (MonoCompile *cfg)
5296 MonoMethod *method = cfg->method;
5297 MonoMethodSignature *sig = mono_method_signature (method);
5299 guint32 stack_to_pop;
5301 int max_epilog_size = 16;
5303 gboolean need_stack_frame = needs_stack_frame (cfg);
5305 if (cfg->method->save_lmf)
5306 max_epilog_size += 128;
5308 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5309 cfg->code_size *= 2;
5310 cfg->native_code = mono_realloc_native_code(cfg);
5311 cfg->stat_code_reallocs++;
5314 code = cfg->native_code + cfg->code_len;
5316 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5317 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5319 /* the code restoring the registers must be kept in sync with OP_JMP */
5322 if (method->save_lmf) {
5323 gint32 prev_lmf_reg;
5324 gint32 lmf_offset = -sizeof (MonoLMF);
5326 /* check if we need to restore protection of the stack after a stack overflow */
5327 if (mono_get_jit_tls_offset () != -1) {
5329 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5330 /* we load the value in a separate instruction: this mechanism may be
5331 * used later as a safer way to do thread interruption
5333 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5334 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5336 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5337 /* note that the call trampoline will preserve eax/edx */
5338 x86_call_reg (code, X86_ECX);
5339 x86_patch (patch, code);
5341 /* FIXME: maybe save the jit tls in the prolog */
5343 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5345 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5346 * through the mono_lmf_addr TLS variable.
5348 /* reg = previous_lmf */
5349 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5351 /* lmf = previous_lmf */
5352 code = mono_x86_emit_tls_set (code, X86_ECX, lmf_tls_offset);
5354 /* Find a spare register */
5355 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
5358 prev_lmf_reg = X86_EDI;
5359 cfg->used_int_regs |= (1 << X86_EDI);
5362 prev_lmf_reg = X86_EDX;
5366 /* reg = previous_lmf */
5367 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5370 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
5372 /* *(lmf) = previous_lmf */
5373 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
5376 /* restore caller saved regs */
5377 if (cfg->used_int_regs & (1 << X86_EBX)) {
5378 x86_mov_reg_membase (code, X86_EBX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
5381 if (cfg->used_int_regs & (1 << X86_EDI)) {
5382 x86_mov_reg_membase (code, X86_EDI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
5384 if (cfg->used_int_regs & (1 << X86_ESI)) {
5385 x86_mov_reg_membase (code, X86_ESI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
5388 /* EBP is restored by LEAVE */
5390 if (cfg->used_int_regs & (1 << X86_EBX)) {
5393 if (cfg->used_int_regs & (1 << X86_EDI)) {
5396 if (cfg->used_int_regs & (1 << X86_ESI)) {
5401 g_assert (need_stack_frame);
5402 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5405 if (cfg->used_int_regs & (1 << X86_ESI)) {
5406 x86_pop_reg (code, X86_ESI);
5408 if (cfg->used_int_regs & (1 << X86_EDI)) {
5409 x86_pop_reg (code, X86_EDI);
5411 if (cfg->used_int_regs & (1 << X86_EBX)) {
5412 x86_pop_reg (code, X86_EBX);
5416 /* Load returned vtypes into registers if needed */
5417 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5418 if (cinfo->ret.storage == ArgValuetypeInReg) {
5419 for (quad = 0; quad < 2; quad ++) {
5420 switch (cinfo->ret.pair_storage [quad]) {
5422 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5424 case ArgOnFloatFpStack:
5425 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5427 case ArgOnDoubleFpStack:
5428 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5433 g_assert_not_reached ();
5438 if (need_stack_frame)
5441 if (CALLCONV_IS_STDCALL (sig)) {
5442 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5444 stack_to_pop = mono_arch_get_argument_info (cfg->generic_sharing_context, sig, sig->param_count, arg_info);
5445 } else if (MONO_TYPE_ISSTRUCT (mono_method_signature (cfg->method)->ret) && (cinfo->ret.storage == ArgOnStack))
5451 g_assert (need_stack_frame);
5452 x86_ret_imm (code, stack_to_pop);
5457 cfg->code_len = code - cfg->native_code;
5459 g_assert (cfg->code_len < cfg->code_size);
5463 mono_arch_emit_exceptions (MonoCompile *cfg)
5465 MonoJumpInfo *patch_info;
5468 MonoClass *exc_classes [16];
5469 guint8 *exc_throw_start [16], *exc_throw_end [16];
5473 /* Compute needed space */
5474 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5475 if (patch_info->type == MONO_PATCH_INFO_EXC)
5480 * make sure we have enough space for exceptions
5481 * 16 is the size of two push_imm instructions and a call
5483 if (cfg->compile_aot)
5484 code_size = exc_count * 32;
5486 code_size = exc_count * 16;
5488 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5489 cfg->code_size *= 2;
5490 cfg->native_code = mono_realloc_native_code(cfg);
5491 cfg->stat_code_reallocs++;
5494 code = cfg->native_code + cfg->code_len;
5497 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5498 switch (patch_info->type) {
5499 case MONO_PATCH_INFO_EXC: {
5500 MonoClass *exc_class;
5504 x86_patch (patch_info->ip.i + cfg->native_code, code);
5506 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5507 g_assert (exc_class);
5508 throw_ip = patch_info->ip.i;
5510 /* Find a throw sequence for the same exception class */
5511 for (i = 0; i < nthrows; ++i)
5512 if (exc_classes [i] == exc_class)
5515 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5516 x86_jump_code (code, exc_throw_start [i]);
5517 patch_info->type = MONO_PATCH_INFO_NONE;
5522 /* Compute size of code following the push <OFFSET> */
5523 #if defined(__default_codegen__)
5525 #elif defined(__native_client_codegen__)
5526 code = mono_nacl_align (code);
5527 size = kNaClAlignment;
5529 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5531 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5532 /* Use the shorter form */
5534 x86_push_imm (code, 0);
5538 x86_push_imm (code, 0xf0f0f0f0);
5543 exc_classes [nthrows] = exc_class;
5544 exc_throw_start [nthrows] = code;
5547 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5548 patch_info->data.name = "mono_arch_throw_corlib_exception";
5549 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5550 patch_info->ip.i = code - cfg->native_code;
5551 x86_call_code (code, 0);
5552 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5557 exc_throw_end [nthrows] = code;
5569 cfg->code_len = code - cfg->native_code;
5571 g_assert (cfg->code_len < cfg->code_size);
5575 mono_arch_flush_icache (guint8 *code, gint size)
5581 mono_arch_flush_register_windows (void)
5586 mono_arch_is_inst_imm (gint64 imm)
5592 mono_arch_finish_init (void)
5594 if (!getenv ("MONO_NO_TLS")) {
5597 * We need to init this multiple times, since when we are first called, the key might not
5598 * be initialized yet.
5600 appdomain_tls_offset = mono_domain_get_tls_key ();
5601 lmf_tls_offset = mono_get_jit_tls_key ();
5603 /* Only 64 tls entries can be accessed using inline code */
5604 if (appdomain_tls_offset >= 64)
5605 appdomain_tls_offset = -1;
5606 if (lmf_tls_offset >= 64)
5607 lmf_tls_offset = -1;
5610 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5612 appdomain_tls_offset = mono_domain_get_tls_offset ();
5613 lmf_tls_offset = mono_get_lmf_tls_offset ();
5614 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5620 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5624 #ifdef MONO_ARCH_HAVE_IMT
5626 // Linear handler, the bsearch head compare is shorter
5627 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5628 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5629 // x86_patch(ins,target)
5630 //[1 + 5] x86_jump_mem(inst,mem)
5633 #if defined(__default_codegen__)
5634 #define BR_SMALL_SIZE 2
5635 #define BR_LARGE_SIZE 5
5636 #elif defined(__native_client_codegen__)
5637 /* I suspect the size calculation below is actually incorrect. */
5638 /* TODO: fix the calculation that uses these sizes. */
5639 #define BR_SMALL_SIZE 16
5640 #define BR_LARGE_SIZE 12
5641 #endif /*__native_client_codegen__*/
5642 #define JUMP_IMM_SIZE 6
5643 #define ENABLE_WRONG_METHOD_CHECK 0
5647 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5649 int i, distance = 0;
5650 for (i = start; i < target; ++i)
5651 distance += imt_entries [i]->chunk_size;
5656 * LOCKING: called with the domain lock held
5659 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5660 gpointer fail_tramp)
5664 guint8 *code, *start;
5666 for (i = 0; i < count; ++i) {
5667 MonoIMTCheckItem *item = imt_entries [i];
5668 if (item->is_equals) {
5669 if (item->check_target_idx) {
5670 if (!item->compare_done)
5671 item->chunk_size += CMP_SIZE;
5672 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5675 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5677 item->chunk_size += JUMP_IMM_SIZE;
5678 #if ENABLE_WRONG_METHOD_CHECK
5679 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5684 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5685 imt_entries [item->check_target_idx]->compare_done = TRUE;
5687 size += item->chunk_size;
5689 #if defined(__native_client__) && defined(__native_client_codegen__)
5690 /* In Native Client, we don't re-use thunks, allocate from the */
5691 /* normal code manager paths. */
5692 code = mono_domain_code_reserve (domain, size);
5695 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5697 code = mono_domain_code_reserve (domain, size);
5700 for (i = 0; i < count; ++i) {
5701 MonoIMTCheckItem *item = imt_entries [i];
5702 item->code_target = code;
5703 if (item->is_equals) {
5704 if (item->check_target_idx) {
5705 if (!item->compare_done)
5706 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5707 item->jmp_code = code;
5708 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5709 if (item->has_target_code)
5710 x86_jump_code (code, item->value.target_code);
5712 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5715 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5716 item->jmp_code = code;
5717 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5718 if (item->has_target_code)
5719 x86_jump_code (code, item->value.target_code);
5721 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5722 x86_patch (item->jmp_code, code);
5723 x86_jump_code (code, fail_tramp);
5724 item->jmp_code = NULL;
5726 /* enable the commented code to assert on wrong method */
5727 #if ENABLE_WRONG_METHOD_CHECK
5728 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5729 item->jmp_code = code;
5730 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5732 if (item->has_target_code)
5733 x86_jump_code (code, item->value.target_code);
5735 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5736 #if ENABLE_WRONG_METHOD_CHECK
5737 x86_patch (item->jmp_code, code);
5738 x86_breakpoint (code);
5739 item->jmp_code = NULL;
5744 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5745 item->jmp_code = code;
5746 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5747 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5749 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5752 /* patch the branches to get to the target items */
5753 for (i = 0; i < count; ++i) {
5754 MonoIMTCheckItem *item = imt_entries [i];
5755 if (item->jmp_code) {
5756 if (item->check_target_idx) {
5757 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5763 mono_stats.imt_thunks_size += code - start;
5764 g_assert (code - start <= size);
5768 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5769 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5773 if (mono_jit_map_is_enabled ()) {
5776 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5778 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5779 mono_emit_jit_tramp (start, code - start, buff);
5783 nacl_domain_code_validate (domain, &start, size, &code);
5789 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5791 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5796 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5798 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5802 mono_arch_get_cie_program (void)
5806 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5807 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5813 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5815 MonoInst *ins = NULL;
5818 if (cmethod->klass == mono_defaults.math_class) {
5819 if (strcmp (cmethod->name, "Sin") == 0) {
5821 } else if (strcmp (cmethod->name, "Cos") == 0) {
5823 } else if (strcmp (cmethod->name, "Tan") == 0) {
5825 } else if (strcmp (cmethod->name, "Atan") == 0) {
5827 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5829 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5831 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5836 MONO_INST_NEW (cfg, ins, opcode);
5837 ins->type = STACK_R8;
5838 ins->dreg = mono_alloc_freg (cfg);
5839 ins->sreg1 = args [0]->dreg;
5840 MONO_ADD_INS (cfg->cbb, ins);
5843 if (cfg->opt & MONO_OPT_CMOV) {
5846 if (strcmp (cmethod->name, "Min") == 0) {
5847 if (fsig->params [0]->type == MONO_TYPE_I4)
5849 } else if (strcmp (cmethod->name, "Max") == 0) {
5850 if (fsig->params [0]->type == MONO_TYPE_I4)
5855 MONO_INST_NEW (cfg, ins, opcode);
5856 ins->type = STACK_I4;
5857 ins->dreg = mono_alloc_ireg (cfg);
5858 ins->sreg1 = args [0]->dreg;
5859 ins->sreg2 = args [1]->dreg;
5860 MONO_ADD_INS (cfg->cbb, ins);
5865 /* OP_FREM is not IEEE compatible */
5866 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5867 MONO_INST_NEW (cfg, ins, OP_FREM);
5868 ins->inst_i0 = args [0];
5869 ins->inst_i1 = args [1];
5878 mono_arch_print_tree (MonoInst *tree, int arity)
5883 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5889 if (appdomain_tls_offset == -1)
5892 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5893 ins->inst_offset = appdomain_tls_offset;
5898 mono_arch_get_patch_offset (guint8 *code)
5900 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5902 else if ((code [0] == 0xba))
5904 else if ((code [0] == 0x68))
5907 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5908 /* push <OFFSET>(<REG>) */
5910 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5911 /* call *<OFFSET>(<REG>) */
5913 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5916 else if ((code [0] == 0x58) && (code [1] == 0x05))
5917 /* pop %eax; add <OFFSET>, %eax */
5919 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5920 /* pop <REG>; add <OFFSET>, <REG> */
5922 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5923 /* mov <REG>, imm */
5926 g_assert_not_reached ();
5932 * mono_breakpoint_clean_code:
5934 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5935 * breakpoints in the original code, they are removed in the copy.
5937 * Returns TRUE if no sw breakpoint was present.
5940 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5943 gboolean can_write = TRUE;
5945 * If method_start is non-NULL we need to perform bound checks, since we access memory
5946 * at code - offset we could go before the start of the method and end up in a different
5947 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5950 if (!method_start || code - offset >= method_start) {
5951 memcpy (buf, code - offset, size);
5953 int diff = code - method_start;
5954 memset (buf, 0, size);
5955 memcpy (buf + offset - diff, method_start, diff + size - offset);
5958 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5959 int idx = mono_breakpoint_info_index [i];
5963 ptr = mono_breakpoint_info [idx].address;
5964 if (ptr >= code && ptr < code + size) {
5965 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5967 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5968 buf [ptr - code] = saved_byte;
5975 * mono_x86_get_this_arg_offset:
5977 * Return the offset of the stack location where this is passed during a virtual
5981 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
5987 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
5989 guint32 esp = regs [X86_ESP];
5990 CallInfo *cinfo = NULL;
5997 * The stack looks like:
6001 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
6003 res = (((MonoObject**)esp) [5 + (offset / 4)]);
6009 #define MAX_ARCH_DELEGATE_PARAMS 10
6012 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6014 guint8 *code, *start;
6015 int code_reserve = 64;
6018 * The stack contains:
6024 start = code = mono_global_codeman_reserve (code_reserve);
6026 /* Replace the this argument with the target */
6027 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6028 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
6029 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6030 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6032 g_assert ((code - start) < code_reserve);
6035 /* 8 for mov_reg and jump, plus 8 for each parameter */
6036 #ifdef __native_client_codegen__
6037 /* TODO: calculate this size correctly */
6038 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6040 code_reserve = 8 + (param_count * 8);
6041 #endif /* __native_client_codegen__ */
6043 * The stack contains:
6044 * <args in reverse order>
6049 * <args in reverse order>
6052 * without unbalancing the stack.
6053 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6054 * and leaving original spot of first arg as placeholder in stack so
6055 * when callee pops stack everything works.
6058 start = code = mono_global_codeman_reserve (code_reserve);
6060 /* store delegate for access to method_ptr */
6061 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6064 for (i = 0; i < param_count; ++i) {
6065 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6066 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6069 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6071 g_assert ((code - start) < code_reserve);
6074 nacl_global_codeman_validate(&start, code_reserve, &code);
6075 mono_debug_add_delegate_trampoline (start, code - start);
6078 *code_len = code - start;
6080 if (mono_jit_map_is_enabled ()) {
6083 buff = (char*)"delegate_invoke_has_target";
6085 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6086 mono_emit_jit_tramp (start, code - start, buff);
6095 mono_arch_get_delegate_invoke_impls (void)
6102 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6103 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
6105 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6106 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6107 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
6114 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6116 guint8 *code, *start;
6118 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6121 /* FIXME: Support more cases */
6122 if (MONO_TYPE_ISSTRUCT (sig->ret))
6126 * The stack contains:
6132 static guint8* cached = NULL;
6137 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6139 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6141 mono_memory_barrier ();
6145 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6148 for (i = 0; i < sig->param_count; ++i)
6149 if (!mono_is_regsize_var (sig->params [i]))
6152 code = cache [sig->param_count];
6156 if (mono_aot_only) {
6157 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6158 start = mono_aot_get_trampoline (name);
6161 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6164 mono_memory_barrier ();
6166 cache [sig->param_count] = start;
6173 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6176 case X86_EAX: return ctx->eax;
6177 case X86_EBX: return ctx->ebx;
6178 case X86_ECX: return ctx->ecx;
6179 case X86_EDX: return ctx->edx;
6180 case X86_ESP: return ctx->esp;
6181 case X86_EBP: return ctx->ebp;
6182 case X86_ESI: return ctx->esi;
6183 case X86_EDI: return ctx->edi;
6185 g_assert_not_reached ();
6191 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6219 g_assert_not_reached ();
6223 #ifdef MONO_ARCH_SIMD_INTRINSICS
6226 get_float_to_x_spill_area (MonoCompile *cfg)
6228 if (!cfg->fconv_to_r8_x_var) {
6229 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6230 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6232 return cfg->fconv_to_r8_x_var;
6236 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6239 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6242 int dreg, src_opcode;
6244 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6247 switch (src_opcode = ins->opcode) {
6248 case OP_FCONV_TO_I1:
6249 case OP_FCONV_TO_U1:
6250 case OP_FCONV_TO_I2:
6251 case OP_FCONV_TO_U2:
6252 case OP_FCONV_TO_I4:
6259 /* dreg is the IREG and sreg1 is the FREG */
6260 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6261 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6262 fconv->sreg1 = ins->sreg1;
6263 fconv->dreg = mono_alloc_ireg (cfg);
6264 fconv->type = STACK_VTYPE;
6265 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6267 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6271 ins->opcode = OP_XCONV_R8_TO_I4;
6273 ins->klass = mono_defaults.int32_class;
6274 ins->sreg1 = fconv->dreg;
6276 ins->type = STACK_I4;
6277 ins->backend.source_opcode = src_opcode;
6280 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6283 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6288 if (long_ins->opcode == OP_LNEG) {
6290 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6291 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6292 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6297 #ifdef MONO_ARCH_SIMD_INTRINSICS
6299 if (!(cfg->opt & MONO_OPT_SIMD))
6302 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6303 switch (long_ins->opcode) {
6305 vreg = long_ins->sreg1;
6307 if (long_ins->inst_c0) {
6308 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6309 ins->klass = long_ins->klass;
6310 ins->sreg1 = long_ins->sreg1;
6312 ins->type = STACK_VTYPE;
6313 ins->dreg = vreg = alloc_ireg (cfg);
6314 MONO_ADD_INS (cfg->cbb, ins);
6317 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6318 ins->klass = mono_defaults.int32_class;
6320 ins->type = STACK_I4;
6321 ins->dreg = long_ins->dreg + 1;
6322 MONO_ADD_INS (cfg->cbb, ins);
6324 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6325 ins->klass = long_ins->klass;
6326 ins->sreg1 = long_ins->sreg1;
6327 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6328 ins->type = STACK_VTYPE;
6329 ins->dreg = vreg = alloc_ireg (cfg);
6330 MONO_ADD_INS (cfg->cbb, ins);
6332 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6333 ins->klass = mono_defaults.int32_class;
6335 ins->type = STACK_I4;
6336 ins->dreg = long_ins->dreg + 2;
6337 MONO_ADD_INS (cfg->cbb, ins);
6339 long_ins->opcode = OP_NOP;
6341 case OP_INSERTX_I8_SLOW:
6342 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6343 ins->dreg = long_ins->dreg;
6344 ins->sreg1 = long_ins->dreg;
6345 ins->sreg2 = long_ins->sreg2 + 1;
6346 ins->inst_c0 = long_ins->inst_c0 * 2;
6347 MONO_ADD_INS (cfg->cbb, ins);
6349 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6350 ins->dreg = long_ins->dreg;
6351 ins->sreg1 = long_ins->dreg;
6352 ins->sreg2 = long_ins->sreg2 + 2;
6353 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6354 MONO_ADD_INS (cfg->cbb, ins);
6356 long_ins->opcode = OP_NOP;
6359 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6360 ins->dreg = long_ins->dreg;
6361 ins->sreg1 = long_ins->sreg1 + 1;
6362 ins->klass = long_ins->klass;
6363 ins->type = STACK_VTYPE;
6364 MONO_ADD_INS (cfg->cbb, ins);
6366 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6367 ins->dreg = long_ins->dreg;
6368 ins->sreg1 = long_ins->dreg;
6369 ins->sreg2 = long_ins->sreg1 + 2;
6371 ins->klass = long_ins->klass;
6372 ins->type = STACK_VTYPE;
6373 MONO_ADD_INS (cfg->cbb, ins);
6375 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6376 ins->dreg = long_ins->dreg;
6377 ins->sreg1 = long_ins->dreg;;
6378 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6379 ins->klass = long_ins->klass;
6380 ins->type = STACK_VTYPE;
6381 MONO_ADD_INS (cfg->cbb, ins);
6383 long_ins->opcode = OP_NOP;
6386 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6389 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6391 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6394 gpointer *sp, old_value;
6396 const unsigned char *handler;
6398 /*Decode the first instruction to figure out where did we store the spvar*/
6399 /*Our jit MUST generate the following:
6401 Which is encoded as: 0x89 mod_rm.
6402 mod_rm (esp, ebp, imm) which can be: (imm will never be zero)
6403 mod (reg + imm8): 01 reg(esp): 100 rm(ebp): 101 -> 01100101 (0x65)
6404 mod (reg + imm32): 10 reg(esp): 100 rm(ebp): 101 -> 10100101 (0xA5)
6406 handler = clause->handler_start;
6408 if (*handler != 0x89)
6413 if (*handler == 0x65)
6414 offset = *(signed char*)(handler + 1);
6415 else if (*handler == 0xA5)
6416 offset = *(int*)(handler + 1);
6421 bp = MONO_CONTEXT_GET_BP (ctx);
6422 sp = *(gpointer*)(bp + offset);
6425 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6434 * mono_aot_emit_load_got_addr:
6436 * Emit code to load the got address.
6437 * On x86, the result is placed into EBX.
6440 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6442 x86_call_imm (code, 0);
6444 * The patch needs to point to the pop, since the GOT offset needs
6445 * to be added to that address.
6448 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6450 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6451 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6452 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6458 * mono_ppc_emit_load_aotconst:
6460 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6461 * TARGET from the mscorlib GOT in full-aot code.
6462 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6466 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6468 /* Load the mscorlib got address */
6469 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6470 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6471 /* arch_emit_got_access () patches this */
6472 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6477 /* Can't put this into mini-x86.h */
6479 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6482 mono_arch_get_trampolines (gboolean aot)
6484 MonoTrampInfo *info;
6485 GSList *tramps = NULL;
6487 mono_x86_get_signal_exception_trampoline (&info, aot);
6489 tramps = g_slist_append (tramps, info);
6496 #define DBG_SIGNAL SIGBUS
6498 #define DBG_SIGNAL SIGSEGV
6501 /* Soft Debug support */
6502 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6505 * mono_arch_set_breakpoint:
6507 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6508 * The location should contain code emitted by OP_SEQ_POINT.
6511 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6516 * In production, we will use int3 (has to fix the size in the md
6517 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6520 g_assert (code [0] == 0x90);
6521 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6525 * mono_arch_clear_breakpoint:
6527 * Clear the breakpoint at IP.
6530 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6535 for (i = 0; i < 6; ++i)
6540 * mono_arch_start_single_stepping:
6542 * Start single stepping.
6545 mono_arch_start_single_stepping (void)
6547 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6551 * mono_arch_stop_single_stepping:
6553 * Stop single stepping.
6556 mono_arch_stop_single_stepping (void)
6558 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6562 * mono_arch_is_single_step_event:
6564 * Return whenever the machine state in SIGCTX corresponds to a single
6568 mono_arch_is_single_step_event (void *info, void *sigctx)
6571 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6573 if ((einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6578 siginfo_t* sinfo = (siginfo_t*) info;
6579 /* Sometimes the address is off by 4 */
6580 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6588 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6591 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6592 if ((einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6597 siginfo_t* sinfo = (siginfo_t*)info;
6598 /* Sometimes the address is off by 4 */
6599 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6606 #define BREAKPOINT_SIZE 6
6609 * mono_arch_skip_breakpoint:
6611 * See mini-amd64.c for docs.
6614 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6616 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6620 * mono_arch_skip_single_step:
6622 * See mini-amd64.c for docs.
6625 mono_arch_skip_single_step (MonoContext *ctx)
6627 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6631 * mono_arch_get_seq_point_info:
6633 * See mini-amd64.c for docs.
6636 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)