2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/appdomain.h>
21 #include <mono/metadata/debug-helpers.h>
22 #include <mono/metadata/threads.h>
23 #include <mono/metadata/profiler-private.h>
24 #include <mono/metadata/mono-debug.h>
25 #include <mono/metadata/gc-internal.h>
26 #include <mono/utils/mono-math.h>
27 #include <mono/utils/mono-counters.h>
28 #include <mono/utils/mono-mmap.h>
29 #include <mono/utils/mono-memory-model.h>
37 /* On windows, these hold the key returned by TlsAlloc () */
38 static gint lmf_tls_offset = -1;
39 static gint lmf_addr_tls_offset = -1;
40 static gint appdomain_tls_offset = -1;
43 static gboolean optimize_for_xen = TRUE;
45 #define optimize_for_xen 0
49 static gboolean is_win32 = TRUE;
51 static gboolean is_win32 = FALSE;
54 /* This mutex protects architecture specific caches */
55 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
56 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
57 static CRITICAL_SECTION mini_arch_mutex;
59 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
64 /* Under windows, the default pinvoke calling convention is stdcall */
65 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT))
67 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL)
70 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
73 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
76 #ifdef __native_client_codegen__
77 const guint kNaClAlignment = kNaClAlignmentX86;
78 const guint kNaClAlignmentMask = kNaClAlignmentMaskX86;
80 /* Default alignment for Native Client is 32-byte. */
81 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
83 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
84 /* Check that alignment doesn't cross an alignment boundary. */
86 mono_arch_nacl_pad (guint8 *code, int pad)
88 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
90 if (pad == 0) return code;
91 /* assertion: alignment cannot cross a block boundary */
92 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
93 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
94 while (pad >= kMaxPadding) {
95 x86_padding (code, kMaxPadding);
98 if (pad != 0) x86_padding (code, pad);
103 mono_arch_nacl_skip_nops (guint8 *code)
105 x86_skip_nops (code);
109 #endif /* __native_client_codegen__ */
112 * The code generated for sequence points reads from this location, which is
113 * made read-only when single stepping is enabled.
115 static gpointer ss_trigger_page;
117 /* Enabled breakpoints read from this trigger page */
118 static gpointer bp_trigger_page;
121 mono_arch_regname (int reg)
124 case X86_EAX: return "%eax";
125 case X86_EBX: return "%ebx";
126 case X86_ECX: return "%ecx";
127 case X86_EDX: return "%edx";
128 case X86_ESP: return "%esp";
129 case X86_EBP: return "%ebp";
130 case X86_EDI: return "%edi";
131 case X86_ESI: return "%esi";
137 mono_arch_fregname (int reg)
162 mono_arch_xregname (int reg)
187 mono_x86_patch (unsigned char* code, gpointer target)
189 x86_patch (code, (unsigned char*)target);
210 /* Only if storage == ArgValuetypeInReg */
211 ArgStorage pair_storage [2];
220 gboolean need_stack_align;
221 guint32 stack_align_amount;
222 gboolean vtype_retaddr;
223 /* The index of the vret arg in the argument list */
233 #define FLOAT_PARAM_REGS 0
235 static X86_Reg_No param_regs [] = { 0 };
237 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
238 #define SMALL_STRUCTS_IN_REGS
239 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
243 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
245 ainfo->offset = *stack_size;
247 if (*gr >= PARAM_REGS) {
248 ainfo->storage = ArgOnStack;
249 (*stack_size) += sizeof (gpointer);
252 ainfo->storage = ArgInIReg;
253 ainfo->reg = param_regs [*gr];
259 add_general_pair (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
261 ainfo->offset = *stack_size;
263 g_assert (PARAM_REGS == 0);
265 ainfo->storage = ArgOnStack;
266 (*stack_size) += sizeof (gpointer) * 2;
271 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
273 ainfo->offset = *stack_size;
275 if (*gr >= FLOAT_PARAM_REGS) {
276 ainfo->storage = ArgOnStack;
277 (*stack_size) += is_double ? 8 : 4;
278 ainfo->nslots = is_double ? 2 : 1;
281 /* A double register */
283 ainfo->storage = ArgInDoubleSSEReg;
285 ainfo->storage = ArgInFloatSSEReg;
293 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
295 guint32 *gr, guint32 *fr, guint32 *stack_size)
300 klass = mono_class_from_mono_type (type);
301 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
303 #ifdef SMALL_STRUCTS_IN_REGS
304 if (sig->pinvoke && is_return) {
305 MonoMarshalType *info;
308 * the exact rules are not very well documented, the code below seems to work with the
309 * code generated by gcc 3.3.3 -mno-cygwin.
311 info = mono_marshal_load_type_info (klass);
314 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
316 /* Special case structs with only a float member */
317 if ((info->native_size == 8) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R8)) {
318 ainfo->storage = ArgValuetypeInReg;
319 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
322 if ((info->native_size == 4) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R4)) {
323 ainfo->storage = ArgValuetypeInReg;
324 ainfo->pair_storage [0] = ArgOnFloatFpStack;
327 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
328 ainfo->storage = ArgValuetypeInReg;
329 ainfo->pair_storage [0] = ArgInIReg;
330 ainfo->pair_regs [0] = return_regs [0];
331 if (info->native_size > 4) {
332 ainfo->pair_storage [1] = ArgInIReg;
333 ainfo->pair_regs [1] = return_regs [1];
340 ainfo->offset = *stack_size;
341 ainfo->storage = ArgOnStack;
342 *stack_size += ALIGN_TO (size, sizeof (gpointer));
343 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
349 * Obtain information about a call according to the calling convention.
350 * For x86 ELF, see the "System V Application Binary Interface Intel386
351 * Architecture Processor Supplment, Fourth Edition" document for more
353 * For x86 win32, see ???.
356 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
358 guint32 i, gr, fr, pstart;
360 int n = sig->hasthis + sig->param_count;
361 guint32 stack_size = 0;
362 gboolean is_pinvoke = sig->pinvoke;
370 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
371 switch (ret_type->type) {
372 case MONO_TYPE_BOOLEAN:
383 case MONO_TYPE_FNPTR:
384 case MONO_TYPE_CLASS:
385 case MONO_TYPE_OBJECT:
386 case MONO_TYPE_SZARRAY:
387 case MONO_TYPE_ARRAY:
388 case MONO_TYPE_STRING:
389 cinfo->ret.storage = ArgInIReg;
390 cinfo->ret.reg = X86_EAX;
394 cinfo->ret.storage = ArgInIReg;
395 cinfo->ret.reg = X86_EAX;
396 cinfo->ret.is_pair = TRUE;
399 cinfo->ret.storage = ArgOnFloatFpStack;
402 cinfo->ret.storage = ArgOnDoubleFpStack;
404 case MONO_TYPE_GENERICINST:
405 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
406 cinfo->ret.storage = ArgInIReg;
407 cinfo->ret.reg = X86_EAX;
411 case MONO_TYPE_VALUETYPE:
412 case MONO_TYPE_TYPEDBYREF: {
413 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
415 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
416 if (cinfo->ret.storage == ArgOnStack) {
417 cinfo->vtype_retaddr = TRUE;
418 /* The caller passes the address where the value is stored */
423 cinfo->ret.storage = ArgNone;
426 g_error ("Can't handle as return value 0x%x", sig->ret->type);
432 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
433 * the first argument, allowing 'this' to be always passed in the first arg reg.
434 * Also do this if the first argument is a reference type, since virtual calls
435 * are sometimes made using calli without sig->hasthis set, like in the delegate
438 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
440 add_general (&gr, &stack_size, cinfo->args + 0);
442 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
445 cinfo->vret_arg_offset = stack_size;
446 add_general (&gr, &stack_size, &cinfo->ret);
447 cinfo->vret_arg_index = 1;
451 add_general (&gr, &stack_size, cinfo->args + 0);
453 if (cinfo->vtype_retaddr)
454 add_general (&gr, &stack_size, &cinfo->ret);
457 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
459 fr = FLOAT_PARAM_REGS;
461 /* Emit the signature cookie just before the implicit arguments */
462 add_general (&gr, &stack_size, &cinfo->sig_cookie);
465 for (i = pstart; i < sig->param_count; ++i) {
466 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
469 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
470 /* We allways pass the sig cookie on the stack for simplicity */
472 * Prevent implicit arguments + the sig cookie from being passed
476 fr = FLOAT_PARAM_REGS;
478 /* Emit the signature cookie just before the implicit arguments */
479 add_general (&gr, &stack_size, &cinfo->sig_cookie);
482 if (sig->params [i]->byref) {
483 add_general (&gr, &stack_size, ainfo);
486 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
487 switch (ptype->type) {
488 case MONO_TYPE_BOOLEAN:
491 add_general (&gr, &stack_size, ainfo);
496 add_general (&gr, &stack_size, ainfo);
500 add_general (&gr, &stack_size, ainfo);
505 case MONO_TYPE_FNPTR:
506 case MONO_TYPE_CLASS:
507 case MONO_TYPE_OBJECT:
508 case MONO_TYPE_STRING:
509 case MONO_TYPE_SZARRAY:
510 case MONO_TYPE_ARRAY:
511 add_general (&gr, &stack_size, ainfo);
513 case MONO_TYPE_GENERICINST:
514 if (!mono_type_generic_inst_is_valuetype (ptype)) {
515 add_general (&gr, &stack_size, ainfo);
519 case MONO_TYPE_VALUETYPE:
520 case MONO_TYPE_TYPEDBYREF:
521 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
525 add_general_pair (&gr, &stack_size, ainfo);
528 add_float (&fr, &stack_size, ainfo, FALSE);
531 add_float (&fr, &stack_size, ainfo, TRUE);
534 g_error ("unexpected type 0x%x", ptype->type);
535 g_assert_not_reached ();
539 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
541 fr = FLOAT_PARAM_REGS;
543 /* Emit the signature cookie just before the implicit arguments */
544 add_general (&gr, &stack_size, &cinfo->sig_cookie);
547 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
548 cinfo->need_stack_align = TRUE;
549 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
550 stack_size += cinfo->stack_align_amount;
553 cinfo->stack_usage = stack_size;
554 cinfo->reg_usage = gr;
555 cinfo->freg_usage = fr;
560 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
562 int n = sig->hasthis + sig->param_count;
566 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
568 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
570 return get_call_info_internal (gsctx, cinfo, sig);
574 * mono_arch_get_argument_info:
575 * @csig: a method signature
576 * @param_count: the number of parameters to consider
577 * @arg_info: an array to store the result infos
579 * Gathers information on parameters such as size, alignment and
580 * padding. arg_info should be large enought to hold param_count + 1 entries.
582 * Returns the size of the argument area on the stack.
583 * This should be signal safe, since it is called from
584 * mono_arch_find_jit_info ().
585 * FIXME: The metadata calls might not be signal safe.
588 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
590 int len, k, args_size = 0;
596 /* Avoid g_malloc as it is not signal safe */
597 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
598 cinfo = (CallInfo*)g_newa (guint8*, len);
599 memset (cinfo, 0, len);
601 cinfo = get_call_info_internal (gsctx, cinfo, csig);
603 arg_info [0].offset = offset;
605 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
606 args_size += sizeof (gpointer);
611 args_size += sizeof (gpointer);
615 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
616 /* Emitted after this */
617 args_size += sizeof (gpointer);
621 arg_info [0].size = args_size;
623 for (k = 0; k < param_count; k++) {
624 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
626 /* ignore alignment for now */
629 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
630 arg_info [k].pad = pad;
632 arg_info [k + 1].pad = 0;
633 arg_info [k + 1].size = size;
635 arg_info [k + 1].offset = offset;
638 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
639 /* Emitted after the first arg */
640 args_size += sizeof (gpointer);
645 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
646 align = MONO_ARCH_FRAME_ALIGNMENT;
649 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
650 arg_info [k].pad = pad;
656 mono_x86_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
661 c1 = get_call_info (NULL, NULL, caller_sig);
662 c2 = get_call_info (NULL, NULL, callee_sig);
663 res = c1->stack_usage >= c2->stack_usage;
664 if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
665 /* An address on the callee's stack is passed as the first argument */
674 #if !defined(__native_client__)
675 static const guchar cpuid_impl [] = {
676 0x55, /* push %ebp */
677 0x89, 0xe5, /* mov %esp,%ebp */
678 0x53, /* push %ebx */
679 0x8b, 0x45, 0x08, /* mov 0x8(%ebp),%eax */
680 0x0f, 0xa2, /* cpuid */
681 0x50, /* push %eax */
682 0x8b, 0x45, 0x10, /* mov 0x10(%ebp),%eax */
683 0x89, 0x18, /* mov %ebx,(%eax) */
684 0x8b, 0x45, 0x14, /* mov 0x14(%ebp),%eax */
685 0x89, 0x08, /* mov %ecx,(%eax) */
686 0x8b, 0x45, 0x18, /* mov 0x18(%ebp),%eax */
687 0x89, 0x10, /* mov %edx,(%eax) */
689 0x8b, 0x55, 0x0c, /* mov 0xc(%ebp),%edx */
690 0x89, 0x02, /* mov %eax,(%edx) */
696 static const guchar cpuid_impl [] = {
697 0x55, /* push %ebp */
698 0x89, 0xe5, /* mov %esp,%ebp */
699 0x53, /* push %ebx */
700 0x8b, 0x45, 0x08, /* mov 0x8(%ebp),%eax */
701 0x0f, 0xa2, /* cpuid */
702 0x50, /* push %eax */
703 0x8b, 0x45, 0x10, /* mov 0x10(%ebp),%eax */
704 0x89, 0x18, /* mov %ebx,(%eax) */
705 0x8b, 0x45, 0x14, /* mov 0x14(%ebp),%eax */
706 0x89, 0x08, /* mov %ecx,(%eax) */
707 0x8b, 0x45, 0x18, /* mov 0x18(%ebp),%eax */
708 0x89, 0x10, /* mov %edx,(%eax) */
710 0x8b, 0x55, 0x0c, /* mov 0xc(%ebp),%edx */
711 0x89, 0x02, /* mov %eax,(%edx) */
714 0x59, 0x83, 0xe1, 0xe0, 0xff, 0xe1 /* naclret */
718 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
721 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
723 #if defined(__native_client__)
724 static CpuidFunc func = NULL;
727 ptr = mono_global_codeman_reserve (sizeof (cpuid_impl));
728 memcpy(ptr, cpuid_impl, sizeof(cpuid_impl));
729 end_ptr = ptr + sizeof(cpuid_impl);
730 nacl_global_codeman_validate (&ptr, sizeof(cpuid_impl), &end_ptr);
731 func = (CpuidFunc)ptr;
733 func (id, p_eax, p_ebx, p_ecx, p_edx);
737 __asm__ __volatile__ (
740 "movl %%eax, %%edx\n"
741 "xorl $0x200000, %%eax\n"
746 "xorl %%edx, %%eax\n"
747 "andl $0x200000, %%eax\n"
769 /* Have to use the code manager to get around WinXP DEP */
770 static CpuidFunc func = NULL;
773 ptr = mono_global_codeman_reserve (sizeof (cpuid_impl));
774 memcpy (ptr, cpuid_impl, sizeof (cpuid_impl));
775 func = (CpuidFunc)ptr;
777 func (id, p_eax, p_ebx, p_ecx, p_edx);
780 * We use this approach because of issues with gcc and pic code, see:
781 * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
782 __asm__ __volatile__ ("cpuid"
783 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
793 * Initialize the cpu to execute managed code.
796 mono_arch_cpu_init (void)
798 /* spec compliance requires running with double precision */
802 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
803 fpcw &= ~X86_FPCW_PRECC_MASK;
804 fpcw |= X86_FPCW_PREC_DOUBLE;
805 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
806 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
808 _control87 (_PC_53, MCW_PC);
813 * Initialize architecture specific code.
816 mono_arch_init (void)
818 InitializeCriticalSection (&mini_arch_mutex);
820 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
821 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
822 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
824 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
825 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
826 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
827 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
832 * Cleanup architecture specific code.
835 mono_arch_cleanup (void)
838 mono_vfree (ss_trigger_page, mono_pagesize ());
840 mono_vfree (bp_trigger_page, mono_pagesize ());
841 DeleteCriticalSection (&mini_arch_mutex);
845 * This function returns the optimizations supported on this cpu.
848 mono_arch_cpu_optimizations (guint32 *exclude_mask)
850 #if !defined(__native_client__)
851 int eax, ebx, ecx, edx;
857 /* The cpuid function allocates from the global codeman */
860 /* Feature Flags function, flags returned in EDX. */
861 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
862 if (edx & (1 << 15)) {
863 opts |= MONO_OPT_CMOV;
865 opts |= MONO_OPT_FCMOV;
867 *exclude_mask |= MONO_OPT_FCMOV;
869 *exclude_mask |= MONO_OPT_CMOV;
871 opts |= MONO_OPT_SSE2;
873 *exclude_mask |= MONO_OPT_SSE2;
875 #ifdef MONO_ARCH_SIMD_INTRINSICS
876 /*SIMD intrinsics require at least SSE2.*/
877 if (!(opts & MONO_OPT_SSE2))
878 *exclude_mask |= MONO_OPT_SIMD;
883 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
888 * This function test for all SSE functions supported.
890 * Returns a bitmask corresponding to all supported versions.
894 mono_arch_cpu_enumerate_simd_versions (void)
896 int eax, ebx, ecx, edx;
897 guint32 sse_opts = 0;
900 /* The cpuid function allocates from the global codeman */
903 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
905 sse_opts |= SIMD_VERSION_SSE1;
907 sse_opts |= SIMD_VERSION_SSE2;
909 sse_opts |= SIMD_VERSION_SSE3;
911 sse_opts |= SIMD_VERSION_SSSE3;
913 sse_opts |= SIMD_VERSION_SSE41;
915 sse_opts |= SIMD_VERSION_SSE42;
918 /* Yes, all this needs to be done to check for sse4a.
919 See: "Amd: CPUID Specification"
921 if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
922 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
923 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
924 cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
926 sse_opts |= SIMD_VERSION_SSE4a;
935 * Determine whenever the trap whose info is in SIGINFO is caused by
939 mono_arch_is_int_overflow (void *sigctx, void *info)
944 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
946 ip = (guint8*)ctx.eip;
948 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
952 switch (x86_modrm_rm (ip [1])) {
972 g_assert_not_reached ();
984 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
989 for (i = 0; i < cfg->num_varinfo; i++) {
990 MonoInst *ins = cfg->varinfo [i];
991 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
994 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
997 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
998 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1001 /* we dont allocate I1 to registers because there is no simply way to sign extend
1002 * 8bit quantities in caller saved registers on x86 */
1003 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
1004 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1005 g_assert (i == vmv->idx);
1006 vars = g_list_prepend (vars, vmv);
1010 vars = mono_varlist_sort (cfg, vars, 0);
1016 mono_arch_get_global_int_regs (MonoCompile *cfg)
1020 /* we can use 3 registers for global allocation */
1021 regs = g_list_prepend (regs, (gpointer)X86_EBX);
1022 regs = g_list_prepend (regs, (gpointer)X86_ESI);
1023 regs = g_list_prepend (regs, (gpointer)X86_EDI);
1029 * mono_arch_regalloc_cost:
1031 * Return the cost, in number of memory references, of the action of
1032 * allocating the variable VMV into a register during global register
1036 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1038 MonoInst *ins = cfg->varinfo [vmv->idx];
1040 if (cfg->method->save_lmf)
1041 /* The register is already saved */
1042 return (ins->opcode == OP_ARG) ? 1 : 0;
1044 /* push+pop+possible load if it is an argument */
1045 return (ins->opcode == OP_ARG) ? 3 : 2;
1049 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
1051 static int inited = FALSE;
1052 static int count = 0;
1054 if (cfg->arch.need_stack_frame_inited) {
1055 g_assert (cfg->arch.need_stack_frame == flag);
1059 cfg->arch.need_stack_frame = flag;
1060 cfg->arch.need_stack_frame_inited = TRUE;
1066 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
1071 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
1075 needs_stack_frame (MonoCompile *cfg)
1077 MonoMethodSignature *sig;
1078 MonoMethodHeader *header;
1079 gboolean result = FALSE;
1081 #if defined(__APPLE__)
1082 /*OSX requires stack frame code to have the correct alignment. */
1086 if (cfg->arch.need_stack_frame_inited)
1087 return cfg->arch.need_stack_frame;
1089 header = cfg->header;
1090 sig = mono_method_signature (cfg->method);
1092 if (cfg->disable_omit_fp)
1094 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1096 else if (cfg->method->save_lmf)
1098 else if (cfg->stack_offset)
1100 else if (cfg->param_area)
1102 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1104 else if (header->num_clauses)
1106 else if (sig->param_count + sig->hasthis)
1108 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1110 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1111 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1114 set_needs_stack_frame (cfg, result);
1116 return cfg->arch.need_stack_frame;
1120 * Set var information according to the calling convention. X86 version.
1121 * The locals var stuff should most likely be split in another method.
1124 mono_arch_allocate_vars (MonoCompile *cfg)
1126 MonoMethodSignature *sig;
1127 MonoMethodHeader *header;
1129 guint32 locals_stack_size, locals_stack_align;
1134 header = cfg->header;
1135 sig = mono_method_signature (cfg->method);
1137 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1139 cfg->frame_reg = X86_EBP;
1142 /* Reserve space to save LMF and caller saved registers */
1144 if (cfg->method->save_lmf) {
1145 offset += sizeof (MonoLMF);
1147 if (cfg->used_int_regs & (1 << X86_EBX)) {
1151 if (cfg->used_int_regs & (1 << X86_EDI)) {
1155 if (cfg->used_int_regs & (1 << X86_ESI)) {
1160 switch (cinfo->ret.storage) {
1161 case ArgValuetypeInReg:
1162 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1164 cfg->ret->opcode = OP_REGOFFSET;
1165 cfg->ret->inst_basereg = X86_EBP;
1166 cfg->ret->inst_offset = - offset;
1172 /* Allocate locals */
1173 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1174 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1175 char *mname = mono_method_full_name (cfg->method, TRUE);
1176 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1177 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1181 if (locals_stack_align) {
1182 int prev_offset = offset;
1184 offset += (locals_stack_align - 1);
1185 offset &= ~(locals_stack_align - 1);
1187 while (prev_offset < offset) {
1189 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1192 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1193 cfg->locals_max_stack_offset = - offset;
1195 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1196 * have locals larger than 8 bytes we need to make sure that
1197 * they have the appropriate offset.
1199 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1200 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1201 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1202 if (offsets [i] != -1) {
1203 MonoInst *inst = cfg->varinfo [i];
1204 inst->opcode = OP_REGOFFSET;
1205 inst->inst_basereg = X86_EBP;
1206 inst->inst_offset = - (offset + offsets [i]);
1207 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1210 offset += locals_stack_size;
1214 * Allocate arguments+return value
1217 switch (cinfo->ret.storage) {
1219 if (cfg->vret_addr) {
1221 * In the new IR, the cfg->vret_addr variable represents the
1222 * vtype return value.
1224 cfg->vret_addr->opcode = OP_REGOFFSET;
1225 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1226 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1227 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1228 printf ("vret_addr =");
1229 mono_print_ins (cfg->vret_addr);
1232 cfg->ret->opcode = OP_REGOFFSET;
1233 cfg->ret->inst_basereg = X86_EBP;
1234 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1237 case ArgValuetypeInReg:
1240 cfg->ret->opcode = OP_REGVAR;
1241 cfg->ret->inst_c0 = cinfo->ret.reg;
1242 cfg->ret->dreg = cinfo->ret.reg;
1245 case ArgOnFloatFpStack:
1246 case ArgOnDoubleFpStack:
1249 g_assert_not_reached ();
1252 if (sig->call_convention == MONO_CALL_VARARG) {
1253 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1254 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1257 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1258 ArgInfo *ainfo = &cinfo->args [i];
1259 inst = cfg->args [i];
1260 if (inst->opcode != OP_REGVAR) {
1261 inst->opcode = OP_REGOFFSET;
1262 inst->inst_basereg = X86_EBP;
1264 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1267 cfg->stack_offset = offset;
1271 mono_arch_create_vars (MonoCompile *cfg)
1273 MonoMethodSignature *sig;
1276 sig = mono_method_signature (cfg->method);
1278 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1280 if (cinfo->ret.storage == ArgValuetypeInReg)
1281 cfg->ret_var_is_local = TRUE;
1282 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig->ret) || mini_is_gsharedvt_variable_type (cfg, sig->ret))) {
1283 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1286 cfg->arch_eh_jit_info = 1;
1290 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1291 * so we try to do it just once when we have multiple fp arguments in a row.
1292 * We don't use this mechanism generally because for int arguments the generated code
1293 * is slightly bigger and new generation cpus optimize away the dependency chains
1294 * created by push instructions on the esp value.
1295 * fp_arg_setup is the first argument in the execution sequence where the esp register
1298 static G_GNUC_UNUSED int
1299 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1304 for (; start_arg < sig->param_count; ++start_arg) {
1305 t = mini_type_get_underlying_type (NULL, sig->params [start_arg]);
1306 if (!t->byref && t->type == MONO_TYPE_R8) {
1307 fp_space += sizeof (double);
1308 *fp_arg_setup = start_arg;
1317 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1319 MonoMethodSignature *tmp_sig;
1323 * mono_ArgIterator_Setup assumes the signature cookie is
1324 * passed first and all the arguments which were before it are
1325 * passed on the stack after the signature. So compensate by
1326 * passing a different signature.
1328 tmp_sig = mono_metadata_signature_dup (call->signature);
1329 tmp_sig->param_count -= call->signature->sentinelpos;
1330 tmp_sig->sentinelpos = 0;
1331 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1333 if (cfg->compile_aot) {
1334 sig_reg = mono_alloc_ireg (cfg);
1335 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1336 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, sig_reg);
1338 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1344 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1349 LLVMCallInfo *linfo;
1352 n = sig->param_count + sig->hasthis;
1354 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1356 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1359 * LLVM always uses the native ABI while we use our own ABI, the
1360 * only difference is the handling of vtypes:
1361 * - we only pass/receive them in registers in some cases, and only
1362 * in 1 or 2 integer registers.
1364 if (cinfo->ret.storage == ArgValuetypeInReg) {
1366 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1367 cfg->disable_llvm = TRUE;
1371 cfg->exception_message = g_strdup ("vtype ret in call");
1372 cfg->disable_llvm = TRUE;
1374 linfo->ret.storage = LLVMArgVtypeInReg;
1375 for (j = 0; j < 2; ++j)
1376 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1380 if (mini_type_is_vtype (cfg, sig->ret) && cinfo->ret.storage == ArgInIReg) {
1381 /* Vtype returned using a hidden argument */
1382 linfo->ret.storage = LLVMArgVtypeRetAddr;
1383 linfo->vret_arg_index = cinfo->vret_arg_index;
1386 if (mini_type_is_vtype (cfg, sig->ret) && cinfo->ret.storage != ArgInIReg) {
1388 cfg->exception_message = g_strdup ("vtype ret in call");
1389 cfg->disable_llvm = TRUE;
1392 for (i = 0; i < n; ++i) {
1393 ainfo = cinfo->args + i;
1395 if (i >= sig->hasthis)
1396 t = sig->params [i - sig->hasthis];
1398 t = &mono_defaults.int_class->byval_arg;
1400 linfo->args [i].storage = LLVMArgNone;
1402 switch (ainfo->storage) {
1404 linfo->args [i].storage = LLVMArgInIReg;
1406 case ArgInDoubleSSEReg:
1407 case ArgInFloatSSEReg:
1408 linfo->args [i].storage = LLVMArgInFPReg;
1411 if (mini_type_is_vtype (cfg, t)) {
1412 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1413 /* LLVM seems to allocate argument space for empty structures too */
1414 linfo->args [i].storage = LLVMArgNone;
1416 linfo->args [i].storage = LLVMArgVtypeByVal;
1418 linfo->args [i].storage = LLVMArgInIReg;
1420 if (t->type == MONO_TYPE_R4)
1421 linfo->args [i].storage = LLVMArgInFPReg;
1422 else if (t->type == MONO_TYPE_R8)
1423 linfo->args [i].storage = LLVMArgInFPReg;
1427 case ArgValuetypeInReg:
1429 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1430 cfg->disable_llvm = TRUE;
1434 cfg->exception_message = g_strdup ("vtype arg");
1435 cfg->disable_llvm = TRUE;
1437 linfo->args [i].storage = LLVMArgVtypeInReg;
1438 for (j = 0; j < 2; ++j)
1439 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1443 cfg->exception_message = g_strdup ("ainfo->storage");
1444 cfg->disable_llvm = TRUE;
1454 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1456 if (cfg->compute_gc_maps) {
1459 /* On x86, the offsets are from the sp value before the start of the call sequence */
1461 t = &mono_defaults.int_class->byval_arg;
1462 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1467 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1470 MonoMethodSignature *sig;
1473 int sentinelpos = 0, sp_offset = 0;
1475 sig = call->signature;
1476 n = sig->param_count + sig->hasthis;
1478 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1480 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1481 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1483 if (cinfo->need_stack_align) {
1484 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1485 arg->dreg = X86_ESP;
1486 arg->sreg1 = X86_ESP;
1487 arg->inst_imm = cinfo->stack_align_amount;
1488 MONO_ADD_INS (cfg->cbb, arg);
1489 for (i = 0; i < cinfo->stack_align_amount; i += sizeof (mgreg_t)) {
1492 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1496 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1497 if (cinfo->ret.storage == ArgValuetypeInReg) {
1499 * Tell the JIT to use a more efficient calling convention: call using
1500 * OP_CALL, compute the result location after the call, and save the
1503 call->vret_in_reg = TRUE;
1505 NULLIFY_INS (call->vret_var);
1509 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1511 /* Handle the case where there are no implicit arguments */
1512 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1513 emit_sig_cookie (cfg, call, cinfo);
1515 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1518 /* Arguments are pushed in the reverse order */
1519 for (i = n - 1; i >= 0; i --) {
1520 ArgInfo *ainfo = cinfo->args + i;
1521 MonoType *orig_type, *t;
1524 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1525 /* Push the vret arg before the first argument */
1527 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1528 vtarg->type = STACK_MP;
1529 vtarg->sreg1 = call->vret_var->dreg;
1530 MONO_ADD_INS (cfg->cbb, vtarg);
1532 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1535 if (i >= sig->hasthis)
1536 t = sig->params [i - sig->hasthis];
1538 t = &mono_defaults.int_class->byval_arg;
1540 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1542 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1544 in = call->args [i];
1545 arg->cil_code = in->cil_code;
1546 arg->sreg1 = in->dreg;
1547 arg->type = in->type;
1549 g_assert (in->dreg != -1);
1551 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1555 g_assert (in->klass);
1557 if (t->type == MONO_TYPE_TYPEDBYREF) {
1558 size = sizeof (MonoTypedRef);
1559 align = sizeof (gpointer);
1562 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1566 arg->opcode = OP_OUTARG_VT;
1567 arg->sreg1 = in->dreg;
1568 arg->klass = in->klass;
1569 arg->backend.size = size;
1571 MONO_ADD_INS (cfg->cbb, arg);
1573 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1578 switch (ainfo->storage) {
1580 arg->opcode = OP_X86_PUSH;
1582 if (t->type == MONO_TYPE_R4) {
1583 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1584 arg->opcode = OP_STORER4_MEMBASE_REG;
1585 arg->inst_destbasereg = X86_ESP;
1586 arg->inst_offset = 0;
1588 } else if (t->type == MONO_TYPE_R8) {
1589 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1590 arg->opcode = OP_STORER8_MEMBASE_REG;
1591 arg->inst_destbasereg = X86_ESP;
1592 arg->inst_offset = 0;
1594 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1596 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1602 g_assert_not_reached ();
1605 MONO_ADD_INS (cfg->cbb, arg);
1607 sp_offset += argsize;
1609 if (cfg->compute_gc_maps) {
1611 /* FIXME: The == STACK_OBJ check might be fragile ? */
1612 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1614 if (call->need_unbox_trampoline)
1615 /* The unbox trampoline transforms this into a managed pointer */
1616 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.int_class->this_arg);
1618 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.object_class->byval_arg);
1620 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1624 for (j = 0; j < argsize; j += 4)
1625 emit_gc_param_slot_def (cfg, sp_offset - j, NULL);
1630 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1631 /* Emit the signature cookie just before the implicit arguments */
1632 emit_sig_cookie (cfg, call, cinfo);
1634 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1638 if (sig->ret && (MONO_TYPE_ISSTRUCT (sig->ret) || cinfo->vtype_retaddr)) {
1641 if (cinfo->ret.storage == ArgValuetypeInReg) {
1644 else if (cinfo->ret.storage == ArgInIReg) {
1646 /* The return address is passed in a register */
1647 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1648 vtarg->sreg1 = call->inst.dreg;
1649 vtarg->dreg = mono_alloc_ireg (cfg);
1650 MONO_ADD_INS (cfg->cbb, vtarg);
1652 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1653 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1655 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1656 vtarg->type = STACK_MP;
1657 vtarg->sreg1 = call->vret_var->dreg;
1658 MONO_ADD_INS (cfg->cbb, vtarg);
1660 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1663 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1664 if (cinfo->ret.storage != ArgValuetypeInReg)
1665 cinfo->stack_usage -= 4;
1668 call->stack_usage = cinfo->stack_usage;
1669 call->stack_align_amount = cinfo->stack_align_amount;
1670 cfg->arch.param_area_size = MAX (cfg->arch.param_area_size, sp_offset);
1674 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1677 int size = ins->backend.size;
1680 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1681 arg->sreg1 = src->dreg;
1683 MONO_ADD_INS (cfg->cbb, arg);
1684 } else if (size <= 20) {
1685 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1686 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1688 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1689 arg->inst_basereg = src->dreg;
1690 arg->inst_offset = 0;
1691 arg->inst_imm = size;
1693 MONO_ADD_INS (cfg->cbb, arg);
1698 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1700 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1703 if (ret->type == MONO_TYPE_R4) {
1704 if (COMPILE_LLVM (cfg))
1705 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1708 } else if (ret->type == MONO_TYPE_R8) {
1709 if (COMPILE_LLVM (cfg))
1710 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1713 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1714 if (COMPILE_LLVM (cfg))
1715 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1717 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1718 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1724 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1728 * Allow tracing to work with this interface (with an optional argument)
1731 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1735 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1736 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1738 /* if some args are passed in registers, we need to save them here */
1739 x86_push_reg (code, X86_EBP);
1741 if (cfg->compile_aot) {
1742 x86_push_imm (code, cfg->method);
1743 x86_mov_reg_imm (code, X86_EAX, func);
1744 x86_call_reg (code, X86_EAX);
1746 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1747 x86_push_imm (code, cfg->method);
1748 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1749 x86_call_code (code, 0);
1751 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1765 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1768 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1769 MonoMethod *method = cfg->method;
1770 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1772 switch (ret_type->type) {
1773 case MONO_TYPE_VOID:
1774 /* special case string .ctor icall */
1775 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1776 save_mode = SAVE_EAX;
1777 stack_usage = enable_arguments ? 8 : 4;
1779 save_mode = SAVE_NONE;
1783 save_mode = SAVE_EAX_EDX;
1784 stack_usage = enable_arguments ? 16 : 8;
1788 save_mode = SAVE_FP;
1789 stack_usage = enable_arguments ? 16 : 8;
1791 case MONO_TYPE_GENERICINST:
1792 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1793 save_mode = SAVE_EAX;
1794 stack_usage = enable_arguments ? 8 : 4;
1798 case MONO_TYPE_VALUETYPE:
1799 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1800 save_mode = SAVE_STRUCT;
1801 stack_usage = enable_arguments ? 4 : 0;
1804 save_mode = SAVE_EAX;
1805 stack_usage = enable_arguments ? 8 : 4;
1809 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1811 switch (save_mode) {
1813 x86_push_reg (code, X86_EDX);
1814 x86_push_reg (code, X86_EAX);
1815 if (enable_arguments) {
1816 x86_push_reg (code, X86_EDX);
1817 x86_push_reg (code, X86_EAX);
1822 x86_push_reg (code, X86_EAX);
1823 if (enable_arguments) {
1824 x86_push_reg (code, X86_EAX);
1829 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1830 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1831 if (enable_arguments) {
1832 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1833 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1838 if (enable_arguments) {
1839 x86_push_membase (code, X86_EBP, 8);
1848 if (cfg->compile_aot) {
1849 x86_push_imm (code, method);
1850 x86_mov_reg_imm (code, X86_EAX, func);
1851 x86_call_reg (code, X86_EAX);
1853 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1854 x86_push_imm (code, method);
1855 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1856 x86_call_code (code, 0);
1859 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1861 switch (save_mode) {
1863 x86_pop_reg (code, X86_EAX);
1864 x86_pop_reg (code, X86_EDX);
1867 x86_pop_reg (code, X86_EAX);
1870 x86_fld_membase (code, X86_ESP, 0, TRUE);
1871 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1878 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1883 #define EMIT_COND_BRANCH(ins,cond,sign) \
1884 if (ins->inst_true_bb->native_offset) { \
1885 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1887 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1888 if ((cfg->opt & MONO_OPT_BRANCH) && \
1889 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1890 x86_branch8 (code, cond, 0, sign); \
1892 x86_branch32 (code, cond, 0, sign); \
1896 * Emit an exception if condition is fail and
1897 * if possible do a directly branch to target
1899 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1901 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1902 if (tins == NULL) { \
1903 mono_add_patch_info (cfg, code - cfg->native_code, \
1904 MONO_PATCH_INFO_EXC, exc_name); \
1905 x86_branch32 (code, cond, 0, signed); \
1907 EMIT_COND_BRANCH (tins, cond, signed); \
1911 #define EMIT_FPCOMPARE(code) do { \
1912 x86_fcompp (code); \
1913 x86_fnstsw (code); \
1918 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1920 gboolean needs_paddings = TRUE;
1922 MonoJumpInfo *jinfo = NULL;
1924 if (cfg->abs_patches) {
1925 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1926 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1927 needs_paddings = FALSE;
1930 if (cfg->compile_aot)
1931 needs_paddings = FALSE;
1932 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1933 This is required for code patching to be safe on SMP machines.
1935 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1936 #ifndef __native_client_codegen__
1937 if (needs_paddings && pad_size)
1938 x86_padding (code, 4 - pad_size);
1941 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1942 x86_call_code (code, 0);
1947 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1950 * mono_peephole_pass_1:
1952 * Perform peephole opts which should/can be performed before local regalloc
1955 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1959 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1960 MonoInst *last_ins = ins->prev;
1962 switch (ins->opcode) {
1965 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1967 * X86_LEA is like ADD, but doesn't have the
1968 * sreg1==dreg restriction.
1970 ins->opcode = OP_X86_LEA_MEMBASE;
1971 ins->inst_basereg = ins->sreg1;
1972 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1973 ins->opcode = OP_X86_INC_REG;
1977 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1978 ins->opcode = OP_X86_LEA_MEMBASE;
1979 ins->inst_basereg = ins->sreg1;
1980 ins->inst_imm = -ins->inst_imm;
1981 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1982 ins->opcode = OP_X86_DEC_REG;
1984 case OP_COMPARE_IMM:
1985 case OP_ICOMPARE_IMM:
1986 /* OP_COMPARE_IMM (reg, 0)
1988 * OP_X86_TEST_NULL (reg)
1991 ins->opcode = OP_X86_TEST_NULL;
1993 case OP_X86_COMPARE_MEMBASE_IMM:
1995 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1996 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1998 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1999 * OP_COMPARE_IMM reg, imm
2001 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2003 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2004 ins->inst_basereg == last_ins->inst_destbasereg &&
2005 ins->inst_offset == last_ins->inst_offset) {
2006 ins->opcode = OP_COMPARE_IMM;
2007 ins->sreg1 = last_ins->sreg1;
2009 /* check if we can remove cmp reg,0 with test null */
2011 ins->opcode = OP_X86_TEST_NULL;
2015 case OP_X86_PUSH_MEMBASE:
2016 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
2017 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2018 ins->inst_basereg == last_ins->inst_destbasereg &&
2019 ins->inst_offset == last_ins->inst_offset) {
2020 ins->opcode = OP_X86_PUSH;
2021 ins->sreg1 = last_ins->sreg1;
2026 mono_peephole_ins (bb, ins);
2031 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2035 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2036 switch (ins->opcode) {
2038 /* reg = 0 -> XOR (reg, reg) */
2039 /* XOR sets cflags on x86, so we cant do it always */
2040 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2043 ins->opcode = OP_IXOR;
2044 ins->sreg1 = ins->dreg;
2045 ins->sreg2 = ins->dreg;
2048 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2049 * since it takes 3 bytes instead of 7.
2051 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2052 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2053 ins2->opcode = OP_STORE_MEMBASE_REG;
2054 ins2->sreg1 = ins->dreg;
2056 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2057 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2058 ins2->sreg1 = ins->dreg;
2060 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2061 /* Continue iteration */
2070 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2071 ins->opcode = OP_X86_INC_REG;
2075 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2076 ins->opcode = OP_X86_DEC_REG;
2080 mono_peephole_ins (bb, ins);
2085 * mono_arch_lowering_pass:
2087 * Converts complex opcodes into simpler ones so that each IR instruction
2088 * corresponds to one machine instruction.
2091 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2093 MonoInst *ins, *next;
2096 * FIXME: Need to add more instructions, but the current machine
2097 * description can't model some parts of the composite instructions like
2100 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2101 switch (ins->opcode) {
2104 case OP_IDIV_UN_IMM:
2105 case OP_IREM_UN_IMM:
2107 * Keep the cases where we could generated optimized code, otherwise convert
2108 * to the non-imm variant.
2110 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2112 mono_decompose_op_imm (cfg, bb, ins);
2119 bb->max_vreg = cfg->next_vreg;
2123 branch_cc_table [] = {
2124 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2125 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2126 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2129 /* Maps CMP_... constants to X86_CC_... constants */
2132 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2133 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2137 cc_signed_table [] = {
2138 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2139 FALSE, FALSE, FALSE, FALSE
2142 static unsigned char*
2143 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2145 #define XMM_TEMP_REG 0
2146 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2147 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2148 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2149 /* optimize by assigning a local var for this use so we avoid
2150 * the stack manipulations */
2151 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2152 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2153 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2154 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2155 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2157 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2159 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2162 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2163 x86_fnstcw_membase(code, X86_ESP, 0);
2164 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2165 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2166 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2167 x86_fldcw_membase (code, X86_ESP, 2);
2169 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2170 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2171 x86_pop_reg (code, dreg);
2172 /* FIXME: need the high register
2173 * x86_pop_reg (code, dreg_high);
2176 x86_push_reg (code, X86_EAX); // SP = SP - 4
2177 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2178 x86_pop_reg (code, dreg);
2180 x86_fldcw_membase (code, X86_ESP, 0);
2181 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2184 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2186 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2190 static unsigned char*
2191 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2193 int sreg = tree->sreg1;
2194 int need_touch = FALSE;
2196 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2205 * If requested stack size is larger than one page,
2206 * perform stack-touch operation
2209 * Generate stack probe code.
2210 * Under Windows, it is necessary to allocate one page at a time,
2211 * "touching" stack after each successful sub-allocation. This is
2212 * because of the way stack growth is implemented - there is a
2213 * guard page before the lowest stack page that is currently commited.
2214 * Stack normally grows sequentially so OS traps access to the
2215 * guard page and commits more pages when needed.
2217 x86_test_reg_imm (code, sreg, ~0xFFF);
2218 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2220 br[2] = code; /* loop */
2221 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2222 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2225 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2226 * that follows only initializes the last part of the area.
2228 /* Same as the init code below with size==0x1000 */
2229 if (tree->flags & MONO_INST_INIT) {
2230 x86_push_reg (code, X86_EAX);
2231 x86_push_reg (code, X86_ECX);
2232 x86_push_reg (code, X86_EDI);
2233 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2234 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2235 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2237 x86_prefix (code, X86_REP_PREFIX);
2239 x86_pop_reg (code, X86_EDI);
2240 x86_pop_reg (code, X86_ECX);
2241 x86_pop_reg (code, X86_EAX);
2244 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2245 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2246 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2247 x86_patch (br[3], br[2]);
2248 x86_test_reg_reg (code, sreg, sreg);
2249 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2250 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2252 br[1] = code; x86_jump8 (code, 0);
2254 x86_patch (br[0], code);
2255 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2256 x86_patch (br[1], code);
2257 x86_patch (br[4], code);
2260 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2262 if (tree->flags & MONO_INST_INIT) {
2264 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2265 x86_push_reg (code, X86_EAX);
2268 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2269 x86_push_reg (code, X86_ECX);
2272 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2273 x86_push_reg (code, X86_EDI);
2277 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2278 if (sreg != X86_ECX)
2279 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2280 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2282 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2284 x86_prefix (code, X86_REP_PREFIX);
2287 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2288 x86_pop_reg (code, X86_EDI);
2289 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2290 x86_pop_reg (code, X86_ECX);
2291 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2292 x86_pop_reg (code, X86_EAX);
2299 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2301 /* Move return value to the target register */
2302 switch (ins->opcode) {
2305 case OP_CALL_MEMBASE:
2306 if (ins->dreg != X86_EAX)
2307 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2317 static int tls_gs_offset;
2321 mono_x86_have_tls_get (void)
2324 static gboolean have_tls_get = FALSE;
2325 static gboolean inited = FALSE;
2329 return have_tls_get;
2331 ins = (guint32*)pthread_getspecific;
2333 * We're looking for these two instructions:
2335 * mov 0x4(%esp),%eax
2336 * mov %gs:[offset](,%eax,4),%eax
2338 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2339 tls_gs_offset = ins [2];
2343 return have_tls_get;
2344 #elif defined(TARGET_ANDROID)
2352 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2354 #if defined(__APPLE__)
2355 x86_prefix (code, X86_GS_PREFIX);
2356 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2357 #elif defined(TARGET_WIN32)
2358 g_assert_not_reached ();
2360 x86_prefix (code, X86_GS_PREFIX);
2361 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2367 * mono_x86_emit_tls_get:
2368 * @code: buffer to store code to
2369 * @dreg: hard register where to place the result
2370 * @tls_offset: offset info
2372 * mono_x86_emit_tls_get emits in @code the native code that puts in
2373 * the dreg register the item in the thread local storage identified
2376 * Returns: a pointer to the end of the stored code
2379 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2381 #if defined(__APPLE__)
2382 x86_prefix (code, X86_GS_PREFIX);
2383 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2384 #elif defined(TARGET_WIN32)
2386 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2387 * Journal and/or a disassembly of the TlsGet () function.
2389 g_assert (tls_offset < 64);
2390 x86_prefix (code, X86_FS_PREFIX);
2391 x86_mov_reg_mem (code, dreg, 0x18, 4);
2392 /* Dunno what this does but TlsGetValue () contains it */
2393 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2394 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2396 if (optimize_for_xen) {
2397 x86_prefix (code, X86_GS_PREFIX);
2398 x86_mov_reg_mem (code, dreg, 0, 4);
2399 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2401 x86_prefix (code, X86_GS_PREFIX);
2402 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2409 * emit_load_volatile_arguments:
2411 * Load volatile arguments from the stack to the original input registers.
2412 * Required before a tail call.
2415 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2417 MonoMethod *method = cfg->method;
2418 MonoMethodSignature *sig;
2423 /* FIXME: Generate intermediate code instead */
2425 sig = mono_method_signature (method);
2427 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2429 /* This is the opposite of the code in emit_prolog */
2431 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2432 ArgInfo *ainfo = cinfo->args + i;
2434 inst = cfg->args [i];
2436 if (sig->hasthis && (i == 0))
2437 arg_type = &mono_defaults.object_class->byval_arg;
2439 arg_type = sig->params [i - sig->hasthis];
2442 * On x86, the arguments are either in their original stack locations, or in
2445 if (inst->opcode == OP_REGVAR) {
2446 g_assert (ainfo->storage == ArgOnStack);
2448 x86_mov_membase_reg (code, X86_EBP, inst->inst_offset, inst->dreg, 4);
2455 #define REAL_PRINT_REG(text,reg) \
2456 mono_assert (reg >= 0); \
2457 x86_push_reg (code, X86_EAX); \
2458 x86_push_reg (code, X86_EDX); \
2459 x86_push_reg (code, X86_ECX); \
2460 x86_push_reg (code, reg); \
2461 x86_push_imm (code, reg); \
2462 x86_push_imm (code, text " %d %p\n"); \
2463 x86_mov_reg_imm (code, X86_EAX, printf); \
2464 x86_call_reg (code, X86_EAX); \
2465 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2466 x86_pop_reg (code, X86_ECX); \
2467 x86_pop_reg (code, X86_EDX); \
2468 x86_pop_reg (code, X86_EAX);
2470 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2471 #ifdef __native__client_codegen__
2472 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2475 /* benchmark and set based on cpu */
2476 #define LOOP_ALIGNMENT 8
2477 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2481 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2486 guint8 *code = cfg->native_code + cfg->code_len;
2489 if (cfg->opt & MONO_OPT_LOOP) {
2490 int pad, align = LOOP_ALIGNMENT;
2491 /* set alignment depending on cpu */
2492 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2494 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2495 x86_padding (code, pad);
2496 cfg->code_len += pad;
2497 bb->native_offset = cfg->code_len;
2500 #ifdef __native_client_codegen__
2502 /* For Native Client, all indirect call/jump targets must be */
2503 /* 32-byte aligned. Exception handler blocks are jumped to */
2504 /* indirectly as well. */
2505 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2506 (bb->flags & BB_EXCEPTION_HANDLER);
2508 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2509 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2510 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2511 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2512 cfg->code_len += pad;
2513 bb->native_offset = cfg->code_len;
2516 #endif /* __native_client_codegen__ */
2517 if (cfg->verbose_level > 2)
2518 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2520 cpos = bb->max_offset;
2522 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2523 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2524 g_assert (!cfg->compile_aot);
2527 cov->data [bb->dfn].cil_code = bb->cil_code;
2528 /* this is not thread save, but good enough */
2529 x86_inc_mem (code, &cov->data [bb->dfn].count);
2532 offset = code - cfg->native_code;
2534 mono_debug_open_block (cfg, bb, offset);
2536 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2537 x86_breakpoint (code);
2539 MONO_BB_FOR_EACH_INS (bb, ins) {
2540 offset = code - cfg->native_code;
2542 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2544 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2546 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2547 cfg->code_size *= 2;
2548 cfg->native_code = mono_realloc_native_code(cfg);
2549 code = cfg->native_code + offset;
2550 cfg->stat_code_reallocs++;
2553 if (cfg->debug_info)
2554 mono_debug_record_line_number (cfg, ins, offset);
2556 switch (ins->opcode) {
2558 x86_mul_reg (code, ins->sreg2, TRUE);
2561 x86_mul_reg (code, ins->sreg2, FALSE);
2563 case OP_X86_SETEQ_MEMBASE:
2564 case OP_X86_SETNE_MEMBASE:
2565 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2566 ins->inst_basereg, ins->inst_offset, TRUE);
2568 case OP_STOREI1_MEMBASE_IMM:
2569 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2571 case OP_STOREI2_MEMBASE_IMM:
2572 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2574 case OP_STORE_MEMBASE_IMM:
2575 case OP_STOREI4_MEMBASE_IMM:
2576 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2578 case OP_STOREI1_MEMBASE_REG:
2579 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2581 case OP_STOREI2_MEMBASE_REG:
2582 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2584 case OP_STORE_MEMBASE_REG:
2585 case OP_STOREI4_MEMBASE_REG:
2586 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2588 case OP_STORE_MEM_IMM:
2589 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2592 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2596 /* These are created by the cprop pass so they use inst_imm as the source */
2597 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2600 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2603 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2605 case OP_LOAD_MEMBASE:
2606 case OP_LOADI4_MEMBASE:
2607 case OP_LOADU4_MEMBASE:
2608 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2610 case OP_LOADU1_MEMBASE:
2611 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2613 case OP_LOADI1_MEMBASE:
2614 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2616 case OP_LOADU2_MEMBASE:
2617 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2619 case OP_LOADI2_MEMBASE:
2620 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2622 case OP_ICONV_TO_I1:
2624 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2626 case OP_ICONV_TO_I2:
2628 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2630 case OP_ICONV_TO_U1:
2631 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2633 case OP_ICONV_TO_U2:
2634 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2638 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2640 case OP_COMPARE_IMM:
2641 case OP_ICOMPARE_IMM:
2642 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2644 case OP_X86_COMPARE_MEMBASE_REG:
2645 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2647 case OP_X86_COMPARE_MEMBASE_IMM:
2648 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2650 case OP_X86_COMPARE_MEMBASE8_IMM:
2651 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2653 case OP_X86_COMPARE_REG_MEMBASE:
2654 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2656 case OP_X86_COMPARE_MEM_IMM:
2657 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2659 case OP_X86_TEST_NULL:
2660 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2662 case OP_X86_ADD_MEMBASE_IMM:
2663 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2665 case OP_X86_ADD_REG_MEMBASE:
2666 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2668 case OP_X86_SUB_MEMBASE_IMM:
2669 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2671 case OP_X86_SUB_REG_MEMBASE:
2672 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2674 case OP_X86_AND_MEMBASE_IMM:
2675 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2677 case OP_X86_OR_MEMBASE_IMM:
2678 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2680 case OP_X86_XOR_MEMBASE_IMM:
2681 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2683 case OP_X86_ADD_MEMBASE_REG:
2684 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2686 case OP_X86_SUB_MEMBASE_REG:
2687 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2689 case OP_X86_AND_MEMBASE_REG:
2690 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2692 case OP_X86_OR_MEMBASE_REG:
2693 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2695 case OP_X86_XOR_MEMBASE_REG:
2696 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2698 case OP_X86_INC_MEMBASE:
2699 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2701 case OP_X86_INC_REG:
2702 x86_inc_reg (code, ins->dreg);
2704 case OP_X86_DEC_MEMBASE:
2705 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2707 case OP_X86_DEC_REG:
2708 x86_dec_reg (code, ins->dreg);
2710 case OP_X86_MUL_REG_MEMBASE:
2711 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2713 case OP_X86_AND_REG_MEMBASE:
2714 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2716 case OP_X86_OR_REG_MEMBASE:
2717 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2719 case OP_X86_XOR_REG_MEMBASE:
2720 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2723 x86_breakpoint (code);
2725 case OP_RELAXED_NOP:
2726 x86_prefix (code, X86_REP_PREFIX);
2734 case OP_DUMMY_STORE:
2735 case OP_NOT_REACHED:
2738 case OP_SEQ_POINT: {
2741 if (cfg->compile_aot)
2745 * Read from the single stepping trigger page. This will cause a
2746 * SIGSEGV when single stepping is enabled.
2747 * We do this _before_ the breakpoint, so single stepping after
2748 * a breakpoint is hit will step to the next IL offset.
2750 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2751 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2753 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2756 * A placeholder for a possible breakpoint inserted by
2757 * mono_arch_set_breakpoint ().
2759 for (i = 0; i < 6; ++i)
2762 * Add an additional nop so skipping the bp doesn't cause the ip to point
2763 * to another IL offset.
2771 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2775 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2780 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2784 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2789 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2793 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2798 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2802 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2805 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2809 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2813 #if defined( __native_client_codegen__ )
2814 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2815 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2818 * The code is the same for div/rem, the allocator will allocate dreg
2819 * to RAX/RDX as appropriate.
2821 if (ins->sreg2 == X86_EDX) {
2822 /* cdq clobbers this */
2823 x86_push_reg (code, ins->sreg2);
2825 x86_div_membase (code, X86_ESP, 0, TRUE);
2826 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2829 x86_div_reg (code, ins->sreg2, TRUE);
2834 #if defined( __native_client_codegen__ )
2835 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2836 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2838 if (ins->sreg2 == X86_EDX) {
2839 x86_push_reg (code, ins->sreg2);
2840 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2841 x86_div_membase (code, X86_ESP, 0, FALSE);
2842 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2844 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2845 x86_div_reg (code, ins->sreg2, FALSE);
2849 #if defined( __native_client_codegen__ )
2850 if (ins->inst_imm == 0) {
2851 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2852 x86_jump32 (code, 0);
2856 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2858 x86_div_reg (code, ins->sreg2, TRUE);
2861 int power = mono_is_power_of_two (ins->inst_imm);
2863 g_assert (ins->sreg1 == X86_EAX);
2864 g_assert (ins->dreg == X86_EAX);
2865 g_assert (power >= 0);
2868 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2870 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2872 * If the divident is >= 0, this does not nothing. If it is positive, it
2873 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2875 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2876 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2877 } else if (power == 0) {
2878 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2880 /* Based on gcc code */
2882 /* Add compensation for negative dividents */
2884 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2885 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2886 /* Compute remainder */
2887 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2888 /* Remove compensation */
2889 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2894 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2898 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2901 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2905 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2908 g_assert (ins->sreg2 == X86_ECX);
2909 x86_shift_reg (code, X86_SHL, ins->dreg);
2912 g_assert (ins->sreg2 == X86_ECX);
2913 x86_shift_reg (code, X86_SAR, ins->dreg);
2917 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2920 case OP_ISHR_UN_IMM:
2921 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2924 g_assert (ins->sreg2 == X86_ECX);
2925 x86_shift_reg (code, X86_SHR, ins->dreg);
2929 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2932 guint8 *jump_to_end;
2934 /* handle shifts below 32 bits */
2935 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2936 x86_shift_reg (code, X86_SHL, ins->sreg1);
2938 x86_test_reg_imm (code, X86_ECX, 32);
2939 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2941 /* handle shift over 32 bit */
2942 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2943 x86_clear_reg (code, ins->sreg1);
2945 x86_patch (jump_to_end, code);
2949 guint8 *jump_to_end;
2951 /* handle shifts below 32 bits */
2952 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2953 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2955 x86_test_reg_imm (code, X86_ECX, 32);
2956 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2958 /* handle shifts over 31 bits */
2959 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2960 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2962 x86_patch (jump_to_end, code);
2966 guint8 *jump_to_end;
2968 /* handle shifts below 32 bits */
2969 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2970 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
2972 x86_test_reg_imm (code, X86_ECX, 32);
2973 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2975 /* handle shifts over 31 bits */
2976 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2977 x86_clear_reg (code, ins->backend.reg3);
2979 x86_patch (jump_to_end, code);
2983 if (ins->inst_imm >= 32) {
2984 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2985 x86_clear_reg (code, ins->sreg1);
2986 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
2988 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
2989 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2993 if (ins->inst_imm >= 32) {
2994 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2995 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
2996 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2998 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
2999 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3002 case OP_LSHR_UN_IMM:
3003 if (ins->inst_imm >= 32) {
3004 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3005 x86_clear_reg (code, ins->backend.reg3);
3006 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3008 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3009 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3013 x86_not_reg (code, ins->sreg1);
3016 x86_neg_reg (code, ins->sreg1);
3020 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3024 switch (ins->inst_imm) {
3028 if (ins->dreg != ins->sreg1)
3029 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3030 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3033 /* LEA r1, [r2 + r2*2] */
3034 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3037 /* LEA r1, [r2 + r2*4] */
3038 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3041 /* LEA r1, [r2 + r2*2] */
3043 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3044 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3047 /* LEA r1, [r2 + r2*8] */
3048 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3051 /* LEA r1, [r2 + r2*4] */
3053 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3054 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3057 /* LEA r1, [r2 + r2*2] */
3059 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3060 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3063 /* LEA r1, [r2 + r2*4] */
3064 /* LEA r1, [r1 + r1*4] */
3065 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3066 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3069 /* LEA r1, [r2 + r2*4] */
3071 /* LEA r1, [r1 + r1*4] */
3072 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3073 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3074 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3077 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3082 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3083 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3085 case OP_IMUL_OVF_UN: {
3086 /* the mul operation and the exception check should most likely be split */
3087 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3088 /*g_assert (ins->sreg2 == X86_EAX);
3089 g_assert (ins->dreg == X86_EAX);*/
3090 if (ins->sreg2 == X86_EAX) {
3091 non_eax_reg = ins->sreg1;
3092 } else if (ins->sreg1 == X86_EAX) {
3093 non_eax_reg = ins->sreg2;
3095 /* no need to save since we're going to store to it anyway */
3096 if (ins->dreg != X86_EAX) {
3098 x86_push_reg (code, X86_EAX);
3100 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3101 non_eax_reg = ins->sreg2;
3103 if (ins->dreg == X86_EDX) {
3106 x86_push_reg (code, X86_EAX);
3108 } else if (ins->dreg != X86_EAX) {
3110 x86_push_reg (code, X86_EDX);
3112 x86_mul_reg (code, non_eax_reg, FALSE);
3113 /* save before the check since pop and mov don't change the flags */
3114 if (ins->dreg != X86_EAX)
3115 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3117 x86_pop_reg (code, X86_EDX);
3119 x86_pop_reg (code, X86_EAX);
3120 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3124 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3127 g_assert_not_reached ();
3128 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3129 x86_mov_reg_imm (code, ins->dreg, 0);
3132 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3133 x86_mov_reg_imm (code, ins->dreg, 0);
3135 case OP_LOAD_GOTADDR:
3136 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3137 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3140 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3141 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3143 case OP_X86_PUSH_GOT_ENTRY:
3144 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3145 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3148 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3152 * Note: this 'frame destruction' logic is useful for tail calls, too.
3153 * Keep in sync with the code in emit_epilog.
3157 /* FIXME: no tracing support... */
3158 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3159 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3160 /* reset offset to make max_len work */
3161 offset = code - cfg->native_code;
3163 g_assert (!cfg->method->save_lmf);
3165 code = emit_load_volatile_arguments (cfg, code);
3167 if (cfg->used_int_regs & (1 << X86_EBX))
3169 if (cfg->used_int_regs & (1 << X86_EDI))
3171 if (cfg->used_int_regs & (1 << X86_ESI))
3174 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
3176 if (cfg->used_int_regs & (1 << X86_ESI))
3177 x86_pop_reg (code, X86_ESI);
3178 if (cfg->used_int_regs & (1 << X86_EDI))
3179 x86_pop_reg (code, X86_EDI);
3180 if (cfg->used_int_regs & (1 << X86_EBX))
3181 x86_pop_reg (code, X86_EBX);
3183 /* restore ESP/EBP */
3185 offset = code - cfg->native_code;
3186 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3187 x86_jump32 (code, 0);
3189 cfg->disable_aot = TRUE;
3193 MonoCallInst *call = (MonoCallInst*)ins;
3196 ins->flags |= MONO_INST_GC_CALLSITE;
3197 ins->backend.pc_offset = code - cfg->native_code;
3199 /* FIXME: no tracing support... */
3200 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3201 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3202 /* reset offset to make max_len work */
3203 offset = code - cfg->native_code;
3205 g_assert (!cfg->method->save_lmf);
3207 //code = emit_load_volatile_arguments (cfg, code);
3209 /* restore callee saved registers */
3210 for (i = 0; i < X86_NREG; ++i)
3211 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3213 if (cfg->used_int_regs & (1 << X86_ESI)) {
3214 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3217 if (cfg->used_int_regs & (1 << X86_EDI)) {
3218 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3221 if (cfg->used_int_regs & (1 << X86_EBX)) {
3222 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3226 /* Copy arguments on the stack to our argument area */
3227 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3228 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3229 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3232 /* restore ESP/EBP */
3234 offset = code - cfg->native_code;
3235 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3236 x86_jump32 (code, 0);
3238 ins->flags |= MONO_INST_GC_CALLSITE;
3239 cfg->disable_aot = TRUE;
3243 /* ensure ins->sreg1 is not NULL
3244 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3245 * cmp DWORD PTR [eax], 0
3247 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3250 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3251 x86_push_reg (code, hreg);
3252 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3253 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3254 x86_pop_reg (code, hreg);
3263 call = (MonoCallInst*)ins;
3264 if (ins->flags & MONO_INST_HAS_METHOD)
3265 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3267 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3268 ins->flags |= MONO_INST_GC_CALLSITE;
3269 ins->backend.pc_offset = code - cfg->native_code;
3270 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3271 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
3272 * bytes to pop, we want to use pops. GCC does this (note it won't happen
3273 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
3274 * smart enough to do that optimization yet
3276 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
3277 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
3278 * (most likely from locality benefits). People with other processors should
3279 * check on theirs to see what happens.
3281 if (call->stack_usage == 4) {
3282 /* we want to use registers that won't get used soon, so use
3283 * ecx, as eax will get allocated first. edx is used by long calls,
3284 * so we can't use that.
3287 x86_pop_reg (code, X86_ECX);
3289 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3292 code = emit_move_return_value (cfg, ins, code);
3298 case OP_VOIDCALL_REG:
3300 call = (MonoCallInst*)ins;
3301 x86_call_reg (code, ins->sreg1);
3302 ins->flags |= MONO_INST_GC_CALLSITE;
3303 ins->backend.pc_offset = code - cfg->native_code;
3304 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3305 if (call->stack_usage == 4)
3306 x86_pop_reg (code, X86_ECX);
3308 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3310 code = emit_move_return_value (cfg, ins, code);
3312 case OP_FCALL_MEMBASE:
3313 case OP_LCALL_MEMBASE:
3314 case OP_VCALL_MEMBASE:
3315 case OP_VCALL2_MEMBASE:
3316 case OP_VOIDCALL_MEMBASE:
3317 case OP_CALL_MEMBASE:
3318 call = (MonoCallInst*)ins;
3320 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3321 ins->flags |= MONO_INST_GC_CALLSITE;
3322 ins->backend.pc_offset = code - cfg->native_code;
3323 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3324 if (call->stack_usage == 4)
3325 x86_pop_reg (code, X86_ECX);
3327 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3329 code = emit_move_return_value (cfg, ins, code);
3332 x86_push_reg (code, ins->sreg1);
3334 case OP_X86_PUSH_IMM:
3335 x86_push_imm (code, ins->inst_imm);
3337 case OP_X86_PUSH_MEMBASE:
3338 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
3340 case OP_X86_PUSH_OBJ:
3341 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
3342 x86_push_reg (code, X86_EDI);
3343 x86_push_reg (code, X86_ESI);
3344 x86_push_reg (code, X86_ECX);
3345 if (ins->inst_offset)
3346 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
3348 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
3349 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
3350 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
3352 x86_prefix (code, X86_REP_PREFIX);
3354 x86_pop_reg (code, X86_ECX);
3355 x86_pop_reg (code, X86_ESI);
3356 x86_pop_reg (code, X86_EDI);
3359 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3361 case OP_X86_LEA_MEMBASE:
3362 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3365 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3368 /* keep alignment */
3369 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3370 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3371 code = mono_emit_stack_alloc (code, ins);
3372 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3374 case OP_LOCALLOC_IMM: {
3375 guint32 size = ins->inst_imm;
3376 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3378 if (ins->flags & MONO_INST_INIT) {
3379 /* FIXME: Optimize this */
3380 x86_mov_reg_imm (code, ins->dreg, size);
3381 ins->sreg1 = ins->dreg;
3383 code = mono_emit_stack_alloc (code, ins);
3384 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3386 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3387 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3392 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3393 x86_push_reg (code, ins->sreg1);
3394 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3395 (gpointer)"mono_arch_throw_exception");
3396 ins->flags |= MONO_INST_GC_CALLSITE;
3397 ins->backend.pc_offset = code - cfg->native_code;
3401 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3402 x86_push_reg (code, ins->sreg1);
3403 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3404 (gpointer)"mono_arch_rethrow_exception");
3405 ins->flags |= MONO_INST_GC_CALLSITE;
3406 ins->backend.pc_offset = code - cfg->native_code;
3409 case OP_CALL_HANDLER:
3410 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3411 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3412 x86_call_imm (code, 0);
3413 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3414 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3416 case OP_START_HANDLER: {
3417 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3418 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3421 case OP_ENDFINALLY: {
3422 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3423 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3427 case OP_ENDFILTER: {
3428 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3429 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3430 /* The local allocator will put the result into EAX */
3436 ins->inst_c0 = code - cfg->native_code;
3439 if (ins->inst_target_bb->native_offset) {
3440 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3442 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3443 if ((cfg->opt & MONO_OPT_BRANCH) &&
3444 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3445 x86_jump8 (code, 0);
3447 x86_jump32 (code, 0);
3451 x86_jump_reg (code, ins->sreg1);
3464 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3465 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3467 case OP_COND_EXC_EQ:
3468 case OP_COND_EXC_NE_UN:
3469 case OP_COND_EXC_LT:
3470 case OP_COND_EXC_LT_UN:
3471 case OP_COND_EXC_GT:
3472 case OP_COND_EXC_GT_UN:
3473 case OP_COND_EXC_GE:
3474 case OP_COND_EXC_GE_UN:
3475 case OP_COND_EXC_LE:
3476 case OP_COND_EXC_LE_UN:
3477 case OP_COND_EXC_IEQ:
3478 case OP_COND_EXC_INE_UN:
3479 case OP_COND_EXC_ILT:
3480 case OP_COND_EXC_ILT_UN:
3481 case OP_COND_EXC_IGT:
3482 case OP_COND_EXC_IGT_UN:
3483 case OP_COND_EXC_IGE:
3484 case OP_COND_EXC_IGE_UN:
3485 case OP_COND_EXC_ILE:
3486 case OP_COND_EXC_ILE_UN:
3487 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3489 case OP_COND_EXC_OV:
3490 case OP_COND_EXC_NO:
3492 case OP_COND_EXC_NC:
3493 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3495 case OP_COND_EXC_IOV:
3496 case OP_COND_EXC_INO:
3497 case OP_COND_EXC_IC:
3498 case OP_COND_EXC_INC:
3499 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3511 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3519 case OP_CMOV_INE_UN:
3520 case OP_CMOV_IGE_UN:
3521 case OP_CMOV_IGT_UN:
3522 case OP_CMOV_ILE_UN:
3523 case OP_CMOV_ILT_UN:
3524 g_assert (ins->dreg == ins->sreg1);
3525 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3528 /* floating point opcodes */
3530 double d = *(double *)ins->inst_p0;
3532 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3534 } else if (d == 1.0) {
3537 if (cfg->compile_aot) {
3538 guint32 *val = (guint32*)&d;
3539 x86_push_imm (code, val [1]);
3540 x86_push_imm (code, val [0]);
3541 x86_fld_membase (code, X86_ESP, 0, TRUE);
3542 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3545 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3546 x86_fld (code, NULL, TRUE);
3552 float f = *(float *)ins->inst_p0;
3554 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3556 } else if (f == 1.0) {
3559 if (cfg->compile_aot) {
3560 guint32 val = *(guint32*)&f;
3561 x86_push_imm (code, val);
3562 x86_fld_membase (code, X86_ESP, 0, FALSE);
3563 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3566 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3567 x86_fld (code, NULL, FALSE);
3572 case OP_STORER8_MEMBASE_REG:
3573 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3575 case OP_LOADR8_MEMBASE:
3576 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3578 case OP_STORER4_MEMBASE_REG:
3579 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3581 case OP_LOADR4_MEMBASE:
3582 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3584 case OP_ICONV_TO_R4:
3585 x86_push_reg (code, ins->sreg1);
3586 x86_fild_membase (code, X86_ESP, 0, FALSE);
3587 /* Change precision */
3588 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3589 x86_fld_membase (code, X86_ESP, 0, FALSE);
3590 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3592 case OP_ICONV_TO_R8:
3593 x86_push_reg (code, ins->sreg1);
3594 x86_fild_membase (code, X86_ESP, 0, FALSE);
3595 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3597 case OP_ICONV_TO_R_UN:
3598 x86_push_imm (code, 0);
3599 x86_push_reg (code, ins->sreg1);
3600 x86_fild_membase (code, X86_ESP, 0, TRUE);
3601 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3603 case OP_X86_FP_LOAD_I8:
3604 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3606 case OP_X86_FP_LOAD_I4:
3607 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3609 case OP_FCONV_TO_R4:
3610 /* Change precision */
3611 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3612 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3613 x86_fld_membase (code, X86_ESP, 0, FALSE);
3614 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3616 case OP_FCONV_TO_I1:
3617 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3619 case OP_FCONV_TO_U1:
3620 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3622 case OP_FCONV_TO_I2:
3623 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3625 case OP_FCONV_TO_U2:
3626 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3628 case OP_FCONV_TO_I4:
3630 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3632 case OP_FCONV_TO_I8:
3633 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3634 x86_fnstcw_membase(code, X86_ESP, 0);
3635 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3636 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3637 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3638 x86_fldcw_membase (code, X86_ESP, 2);
3639 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3640 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3641 x86_pop_reg (code, ins->dreg);
3642 x86_pop_reg (code, ins->backend.reg3);
3643 x86_fldcw_membase (code, X86_ESP, 0);
3644 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3646 case OP_LCONV_TO_R8_2:
3647 x86_push_reg (code, ins->sreg2);
3648 x86_push_reg (code, ins->sreg1);
3649 x86_fild_membase (code, X86_ESP, 0, TRUE);
3650 /* Change precision */
3651 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3652 x86_fld_membase (code, X86_ESP, 0, TRUE);
3653 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3655 case OP_LCONV_TO_R4_2:
3656 x86_push_reg (code, ins->sreg2);
3657 x86_push_reg (code, ins->sreg1);
3658 x86_fild_membase (code, X86_ESP, 0, TRUE);
3659 /* Change precision */
3660 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3661 x86_fld_membase (code, X86_ESP, 0, FALSE);
3662 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3664 case OP_LCONV_TO_R_UN_2: {
3665 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3668 /* load 64bit integer to FP stack */
3669 x86_push_reg (code, ins->sreg2);
3670 x86_push_reg (code, ins->sreg1);
3671 x86_fild_membase (code, X86_ESP, 0, TRUE);
3673 /* test if lreg is negative */
3674 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3675 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3677 /* add correction constant mn */
3678 if (cfg->compile_aot) {
3679 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3680 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3681 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3682 x86_fld80_membase (code, X86_ESP, 2);
3683 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3685 x86_fld80_mem (code, mn);
3687 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3689 x86_patch (br, code);
3691 /* Change precision */
3692 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3693 x86_fld_membase (code, X86_ESP, 0, TRUE);
3695 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3699 case OP_LCONV_TO_OVF_I:
3700 case OP_LCONV_TO_OVF_I4_2: {
3701 guint8 *br [3], *label [1];
3705 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3707 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3709 /* If the low word top bit is set, see if we are negative */
3710 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3711 /* We are not negative (no top bit set, check for our top word to be zero */
3712 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3713 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3716 /* throw exception */
3717 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3719 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3720 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3721 x86_jump8 (code, 0);
3723 x86_jump32 (code, 0);
3725 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3726 x86_jump32 (code, 0);
3730 x86_patch (br [0], code);
3731 /* our top bit is set, check that top word is 0xfffffff */
3732 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3734 x86_patch (br [1], code);
3735 /* nope, emit exception */
3736 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3737 x86_patch (br [2], label [0]);
3739 if (ins->dreg != ins->sreg1)
3740 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3744 /* Not needed on the fp stack */
3747 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3750 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3753 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3756 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3764 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3769 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3776 * it really doesn't make sense to inline all this code,
3777 * it's here just to show that things may not be as simple
3780 guchar *check_pos, *end_tan, *pop_jump;
3781 x86_push_reg (code, X86_EAX);
3784 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3786 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3787 x86_fstp (code, 0); /* pop the 1.0 */
3789 x86_jump8 (code, 0);
3791 x86_fp_op (code, X86_FADD, 0);
3795 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3797 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3800 x86_patch (pop_jump, code);
3801 x86_fstp (code, 0); /* pop the 1.0 */
3802 x86_patch (check_pos, code);
3803 x86_patch (end_tan, code);
3805 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3806 x86_pop_reg (code, X86_EAX);
3813 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3822 g_assert (cfg->opt & MONO_OPT_CMOV);
3823 g_assert (ins->dreg == ins->sreg1);
3824 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3825 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3828 g_assert (cfg->opt & MONO_OPT_CMOV);
3829 g_assert (ins->dreg == ins->sreg1);
3830 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3831 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3834 g_assert (cfg->opt & MONO_OPT_CMOV);
3835 g_assert (ins->dreg == ins->sreg1);
3836 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3837 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3840 g_assert (cfg->opt & MONO_OPT_CMOV);
3841 g_assert (ins->dreg == ins->sreg1);
3842 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3843 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3849 x86_fxch (code, ins->inst_imm);
3854 x86_push_reg (code, X86_EAX);
3855 /* we need to exchange ST(0) with ST(1) */
3858 /* this requires a loop, because fprem somtimes
3859 * returns a partial remainder */
3861 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3862 /* x86_fprem1 (code); */
3865 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3867 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3873 x86_pop_reg (code, X86_EAX);
3877 if (cfg->opt & MONO_OPT_FCMOV) {
3878 x86_fcomip (code, 1);
3882 /* this overwrites EAX */
3883 EMIT_FPCOMPARE(code);
3884 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3887 if (cfg->opt & MONO_OPT_FCMOV) {
3888 /* zeroing the register at the start results in
3889 * shorter and faster code (we can also remove the widening op)
3891 guchar *unordered_check;
3892 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3893 x86_fcomip (code, 1);
3895 unordered_check = code;
3896 x86_branch8 (code, X86_CC_P, 0, FALSE);
3897 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3898 x86_patch (unordered_check, code);
3901 if (ins->dreg != X86_EAX)
3902 x86_push_reg (code, X86_EAX);
3904 EMIT_FPCOMPARE(code);
3905 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3906 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3907 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3908 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3910 if (ins->dreg != X86_EAX)
3911 x86_pop_reg (code, X86_EAX);
3915 if (cfg->opt & MONO_OPT_FCMOV) {
3916 /* zeroing the register at the start results in
3917 * shorter and faster code (we can also remove the widening op)
3919 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3920 x86_fcomip (code, 1);
3922 if (ins->opcode == OP_FCLT_UN) {
3923 guchar *unordered_check = code;
3924 guchar *jump_to_end;
3925 x86_branch8 (code, X86_CC_P, 0, FALSE);
3926 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3928 x86_jump8 (code, 0);
3929 x86_patch (unordered_check, code);
3930 x86_inc_reg (code, ins->dreg);
3931 x86_patch (jump_to_end, code);
3933 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3937 if (ins->dreg != X86_EAX)
3938 x86_push_reg (code, X86_EAX);
3940 EMIT_FPCOMPARE(code);
3941 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3942 if (ins->opcode == OP_FCLT_UN) {
3943 guchar *is_not_zero_check, *end_jump;
3944 is_not_zero_check = code;
3945 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3947 x86_jump8 (code, 0);
3948 x86_patch (is_not_zero_check, code);
3949 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3951 x86_patch (end_jump, code);
3953 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3954 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3956 if (ins->dreg != X86_EAX)
3957 x86_pop_reg (code, X86_EAX);
3961 if (cfg->opt & MONO_OPT_FCMOV) {
3962 /* zeroing the register at the start results in
3963 * shorter and faster code (we can also remove the widening op)
3965 guchar *unordered_check;
3966 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3967 x86_fcomip (code, 1);
3969 if (ins->opcode == OP_FCGT) {
3970 unordered_check = code;
3971 x86_branch8 (code, X86_CC_P, 0, FALSE);
3972 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3973 x86_patch (unordered_check, code);
3975 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3979 if (ins->dreg != X86_EAX)
3980 x86_push_reg (code, X86_EAX);
3982 EMIT_FPCOMPARE(code);
3983 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3984 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3985 if (ins->opcode == OP_FCGT_UN) {
3986 guchar *is_not_zero_check, *end_jump;
3987 is_not_zero_check = code;
3988 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3990 x86_jump8 (code, 0);
3991 x86_patch (is_not_zero_check, code);
3992 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3994 x86_patch (end_jump, code);
3996 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3997 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3999 if (ins->dreg != X86_EAX)
4000 x86_pop_reg (code, X86_EAX);
4003 if (cfg->opt & MONO_OPT_FCMOV) {
4004 guchar *jump = code;
4005 x86_branch8 (code, X86_CC_P, 0, TRUE);
4006 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4007 x86_patch (jump, code);
4010 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4011 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4014 /* Branch if C013 != 100 */
4015 if (cfg->opt & MONO_OPT_FCMOV) {
4016 /* branch if !ZF or (PF|CF) */
4017 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4018 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4019 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4022 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4023 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4026 if (cfg->opt & MONO_OPT_FCMOV) {
4027 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4030 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4033 if (cfg->opt & MONO_OPT_FCMOV) {
4034 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4035 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4038 if (ins->opcode == OP_FBLT_UN) {
4039 guchar *is_not_zero_check, *end_jump;
4040 is_not_zero_check = code;
4041 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4043 x86_jump8 (code, 0);
4044 x86_patch (is_not_zero_check, code);
4045 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4047 x86_patch (end_jump, code);
4049 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4053 if (cfg->opt & MONO_OPT_FCMOV) {
4054 if (ins->opcode == OP_FBGT) {
4057 /* skip branch if C1=1 */
4059 x86_branch8 (code, X86_CC_P, 0, FALSE);
4060 /* branch if (C0 | C3) = 1 */
4061 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4062 x86_patch (br1, code);
4064 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4068 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4069 if (ins->opcode == OP_FBGT_UN) {
4070 guchar *is_not_zero_check, *end_jump;
4071 is_not_zero_check = code;
4072 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4074 x86_jump8 (code, 0);
4075 x86_patch (is_not_zero_check, code);
4076 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4078 x86_patch (end_jump, code);
4080 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4083 /* Branch if C013 == 100 or 001 */
4084 if (cfg->opt & MONO_OPT_FCMOV) {
4087 /* skip branch if C1=1 */
4089 x86_branch8 (code, X86_CC_P, 0, FALSE);
4090 /* branch if (C0 | C3) = 1 */
4091 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4092 x86_patch (br1, code);
4095 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4096 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4097 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4098 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4101 /* Branch if C013 == 000 */
4102 if (cfg->opt & MONO_OPT_FCMOV) {
4103 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4106 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4109 /* Branch if C013=000 or 100 */
4110 if (cfg->opt & MONO_OPT_FCMOV) {
4113 /* skip branch if C1=1 */
4115 x86_branch8 (code, X86_CC_P, 0, FALSE);
4116 /* branch if C0=0 */
4117 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4118 x86_patch (br1, code);
4121 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4122 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4123 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4126 /* Branch if C013 != 001 */
4127 if (cfg->opt & MONO_OPT_FCMOV) {
4128 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4129 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4132 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4133 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4137 x86_push_reg (code, X86_EAX);
4140 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4141 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4142 x86_pop_reg (code, X86_EAX);
4144 /* Have to clean up the fp stack before throwing the exception */
4146 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4149 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4151 x86_patch (br1, code);
4155 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4158 case OP_MEMORY_BARRIER: {
4159 /* x86 only needs barrier for StoreLoad and FullBarrier */
4160 switch (ins->backend.memory_barrier_kind) {
4161 case StoreLoadBarrier:
4163 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4164 x86_prefix (code, X86_LOCK_PREFIX);
4165 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4170 case OP_ATOMIC_ADD_I4: {
4171 int dreg = ins->dreg;
4173 if (dreg == ins->inst_basereg) {
4174 x86_push_reg (code, ins->sreg2);
4178 if (dreg != ins->sreg2)
4179 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
4181 x86_prefix (code, X86_LOCK_PREFIX);
4182 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4184 if (dreg != ins->dreg) {
4185 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4186 x86_pop_reg (code, dreg);
4191 case OP_ATOMIC_ADD_NEW_I4: {
4192 int dreg = ins->dreg;
4194 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4195 if (ins->sreg2 == dreg) {
4196 if (dreg == X86_EBX) {
4198 if (ins->inst_basereg == X86_EDI)
4202 if (ins->inst_basereg == X86_EBX)
4205 } else if (ins->inst_basereg == dreg) {
4206 if (dreg == X86_EBX) {
4208 if (ins->sreg2 == X86_EDI)
4212 if (ins->sreg2 == X86_EBX)
4217 if (dreg != ins->dreg) {
4218 x86_push_reg (code, dreg);
4221 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4222 x86_prefix (code, X86_LOCK_PREFIX);
4223 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4224 /* dreg contains the old value, add with sreg2 value */
4225 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4227 if (ins->dreg != dreg) {
4228 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4229 x86_pop_reg (code, dreg);
4234 case OP_ATOMIC_EXCHANGE_I4: {
4236 int sreg2 = ins->sreg2;
4237 int breg = ins->inst_basereg;
4239 /* cmpxchg uses eax as comperand, need to make sure we can use it
4240 * hack to overcome limits in x86 reg allocator
4241 * (req: dreg == eax and sreg2 != eax and breg != eax)
4243 g_assert (ins->dreg == X86_EAX);
4245 /* We need the EAX reg for the cmpxchg */
4246 if (ins->sreg2 == X86_EAX) {
4247 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4248 x86_push_reg (code, sreg2);
4249 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4252 if (breg == X86_EAX) {
4253 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4254 x86_push_reg (code, breg);
4255 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4258 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4260 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4261 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4262 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4263 x86_patch (br [1], br [0]);
4265 if (breg != ins->inst_basereg)
4266 x86_pop_reg (code, breg);
4268 if (ins->sreg2 != sreg2)
4269 x86_pop_reg (code, sreg2);
4273 case OP_ATOMIC_CAS_I4: {
4274 g_assert (ins->dreg == X86_EAX);
4275 g_assert (ins->sreg3 == X86_EAX);
4276 g_assert (ins->sreg1 != X86_EAX);
4277 g_assert (ins->sreg1 != ins->sreg2);
4279 x86_prefix (code, X86_LOCK_PREFIX);
4280 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4283 case OP_CARD_TABLE_WBARRIER: {
4284 int ptr = ins->sreg1;
4285 int value = ins->sreg2;
4287 int nursery_shift, card_table_shift;
4288 gpointer card_table_mask;
4289 size_t nursery_size;
4290 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4291 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4292 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4295 * We need one register we can clobber, we choose EDX and make sreg1
4296 * fixed EAX to work around limitations in the local register allocator.
4297 * sreg2 might get allocated to EDX, but that is not a problem since
4298 * we use it before clobbering EDX.
4300 g_assert (ins->sreg1 == X86_EAX);
4303 * This is the code we produce:
4306 * edx >>= nursery_shift
4307 * cmp edx, (nursery_start >> nursery_shift)
4310 * edx >>= card_table_shift
4311 * card_table[edx] = 1
4315 if (card_table_nursery_check) {
4316 if (value != X86_EDX)
4317 x86_mov_reg_reg (code, X86_EDX, value, 4);
4318 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4319 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4320 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4322 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4323 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4324 if (card_table_mask)
4325 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4326 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4327 if (card_table_nursery_check)
4328 x86_patch (br, code);
4331 #ifdef MONO_ARCH_SIMD_INTRINSICS
4333 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4336 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4339 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4342 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4345 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4348 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4351 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4352 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4355 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4358 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4361 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4364 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4367 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4370 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4373 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4376 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4379 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4382 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4385 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4388 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4391 case OP_PSHUFLEW_HIGH:
4392 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4393 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4395 case OP_PSHUFLEW_LOW:
4396 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4397 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4400 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4401 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4404 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4405 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4408 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4409 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4413 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4416 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4419 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4422 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4425 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4428 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4431 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4432 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4435 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4438 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4441 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4444 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4447 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4450 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4453 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4456 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4459 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4462 case OP_EXTRACT_MASK:
4463 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4467 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4470 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4473 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4477 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4480 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4483 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4486 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4490 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4493 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4496 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4499 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4503 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4506 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4509 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4513 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4516 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4519 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4523 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4526 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4530 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4533 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4536 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4540 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4543 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4546 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4550 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4553 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4556 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4559 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4563 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4566 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4569 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4572 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4575 case OP_PSUM_ABS_DIFF:
4576 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4579 case OP_UNPACK_LOWB:
4580 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4582 case OP_UNPACK_LOWW:
4583 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4585 case OP_UNPACK_LOWD:
4586 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4588 case OP_UNPACK_LOWQ:
4589 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4591 case OP_UNPACK_LOWPS:
4592 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4594 case OP_UNPACK_LOWPD:
4595 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4598 case OP_UNPACK_HIGHB:
4599 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4601 case OP_UNPACK_HIGHW:
4602 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4604 case OP_UNPACK_HIGHD:
4605 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4607 case OP_UNPACK_HIGHQ:
4608 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4610 case OP_UNPACK_HIGHPS:
4611 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4613 case OP_UNPACK_HIGHPD:
4614 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4618 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4621 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4624 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4627 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4630 case OP_PADDB_SAT_UN:
4631 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4633 case OP_PSUBB_SAT_UN:
4634 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4636 case OP_PADDW_SAT_UN:
4637 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4639 case OP_PSUBW_SAT_UN:
4640 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4644 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4647 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4650 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4653 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4657 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4660 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4663 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4665 case OP_PMULW_HIGH_UN:
4666 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4669 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4673 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4676 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4680 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4683 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4687 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4690 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4694 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4697 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4701 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4704 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4708 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4711 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4715 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4718 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4722 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4725 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4729 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4732 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4736 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4738 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4739 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4743 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4745 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4746 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4750 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4752 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4753 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4757 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4759 case OP_EXTRACTX_U2:
4760 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4762 case OP_INSERTX_U1_SLOW:
4763 /*sreg1 is the extracted ireg (scratch)
4764 /sreg2 is the to be inserted ireg (scratch)
4765 /dreg is the xreg to receive the value*/
4767 /*clear the bits from the extracted word*/
4768 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4769 /*shift the value to insert if needed*/
4770 if (ins->inst_c0 & 1)
4771 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4772 /*join them together*/
4773 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4774 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4776 case OP_INSERTX_I4_SLOW:
4777 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4778 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4779 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4782 case OP_INSERTX_R4_SLOW:
4783 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4784 /*TODO if inst_c0 == 0 use movss*/
4785 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4786 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4788 case OP_INSERTX_R8_SLOW:
4789 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4790 if (cfg->verbose_level)
4791 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4793 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4795 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4798 case OP_STOREX_MEMBASE_REG:
4799 case OP_STOREX_MEMBASE:
4800 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4802 case OP_LOADX_MEMBASE:
4803 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4805 case OP_LOADX_ALIGNED_MEMBASE:
4806 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4808 case OP_STOREX_ALIGNED_MEMBASE_REG:
4809 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4811 case OP_STOREX_NTA_MEMBASE_REG:
4812 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4814 case OP_PREFETCH_MEMBASE:
4815 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4819 /*FIXME the peephole pass should have killed this*/
4820 if (ins->dreg != ins->sreg1)
4821 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4824 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4826 case OP_ICONV_TO_R8_RAW:
4827 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4828 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4831 case OP_FCONV_TO_R8_X:
4832 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4833 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4836 case OP_XCONV_R8_TO_I4:
4837 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4838 switch (ins->backend.source_opcode) {
4839 case OP_FCONV_TO_I1:
4840 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4842 case OP_FCONV_TO_U1:
4843 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4845 case OP_FCONV_TO_I2:
4846 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4848 case OP_FCONV_TO_U2:
4849 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4855 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4856 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4857 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4858 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4859 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4860 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4863 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4864 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4865 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4868 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4869 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4872 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4873 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4874 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4877 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4878 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4879 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4883 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4886 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4889 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4892 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4895 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4898 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4901 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4904 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4908 case OP_LIVERANGE_START: {
4909 if (cfg->verbose_level > 1)
4910 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4911 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4914 case OP_LIVERANGE_END: {
4915 if (cfg->verbose_level > 1)
4916 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4917 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4920 case OP_NACL_GC_SAFE_POINT: {
4921 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
4922 if (cfg->compile_aot)
4923 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
4927 x86_test_mem_imm8 (code, (gpointer)&__nacl_thread_suspension_needed, 0xFFFFFFFF);
4928 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4929 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
4930 x86_patch (br[0], code);
4935 case OP_GC_LIVENESS_DEF:
4936 case OP_GC_LIVENESS_USE:
4937 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4938 ins->backend.pc_offset = code - cfg->native_code;
4940 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4941 ins->backend.pc_offset = code - cfg->native_code;
4942 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4945 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4946 g_assert_not_reached ();
4949 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4950 #ifndef __native_client_codegen__
4951 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4952 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4953 g_assert_not_reached ();
4954 #endif /* __native_client_codegen__ */
4960 cfg->code_len = code - cfg->native_code;
4963 #endif /* DISABLE_JIT */
4966 mono_arch_register_lowlevel_calls (void)
4971 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
4973 MonoJumpInfo *patch_info;
4974 gboolean compile_aot = !run_cctors;
4976 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4977 unsigned char *ip = patch_info->ip.i + code;
4978 const unsigned char *target;
4980 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4983 switch (patch_info->type) {
4984 case MONO_PATCH_INFO_BB:
4985 case MONO_PATCH_INFO_LABEL:
4988 /* No need to patch these */
4993 switch (patch_info->type) {
4994 case MONO_PATCH_INFO_IP:
4995 *((gconstpointer *)(ip)) = target;
4997 case MONO_PATCH_INFO_CLASS_INIT: {
4999 /* Might already been changed to a nop */
5000 x86_call_code (code, 0);
5001 x86_patch (ip, target);
5004 case MONO_PATCH_INFO_ABS:
5005 case MONO_PATCH_INFO_METHOD:
5006 case MONO_PATCH_INFO_METHOD_JUMP:
5007 case MONO_PATCH_INFO_INTERNAL_METHOD:
5008 case MONO_PATCH_INFO_BB:
5009 case MONO_PATCH_INFO_LABEL:
5010 case MONO_PATCH_INFO_RGCTX_FETCH:
5011 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
5012 case MONO_PATCH_INFO_MONITOR_ENTER:
5013 case MONO_PATCH_INFO_MONITOR_EXIT:
5014 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5015 #if defined(__native_client_codegen__) && defined(__native_client__)
5016 if (nacl_is_code_address (code)) {
5017 /* For tail calls, code is patched after being installed */
5018 /* but not through the normal "patch callsite" method. */
5019 unsigned char buf[kNaClAlignment];
5020 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5021 unsigned char *_target = target;
5023 /* All patch targets modified in x86_patch */
5024 /* are IP relative. */
5025 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5026 memcpy (buf, aligned_code, kNaClAlignment);
5027 /* Patch a temp buffer of bundle size, */
5028 /* then install to actual location. */
5029 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5030 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5031 g_assert (ret == 0);
5034 x86_patch (ip, target);
5037 x86_patch (ip, target);
5040 case MONO_PATCH_INFO_NONE:
5042 case MONO_PATCH_INFO_R4:
5043 case MONO_PATCH_INFO_R8: {
5044 guint32 offset = mono_arch_get_patch_offset (ip);
5045 *((gconstpointer *)(ip + offset)) = target;
5049 guint32 offset = mono_arch_get_patch_offset (ip);
5050 #if !defined(__native_client__)
5051 *((gconstpointer *)(ip + offset)) = target;
5053 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5061 static G_GNUC_UNUSED void
5062 stack_unaligned (MonoMethod *m, gpointer caller)
5064 printf ("%s\n", mono_method_full_name (m, TRUE));
5065 g_assert_not_reached ();
5069 mono_arch_emit_prolog (MonoCompile *cfg)
5071 MonoMethod *method = cfg->method;
5073 MonoMethodSignature *sig;
5075 int alloc_size, pos, max_offset, i, cfa_offset;
5077 gboolean need_stack_frame;
5078 #ifdef __native_client_codegen__
5079 guint alignment_check;
5082 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5084 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5085 cfg->code_size += 512;
5087 #if defined(__default_codegen__)
5088 code = cfg->native_code = g_malloc (cfg->code_size);
5089 #elif defined(__native_client_codegen__)
5090 /* native_code_alloc is not 32-byte aligned, native_code is. */
5091 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5093 /* Align native_code to next nearest kNaclAlignment byte. */
5094 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5095 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5097 code = cfg->native_code;
5099 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5100 g_assert(alignment_check == 0);
5107 /* Check that the stack is aligned on osx */
5108 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5109 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5110 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5112 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5113 x86_push_membase (code, X86_ESP, 0);
5114 x86_push_imm (code, cfg->method);
5115 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5116 x86_call_reg (code, X86_EAX);
5117 x86_patch (br [0], code);
5121 /* Offset between RSP and the CFA */
5125 cfa_offset = sizeof (gpointer);
5126 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5127 // IP saved at CFA - 4
5128 /* There is no IP reg on x86 */
5129 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5130 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5132 need_stack_frame = needs_stack_frame (cfg);
5134 if (need_stack_frame) {
5135 x86_push_reg (code, X86_EBP);
5136 cfa_offset += sizeof (gpointer);
5137 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5138 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5139 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5140 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5141 /* These are handled automatically by the stack marking code */
5142 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5144 cfg->frame_reg = X86_ESP;
5147 alloc_size = cfg->stack_offset;
5150 if (method->save_lmf) {
5151 pos += sizeof (MonoLMF);
5153 /* save the current IP */
5154 if (cfg->compile_aot) {
5155 /* This pushes the current ip */
5156 x86_call_imm (code, 0);
5158 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
5159 x86_push_imm_template (code);
5161 cfa_offset += sizeof (gpointer);
5162 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5164 /* save all caller saved regs */
5165 x86_push_reg (code, X86_EBP);
5166 cfa_offset += sizeof (gpointer);
5167 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5168 x86_push_reg (code, X86_ESI);
5169 cfa_offset += sizeof (gpointer);
5170 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5171 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5172 x86_push_reg (code, X86_EDI);
5173 cfa_offset += sizeof (gpointer);
5174 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5175 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5176 x86_push_reg (code, X86_EBX);
5177 cfa_offset += sizeof (gpointer);
5178 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5179 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5181 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5183 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5184 * through the mono_lmf_addr TLS variable.
5186 /* %eax = previous_lmf */
5187 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_tls_offset);
5188 /* skip esp + method_info + lmf */
5189 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 12);
5191 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5192 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + 4, SLOT_NOREF);
5193 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + 8, SLOT_NOREF);
5194 /* push previous_lmf */
5195 x86_push_reg (code, X86_EAX);
5197 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5199 code = mono_x86_emit_tls_set (code, X86_ESP, lmf_tls_offset);
5201 /* get the address of lmf for the current thread */
5203 * This is performance critical so we try to use some tricks to make
5207 if (lmf_addr_tls_offset != -1) {
5208 /* Load lmf quicky using the GS register */
5209 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
5211 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5212 /* FIXME: Add a separate key for LMF to avoid this */
5213 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5216 if (cfg->compile_aot)
5217 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
5218 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
5221 /* Skip esp + method info */
5222 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
5225 x86_push_reg (code, X86_EAX);
5226 /* push *lfm (previous_lmf) */
5227 x86_push_membase (code, X86_EAX, 0);
5229 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
5233 if (cfg->used_int_regs & (1 << X86_EBX)) {
5234 x86_push_reg (code, X86_EBX);
5236 cfa_offset += sizeof (gpointer);
5237 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5238 /* These are handled automatically by the stack marking code */
5239 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5242 if (cfg->used_int_regs & (1 << X86_EDI)) {
5243 x86_push_reg (code, X86_EDI);
5245 cfa_offset += sizeof (gpointer);
5246 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5247 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5250 if (cfg->used_int_regs & (1 << X86_ESI)) {
5251 x86_push_reg (code, X86_ESI);
5253 cfa_offset += sizeof (gpointer);
5254 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5255 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5261 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5262 if (mono_do_x86_stack_align && need_stack_frame) {
5263 int tot = alloc_size + pos + 4; /* ret ip */
5264 if (need_stack_frame)
5266 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5268 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5269 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5270 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5274 cfg->arch.sp_fp_offset = alloc_size + pos;
5277 /* See mono_emit_stack_alloc */
5278 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5279 guint32 remaining_size = alloc_size;
5280 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5281 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5282 guint32 offset = code - cfg->native_code;
5283 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5284 while (required_code_size >= (cfg->code_size - offset))
5285 cfg->code_size *= 2;
5286 cfg->native_code = mono_realloc_native_code(cfg);
5287 code = cfg->native_code + offset;
5288 cfg->stat_code_reallocs++;
5290 while (remaining_size >= 0x1000) {
5291 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5292 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5293 remaining_size -= 0x1000;
5296 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5298 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5301 g_assert (need_stack_frame);
5304 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5305 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5306 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5309 #if DEBUG_STACK_ALIGNMENT
5310 /* check the stack is aligned */
5311 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5312 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5313 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5314 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5315 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5316 x86_breakpoint (code);
5320 /* compute max_offset in order to use short forward jumps */
5322 if (cfg->opt & MONO_OPT_BRANCH) {
5323 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5325 bb->max_offset = max_offset;
5327 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5329 /* max alignment for loops */
5330 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5331 max_offset += LOOP_ALIGNMENT;
5332 #ifdef __native_client_codegen__
5333 /* max alignment for native client */
5334 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5335 max_offset += kNaClAlignment;
5337 MONO_BB_FOR_EACH_INS (bb, ins) {
5338 if (ins->opcode == OP_LABEL)
5339 ins->inst_c1 = max_offset;
5340 #ifdef __native_client_codegen__
5341 switch (ins->opcode)
5353 case OP_VOIDCALL_REG:
5355 case OP_FCALL_MEMBASE:
5356 case OP_LCALL_MEMBASE:
5357 case OP_VCALL_MEMBASE:
5358 case OP_VCALL2_MEMBASE:
5359 case OP_VOIDCALL_MEMBASE:
5360 case OP_CALL_MEMBASE:
5361 max_offset += kNaClAlignment;
5364 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5367 #endif /* __native_client_codegen__ */
5368 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5373 /* store runtime generic context */
5374 if (cfg->rgctx_var) {
5375 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5377 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5380 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5381 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5383 /* load arguments allocated to register from the stack */
5384 sig = mono_method_signature (method);
5387 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5388 inst = cfg->args [pos];
5389 if (inst->opcode == OP_REGVAR) {
5390 g_assert (need_stack_frame);
5391 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5392 if (cfg->verbose_level > 2)
5393 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5398 cfg->code_len = code - cfg->native_code;
5400 g_assert (cfg->code_len < cfg->code_size);
5406 mono_arch_emit_epilog (MonoCompile *cfg)
5408 MonoMethod *method = cfg->method;
5409 MonoMethodSignature *sig = mono_method_signature (method);
5411 guint32 stack_to_pop;
5413 int max_epilog_size = 16;
5415 gboolean need_stack_frame = needs_stack_frame (cfg);
5417 if (cfg->method->save_lmf)
5418 max_epilog_size += 128;
5420 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5421 cfg->code_size *= 2;
5422 cfg->native_code = mono_realloc_native_code(cfg);
5423 cfg->stat_code_reallocs++;
5426 code = cfg->native_code + cfg->code_len;
5428 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5429 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5431 /* the code restoring the registers must be kept in sync with OP_JMP */
5434 if (method->save_lmf) {
5435 gint32 prev_lmf_reg;
5436 gint32 lmf_offset = -sizeof (MonoLMF);
5438 /* check if we need to restore protection of the stack after a stack overflow */
5439 if (mono_get_jit_tls_offset () != -1) {
5441 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5442 /* we load the value in a separate instruction: this mechanism may be
5443 * used later as a safer way to do thread interruption
5445 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5446 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5448 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5449 /* note that the call trampoline will preserve eax/edx */
5450 x86_call_reg (code, X86_ECX);
5451 x86_patch (patch, code);
5453 /* FIXME: maybe save the jit tls in the prolog */
5455 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5457 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5458 * through the mono_lmf_addr TLS variable.
5460 /* reg = previous_lmf */
5461 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5463 /* lmf = previous_lmf */
5464 code = mono_x86_emit_tls_set (code, X86_ECX, lmf_tls_offset);
5466 /* Find a spare register */
5467 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
5470 prev_lmf_reg = X86_EDI;
5471 cfg->used_int_regs |= (1 << X86_EDI);
5474 prev_lmf_reg = X86_EDX;
5478 /* reg = previous_lmf */
5479 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5482 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
5484 /* *(lmf) = previous_lmf */
5485 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
5488 /* restore caller saved regs */
5489 if (cfg->used_int_regs & (1 << X86_EBX)) {
5490 x86_mov_reg_membase (code, X86_EBX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
5493 if (cfg->used_int_regs & (1 << X86_EDI)) {
5494 x86_mov_reg_membase (code, X86_EDI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
5496 if (cfg->used_int_regs & (1 << X86_ESI)) {
5497 x86_mov_reg_membase (code, X86_ESI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
5500 /* EBP is restored by LEAVE */
5502 if (cfg->used_int_regs & (1 << X86_EBX)) {
5505 if (cfg->used_int_regs & (1 << X86_EDI)) {
5508 if (cfg->used_int_regs & (1 << X86_ESI)) {
5513 g_assert (need_stack_frame);
5514 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5517 if (cfg->used_int_regs & (1 << X86_ESI)) {
5518 x86_pop_reg (code, X86_ESI);
5520 if (cfg->used_int_regs & (1 << X86_EDI)) {
5521 x86_pop_reg (code, X86_EDI);
5523 if (cfg->used_int_regs & (1 << X86_EBX)) {
5524 x86_pop_reg (code, X86_EBX);
5528 /* Load returned vtypes into registers if needed */
5529 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5530 if (cinfo->ret.storage == ArgValuetypeInReg) {
5531 for (quad = 0; quad < 2; quad ++) {
5532 switch (cinfo->ret.pair_storage [quad]) {
5534 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5536 case ArgOnFloatFpStack:
5537 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5539 case ArgOnDoubleFpStack:
5540 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5545 g_assert_not_reached ();
5550 if (need_stack_frame)
5553 if (CALLCONV_IS_STDCALL (sig)) {
5554 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5556 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5557 } else if (cinfo->vtype_retaddr)
5563 g_assert (need_stack_frame);
5564 x86_ret_imm (code, stack_to_pop);
5569 cfg->code_len = code - cfg->native_code;
5571 g_assert (cfg->code_len < cfg->code_size);
5575 mono_arch_emit_exceptions (MonoCompile *cfg)
5577 MonoJumpInfo *patch_info;
5580 MonoClass *exc_classes [16];
5581 guint8 *exc_throw_start [16], *exc_throw_end [16];
5585 /* Compute needed space */
5586 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5587 if (patch_info->type == MONO_PATCH_INFO_EXC)
5592 * make sure we have enough space for exceptions
5593 * 16 is the size of two push_imm instructions and a call
5595 if (cfg->compile_aot)
5596 code_size = exc_count * 32;
5598 code_size = exc_count * 16;
5600 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5601 cfg->code_size *= 2;
5602 cfg->native_code = mono_realloc_native_code(cfg);
5603 cfg->stat_code_reallocs++;
5606 code = cfg->native_code + cfg->code_len;
5609 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5610 switch (patch_info->type) {
5611 case MONO_PATCH_INFO_EXC: {
5612 MonoClass *exc_class;
5616 x86_patch (patch_info->ip.i + cfg->native_code, code);
5618 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5619 g_assert (exc_class);
5620 throw_ip = patch_info->ip.i;
5622 /* Find a throw sequence for the same exception class */
5623 for (i = 0; i < nthrows; ++i)
5624 if (exc_classes [i] == exc_class)
5627 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5628 x86_jump_code (code, exc_throw_start [i]);
5629 patch_info->type = MONO_PATCH_INFO_NONE;
5634 /* Compute size of code following the push <OFFSET> */
5635 #if defined(__default_codegen__)
5637 #elif defined(__native_client_codegen__)
5638 code = mono_nacl_align (code);
5639 size = kNaClAlignment;
5641 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5643 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5644 /* Use the shorter form */
5646 x86_push_imm (code, 0);
5650 x86_push_imm (code, 0xf0f0f0f0);
5655 exc_classes [nthrows] = exc_class;
5656 exc_throw_start [nthrows] = code;
5659 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5660 patch_info->data.name = "mono_arch_throw_corlib_exception";
5661 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5662 patch_info->ip.i = code - cfg->native_code;
5663 x86_call_code (code, 0);
5664 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5669 exc_throw_end [nthrows] = code;
5681 cfg->code_len = code - cfg->native_code;
5683 g_assert (cfg->code_len < cfg->code_size);
5687 mono_arch_flush_icache (guint8 *code, gint size)
5693 mono_arch_flush_register_windows (void)
5698 mono_arch_is_inst_imm (gint64 imm)
5704 mono_arch_finish_init (void)
5706 if (!getenv ("MONO_NO_TLS")) {
5709 * We need to init this multiple times, since when we are first called, the key might not
5710 * be initialized yet.
5712 appdomain_tls_offset = mono_domain_get_tls_key ();
5713 lmf_tls_offset = mono_get_jit_tls_key ();
5715 /* Only 64 tls entries can be accessed using inline code */
5716 if (appdomain_tls_offset >= 64)
5717 appdomain_tls_offset = -1;
5718 if (lmf_tls_offset >= 64)
5719 lmf_tls_offset = -1;
5722 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5724 appdomain_tls_offset = mono_domain_get_tls_offset ();
5725 lmf_tls_offset = mono_get_lmf_tls_offset ();
5726 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5732 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5736 #ifdef MONO_ARCH_HAVE_IMT
5738 // Linear handler, the bsearch head compare is shorter
5739 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5740 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5741 // x86_patch(ins,target)
5742 //[1 + 5] x86_jump_mem(inst,mem)
5745 #if defined(__default_codegen__)
5746 #define BR_SMALL_SIZE 2
5747 #define BR_LARGE_SIZE 5
5748 #elif defined(__native_client_codegen__)
5749 /* I suspect the size calculation below is actually incorrect. */
5750 /* TODO: fix the calculation that uses these sizes. */
5751 #define BR_SMALL_SIZE 16
5752 #define BR_LARGE_SIZE 12
5753 #endif /*__native_client_codegen__*/
5754 #define JUMP_IMM_SIZE 6
5755 #define ENABLE_WRONG_METHOD_CHECK 0
5759 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5761 int i, distance = 0;
5762 for (i = start; i < target; ++i)
5763 distance += imt_entries [i]->chunk_size;
5768 * LOCKING: called with the domain lock held
5771 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5772 gpointer fail_tramp)
5776 guint8 *code, *start;
5778 for (i = 0; i < count; ++i) {
5779 MonoIMTCheckItem *item = imt_entries [i];
5780 if (item->is_equals) {
5781 if (item->check_target_idx) {
5782 if (!item->compare_done)
5783 item->chunk_size += CMP_SIZE;
5784 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5787 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5789 item->chunk_size += JUMP_IMM_SIZE;
5790 #if ENABLE_WRONG_METHOD_CHECK
5791 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5796 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5797 imt_entries [item->check_target_idx]->compare_done = TRUE;
5799 size += item->chunk_size;
5801 #if defined(__native_client__) && defined(__native_client_codegen__)
5802 /* In Native Client, we don't re-use thunks, allocate from the */
5803 /* normal code manager paths. */
5804 code = mono_domain_code_reserve (domain, size);
5807 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5809 code = mono_domain_code_reserve (domain, size);
5812 for (i = 0; i < count; ++i) {
5813 MonoIMTCheckItem *item = imt_entries [i];
5814 item->code_target = code;
5815 if (item->is_equals) {
5816 if (item->check_target_idx) {
5817 if (!item->compare_done)
5818 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5819 item->jmp_code = code;
5820 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5821 if (item->has_target_code)
5822 x86_jump_code (code, item->value.target_code);
5824 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5827 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5828 item->jmp_code = code;
5829 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5830 if (item->has_target_code)
5831 x86_jump_code (code, item->value.target_code);
5833 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5834 x86_patch (item->jmp_code, code);
5835 x86_jump_code (code, fail_tramp);
5836 item->jmp_code = NULL;
5838 /* enable the commented code to assert on wrong method */
5839 #if ENABLE_WRONG_METHOD_CHECK
5840 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5841 item->jmp_code = code;
5842 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5844 if (item->has_target_code)
5845 x86_jump_code (code, item->value.target_code);
5847 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5848 #if ENABLE_WRONG_METHOD_CHECK
5849 x86_patch (item->jmp_code, code);
5850 x86_breakpoint (code);
5851 item->jmp_code = NULL;
5856 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5857 item->jmp_code = code;
5858 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5859 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5861 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5864 /* patch the branches to get to the target items */
5865 for (i = 0; i < count; ++i) {
5866 MonoIMTCheckItem *item = imt_entries [i];
5867 if (item->jmp_code) {
5868 if (item->check_target_idx) {
5869 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5875 mono_stats.imt_thunks_size += code - start;
5876 g_assert (code - start <= size);
5880 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5881 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5885 if (mono_jit_map_is_enabled ()) {
5888 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5890 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5891 mono_emit_jit_tramp (start, code - start, buff);
5895 nacl_domain_code_validate (domain, &start, size, &code);
5901 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5903 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5908 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5910 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5914 mono_arch_get_cie_program (void)
5918 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5919 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5925 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5927 MonoInst *ins = NULL;
5930 if (cmethod->klass == mono_defaults.math_class) {
5931 if (strcmp (cmethod->name, "Sin") == 0) {
5933 } else if (strcmp (cmethod->name, "Cos") == 0) {
5935 } else if (strcmp (cmethod->name, "Tan") == 0) {
5937 } else if (strcmp (cmethod->name, "Atan") == 0) {
5939 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5941 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5943 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5948 MONO_INST_NEW (cfg, ins, opcode);
5949 ins->type = STACK_R8;
5950 ins->dreg = mono_alloc_freg (cfg);
5951 ins->sreg1 = args [0]->dreg;
5952 MONO_ADD_INS (cfg->cbb, ins);
5955 if (cfg->opt & MONO_OPT_CMOV) {
5958 if (strcmp (cmethod->name, "Min") == 0) {
5959 if (fsig->params [0]->type == MONO_TYPE_I4)
5961 } else if (strcmp (cmethod->name, "Max") == 0) {
5962 if (fsig->params [0]->type == MONO_TYPE_I4)
5967 MONO_INST_NEW (cfg, ins, opcode);
5968 ins->type = STACK_I4;
5969 ins->dreg = mono_alloc_ireg (cfg);
5970 ins->sreg1 = args [0]->dreg;
5971 ins->sreg2 = args [1]->dreg;
5972 MONO_ADD_INS (cfg->cbb, ins);
5977 /* OP_FREM is not IEEE compatible */
5978 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5979 MONO_INST_NEW (cfg, ins, OP_FREM);
5980 ins->inst_i0 = args [0];
5981 ins->inst_i1 = args [1];
5990 mono_arch_print_tree (MonoInst *tree, int arity)
5995 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6001 if (appdomain_tls_offset == -1)
6004 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6005 ins->inst_offset = appdomain_tls_offset;
6010 mono_arch_get_patch_offset (guint8 *code)
6012 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
6014 else if (code [0] == 0xba)
6016 else if (code [0] == 0x68)
6019 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
6020 /* push <OFFSET>(<REG>) */
6022 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
6023 /* call *<OFFSET>(<REG>) */
6025 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
6028 else if ((code [0] == 0x58) && (code [1] == 0x05))
6029 /* pop %eax; add <OFFSET>, %eax */
6031 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6032 /* pop <REG>; add <OFFSET>, <REG> */
6034 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6035 /* mov <REG>, imm */
6038 g_assert_not_reached ();
6044 * mono_breakpoint_clean_code:
6046 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6047 * breakpoints in the original code, they are removed in the copy.
6049 * Returns TRUE if no sw breakpoint was present.
6052 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6055 gboolean can_write = TRUE;
6057 * If method_start is non-NULL we need to perform bound checks, since we access memory
6058 * at code - offset we could go before the start of the method and end up in a different
6059 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6062 if (!method_start || code - offset >= method_start) {
6063 memcpy (buf, code - offset, size);
6065 int diff = code - method_start;
6066 memset (buf, 0, size);
6067 memcpy (buf + offset - diff, method_start, diff + size - offset);
6070 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6071 int idx = mono_breakpoint_info_index [i];
6075 ptr = mono_breakpoint_info [idx].address;
6076 if (ptr >= code && ptr < code + size) {
6077 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6079 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6080 buf [ptr - code] = saved_byte;
6087 * mono_x86_get_this_arg_offset:
6089 * Return the offset of the stack location where this is passed during a virtual
6093 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6099 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6101 guint32 esp = regs [X86_ESP];
6102 CallInfo *cinfo = NULL;
6109 * The stack looks like:
6113 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
6115 res = (((MonoObject**)esp) [5 + (offset / 4)]);
6121 #define MAX_ARCH_DELEGATE_PARAMS 10
6124 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6126 guint8 *code, *start;
6127 int code_reserve = 64;
6130 * The stack contains:
6136 start = code = mono_global_codeman_reserve (code_reserve);
6138 /* Replace the this argument with the target */
6139 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6140 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
6141 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6142 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6144 g_assert ((code - start) < code_reserve);
6147 /* 8 for mov_reg and jump, plus 8 for each parameter */
6148 #ifdef __native_client_codegen__
6149 /* TODO: calculate this size correctly */
6150 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6152 code_reserve = 8 + (param_count * 8);
6153 #endif /* __native_client_codegen__ */
6155 * The stack contains:
6156 * <args in reverse order>
6161 * <args in reverse order>
6164 * without unbalancing the stack.
6165 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6166 * and leaving original spot of first arg as placeholder in stack so
6167 * when callee pops stack everything works.
6170 start = code = mono_global_codeman_reserve (code_reserve);
6172 /* store delegate for access to method_ptr */
6173 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6176 for (i = 0; i < param_count; ++i) {
6177 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6178 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6181 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6183 g_assert ((code - start) < code_reserve);
6186 nacl_global_codeman_validate(&start, code_reserve, &code);
6187 mono_debug_add_delegate_trampoline (start, code - start);
6190 *code_len = code - start;
6192 if (mono_jit_map_is_enabled ()) {
6195 buff = (char*)"delegate_invoke_has_target";
6197 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6198 mono_emit_jit_tramp (start, code - start, buff);
6207 mono_arch_get_delegate_invoke_impls (void)
6214 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6215 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
6217 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6218 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6219 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
6226 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6228 guint8 *code, *start;
6230 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6233 /* FIXME: Support more cases */
6234 if (MONO_TYPE_ISSTRUCT (sig->ret))
6238 * The stack contains:
6244 static guint8* cached = NULL;
6249 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6251 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6253 mono_memory_barrier ();
6257 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6260 for (i = 0; i < sig->param_count; ++i)
6261 if (!mono_is_regsize_var (sig->params [i]))
6264 code = cache [sig->param_count];
6268 if (mono_aot_only) {
6269 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6270 start = mono_aot_get_trampoline (name);
6273 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6276 mono_memory_barrier ();
6278 cache [sig->param_count] = start;
6285 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6288 case X86_EAX: return ctx->eax;
6289 case X86_EBX: return ctx->ebx;
6290 case X86_ECX: return ctx->ecx;
6291 case X86_EDX: return ctx->edx;
6292 case X86_ESP: return ctx->esp;
6293 case X86_EBP: return ctx->ebp;
6294 case X86_ESI: return ctx->esi;
6295 case X86_EDI: return ctx->edi;
6297 g_assert_not_reached ();
6303 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6331 g_assert_not_reached ();
6335 #ifdef MONO_ARCH_SIMD_INTRINSICS
6338 get_float_to_x_spill_area (MonoCompile *cfg)
6340 if (!cfg->fconv_to_r8_x_var) {
6341 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6342 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6344 return cfg->fconv_to_r8_x_var;
6348 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6351 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6354 int dreg, src_opcode;
6356 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6359 switch (src_opcode = ins->opcode) {
6360 case OP_FCONV_TO_I1:
6361 case OP_FCONV_TO_U1:
6362 case OP_FCONV_TO_I2:
6363 case OP_FCONV_TO_U2:
6364 case OP_FCONV_TO_I4:
6371 /* dreg is the IREG and sreg1 is the FREG */
6372 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6373 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6374 fconv->sreg1 = ins->sreg1;
6375 fconv->dreg = mono_alloc_ireg (cfg);
6376 fconv->type = STACK_VTYPE;
6377 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6379 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6383 ins->opcode = OP_XCONV_R8_TO_I4;
6385 ins->klass = mono_defaults.int32_class;
6386 ins->sreg1 = fconv->dreg;
6388 ins->type = STACK_I4;
6389 ins->backend.source_opcode = src_opcode;
6392 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6395 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6400 if (long_ins->opcode == OP_LNEG) {
6402 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6403 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6404 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6409 #ifdef MONO_ARCH_SIMD_INTRINSICS
6411 if (!(cfg->opt & MONO_OPT_SIMD))
6414 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6415 switch (long_ins->opcode) {
6417 vreg = long_ins->sreg1;
6419 if (long_ins->inst_c0) {
6420 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6421 ins->klass = long_ins->klass;
6422 ins->sreg1 = long_ins->sreg1;
6424 ins->type = STACK_VTYPE;
6425 ins->dreg = vreg = alloc_ireg (cfg);
6426 MONO_ADD_INS (cfg->cbb, ins);
6429 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6430 ins->klass = mono_defaults.int32_class;
6432 ins->type = STACK_I4;
6433 ins->dreg = long_ins->dreg + 1;
6434 MONO_ADD_INS (cfg->cbb, ins);
6436 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6437 ins->klass = long_ins->klass;
6438 ins->sreg1 = long_ins->sreg1;
6439 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6440 ins->type = STACK_VTYPE;
6441 ins->dreg = vreg = alloc_ireg (cfg);
6442 MONO_ADD_INS (cfg->cbb, ins);
6444 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6445 ins->klass = mono_defaults.int32_class;
6447 ins->type = STACK_I4;
6448 ins->dreg = long_ins->dreg + 2;
6449 MONO_ADD_INS (cfg->cbb, ins);
6451 long_ins->opcode = OP_NOP;
6453 case OP_INSERTX_I8_SLOW:
6454 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6455 ins->dreg = long_ins->dreg;
6456 ins->sreg1 = long_ins->dreg;
6457 ins->sreg2 = long_ins->sreg2 + 1;
6458 ins->inst_c0 = long_ins->inst_c0 * 2;
6459 MONO_ADD_INS (cfg->cbb, ins);
6461 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6462 ins->dreg = long_ins->dreg;
6463 ins->sreg1 = long_ins->dreg;
6464 ins->sreg2 = long_ins->sreg2 + 2;
6465 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6466 MONO_ADD_INS (cfg->cbb, ins);
6468 long_ins->opcode = OP_NOP;
6471 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6472 ins->dreg = long_ins->dreg;
6473 ins->sreg1 = long_ins->sreg1 + 1;
6474 ins->klass = long_ins->klass;
6475 ins->type = STACK_VTYPE;
6476 MONO_ADD_INS (cfg->cbb, ins);
6478 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6479 ins->dreg = long_ins->dreg;
6480 ins->sreg1 = long_ins->dreg;
6481 ins->sreg2 = long_ins->sreg1 + 2;
6483 ins->klass = long_ins->klass;
6484 ins->type = STACK_VTYPE;
6485 MONO_ADD_INS (cfg->cbb, ins);
6487 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6488 ins->dreg = long_ins->dreg;
6489 ins->sreg1 = long_ins->dreg;;
6490 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6491 ins->klass = long_ins->klass;
6492 ins->type = STACK_VTYPE;
6493 MONO_ADD_INS (cfg->cbb, ins);
6495 long_ins->opcode = OP_NOP;
6498 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6501 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6503 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6506 gpointer *sp, old_value;
6508 const unsigned char *handler;
6510 /*Decode the first instruction to figure out where did we store the spvar*/
6511 /*Our jit MUST generate the following:
6513 Which is encoded as: 0x89 mod_rm.
6514 mod_rm (esp, ebp, imm) which can be: (imm will never be zero)
6515 mod (reg + imm8): 01 reg(esp): 100 rm(ebp): 101 -> 01100101 (0x65)
6516 mod (reg + imm32): 10 reg(esp): 100 rm(ebp): 101 -> 10100101 (0xA5)
6518 handler = clause->handler_start;
6520 if (*handler != 0x89)
6525 if (*handler == 0x65)
6526 offset = *(signed char*)(handler + 1);
6527 else if (*handler == 0xA5)
6528 offset = *(int*)(handler + 1);
6533 bp = MONO_CONTEXT_GET_BP (ctx);
6534 sp = *(gpointer*)(bp + offset);
6537 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6546 * mono_aot_emit_load_got_addr:
6548 * Emit code to load the got address.
6549 * On x86, the result is placed into EBX.
6552 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6554 x86_call_imm (code, 0);
6556 * The patch needs to point to the pop, since the GOT offset needs
6557 * to be added to that address.
6560 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6562 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6563 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6564 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6570 * mono_ppc_emit_load_aotconst:
6572 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6573 * TARGET from the mscorlib GOT in full-aot code.
6574 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6578 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6580 /* Load the mscorlib got address */
6581 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6582 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6583 /* arch_emit_got_access () patches this */
6584 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6589 /* Can't put this into mini-x86.h */
6591 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6594 mono_arch_get_trampolines (gboolean aot)
6596 MonoTrampInfo *info;
6597 GSList *tramps = NULL;
6599 mono_x86_get_signal_exception_trampoline (&info, aot);
6601 tramps = g_slist_append (tramps, info);
6608 #define DBG_SIGNAL SIGBUS
6610 #define DBG_SIGNAL SIGSEGV
6613 /* Soft Debug support */
6614 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6617 * mono_arch_set_breakpoint:
6619 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6620 * The location should contain code emitted by OP_SEQ_POINT.
6623 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6628 * In production, we will use int3 (has to fix the size in the md
6629 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6632 g_assert (code [0] == 0x90);
6633 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6637 * mono_arch_clear_breakpoint:
6639 * Clear the breakpoint at IP.
6642 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6647 for (i = 0; i < 6; ++i)
6652 * mono_arch_start_single_stepping:
6654 * Start single stepping.
6657 mono_arch_start_single_stepping (void)
6659 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6663 * mono_arch_stop_single_stepping:
6665 * Stop single stepping.
6668 mono_arch_stop_single_stepping (void)
6670 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6674 * mono_arch_is_single_step_event:
6676 * Return whenever the machine state in SIGCTX corresponds to a single
6680 mono_arch_is_single_step_event (void *info, void *sigctx)
6683 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6685 if ((einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6690 siginfo_t* sinfo = (siginfo_t*) info;
6691 /* Sometimes the address is off by 4 */
6692 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6700 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6703 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6704 if ((einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6709 siginfo_t* sinfo = (siginfo_t*)info;
6710 /* Sometimes the address is off by 4 */
6711 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6718 #define BREAKPOINT_SIZE 6
6721 * mono_arch_skip_breakpoint:
6723 * See mini-amd64.c for docs.
6726 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6728 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6732 * mono_arch_skip_single_step:
6734 * See mini-amd64.c for docs.
6737 mono_arch_skip_single_step (MonoContext *ctx)
6739 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6743 * mono_arch_get_seq_point_info:
6745 * See mini-amd64.c for docs.
6748 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6756 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
6758 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6760 #endif /* !MONOTOUCH */