2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * (C) 2003 Ximian, Inc.
15 #include <mono/metadata/appdomain.h>
16 #include <mono/metadata/debug-helpers.h>
17 #include <mono/metadata/threads.h>
18 #include <mono/metadata/profiler-private.h>
19 #include <mono/utils/mono-math.h>
24 #include "cpu-pentium.h"
26 static gint lmf_tls_offset = -1;
27 static gint appdomain_tls_offset = -1;
28 static gint thread_tls_offset = -1;
31 /* Under windows, the default pinvoke calling convention is stdcall */
32 #define CALLCONV_IS_STDCALL(call_conv) (((call_conv) == MONO_CALL_STDCALL) || ((call_conv) == MONO_CALL_DEFAULT))
34 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
37 #define SIGNAL_STACK_SIZE (64 * 1024)
40 mono_arch_regname (int reg) {
42 case X86_EAX: return "%eax";
43 case X86_EBX: return "%ebx";
44 case X86_ECX: return "%ecx";
45 case X86_EDX: return "%edx";
46 case X86_ESP: return "%esp"; case X86_EBP: return "%ebp";
47 case X86_EDI: return "%edi";
48 case X86_ESI: return "%esi";
54 * mono_arch_get_argument_info:
55 * @csig: a method signature
56 * @param_count: the number of parameters to consider
57 * @arg_info: an array to store the result infos
59 * Gathers information on parameters such as size, alignment and
60 * padding. arg_info should be large enought to hold param_count + 1 entries.
62 * Returns the size of the activation frame.
65 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
67 int k, frame_size = 0;
71 if (MONO_TYPE_ISSTRUCT (csig->ret)) {
72 frame_size += sizeof (gpointer);
76 arg_info [0].offset = offset;
79 frame_size += sizeof (gpointer);
83 arg_info [0].size = frame_size;
85 for (k = 0; k < param_count; k++) {
88 size = mono_type_native_stack_size (csig->params [k], &align);
90 size = mono_type_stack_size (csig->params [k], &align);
92 /* ignore alignment for now */
95 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
96 arg_info [k].pad = pad;
98 arg_info [k + 1].pad = 0;
99 arg_info [k + 1].size = size;
101 arg_info [k + 1].offset = offset;
105 align = MONO_ARCH_FRAME_ALIGNMENT;
106 frame_size += pad = (align - (frame_size & (align - 1))) & (align - 1);
107 arg_info [k].pad = pad;
112 static const guchar cpuid_impl [] = {
113 0x55, /* push %ebp */
114 0x89, 0xe5, /* mov %esp,%ebp */
115 0x53, /* push %ebx */
116 0x8b, 0x45, 0x08, /* mov 0x8(%ebp),%eax */
117 0x0f, 0xa2, /* cpuid */
118 0x50, /* push %eax */
119 0x8b, 0x45, 0x10, /* mov 0x10(%ebp),%eax */
120 0x89, 0x18, /* mov %ebx,(%eax) */
121 0x8b, 0x45, 0x14, /* mov 0x14(%ebp),%eax */
122 0x89, 0x08, /* mov %ecx,(%eax) */
123 0x8b, 0x45, 0x18, /* mov 0x18(%ebp),%eax */
124 0x89, 0x10, /* mov %edx,(%eax) */
126 0x8b, 0x55, 0x0c, /* mov 0xc(%ebp),%edx */
127 0x89, 0x02, /* mov %eax,(%edx) */
133 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
136 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
139 __asm__ __volatile__ (
142 "movl %%eax, %%edx\n"
143 "xorl $0x200000, %%eax\n"
148 "xorl %%edx, %%eax\n"
149 "andl $0x200000, %%eax\n"
157 CpuidFunc func = (CpuidFunc)cpuid_impl;
158 func (id, p_eax, p_ebx, p_ecx, p_edx);
160 * We use this approach because of issues with gcc and pic code, see:
161 * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
162 __asm__ __volatile__ ("cpuid"
163 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
172 * Initialize the cpu to execute managed code.
175 mono_arch_cpu_init (void)
179 /* spec compliance requires running with double precision */
180 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
181 fpcw &= ~X86_FPCW_PRECC_MASK;
182 fpcw |= X86_FPCW_PREC_DOUBLE;
183 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
184 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
189 * This function returns the optimizations supported on this cpu.
192 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
194 int eax, ebx, ecx, edx;
198 /* Feature Flags function, flags returned in EDX. */
199 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
200 if (edx & (1 << 15)) {
201 opts |= MONO_OPT_CMOV;
203 opts |= MONO_OPT_FCMOV;
205 *exclude_mask |= MONO_OPT_FCMOV;
207 *exclude_mask |= MONO_OPT_CMOV;
213 * Determine whenever the trap whose info is in SIGINFO is caused by
217 mono_arch_is_int_overflow (void *sigctx)
219 struct sigcontext *ctx = (struct sigcontext*)sigctx;
222 ip = (guint8*)ctx->SC_EIP;
224 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
228 switch (x86_modrm_rm (ip [1])) {
236 g_assert_not_reached ();
248 is_regsize_var (MonoType *t) {
251 switch (mono_type_get_underlying_type (t)->type) {
258 case MONO_TYPE_OBJECT:
259 case MONO_TYPE_STRING:
260 case MONO_TYPE_CLASS:
261 case MONO_TYPE_SZARRAY:
262 case MONO_TYPE_ARRAY:
264 case MONO_TYPE_VALUETYPE:
271 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
276 for (i = 0; i < cfg->num_varinfo; i++) {
277 MonoInst *ins = cfg->varinfo [i];
278 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
281 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
284 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
285 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
288 /* we dont allocate I1 to registers because there is no simply way to sign extend
289 * 8bit quantities in caller saved registers on x86 */
290 if (is_regsize_var (ins->inst_vtype) || (ins->inst_vtype->type == MONO_TYPE_BOOLEAN) ||
291 (ins->inst_vtype->type == MONO_TYPE_U1) || (ins->inst_vtype->type == MONO_TYPE_U2)||
292 (ins->inst_vtype->type == MONO_TYPE_I2) || (ins->inst_vtype->type == MONO_TYPE_CHAR)) {
293 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
294 g_assert (i == vmv->idx);
295 vars = g_list_prepend (vars, vmv);
299 vars = mono_varlist_sort (cfg, vars, 0);
305 mono_arch_get_global_int_regs (MonoCompile *cfg)
309 /* we can use 3 registers for global allocation */
310 regs = g_list_prepend (regs, (gpointer)X86_EBX);
311 regs = g_list_prepend (regs, (gpointer)X86_ESI);
312 regs = g_list_prepend (regs, (gpointer)X86_EDI);
318 * mono_arch_regalloc_cost:
320 * Return the cost, in number of memory references, of the action of
321 * allocating the variable VMV into a register during global register
325 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
327 MonoInst *ins = cfg->varinfo [vmv->idx];
329 if (cfg->method->save_lmf)
330 /* The register is already saved */
331 return (ins->opcode == OP_ARG) ? 1 : 0;
333 /* push+pop+possible load if it is an argument */
334 return (ins->opcode == OP_ARG) ? 3 : 2;
338 * Set var information according to the calling convention. X86 version.
339 * The locals var stuff should most likely be split in another method.
342 mono_arch_allocate_vars (MonoCompile *m)
344 MonoMethodSignature *sig;
345 MonoMethodHeader *header;
347 int i, offset, size, align, curinst;
349 header = ((MonoMethodNormal *)m->method)->header;
351 sig = m->method->signature;
355 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
356 m->ret->opcode = OP_REGOFFSET;
357 m->ret->inst_basereg = X86_EBP;
358 m->ret->inst_offset = offset;
359 offset += sizeof (gpointer);
361 /* FIXME: handle long and FP values */
362 switch (sig->ret->type) {
366 m->ret->opcode = OP_REGVAR;
367 m->ret->inst_c0 = X86_EAX;
372 inst = m->varinfo [curinst];
373 if (inst->opcode != OP_REGVAR) {
374 inst->opcode = OP_REGOFFSET;
375 inst->inst_basereg = X86_EBP;
377 inst->inst_offset = offset;
378 offset += sizeof (gpointer);
382 if (sig->call_convention == MONO_CALL_VARARG) {
383 m->sig_cookie = offset;
384 offset += sizeof (gpointer);
387 for (i = 0; i < sig->param_count; ++i) {
388 inst = m->varinfo [curinst];
389 if (inst->opcode != OP_REGVAR) {
390 inst->opcode = OP_REGOFFSET;
391 inst->inst_basereg = X86_EBP;
393 inst->inst_offset = offset;
394 size = mono_type_size (sig->params [i], &align);
403 /* reserve space to save LMF and caller saved registers */
405 if (m->method->save_lmf) {
406 offset += sizeof (MonoLMF);
408 if (m->used_int_regs & (1 << X86_EBX)) {
412 if (m->used_int_regs & (1 << X86_EDI)) {
416 if (m->used_int_regs & (1 << X86_ESI)) {
421 for (i = curinst; i < m->num_varinfo; ++i) {
422 inst = m->varinfo [i];
424 if ((inst->flags & MONO_INST_IS_DEAD) || inst->opcode == OP_REGVAR)
427 /* inst->unused indicates native sized value types, this is used by the
428 * pinvoke wrappers when they call functions returning structure */
429 if (inst->unused && MONO_TYPE_ISSTRUCT (inst->inst_vtype) && inst->inst_vtype->type != MONO_TYPE_TYPEDBYREF)
430 size = mono_class_native_size (inst->inst_vtype->data.klass, &align);
432 size = mono_type_size (inst->inst_vtype, &align);
436 offset &= ~(align - 1);
437 inst->opcode = OP_REGOFFSET;
438 inst->inst_basereg = X86_EBP;
439 inst->inst_offset = -offset;
440 //g_print ("allocating local %d to %d\n", i, -offset);
442 offset += (MONO_ARCH_FRAME_ALIGNMENT - 1);
443 offset &= ~(MONO_ARCH_FRAME_ALIGNMENT - 1);
446 m->stack_offset = -offset;
449 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
450 * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
454 * take the arguments and generate the arch-specific
455 * instructions to properly call the function in call.
456 * This includes pushing, moving arguments to the right register
458 * Issue: who does the spilling if needed, and when?
461 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
463 MonoMethodSignature *sig;
464 int i, n, stack_size, type;
468 /* add the vararg cookie before the non-implicit args */
469 if (call->signature->call_convention == MONO_CALL_VARARG) {
471 /* FIXME: Add support for signature tokens to AOT */
472 cfg->disable_aot = TRUE;
473 MONO_INST_NEW (cfg, arg, OP_OUTARG);
474 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
475 sig_arg->inst_p0 = call->signature;
476 arg->inst_left = sig_arg;
477 arg->type = STACK_PTR;
478 /* prepend, so they get reversed */
479 arg->next = call->out_args;
480 call->out_args = arg;
481 stack_size += sizeof (gpointer);
483 sig = call->signature;
484 n = sig->param_count + sig->hasthis;
486 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret))
487 stack_size += sizeof (gpointer);
488 for (i = 0; i < n; ++i) {
489 if (is_virtual && i == 0) {
490 /* the argument will be attached to the call instrucion */
494 MONO_INST_NEW (cfg, arg, OP_OUTARG);
496 arg->cil_code = in->cil_code;
498 arg->type = in->type;
499 /* prepend, so they get reversed */
500 arg->next = call->out_args;
501 call->out_args = arg;
502 if (i >= sig->hasthis) {
503 ptype = mono_type_get_underlying_type (sig->params [i - sig->hasthis]);
508 /* FIXME: validate arguments... */
512 case MONO_TYPE_BOOLEAN:
520 case MONO_TYPE_STRING:
521 case MONO_TYPE_CLASS:
522 case MONO_TYPE_OBJECT:
524 case MONO_TYPE_FNPTR:
525 case MONO_TYPE_ARRAY:
526 case MONO_TYPE_SZARRAY:
535 arg->opcode = OP_OUTARG_R4;
539 arg->opcode = OP_OUTARG_R8;
541 case MONO_TYPE_VALUETYPE: {
544 size = mono_type_native_stack_size (&in->klass->byval_arg, NULL);
546 size = mono_type_stack_size (&in->klass->byval_arg, NULL);
549 arg->opcode = OP_OUTARG_VT;
550 arg->klass = in->klass;
551 arg->unused = sig->pinvoke;
552 arg->inst_imm = size;
555 case MONO_TYPE_TYPEDBYREF:
556 stack_size += sizeof (MonoTypedRef);
557 arg->opcode = OP_OUTARG_VT;
558 arg->klass = in->klass;
559 arg->unused = sig->pinvoke;
560 arg->inst_imm = sizeof (MonoTypedRef);
563 g_error ("unknown type 0x%02x in mono_arch_call_opcode\n", type);
566 /* the this argument */
571 /* if the function returns a struct, the called method already does a ret $0x4 */
572 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret))
574 call->stack_usage = stack_size;
576 * should set more info in call, such as the stack space
577 * used by the args that needs to be added back to esp
584 * Allow tracing to work with this interface (with an optional argument)
588 * This may be needed on some archs or for debugging support.
591 mono_arch_instrument_mem_needs (MonoMethod *method, int *stack, int *code)
593 /* no stack room needed now (may be needed for FASTCALL-trace support) */
595 /* split prolog-epilog requirements? */
596 *code = 50; /* max bytes needed: check this number */
600 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
604 /* if some args are passed in registers, we need to save them here */
605 x86_push_reg (code, X86_EBP);
606 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
607 x86_push_imm (code, cfg->method);
608 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
609 x86_call_code (code, 0);
610 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
624 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
627 int arg_size = 0, save_mode = SAVE_NONE;
628 MonoMethod *method = cfg->method;
630 switch (mono_type_get_underlying_type (method->signature->ret)->type) {
632 /* special case string .ctor icall */
633 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
634 save_mode = SAVE_EAX;
636 save_mode = SAVE_NONE;
640 save_mode = SAVE_EAX_EDX;
646 case MONO_TYPE_VALUETYPE:
647 save_mode = SAVE_STRUCT;
650 save_mode = SAVE_EAX;
656 x86_push_reg (code, X86_EDX);
657 x86_push_reg (code, X86_EAX);
658 if (enable_arguments) {
659 x86_push_reg (code, X86_EDX);
660 x86_push_reg (code, X86_EAX);
665 x86_push_reg (code, X86_EAX);
666 if (enable_arguments) {
667 x86_push_reg (code, X86_EAX);
672 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
673 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
674 if (enable_arguments) {
675 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
676 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
681 if (enable_arguments) {
682 x86_push_membase (code, X86_EBP, 8);
692 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
693 x86_push_imm (code, method);
694 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
695 x86_call_code (code, 0);
696 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
700 x86_pop_reg (code, X86_EAX);
701 x86_pop_reg (code, X86_EDX);
704 x86_pop_reg (code, X86_EAX);
707 x86_fld_membase (code, X86_ESP, 0, TRUE);
708 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
718 #define EMIT_COND_BRANCH(ins,cond,sign) \
719 if (ins->flags & MONO_INST_BRLABEL) { \
720 if (ins->inst_i0->inst_c0) { \
721 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
723 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
724 if ((cfg->opt & MONO_OPT_BRANCH) && \
725 x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
726 x86_branch8 (code, cond, 0, sign); \
728 x86_branch32 (code, cond, 0, sign); \
731 if (ins->inst_true_bb->native_offset) { \
732 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
734 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
735 if ((cfg->opt & MONO_OPT_BRANCH) && \
736 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
737 x86_branch8 (code, cond, 0, sign); \
739 x86_branch32 (code, cond, 0, sign); \
743 /* emit an exception if condition is fail */
744 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
746 mono_add_patch_info (cfg, code - cfg->native_code, \
747 MONO_PATCH_INFO_EXC, exc_name); \
748 x86_branch32 (code, cond, 0, signed); \
751 #define EMIT_FPCOMPARE(code) do { \
756 /* FIXME: Add more instructions */
757 #define INST_IGNORES_CFLAGS(ins) (((ins)->opcode == CEE_BR) || ((ins)->opcode == OP_STORE_MEMBASE_IMM))
760 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
762 MonoInst *ins, *last_ins = NULL;
767 switch (ins->opcode) {
769 /* reg = 0 -> XOR (reg, reg) */
770 /* XOR sets cflags on x86, so we cant do it always */
771 if (ins->inst_c0 == 0 && ins->next && INST_IGNORES_CFLAGS (ins->next)) {
772 ins->opcode = CEE_XOR;
773 ins->sreg1 = ins->dreg;
774 ins->sreg2 = ins->dreg;
778 /* remove unnecessary multiplication with 1 */
779 if (ins->inst_imm == 1) {
780 if (ins->dreg != ins->sreg1) {
781 ins->opcode = OP_MOVE;
783 last_ins->next = ins->next;
790 /* OP_COMPARE_IMM (reg, 0)
792 * OP_X86_TEST_NULL (reg)
795 ins->opcode = OP_X86_TEST_NULL;
797 case OP_X86_COMPARE_MEMBASE_IMM:
799 * OP_STORE_MEMBASE_REG reg, offset(basereg)
800 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
802 * OP_STORE_MEMBASE_REG reg, offset(basereg)
803 * OP_COMPARE_IMM reg, imm
805 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
807 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
808 ins->inst_basereg == last_ins->inst_destbasereg &&
809 ins->inst_offset == last_ins->inst_offset) {
810 ins->opcode = OP_COMPARE_IMM;
811 ins->sreg1 = last_ins->sreg1;
813 /* check if we can remove cmp reg,0 with test null */
815 ins->opcode = OP_X86_TEST_NULL;
819 case OP_LOAD_MEMBASE:
820 case OP_LOADI4_MEMBASE:
822 * Note: if reg1 = reg2 the load op is removed
824 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
825 * OP_LOAD_MEMBASE offset(basereg), reg2
827 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
830 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
831 || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
832 ins->inst_basereg == last_ins->inst_destbasereg &&
833 ins->inst_offset == last_ins->inst_offset) {
834 if (ins->dreg == last_ins->sreg1) {
835 last_ins->next = ins->next;
839 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
840 ins->opcode = OP_MOVE;
841 ins->sreg1 = last_ins->sreg1;
845 * Note: reg1 must be different from the basereg in the second load
846 * Note: if reg1 = reg2 is equal then second load is removed
848 * OP_LOAD_MEMBASE offset(basereg), reg1
849 * OP_LOAD_MEMBASE offset(basereg), reg2
851 * OP_LOAD_MEMBASE offset(basereg), reg1
854 } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
855 || last_ins->opcode == OP_LOAD_MEMBASE) &&
856 ins->inst_basereg != last_ins->dreg &&
857 ins->inst_basereg == last_ins->inst_basereg &&
858 ins->inst_offset == last_ins->inst_offset) {
860 if (ins->dreg == last_ins->dreg) {
861 last_ins->next = ins->next;
865 ins->opcode = OP_MOVE;
866 ins->sreg1 = last_ins->dreg;
869 //g_assert_not_reached ();
873 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
874 * OP_LOAD_MEMBASE offset(basereg), reg
876 * OP_STORE_MEMBASE_IMM imm, offset(basereg)
879 } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
880 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
881 ins->inst_basereg == last_ins->inst_destbasereg &&
882 ins->inst_offset == last_ins->inst_offset) {
883 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
884 ins->opcode = OP_ICONST;
885 ins->inst_c0 = last_ins->inst_imm;
886 g_assert_not_reached (); // check this rule
890 case OP_LOADU1_MEMBASE:
891 case OP_LOADI1_MEMBASE:
893 * Note: if reg1 = reg2 the load op is removed
895 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
896 * OP_LOAD_MEMBASE offset(basereg), reg2
898 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
901 if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
902 ins->inst_basereg == last_ins->inst_destbasereg &&
903 ins->inst_offset == last_ins->inst_offset) {
904 if (ins->dreg == last_ins->sreg1) {
905 last_ins->next = ins->next;
909 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
910 ins->opcode = OP_MOVE;
911 ins->sreg1 = last_ins->sreg1;
915 case OP_LOADU2_MEMBASE:
916 case OP_LOADI2_MEMBASE:
918 * Note: if reg1 = reg2 the load op is removed
920 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
921 * OP_LOAD_MEMBASE offset(basereg), reg2
923 * OP_STORE_MEMBASE_REG reg1, offset(basereg)
926 if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
927 ins->inst_basereg == last_ins->inst_destbasereg &&
928 ins->inst_offset == last_ins->inst_offset) {
929 if (ins->dreg == last_ins->sreg1) {
930 last_ins->next = ins->next;
934 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
935 ins->opcode = OP_MOVE;
936 ins->sreg1 = last_ins->sreg1;
948 if (ins->dreg == ins->sreg1) {
950 last_ins->next = ins->next;
960 if (last_ins && last_ins->opcode == OP_MOVE &&
961 ins->sreg1 == last_ins->dreg &&
962 ins->dreg == last_ins->sreg1) {
963 last_ins->next = ins->next;
972 bb->last_ins = last_ins;
976 branch_cc_table [] = {
977 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
978 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
979 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
982 #define DEBUG(a) if (cfg->verbose_level > 1) a
986 * returns the offset used by spillvar. It allocates a new
987 * spill variable if necessary.
990 mono_spillvar_offset (MonoCompile *cfg, int spillvar)
992 MonoSpillInfo **si, *info;
995 si = &cfg->spill_info;
997 while (i <= spillvar) {
1000 *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
1002 cfg->stack_offset -= sizeof (gpointer);
1003 info->offset = cfg->stack_offset;
1007 return (*si)->offset;
1013 g_assert_not_reached ();
1018 * returns the offset used by spillvar. It allocates a new
1019 * spill float variable if necessary.
1020 * (same as mono_spillvar_offset but for float)
1023 mono_spillvar_offset_float (MonoCompile *cfg, int spillvar)
1025 MonoSpillInfo **si, *info;
1028 si = &cfg->spill_info_float;
1030 while (i <= spillvar) {
1033 *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
1035 cfg->stack_offset -= sizeof (double);
1036 info->offset = cfg->stack_offset;
1040 return (*si)->offset;
1046 g_assert_not_reached ();
1051 * Creates a store for spilled floating point items
1054 create_spilled_store_float (MonoCompile *cfg, int spill, int reg, MonoInst *ins)
1057 MONO_INST_NEW (cfg, store, OP_STORER8_MEMBASE_REG);
1059 store->inst_destbasereg = X86_EBP;
1060 store->inst_offset = mono_spillvar_offset_float (cfg, spill);
1062 DEBUG (g_print ("SPILLED FLOAT STORE (%d at 0x%08x(%%sp)) (from %d)\n", spill, store->inst_offset, reg));
1067 * Creates a load for spilled floating point items
1070 create_spilled_load_float (MonoCompile *cfg, int spill, int reg, MonoInst *ins)
1073 MONO_INST_NEW (cfg, load, OP_LOADR8_SPILL_MEMBASE);
1075 load->inst_basereg = X86_EBP;
1076 load->inst_offset = mono_spillvar_offset_float (cfg, spill);
1078 DEBUG (g_print ("SPILLED FLOAT LOAD (%d at 0x%08x(%%sp)) (from %d)\n", spill, load->inst_offset, reg));
1082 #define reg_is_freeable(r) ((r) >= 0 && (r) <= 7 && X86_IS_CALLEE ((r)))
1089 int flags; /* used to track fp spill/load */
1092 static const char*const * ins_spec = pentium_desc;
1095 print_ins (int i, MonoInst *ins)
1097 const char *spec = ins_spec [ins->opcode];
1098 g_print ("\t%-2d %s", i, mono_inst_name (ins->opcode));
1099 if (spec [MONO_INST_DEST]) {
1100 if (ins->dreg >= MONO_MAX_IREGS)
1101 g_print (" R%d <-", ins->dreg);
1103 g_print (" %s <-", mono_arch_regname (ins->dreg));
1105 if (spec [MONO_INST_SRC1]) {
1106 if (ins->sreg1 >= MONO_MAX_IREGS)
1107 g_print (" R%d", ins->sreg1);
1109 g_print (" %s", mono_arch_regname (ins->sreg1));
1111 if (spec [MONO_INST_SRC2]) {
1112 if (ins->sreg2 >= MONO_MAX_IREGS)
1113 g_print (" R%d", ins->sreg2);
1115 g_print (" %s", mono_arch_regname (ins->sreg2));
1117 if (spec [MONO_INST_CLOB])
1118 g_print (" clobbers: %c", spec [MONO_INST_CLOB]);
1123 print_regtrack (RegTrack *t, int num)
1129 for (i = 0; i < num; ++i) {
1132 if (i >= MONO_MAX_IREGS) {
1133 g_snprintf (buf, sizeof(buf), "R%d", i);
1136 r = mono_arch_regname (i);
1137 g_print ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].last_use);
1141 typedef struct InstList InstList;
1149 static inline InstList*
1150 inst_list_prepend (MonoMemPool *pool, InstList *list, MonoInst *data)
1152 InstList *item = mono_mempool_alloc (pool, sizeof (InstList));
1162 * Force the spilling of the variable in the symbolic register 'reg'.
1165 get_register_force_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, int reg)
1170 sel = cfg->rs->iassign [reg];
1171 /*i = cfg->rs->isymbolic [sel];
1172 g_assert (i == reg);*/
1174 spill = ++cfg->spill_count;
1175 cfg->rs->iassign [i] = -spill - 1;
1176 mono_regstate_free_int (cfg->rs, sel);
1177 /* we need to create a spill var and insert a load to sel after the current instruction */
1178 MONO_INST_NEW (cfg, load, OP_LOAD_MEMBASE);
1180 load->inst_basereg = X86_EBP;
1181 load->inst_offset = mono_spillvar_offset (cfg, spill);
1183 while (ins->next != item->prev->data)
1186 load->next = ins->next;
1188 DEBUG (g_print ("SPILLED LOAD (%d at 0x%08x(%%ebp)) R%d (freed %s)\n", spill, load->inst_offset, i, mono_arch_regname (sel)));
1189 i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
1190 g_assert (i == sel);
1196 get_register_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, guint32 regmask, int reg)
1201 DEBUG (g_print ("\tstart regmask to assign R%d: 0x%08x (R%d <- R%d R%d)\n", reg, regmask, ins->dreg, ins->sreg1, ins->sreg2));
1202 /* exclude the registers in the current instruction */
1203 if (reg != ins->sreg1 && (reg_is_freeable (ins->sreg1) || (ins->sreg1 >= MONO_MAX_IREGS && cfg->rs->iassign [ins->sreg1] >= 0))) {
1204 if (ins->sreg1 >= MONO_MAX_IREGS)
1205 regmask &= ~ (1 << cfg->rs->iassign [ins->sreg1]);
1207 regmask &= ~ (1 << ins->sreg1);
1208 DEBUG (g_print ("\t\texcluding sreg1 %s\n", mono_arch_regname (ins->sreg1)));
1210 if (reg != ins->sreg2 && (reg_is_freeable (ins->sreg2) || (ins->sreg2 >= MONO_MAX_IREGS && cfg->rs->iassign [ins->sreg2] >= 0))) {
1211 if (ins->sreg2 >= MONO_MAX_IREGS)
1212 regmask &= ~ (1 << cfg->rs->iassign [ins->sreg2]);
1214 regmask &= ~ (1 << ins->sreg2);
1215 DEBUG (g_print ("\t\texcluding sreg2 %s %d\n", mono_arch_regname (ins->sreg2), ins->sreg2));
1217 if (reg != ins->dreg && reg_is_freeable (ins->dreg)) {
1218 regmask &= ~ (1 << ins->dreg);
1219 DEBUG (g_print ("\t\texcluding dreg %s\n", mono_arch_regname (ins->dreg)));
1222 DEBUG (g_print ("\t\tavailable regmask: 0x%08x\n", regmask));
1223 g_assert (regmask); /* need at least a register we can free */
1225 /* we should track prev_use and spill the register that's farther */
1226 for (i = 0; i < MONO_MAX_IREGS; ++i) {
1227 if (regmask & (1 << i)) {
1229 DEBUG (g_print ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), cfg->rs->iassign [sel]));
1233 i = cfg->rs->isymbolic [sel];
1234 spill = ++cfg->spill_count;
1235 cfg->rs->iassign [i] = -spill - 1;
1236 mono_regstate_free_int (cfg->rs, sel);
1237 /* we need to create a spill var and insert a load to sel after the current instruction */
1238 MONO_INST_NEW (cfg, load, OP_LOAD_MEMBASE);
1240 load->inst_basereg = X86_EBP;
1241 load->inst_offset = mono_spillvar_offset (cfg, spill);
1243 while (ins->next != item->prev->data)
1246 load->next = ins->next;
1248 DEBUG (g_print ("\tSPILLED LOAD (%d at 0x%08x(%%ebp)) R%d (freed %s)\n", spill, load->inst_offset, i, mono_arch_regname (sel)));
1249 i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
1250 g_assert (i == sel);
1256 create_copy_ins (MonoCompile *cfg, int dest, int src, MonoInst *ins)
1259 MONO_INST_NEW (cfg, copy, OP_MOVE);
1263 copy->next = ins->next;
1266 DEBUG (g_print ("\tforced copy from %s to %s\n", mono_arch_regname (src), mono_arch_regname (dest)));
1271 create_spilled_store (MonoCompile *cfg, int spill, int reg, int prev_reg, MonoInst *ins)
1274 MONO_INST_NEW (cfg, store, OP_STORE_MEMBASE_REG);
1276 store->inst_destbasereg = X86_EBP;
1277 store->inst_offset = mono_spillvar_offset (cfg, spill);
1279 store->next = ins->next;
1282 DEBUG (g_print ("\tSPILLED STORE (%d at 0x%08x(%%ebp)) R%d (from %s)\n", spill, store->inst_offset, prev_reg, mono_arch_regname (reg)));
1287 insert_before_ins (MonoInst *ins, InstList *item, MonoInst* to_insert)
1291 prev = item->next->data;
1293 while (prev->next != ins)
1295 to_insert->next = ins;
1296 prev->next = to_insert;
1298 to_insert->next = ins;
1301 * needed otherwise in the next instruction we can add an ins to the
1302 * end and that would get past this instruction.
1304 item->data = to_insert;
1310 alloc_int_reg (MonoCompile *cfg, InstList *curinst, MonoInst *ins, int sym_reg, guint32 allow_mask)
1312 int val = cfg->rs->iassign [sym_reg];
1316 /* the register gets spilled after this inst */
1319 val = mono_regstate_alloc_int (cfg->rs, allow_mask);
1321 val = get_register_spilling (cfg, curinst, ins, allow_mask, sym_reg);
1322 cfg->rs->iassign [sym_reg] = val;
1323 /* add option to store before the instruction for src registers */
1325 create_spilled_store (cfg, spill, val, sym_reg, ins);
1327 cfg->rs->isymbolic [val] = sym_reg;
1332 /* flags used in reginfo->flags */
1334 MONO_X86_FP_NEEDS_LOAD_SPILL = 1 << 0,
1335 MONO_X86_FP_NEEDS_SPILL = 1 << 1,
1336 MONO_X86_FP_NEEDS_LOAD = 1 << 2,
1337 MONO_X86_REG_NOT_ECX = 1 << 3,
1338 MONO_X86_REG_EAX = 1 << 4,
1339 MONO_X86_REG_EDX = 1 << 5,
1340 MONO_X86_REG_ECX = 1 << 6
1344 mono_x86_alloc_int_reg (MonoCompile *cfg, InstList *tmp, MonoInst *ins, guint32 dest_mask, int sym_reg, int flags)
1347 int test_mask = dest_mask;
1349 if (flags & MONO_X86_REG_EAX)
1350 test_mask &= (1 << X86_EAX);
1351 else if (flags & MONO_X86_REG_EDX)
1352 test_mask &= (1 << X86_EDX);
1353 else if (flags & MONO_X86_REG_ECX)
1354 test_mask &= (1 << X86_ECX);
1355 else if (flags & MONO_X86_REG_NOT_ECX)
1356 test_mask &= ~ (1 << X86_ECX);
1358 val = mono_regstate_alloc_int (cfg->rs, test_mask);
1359 if (val >= 0 && test_mask != dest_mask)
1360 DEBUG(g_print ("\tUsed flag to allocate reg %s for R%u\n", mono_arch_regname (val), sym_reg));
1362 if (val < 0 && (flags & MONO_X86_REG_NOT_ECX)) {
1363 DEBUG(g_print ("\tFailed to allocate flag suggested mask (%u) but exluding ECX\n", test_mask));
1364 val = mono_regstate_alloc_int (cfg->rs, (dest_mask & (~1 << X86_ECX)));
1368 val = mono_regstate_alloc_int (cfg->rs, dest_mask);
1370 val = get_register_spilling (cfg, tmp, ins, dest_mask, sym_reg);
1377 /*#include "cprop.c"*/
1380 * Local register allocation.
1381 * We first scan the list of instructions and we save the liveness info of
1382 * each register (when the register is first used, when it's value is set etc.).
1383 * We also reverse the list of instructions (in the InstList list) because assigning
1384 * registers backwards allows for more tricks to be used.
1387 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1390 MonoRegState *rs = cfg->rs;
1391 int i, val, fpcount;
1392 RegTrack *reginfo, *reginfof;
1393 RegTrack *reginfo1, *reginfo2, *reginfod;
1394 InstList *tmp, *reversed = NULL;
1396 guint32 src1_mask, src2_mask, dest_mask;
1397 GList *fspill_list = NULL;
1402 rs->next_vireg = bb->max_ireg;
1403 rs->next_vfreg = bb->max_freg;
1404 mono_regstate_assign (rs);
1405 reginfo = g_malloc0 (sizeof (RegTrack) * rs->next_vireg);
1406 reginfof = g_malloc0 (sizeof (RegTrack) * rs->next_vfreg);
1407 rs->ifree_mask = X86_CALLEE_REGS;
1411 /*if (cfg->opt & MONO_OPT_COPYPROP)
1412 local_copy_prop (cfg, ins);*/
1416 DEBUG (g_print ("LOCAL regalloc: basic block: %d\n", bb->block_num));
1417 /* forward pass on the instructions to collect register liveness info */
1419 spec = ins_spec [ins->opcode];
1421 DEBUG (print_ins (i, ins));
1423 if (spec [MONO_INST_SRC1]) {
1424 if (spec [MONO_INST_SRC1] == 'f') {
1426 reginfo1 = reginfof;
1428 spill = g_list_first (fspill_list);
1429 if (spill && fpcount < MONO_MAX_FREGS) {
1430 reginfo1 [ins->sreg1].flags |= MONO_X86_FP_NEEDS_LOAD;
1431 fspill_list = g_list_remove (fspill_list, spill->data);
1437 reginfo1 [ins->sreg1].prev_use = reginfo1 [ins->sreg1].last_use;
1438 reginfo1 [ins->sreg1].last_use = i;
1439 if (spec [MONO_INST_SRC1] == 'L') {
1440 /* The virtual register is allocated sequentially */
1441 reginfo1 [ins->sreg1 + 1].prev_use = reginfo1 [ins->sreg1 + 1].last_use;
1442 reginfo1 [ins->sreg1 + 1].last_use = i;
1443 if (reginfo1 [ins->sreg1 + 1].born_in == 0 || reginfo1 [ins->sreg1 + 1].born_in > i)
1444 reginfo1 [ins->sreg1 + 1].born_in = i;
1446 reginfo1 [ins->sreg1].flags |= MONO_X86_REG_EAX;
1447 reginfo1 [ins->sreg1 + 1].flags |= MONO_X86_REG_EDX;
1452 if (spec [MONO_INST_SRC2]) {
1453 if (spec [MONO_INST_SRC2] == 'f') {
1455 reginfo2 = reginfof;
1456 spill = g_list_first (fspill_list);
1458 reginfo2 [ins->sreg2].flags |= MONO_X86_FP_NEEDS_LOAD;
1459 fspill_list = g_list_remove (fspill_list, spill->data);
1460 if (fpcount >= MONO_MAX_FREGS) {
1462 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1463 reginfo2 [ins->sreg2].flags |= MONO_X86_FP_NEEDS_LOAD_SPILL;
1470 reginfo2 [ins->sreg2].prev_use = reginfo2 [ins->sreg2].last_use;
1471 reginfo2 [ins->sreg2].last_use = i;
1472 if (spec [MONO_INST_SRC2] == 'L') {
1473 /* The virtual register is allocated sequentially */
1474 reginfo2 [ins->sreg2 + 1].prev_use = reginfo2 [ins->sreg2 + 1].last_use;
1475 reginfo2 [ins->sreg2 + 1].last_use = i;
1476 if (reginfo2 [ins->sreg2 + 1].born_in == 0 || reginfo2 [ins->sreg2 + 1].born_in > i)
1477 reginfo2 [ins->sreg2 + 1].born_in = i;
1479 if (spec [MONO_INST_CLOB] == 's') {
1480 reginfo2 [ins->sreg1].flags |= MONO_X86_REG_NOT_ECX;
1481 reginfo2 [ins->sreg2].flags |= MONO_X86_REG_ECX;
1486 if (spec [MONO_INST_DEST]) {
1487 if (spec [MONO_INST_DEST] == 'f') {
1488 reginfod = reginfof;
1489 if (fpcount >= MONO_MAX_FREGS) {
1490 reginfod [ins->dreg].flags |= MONO_X86_FP_NEEDS_SPILL;
1492 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1499 if (spec [MONO_INST_DEST] != 'b') /* it's not just a base register */
1500 reginfod [ins->dreg].killed_in = i;
1501 reginfod [ins->dreg].prev_use = reginfod [ins->dreg].last_use;
1502 reginfod [ins->dreg].last_use = i;
1503 if (reginfod [ins->dreg].born_in == 0 || reginfod [ins->dreg].born_in > i)
1504 reginfod [ins->dreg].born_in = i;
1505 if (spec [MONO_INST_DEST] == 'l' || spec [MONO_INST_DEST] == 'L') {
1506 /* The virtual register is allocated sequentially */
1507 reginfod [ins->dreg + 1].prev_use = reginfod [ins->dreg + 1].last_use;
1508 reginfod [ins->dreg + 1].last_use = i;
1509 if (reginfod [ins->dreg + 1].born_in == 0 || reginfod [ins->dreg + 1].born_in > i)
1510 reginfod [ins->dreg + 1].born_in = i;
1512 reginfod [ins->dreg].flags |= MONO_X86_REG_EAX;
1513 reginfod [ins->dreg + 1].flags |= MONO_X86_REG_EDX;
1519 reversed = inst_list_prepend (cfg->mempool, reversed, ins);
1524 // todo: check if we have anything left on fp stack, in verify mode?
1527 DEBUG (print_regtrack (reginfo, rs->next_vireg));
1528 DEBUG (print_regtrack (reginfof, rs->next_vfreg));
1531 int prev_dreg, prev_sreg1, prev_sreg2, clob_dreg;
1532 dest_mask = src1_mask = src2_mask = X86_CALLEE_REGS;
1535 spec = ins_spec [ins->opcode];
1538 DEBUG (g_print ("processing:"));
1539 DEBUG (print_ins (i, ins));
1540 if (spec [MONO_INST_CLOB] == 's') {
1541 if (rs->ifree_mask & (1 << X86_ECX)) {
1542 DEBUG (g_print ("\tshortcut assignment of R%d to ECX\n", ins->sreg2));
1543 rs->iassign [ins->sreg2] = X86_ECX;
1544 rs->isymbolic [X86_ECX] = ins->sreg2;
1545 ins->sreg2 = X86_ECX;
1546 rs->ifree_mask &= ~ (1 << X86_ECX);
1548 int need_ecx_spill = TRUE;
1550 * we first check if src1/dreg is already assigned a register
1551 * and then we force a spill of the var assigned to ECX.
1553 /* the destination register can't be ECX */
1554 dest_mask &= ~ (1 << X86_ECX);
1555 src1_mask &= ~ (1 << X86_ECX);
1556 val = rs->iassign [ins->dreg];
1558 * the destination register is already assigned to ECX:
1559 * we need to allocate another register for it and then
1560 * copy from this to ECX.
1562 if (val == X86_ECX && ins->dreg != ins->sreg2) {
1564 new_dest = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, ins->dreg, reginfo [ins->dreg].flags);
1565 g_assert (new_dest >= 0);
1566 DEBUG (g_print ("\tclob:s changing dreg R%d to %s from ECX\n", ins->dreg, mono_arch_regname (new_dest)));
1568 rs->isymbolic [new_dest] = ins->dreg;
1569 rs->iassign [ins->dreg] = new_dest;
1570 clob_dreg = ins->dreg;
1571 ins->dreg = new_dest;
1572 create_copy_ins (cfg, X86_ECX, new_dest, ins);
1573 need_ecx_spill = FALSE;
1574 /*DEBUG (g_print ("\tforced spill of R%d\n", ins->dreg));
1575 val = get_register_force_spilling (cfg, tmp, ins, ins->dreg);
1576 rs->iassign [ins->dreg] = val;
1577 rs->isymbolic [val] = prev_dreg;
1580 val = rs->iassign [ins->sreg1];
1581 if (val == X86_ECX) {
1582 g_assert_not_reached ();
1583 } else if (val >= 0) {
1585 * the first src reg was already assigned to a register,
1586 * we need to copy it to the dest register because the
1587 * shift instruction clobbers the first operand.
1589 MonoInst *copy = create_copy_ins (cfg, ins->dreg, val, NULL);
1590 DEBUG (g_print ("\tclob:s moved sreg1 from R%d to R%d\n", val, ins->dreg));
1591 insert_before_ins (ins, tmp, copy);
1593 val = rs->iassign [ins->sreg2];
1594 if (val >= 0 && val != X86_ECX) {
1595 MonoInst *move = create_copy_ins (cfg, X86_ECX, val, NULL);
1596 DEBUG (g_print ("\tmoved arg from R%d (%d) to ECX\n", val, ins->sreg2));
1598 g_assert_not_reached ();
1599 /* FIXME: where is move connected to the instruction list? */
1600 //tmp->prev->data->next = move;
1602 if (need_ecx_spill && !(rs->ifree_mask & (1 << X86_ECX))) {
1603 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [X86_ECX]));
1604 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_ECX]);
1605 mono_regstate_free_int (rs, X86_ECX);
1607 /* force-set sreg2 */
1608 rs->iassign [ins->sreg2] = X86_ECX;
1609 rs->isymbolic [X86_ECX] = ins->sreg2;
1610 ins->sreg2 = X86_ECX;
1611 rs->ifree_mask &= ~ (1 << X86_ECX);
1613 } else if (spec [MONO_INST_CLOB] == 'd') { /* division */
1614 int dest_reg = X86_EAX;
1615 int clob_reg = X86_EDX;
1616 if (spec [MONO_INST_DEST] == 'd') {
1617 dest_reg = X86_EDX; /* reminder */
1620 val = rs->iassign [ins->dreg];
1621 if (0 && val >= 0 && val != dest_reg && !(rs->ifree_mask & (1 << dest_reg))) {
1622 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [dest_reg]));
1623 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [dest_reg]);
1624 mono_regstate_free_int (rs, dest_reg);
1628 /* the register gets spilled after this inst */
1629 int spill = -val -1;
1630 dest_mask = 1 << clob_reg;
1631 prev_dreg = ins->dreg;
1632 val = mono_regstate_alloc_int (rs, dest_mask);
1634 val = get_register_spilling (cfg, tmp, ins, dest_mask, ins->dreg);
1635 rs->iassign [ins->dreg] = val;
1637 create_spilled_store (cfg, spill, val, prev_dreg, ins);
1638 DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_arch_regname (val), ins->dreg));
1639 rs->isymbolic [val] = prev_dreg;
1641 if (val != dest_reg) { /* force a copy */
1642 create_copy_ins (cfg, val, dest_reg, ins);
1645 DEBUG (g_print ("\tshortcut assignment of R%d to %s\n", ins->dreg, mono_arch_regname (dest_reg)));
1646 prev_dreg = ins->dreg;
1647 rs->iassign [ins->dreg] = dest_reg;
1648 rs->isymbolic [dest_reg] = ins->dreg;
1649 ins->dreg = dest_reg;
1650 rs->ifree_mask &= ~ (1 << dest_reg);
1653 //DEBUG (g_print ("dest reg in div assigned: %s\n", mono_arch_regname (val)));
1654 if (val != dest_reg) { /* force a copy */
1655 create_copy_ins (cfg, val, dest_reg, ins);
1656 if (!(rs->ifree_mask & (1 << dest_reg)) && rs->isymbolic [dest_reg] >= MONO_MAX_IREGS) {
1657 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [dest_reg]));
1658 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [dest_reg]);
1659 mono_regstate_free_int (rs, dest_reg);
1663 if (!(rs->ifree_mask & (1 << clob_reg)) && (clob_reg != val) && (rs->isymbolic [clob_reg] >= 8)) {
1664 DEBUG (g_print ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
1665 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [clob_reg]);
1666 mono_regstate_free_int (rs, clob_reg);
1668 src1_mask = 1 << X86_EAX;
1669 src2_mask = 1 << X86_ECX;
1671 if (spec [MONO_INST_DEST] == 'l') {
1673 val = rs->iassign [ins->dreg];
1674 /* check special case when dreg have been moved from ecx (clob shift) */
1675 if (spec [MONO_INST_CLOB] == 's' && clob_dreg != -1)
1676 hreg = clob_dreg + 1;
1678 hreg = ins->dreg + 1;
1680 /* base prev_dreg on fixed hreg, handle clob case */
1683 if (val != rs->isymbolic [X86_EAX] && !(rs->ifree_mask & (1 << X86_EAX))) {
1684 DEBUG (g_print ("\t(long-low) forced spill of R%d\n", rs->isymbolic [X86_EAX]));
1685 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_EAX]);
1686 mono_regstate_free_int (rs, X86_EAX);
1688 if (hreg != rs->isymbolic [X86_EDX] && !(rs->ifree_mask & (1 << X86_EDX))) {
1689 DEBUG (g_print ("\t(long-high) forced spill of R%d\n", rs->isymbolic [X86_EDX]));
1690 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_EDX]);
1691 mono_regstate_free_int (rs, X86_EDX);
1696 if (spec [MONO_INST_DEST] == 'f') {
1697 if (reginfof [ins->dreg].flags & MONO_X86_FP_NEEDS_SPILL) {
1700 spill_node = g_list_first (fspill_list);
1701 g_assert (spill_node);
1703 store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->dreg, ins);
1704 insert_before_ins (ins, tmp, store);
1705 fspill_list = g_list_remove (fspill_list, spill_node->data);
1708 } else if (spec [MONO_INST_DEST] == 'L') {
1710 val = rs->iassign [ins->dreg];
1711 /* check special case when dreg have been moved from ecx (clob shift) */
1712 if (spec [MONO_INST_CLOB] == 's' && clob_dreg != -1)
1713 hreg = clob_dreg + 1;
1715 hreg = ins->dreg + 1;
1717 /* base prev_dreg on fixed hreg, handle clob case */
1718 prev_dreg = hreg - 1;
1723 /* the register gets spilled after this inst */
1726 val = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, ins->dreg, reginfo [ins->dreg].flags);
1727 rs->iassign [ins->dreg] = val;
1729 create_spilled_store (cfg, spill, val, prev_dreg, ins);
1732 DEBUG (g_print ("\tassigned dreg (long) %s to dest R%d\n", mono_arch_regname (val), hreg - 1));
1734 rs->isymbolic [val] = hreg - 1;
1737 val = rs->iassign [hreg];
1741 /* the register gets spilled after this inst */
1744 val = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, hreg, reginfo [hreg].flags);
1745 rs->iassign [hreg] = val;
1747 create_spilled_store (cfg, spill, val, hreg, ins);
1750 DEBUG (g_print ("\tassigned hreg (long-high) %s to dest R%d\n", mono_arch_regname (val), hreg));
1751 rs->isymbolic [val] = hreg;
1752 /* save reg allocating into unused */
1755 /* check if we can free our long reg */
1756 if (reg_is_freeable (val) && hreg >= 0 && reginfo [hreg].born_in >= i) {
1757 DEBUG (g_print ("\tfreeable %s (R%d) (born in %d)\n", mono_arch_regname (val), hreg, reginfo [hreg].born_in));
1758 mono_regstate_free_int (rs, val);
1761 else if (ins->dreg >= MONO_MAX_IREGS) {
1763 val = rs->iassign [ins->dreg];
1764 if (spec [MONO_INST_DEST] == 'l') {
1765 /* check special case when dreg have been moved from ecx (clob shift) */
1766 if (spec [MONO_INST_CLOB] == 's' && clob_dreg != -1)
1767 hreg = clob_dreg + 1;
1769 hreg = ins->dreg + 1;
1771 /* base prev_dreg on fixed hreg, handle clob case */
1772 prev_dreg = hreg - 1;
1774 prev_dreg = ins->dreg;
1779 /* the register gets spilled after this inst */
1782 val = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, ins->dreg, reginfo [ins->dreg].flags);
1783 rs->iassign [ins->dreg] = val;
1785 create_spilled_store (cfg, spill, val, prev_dreg, ins);
1787 DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_arch_regname (val), ins->dreg));
1788 rs->isymbolic [val] = prev_dreg;
1790 /* handle cases where lreg needs to be eax:edx */
1791 if (spec [MONO_INST_DEST] == 'l') {
1792 /* check special case when dreg have been moved from ecx (clob shift) */
1793 int hreg = prev_dreg + 1;
1794 val = rs->iassign [hreg];
1798 /* the register gets spilled after this inst */
1801 val = mono_x86_alloc_int_reg (cfg, tmp, ins, dest_mask, hreg, reginfo [hreg].flags);
1802 rs->iassign [hreg] = val;
1804 create_spilled_store (cfg, spill, val, hreg, ins);
1806 DEBUG (g_print ("\tassigned hreg %s to dest R%d\n", mono_arch_regname (val), hreg));
1807 rs->isymbolic [val] = hreg;
1808 if (ins->dreg == X86_EAX) {
1810 create_copy_ins (cfg, val, X86_EDX, ins);
1811 } else if (ins->dreg == X86_EDX) {
1812 if (val == X86_EAX) {
1814 g_assert_not_reached ();
1816 /* two forced copies */
1817 create_copy_ins (cfg, val, X86_EDX, ins);
1818 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1821 if (val == X86_EDX) {
1822 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1824 /* two forced copies */
1825 create_copy_ins (cfg, val, X86_EDX, ins);
1826 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1829 if (reg_is_freeable (val) && hreg >= 0 && reginfo [hreg].born_in >= i) {
1830 DEBUG (g_print ("\tfreeable %s (R%d)\n", mono_arch_regname (val), hreg));
1831 mono_regstate_free_int (rs, val);
1833 } else if (spec [MONO_INST_DEST] == 'a' && ins->dreg != X86_EAX && spec [MONO_INST_CLOB] != 'd') {
1834 /* this instruction only outputs to EAX, need to copy */
1835 create_copy_ins (cfg, ins->dreg, X86_EAX, ins);
1836 } else if (spec [MONO_INST_DEST] == 'd' && ins->dreg != X86_EDX && spec [MONO_INST_CLOB] != 'd') {
1837 create_copy_ins (cfg, ins->dreg, X86_EDX, ins);
1840 if (spec [MONO_INST_DEST] != 'f' && reg_is_freeable (ins->dreg) && prev_dreg >= 0 && reginfo [prev_dreg].born_in >= i) {
1841 DEBUG (g_print ("\tfreeable %s (R%d) (born in %d)\n", mono_arch_regname (ins->dreg), prev_dreg, reginfo [prev_dreg].born_in));
1842 mono_regstate_free_int (rs, ins->dreg);
1844 /* put src1 in EAX if it needs to be */
1845 if (spec [MONO_INST_SRC1] == 'a') {
1846 if (!(rs->ifree_mask & (1 << X86_EAX))) {
1847 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [X86_EAX]));
1848 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [X86_EAX]);
1849 mono_regstate_free_int (rs, X86_EAX);
1851 /* force-set sreg1 */
1852 rs->iassign [ins->sreg1] = X86_EAX;
1853 rs->isymbolic [X86_EAX] = ins->sreg1;
1854 ins->sreg1 = X86_EAX;
1855 rs->ifree_mask &= ~ (1 << X86_EAX);
1859 if (spec [MONO_INST_SRC1] == 'f') {
1860 if (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD) {
1862 MonoInst *store = NULL;
1864 if (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD_SPILL) {
1866 spill_node = g_list_first (fspill_list);
1867 g_assert (spill_node);
1869 store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->sreg1, ins);
1870 fspill_list = g_list_remove (fspill_list, spill_node->data);
1874 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1875 load = create_spilled_load_float (cfg, fspill, ins->sreg1, ins);
1876 insert_before_ins (ins, tmp, load);
1878 insert_before_ins (load, tmp, store);
1880 } else if ((spec [MONO_INST_DEST] == 'L') && (spec [MONO_INST_SRC1] == 'L')) {
1881 /* force source to be same as dest */
1882 rs->iassign [ins->sreg1] = ins->dreg;
1883 rs->iassign [ins->sreg1 + 1] = ins->unused;
1884 rs->isymbolic [ins->dreg] = ins->sreg1;
1885 rs->isymbolic [ins->unused] = ins->sreg1 + 1;
1887 DEBUG (g_print ("\tassigned sreg1 (long) %s to sreg1 R%d\n", mono_arch_regname (ins->dreg), ins->sreg1));
1888 DEBUG (g_print ("\tassigned sreg1 (long-high) %s to sreg1 R%d\n", mono_arch_regname (ins->unused), ins->sreg1 + 1));
1890 ins->sreg1 = ins->dreg;
1892 * No need for saving the reg, we know that src1=dest in this cases
1893 * ins->inst_c0 = ins->unused;
1896 /* make sure that we remove them from free mask */
1897 rs->ifree_mask &= ~ (1 << ins->dreg);
1898 rs->ifree_mask &= ~ (1 << ins->unused);
1900 else if (ins->sreg1 >= MONO_MAX_IREGS) {
1901 val = rs->iassign [ins->sreg1];
1902 prev_sreg1 = ins->sreg1;
1906 /* the register gets spilled after this inst */
1909 if (0 && ins->opcode == OP_MOVE) {
1911 * small optimization: the dest register is already allocated
1912 * but the src one is not: we can simply assign the same register
1913 * here and peephole will get rid of the instruction later.
1914 * This optimization may interfere with the clobbering handling:
1915 * it removes a mov operation that will be added again to handle clobbering.
1916 * There are also some other issues that should with make testjit.
1918 mono_regstate_alloc_int (rs, 1 << ins->dreg);
1919 val = rs->iassign [ins->sreg1] = ins->dreg;
1920 //g_assert (val >= 0);
1921 DEBUG (g_print ("\tfast assigned sreg1 %s to R%d\n", mono_arch_regname (val), ins->sreg1));
1923 //g_assert (val == -1); /* source cannot be spilled */
1924 val = mono_x86_alloc_int_reg (cfg, tmp, ins, src1_mask, ins->sreg1, reginfo [ins->sreg1].flags);
1925 rs->iassign [ins->sreg1] = val;
1926 DEBUG (g_print ("\tassigned sreg1 %s to R%d\n", mono_arch_regname (val), ins->sreg1));
1929 MonoInst *store = create_spilled_store (cfg, spill, val, prev_sreg1, NULL);
1930 insert_before_ins (ins, tmp, store);
1933 rs->isymbolic [val] = prev_sreg1;
1938 /* handle clobbering of sreg1 */
1939 if ((spec [MONO_INST_CLOB] == '1' || spec [MONO_INST_CLOB] == 's') && ins->dreg != ins->sreg1) {
1940 MonoInst *copy = create_copy_ins (cfg, ins->dreg, ins->sreg1, NULL);
1941 DEBUG (g_print ("\tneed to copy sreg1 %s to dreg %s\n", mono_arch_regname (ins->sreg1), mono_arch_regname (ins->dreg)));
1942 if (ins->sreg2 == -1 || spec [MONO_INST_CLOB] == 's') {
1943 /* note: the copy is inserted before the current instruction! */
1944 insert_before_ins (ins, tmp, copy);
1945 /* we set sreg1 to dest as well */
1946 prev_sreg1 = ins->sreg1 = ins->dreg;
1948 /* inserted after the operation */
1949 copy->next = ins->next;
1954 if (spec [MONO_INST_SRC2] == 'f') {
1955 if (reginfof [ins->sreg2].flags & MONO_X86_FP_NEEDS_LOAD) {
1957 MonoInst *store = NULL;
1959 if (reginfof [ins->sreg2].flags & MONO_X86_FP_NEEDS_LOAD_SPILL) {
1962 spill_node = g_list_first (fspill_list);
1963 g_assert (spill_node);
1964 if (spec [MONO_INST_SRC1] == 'f' && (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD_SPILL))
1965 spill_node = g_list_next (spill_node);
1967 store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->sreg2, ins);
1968 fspill_list = g_list_remove (fspill_list, spill_node->data);
1972 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
1973 load = create_spilled_load_float (cfg, fspill, ins->sreg2, ins);
1974 insert_before_ins (ins, tmp, load);
1976 insert_before_ins (load, tmp, store);
1979 else if (ins->sreg2 >= MONO_MAX_IREGS) {
1980 val = rs->iassign [ins->sreg2];
1981 prev_sreg2 = ins->sreg2;
1985 /* the register gets spilled after this inst */
1988 val = mono_x86_alloc_int_reg (cfg, tmp, ins, src2_mask, ins->sreg2, reginfo [ins->sreg2].flags);
1989 rs->iassign [ins->sreg2] = val;
1990 DEBUG (g_print ("\tassigned sreg2 %s to R%d\n", mono_arch_regname (val), ins->sreg2));
1992 create_spilled_store (cfg, spill, val, prev_sreg2, ins);
1994 rs->isymbolic [val] = prev_sreg2;
1996 if (spec [MONO_INST_CLOB] == 's' && ins->sreg2 != X86_ECX) {
1997 DEBUG (g_print ("\tassigned sreg2 %s to R%d, but ECX is needed (R%d)\n", mono_arch_regname (val), ins->sreg2, rs->iassign [X86_ECX]));
2003 if (spec [MONO_INST_CLOB] == 'c') {
2005 guint32 clob_mask = X86_CALLEE_REGS;
2006 for (j = 0; j < MONO_MAX_IREGS; ++j) {
2008 if ((clob_mask & s) && !(rs->ifree_mask & s) && j != ins->sreg1) {
2009 //g_warning ("register %s busy at call site\n", mono_arch_regname (j));
2013 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2014 DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2015 mono_regstate_free_int (rs, ins->sreg1);
2017 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2018 DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2019 mono_regstate_free_int (rs, ins->sreg2);
2022 //DEBUG (print_ins (i, ins));
2023 /* this may result from a insert_before call */
2025 bb->code = tmp->data;
2031 g_list_free (fspill_list);
2034 static unsigned char*
2035 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2037 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2038 x86_fnstcw_membase(code, X86_ESP, 0);
2039 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2040 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2041 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2042 x86_fldcw_membase (code, X86_ESP, 2);
2044 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2045 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2046 x86_pop_reg (code, dreg);
2047 /* FIXME: need the high register
2048 * x86_pop_reg (code, dreg_high);
2051 x86_push_reg (code, X86_EAX); // SP = SP - 4
2052 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2053 x86_pop_reg (code, dreg);
2055 x86_fldcw_membase (code, X86_ESP, 0);
2056 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2059 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2061 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2065 static unsigned char*
2066 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2068 int sreg = tree->sreg1;
2069 #ifdef PLATFORM_WIN32
2074 * If requested stack size is larger than one page,
2075 * perform stack-touch operation
2078 * Generate stack probe code.
2079 * Under Windows, it is necessary to allocate one page at a time,
2080 * "touching" stack after each successful sub-allocation. This is
2081 * because of the way stack growth is implemented - there is a
2082 * guard page before the lowest stack page that is currently commited.
2083 * Stack normally grows sequentially so OS traps access to the
2084 * guard page and commits more pages when needed.
2086 x86_test_reg_imm (code, sreg, ~0xFFF);
2087 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2089 br[2] = code; /* loop */
2090 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2091 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2092 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2093 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2094 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2095 x86_patch (br[3], br[2]);
2096 x86_test_reg_reg (code, sreg, sreg);
2097 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2098 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2100 br[1] = code; x86_jump8 (code, 0);
2102 x86_patch (br[0], code);
2103 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2104 x86_patch (br[1], code);
2105 x86_patch (br[4], code);
2106 #else /* PLATFORM_WIN32 */
2107 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2109 if (tree->flags & MONO_INST_INIT) {
2111 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2112 x86_push_reg (code, X86_EAX);
2115 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2116 x86_push_reg (code, X86_ECX);
2119 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2120 x86_push_reg (code, X86_EDI);
2124 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2125 if (sreg != X86_ECX)
2126 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2127 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2129 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2131 x86_prefix (code, X86_REP_PREFIX);
2134 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2135 x86_pop_reg (code, X86_EDI);
2136 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2137 x86_pop_reg (code, X86_ECX);
2138 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2139 x86_pop_reg (code, X86_EAX);
2144 #define REAL_PRINT_REG(text,reg) \
2145 mono_assert (reg >= 0); \
2146 x86_push_reg (code, X86_EAX); \
2147 x86_push_reg (code, X86_EDX); \
2148 x86_push_reg (code, X86_ECX); \
2149 x86_push_reg (code, reg); \
2150 x86_push_imm (code, reg); \
2151 x86_push_imm (code, text " %d %p\n"); \
2152 x86_mov_reg_imm (code, X86_EAX, printf); \
2153 x86_call_reg (code, X86_EAX); \
2154 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2155 x86_pop_reg (code, X86_ECX); \
2156 x86_pop_reg (code, X86_EDX); \
2157 x86_pop_reg (code, X86_EAX);
2159 /* benchmark and set based on cpu */
2160 #define LOOP_ALIGNMENT 8
2161 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2164 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2169 guint8 *code = cfg->native_code + cfg->code_len;
2170 MonoInst *last_ins = NULL;
2171 guint last_offset = 0;
2174 if (cfg->opt & MONO_OPT_PEEPHOLE)
2175 peephole_pass (cfg, bb);
2177 if (cfg->opt & MONO_OPT_LOOP) {
2178 int pad, align = LOOP_ALIGNMENT;
2179 /* set alignment depending on cpu */
2180 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2182 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2183 x86_padding (code, pad);
2184 cfg->code_len += pad;
2185 bb->native_offset = cfg->code_len;
2189 if (cfg->verbose_level > 2)
2190 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2192 cpos = bb->max_offset;
2194 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2195 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2196 g_assert (!mono_compile_aot);
2199 cov->data [bb->dfn].cil_code = bb->cil_code;
2200 /* this is not thread save, but good enough */
2201 x86_inc_mem (code, &cov->data [bb->dfn].count);
2204 offset = code - cfg->native_code;
2208 offset = code - cfg->native_code;
2210 max_len = ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
2212 if (offset > (cfg->code_size - max_len - 16)) {
2213 cfg->code_size *= 2;
2214 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2215 code = cfg->native_code + offset;
2216 mono_jit_stats.code_reallocs++;
2219 mono_debug_record_line_number (cfg, ins, offset);
2221 switch (ins->opcode) {
2223 x86_mul_reg (code, ins->sreg2, TRUE);
2226 x86_mul_reg (code, ins->sreg2, FALSE);
2228 case OP_X86_SETEQ_MEMBASE:
2229 case OP_X86_SETNE_MEMBASE:
2230 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2231 ins->inst_basereg, ins->inst_offset, TRUE);
2233 case OP_STOREI1_MEMBASE_IMM:
2234 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2236 case OP_STOREI2_MEMBASE_IMM:
2237 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2239 case OP_STORE_MEMBASE_IMM:
2240 case OP_STOREI4_MEMBASE_IMM:
2241 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2243 case OP_STOREI1_MEMBASE_REG:
2244 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2246 case OP_STOREI2_MEMBASE_REG:
2247 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2249 case OP_STORE_MEMBASE_REG:
2250 case OP_STOREI4_MEMBASE_REG:
2251 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2256 x86_mov_reg_mem (code, ins->dreg, ins->inst_p0, 4);
2259 x86_mov_reg_imm (code, ins->dreg, ins->inst_p0);
2260 x86_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2262 case OP_LOAD_MEMBASE:
2263 case OP_LOADI4_MEMBASE:
2264 case OP_LOADU4_MEMBASE:
2265 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2267 case OP_LOADU1_MEMBASE:
2268 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2270 case OP_LOADI1_MEMBASE:
2271 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2273 case OP_LOADU2_MEMBASE:
2274 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2276 case OP_LOADI2_MEMBASE:
2277 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2280 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2283 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2286 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2289 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2292 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2294 case OP_COMPARE_IMM:
2295 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2297 case OP_X86_COMPARE_MEMBASE_REG:
2298 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2300 case OP_X86_COMPARE_MEMBASE_IMM:
2301 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2303 case OP_X86_COMPARE_MEMBASE8_IMM:
2304 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2306 case OP_X86_COMPARE_REG_MEMBASE:
2307 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2309 case OP_X86_TEST_NULL:
2310 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2312 case OP_X86_ADD_MEMBASE_IMM:
2313 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2315 case OP_X86_ADD_MEMBASE:
2316 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2318 case OP_X86_SUB_MEMBASE_IMM:
2319 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2321 case OP_X86_SUB_MEMBASE:
2322 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2324 case OP_X86_INC_MEMBASE:
2325 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2327 case OP_X86_INC_REG:
2328 x86_inc_reg (code, ins->dreg);
2330 case OP_X86_DEC_MEMBASE:
2331 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2333 case OP_X86_DEC_REG:
2334 x86_dec_reg (code, ins->dreg);
2336 case OP_X86_MUL_MEMBASE:
2337 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2340 x86_breakpoint (code);
2344 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2347 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2351 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2354 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2358 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2361 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2365 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2368 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2371 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2374 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2378 x86_div_reg (code, ins->sreg2, TRUE);
2381 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2382 x86_div_reg (code, ins->sreg2, FALSE);
2385 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2387 x86_div_reg (code, ins->sreg2, TRUE);
2391 x86_div_reg (code, ins->sreg2, TRUE);
2394 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2395 x86_div_reg (code, ins->sreg2, FALSE);
2398 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2400 x86_div_reg (code, ins->sreg2, TRUE);
2403 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2406 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2409 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2412 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2415 g_assert (ins->sreg2 == X86_ECX);
2416 x86_shift_reg (code, X86_SHL, ins->dreg);
2419 g_assert (ins->sreg2 == X86_ECX);
2420 x86_shift_reg (code, X86_SAR, ins->dreg);
2423 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2426 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2429 g_assert (ins->sreg2 == X86_ECX);
2430 x86_shift_reg (code, X86_SHR, ins->dreg);
2433 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2436 guint8 *jump_to_end;
2438 /* handle shifts below 32 bits */
2439 x86_shld_reg (code, ins->unused, ins->sreg1);
2440 x86_shift_reg (code, X86_SHL, ins->sreg1);
2442 x86_test_reg_imm (code, X86_ECX, 32);
2443 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2445 /* handle shift over 32 bit */
2446 x86_mov_reg_reg (code, ins->unused, ins->sreg1, 4);
2447 x86_clear_reg (code, ins->sreg1);
2449 x86_patch (jump_to_end, code);
2453 guint8 *jump_to_end;
2455 /* handle shifts below 32 bits */
2456 x86_shrd_reg (code, ins->sreg1, ins->unused);
2457 x86_shift_reg (code, X86_SAR, ins->unused);
2459 x86_test_reg_imm (code, X86_ECX, 32);
2460 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2462 /* handle shifts over 31 bits */
2463 x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
2464 x86_shift_reg_imm (code, X86_SAR, ins->unused, 31);
2466 x86_patch (jump_to_end, code);
2470 guint8 *jump_to_end;
2472 /* handle shifts below 32 bits */
2473 x86_shrd_reg (code, ins->sreg1, ins->unused);
2474 x86_shift_reg (code, X86_SHR, ins->unused);
2476 x86_test_reg_imm (code, X86_ECX, 32);
2477 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2479 /* handle shifts over 31 bits */
2480 x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
2481 x86_shift_reg_imm (code, X86_SHR, ins->unused, 31);
2483 x86_patch (jump_to_end, code);
2487 if (ins->inst_imm >= 32) {
2488 x86_mov_reg_reg (code, ins->unused, ins->sreg1, 4);
2489 x86_clear_reg (code, ins->sreg1);
2490 x86_shift_reg_imm (code, X86_SHL, ins->unused, ins->inst_imm - 32);
2492 x86_shld_reg_imm (code, ins->unused, ins->sreg1, ins->inst_imm);
2493 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
2497 if (ins->inst_imm >= 32) {
2498 x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
2499 x86_shift_reg_imm (code, X86_SAR, ins->unused, 0x1f);
2500 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
2502 x86_shrd_reg_imm (code, ins->sreg1, ins->unused, ins->inst_imm);
2503 x86_shift_reg_imm (code, X86_SAR, ins->unused, ins->inst_imm);
2506 case OP_LSHR_UN_IMM:
2507 if (ins->inst_imm >= 32) {
2508 x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
2509 x86_clear_reg (code, ins->unused);
2510 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
2512 x86_shrd_reg_imm (code, ins->sreg1, ins->unused, ins->inst_imm);
2513 x86_shift_reg_imm (code, X86_SHR, ins->unused, ins->inst_imm);
2517 x86_not_reg (code, ins->sreg1);
2520 x86_neg_reg (code, ins->sreg1);
2523 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2526 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2529 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2532 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2535 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2536 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2538 case CEE_MUL_OVF_UN: {
2539 /* the mul operation and the exception check should most likely be split */
2540 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2541 /*g_assert (ins->sreg2 == X86_EAX);
2542 g_assert (ins->dreg == X86_EAX);*/
2543 if (ins->sreg2 == X86_EAX) {
2544 non_eax_reg = ins->sreg1;
2545 } else if (ins->sreg1 == X86_EAX) {
2546 non_eax_reg = ins->sreg2;
2548 /* no need to save since we're going to store to it anyway */
2549 if (ins->dreg != X86_EAX) {
2551 x86_push_reg (code, X86_EAX);
2553 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
2554 non_eax_reg = ins->sreg2;
2556 if (ins->dreg == X86_EDX) {
2559 x86_push_reg (code, X86_EAX);
2561 } else if (ins->dreg != X86_EAX) {
2563 x86_push_reg (code, X86_EDX);
2565 x86_mul_reg (code, non_eax_reg, FALSE);
2566 /* save before the check since pop and mov don't change the flags */
2567 if (ins->dreg != X86_EAX)
2568 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2570 x86_pop_reg (code, X86_EDX);
2572 x86_pop_reg (code, X86_EAX);
2573 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2577 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
2580 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2581 x86_mov_reg_imm (code, ins->dreg, 0);
2585 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2588 g_assert_not_reached ();
2591 * Note: this 'frame destruction' logic is useful for tail calls, too.
2592 * Keep in sync with the code in emit_epilog.
2596 /* FIXME: no tracing support... */
2597 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2598 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2599 /* reset offset to make max_len work */
2600 offset = code - cfg->native_code;
2602 g_assert (!cfg->method->save_lmf);
2604 if (cfg->used_int_regs & (1 << X86_EBX))
2606 if (cfg->used_int_regs & (1 << X86_EDI))
2608 if (cfg->used_int_regs & (1 << X86_ESI))
2611 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
2613 if (cfg->used_int_regs & (1 << X86_ESI))
2614 x86_pop_reg (code, X86_ESI);
2615 if (cfg->used_int_regs & (1 << X86_EDI))
2616 x86_pop_reg (code, X86_EDI);
2617 if (cfg->used_int_regs & (1 << X86_EBX))
2618 x86_pop_reg (code, X86_EBX);
2620 /* restore ESP/EBP */
2622 offset = code - cfg->native_code;
2623 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2624 x86_jump32 (code, 0);
2628 /* ensure ins->sreg1 is not NULL
2629 * note that cmp DWORD PTR [eax], eax is one byte shorter than
2630 * cmp DWORD PTR [eax], 0
2632 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
2635 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
2636 x86_push_reg (code, hreg);
2637 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
2638 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
2639 x86_pop_reg (code, hreg);
2647 call = (MonoCallInst*)ins;
2648 if (ins->flags & MONO_INST_HAS_METHOD)
2649 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD, call->method);
2651 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, call->fptr);
2653 x86_call_code (code, 0);
2654 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2655 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2660 case OP_VOIDCALL_REG:
2662 call = (MonoCallInst*)ins;
2663 x86_call_reg (code, ins->sreg1);
2664 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2665 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2667 case OP_FCALL_MEMBASE:
2668 case OP_LCALL_MEMBASE:
2669 case OP_VCALL_MEMBASE:
2670 case OP_VOIDCALL_MEMBASE:
2671 case OP_CALL_MEMBASE:
2672 call = (MonoCallInst*)ins;
2673 x86_call_membase (code, ins->sreg1, ins->inst_offset);
2674 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2675 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
2679 x86_push_reg (code, ins->sreg1);
2681 case OP_X86_PUSH_IMM:
2682 x86_push_imm (code, ins->inst_imm);
2684 case OP_X86_PUSH_MEMBASE:
2685 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
2687 case OP_X86_PUSH_OBJ:
2688 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
2689 x86_push_reg (code, X86_EDI);
2690 x86_push_reg (code, X86_ESI);
2691 x86_push_reg (code, X86_ECX);
2692 if (ins->inst_offset)
2693 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
2695 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
2696 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2697 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
2699 x86_prefix (code, X86_REP_PREFIX);
2701 x86_pop_reg (code, X86_ECX);
2702 x86_pop_reg (code, X86_ESI);
2703 x86_pop_reg (code, X86_EDI);
2706 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->unused);
2708 case OP_X86_LEA_MEMBASE:
2709 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
2712 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
2715 /* keep alignment */
2716 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
2717 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
2718 code = mono_emit_stack_alloc (code, ins);
2719 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
2725 x86_push_reg (code, ins->sreg1);
2726 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2727 (gpointer)"mono_arch_throw_exception");
2728 x86_call_code (code, 0);
2731 case OP_CALL_HANDLER:
2732 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2733 x86_call_imm (code, 0);
2736 ins->inst_c0 = code - cfg->native_code;
2739 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
2740 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
2742 if (ins->flags & MONO_INST_BRLABEL) {
2743 if (ins->inst_i0->inst_c0) {
2744 x86_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
2746 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
2747 if ((cfg->opt & MONO_OPT_BRANCH) &&
2748 x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
2749 x86_jump8 (code, 0);
2751 x86_jump32 (code, 0);
2754 if (ins->inst_target_bb->native_offset) {
2755 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
2757 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2758 if ((cfg->opt & MONO_OPT_BRANCH) &&
2759 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
2760 x86_jump8 (code, 0);
2762 x86_jump32 (code, 0);
2767 x86_jump_reg (code, ins->sreg1);
2770 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
2771 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2774 x86_set_reg (code, X86_CC_LT, ins->dreg, TRUE);
2775 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2778 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
2779 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2782 x86_set_reg (code, X86_CC_GT, ins->dreg, TRUE);
2783 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2786 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
2787 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2790 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
2791 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
2793 case OP_COND_EXC_EQ:
2794 case OP_COND_EXC_NE_UN:
2795 case OP_COND_EXC_LT:
2796 case OP_COND_EXC_LT_UN:
2797 case OP_COND_EXC_GT:
2798 case OP_COND_EXC_GT_UN:
2799 case OP_COND_EXC_GE:
2800 case OP_COND_EXC_GE_UN:
2801 case OP_COND_EXC_LE:
2802 case OP_COND_EXC_LE_UN:
2803 case OP_COND_EXC_OV:
2804 case OP_COND_EXC_NO:
2806 case OP_COND_EXC_NC:
2807 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
2808 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
2820 EMIT_COND_BRANCH (ins, branch_cc_table [ins->opcode - CEE_BEQ], (ins->opcode < CEE_BNE_UN));
2823 /* floating point opcodes */
2825 double d = *(double *)ins->inst_p0;
2827 if ((d == 0.0) && (mono_signbit (d) == 0)) {
2829 } else if (d == 1.0) {
2832 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
2833 x86_fld (code, NULL, TRUE);
2838 float f = *(float *)ins->inst_p0;
2840 if ((f == 0.0) && (mono_signbit (f) == 0)) {
2842 } else if (f == 1.0) {
2845 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
2846 x86_fld (code, NULL, FALSE);
2850 case OP_STORER8_MEMBASE_REG:
2851 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
2853 case OP_LOADR8_SPILL_MEMBASE:
2854 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
2857 case OP_LOADR8_MEMBASE:
2858 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
2860 case OP_STORER4_MEMBASE_REG:
2861 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
2863 case OP_LOADR4_MEMBASE:
2864 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
2866 case CEE_CONV_R4: /* FIXME: change precision */
2868 x86_push_reg (code, ins->sreg1);
2869 x86_fild_membase (code, X86_ESP, 0, FALSE);
2870 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2872 case OP_X86_FP_LOAD_I8:
2873 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
2875 case OP_X86_FP_LOAD_I4:
2876 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
2878 case OP_FCONV_TO_I1:
2879 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
2881 case OP_FCONV_TO_U1:
2882 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
2884 case OP_FCONV_TO_I2:
2885 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
2887 case OP_FCONV_TO_U2:
2888 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
2890 case OP_FCONV_TO_I4:
2892 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
2894 case OP_FCONV_TO_I8:
2895 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2896 x86_fnstcw_membase(code, X86_ESP, 0);
2897 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
2898 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
2899 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
2900 x86_fldcw_membase (code, X86_ESP, 2);
2901 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2902 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2903 x86_pop_reg (code, ins->dreg);
2904 x86_pop_reg (code, ins->unused);
2905 x86_fldcw_membase (code, X86_ESP, 0);
2906 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2908 case OP_LCONV_TO_R_UN: {
2909 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
2912 /* load 64bit integer to FP stack */
2913 x86_push_imm (code, 0);
2914 x86_push_reg (code, ins->sreg2);
2915 x86_push_reg (code, ins->sreg1);
2916 x86_fild_membase (code, X86_ESP, 0, TRUE);
2917 /* store as 80bit FP value */
2918 x86_fst80_membase (code, X86_ESP, 0);
2920 /* test if lreg is negative */
2921 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
2922 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
2924 /* add correction constant mn */
2925 x86_fld80_mem (code, mn);
2926 x86_fld80_membase (code, X86_ESP, 0);
2927 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
2928 x86_fst80_membase (code, X86_ESP, 0);
2930 x86_patch (br, code);
2932 x86_fld80_membase (code, X86_ESP, 0);
2933 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
2937 case OP_LCONV_TO_OVF_I: {
2938 guint8 *br [3], *label [1];
2941 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
2943 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2945 /* If the low word top bit is set, see if we are negative */
2946 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
2947 /* We are not negative (no top bit set, check for our top word to be zero */
2948 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
2949 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2952 /* throw exception */
2953 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
2954 x86_jump32 (code, 0);
2956 x86_patch (br [0], code);
2957 /* our top bit is set, check that top word is 0xfffffff */
2958 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
2960 x86_patch (br [1], code);
2961 /* nope, emit exception */
2962 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
2963 x86_patch (br [2], label [0]);
2965 if (ins->dreg != ins->sreg1)
2966 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
2970 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
2973 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
2976 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
2979 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
2987 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
2992 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
2999 * it really doesn't make sense to inline all this code,
3000 * it's here just to show that things may not be as simple
3003 guchar *check_pos, *end_tan, *pop_jump;
3004 x86_push_reg (code, X86_EAX);
3007 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3009 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3010 x86_fstp (code, 0); /* pop the 1.0 */
3012 x86_jump8 (code, 0);
3014 x86_fp_op (code, X86_FADD, 0);
3018 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3020 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3023 x86_patch (pop_jump, code);
3024 x86_fstp (code, 0); /* pop the 1.0 */
3025 x86_patch (check_pos, code);
3026 x86_patch (end_tan, code);
3028 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3029 x86_pop_reg (code, X86_EAX);
3036 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3047 x86_push_reg (code, X86_EAX);
3048 /* we need to exchange ST(0) with ST(1) */
3051 /* this requires a loop, because fprem somtimes
3052 * returns a partial remainder */
3054 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3055 /* x86_fprem1 (code); */
3058 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3060 x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3065 x86_pop_reg (code, X86_EAX);
3069 if (cfg->opt & MONO_OPT_FCMOV) {
3070 x86_fcomip (code, 1);
3074 /* this overwrites EAX */
3075 EMIT_FPCOMPARE(code);
3076 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3079 if (cfg->opt & MONO_OPT_FCMOV) {
3080 /* zeroing the register at the start results in
3081 * shorter and faster code (we can also remove the widening op)
3083 guchar *unordered_check;
3084 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3085 x86_fcomip (code, 1);
3087 unordered_check = code;
3088 x86_branch8 (code, X86_CC_P, 0, FALSE);
3089 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3090 x86_patch (unordered_check, code);
3093 if (ins->dreg != X86_EAX)
3094 x86_push_reg (code, X86_EAX);
3096 EMIT_FPCOMPARE(code);
3097 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3098 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3099 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3100 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3102 if (ins->dreg != X86_EAX)
3103 x86_pop_reg (code, X86_EAX);
3107 if (cfg->opt & MONO_OPT_FCMOV) {
3108 /* zeroing the register at the start results in
3109 * shorter and faster code (we can also remove the widening op)
3111 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3112 x86_fcomip (code, 1);
3114 if (ins->opcode == OP_FCLT_UN) {
3115 guchar *unordered_check = code;
3116 guchar *jump_to_end;
3117 x86_branch8 (code, X86_CC_P, 0, FALSE);
3118 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3120 x86_jump8 (code, 0);
3121 x86_patch (unordered_check, code);
3122 x86_inc_reg (code, ins->dreg);
3123 x86_patch (jump_to_end, code);
3125 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3129 if (ins->dreg != X86_EAX)
3130 x86_push_reg (code, X86_EAX);
3132 EMIT_FPCOMPARE(code);
3133 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3134 if (ins->opcode == OP_FCLT_UN) {
3135 guchar *is_not_zero_check, *end_jump;
3136 is_not_zero_check = code;
3137 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3139 x86_jump8 (code, 0);
3140 x86_patch (is_not_zero_check, code);
3141 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3143 x86_patch (end_jump, code);
3145 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3146 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3148 if (ins->dreg != X86_EAX)
3149 x86_pop_reg (code, X86_EAX);
3153 if (cfg->opt & MONO_OPT_FCMOV) {
3154 /* zeroing the register at the start results in
3155 * shorter and faster code (we can also remove the widening op)
3157 guchar *unordered_check;
3158 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3159 x86_fcomip (code, 1);
3161 if (ins->opcode == OP_FCGT) {
3162 unordered_check = code;
3163 x86_branch8 (code, X86_CC_P, 0, FALSE);
3164 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3165 x86_patch (unordered_check, code);
3167 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3171 if (ins->dreg != X86_EAX)
3172 x86_push_reg (code, X86_EAX);
3174 EMIT_FPCOMPARE(code);
3175 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3176 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3177 if (ins->opcode == OP_FCGT_UN) {
3178 guchar *is_not_zero_check, *end_jump;
3179 is_not_zero_check = code;
3180 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3182 x86_jump8 (code, 0);
3183 x86_patch (is_not_zero_check, code);
3184 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3186 x86_patch (end_jump, code);
3188 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3189 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3191 if (ins->dreg != X86_EAX)
3192 x86_pop_reg (code, X86_EAX);
3195 if (cfg->opt & MONO_OPT_FCMOV) {
3196 guchar *jump = code;
3197 x86_branch8 (code, X86_CC_P, 0, TRUE);
3198 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3199 x86_patch (jump, code);
3202 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3203 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3206 /* Branch if C013 != 100 */
3207 if (cfg->opt & MONO_OPT_FCMOV) {
3208 /* branch if !ZF or (PF|CF) */
3209 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3210 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3211 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3214 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3215 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3218 if (cfg->opt & MONO_OPT_FCMOV) {
3219 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3222 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3225 if (cfg->opt & MONO_OPT_FCMOV) {
3226 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3227 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3230 if (ins->opcode == OP_FBLT_UN) {
3231 guchar *is_not_zero_check, *end_jump;
3232 is_not_zero_check = code;
3233 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3235 x86_jump8 (code, 0);
3236 x86_patch (is_not_zero_check, code);
3237 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3239 x86_patch (end_jump, code);
3241 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3245 if (cfg->opt & MONO_OPT_FCMOV) {
3246 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3249 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3250 if (ins->opcode == OP_FBGT_UN) {
3251 guchar *is_not_zero_check, *end_jump;
3252 is_not_zero_check = code;
3253 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3255 x86_jump8 (code, 0);
3256 x86_patch (is_not_zero_check, code);
3257 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3259 x86_patch (end_jump, code);
3261 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3264 /* Branch if C013 == 100 or 001 */
3265 if (cfg->opt & MONO_OPT_FCMOV) {
3268 /* skip branch if C1=1 */
3270 x86_branch8 (code, X86_CC_P, 0, FALSE);
3271 /* branch if (C0 | C3) = 1 */
3272 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3273 x86_patch (br1, code);
3276 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3277 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3278 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
3279 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3282 /* Branch if C013 == 000 */
3283 if (cfg->opt & MONO_OPT_FCMOV) {
3284 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3287 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3290 /* Branch if C013=000 or 100 */
3291 if (cfg->opt & MONO_OPT_FCMOV) {
3294 /* skip branch if C1=1 */
3296 x86_branch8 (code, X86_CC_P, 0, FALSE);
3297 /* branch if C0=0 */
3298 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3299 x86_patch (br1, code);
3302 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
3303 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
3304 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3307 /* Branch if C013 != 001 */
3308 if (cfg->opt & MONO_OPT_FCMOV) {
3309 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3310 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3313 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3314 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3316 case CEE_CKFINITE: {
3317 x86_push_reg (code, X86_EAX);
3320 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
3321 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3322 x86_pop_reg (code, X86_EAX);
3323 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3327 case OP_X86_TLS_GET: {
3328 x86_prefix (code, X86_GS_PREFIX);
3329 x86_mov_reg_mem (code, ins->dreg, ins->inst_offset, 4);
3333 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3334 g_assert_not_reached ();
3337 if ((code - cfg->native_code - offset) > max_len) {
3338 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
3339 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
3340 g_assert_not_reached ();
3346 last_offset = offset;
3351 cfg->code_len = code - cfg->native_code;
3355 mono_arch_register_lowlevel_calls (void)
3360 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3362 MonoJumpInfo *patch_info;
3364 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3365 unsigned char *ip = patch_info->ip.i + code;
3366 const unsigned char *target;
3368 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3370 switch (patch_info->type) {
3371 case MONO_PATCH_INFO_IP:
3372 *((gconstpointer *)(ip)) = target;
3374 case MONO_PATCH_INFO_METHOD_REL:
3375 *((gconstpointer *)(ip)) = target;
3377 case MONO_PATCH_INFO_SWITCH: {
3378 *((gconstpointer *)(ip + 2)) = target;
3379 /* we put into the table the absolute address, no need for x86_patch in this case */
3382 case MONO_PATCH_INFO_IID:
3383 *((guint32 *)(ip + 1)) = (guint32)target;
3385 case MONO_PATCH_INFO_CLASS_INIT: {
3387 /* Might already been changed to a nop */
3388 x86_call_imm (code, 0);
3391 case MONO_PATCH_INFO_R4:
3392 case MONO_PATCH_INFO_R8:
3393 *((gconstpointer *)(ip + 2)) = target;
3395 case MONO_PATCH_INFO_METHODCONST:
3396 case MONO_PATCH_INFO_CLASS:
3397 case MONO_PATCH_INFO_IMAGE:
3398 case MONO_PATCH_INFO_FIELD:
3399 case MONO_PATCH_INFO_VTABLE:
3400 case MONO_PATCH_INFO_SFLDA:
3401 case MONO_PATCH_INFO_EXC_NAME:
3402 case MONO_PATCH_INFO_LDSTR:
3403 case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
3404 case MONO_PATCH_INFO_LDTOKEN:
3405 *((gconstpointer *)(ip + 1)) = target;
3410 x86_patch (ip, target);
3415 mono_arch_max_epilog_size (MonoCompile *cfg)
3417 int exc_count = 0, max_epilog_size = 16;
3418 MonoJumpInfo *patch_info;
3420 if (cfg->method->save_lmf)
3421 max_epilog_size += 128;
3423 if (mono_jit_trace_calls != NULL)
3424 max_epilog_size += 50;
3426 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3427 max_epilog_size += 50;
3429 /* count the number of exception infos */
3431 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
3432 if (patch_info->type == MONO_PATCH_INFO_EXC)
3437 * make sure we have enough space for exceptions
3438 * 16 is the size of two push_imm instructions and a call
3440 max_epilog_size += exc_count*16;
3442 return max_epilog_size;
3446 mono_arch_emit_prolog (MonoCompile *cfg)
3448 MonoMethod *method = cfg->method;
3450 MonoMethodSignature *sig;
3452 int alloc_size, pos, max_offset, i;
3455 cfg->code_size = MAX (((MonoMethodNormal *)method)->header->code_size * 4, 256);
3456 code = cfg->native_code = g_malloc (cfg->code_size);
3458 x86_push_reg (code, X86_EBP);
3459 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
3461 alloc_size = - cfg->stack_offset;
3464 if (method->save_lmf) {
3465 pos += sizeof (MonoLMF);
3467 /* save the current IP */
3468 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
3469 x86_push_imm_template (code);
3471 /* save all caller saved regs */
3472 x86_push_reg (code, X86_EBP);
3473 x86_push_reg (code, X86_ESI);
3474 x86_push_reg (code, X86_EDI);
3475 x86_push_reg (code, X86_EBX);
3477 /* save method info */
3478 x86_push_imm (code, method);
3480 /* get the address of lmf for the current thread */
3482 * This is performance critical so we try to use some tricks to make
3485 if (lmf_tls_offset != -1) {
3486 /* Load lmf quicky using the GS register */
3487 x86_prefix (code, X86_GS_PREFIX);
3488 x86_mov_reg_mem (code, X86_EAX, lmf_tls_offset, 4);
3491 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3492 (gpointer)"mono_get_lmf_addr");
3493 x86_call_code (code, 0);
3497 x86_push_reg (code, X86_EAX);
3498 /* push *lfm (previous_lmf) */
3499 x86_push_membase (code, X86_EAX, 0);
3501 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
3504 if (cfg->used_int_regs & (1 << X86_EBX)) {
3505 x86_push_reg (code, X86_EBX);
3509 if (cfg->used_int_regs & (1 << X86_EDI)) {
3510 x86_push_reg (code, X86_EDI);
3514 if (cfg->used_int_regs & (1 << X86_ESI)) {
3515 x86_push_reg (code, X86_ESI);
3523 /* See mono_emit_stack_alloc */
3524 #ifdef PLATFORM_WIN32
3525 guint32 remaining_size = alloc_size;
3526 while (remaining_size >= 0x1000) {
3527 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
3528 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
3529 remaining_size -= 0x1000;
3532 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
3534 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
3538 /* compute max_offset in order to use short forward jumps */
3540 if (cfg->opt & MONO_OPT_BRANCH) {
3541 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
3542 MonoInst *ins = bb->code;
3543 bb->max_offset = max_offset;
3545 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
3547 /* max alignment for loops */
3548 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
3549 max_offset += LOOP_ALIGNMENT;
3552 if (ins->opcode == OP_LABEL)
3553 ins->inst_c1 = max_offset;
3555 max_offset += ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
3561 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3562 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
3564 /* load arguments allocated to register from the stack */
3565 sig = method->signature;
3568 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3569 inst = cfg->varinfo [pos];
3570 if (inst->opcode == OP_REGVAR) {
3571 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
3572 if (cfg->verbose_level > 2)
3573 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
3578 cfg->code_len = code - cfg->native_code;
3584 mono_arch_emit_epilog (MonoCompile *cfg)
3586 MonoJumpInfo *patch_info;
3587 MonoMethod *method = cfg->method;
3588 MonoMethodSignature *sig = method->signature;
3590 guint32 stack_to_pop;
3593 code = cfg->native_code + cfg->code_len;
3595 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3596 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
3598 /* the code restoring the registers must be kept in sync with CEE_JMP */
3601 if (method->save_lmf) {
3602 gint32 prev_lmf_reg;
3604 /* Find a spare register */
3605 switch (sig->ret->type) {
3608 prev_lmf_reg = X86_EDI;
3609 cfg->used_int_regs |= (1 << X86_EDI);
3612 prev_lmf_reg = X86_EDX;
3616 /* reg = previous_lmf */
3617 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, -32, 4);
3620 x86_mov_reg_membase (code, X86_ECX, X86_EBP, -28, 4);
3622 /* *(lmf) = previous_lmf */
3623 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
3625 /* restore caller saved regs */
3626 if (cfg->used_int_regs & (1 << X86_EBX)) {
3627 x86_mov_reg_membase (code, X86_EBX, X86_EBP, -20, 4);
3630 if (cfg->used_int_regs & (1 << X86_EDI)) {
3631 x86_mov_reg_membase (code, X86_EDI, X86_EBP, -16, 4);
3633 if (cfg->used_int_regs & (1 << X86_ESI)) {
3634 x86_mov_reg_membase (code, X86_ESI, X86_EBP, -12, 4);
3637 /* EBP is restored by LEAVE */
3639 if (cfg->used_int_regs & (1 << X86_EBX)) {
3642 if (cfg->used_int_regs & (1 << X86_EDI)) {
3645 if (cfg->used_int_regs & (1 << X86_ESI)) {
3650 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
3652 if (cfg->used_int_regs & (1 << X86_ESI)) {
3653 x86_pop_reg (code, X86_ESI);
3655 if (cfg->used_int_regs & (1 << X86_EDI)) {
3656 x86_pop_reg (code, X86_EDI);
3658 if (cfg->used_int_regs & (1 << X86_EBX)) {
3659 x86_pop_reg (code, X86_EBX);
3665 if (CALLCONV_IS_STDCALL (sig->call_convention)) {
3666 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
3668 stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
3669 } else if (MONO_TYPE_ISSTRUCT (cfg->method->signature->ret))
3675 x86_ret_imm (code, stack_to_pop);
3679 /* add code to raise exceptions */
3680 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
3681 switch (patch_info->type) {
3682 case MONO_PATCH_INFO_EXC:
3683 x86_patch (patch_info->ip.i + cfg->native_code, code);
3684 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC_NAME, patch_info->data.target);
3685 x86_push_imm (code, patch_info->data.target);
3686 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_METHOD_REL, (gpointer)patch_info->ip.i);
3687 x86_push_imm (code, patch_info->ip.i + cfg->native_code);
3688 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
3689 patch_info->data.name = "mono_arch_throw_exception_by_name";
3690 patch_info->ip.i = code - cfg->native_code;
3691 x86_jump_code (code, 0);
3699 cfg->code_len = code - cfg->native_code;
3701 g_assert (cfg->code_len < cfg->code_size);
3706 mono_arch_flush_icache (guint8 *code, gint size)
3712 mono_arch_flush_register_windows (void)
3717 * Support for fast access to the thread-local lmf structure using the GS
3718 * segment register on NPTL + kernel 2.6.x.
3721 static gboolean tls_offset_inited = FALSE;
3723 /* code should be simply return <tls var>; */
3724 static int read_tls_offset_from_method (void* method)
3726 guint8* code = (guint8*) method;
3728 * Determine the offset of the variable inside the TLS structures
3729 * by disassembling the function.
3737 * mov eax, DWORD PTR [eax+<offset>]
3740 (code [0] == 0x55) && (code [1] == 0x89) && (code [2] == 0xe5) &&
3741 (code [3] == 0x65) && (code [4] == 0xa1) && (code [5] == 0x00) &&
3742 (code [6] == 0x00) && (code [7] == 0x00) && (code [8] == 0x00) &&
3743 (code [9] == 0x8b) && (code [10] == 0x80)) {
3744 return *(int*)&(code [11]);
3751 * mov eax, gs:<offset>
3754 (code [0] == 0x55) && (code [1] == 0x89) && (code [2] == 0xe5) &&
3755 (code [3] == 0x65) && (code [4] == 0xa1)) {
3756 return *(int*)&(code [5]);
3759 /* 3.2.2 with -march=athlon
3762 * mov eax, gs:<offset>
3766 (code [0] == 0x55) && (code [1] == 0x65) && (code [2] == 0xa1)) {
3767 return *(int*)&(code [3]);
3773 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
3775 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3776 pthread_t self = pthread_self();
3777 pthread_attr_t attr;
3778 void *staddr = NULL;
3780 struct sigaltstack sa;
3783 if (!tls_offset_inited) {
3784 tls_offset_inited = TRUE;
3785 if (getenv ("MONO_NPTL")) {
3786 lmf_tls_offset = read_tls_offset_from_method (mono_get_lmf_addr);
3787 appdomain_tls_offset = read_tls_offset_from_method (mono_domain_get);
3788 thread_tls_offset = read_tls_offset_from_method (mono_thread_current);
3792 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3794 /* Determine stack boundaries */
3795 if (!mono_running_on_valgrind ()) {
3796 #ifdef HAVE_PTHREAD_GETATTR_NP
3797 pthread_getattr_np( self, &attr );
3799 #ifdef HAVE_PTHREAD_ATTR_GET_NP
3800 pthread_attr_get_np( self, &attr );
3802 pthread_attr_init( &attr );
3803 pthread_attr_getstacksize( &attr, &stsize );
3805 #error "Not implemented"
3809 pthread_attr_getstack( &attr, &staddr, &stsize );
3814 * staddr seems to be wrong for the main thread, so we keep the value in
3817 tls->stack_size = stsize;
3819 /* Setup an alternate signal stack */
3820 tls->signal_stack = g_malloc (SIGNAL_STACK_SIZE);
3821 tls->signal_stack_size = SIGNAL_STACK_SIZE;
3823 sa.ss_sp = tls->signal_stack;
3824 sa.ss_size = SIGNAL_STACK_SIZE;
3825 sa.ss_flags = SS_ONSTACK;
3826 sigaltstack (&sa, NULL);
3831 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
3833 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3834 struct sigaltstack sa;
3836 sa.ss_sp = tls->signal_stack;
3837 sa.ss_size = SIGNAL_STACK_SIZE;
3838 sa.ss_flags = SS_DISABLE;
3839 sigaltstack (&sa, NULL);
3841 if (tls->signal_stack)
3842 g_free (tls->signal_stack);
3847 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
3850 /* add the this argument */
3851 if (this_reg != -1) {
3853 MONO_INST_NEW (cfg, this, OP_OUTARG);
3854 this->type = this_type;
3855 this->sreg1 = this_reg;
3856 mono_bblock_add_inst (cfg->cbb, this);
3861 MONO_INST_NEW (cfg, vtarg, OP_OUTARG);
3862 vtarg->type = STACK_MP;
3863 vtarg->sreg1 = vt_reg;
3864 mono_bblock_add_inst (cfg->cbb, vtarg);
3870 mono_arch_get_opcode_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
3872 if (cmethod->klass == mono_defaults.math_class) {
3873 if (strcmp (cmethod->name, "Sin") == 0)
3875 else if (strcmp (cmethod->name, "Cos") == 0)
3877 else if (strcmp (cmethod->name, "Tan") == 0)
3879 else if (strcmp (cmethod->name, "Atan") == 0)
3881 else if (strcmp (cmethod->name, "Sqrt") == 0)
3883 else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8)
3886 /* OP_FREM is not IEEE compatible */
3887 else if (strcmp (cmethod->name, "IEEERemainder") == 0)
3900 mono_arch_print_tree (MonoInst *tree, int arity)
3905 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
3909 if (appdomain_tls_offset == -1)
3912 MONO_INST_NEW (cfg, ins, OP_X86_TLS_GET);
3913 ins->inst_offset = appdomain_tls_offset;
3917 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
3921 if (thread_tls_offset == -1)
3924 MONO_INST_NEW (cfg, ins, OP_X86_TLS_GET);
3925 ins->inst_offset = thread_tls_offset;