2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/appdomain.h>
21 #include <mono/metadata/debug-helpers.h>
22 #include <mono/metadata/threads.h>
23 #include <mono/metadata/profiler-private.h>
24 #include <mono/metadata/mono-debug.h>
25 #include <mono/metadata/gc-internal.h>
26 #include <mono/utils/mono-math.h>
27 #include <mono/utils/mono-counters.h>
28 #include <mono/utils/mono-mmap.h>
29 #include <mono/utils/mono-memory-model.h>
30 #include <mono/utils/mono-hwcap-x86.h>
38 /* On windows, these hold the key returned by TlsAlloc () */
40 static gint jit_tls_offset = -1;
42 static gint lmf_addr_tls_offset = -1;
46 static gboolean optimize_for_xen = TRUE;
48 #define optimize_for_xen 0
51 /* This mutex protects architecture specific caches */
52 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
53 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
54 static CRITICAL_SECTION mini_arch_mutex;
56 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
61 /* Under windows, the default pinvoke calling convention is stdcall */
62 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
64 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
67 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
70 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
73 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
75 #ifdef __native_client_codegen__
77 /* Default alignment for Native Client is 32-byte. */
78 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
80 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
81 /* Check that alignment doesn't cross an alignment boundary. */
83 mono_arch_nacl_pad (guint8 *code, int pad)
85 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
87 if (pad == 0) return code;
88 /* assertion: alignment cannot cross a block boundary */
89 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
90 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
91 while (pad >= kMaxPadding) {
92 x86_padding (code, kMaxPadding);
95 if (pad != 0) x86_padding (code, pad);
100 mono_arch_nacl_skip_nops (guint8 *code)
102 x86_skip_nops (code);
106 #endif /* __native_client_codegen__ */
109 * The code generated for sequence points reads from this location, which is
110 * made read-only when single stepping is enabled.
112 static gpointer ss_trigger_page;
114 /* Enabled breakpoints read from this trigger page */
115 static gpointer bp_trigger_page;
118 mono_arch_regname (int reg)
121 case X86_EAX: return "%eax";
122 case X86_EBX: return "%ebx";
123 case X86_ECX: return "%ecx";
124 case X86_EDX: return "%edx";
125 case X86_ESP: return "%esp";
126 case X86_EBP: return "%ebp";
127 case X86_EDI: return "%edi";
128 case X86_ESI: return "%esi";
134 mono_arch_fregname (int reg)
159 mono_arch_xregname (int reg)
184 mono_x86_patch (unsigned char* code, gpointer target)
186 x86_patch (code, (unsigned char*)target);
197 /* gsharedvt argument passed by addr */
209 /* Only if storage == ArgValuetypeInReg */
210 ArgStorage pair_storage [2];
219 gboolean need_stack_align;
220 guint32 stack_align_amount;
221 gboolean vtype_retaddr;
222 /* The index of the vret arg in the argument list */
230 #define FLOAT_PARAM_REGS 0
232 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
234 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
239 switch (sig->call_convention) {
240 case MONO_CALL_THISCALL:
241 return thiscall_param_regs;
247 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
248 #define SMALL_STRUCTS_IN_REGS
249 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
253 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
255 ainfo->offset = *stack_size;
257 if (!param_regs || param_regs [*gr] == X86_NREG) {
258 ainfo->storage = ArgOnStack;
260 (*stack_size) += sizeof (gpointer);
263 ainfo->storage = ArgInIReg;
264 ainfo->reg = param_regs [*gr];
270 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
272 ainfo->offset = *stack_size;
274 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
276 ainfo->storage = ArgOnStack;
277 (*stack_size) += sizeof (gpointer) * 2;
282 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
284 ainfo->offset = *stack_size;
286 if (*gr >= FLOAT_PARAM_REGS) {
287 ainfo->storage = ArgOnStack;
288 (*stack_size) += is_double ? 8 : 4;
289 ainfo->nslots = is_double ? 2 : 1;
292 /* A double register */
294 ainfo->storage = ArgInDoubleSSEReg;
296 ainfo->storage = ArgInFloatSSEReg;
304 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
306 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
311 klass = mono_class_from_mono_type (type);
312 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
314 #ifdef SMALL_STRUCTS_IN_REGS
315 if (sig->pinvoke && is_return) {
316 MonoMarshalType *info;
319 * the exact rules are not very well documented, the code below seems to work with the
320 * code generated by gcc 3.3.3 -mno-cygwin.
322 info = mono_marshal_load_type_info (klass);
325 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
327 /* Special case structs with only a float member */
328 if (info->num_fields == 1) {
329 int ftype = mini_replace_type (info->fields [0].field->type)->type;
330 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
331 ainfo->storage = ArgValuetypeInReg;
332 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
335 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
336 ainfo->storage = ArgValuetypeInReg;
337 ainfo->pair_storage [0] = ArgOnFloatFpStack;
341 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
342 ainfo->storage = ArgValuetypeInReg;
343 ainfo->pair_storage [0] = ArgInIReg;
344 ainfo->pair_regs [0] = return_regs [0];
345 if (info->native_size > 4) {
346 ainfo->pair_storage [1] = ArgInIReg;
347 ainfo->pair_regs [1] = return_regs [1];
354 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
355 g_assert (size <= 4);
356 ainfo->storage = ArgValuetypeInReg;
357 ainfo->reg = param_regs [*gr];
362 ainfo->offset = *stack_size;
363 ainfo->storage = ArgOnStack;
364 *stack_size += ALIGN_TO (size, sizeof (gpointer));
365 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
371 * Obtain information about a call according to the calling convention.
372 * For x86 ELF, see the "System V Application Binary Interface Intel386
373 * Architecture Processor Supplment, Fourth Edition" document for more
375 * For x86 win32, see ???.
378 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
380 guint32 i, gr, fr, pstart;
381 const guint32 *param_regs;
383 int n = sig->hasthis + sig->param_count;
384 guint32 stack_size = 0;
385 gboolean is_pinvoke = sig->pinvoke;
391 param_regs = callconv_param_regs(sig);
395 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
396 switch (ret_type->type) {
397 case MONO_TYPE_BOOLEAN:
408 case MONO_TYPE_FNPTR:
409 case MONO_TYPE_CLASS:
410 case MONO_TYPE_OBJECT:
411 case MONO_TYPE_SZARRAY:
412 case MONO_TYPE_ARRAY:
413 case MONO_TYPE_STRING:
414 cinfo->ret.storage = ArgInIReg;
415 cinfo->ret.reg = X86_EAX;
419 cinfo->ret.storage = ArgInIReg;
420 cinfo->ret.reg = X86_EAX;
421 cinfo->ret.is_pair = TRUE;
424 cinfo->ret.storage = ArgOnFloatFpStack;
427 cinfo->ret.storage = ArgOnDoubleFpStack;
429 case MONO_TYPE_GENERICINST:
430 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
431 cinfo->ret.storage = ArgInIReg;
432 cinfo->ret.reg = X86_EAX;
435 if (mini_is_gsharedvt_type_gsctx (gsctx, ret_type)) {
436 cinfo->ret.storage = ArgOnStack;
437 cinfo->vtype_retaddr = TRUE;
441 case MONO_TYPE_VALUETYPE:
442 case MONO_TYPE_TYPEDBYREF: {
443 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
445 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
446 if (cinfo->ret.storage == ArgOnStack) {
447 cinfo->vtype_retaddr = TRUE;
448 /* The caller passes the address where the value is stored */
454 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ret_type));
455 cinfo->ret.storage = ArgOnStack;
456 cinfo->vtype_retaddr = TRUE;
459 cinfo->ret.storage = ArgNone;
462 g_error ("Can't handle as return value 0x%x", ret_type->type);
468 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
469 * the first argument, allowing 'this' to be always passed in the first arg reg.
470 * Also do this if the first argument is a reference type, since virtual calls
471 * are sometimes made using calli without sig->hasthis set, like in the delegate
474 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
476 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
478 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
481 cinfo->vret_arg_offset = stack_size;
482 add_general (&gr, NULL, &stack_size, &cinfo->ret);
483 cinfo->vret_arg_index = 1;
487 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
489 if (cinfo->vtype_retaddr)
490 add_general (&gr, NULL, &stack_size, &cinfo->ret);
493 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
494 fr = FLOAT_PARAM_REGS;
496 /* Emit the signature cookie just before the implicit arguments */
497 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
500 for (i = pstart; i < sig->param_count; ++i) {
501 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
504 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
505 /* We allways pass the sig cookie on the stack for simplicity */
507 * Prevent implicit arguments + the sig cookie from being passed
510 fr = FLOAT_PARAM_REGS;
512 /* Emit the signature cookie just before the implicit arguments */
513 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
516 if (sig->params [i]->byref) {
517 add_general (&gr, param_regs, &stack_size, ainfo);
520 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
521 switch (ptype->type) {
522 case MONO_TYPE_BOOLEAN:
525 add_general (&gr, param_regs, &stack_size, ainfo);
530 add_general (&gr, param_regs, &stack_size, ainfo);
534 add_general (&gr, param_regs, &stack_size, ainfo);
539 case MONO_TYPE_FNPTR:
540 case MONO_TYPE_CLASS:
541 case MONO_TYPE_OBJECT:
542 case MONO_TYPE_STRING:
543 case MONO_TYPE_SZARRAY:
544 case MONO_TYPE_ARRAY:
545 add_general (&gr, param_regs, &stack_size, ainfo);
547 case MONO_TYPE_GENERICINST:
548 if (!mono_type_generic_inst_is_valuetype (ptype)) {
549 add_general (&gr, param_regs, &stack_size, ainfo);
552 if (mini_is_gsharedvt_type_gsctx (gsctx, ptype)) {
553 /* gsharedvt arguments are passed by ref */
554 add_general (&gr, param_regs, &stack_size, ainfo);
555 g_assert (ainfo->storage == ArgOnStack);
556 ainfo->storage = ArgGSharedVt;
560 case MONO_TYPE_VALUETYPE:
561 case MONO_TYPE_TYPEDBYREF:
562 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
566 add_general_pair (&gr, param_regs, &stack_size, ainfo);
569 add_float (&fr, &stack_size, ainfo, FALSE);
572 add_float (&fr, &stack_size, ainfo, TRUE);
576 /* gsharedvt arguments are passed by ref */
577 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ptype));
578 add_general (&gr, param_regs, &stack_size, ainfo);
579 g_assert (ainfo->storage == ArgOnStack);
580 ainfo->storage = ArgGSharedVt;
583 g_error ("unexpected type 0x%x", ptype->type);
584 g_assert_not_reached ();
588 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
589 fr = FLOAT_PARAM_REGS;
591 /* Emit the signature cookie just before the implicit arguments */
592 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
595 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
596 cinfo->need_stack_align = TRUE;
597 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
598 stack_size += cinfo->stack_align_amount;
601 cinfo->stack_usage = stack_size;
602 cinfo->reg_usage = gr;
603 cinfo->freg_usage = fr;
608 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
610 int n = sig->hasthis + sig->param_count;
614 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
616 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
618 return get_call_info_internal (gsctx, cinfo, sig);
622 * mono_arch_get_argument_info:
623 * @csig: a method signature
624 * @param_count: the number of parameters to consider
625 * @arg_info: an array to store the result infos
627 * Gathers information on parameters such as size, alignment and
628 * padding. arg_info should be large enought to hold param_count + 1 entries.
630 * Returns the size of the argument area on the stack.
631 * This should be signal safe, since it is called from
632 * mono_arch_find_jit_info ().
633 * FIXME: The metadata calls might not be signal safe.
636 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
638 int len, k, args_size = 0;
644 /* Avoid g_malloc as it is not signal safe */
645 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
646 cinfo = (CallInfo*)g_newa (guint8*, len);
647 memset (cinfo, 0, len);
649 cinfo = get_call_info_internal (gsctx, cinfo, csig);
651 arg_info [0].offset = offset;
653 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
654 args_size += sizeof (gpointer);
659 args_size += sizeof (gpointer);
663 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
664 /* Emitted after this */
665 args_size += sizeof (gpointer);
669 arg_info [0].size = args_size;
671 for (k = 0; k < param_count; k++) {
672 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
674 /* ignore alignment for now */
677 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
678 arg_info [k].pad = pad;
680 arg_info [k + 1].pad = 0;
681 arg_info [k + 1].size = size;
683 arg_info [k + 1].offset = offset;
686 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
687 /* Emitted after the first arg */
688 args_size += sizeof (gpointer);
693 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
694 align = MONO_ARCH_FRAME_ALIGNMENT;
697 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
698 arg_info [k].pad = pad;
704 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
706 MonoType *callee_ret;
710 if (cfg->compile_aot && !cfg->full_aot)
711 /* OP_TAILCALL doesn't work with AOT */
714 c1 = get_call_info (NULL, NULL, caller_sig);
715 c2 = get_call_info (NULL, NULL, callee_sig);
717 * Tail calls with more callee stack usage than the caller cannot be supported, since
718 * the extra stack space would be left on the stack after the tail call.
720 res = c1->stack_usage >= c2->stack_usage;
721 callee_ret = mini_replace_type (callee_sig->ret);
722 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
723 /* An address on the callee's stack is passed as the first argument */
733 * Initialize the cpu to execute managed code.
736 mono_arch_cpu_init (void)
738 /* spec compliance requires running with double precision */
742 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
743 fpcw &= ~X86_FPCW_PRECC_MASK;
744 fpcw |= X86_FPCW_PREC_DOUBLE;
745 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
746 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
748 _control87 (_PC_53, MCW_PC);
753 * Initialize architecture specific code.
756 mono_arch_init (void)
758 InitializeCriticalSection (&mini_arch_mutex);
760 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
761 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
762 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
764 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
765 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
766 #if defined(ENABLE_GSHAREDVT)
767 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
772 * Cleanup architecture specific code.
775 mono_arch_cleanup (void)
778 mono_vfree (ss_trigger_page, mono_pagesize ());
780 mono_vfree (bp_trigger_page, mono_pagesize ());
781 DeleteCriticalSection (&mini_arch_mutex);
785 * This function returns the optimizations supported on this cpu.
788 mono_arch_cpu_optimizations (guint32 *exclude_mask)
790 #if !defined(__native_client__)
795 if (mono_hwcap_x86_has_cmov) {
796 opts |= MONO_OPT_CMOV;
798 if (mono_hwcap_x86_has_fcmov)
799 opts |= MONO_OPT_FCMOV;
801 *exclude_mask |= MONO_OPT_FCMOV;
803 *exclude_mask |= MONO_OPT_CMOV;
806 if (mono_hwcap_x86_has_sse2)
807 opts |= MONO_OPT_SSE2;
809 *exclude_mask |= MONO_OPT_SSE2;
811 #ifdef MONO_ARCH_SIMD_INTRINSICS
812 /*SIMD intrinsics require at least SSE2.*/
813 if (!mono_hwcap_x86_has_sse2)
814 *exclude_mask |= MONO_OPT_SIMD;
819 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
824 * This function test for all SSE functions supported.
826 * Returns a bitmask corresponding to all supported versions.
830 mono_arch_cpu_enumerate_simd_versions (void)
832 guint32 sse_opts = 0;
834 if (mono_hwcap_x86_has_sse1)
835 sse_opts |= SIMD_VERSION_SSE1;
837 if (mono_hwcap_x86_has_sse2)
838 sse_opts |= SIMD_VERSION_SSE2;
840 if (mono_hwcap_x86_has_sse3)
841 sse_opts |= SIMD_VERSION_SSE3;
843 if (mono_hwcap_x86_has_ssse3)
844 sse_opts |= SIMD_VERSION_SSSE3;
846 if (mono_hwcap_x86_has_sse41)
847 sse_opts |= SIMD_VERSION_SSE41;
849 if (mono_hwcap_x86_has_sse42)
850 sse_opts |= SIMD_VERSION_SSE42;
852 if (mono_hwcap_x86_has_sse4a)
853 sse_opts |= SIMD_VERSION_SSE4a;
859 * Determine whenever the trap whose info is in SIGINFO is caused by
863 mono_arch_is_int_overflow (void *sigctx, void *info)
868 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
870 ip = (guint8*)ctx.eip;
872 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
876 switch (x86_modrm_rm (ip [1])) {
896 g_assert_not_reached ();
908 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
913 for (i = 0; i < cfg->num_varinfo; i++) {
914 MonoInst *ins = cfg->varinfo [i];
915 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
918 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
921 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
922 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
925 /* we dont allocate I1 to registers because there is no simply way to sign extend
926 * 8bit quantities in caller saved registers on x86 */
927 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
928 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
929 g_assert (i == vmv->idx);
930 vars = g_list_prepend (vars, vmv);
934 vars = mono_varlist_sort (cfg, vars, 0);
940 mono_arch_get_global_int_regs (MonoCompile *cfg)
944 /* we can use 3 registers for global allocation */
945 regs = g_list_prepend (regs, (gpointer)X86_EBX);
946 regs = g_list_prepend (regs, (gpointer)X86_ESI);
947 regs = g_list_prepend (regs, (gpointer)X86_EDI);
953 * mono_arch_regalloc_cost:
955 * Return the cost, in number of memory references, of the action of
956 * allocating the variable VMV into a register during global register
960 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
962 MonoInst *ins = cfg->varinfo [vmv->idx];
964 if (cfg->method->save_lmf)
965 /* The register is already saved */
966 return (ins->opcode == OP_ARG) ? 1 : 0;
968 /* push+pop+possible load if it is an argument */
969 return (ins->opcode == OP_ARG) ? 3 : 2;
973 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
975 static int inited = FALSE;
976 static int count = 0;
978 if (cfg->arch.need_stack_frame_inited) {
979 g_assert (cfg->arch.need_stack_frame == flag);
983 cfg->arch.need_stack_frame = flag;
984 cfg->arch.need_stack_frame_inited = TRUE;
990 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
995 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
999 needs_stack_frame (MonoCompile *cfg)
1001 MonoMethodSignature *sig;
1002 MonoMethodHeader *header;
1003 gboolean result = FALSE;
1005 #if defined(__APPLE__)
1006 /*OSX requires stack frame code to have the correct alignment. */
1010 if (cfg->arch.need_stack_frame_inited)
1011 return cfg->arch.need_stack_frame;
1013 header = cfg->header;
1014 sig = mono_method_signature (cfg->method);
1016 if (cfg->disable_omit_fp)
1018 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1020 else if (cfg->method->save_lmf)
1022 else if (cfg->stack_offset)
1024 else if (cfg->param_area)
1026 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1028 else if (header->num_clauses)
1030 else if (sig->param_count + sig->hasthis)
1032 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1034 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1035 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1038 set_needs_stack_frame (cfg, result);
1040 return cfg->arch.need_stack_frame;
1044 * Set var information according to the calling convention. X86 version.
1045 * The locals var stuff should most likely be split in another method.
1048 mono_arch_allocate_vars (MonoCompile *cfg)
1050 MonoMethodSignature *sig;
1051 MonoMethodHeader *header;
1053 guint32 locals_stack_size, locals_stack_align;
1058 header = cfg->header;
1059 sig = mono_method_signature (cfg->method);
1061 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1063 cfg->frame_reg = X86_EBP;
1066 if (cfg->has_atomic_add_new_i4 || cfg->has_atomic_exchange_i4) {
1067 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1068 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1071 /* Reserve space to save LMF and caller saved registers */
1073 if (cfg->method->save_lmf) {
1074 /* The LMF var is allocated normally */
1076 if (cfg->used_int_regs & (1 << X86_EBX)) {
1080 if (cfg->used_int_regs & (1 << X86_EDI)) {
1084 if (cfg->used_int_regs & (1 << X86_ESI)) {
1089 switch (cinfo->ret.storage) {
1090 case ArgValuetypeInReg:
1091 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1093 cfg->ret->opcode = OP_REGOFFSET;
1094 cfg->ret->inst_basereg = X86_EBP;
1095 cfg->ret->inst_offset = - offset;
1101 /* Allocate locals */
1102 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1103 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1104 char *mname = mono_method_full_name (cfg->method, TRUE);
1105 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1106 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1110 if (locals_stack_align) {
1111 int prev_offset = offset;
1113 offset += (locals_stack_align - 1);
1114 offset &= ~(locals_stack_align - 1);
1116 while (prev_offset < offset) {
1118 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1121 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1122 cfg->locals_max_stack_offset = - offset;
1124 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1125 * have locals larger than 8 bytes we need to make sure that
1126 * they have the appropriate offset.
1128 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1129 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1130 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1131 if (offsets [i] != -1) {
1132 MonoInst *inst = cfg->varinfo [i];
1133 inst->opcode = OP_REGOFFSET;
1134 inst->inst_basereg = X86_EBP;
1135 inst->inst_offset = - (offset + offsets [i]);
1136 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1139 offset += locals_stack_size;
1143 * Allocate arguments+return value
1146 switch (cinfo->ret.storage) {
1148 if (cfg->vret_addr) {
1150 * In the new IR, the cfg->vret_addr variable represents the
1151 * vtype return value.
1153 cfg->vret_addr->opcode = OP_REGOFFSET;
1154 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1155 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1156 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1157 printf ("vret_addr =");
1158 mono_print_ins (cfg->vret_addr);
1161 cfg->ret->opcode = OP_REGOFFSET;
1162 cfg->ret->inst_basereg = X86_EBP;
1163 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1166 case ArgValuetypeInReg:
1169 cfg->ret->opcode = OP_REGVAR;
1170 cfg->ret->inst_c0 = cinfo->ret.reg;
1171 cfg->ret->dreg = cinfo->ret.reg;
1174 case ArgOnFloatFpStack:
1175 case ArgOnDoubleFpStack:
1178 g_assert_not_reached ();
1181 if (sig->call_convention == MONO_CALL_VARARG) {
1182 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1183 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1186 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1187 ArgInfo *ainfo = &cinfo->args [i];
1188 inst = cfg->args [i];
1189 if (inst->opcode != OP_REGVAR) {
1190 inst->opcode = OP_REGOFFSET;
1191 inst->inst_basereg = X86_EBP;
1193 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1196 cfg->stack_offset = offset;
1200 mono_arch_create_vars (MonoCompile *cfg)
1203 MonoMethodSignature *sig;
1206 sig = mono_method_signature (cfg->method);
1208 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1209 sig_ret = mini_replace_type (sig->ret);
1211 if (cinfo->ret.storage == ArgValuetypeInReg)
1212 cfg->ret_var_is_local = TRUE;
1213 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (cfg, sig_ret))) {
1214 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1217 if (cfg->method->save_lmf) {
1218 cfg->create_lmf_var = TRUE;
1220 if (!optimize_for_xen) {
1222 cfg->lmf_ir_mono_lmf = TRUE;
1227 cfg->arch_eh_jit_info = 1;
1231 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1232 * so we try to do it just once when we have multiple fp arguments in a row.
1233 * We don't use this mechanism generally because for int arguments the generated code
1234 * is slightly bigger and new generation cpus optimize away the dependency chains
1235 * created by push instructions on the esp value.
1236 * fp_arg_setup is the first argument in the execution sequence where the esp register
1239 static G_GNUC_UNUSED int
1240 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1245 for (; start_arg < sig->param_count; ++start_arg) {
1246 t = mini_replace_type (sig->params [start_arg]);
1247 if (!t->byref && t->type == MONO_TYPE_R8) {
1248 fp_space += sizeof (double);
1249 *fp_arg_setup = start_arg;
1258 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1260 MonoMethodSignature *tmp_sig;
1264 * mono_ArgIterator_Setup assumes the signature cookie is
1265 * passed first and all the arguments which were before it are
1266 * passed on the stack after the signature. So compensate by
1267 * passing a different signature.
1269 tmp_sig = mono_metadata_signature_dup (call->signature);
1270 tmp_sig->param_count -= call->signature->sentinelpos;
1271 tmp_sig->sentinelpos = 0;
1272 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1274 if (cfg->compile_aot) {
1275 sig_reg = mono_alloc_ireg (cfg);
1276 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1277 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, sig_reg);
1279 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1285 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1290 LLVMCallInfo *linfo;
1291 MonoType *t, *sig_ret;
1293 n = sig->param_count + sig->hasthis;
1295 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1298 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1301 * LLVM always uses the native ABI while we use our own ABI, the
1302 * only difference is the handling of vtypes:
1303 * - we only pass/receive them in registers in some cases, and only
1304 * in 1 or 2 integer registers.
1306 if (cinfo->ret.storage == ArgValuetypeInReg) {
1308 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1309 cfg->disable_llvm = TRUE;
1313 cfg->exception_message = g_strdup ("vtype ret in call");
1314 cfg->disable_llvm = TRUE;
1316 linfo->ret.storage = LLVMArgVtypeInReg;
1317 for (j = 0; j < 2; ++j)
1318 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1322 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage == ArgInIReg) {
1323 /* Vtype returned using a hidden argument */
1324 linfo->ret.storage = LLVMArgVtypeRetAddr;
1325 linfo->vret_arg_index = cinfo->vret_arg_index;
1328 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage != ArgInIReg) {
1330 cfg->exception_message = g_strdup ("vtype ret in call");
1331 cfg->disable_llvm = TRUE;
1334 for (i = 0; i < n; ++i) {
1335 ainfo = cinfo->args + i;
1337 if (i >= sig->hasthis)
1338 t = sig->params [i - sig->hasthis];
1340 t = &mono_defaults.int_class->byval_arg;
1342 linfo->args [i].storage = LLVMArgNone;
1344 switch (ainfo->storage) {
1346 linfo->args [i].storage = LLVMArgInIReg;
1348 case ArgInDoubleSSEReg:
1349 case ArgInFloatSSEReg:
1350 linfo->args [i].storage = LLVMArgInFPReg;
1353 if (mini_type_is_vtype (cfg, t)) {
1354 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1355 /* LLVM seems to allocate argument space for empty structures too */
1356 linfo->args [i].storage = LLVMArgNone;
1358 linfo->args [i].storage = LLVMArgVtypeByVal;
1360 linfo->args [i].storage = LLVMArgInIReg;
1362 if (t->type == MONO_TYPE_R4)
1363 linfo->args [i].storage = LLVMArgInFPReg;
1364 else if (t->type == MONO_TYPE_R8)
1365 linfo->args [i].storage = LLVMArgInFPReg;
1369 case ArgValuetypeInReg:
1371 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1372 cfg->disable_llvm = TRUE;
1376 cfg->exception_message = g_strdup ("vtype arg");
1377 cfg->disable_llvm = TRUE;
1379 linfo->args [i].storage = LLVMArgVtypeInReg;
1380 for (j = 0; j < 2; ++j)
1381 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1385 linfo->args [i].storage = LLVMArgGSharedVt;
1388 cfg->exception_message = g_strdup ("ainfo->storage");
1389 cfg->disable_llvm = TRUE;
1399 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1401 if (cfg->compute_gc_maps) {
1404 /* On x86, the offsets are from the sp value before the start of the call sequence */
1406 t = &mono_defaults.int_class->byval_arg;
1407 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1412 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1416 MonoMethodSignature *sig;
1419 int sentinelpos = 0, sp_offset = 0;
1421 sig = call->signature;
1422 n = sig->param_count + sig->hasthis;
1423 sig_ret = mini_replace_type (sig->ret);
1425 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1427 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1428 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1430 if (cinfo->need_stack_align) {
1431 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1432 arg->dreg = X86_ESP;
1433 arg->sreg1 = X86_ESP;
1434 arg->inst_imm = cinfo->stack_align_amount;
1435 MONO_ADD_INS (cfg->cbb, arg);
1436 for (i = 0; i < cinfo->stack_align_amount; i += sizeof (mgreg_t)) {
1439 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1443 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1444 if (cinfo->ret.storage == ArgValuetypeInReg) {
1446 * Tell the JIT to use a more efficient calling convention: call using
1447 * OP_CALL, compute the result location after the call, and save the
1450 call->vret_in_reg = TRUE;
1452 NULLIFY_INS (call->vret_var);
1456 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1458 /* Handle the case where there are no implicit arguments */
1459 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1460 emit_sig_cookie (cfg, call, cinfo);
1462 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1465 /* Arguments are pushed in the reverse order */
1466 for (i = n - 1; i >= 0; i --) {
1467 ArgInfo *ainfo = cinfo->args + i;
1468 MonoType *orig_type, *t;
1471 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1472 /* Push the vret arg before the first argument */
1474 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1475 vtarg->type = STACK_MP;
1476 vtarg->sreg1 = call->vret_var->dreg;
1477 MONO_ADD_INS (cfg->cbb, vtarg);
1479 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1482 if (i >= sig->hasthis)
1483 t = sig->params [i - sig->hasthis];
1485 t = &mono_defaults.int_class->byval_arg;
1487 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1489 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1491 in = call->args [i];
1492 arg->cil_code = in->cil_code;
1493 arg->sreg1 = in->dreg;
1494 arg->type = in->type;
1496 g_assert (in->dreg != -1);
1498 if (ainfo->storage == ArgGSharedVt) {
1499 arg->opcode = OP_OUTARG_VT;
1500 arg->sreg1 = in->dreg;
1501 arg->klass = in->klass;
1502 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1503 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1505 MONO_ADD_INS (cfg->cbb, arg);
1506 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1510 g_assert (in->klass);
1512 if (t->type == MONO_TYPE_TYPEDBYREF) {
1513 size = sizeof (MonoTypedRef);
1514 align = sizeof (gpointer);
1517 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1521 arg->opcode = OP_OUTARG_VT;
1522 arg->sreg1 = in->dreg;
1523 arg->klass = in->klass;
1524 arg->backend.size = size;
1525 arg->inst_p0 = call;
1526 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1527 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1529 MONO_ADD_INS (cfg->cbb, arg);
1530 if (ainfo->storage != ArgValuetypeInReg) {
1532 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1538 switch (ainfo->storage) {
1540 arg->opcode = OP_X86_PUSH;
1542 if (t->type == MONO_TYPE_R4) {
1543 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1544 arg->opcode = OP_STORER4_MEMBASE_REG;
1545 arg->inst_destbasereg = X86_ESP;
1546 arg->inst_offset = 0;
1548 } else if (t->type == MONO_TYPE_R8) {
1549 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1550 arg->opcode = OP_STORER8_MEMBASE_REG;
1551 arg->inst_destbasereg = X86_ESP;
1552 arg->inst_offset = 0;
1554 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1556 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1562 arg->opcode = OP_MOVE;
1563 arg->dreg = ainfo->reg;
1567 g_assert_not_reached ();
1570 MONO_ADD_INS (cfg->cbb, arg);
1572 sp_offset += argsize;
1574 if (cfg->compute_gc_maps) {
1576 /* FIXME: The == STACK_OBJ check might be fragile ? */
1577 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1579 if (call->need_unbox_trampoline)
1580 /* The unbox trampoline transforms this into a managed pointer */
1581 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.int_class->this_arg);
1583 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.object_class->byval_arg);
1585 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1589 for (j = 0; j < argsize; j += 4)
1590 emit_gc_param_slot_def (cfg, sp_offset - j, NULL);
1595 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1596 /* Emit the signature cookie just before the implicit arguments */
1597 emit_sig_cookie (cfg, call, cinfo);
1599 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1603 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1606 if (cinfo->ret.storage == ArgValuetypeInReg) {
1609 else if (cinfo->ret.storage == ArgInIReg) {
1611 /* The return address is passed in a register */
1612 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1613 vtarg->sreg1 = call->inst.dreg;
1614 vtarg->dreg = mono_alloc_ireg (cfg);
1615 MONO_ADD_INS (cfg->cbb, vtarg);
1617 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1618 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1620 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1621 vtarg->type = STACK_MP;
1622 vtarg->sreg1 = call->vret_var->dreg;
1623 MONO_ADD_INS (cfg->cbb, vtarg);
1625 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1628 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1629 if (cinfo->ret.storage != ArgValuetypeInReg)
1630 cinfo->stack_usage -= 4;
1633 call->stack_usage = cinfo->stack_usage;
1634 call->stack_align_amount = cinfo->stack_align_amount;
1635 cfg->arch.param_area_size = MAX (cfg->arch.param_area_size, sp_offset);
1639 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1641 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1642 ArgInfo *ainfo = ins->inst_p1;
1644 int size = ins->backend.size;
1646 if (ainfo->storage == ArgValuetypeInReg) {
1647 int dreg = mono_alloc_ireg (cfg);
1650 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1653 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1656 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1660 g_assert_not_reached ();
1662 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1665 if (cfg->gsharedvt && mini_is_gsharedvt_klass (cfg, ins->klass)) {
1667 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1668 arg->sreg1 = src->dreg;
1669 MONO_ADD_INS (cfg->cbb, arg);
1670 } else if (size <= 4) {
1671 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1672 arg->sreg1 = src->dreg;
1674 MONO_ADD_INS (cfg->cbb, arg);
1675 } else if (size <= 20) {
1676 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1677 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1679 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1680 arg->inst_basereg = src->dreg;
1681 arg->inst_offset = 0;
1682 arg->inst_imm = size;
1684 MONO_ADD_INS (cfg->cbb, arg);
1690 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1692 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1695 if (ret->type == MONO_TYPE_R4) {
1696 if (COMPILE_LLVM (cfg))
1697 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1700 } else if (ret->type == MONO_TYPE_R8) {
1701 if (COMPILE_LLVM (cfg))
1702 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1705 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1706 if (COMPILE_LLVM (cfg))
1707 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1709 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1710 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1716 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1720 * Allow tracing to work with this interface (with an optional argument)
1723 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1727 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1728 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1730 /* if some args are passed in registers, we need to save them here */
1731 x86_push_reg (code, X86_EBP);
1733 if (cfg->compile_aot) {
1734 x86_push_imm (code, cfg->method);
1735 x86_mov_reg_imm (code, X86_EAX, func);
1736 x86_call_reg (code, X86_EAX);
1738 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1739 x86_push_imm (code, cfg->method);
1740 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1741 x86_call_code (code, 0);
1743 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1757 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1760 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1761 MonoMethod *method = cfg->method;
1762 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1764 switch (ret_type->type) {
1765 case MONO_TYPE_VOID:
1766 /* special case string .ctor icall */
1767 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1768 save_mode = SAVE_EAX;
1769 stack_usage = enable_arguments ? 8 : 4;
1771 save_mode = SAVE_NONE;
1775 save_mode = SAVE_EAX_EDX;
1776 stack_usage = enable_arguments ? 16 : 8;
1780 save_mode = SAVE_FP;
1781 stack_usage = enable_arguments ? 16 : 8;
1783 case MONO_TYPE_GENERICINST:
1784 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1785 save_mode = SAVE_EAX;
1786 stack_usage = enable_arguments ? 8 : 4;
1790 case MONO_TYPE_VALUETYPE:
1791 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1792 save_mode = SAVE_STRUCT;
1793 stack_usage = enable_arguments ? 4 : 0;
1796 save_mode = SAVE_EAX;
1797 stack_usage = enable_arguments ? 8 : 4;
1801 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1803 switch (save_mode) {
1805 x86_push_reg (code, X86_EDX);
1806 x86_push_reg (code, X86_EAX);
1807 if (enable_arguments) {
1808 x86_push_reg (code, X86_EDX);
1809 x86_push_reg (code, X86_EAX);
1814 x86_push_reg (code, X86_EAX);
1815 if (enable_arguments) {
1816 x86_push_reg (code, X86_EAX);
1821 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1822 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1823 if (enable_arguments) {
1824 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1825 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1830 if (enable_arguments) {
1831 x86_push_membase (code, X86_EBP, 8);
1840 if (cfg->compile_aot) {
1841 x86_push_imm (code, method);
1842 x86_mov_reg_imm (code, X86_EAX, func);
1843 x86_call_reg (code, X86_EAX);
1845 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1846 x86_push_imm (code, method);
1847 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1848 x86_call_code (code, 0);
1851 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1853 switch (save_mode) {
1855 x86_pop_reg (code, X86_EAX);
1856 x86_pop_reg (code, X86_EDX);
1859 x86_pop_reg (code, X86_EAX);
1862 x86_fld_membase (code, X86_ESP, 0, TRUE);
1863 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1870 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1875 #define EMIT_COND_BRANCH(ins,cond,sign) \
1876 if (ins->inst_true_bb->native_offset) { \
1877 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1879 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1880 if ((cfg->opt & MONO_OPT_BRANCH) && \
1881 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1882 x86_branch8 (code, cond, 0, sign); \
1884 x86_branch32 (code, cond, 0, sign); \
1888 * Emit an exception if condition is fail and
1889 * if possible do a directly branch to target
1891 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1893 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1894 if (tins == NULL) { \
1895 mono_add_patch_info (cfg, code - cfg->native_code, \
1896 MONO_PATCH_INFO_EXC, exc_name); \
1897 x86_branch32 (code, cond, 0, signed); \
1899 EMIT_COND_BRANCH (tins, cond, signed); \
1903 #define EMIT_FPCOMPARE(code) do { \
1904 x86_fcompp (code); \
1905 x86_fnstsw (code); \
1910 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1912 gboolean needs_paddings = TRUE;
1914 MonoJumpInfo *jinfo = NULL;
1916 if (cfg->abs_patches) {
1917 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1918 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1919 needs_paddings = FALSE;
1922 if (cfg->compile_aot)
1923 needs_paddings = FALSE;
1924 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1925 This is required for code patching to be safe on SMP machines.
1927 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1928 #ifndef __native_client_codegen__
1929 if (needs_paddings && pad_size)
1930 x86_padding (code, 4 - pad_size);
1933 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1934 x86_call_code (code, 0);
1939 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1942 * mono_peephole_pass_1:
1944 * Perform peephole opts which should/can be performed before local regalloc
1947 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1951 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1952 MonoInst *last_ins = ins->prev;
1954 switch (ins->opcode) {
1957 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1959 * X86_LEA is like ADD, but doesn't have the
1960 * sreg1==dreg restriction.
1962 ins->opcode = OP_X86_LEA_MEMBASE;
1963 ins->inst_basereg = ins->sreg1;
1964 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1965 ins->opcode = OP_X86_INC_REG;
1969 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1970 ins->opcode = OP_X86_LEA_MEMBASE;
1971 ins->inst_basereg = ins->sreg1;
1972 ins->inst_imm = -ins->inst_imm;
1973 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1974 ins->opcode = OP_X86_DEC_REG;
1976 case OP_COMPARE_IMM:
1977 case OP_ICOMPARE_IMM:
1978 /* OP_COMPARE_IMM (reg, 0)
1980 * OP_X86_TEST_NULL (reg)
1983 ins->opcode = OP_X86_TEST_NULL;
1985 case OP_X86_COMPARE_MEMBASE_IMM:
1987 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1988 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1990 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1991 * OP_COMPARE_IMM reg, imm
1993 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1995 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1996 ins->inst_basereg == last_ins->inst_destbasereg &&
1997 ins->inst_offset == last_ins->inst_offset) {
1998 ins->opcode = OP_COMPARE_IMM;
1999 ins->sreg1 = last_ins->sreg1;
2001 /* check if we can remove cmp reg,0 with test null */
2003 ins->opcode = OP_X86_TEST_NULL;
2007 case OP_X86_PUSH_MEMBASE:
2008 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
2009 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2010 ins->inst_basereg == last_ins->inst_destbasereg &&
2011 ins->inst_offset == last_ins->inst_offset) {
2012 ins->opcode = OP_X86_PUSH;
2013 ins->sreg1 = last_ins->sreg1;
2018 mono_peephole_ins (bb, ins);
2023 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2027 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2028 switch (ins->opcode) {
2030 /* reg = 0 -> XOR (reg, reg) */
2031 /* XOR sets cflags on x86, so we cant do it always */
2032 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2035 ins->opcode = OP_IXOR;
2036 ins->sreg1 = ins->dreg;
2037 ins->sreg2 = ins->dreg;
2040 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2041 * since it takes 3 bytes instead of 7.
2043 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2044 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2045 ins2->opcode = OP_STORE_MEMBASE_REG;
2046 ins2->sreg1 = ins->dreg;
2048 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2049 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2050 ins2->sreg1 = ins->dreg;
2052 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2053 /* Continue iteration */
2062 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2063 ins->opcode = OP_X86_INC_REG;
2067 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2068 ins->opcode = OP_X86_DEC_REG;
2072 mono_peephole_ins (bb, ins);
2077 * mono_arch_lowering_pass:
2079 * Converts complex opcodes into simpler ones so that each IR instruction
2080 * corresponds to one machine instruction.
2083 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2085 MonoInst *ins, *next;
2088 * FIXME: Need to add more instructions, but the current machine
2089 * description can't model some parts of the composite instructions like
2092 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2093 switch (ins->opcode) {
2096 case OP_IDIV_UN_IMM:
2097 case OP_IREM_UN_IMM:
2099 * Keep the cases where we could generated optimized code, otherwise convert
2100 * to the non-imm variant.
2102 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2104 mono_decompose_op_imm (cfg, bb, ins);
2111 bb->max_vreg = cfg->next_vreg;
2115 branch_cc_table [] = {
2116 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2117 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2118 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2121 /* Maps CMP_... constants to X86_CC_... constants */
2124 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2125 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2129 cc_signed_table [] = {
2130 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2131 FALSE, FALSE, FALSE, FALSE
2134 static unsigned char*
2135 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2137 #define XMM_TEMP_REG 0
2138 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2139 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2140 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2141 /* optimize by assigning a local var for this use so we avoid
2142 * the stack manipulations */
2143 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2144 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2145 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2146 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2147 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2149 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2151 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2154 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2155 x86_fnstcw_membase(code, X86_ESP, 0);
2156 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2157 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2158 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2159 x86_fldcw_membase (code, X86_ESP, 2);
2161 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2162 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2163 x86_pop_reg (code, dreg);
2164 /* FIXME: need the high register
2165 * x86_pop_reg (code, dreg_high);
2168 x86_push_reg (code, X86_EAX); // SP = SP - 4
2169 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2170 x86_pop_reg (code, dreg);
2172 x86_fldcw_membase (code, X86_ESP, 0);
2173 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2176 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2178 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2182 static unsigned char*
2183 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2185 int sreg = tree->sreg1;
2186 int need_touch = FALSE;
2188 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2197 * If requested stack size is larger than one page,
2198 * perform stack-touch operation
2201 * Generate stack probe code.
2202 * Under Windows, it is necessary to allocate one page at a time,
2203 * "touching" stack after each successful sub-allocation. This is
2204 * because of the way stack growth is implemented - there is a
2205 * guard page before the lowest stack page that is currently commited.
2206 * Stack normally grows sequentially so OS traps access to the
2207 * guard page and commits more pages when needed.
2209 x86_test_reg_imm (code, sreg, ~0xFFF);
2210 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2212 br[2] = code; /* loop */
2213 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2214 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2217 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2218 * that follows only initializes the last part of the area.
2220 /* Same as the init code below with size==0x1000 */
2221 if (tree->flags & MONO_INST_INIT) {
2222 x86_push_reg (code, X86_EAX);
2223 x86_push_reg (code, X86_ECX);
2224 x86_push_reg (code, X86_EDI);
2225 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2226 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2227 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2229 x86_prefix (code, X86_REP_PREFIX);
2231 x86_pop_reg (code, X86_EDI);
2232 x86_pop_reg (code, X86_ECX);
2233 x86_pop_reg (code, X86_EAX);
2236 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2237 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2238 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2239 x86_patch (br[3], br[2]);
2240 x86_test_reg_reg (code, sreg, sreg);
2241 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2242 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2244 br[1] = code; x86_jump8 (code, 0);
2246 x86_patch (br[0], code);
2247 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2248 x86_patch (br[1], code);
2249 x86_patch (br[4], code);
2252 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2254 if (tree->flags & MONO_INST_INIT) {
2256 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2257 x86_push_reg (code, X86_EAX);
2260 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2261 x86_push_reg (code, X86_ECX);
2264 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2265 x86_push_reg (code, X86_EDI);
2269 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2270 if (sreg != X86_ECX)
2271 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2272 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2274 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2276 x86_prefix (code, X86_REP_PREFIX);
2279 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2280 x86_pop_reg (code, X86_EDI);
2281 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2282 x86_pop_reg (code, X86_ECX);
2283 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2284 x86_pop_reg (code, X86_EAX);
2291 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2293 /* Move return value to the target register */
2294 switch (ins->opcode) {
2297 case OP_CALL_MEMBASE:
2298 if (ins->dreg != X86_EAX)
2299 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2309 static int tls_gs_offset;
2313 mono_x86_have_tls_get (void)
2316 static gboolean have_tls_get = FALSE;
2317 static gboolean inited = FALSE;
2321 return have_tls_get;
2323 ins = (guint32*)pthread_getspecific;
2325 * We're looking for these two instructions:
2327 * mov 0x4(%esp),%eax
2328 * mov %gs:[offset](,%eax,4),%eax
2330 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2331 tls_gs_offset = ins [2];
2335 return have_tls_get;
2336 #elif defined(TARGET_ANDROID)
2344 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2346 #if defined(__APPLE__)
2347 x86_prefix (code, X86_GS_PREFIX);
2348 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2349 #elif defined(TARGET_WIN32)
2350 g_assert_not_reached ();
2352 x86_prefix (code, X86_GS_PREFIX);
2353 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2359 * mono_x86_emit_tls_get:
2360 * @code: buffer to store code to
2361 * @dreg: hard register where to place the result
2362 * @tls_offset: offset info
2364 * mono_x86_emit_tls_get emits in @code the native code that puts in
2365 * the dreg register the item in the thread local storage identified
2368 * Returns: a pointer to the end of the stored code
2371 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2373 #if defined(__APPLE__)
2374 x86_prefix (code, X86_GS_PREFIX);
2375 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2376 #elif defined(TARGET_WIN32)
2378 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2379 * Journal and/or a disassembly of the TlsGet () function.
2381 g_assert (tls_offset < 64);
2382 x86_prefix (code, X86_FS_PREFIX);
2383 x86_mov_reg_mem (code, dreg, 0x18, 4);
2384 /* Dunno what this does but TlsGetValue () contains it */
2385 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2386 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2388 if (optimize_for_xen) {
2389 x86_prefix (code, X86_GS_PREFIX);
2390 x86_mov_reg_mem (code, dreg, 0, 4);
2391 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2393 x86_prefix (code, X86_GS_PREFIX);
2394 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2401 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2403 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2404 #if defined(__APPLE__) || defined(__linux__)
2405 if (dreg != offset_reg)
2406 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2407 x86_prefix (code, X86_GS_PREFIX);
2408 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2410 g_assert_not_reached ();
2416 mono_x86_emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2418 return emit_tls_get_reg (code, dreg, offset_reg);
2422 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2424 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2426 g_assert_not_reached ();
2427 #elif defined(__APPLE__) || defined(__linux__)
2428 x86_prefix (code, X86_GS_PREFIX);
2429 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2431 g_assert_not_reached ();
2437 * mono_arch_translate_tls_offset:
2439 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2442 mono_arch_translate_tls_offset (int offset)
2445 return tls_gs_offset + (offset * 4);
2454 * Emit code to initialize an LMF structure at LMF_OFFSET.
2457 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2459 /* save all caller saved regs */
2460 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2461 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx));
2462 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2463 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi));
2464 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2465 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi));
2466 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2468 /* save the current IP */
2469 if (cfg->compile_aot) {
2470 /* This pushes the current ip */
2471 x86_call_imm (code, 0);
2472 x86_pop_reg (code, X86_EAX);
2474 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2475 x86_mov_reg_imm (code, X86_EAX, 0);
2477 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2479 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2480 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2481 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2482 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2483 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2484 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2485 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2486 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2487 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2495 * Emit code to push an LMF structure on the LMF stack.
2498 emit_push_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
2500 /* get the address of lmf for the current thread */
2502 * This is performance critical so we try to use some tricks to make
2505 gboolean have_fastpath = FALSE;
2508 if (jit_tls_offset != -1) {
2509 code = mono_x86_emit_tls_get (code, X86_EAX, jit_tls_offset);
2510 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
2511 have_fastpath = TRUE;
2514 if (!cfg->compile_aot && lmf_addr_tls_offset != -1) {
2515 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
2516 have_fastpath = TRUE;
2519 if (!have_fastpath) {
2520 if (cfg->compile_aot)
2521 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
2522 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
2526 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), X86_EAX, sizeof (mgreg_t));
2527 /* save previous_lmf */
2528 x86_mov_reg_membase (code, X86_ECX, X86_EAX, 0, sizeof (mgreg_t));
2529 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), X86_ECX, sizeof (mgreg_t));
2531 x86_lea_membase (code, X86_ECX, cfg->frame_reg, lmf_offset);
2532 x86_mov_membase_reg (code, X86_EAX, 0, X86_ECX, sizeof (mgreg_t));
2540 * Emit code to pop an LMF structure from the LMF stack.
2541 * Preserves the return registers.
2544 emit_pop_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
2546 MonoMethodSignature *sig = mono_method_signature (cfg->method);
2549 /* Find a spare register */
2550 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
2553 prev_lmf_reg = X86_EDI;
2554 cfg->used_int_regs |= (1 << X86_EDI);
2557 prev_lmf_reg = X86_EDX;
2561 /* reg = previous_lmf */
2562 x86_mov_reg_membase (code, prev_lmf_reg, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
2565 x86_mov_reg_membase (code, X86_ECX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
2567 /* *(lmf) = previous_lmf */
2568 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
2573 #define REAL_PRINT_REG(text,reg) \
2574 mono_assert (reg >= 0); \
2575 x86_push_reg (code, X86_EAX); \
2576 x86_push_reg (code, X86_EDX); \
2577 x86_push_reg (code, X86_ECX); \
2578 x86_push_reg (code, reg); \
2579 x86_push_imm (code, reg); \
2580 x86_push_imm (code, text " %d %p\n"); \
2581 x86_mov_reg_imm (code, X86_EAX, printf); \
2582 x86_call_reg (code, X86_EAX); \
2583 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2584 x86_pop_reg (code, X86_ECX); \
2585 x86_pop_reg (code, X86_EDX); \
2586 x86_pop_reg (code, X86_EAX);
2588 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2589 #ifdef __native__client_codegen__
2590 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2593 /* benchmark and set based on cpu */
2594 #define LOOP_ALIGNMENT 8
2595 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2599 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2604 guint8 *code = cfg->native_code + cfg->code_len;
2607 if (cfg->opt & MONO_OPT_LOOP) {
2608 int pad, align = LOOP_ALIGNMENT;
2609 /* set alignment depending on cpu */
2610 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2612 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2613 x86_padding (code, pad);
2614 cfg->code_len += pad;
2615 bb->native_offset = cfg->code_len;
2618 #ifdef __native_client_codegen__
2620 /* For Native Client, all indirect call/jump targets must be */
2621 /* 32-byte aligned. Exception handler blocks are jumped to */
2622 /* indirectly as well. */
2623 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2624 (bb->flags & BB_EXCEPTION_HANDLER);
2626 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2627 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2628 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2629 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2630 cfg->code_len += pad;
2631 bb->native_offset = cfg->code_len;
2634 #endif /* __native_client_codegen__ */
2635 if (cfg->verbose_level > 2)
2636 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2638 cpos = bb->max_offset;
2640 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2641 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2642 g_assert (!cfg->compile_aot);
2645 cov->data [bb->dfn].cil_code = bb->cil_code;
2646 /* this is not thread save, but good enough */
2647 x86_inc_mem (code, &cov->data [bb->dfn].count);
2650 offset = code - cfg->native_code;
2652 mono_debug_open_block (cfg, bb, offset);
2654 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2655 x86_breakpoint (code);
2657 MONO_BB_FOR_EACH_INS (bb, ins) {
2658 offset = code - cfg->native_code;
2660 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2662 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2664 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2665 cfg->code_size *= 2;
2666 cfg->native_code = mono_realloc_native_code(cfg);
2667 code = cfg->native_code + offset;
2668 cfg->stat_code_reallocs++;
2671 if (cfg->debug_info)
2672 mono_debug_record_line_number (cfg, ins, offset);
2674 switch (ins->opcode) {
2676 x86_mul_reg (code, ins->sreg2, TRUE);
2679 x86_mul_reg (code, ins->sreg2, FALSE);
2681 case OP_X86_SETEQ_MEMBASE:
2682 case OP_X86_SETNE_MEMBASE:
2683 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2684 ins->inst_basereg, ins->inst_offset, TRUE);
2686 case OP_STOREI1_MEMBASE_IMM:
2687 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2689 case OP_STOREI2_MEMBASE_IMM:
2690 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2692 case OP_STORE_MEMBASE_IMM:
2693 case OP_STOREI4_MEMBASE_IMM:
2694 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2696 case OP_STOREI1_MEMBASE_REG:
2697 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2699 case OP_STOREI2_MEMBASE_REG:
2700 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2702 case OP_STORE_MEMBASE_REG:
2703 case OP_STOREI4_MEMBASE_REG:
2704 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2706 case OP_STORE_MEM_IMM:
2707 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2710 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2714 /* These are created by the cprop pass so they use inst_imm as the source */
2715 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2718 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2721 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2723 case OP_LOAD_MEMBASE:
2724 case OP_LOADI4_MEMBASE:
2725 case OP_LOADU4_MEMBASE:
2726 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2728 case OP_LOADU1_MEMBASE:
2729 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2731 case OP_LOADI1_MEMBASE:
2732 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2734 case OP_LOADU2_MEMBASE:
2735 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2737 case OP_LOADI2_MEMBASE:
2738 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2740 case OP_ICONV_TO_I1:
2742 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2744 case OP_ICONV_TO_I2:
2746 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2748 case OP_ICONV_TO_U1:
2749 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2751 case OP_ICONV_TO_U2:
2752 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2756 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2758 case OP_COMPARE_IMM:
2759 case OP_ICOMPARE_IMM:
2760 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2762 case OP_X86_COMPARE_MEMBASE_REG:
2763 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2765 case OP_X86_COMPARE_MEMBASE_IMM:
2766 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2768 case OP_X86_COMPARE_MEMBASE8_IMM:
2769 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2771 case OP_X86_COMPARE_REG_MEMBASE:
2772 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2774 case OP_X86_COMPARE_MEM_IMM:
2775 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2777 case OP_X86_TEST_NULL:
2778 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2780 case OP_X86_ADD_MEMBASE_IMM:
2781 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2783 case OP_X86_ADD_REG_MEMBASE:
2784 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2786 case OP_X86_SUB_MEMBASE_IMM:
2787 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2789 case OP_X86_SUB_REG_MEMBASE:
2790 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2792 case OP_X86_AND_MEMBASE_IMM:
2793 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2795 case OP_X86_OR_MEMBASE_IMM:
2796 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2798 case OP_X86_XOR_MEMBASE_IMM:
2799 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2801 case OP_X86_ADD_MEMBASE_REG:
2802 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2804 case OP_X86_SUB_MEMBASE_REG:
2805 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2807 case OP_X86_AND_MEMBASE_REG:
2808 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2810 case OP_X86_OR_MEMBASE_REG:
2811 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2813 case OP_X86_XOR_MEMBASE_REG:
2814 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2816 case OP_X86_INC_MEMBASE:
2817 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2819 case OP_X86_INC_REG:
2820 x86_inc_reg (code, ins->dreg);
2822 case OP_X86_DEC_MEMBASE:
2823 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2825 case OP_X86_DEC_REG:
2826 x86_dec_reg (code, ins->dreg);
2828 case OP_X86_MUL_REG_MEMBASE:
2829 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2831 case OP_X86_AND_REG_MEMBASE:
2832 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2834 case OP_X86_OR_REG_MEMBASE:
2835 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2837 case OP_X86_XOR_REG_MEMBASE:
2838 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2841 x86_breakpoint (code);
2843 case OP_RELAXED_NOP:
2844 x86_prefix (code, X86_REP_PREFIX);
2852 case OP_DUMMY_STORE:
2853 case OP_NOT_REACHED:
2856 case OP_SEQ_POINT: {
2859 if (cfg->compile_aot)
2863 * Read from the single stepping trigger page. This will cause a
2864 * SIGSEGV when single stepping is enabled.
2865 * We do this _before_ the breakpoint, so single stepping after
2866 * a breakpoint is hit will step to the next IL offset.
2868 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2869 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2871 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2874 * A placeholder for a possible breakpoint inserted by
2875 * mono_arch_set_breakpoint ().
2877 for (i = 0; i < 6; ++i)
2880 * Add an additional nop so skipping the bp doesn't cause the ip to point
2881 * to another IL offset.
2889 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2893 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2898 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2902 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2907 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2911 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2916 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2920 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2923 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2927 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2931 #if defined( __native_client_codegen__ )
2932 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2933 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2936 * The code is the same for div/rem, the allocator will allocate dreg
2937 * to RAX/RDX as appropriate.
2939 if (ins->sreg2 == X86_EDX) {
2940 /* cdq clobbers this */
2941 x86_push_reg (code, ins->sreg2);
2943 x86_div_membase (code, X86_ESP, 0, TRUE);
2944 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2947 x86_div_reg (code, ins->sreg2, TRUE);
2952 #if defined( __native_client_codegen__ )
2953 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2954 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2956 if (ins->sreg2 == X86_EDX) {
2957 x86_push_reg (code, ins->sreg2);
2958 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2959 x86_div_membase (code, X86_ESP, 0, FALSE);
2960 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2962 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2963 x86_div_reg (code, ins->sreg2, FALSE);
2967 #if defined( __native_client_codegen__ )
2968 if (ins->inst_imm == 0) {
2969 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2970 x86_jump32 (code, 0);
2974 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2976 x86_div_reg (code, ins->sreg2, TRUE);
2979 int power = mono_is_power_of_two (ins->inst_imm);
2981 g_assert (ins->sreg1 == X86_EAX);
2982 g_assert (ins->dreg == X86_EAX);
2983 g_assert (power >= 0);
2986 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2988 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2990 * If the divident is >= 0, this does not nothing. If it is positive, it
2991 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2993 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2994 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2995 } else if (power == 0) {
2996 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2998 /* Based on gcc code */
3000 /* Add compensation for negative dividents */
3002 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
3003 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
3004 /* Compute remainder */
3005 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
3006 /* Remove compensation */
3007 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
3012 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3016 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3019 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3023 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3026 g_assert (ins->sreg2 == X86_ECX);
3027 x86_shift_reg (code, X86_SHL, ins->dreg);
3030 g_assert (ins->sreg2 == X86_ECX);
3031 x86_shift_reg (code, X86_SAR, ins->dreg);
3035 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3038 case OP_ISHR_UN_IMM:
3039 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3042 g_assert (ins->sreg2 == X86_ECX);
3043 x86_shift_reg (code, X86_SHR, ins->dreg);
3047 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3050 guint8 *jump_to_end;
3052 /* handle shifts below 32 bits */
3053 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
3054 x86_shift_reg (code, X86_SHL, ins->sreg1);
3056 x86_test_reg_imm (code, X86_ECX, 32);
3057 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3059 /* handle shift over 32 bit */
3060 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3061 x86_clear_reg (code, ins->sreg1);
3063 x86_patch (jump_to_end, code);
3067 guint8 *jump_to_end;
3069 /* handle shifts below 32 bits */
3070 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3071 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
3073 x86_test_reg_imm (code, X86_ECX, 32);
3074 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3076 /* handle shifts over 31 bits */
3077 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3078 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
3080 x86_patch (jump_to_end, code);
3084 guint8 *jump_to_end;
3086 /* handle shifts below 32 bits */
3087 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3088 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
3090 x86_test_reg_imm (code, X86_ECX, 32);
3091 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3093 /* handle shifts over 31 bits */
3094 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3095 x86_clear_reg (code, ins->backend.reg3);
3097 x86_patch (jump_to_end, code);
3101 if (ins->inst_imm >= 32) {
3102 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3103 x86_clear_reg (code, ins->sreg1);
3104 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
3106 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
3107 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
3111 if (ins->inst_imm >= 32) {
3112 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3113 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
3114 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
3116 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3117 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3120 case OP_LSHR_UN_IMM:
3121 if (ins->inst_imm >= 32) {
3122 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3123 x86_clear_reg (code, ins->backend.reg3);
3124 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3126 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3127 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3131 x86_not_reg (code, ins->sreg1);
3134 x86_neg_reg (code, ins->sreg1);
3138 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3142 switch (ins->inst_imm) {
3146 if (ins->dreg != ins->sreg1)
3147 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3148 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3151 /* LEA r1, [r2 + r2*2] */
3152 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3155 /* LEA r1, [r2 + r2*4] */
3156 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3159 /* LEA r1, [r2 + r2*2] */
3161 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3162 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3165 /* LEA r1, [r2 + r2*8] */
3166 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3169 /* LEA r1, [r2 + r2*4] */
3171 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3172 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3175 /* LEA r1, [r2 + r2*2] */
3177 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3178 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3181 /* LEA r1, [r2 + r2*4] */
3182 /* LEA r1, [r1 + r1*4] */
3183 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3184 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3187 /* LEA r1, [r2 + r2*4] */
3189 /* LEA r1, [r1 + r1*4] */
3190 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3191 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3192 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3195 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3200 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3201 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3203 case OP_IMUL_OVF_UN: {
3204 /* the mul operation and the exception check should most likely be split */
3205 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3206 /*g_assert (ins->sreg2 == X86_EAX);
3207 g_assert (ins->dreg == X86_EAX);*/
3208 if (ins->sreg2 == X86_EAX) {
3209 non_eax_reg = ins->sreg1;
3210 } else if (ins->sreg1 == X86_EAX) {
3211 non_eax_reg = ins->sreg2;
3213 /* no need to save since we're going to store to it anyway */
3214 if (ins->dreg != X86_EAX) {
3216 x86_push_reg (code, X86_EAX);
3218 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3219 non_eax_reg = ins->sreg2;
3221 if (ins->dreg == X86_EDX) {
3224 x86_push_reg (code, X86_EAX);
3226 } else if (ins->dreg != X86_EAX) {
3228 x86_push_reg (code, X86_EDX);
3230 x86_mul_reg (code, non_eax_reg, FALSE);
3231 /* save before the check since pop and mov don't change the flags */
3232 if (ins->dreg != X86_EAX)
3233 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3235 x86_pop_reg (code, X86_EDX);
3237 x86_pop_reg (code, X86_EAX);
3238 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3242 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3245 g_assert_not_reached ();
3246 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3247 x86_mov_reg_imm (code, ins->dreg, 0);
3250 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3251 x86_mov_reg_imm (code, ins->dreg, 0);
3253 case OP_LOAD_GOTADDR:
3254 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3255 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3258 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3259 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3261 case OP_X86_PUSH_GOT_ENTRY:
3262 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3263 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3266 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3269 MonoCallInst *call = (MonoCallInst*)ins;
3272 ins->flags |= MONO_INST_GC_CALLSITE;
3273 ins->backend.pc_offset = code - cfg->native_code;
3275 /* FIXME: no tracing support... */
3276 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3277 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3278 /* reset offset to make max_len work */
3279 offset = code - cfg->native_code;
3281 g_assert (!cfg->method->save_lmf);
3283 /* restore callee saved registers */
3284 for (i = 0; i < X86_NREG; ++i)
3285 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3287 if (cfg->used_int_regs & (1 << X86_ESI)) {
3288 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3291 if (cfg->used_int_regs & (1 << X86_EDI)) {
3292 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3295 if (cfg->used_int_regs & (1 << X86_EBX)) {
3296 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3300 /* Copy arguments on the stack to our argument area */
3301 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3302 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3303 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3306 /* restore ESP/EBP */
3308 offset = code - cfg->native_code;
3309 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3310 x86_jump32 (code, 0);
3312 ins->flags |= MONO_INST_GC_CALLSITE;
3313 cfg->disable_aot = TRUE;
3317 /* ensure ins->sreg1 is not NULL
3318 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3319 * cmp DWORD PTR [eax], 0
3321 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3324 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3325 x86_push_reg (code, hreg);
3326 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3327 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3328 x86_pop_reg (code, hreg);
3337 call = (MonoCallInst*)ins;
3338 if (ins->flags & MONO_INST_HAS_METHOD)
3339 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3341 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3342 ins->flags |= MONO_INST_GC_CALLSITE;
3343 ins->backend.pc_offset = code - cfg->native_code;
3344 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3345 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
3346 * bytes to pop, we want to use pops. GCC does this (note it won't happen
3347 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
3348 * smart enough to do that optimization yet
3350 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
3351 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
3352 * (most likely from locality benefits). People with other processors should
3353 * check on theirs to see what happens.
3355 if (call->stack_usage == 4) {
3356 /* we want to use registers that won't get used soon, so use
3357 * ecx, as eax will get allocated first. edx is used by long calls,
3358 * so we can't use that.
3361 x86_pop_reg (code, X86_ECX);
3363 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3366 code = emit_move_return_value (cfg, ins, code);
3372 case OP_VOIDCALL_REG:
3374 call = (MonoCallInst*)ins;
3375 x86_call_reg (code, ins->sreg1);
3376 ins->flags |= MONO_INST_GC_CALLSITE;
3377 ins->backend.pc_offset = code - cfg->native_code;
3378 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3379 if (call->stack_usage == 4)
3380 x86_pop_reg (code, X86_ECX);
3382 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3384 code = emit_move_return_value (cfg, ins, code);
3386 case OP_FCALL_MEMBASE:
3387 case OP_LCALL_MEMBASE:
3388 case OP_VCALL_MEMBASE:
3389 case OP_VCALL2_MEMBASE:
3390 case OP_VOIDCALL_MEMBASE:
3391 case OP_CALL_MEMBASE:
3392 call = (MonoCallInst*)ins;
3394 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3395 ins->flags |= MONO_INST_GC_CALLSITE;
3396 ins->backend.pc_offset = code - cfg->native_code;
3397 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3398 if (call->stack_usage == 4)
3399 x86_pop_reg (code, X86_ECX);
3401 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3403 code = emit_move_return_value (cfg, ins, code);
3406 x86_push_reg (code, ins->sreg1);
3408 case OP_X86_PUSH_IMM:
3409 x86_push_imm (code, ins->inst_imm);
3411 case OP_X86_PUSH_MEMBASE:
3412 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
3414 case OP_X86_PUSH_OBJ:
3415 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
3416 x86_push_reg (code, X86_EDI);
3417 x86_push_reg (code, X86_ESI);
3418 x86_push_reg (code, X86_ECX);
3419 if (ins->inst_offset)
3420 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
3422 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
3423 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
3424 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
3426 x86_prefix (code, X86_REP_PREFIX);
3428 x86_pop_reg (code, X86_ECX);
3429 x86_pop_reg (code, X86_ESI);
3430 x86_pop_reg (code, X86_EDI);
3433 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3435 case OP_X86_LEA_MEMBASE:
3436 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3439 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3442 /* keep alignment */
3443 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3444 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3445 code = mono_emit_stack_alloc (code, ins);
3446 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3448 case OP_LOCALLOC_IMM: {
3449 guint32 size = ins->inst_imm;
3450 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3452 if (ins->flags & MONO_INST_INIT) {
3453 /* FIXME: Optimize this */
3454 x86_mov_reg_imm (code, ins->dreg, size);
3455 ins->sreg1 = ins->dreg;
3457 code = mono_emit_stack_alloc (code, ins);
3458 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3460 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3461 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3466 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3467 x86_push_reg (code, ins->sreg1);
3468 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3469 (gpointer)"mono_arch_throw_exception");
3470 ins->flags |= MONO_INST_GC_CALLSITE;
3471 ins->backend.pc_offset = code - cfg->native_code;
3475 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3476 x86_push_reg (code, ins->sreg1);
3477 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3478 (gpointer)"mono_arch_rethrow_exception");
3479 ins->flags |= MONO_INST_GC_CALLSITE;
3480 ins->backend.pc_offset = code - cfg->native_code;
3483 case OP_CALL_HANDLER:
3484 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3485 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3486 x86_call_imm (code, 0);
3487 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3488 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3490 case OP_START_HANDLER: {
3491 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3492 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3495 case OP_ENDFINALLY: {
3496 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3497 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3501 case OP_ENDFILTER: {
3502 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3503 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3504 /* The local allocator will put the result into EAX */
3510 ins->inst_c0 = code - cfg->native_code;
3513 if (ins->inst_target_bb->native_offset) {
3514 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3516 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3517 if ((cfg->opt & MONO_OPT_BRANCH) &&
3518 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3519 x86_jump8 (code, 0);
3521 x86_jump32 (code, 0);
3525 x86_jump_reg (code, ins->sreg1);
3544 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3545 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3547 case OP_COND_EXC_EQ:
3548 case OP_COND_EXC_NE_UN:
3549 case OP_COND_EXC_LT:
3550 case OP_COND_EXC_LT_UN:
3551 case OP_COND_EXC_GT:
3552 case OP_COND_EXC_GT_UN:
3553 case OP_COND_EXC_GE:
3554 case OP_COND_EXC_GE_UN:
3555 case OP_COND_EXC_LE:
3556 case OP_COND_EXC_LE_UN:
3557 case OP_COND_EXC_IEQ:
3558 case OP_COND_EXC_INE_UN:
3559 case OP_COND_EXC_ILT:
3560 case OP_COND_EXC_ILT_UN:
3561 case OP_COND_EXC_IGT:
3562 case OP_COND_EXC_IGT_UN:
3563 case OP_COND_EXC_IGE:
3564 case OP_COND_EXC_IGE_UN:
3565 case OP_COND_EXC_ILE:
3566 case OP_COND_EXC_ILE_UN:
3567 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3569 case OP_COND_EXC_OV:
3570 case OP_COND_EXC_NO:
3572 case OP_COND_EXC_NC:
3573 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3575 case OP_COND_EXC_IOV:
3576 case OP_COND_EXC_INO:
3577 case OP_COND_EXC_IC:
3578 case OP_COND_EXC_INC:
3579 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3591 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3599 case OP_CMOV_INE_UN:
3600 case OP_CMOV_IGE_UN:
3601 case OP_CMOV_IGT_UN:
3602 case OP_CMOV_ILE_UN:
3603 case OP_CMOV_ILT_UN:
3604 g_assert (ins->dreg == ins->sreg1);
3605 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3608 /* floating point opcodes */
3610 double d = *(double *)ins->inst_p0;
3612 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3614 } else if (d == 1.0) {
3617 if (cfg->compile_aot) {
3618 guint32 *val = (guint32*)&d;
3619 x86_push_imm (code, val [1]);
3620 x86_push_imm (code, val [0]);
3621 x86_fld_membase (code, X86_ESP, 0, TRUE);
3622 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3625 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3626 x86_fld (code, NULL, TRUE);
3632 float f = *(float *)ins->inst_p0;
3634 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3636 } else if (f == 1.0) {
3639 if (cfg->compile_aot) {
3640 guint32 val = *(guint32*)&f;
3641 x86_push_imm (code, val);
3642 x86_fld_membase (code, X86_ESP, 0, FALSE);
3643 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3646 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3647 x86_fld (code, NULL, FALSE);
3652 case OP_STORER8_MEMBASE_REG:
3653 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3655 case OP_LOADR8_MEMBASE:
3656 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3658 case OP_STORER4_MEMBASE_REG:
3659 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3661 case OP_LOADR4_MEMBASE:
3662 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3664 case OP_ICONV_TO_R4:
3665 x86_push_reg (code, ins->sreg1);
3666 x86_fild_membase (code, X86_ESP, 0, FALSE);
3667 /* Change precision */
3668 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3669 x86_fld_membase (code, X86_ESP, 0, FALSE);
3670 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3672 case OP_ICONV_TO_R8:
3673 x86_push_reg (code, ins->sreg1);
3674 x86_fild_membase (code, X86_ESP, 0, FALSE);
3675 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3677 case OP_ICONV_TO_R_UN:
3678 x86_push_imm (code, 0);
3679 x86_push_reg (code, ins->sreg1);
3680 x86_fild_membase (code, X86_ESP, 0, TRUE);
3681 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3683 case OP_X86_FP_LOAD_I8:
3684 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3686 case OP_X86_FP_LOAD_I4:
3687 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3689 case OP_FCONV_TO_R4:
3690 /* Change precision */
3691 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3692 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3693 x86_fld_membase (code, X86_ESP, 0, FALSE);
3694 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3696 case OP_FCONV_TO_I1:
3697 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3699 case OP_FCONV_TO_U1:
3700 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3702 case OP_FCONV_TO_I2:
3703 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3705 case OP_FCONV_TO_U2:
3706 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3708 case OP_FCONV_TO_I4:
3710 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3712 case OP_FCONV_TO_I8:
3713 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3714 x86_fnstcw_membase(code, X86_ESP, 0);
3715 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3716 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3717 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3718 x86_fldcw_membase (code, X86_ESP, 2);
3719 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3720 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3721 x86_pop_reg (code, ins->dreg);
3722 x86_pop_reg (code, ins->backend.reg3);
3723 x86_fldcw_membase (code, X86_ESP, 0);
3724 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3726 case OP_LCONV_TO_R8_2:
3727 x86_push_reg (code, ins->sreg2);
3728 x86_push_reg (code, ins->sreg1);
3729 x86_fild_membase (code, X86_ESP, 0, TRUE);
3730 /* Change precision */
3731 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3732 x86_fld_membase (code, X86_ESP, 0, TRUE);
3733 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3735 case OP_LCONV_TO_R4_2:
3736 x86_push_reg (code, ins->sreg2);
3737 x86_push_reg (code, ins->sreg1);
3738 x86_fild_membase (code, X86_ESP, 0, TRUE);
3739 /* Change precision */
3740 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3741 x86_fld_membase (code, X86_ESP, 0, FALSE);
3742 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3744 case OP_LCONV_TO_R_UN_2: {
3745 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3748 /* load 64bit integer to FP stack */
3749 x86_push_reg (code, ins->sreg2);
3750 x86_push_reg (code, ins->sreg1);
3751 x86_fild_membase (code, X86_ESP, 0, TRUE);
3753 /* test if lreg is negative */
3754 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3755 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3757 /* add correction constant mn */
3758 if (cfg->compile_aot) {
3759 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3760 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3761 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3762 x86_fld80_membase (code, X86_ESP, 2);
3763 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3765 x86_fld80_mem (code, mn);
3767 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3769 x86_patch (br, code);
3771 /* Change precision */
3772 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3773 x86_fld_membase (code, X86_ESP, 0, TRUE);
3775 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3779 case OP_LCONV_TO_OVF_I:
3780 case OP_LCONV_TO_OVF_I4_2: {
3781 guint8 *br [3], *label [1];
3785 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3787 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3789 /* If the low word top bit is set, see if we are negative */
3790 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3791 /* We are not negative (no top bit set, check for our top word to be zero */
3792 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3793 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3796 /* throw exception */
3797 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3799 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3800 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3801 x86_jump8 (code, 0);
3803 x86_jump32 (code, 0);
3805 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3806 x86_jump32 (code, 0);
3810 x86_patch (br [0], code);
3811 /* our top bit is set, check that top word is 0xfffffff */
3812 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3814 x86_patch (br [1], code);
3815 /* nope, emit exception */
3816 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3817 x86_patch (br [2], label [0]);
3819 if (ins->dreg != ins->sreg1)
3820 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3824 /* Not needed on the fp stack */
3827 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3830 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3833 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3836 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3844 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3849 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3856 * it really doesn't make sense to inline all this code,
3857 * it's here just to show that things may not be as simple
3860 guchar *check_pos, *end_tan, *pop_jump;
3861 x86_push_reg (code, X86_EAX);
3864 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3866 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3867 x86_fstp (code, 0); /* pop the 1.0 */
3869 x86_jump8 (code, 0);
3871 x86_fp_op (code, X86_FADD, 0);
3875 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3877 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3880 x86_patch (pop_jump, code);
3881 x86_fstp (code, 0); /* pop the 1.0 */
3882 x86_patch (check_pos, code);
3883 x86_patch (end_tan, code);
3885 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3886 x86_pop_reg (code, X86_EAX);
3893 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3902 g_assert (cfg->opt & MONO_OPT_CMOV);
3903 g_assert (ins->dreg == ins->sreg1);
3904 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3905 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3908 g_assert (cfg->opt & MONO_OPT_CMOV);
3909 g_assert (ins->dreg == ins->sreg1);
3910 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3911 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3914 g_assert (cfg->opt & MONO_OPT_CMOV);
3915 g_assert (ins->dreg == ins->sreg1);
3916 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3917 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3920 g_assert (cfg->opt & MONO_OPT_CMOV);
3921 g_assert (ins->dreg == ins->sreg1);
3922 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3923 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3929 x86_fxch (code, ins->inst_imm);
3934 x86_push_reg (code, X86_EAX);
3935 /* we need to exchange ST(0) with ST(1) */
3938 /* this requires a loop, because fprem somtimes
3939 * returns a partial remainder */
3941 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3942 /* x86_fprem1 (code); */
3945 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3947 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3953 x86_pop_reg (code, X86_EAX);
3957 if (cfg->opt & MONO_OPT_FCMOV) {
3958 x86_fcomip (code, 1);
3962 /* this overwrites EAX */
3963 EMIT_FPCOMPARE(code);
3964 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3968 if (cfg->opt & MONO_OPT_FCMOV) {
3969 /* zeroing the register at the start results in
3970 * shorter and faster code (we can also remove the widening op)
3972 guchar *unordered_check;
3973 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3974 x86_fcomip (code, 1);
3976 unordered_check = code;
3977 x86_branch8 (code, X86_CC_P, 0, FALSE);
3978 if (ins->opcode == OP_FCEQ) {
3979 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3980 x86_patch (unordered_check, code);
3982 guchar *jump_to_end;
3983 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3985 x86_jump8 (code, 0);
3986 x86_patch (unordered_check, code);
3987 x86_inc_reg (code, ins->dreg);
3988 x86_patch (jump_to_end, code);
3993 if (ins->dreg != X86_EAX)
3994 x86_push_reg (code, X86_EAX);
3996 EMIT_FPCOMPARE(code);
3997 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3998 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3999 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
4000 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4002 if (ins->dreg != X86_EAX)
4003 x86_pop_reg (code, X86_EAX);
4007 if (cfg->opt & MONO_OPT_FCMOV) {
4008 /* zeroing the register at the start results in
4009 * shorter and faster code (we can also remove the widening op)
4011 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4012 x86_fcomip (code, 1);
4014 if (ins->opcode == OP_FCLT_UN) {
4015 guchar *unordered_check = code;
4016 guchar *jump_to_end;
4017 x86_branch8 (code, X86_CC_P, 0, FALSE);
4018 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4020 x86_jump8 (code, 0);
4021 x86_patch (unordered_check, code);
4022 x86_inc_reg (code, ins->dreg);
4023 x86_patch (jump_to_end, code);
4025 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4029 if (ins->dreg != X86_EAX)
4030 x86_push_reg (code, X86_EAX);
4032 EMIT_FPCOMPARE(code);
4033 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4034 if (ins->opcode == OP_FCLT_UN) {
4035 guchar *is_not_zero_check, *end_jump;
4036 is_not_zero_check = code;
4037 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4039 x86_jump8 (code, 0);
4040 x86_patch (is_not_zero_check, code);
4041 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4043 x86_patch (end_jump, code);
4045 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4046 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4048 if (ins->dreg != X86_EAX)
4049 x86_pop_reg (code, X86_EAX);
4052 guchar *unordered_check;
4053 guchar *jump_to_end;
4054 if (cfg->opt & MONO_OPT_FCMOV) {
4055 /* zeroing the register at the start results in
4056 * shorter and faster code (we can also remove the widening op)
4058 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4059 x86_fcomip (code, 1);
4061 unordered_check = code;
4062 x86_branch8 (code, X86_CC_P, 0, FALSE);
4063 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
4064 x86_patch (unordered_check, code);
4067 if (ins->dreg != X86_EAX)
4068 x86_push_reg (code, X86_EAX);
4070 EMIT_FPCOMPARE(code);
4071 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4072 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4073 unordered_check = code;
4074 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4076 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4077 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
4078 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4080 x86_jump8 (code, 0);
4081 x86_patch (unordered_check, code);
4082 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4083 x86_patch (jump_to_end, code);
4085 if (ins->dreg != X86_EAX)
4086 x86_pop_reg (code, X86_EAX);
4091 if (cfg->opt & MONO_OPT_FCMOV) {
4092 /* zeroing the register at the start results in
4093 * shorter and faster code (we can also remove the widening op)
4095 guchar *unordered_check;
4096 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4097 x86_fcomip (code, 1);
4099 if (ins->opcode == OP_FCGT) {
4100 unordered_check = code;
4101 x86_branch8 (code, X86_CC_P, 0, FALSE);
4102 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4103 x86_patch (unordered_check, code);
4105 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4109 if (ins->dreg != X86_EAX)
4110 x86_push_reg (code, X86_EAX);
4112 EMIT_FPCOMPARE(code);
4113 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4114 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4115 if (ins->opcode == OP_FCGT_UN) {
4116 guchar *is_not_zero_check, *end_jump;
4117 is_not_zero_check = code;
4118 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4120 x86_jump8 (code, 0);
4121 x86_patch (is_not_zero_check, code);
4122 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4124 x86_patch (end_jump, code);
4126 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4127 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4129 if (ins->dreg != X86_EAX)
4130 x86_pop_reg (code, X86_EAX);
4133 guchar *unordered_check;
4134 guchar *jump_to_end;
4135 if (cfg->opt & MONO_OPT_FCMOV) {
4136 /* zeroing the register at the start results in
4137 * shorter and faster code (we can also remove the widening op)
4139 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4140 x86_fcomip (code, 1);
4142 unordered_check = code;
4143 x86_branch8 (code, X86_CC_P, 0, FALSE);
4144 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4145 x86_patch (unordered_check, code);
4148 if (ins->dreg != X86_EAX)
4149 x86_push_reg (code, X86_EAX);
4151 EMIT_FPCOMPARE(code);
4152 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4153 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4154 unordered_check = code;
4155 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4157 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4158 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4159 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4161 x86_jump8 (code, 0);
4162 x86_patch (unordered_check, code);
4163 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4164 x86_patch (jump_to_end, code);
4166 if (ins->dreg != X86_EAX)
4167 x86_pop_reg (code, X86_EAX);
4171 if (cfg->opt & MONO_OPT_FCMOV) {
4172 guchar *jump = code;
4173 x86_branch8 (code, X86_CC_P, 0, TRUE);
4174 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4175 x86_patch (jump, code);
4178 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4179 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4182 /* Branch if C013 != 100 */
4183 if (cfg->opt & MONO_OPT_FCMOV) {
4184 /* branch if !ZF or (PF|CF) */
4185 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4186 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4187 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4190 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4191 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4194 if (cfg->opt & MONO_OPT_FCMOV) {
4195 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4198 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4201 if (cfg->opt & MONO_OPT_FCMOV) {
4202 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4203 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4206 if (ins->opcode == OP_FBLT_UN) {
4207 guchar *is_not_zero_check, *end_jump;
4208 is_not_zero_check = code;
4209 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4211 x86_jump8 (code, 0);
4212 x86_patch (is_not_zero_check, code);
4213 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4215 x86_patch (end_jump, code);
4217 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4221 if (cfg->opt & MONO_OPT_FCMOV) {
4222 if (ins->opcode == OP_FBGT) {
4225 /* skip branch if C1=1 */
4227 x86_branch8 (code, X86_CC_P, 0, FALSE);
4228 /* branch if (C0 | C3) = 1 */
4229 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4230 x86_patch (br1, code);
4232 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4236 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4237 if (ins->opcode == OP_FBGT_UN) {
4238 guchar *is_not_zero_check, *end_jump;
4239 is_not_zero_check = code;
4240 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4242 x86_jump8 (code, 0);
4243 x86_patch (is_not_zero_check, code);
4244 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4246 x86_patch (end_jump, code);
4248 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4251 /* Branch if C013 == 100 or 001 */
4252 if (cfg->opt & MONO_OPT_FCMOV) {
4255 /* skip branch if C1=1 */
4257 x86_branch8 (code, X86_CC_P, 0, FALSE);
4258 /* branch if (C0 | C3) = 1 */
4259 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4260 x86_patch (br1, code);
4263 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4264 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4265 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4266 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4269 /* Branch if C013 == 000 */
4270 if (cfg->opt & MONO_OPT_FCMOV) {
4271 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4274 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4277 /* Branch if C013=000 or 100 */
4278 if (cfg->opt & MONO_OPT_FCMOV) {
4281 /* skip branch if C1=1 */
4283 x86_branch8 (code, X86_CC_P, 0, FALSE);
4284 /* branch if C0=0 */
4285 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4286 x86_patch (br1, code);
4289 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4290 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4291 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4294 /* Branch if C013 != 001 */
4295 if (cfg->opt & MONO_OPT_FCMOV) {
4296 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4297 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4300 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4301 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4305 x86_push_reg (code, X86_EAX);
4308 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4309 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4310 x86_pop_reg (code, X86_EAX);
4312 /* Have to clean up the fp stack before throwing the exception */
4314 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4317 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4319 x86_patch (br1, code);
4323 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4326 case OP_TLS_GET_REG: {
4327 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4331 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4334 case OP_TLS_SET_REG: {
4335 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4338 case OP_MEMORY_BARRIER: {
4339 /* x86 only needs barrier for StoreLoad and FullBarrier */
4340 switch (ins->backend.memory_barrier_kind) {
4341 case StoreLoadBarrier:
4343 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4344 x86_prefix (code, X86_LOCK_PREFIX);
4345 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4350 case OP_ATOMIC_ADD_I4: {
4351 int dreg = ins->dreg;
4353 if (dreg == ins->inst_basereg) {
4354 x86_push_reg (code, ins->sreg2);
4358 if (dreg != ins->sreg2)
4359 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
4361 x86_prefix (code, X86_LOCK_PREFIX);
4362 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4364 if (dreg != ins->dreg) {
4365 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4366 x86_pop_reg (code, dreg);
4371 case OP_ATOMIC_ADD_NEW_I4: {
4372 int dreg = ins->dreg;
4374 g_assert (cfg->has_atomic_add_new_i4);
4376 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4377 if (ins->sreg2 == dreg) {
4378 if (dreg == X86_EBX) {
4380 if (ins->inst_basereg == X86_EDI)
4384 if (ins->inst_basereg == X86_EBX)
4387 } else if (ins->inst_basereg == dreg) {
4388 if (dreg == X86_EBX) {
4390 if (ins->sreg2 == X86_EDI)
4394 if (ins->sreg2 == X86_EBX)
4399 if (dreg != ins->dreg) {
4400 x86_push_reg (code, dreg);
4403 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4404 x86_prefix (code, X86_LOCK_PREFIX);
4405 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4406 /* dreg contains the old value, add with sreg2 value */
4407 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4409 if (ins->dreg != dreg) {
4410 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4411 x86_pop_reg (code, dreg);
4416 case OP_ATOMIC_EXCHANGE_I4: {
4418 int sreg2 = ins->sreg2;
4419 int breg = ins->inst_basereg;
4421 g_assert (cfg->has_atomic_exchange_i4);
4423 /* cmpxchg uses eax as comperand, need to make sure we can use it
4424 * hack to overcome limits in x86 reg allocator
4425 * (req: dreg == eax and sreg2 != eax and breg != eax)
4427 g_assert (ins->dreg == X86_EAX);
4429 /* We need the EAX reg for the cmpxchg */
4430 if (ins->sreg2 == X86_EAX) {
4431 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4432 x86_push_reg (code, sreg2);
4433 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4436 if (breg == X86_EAX) {
4437 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4438 x86_push_reg (code, breg);
4439 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4442 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4444 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4445 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4446 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4447 x86_patch (br [1], br [0]);
4449 if (breg != ins->inst_basereg)
4450 x86_pop_reg (code, breg);
4452 if (ins->sreg2 != sreg2)
4453 x86_pop_reg (code, sreg2);
4457 case OP_ATOMIC_CAS_I4: {
4458 g_assert (ins->dreg == X86_EAX);
4459 g_assert (ins->sreg3 == X86_EAX);
4460 g_assert (ins->sreg1 != X86_EAX);
4461 g_assert (ins->sreg1 != ins->sreg2);
4463 x86_prefix (code, X86_LOCK_PREFIX);
4464 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4467 case OP_CARD_TABLE_WBARRIER: {
4468 int ptr = ins->sreg1;
4469 int value = ins->sreg2;
4471 int nursery_shift, card_table_shift;
4472 gpointer card_table_mask;
4473 size_t nursery_size;
4474 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4475 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4476 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4479 * We need one register we can clobber, we choose EDX and make sreg1
4480 * fixed EAX to work around limitations in the local register allocator.
4481 * sreg2 might get allocated to EDX, but that is not a problem since
4482 * we use it before clobbering EDX.
4484 g_assert (ins->sreg1 == X86_EAX);
4487 * This is the code we produce:
4490 * edx >>= nursery_shift
4491 * cmp edx, (nursery_start >> nursery_shift)
4494 * edx >>= card_table_shift
4495 * card_table[edx] = 1
4499 if (card_table_nursery_check) {
4500 if (value != X86_EDX)
4501 x86_mov_reg_reg (code, X86_EDX, value, 4);
4502 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4503 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4504 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4506 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4507 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4508 if (card_table_mask)
4509 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4510 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4511 if (card_table_nursery_check)
4512 x86_patch (br, code);
4515 #ifdef MONO_ARCH_SIMD_INTRINSICS
4517 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4520 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4523 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4526 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4529 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4532 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4535 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4536 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4539 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4542 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4545 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4548 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4551 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4554 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4557 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4560 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4563 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4566 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4569 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4572 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4575 case OP_PSHUFLEW_HIGH:
4576 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4577 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4579 case OP_PSHUFLEW_LOW:
4580 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4581 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4584 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4585 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4588 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4589 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4592 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4593 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4597 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4600 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4603 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4606 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4609 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4612 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4615 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4616 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4619 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4622 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4625 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4628 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4631 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4634 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4637 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4640 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4643 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4646 case OP_EXTRACT_MASK:
4647 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4651 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4654 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4657 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4661 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4664 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4667 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4670 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4674 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4677 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4680 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4683 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4687 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4690 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4693 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4697 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4700 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4703 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4707 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4710 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4714 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4717 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4720 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4724 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4727 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4730 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4734 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4737 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4740 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4743 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4747 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4750 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4753 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4756 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4759 case OP_PSUM_ABS_DIFF:
4760 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4763 case OP_UNPACK_LOWB:
4764 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4766 case OP_UNPACK_LOWW:
4767 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4769 case OP_UNPACK_LOWD:
4770 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4772 case OP_UNPACK_LOWQ:
4773 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4775 case OP_UNPACK_LOWPS:
4776 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4778 case OP_UNPACK_LOWPD:
4779 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4782 case OP_UNPACK_HIGHB:
4783 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4785 case OP_UNPACK_HIGHW:
4786 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4788 case OP_UNPACK_HIGHD:
4789 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4791 case OP_UNPACK_HIGHQ:
4792 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4794 case OP_UNPACK_HIGHPS:
4795 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4797 case OP_UNPACK_HIGHPD:
4798 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4802 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4805 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4808 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4811 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4814 case OP_PADDB_SAT_UN:
4815 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4817 case OP_PSUBB_SAT_UN:
4818 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4820 case OP_PADDW_SAT_UN:
4821 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4823 case OP_PSUBW_SAT_UN:
4824 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4828 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4831 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4834 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4837 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4841 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4844 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4847 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4849 case OP_PMULW_HIGH_UN:
4850 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4853 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4857 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4860 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4864 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4867 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4871 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4874 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4878 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4881 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4885 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4888 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4892 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4895 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4899 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4902 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4906 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4909 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4913 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4916 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4920 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4922 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4923 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4927 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4929 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4930 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4934 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4936 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4937 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4941 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4943 case OP_EXTRACTX_U2:
4944 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4946 case OP_INSERTX_U1_SLOW:
4947 /*sreg1 is the extracted ireg (scratch)
4948 /sreg2 is the to be inserted ireg (scratch)
4949 /dreg is the xreg to receive the value*/
4951 /*clear the bits from the extracted word*/
4952 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4953 /*shift the value to insert if needed*/
4954 if (ins->inst_c0 & 1)
4955 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4956 /*join them together*/
4957 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4958 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4960 case OP_INSERTX_I4_SLOW:
4961 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4962 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4963 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4966 case OP_INSERTX_R4_SLOW:
4967 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4968 /*TODO if inst_c0 == 0 use movss*/
4969 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4970 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4972 case OP_INSERTX_R8_SLOW:
4973 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4974 if (cfg->verbose_level)
4975 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4977 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4979 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4982 case OP_STOREX_MEMBASE_REG:
4983 case OP_STOREX_MEMBASE:
4984 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4986 case OP_LOADX_MEMBASE:
4987 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4989 case OP_LOADX_ALIGNED_MEMBASE:
4990 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4992 case OP_STOREX_ALIGNED_MEMBASE_REG:
4993 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4995 case OP_STOREX_NTA_MEMBASE_REG:
4996 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4998 case OP_PREFETCH_MEMBASE:
4999 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5003 /*FIXME the peephole pass should have killed this*/
5004 if (ins->dreg != ins->sreg1)
5005 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5008 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
5010 case OP_ICONV_TO_R8_RAW:
5011 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
5012 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
5015 case OP_FCONV_TO_R8_X:
5016 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
5017 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5020 case OP_XCONV_R8_TO_I4:
5021 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
5022 switch (ins->backend.source_opcode) {
5023 case OP_FCONV_TO_I1:
5024 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5026 case OP_FCONV_TO_U1:
5027 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5029 case OP_FCONV_TO_I2:
5030 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5032 case OP_FCONV_TO_U2:
5033 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5039 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
5040 /*The +4 is to get a mov ?h, ?l over the same reg.*/
5041 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
5042 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
5043 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
5044 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5047 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
5048 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
5049 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5052 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
5053 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5056 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
5057 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5058 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
5061 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
5062 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
5063 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
5067 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
5070 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
5073 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
5076 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
5079 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
5082 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
5085 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
5088 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
5092 case OP_LIVERANGE_START: {
5093 if (cfg->verbose_level > 1)
5094 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5095 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5098 case OP_LIVERANGE_END: {
5099 if (cfg->verbose_level > 1)
5100 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5101 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5104 case OP_NACL_GC_SAFE_POINT: {
5105 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
5106 if (cfg->compile_aot)
5107 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5111 x86_test_mem_imm8 (code, (gpointer)&__nacl_thread_suspension_needed, 0xFFFFFFFF);
5112 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
5113 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5114 x86_patch (br[0], code);
5119 case OP_GC_LIVENESS_DEF:
5120 case OP_GC_LIVENESS_USE:
5121 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5122 ins->backend.pc_offset = code - cfg->native_code;
5124 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5125 ins->backend.pc_offset = code - cfg->native_code;
5126 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5129 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
5130 g_assert_not_reached ();
5133 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
5134 #ifndef __native_client_codegen__
5135 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5136 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5137 g_assert_not_reached ();
5138 #endif /* __native_client_codegen__ */
5144 cfg->code_len = code - cfg->native_code;
5147 #endif /* DISABLE_JIT */
5150 mono_arch_register_lowlevel_calls (void)
5155 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
5157 MonoJumpInfo *patch_info;
5158 gboolean compile_aot = !run_cctors;
5160 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5161 unsigned char *ip = patch_info->ip.i + code;
5162 const unsigned char *target;
5165 switch (patch_info->type) {
5166 case MONO_PATCH_INFO_BB:
5167 case MONO_PATCH_INFO_LABEL:
5170 /* No need to patch these */
5175 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5177 switch (patch_info->type) {
5178 case MONO_PATCH_INFO_IP:
5179 *((gconstpointer *)(ip)) = target;
5181 case MONO_PATCH_INFO_CLASS_INIT: {
5183 /* Might already been changed to a nop */
5184 x86_call_code (code, 0);
5185 x86_patch (ip, target);
5188 case MONO_PATCH_INFO_ABS:
5189 case MONO_PATCH_INFO_METHOD:
5190 case MONO_PATCH_INFO_METHOD_JUMP:
5191 case MONO_PATCH_INFO_INTERNAL_METHOD:
5192 case MONO_PATCH_INFO_BB:
5193 case MONO_PATCH_INFO_LABEL:
5194 case MONO_PATCH_INFO_RGCTX_FETCH:
5195 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
5196 case MONO_PATCH_INFO_MONITOR_ENTER:
5197 case MONO_PATCH_INFO_MONITOR_EXIT:
5198 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5199 #if defined(__native_client_codegen__) && defined(__native_client__)
5200 if (nacl_is_code_address (code)) {
5201 /* For tail calls, code is patched after being installed */
5202 /* but not through the normal "patch callsite" method. */
5203 unsigned char buf[kNaClAlignment];
5204 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5205 unsigned char *_target = target;
5207 /* All patch targets modified in x86_patch */
5208 /* are IP relative. */
5209 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5210 memcpy (buf, aligned_code, kNaClAlignment);
5211 /* Patch a temp buffer of bundle size, */
5212 /* then install to actual location. */
5213 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5214 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5215 g_assert (ret == 0);
5218 x86_patch (ip, target);
5221 x86_patch (ip, target);
5224 case MONO_PATCH_INFO_NONE:
5226 case MONO_PATCH_INFO_R4:
5227 case MONO_PATCH_INFO_R8: {
5228 guint32 offset = mono_arch_get_patch_offset (ip);
5229 *((gconstpointer *)(ip + offset)) = target;
5233 guint32 offset = mono_arch_get_patch_offset (ip);
5234 #if !defined(__native_client__)
5235 *((gconstpointer *)(ip + offset)) = target;
5237 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5245 static G_GNUC_UNUSED void
5246 stack_unaligned (MonoMethod *m, gpointer caller)
5248 printf ("%s\n", mono_method_full_name (m, TRUE));
5249 g_assert_not_reached ();
5253 mono_arch_emit_prolog (MonoCompile *cfg)
5255 MonoMethod *method = cfg->method;
5257 MonoMethodSignature *sig;
5259 int alloc_size, pos, max_offset, i, cfa_offset;
5261 gboolean need_stack_frame;
5262 #ifdef __native_client_codegen__
5263 guint alignment_check;
5266 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5268 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5269 cfg->code_size += 512;
5271 #if defined(__default_codegen__)
5272 code = cfg->native_code = g_malloc (cfg->code_size);
5273 #elif defined(__native_client_codegen__)
5274 /* native_code_alloc is not 32-byte aligned, native_code is. */
5275 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5276 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5278 /* Align native_code to next nearest kNaclAlignment byte. */
5279 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5280 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5282 code = cfg->native_code;
5284 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5285 g_assert(alignment_check == 0);
5292 /* Check that the stack is aligned on osx */
5293 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5294 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5295 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5297 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5298 x86_push_membase (code, X86_ESP, 0);
5299 x86_push_imm (code, cfg->method);
5300 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5301 x86_call_reg (code, X86_EAX);
5302 x86_patch (br [0], code);
5306 /* Offset between RSP and the CFA */
5310 cfa_offset = sizeof (gpointer);
5311 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5312 // IP saved at CFA - 4
5313 /* There is no IP reg on x86 */
5314 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5315 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5317 need_stack_frame = needs_stack_frame (cfg);
5319 if (need_stack_frame) {
5320 x86_push_reg (code, X86_EBP);
5321 cfa_offset += sizeof (gpointer);
5322 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5323 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5324 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5325 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5326 /* These are handled automatically by the stack marking code */
5327 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5329 cfg->frame_reg = X86_ESP;
5332 alloc_size = cfg->stack_offset;
5335 if (!method->save_lmf) {
5336 if (cfg->used_int_regs & (1 << X86_EBX)) {
5337 x86_push_reg (code, X86_EBX);
5339 cfa_offset += sizeof (gpointer);
5340 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5341 /* These are handled automatically by the stack marking code */
5342 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5345 if (cfg->used_int_regs & (1 << X86_EDI)) {
5346 x86_push_reg (code, X86_EDI);
5348 cfa_offset += sizeof (gpointer);
5349 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5350 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5353 if (cfg->used_int_regs & (1 << X86_ESI)) {
5354 x86_push_reg (code, X86_ESI);
5356 cfa_offset += sizeof (gpointer);
5357 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5358 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5364 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5365 if (mono_do_x86_stack_align && need_stack_frame) {
5366 int tot = alloc_size + pos + 4; /* ret ip */
5367 if (need_stack_frame)
5369 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5371 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5372 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5373 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5377 cfg->arch.sp_fp_offset = alloc_size + pos;
5380 /* See mono_emit_stack_alloc */
5381 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5382 guint32 remaining_size = alloc_size;
5383 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5384 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5385 guint32 offset = code - cfg->native_code;
5386 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5387 while (required_code_size >= (cfg->code_size - offset))
5388 cfg->code_size *= 2;
5389 cfg->native_code = mono_realloc_native_code(cfg);
5390 code = cfg->native_code + offset;
5391 cfg->stat_code_reallocs++;
5393 while (remaining_size >= 0x1000) {
5394 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5395 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5396 remaining_size -= 0x1000;
5399 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5401 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5404 g_assert (need_stack_frame);
5407 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5408 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5409 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5412 #if DEBUG_STACK_ALIGNMENT
5413 /* check the stack is aligned */
5414 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5415 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5416 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5417 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5418 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5419 x86_breakpoint (code);
5423 /* compute max_offset in order to use short forward jumps */
5425 if (cfg->opt & MONO_OPT_BRANCH) {
5426 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5428 bb->max_offset = max_offset;
5430 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5432 /* max alignment for loops */
5433 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5434 max_offset += LOOP_ALIGNMENT;
5435 #ifdef __native_client_codegen__
5436 /* max alignment for native client */
5437 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5438 max_offset += kNaClAlignment;
5440 MONO_BB_FOR_EACH_INS (bb, ins) {
5441 if (ins->opcode == OP_LABEL)
5442 ins->inst_c1 = max_offset;
5443 #ifdef __native_client_codegen__
5444 switch (ins->opcode)
5456 case OP_VOIDCALL_REG:
5458 case OP_FCALL_MEMBASE:
5459 case OP_LCALL_MEMBASE:
5460 case OP_VCALL_MEMBASE:
5461 case OP_VCALL2_MEMBASE:
5462 case OP_VOIDCALL_MEMBASE:
5463 case OP_CALL_MEMBASE:
5464 max_offset += kNaClAlignment;
5467 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5470 #endif /* __native_client_codegen__ */
5471 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5476 /* store runtime generic context */
5477 if (cfg->rgctx_var) {
5478 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5480 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5483 if (method->save_lmf) {
5484 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5486 code = emit_push_lmf (cfg, code, cfg->lmf_var->inst_offset);
5489 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5490 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5492 /* load arguments allocated to register from the stack */
5493 sig = mono_method_signature (method);
5496 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5497 inst = cfg->args [pos];
5498 if (inst->opcode == OP_REGVAR) {
5499 g_assert (need_stack_frame);
5500 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5501 if (cfg->verbose_level > 2)
5502 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5507 cfg->code_len = code - cfg->native_code;
5509 g_assert (cfg->code_len < cfg->code_size);
5515 mono_arch_emit_epilog (MonoCompile *cfg)
5517 MonoMethod *method = cfg->method;
5518 MonoMethodSignature *sig = mono_method_signature (method);
5520 guint32 stack_to_pop;
5522 int max_epilog_size = 16;
5524 gboolean need_stack_frame = needs_stack_frame (cfg);
5526 if (cfg->method->save_lmf)
5527 max_epilog_size += 128;
5529 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5530 cfg->code_size *= 2;
5531 cfg->native_code = mono_realloc_native_code(cfg);
5532 cfg->stat_code_reallocs++;
5535 code = cfg->native_code + cfg->code_len;
5537 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5538 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5540 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5543 if (method->save_lmf) {
5544 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5546 gboolean supported = FALSE;
5548 if (cfg->compile_aot) {
5549 #if defined(__APPLE__) || defined(__linux__)
5552 } else if (mono_get_jit_tls_offset () != -1) {
5556 /* check if we need to restore protection of the stack after a stack overflow */
5558 if (cfg->compile_aot) {
5559 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5561 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5563 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5566 /* we load the value in a separate instruction: this mechanism may be
5567 * used later as a safer way to do thread interruption
5569 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5570 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5572 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5573 /* note that the call trampoline will preserve eax/edx */
5574 x86_call_reg (code, X86_ECX);
5575 x86_patch (patch, code);
5577 /* FIXME: maybe save the jit tls in the prolog */
5581 code = emit_pop_lmf (cfg, code, lmf_offset);
5583 /* restore caller saved regs */
5584 if (cfg->used_int_regs & (1 << X86_EBX)) {
5585 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
5588 if (cfg->used_int_regs & (1 << X86_EDI)) {
5589 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
5591 if (cfg->used_int_regs & (1 << X86_ESI)) {
5592 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
5595 /* EBP is restored by LEAVE */
5597 for (i = 0; i < X86_NREG; ++i) {
5598 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5604 g_assert (need_stack_frame);
5605 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5609 g_assert (need_stack_frame);
5610 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5613 if (cfg->used_int_regs & (1 << X86_ESI)) {
5614 x86_pop_reg (code, X86_ESI);
5616 if (cfg->used_int_regs & (1 << X86_EDI)) {
5617 x86_pop_reg (code, X86_EDI);
5619 if (cfg->used_int_regs & (1 << X86_EBX)) {
5620 x86_pop_reg (code, X86_EBX);
5624 /* Load returned vtypes into registers if needed */
5625 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5626 if (cinfo->ret.storage == ArgValuetypeInReg) {
5627 for (quad = 0; quad < 2; quad ++) {
5628 switch (cinfo->ret.pair_storage [quad]) {
5630 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5632 case ArgOnFloatFpStack:
5633 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5635 case ArgOnDoubleFpStack:
5636 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5641 g_assert_not_reached ();
5646 if (need_stack_frame)
5649 if (CALLCONV_IS_STDCALL (sig)) {
5650 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5652 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5653 } else if (cinfo->vtype_retaddr)
5659 g_assert (need_stack_frame);
5660 x86_ret_imm (code, stack_to_pop);
5665 cfg->code_len = code - cfg->native_code;
5667 g_assert (cfg->code_len < cfg->code_size);
5671 mono_arch_emit_exceptions (MonoCompile *cfg)
5673 MonoJumpInfo *patch_info;
5676 MonoClass *exc_classes [16];
5677 guint8 *exc_throw_start [16], *exc_throw_end [16];
5681 /* Compute needed space */
5682 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5683 if (patch_info->type == MONO_PATCH_INFO_EXC)
5688 * make sure we have enough space for exceptions
5689 * 16 is the size of two push_imm instructions and a call
5691 if (cfg->compile_aot)
5692 code_size = exc_count * 32;
5694 code_size = exc_count * 16;
5696 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5697 cfg->code_size *= 2;
5698 cfg->native_code = mono_realloc_native_code(cfg);
5699 cfg->stat_code_reallocs++;
5702 code = cfg->native_code + cfg->code_len;
5705 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5706 switch (patch_info->type) {
5707 case MONO_PATCH_INFO_EXC: {
5708 MonoClass *exc_class;
5712 x86_patch (patch_info->ip.i + cfg->native_code, code);
5714 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5715 g_assert (exc_class);
5716 throw_ip = patch_info->ip.i;
5718 /* Find a throw sequence for the same exception class */
5719 for (i = 0; i < nthrows; ++i)
5720 if (exc_classes [i] == exc_class)
5723 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5724 x86_jump_code (code, exc_throw_start [i]);
5725 patch_info->type = MONO_PATCH_INFO_NONE;
5730 /* Compute size of code following the push <OFFSET> */
5731 #if defined(__default_codegen__)
5733 #elif defined(__native_client_codegen__)
5734 code = mono_nacl_align (code);
5735 size = kNaClAlignment;
5737 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5739 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5740 /* Use the shorter form */
5742 x86_push_imm (code, 0);
5746 x86_push_imm (code, 0xf0f0f0f0);
5751 exc_classes [nthrows] = exc_class;
5752 exc_throw_start [nthrows] = code;
5755 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5756 patch_info->data.name = "mono_arch_throw_corlib_exception";
5757 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5758 patch_info->ip.i = code - cfg->native_code;
5759 x86_call_code (code, 0);
5760 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5765 exc_throw_end [nthrows] = code;
5777 cfg->code_len = code - cfg->native_code;
5779 g_assert (cfg->code_len < cfg->code_size);
5783 mono_arch_flush_icache (guint8 *code, gint size)
5789 mono_arch_flush_register_windows (void)
5794 mono_arch_is_inst_imm (gint64 imm)
5800 mono_arch_finish_init (void)
5802 if (!g_getenv ("MONO_NO_TLS")) {
5805 * We need to init this multiple times, since when we are first called, the key might not
5806 * be initialized yet.
5808 jit_tls_offset = mono_get_jit_tls_key ();
5810 /* Only 64 tls entries can be accessed using inline code */
5811 if (jit_tls_offset >= 64)
5812 jit_tls_offset = -1;
5815 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5817 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5823 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5827 #ifdef MONO_ARCH_HAVE_IMT
5829 // Linear handler, the bsearch head compare is shorter
5830 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5831 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5832 // x86_patch(ins,target)
5833 //[1 + 5] x86_jump_mem(inst,mem)
5836 #if defined(__default_codegen__)
5837 #define BR_SMALL_SIZE 2
5838 #define BR_LARGE_SIZE 5
5839 #elif defined(__native_client_codegen__)
5840 /* I suspect the size calculation below is actually incorrect. */
5841 /* TODO: fix the calculation that uses these sizes. */
5842 #define BR_SMALL_SIZE 16
5843 #define BR_LARGE_SIZE 12
5844 #endif /*__native_client_codegen__*/
5845 #define JUMP_IMM_SIZE 6
5846 #define ENABLE_WRONG_METHOD_CHECK 0
5850 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5852 int i, distance = 0;
5853 for (i = start; i < target; ++i)
5854 distance += imt_entries [i]->chunk_size;
5859 * LOCKING: called with the domain lock held
5862 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5863 gpointer fail_tramp)
5867 guint8 *code, *start;
5869 for (i = 0; i < count; ++i) {
5870 MonoIMTCheckItem *item = imt_entries [i];
5871 if (item->is_equals) {
5872 if (item->check_target_idx) {
5873 if (!item->compare_done)
5874 item->chunk_size += CMP_SIZE;
5875 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5878 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5880 item->chunk_size += JUMP_IMM_SIZE;
5881 #if ENABLE_WRONG_METHOD_CHECK
5882 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5887 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5888 imt_entries [item->check_target_idx]->compare_done = TRUE;
5890 size += item->chunk_size;
5892 #if defined(__native_client__) && defined(__native_client_codegen__)
5893 /* In Native Client, we don't re-use thunks, allocate from the */
5894 /* normal code manager paths. */
5895 size = NACL_BUNDLE_ALIGN_UP (size);
5896 code = mono_domain_code_reserve (domain, size);
5899 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5901 code = mono_domain_code_reserve (domain, size);
5904 for (i = 0; i < count; ++i) {
5905 MonoIMTCheckItem *item = imt_entries [i];
5906 item->code_target = code;
5907 if (item->is_equals) {
5908 if (item->check_target_idx) {
5909 if (!item->compare_done)
5910 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5911 item->jmp_code = code;
5912 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5913 if (item->has_target_code)
5914 x86_jump_code (code, item->value.target_code);
5916 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5919 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5920 item->jmp_code = code;
5921 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5922 if (item->has_target_code)
5923 x86_jump_code (code, item->value.target_code);
5925 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5926 x86_patch (item->jmp_code, code);
5927 x86_jump_code (code, fail_tramp);
5928 item->jmp_code = NULL;
5930 /* enable the commented code to assert on wrong method */
5931 #if ENABLE_WRONG_METHOD_CHECK
5932 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5933 item->jmp_code = code;
5934 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5936 if (item->has_target_code)
5937 x86_jump_code (code, item->value.target_code);
5939 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5940 #if ENABLE_WRONG_METHOD_CHECK
5941 x86_patch (item->jmp_code, code);
5942 x86_breakpoint (code);
5943 item->jmp_code = NULL;
5948 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5949 item->jmp_code = code;
5950 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5951 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5953 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5956 /* patch the branches to get to the target items */
5957 for (i = 0; i < count; ++i) {
5958 MonoIMTCheckItem *item = imt_entries [i];
5959 if (item->jmp_code) {
5960 if (item->check_target_idx) {
5961 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5967 mono_stats.imt_thunks_size += code - start;
5968 g_assert (code - start <= size);
5972 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5973 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5977 if (mono_jit_map_is_enabled ()) {
5980 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5982 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5983 mono_emit_jit_tramp (start, code - start, buff);
5987 nacl_domain_code_validate (domain, &start, size, &code);
5993 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5995 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
6000 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6002 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6006 mono_arch_get_cie_program (void)
6010 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
6011 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
6017 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6019 MonoInst *ins = NULL;
6022 if (cmethod->klass == mono_defaults.math_class) {
6023 if (strcmp (cmethod->name, "Sin") == 0) {
6025 } else if (strcmp (cmethod->name, "Cos") == 0) {
6027 } else if (strcmp (cmethod->name, "Tan") == 0) {
6029 } else if (strcmp (cmethod->name, "Atan") == 0) {
6031 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6033 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6035 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
6040 MONO_INST_NEW (cfg, ins, opcode);
6041 ins->type = STACK_R8;
6042 ins->dreg = mono_alloc_freg (cfg);
6043 ins->sreg1 = args [0]->dreg;
6044 MONO_ADD_INS (cfg->cbb, ins);
6047 if (cfg->opt & MONO_OPT_CMOV) {
6050 if (strcmp (cmethod->name, "Min") == 0) {
6051 if (fsig->params [0]->type == MONO_TYPE_I4)
6053 } else if (strcmp (cmethod->name, "Max") == 0) {
6054 if (fsig->params [0]->type == MONO_TYPE_I4)
6059 MONO_INST_NEW (cfg, ins, opcode);
6060 ins->type = STACK_I4;
6061 ins->dreg = mono_alloc_ireg (cfg);
6062 ins->sreg1 = args [0]->dreg;
6063 ins->sreg2 = args [1]->dreg;
6064 MONO_ADD_INS (cfg->cbb, ins);
6069 /* OP_FREM is not IEEE compatible */
6070 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6071 MONO_INST_NEW (cfg, ins, OP_FREM);
6072 ins->inst_i0 = args [0];
6073 ins->inst_i1 = args [1];
6082 mono_arch_print_tree (MonoInst *tree, int arity)
6088 mono_arch_get_patch_offset (guint8 *code)
6090 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
6092 else if (code [0] == 0xba)
6094 else if (code [0] == 0x68)
6097 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
6098 /* push <OFFSET>(<REG>) */
6100 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
6101 /* call *<OFFSET>(<REG>) */
6103 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
6106 else if ((code [0] == 0x58) && (code [1] == 0x05))
6107 /* pop %eax; add <OFFSET>, %eax */
6109 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6110 /* pop <REG>; add <OFFSET>, <REG> */
6112 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6113 /* mov <REG>, imm */
6116 g_assert_not_reached ();
6122 * mono_breakpoint_clean_code:
6124 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6125 * breakpoints in the original code, they are removed in the copy.
6127 * Returns TRUE if no sw breakpoint was present.
6130 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6133 gboolean can_write = TRUE;
6135 * If method_start is non-NULL we need to perform bound checks, since we access memory
6136 * at code - offset we could go before the start of the method and end up in a different
6137 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6140 if (!method_start || code - offset >= method_start) {
6141 memcpy (buf, code - offset, size);
6143 int diff = code - method_start;
6144 memset (buf, 0, size);
6145 memcpy (buf + offset - diff, method_start, diff + size - offset);
6148 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6149 int idx = mono_breakpoint_info_index [i];
6153 ptr = mono_breakpoint_info [idx].address;
6154 if (ptr >= code && ptr < code + size) {
6155 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6157 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6158 buf [ptr - code] = saved_byte;
6165 * mono_x86_get_this_arg_offset:
6167 * Return the offset of the stack location where this is passed during a virtual
6171 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6177 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6179 guint32 esp = regs [X86_ESP];
6180 CallInfo *cinfo = NULL;
6187 * The stack looks like:
6191 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
6193 res = (((MonoObject**)esp) [5 + (offset / 4)]);
6199 #define MAX_ARCH_DELEGATE_PARAMS 10
6202 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6204 guint8 *code, *start;
6205 int code_reserve = 64;
6208 * The stack contains:
6214 start = code = mono_global_codeman_reserve (code_reserve);
6216 /* Replace the this argument with the target */
6217 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6218 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
6219 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6220 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6222 g_assert ((code - start) < code_reserve);
6225 /* 8 for mov_reg and jump, plus 8 for each parameter */
6226 #ifdef __native_client_codegen__
6227 /* TODO: calculate this size correctly */
6228 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6230 code_reserve = 8 + (param_count * 8);
6231 #endif /* __native_client_codegen__ */
6233 * The stack contains:
6234 * <args in reverse order>
6239 * <args in reverse order>
6242 * without unbalancing the stack.
6243 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6244 * and leaving original spot of first arg as placeholder in stack so
6245 * when callee pops stack everything works.
6248 start = code = mono_global_codeman_reserve (code_reserve);
6250 /* store delegate for access to method_ptr */
6251 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6254 for (i = 0; i < param_count; ++i) {
6255 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6256 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6259 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6261 g_assert ((code - start) < code_reserve);
6264 nacl_global_codeman_validate(&start, code_reserve, &code);
6265 mono_debug_add_delegate_trampoline (start, code - start);
6268 *code_len = code - start;
6270 if (mono_jit_map_is_enabled ()) {
6273 buff = (char*)"delegate_invoke_has_target";
6275 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6276 mono_emit_jit_tramp (start, code - start, buff);
6285 mono_arch_get_delegate_invoke_impls (void)
6293 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6294 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
6296 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6297 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6298 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
6299 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
6300 g_free (tramp_name);
6307 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6309 guint8 *code, *start;
6311 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6314 /* FIXME: Support more cases */
6315 if (MONO_TYPE_ISSTRUCT (sig->ret))
6319 * The stack contains:
6325 static guint8* cached = NULL;
6330 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6332 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6334 mono_memory_barrier ();
6338 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6341 for (i = 0; i < sig->param_count; ++i)
6342 if (!mono_is_regsize_var (sig->params [i]))
6345 code = cache [sig->param_count];
6349 if (mono_aot_only) {
6350 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6351 start = mono_aot_get_trampoline (name);
6354 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6357 mono_memory_barrier ();
6359 cache [sig->param_count] = start;
6366 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6369 case X86_EAX: return ctx->eax;
6370 case X86_EBX: return ctx->ebx;
6371 case X86_ECX: return ctx->ecx;
6372 case X86_EDX: return ctx->edx;
6373 case X86_ESP: return ctx->esp;
6374 case X86_EBP: return ctx->ebp;
6375 case X86_ESI: return ctx->esi;
6376 case X86_EDI: return ctx->edi;
6378 g_assert_not_reached ();
6384 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6412 g_assert_not_reached ();
6416 #ifdef MONO_ARCH_SIMD_INTRINSICS
6419 get_float_to_x_spill_area (MonoCompile *cfg)
6421 if (!cfg->fconv_to_r8_x_var) {
6422 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6423 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6425 return cfg->fconv_to_r8_x_var;
6429 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6432 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6435 int dreg, src_opcode;
6437 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6440 switch (src_opcode = ins->opcode) {
6441 case OP_FCONV_TO_I1:
6442 case OP_FCONV_TO_U1:
6443 case OP_FCONV_TO_I2:
6444 case OP_FCONV_TO_U2:
6445 case OP_FCONV_TO_I4:
6452 /* dreg is the IREG and sreg1 is the FREG */
6453 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6454 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6455 fconv->sreg1 = ins->sreg1;
6456 fconv->dreg = mono_alloc_ireg (cfg);
6457 fconv->type = STACK_VTYPE;
6458 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6460 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6464 ins->opcode = OP_XCONV_R8_TO_I4;
6466 ins->klass = mono_defaults.int32_class;
6467 ins->sreg1 = fconv->dreg;
6469 ins->type = STACK_I4;
6470 ins->backend.source_opcode = src_opcode;
6473 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6476 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6481 if (long_ins->opcode == OP_LNEG) {
6483 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6484 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6485 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6490 #ifdef MONO_ARCH_SIMD_INTRINSICS
6492 if (!(cfg->opt & MONO_OPT_SIMD))
6495 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6496 switch (long_ins->opcode) {
6498 vreg = long_ins->sreg1;
6500 if (long_ins->inst_c0) {
6501 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6502 ins->klass = long_ins->klass;
6503 ins->sreg1 = long_ins->sreg1;
6505 ins->type = STACK_VTYPE;
6506 ins->dreg = vreg = alloc_ireg (cfg);
6507 MONO_ADD_INS (cfg->cbb, ins);
6510 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6511 ins->klass = mono_defaults.int32_class;
6513 ins->type = STACK_I4;
6514 ins->dreg = long_ins->dreg + 1;
6515 MONO_ADD_INS (cfg->cbb, ins);
6517 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6518 ins->klass = long_ins->klass;
6519 ins->sreg1 = long_ins->sreg1;
6520 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6521 ins->type = STACK_VTYPE;
6522 ins->dreg = vreg = alloc_ireg (cfg);
6523 MONO_ADD_INS (cfg->cbb, ins);
6525 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6526 ins->klass = mono_defaults.int32_class;
6528 ins->type = STACK_I4;
6529 ins->dreg = long_ins->dreg + 2;
6530 MONO_ADD_INS (cfg->cbb, ins);
6532 long_ins->opcode = OP_NOP;
6534 case OP_INSERTX_I8_SLOW:
6535 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6536 ins->dreg = long_ins->dreg;
6537 ins->sreg1 = long_ins->dreg;
6538 ins->sreg2 = long_ins->sreg2 + 1;
6539 ins->inst_c0 = long_ins->inst_c0 * 2;
6540 MONO_ADD_INS (cfg->cbb, ins);
6542 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6543 ins->dreg = long_ins->dreg;
6544 ins->sreg1 = long_ins->dreg;
6545 ins->sreg2 = long_ins->sreg2 + 2;
6546 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6547 MONO_ADD_INS (cfg->cbb, ins);
6549 long_ins->opcode = OP_NOP;
6552 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6553 ins->dreg = long_ins->dreg;
6554 ins->sreg1 = long_ins->sreg1 + 1;
6555 ins->klass = long_ins->klass;
6556 ins->type = STACK_VTYPE;
6557 MONO_ADD_INS (cfg->cbb, ins);
6559 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6560 ins->dreg = long_ins->dreg;
6561 ins->sreg1 = long_ins->dreg;
6562 ins->sreg2 = long_ins->sreg1 + 2;
6564 ins->klass = long_ins->klass;
6565 ins->type = STACK_VTYPE;
6566 MONO_ADD_INS (cfg->cbb, ins);
6568 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6569 ins->dreg = long_ins->dreg;
6570 ins->sreg1 = long_ins->dreg;;
6571 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6572 ins->klass = long_ins->klass;
6573 ins->type = STACK_VTYPE;
6574 MONO_ADD_INS (cfg->cbb, ins);
6576 long_ins->opcode = OP_NOP;
6579 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6582 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6584 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6587 gpointer *sp, old_value;
6590 offset = clause->exvar_offset;
6593 bp = MONO_CONTEXT_GET_BP (ctx);
6594 sp = *(gpointer*)(bp + offset);
6597 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6606 * mono_aot_emit_load_got_addr:
6608 * Emit code to load the got address.
6609 * On x86, the result is placed into EBX.
6612 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6614 x86_call_imm (code, 0);
6616 * The patch needs to point to the pop, since the GOT offset needs
6617 * to be added to that address.
6620 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6622 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6623 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6624 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6630 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6633 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6635 g_assert_not_reached ();
6636 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6641 * mono_arch_emit_load_aotconst:
6643 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6644 * TARGET from the mscorlib GOT in full-aot code.
6645 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6649 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6651 /* Load the mscorlib got address */
6652 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6653 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6654 /* arch_emit_got_access () patches this */
6655 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6660 /* Can't put this into mini-x86.h */
6662 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6665 mono_arch_get_trampolines (gboolean aot)
6667 MonoTrampInfo *info;
6668 GSList *tramps = NULL;
6670 mono_x86_get_signal_exception_trampoline (&info, aot);
6672 tramps = g_slist_append (tramps, info);
6679 #define DBG_SIGNAL SIGBUS
6681 #define DBG_SIGNAL SIGSEGV
6684 /* Soft Debug support */
6685 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6688 * mono_arch_set_breakpoint:
6690 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6691 * The location should contain code emitted by OP_SEQ_POINT.
6694 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6699 * In production, we will use int3 (has to fix the size in the md
6700 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6703 g_assert (code [0] == 0x90);
6704 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6708 * mono_arch_clear_breakpoint:
6710 * Clear the breakpoint at IP.
6713 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6718 for (i = 0; i < 6; ++i)
6723 * mono_arch_start_single_stepping:
6725 * Start single stepping.
6728 mono_arch_start_single_stepping (void)
6730 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6734 * mono_arch_stop_single_stepping:
6736 * Stop single stepping.
6739 mono_arch_stop_single_stepping (void)
6741 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6745 * mono_arch_is_single_step_event:
6747 * Return whenever the machine state in SIGCTX corresponds to a single
6751 mono_arch_is_single_step_event (void *info, void *sigctx)
6754 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6756 if (((gpointer)einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6761 siginfo_t* sinfo = (siginfo_t*) info;
6762 /* Sometimes the address is off by 4 */
6763 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6771 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6774 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6775 if (((gpointer)einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6780 siginfo_t* sinfo = (siginfo_t*)info;
6781 /* Sometimes the address is off by 4 */
6782 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6789 #define BREAKPOINT_SIZE 6
6792 * mono_arch_skip_breakpoint:
6794 * See mini-amd64.c for docs.
6797 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6799 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6803 * mono_arch_skip_single_step:
6805 * See mini-amd64.c for docs.
6808 mono_arch_skip_single_step (MonoContext *ctx)
6810 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6814 * mono_arch_get_seq_point_info:
6816 * See mini-amd64.c for docs.
6819 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6826 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6828 ext->lmf.previous_lmf = (gsize)prev_lmf;
6829 /* Mark that this is a MonoLMFExt */
6830 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6831 ext->lmf.ebp = (gssize)ext;
6836 #if defined(ENABLE_GSHAREDVT)
6838 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6840 #endif /* !MONOTOUCH */