mono/mini/mini-sparc.c

   1 /*
   2  * mini-sparc.c: Sparc backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Paolo Molaro (lupus@ximian.com)
   6  *   Dietmar Maurer (dietmar@ximian.com)
   7  *
   8  * Modified for SPARC:
   9  *   Christopher Taylor (ct@gentoo.org)
  10  *   Mark Crichton (crichton@gimp.org)
  11  *   Zoltan Varga (vargaz@freemail.hu)
  12  *
  13  * (C) 2003 Ximian, Inc.
  14  */
  15 #include "mini.h"
  16 #include <string.h>
  17 #include <pthread.h>
  18 #include <unistd.h>
  19
  20 #ifndef __linux__
  21 #include <sys/systeminfo.h>
  22 #include <thread.h>
  23 #endif
  24
  25 #include <unistd.h>
  26 #include <sys/mman.h>
  27
  28 #include <mono/metadata/appdomain.h>
  29 #include <mono/metadata/debug-helpers.h>
  30 #include <mono/metadata/tokentype.h>
  31 #include <mono/utils/mono-math.h>
  32
  33 #include "mini-sparc.h"
  34 #include "inssel.h"
  35 #include "trace.h"
  36 #include "cpu-sparc.h"
  37
  38 /*
  39  * Sparc V9 means two things:
  40  * - the instruction set
  41  * - the ABI
  42  *
  43  * V9 instructions are only usable if the underlying processor is 64 bit. Most Sparc
  44  * processors in use are 64 bit processors. The V9 ABI is only usable if the
  45  * mono executable is a 64 bit executable. So it would make sense to use the 64 bit
  46  * instructions without using the 64 bit ABI.
  47  */
  48
  49 /*
  50  * Register usage:
  51  * - %i0..%i<n> hold the incoming arguments, these are never written by JITted
  52  * code. Unused input registers are used for global register allocation.
  53  * - %o0..%o5 and %l7 is used for local register allocation and passing arguments
  54  * - %l0..%l6 is used for global register allocation
  55  * - %o7 and %g1 is used as scratch registers in opcodes
  56  * - all floating point registers are used for local register allocation except %f0.
  57  *   Only double precision registers are used.
  58  * In 64 bit mode:
  59  * - fp registers %d0..%d30 are used for parameter passing, and %d32..%d62 are
  60  *   used for local allocation.
  61  */
  62
  63 /*
  64  * Alignment:
  65  * - doubles and longs must be stored in dword aligned locations
  66  */
  67
  68 /*
  69  * The following things are not implemented or do not work:
  70  *  - some fp arithmetic corner cases
  71  * The following tests in mono/mini are expected to fail:
  72  *  - test_0_simple_double_casts
  73  *      This test casts (guint64)-1 to double and then back to guint64 again.
  74  *    Under x86, it returns 0, while under sparc it returns -1.
  75  *
  76  * In addition to this, the runtime requires the trunc function, or its
  77  * solaris counterpart, aintl, to do some double->int conversions. If this
  78  * function is not available, it is emulated somewhat, but the results can be
  79  * strange.
  80  */
  81
  82 /*
  83  * SPARCV9 FIXME:
  84  * - optimize sparc_set according to the memory model
  85  * - when non-AOT compiling, compute patch targets immediately so we don't
  86  *   have to emit the 6 byte template.
  87  * - varags
  88  * - struct arguments/returns
  89  */
  90
  91 /*
  92  * SPARCV9 ISSUES:
  93  * - sparc_call_simple can't be used in a lot of places since the displacement
  94  *   might not fit into an imm30.
  95  * - g1 can't be used in a lot of places since it is used as a scratch reg in
  96  *   sparc_set.
  97  * - sparc_f0 can't be used as a scratch register on V9
  98  * - the %d34..%d62 fp registers are encoded as: %dx = %f(x - 32 + 1), ie.
  99  *   %d36 = %f5.
 100  * - ldind.i4/u4 needs to sign extend/clear out upper word -> slows things down
 101  * - ins->dreg can't be used as a scatch register in r4 opcodes since it might
 102  *   be a double precision register which has no single precision part.
 103  * - passing/returning structs is hard to implement, because:
 104  *   - the spec is very hard to understand
 105  *   - it requires knowledge about the fields of structure, needs to handle
 106  *     nested structures etc.
 107  */
 108
 109 /*
 110  * Possible optimizations:
 111  * - delay slot scheduling
 112  * - allocate large constants to registers
 113  * - add more mul/div/rem optimizations
 114  */
 115
 116 #ifndef __linux__
 117 #define MONO_SPARC_THR_TLS 1
 118 #endif
 119
 120 /*
 121  * There was a 64 bit bug in glib-2.2: g_bit_nth_msf (0, -1) would return 32,
 122  * causing infinite loops in dominator computation. So glib-2.4 is required.
 123  */
 124 #ifdef SPARCV9
 125 #if GLIB_MAJOR_VERSION == 2 && GLIB_MINOR_VERSION < 4
 126 #error "glib 2.4 or later is required for 64 bit mode."
 127 #endif
 128 #endif
 129
 130 #define NOT_IMPLEMENTED do { g_assert_not_reached (); } while (0)
 131
 132 #define ALIGN_TO(val,align) (((val) + ((align) - 1)) & ~((align) - 1))
 133
 134 #define SIGNAL_STACK_SIZE (64 * 1024)
 135
 136 #define STACK_BIAS MONO_SPARC_STACK_BIAS
 137
 138 #ifdef SPARCV9
 139
 140 /* %g1 is used by sparc_set */
 141 #define GP_SCRATCH_REG sparc_g4
 142 /* %f0 is used for parameter passing */
 143 #define FP_SCRATCH_REG sparc_f30
 144 #define ARGS_OFFSET (STACK_BIAS + 128)
 145
 146 #else
 147
 148 #define FP_SCRATCH_REG sparc_f0
 149 #define ARGS_OFFSET 68
 150 #define GP_SCRATCH_REG sparc_g1
 151
 152 #endif
 153
 154 /* Whenever the CPU supports v9 instructions */
 155 static gboolean sparcv9 = FALSE;
 156
 157 /* Whenever this is a 64bit executable */
 158 #if SPARCV9
 159 static gboolean v64 = TRUE;
 160 #else
 161 static gboolean v64 = FALSE;
 162 #endif
 163
 164 static gpointer mono_arch_get_lmf_addr (void);
 165
 166 static int
 167 mono_spillvar_offset_float (MonoCompile *cfg, int spillvar);
 168
 169 const char*
 170 mono_arch_regname (int reg) {
 171         static const char * rnames[] = {
 172                 "sparc_g0", "sparc_g1", "sparc_g2", "sparc_g3", "sparc_g4",
 173                 "sparc_g5", "sparc_g6", "sparc_g7", "sparc_o0", "sparc_o1",
 174                 "sparc_o2", "sparc_o3", "sparc_o4", "sparc_o5", "sparc_sp",
 175                 "sparc_call", "sparc_l0", "sparc_l1", "sparc_l2", "sparc_l3",
 176                 "sparc_l4", "sparc_l5", "sparc_l6", "sparc_l7", "sparc_i0",
 177                 "sparc_i1", "sparc_i2", "sparc_i3", "sparc_i4", "sparc_i5",
 178                 "sparc_fp", "sparc_retadr"
 179         };
 180         if (reg >= 0 && reg < 32)
 181                 return rnames [reg];
 182         return "unknown";
 183 }
 184
 185 const char*
 186 mono_arch_fregname (int reg) {
 187         static const char *rnames [] = {
 188                 "sparc_f0", "sparc_f1", "sparc_f2", "sparc_f3", "sparc_f4",
 189                 "sparc_f5", "sparc_f6", "sparc_f7", "sparc_f8", "sparc_f9",
 190                 "sparc_f10", "sparc_f11", "sparc_f12", "sparc_f13", "sparc_f14",
 191                 "sparc_f15", "sparc_f16", "sparc_f17", "sparc_f18", "sparc_f19",
 192                 "sparc_f20", "sparc_f21", "sparc_f22", "sparc_f23", "sparc_f24",
 193                 "sparc_f25", "sparc_f26", "sparc_f27", "sparc_f28", "sparc_f29",
 194                 "sparc_f30", "sparc_f31"
 195         };
 196
 197         if (reg >= 0 && reg < 32)
 198                 return rnames [reg];
 199         else
 200                 return "unknown";
 201 }
 202
 203 /*
 204  * Initialize the cpu to execute managed code.
 205  */
 206 void
 207 mono_arch_cpu_init (void)
 208 {
 209         guint32 dummy;
 210         /* make sure sparcv9 is initialized for embedded use */
 211         mono_arch_cpu_optimizazions(&dummy);
 212 }
 213
 214 /*
 215  * This function returns the optimizations supported on this cpu.
 216  */
 217 guint32
 218 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 219 {
 220         char buf [1024];
 221         guint32 opts = 0;
 222
 223         *exclude_mask = 0;
 224
 225 #ifndef __linux__
 226         if (!sysinfo (SI_ISALIST, buf, 1024))
 227                 g_assert_not_reached ();
 228 #else
 229         /* From glibc.  If the getpagesize is 8192, we're on sparc64, which
 230          * (in)directly implies that we're a v9 or better.
 231          * Improvements to this are greatly accepted...
 232          * Also, we don't differentiate between v7 and v8.  I sense SIGILL
 233          * sniffing in my future.
 234          */
 235         if (getpagesize() == 8192)
 236                 strcpy (buf, "sparcv9");
 237         else
 238                 strcpy (buf, "sparcv8");
 239 #endif
 240
 241         /*
 242          * On some processors, the cmov instructions are even slower than the
 243          * normal ones...
 244          */
 245         if (strstr (buf, "sparcv9")) {
 246                 opts |= MONO_OPT_CMOV | MONO_OPT_FCMOV;
 247                 sparcv9 = TRUE;
 248         }
 249         else
 250                 *exclude_mask |= MONO_OPT_CMOV | MONO_OPT_FCMOV;
 251
 252         return opts;
 253 }
 254
 255 static void
 256 mono_arch_break (void)
 257 {
 258 }
 259
 260 #ifdef __GNUC__
 261 #define flushi(addr)    __asm__ __volatile__ ("iflush %0"::"r"(addr):"memory")
 262 #else /* assume Sun's compiler */
 263 static void flushi(void *addr)
 264 {
 265     asm("flush %i0");
 266 }
 267 #endif
 268
 269 #ifndef __linux__
 270 void sync_instruction_memory(caddr_t addr, int len);
 271 #endif
 272
 273 void
 274 mono_arch_flush_icache (guint8 *code, gint size)
 275 {
 276 #ifndef __linux__
 277         /* Hopefully this is optimized based on the actual CPU */
 278         sync_instruction_memory (code, size);
 279 #else
 280         guint64 *p = (guint64*)code;
 281         guint64 *end = (guint64*)(code + ((size + 8) /8));
 282
 283         /*
 284          * FIXME: Flushing code in dword chunks in _slow_.
 285          */
 286         while (p < end)
 287 #ifdef __GNUC__
 288                 __asm__ __volatile__ ("iflush %0"::"r"(p++));
 289 #else
 290                         flushi (p ++);
 291 #endif
 292 #endif
 293 }
 294
 295 /*
 296  * mono_sparc_flushw:
 297  *
 298  * Flush all register windows to memory. Every register window is saved to
 299  * a 16 word area on the stack pointed to by its %sp register.
 300  */
 301 void
 302 mono_sparc_flushw (void)
 303 {
 304         static guint32 start [64];
 305         static int inited = 0;
 306         guint32 *code;
 307         static void (*flushw) (void);
 308
 309         if (!inited) {
 310                 code = start;
 311
 312                 sparc_save_imm (code, sparc_sp, -160, sparc_sp);
 313                 sparc_flushw (code);
 314                 sparc_ret (code);
 315                 sparc_restore_simple (code);
 316
 317                 g_assert ((code - start) < 64);
 318
 319                 mono_arch_flush_icache ((guint8*)start, (guint8*)code - (guint8*)start);
 320
 321                 flushw = (gpointer)start;
 322
 323                 inited = 1;
 324         }
 325
 326         flushw ();
 327 }
 328
 329 void
 330 mono_arch_flush_register_windows (void)
 331 {
 332         mono_sparc_flushw ();
 333 }
 334
 335 gboolean
 336 mono_arch_is_inst_imm (gint64 imm)
 337 {
 338         return sparc_is_imm13 (imm);
 339 }
 340
 341 gboolean
 342 mono_sparc_is_v9 (void) {
 343         return sparcv9;
 344 }
 345
 346 gboolean
 347 mono_sparc_is_sparc64 (void) {
 348         return v64;
 349 }
 350
 351 typedef enum {
 352         ArgInIReg,
 353         ArgInIRegPair,
 354         ArgInSplitRegStack,
 355         ArgInFReg,
 356         ArgInFRegPair,
 357         ArgOnStack,
 358         ArgOnStackPair,
 359         ArgInFloatReg,  /* V9 only */
 360         ArgInDoubleReg  /* V9 only */
 361 } ArgStorage;
 362
 363 typedef struct {
 364         gint16 offset;
 365         /* This needs to be offset by %i0 or %o0 depending on caller/callee */
 366         gint8  reg;
 367         ArgStorage storage;
 368         guint32 vt_offset; /* for valuetypes */
 369 } ArgInfo;
 370
 371 typedef struct {
 372         int nargs;
 373         guint32 stack_usage;
 374         guint32 reg_usage;
 375         ArgInfo ret;
 376         ArgInfo sig_cookie;
 377         ArgInfo args [1];
 378 } CallInfo;
 379
 380 #define DEBUG(a)
 381
 382 /* %o0..%o5 */
 383 #define PARAM_REGS 6
 384
 385 static void inline
 386 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean pair)
 387 {
 388         ainfo->offset = *stack_size;
 389
 390         if (!pair) {
 391                 if (*gr >= PARAM_REGS) {
 392                         ainfo->storage = ArgOnStack;
 393                 }
 394                 else {
 395                         ainfo->storage = ArgInIReg;
 396                         ainfo->reg = *gr;
 397                         (*gr) ++;
 398                 }
 399
 400                 /* Allways reserve stack space for parameters passed in registers */
 401                 (*stack_size) += sizeof (gpointer);
 402         }
 403         else {
 404                 if (*gr < PARAM_REGS - 1) {
 405                         /* A pair of registers */
 406                         ainfo->storage = ArgInIRegPair;
 407                         ainfo->reg = *gr;
 408                         (*gr) += 2;
 409                 }
 410                 else if (*gr >= PARAM_REGS) {
 411                         /* A pair of stack locations */
 412                         ainfo->storage = ArgOnStackPair;
 413                 }
 414                 else {
 415                         ainfo->storage = ArgInSplitRegStack;
 416                         ainfo->reg = *gr;
 417                         (*gr) ++;
 418                 }
 419
 420                 (*stack_size) += 2 * sizeof (gpointer);
 421         }
 422 }
 423
 424 #ifdef SPARCV9
 425
 426 #define FLOAT_PARAM_REGS 32
 427
 428 static void inline
 429 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean single)
 430 {
 431         ainfo->offset = *stack_size;
 432
 433         if (single) {
 434                 if (*gr >= FLOAT_PARAM_REGS) {
 435                         ainfo->storage = ArgOnStack;
 436                 }
 437                 else {
 438                         /* A single is passed in an even numbered fp register */
 439                         ainfo->storage = ArgInFloatReg;
 440                         ainfo->reg = *gr + 1;
 441                         (*gr) += 2;
 442                 }
 443         }
 444         else {
 445                 if (*gr < FLOAT_PARAM_REGS) {
 446                         /* A double register */
 447                         ainfo->storage = ArgInDoubleReg;
 448                         ainfo->reg = *gr;
 449                         (*gr) += 2;
 450                 }
 451                 else {
 452                         ainfo->storage = ArgOnStack;
 453                 }
 454         }
 455
 456         (*stack_size) += sizeof (gpointer);
 457 }
 458
 459 #endif
 460
 461 /*
 462  * get_call_info:
 463  *
 464  *  Obtain information about a call according to the calling convention.
 465  * For V8, see the "System V ABI, Sparc Processor Supplement" Sparc V8 version
 466  * document for more information.
 467  * For V9, see the "Low Level System Information (64-bit psABI)" chapter in
 468  * the 'Sparc Compliance Definition 2.4' document.
 469  */
 470 static CallInfo*
 471 get_call_info (MonoMethodSignature *sig, gboolean is_pinvoke)
 472 {
 473         guint32 i, gr, fr;
 474         int n = sig->hasthis + sig->param_count;
 475         guint32 stack_size = 0;
 476         CallInfo *cinfo;
 477
 478         cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 479
 480         gr = 0;
 481         fr = 0;
 482
 483 #ifdef SPARCV9
 484         if (MONO_TYPE_ISSTRUCT ((sig->ret))) {
 485                 /* The address of the return value is passed in %o0 */
 486                 add_general (&gr, &stack_size, &cinfo->ret, FALSE);
 487                 cinfo->ret.reg += sparc_i0;
 488         }
 489 #endif
 490
 491         /* this */
 492         if (sig->hasthis)
 493                 add_general (&gr, &stack_size, cinfo->args + 0, FALSE);
 494
 495         if ((sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 496                 gr = PARAM_REGS;
 497
 498                 /* Emit the signature cookie just before the implicit arguments */
 499                 add_general (&gr, &stack_size, &cinfo->sig_cookie, FALSE);
 500         }
 501
 502         for (i = 0; i < sig->param_count; ++i) {
 503                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 504
 505                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 506                         gr = PARAM_REGS;
 507
 508                         /* Emit the signature cookie just before the implicit arguments */
 509                         add_general (&gr, &stack_size, &cinfo->sig_cookie, FALSE);
 510                 }
 511
 512                 DEBUG(printf("param %d: ", i));
 513                 if (sig->params [i]->byref) {
 514                         DEBUG(printf("byref\n"));
 515
 516                         add_general (&gr, &stack_size, ainfo, FALSE);
 517                         continue;
 518                 }
 519                 switch (mono_type_get_underlying_type (sig->params [i])->type) {
 520                 case MONO_TYPE_BOOLEAN:
 521                 case MONO_TYPE_I1:
 522                 case MONO_TYPE_U1:
 523                         add_general (&gr, &stack_size, ainfo, FALSE);
 524                         /* the value is in the ls byte */
 525                         ainfo->offset += sizeof (gpointer) - 1;
 526                         break;
 527                 case MONO_TYPE_I2:
 528                 case MONO_TYPE_U2:
 529                 case MONO_TYPE_CHAR:
 530                         add_general (&gr, &stack_size, ainfo, FALSE);
 531                         /* the value is in the ls word */
 532                         ainfo->offset += sizeof (gpointer) - 2;
 533                         break;
 534                 case MONO_TYPE_I4:
 535                 case MONO_TYPE_U4:
 536                         add_general (&gr, &stack_size, ainfo, FALSE);
 537                         /* the value is in the ls dword */
 538                         ainfo->offset += sizeof (gpointer) - 4;
 539                         break;
 540                 case MONO_TYPE_I:
 541                 case MONO_TYPE_U:
 542                 case MONO_TYPE_PTR:
 543                 case MONO_TYPE_FNPTR:
 544                 case MONO_TYPE_CLASS:
 545                 case MONO_TYPE_OBJECT:
 546                 case MONO_TYPE_STRING:
 547                 case MONO_TYPE_SZARRAY:
 548                 case MONO_TYPE_ARRAY:
 549                         add_general (&gr, &stack_size, ainfo, FALSE);
 550                         break;
 551                 case MONO_TYPE_GENERICINST:
 552                         if (!mono_type_generic_inst_is_valuetype (sig->params [i])) {
 553                                 add_general (&gr, &stack_size, ainfo, FALSE);
 554                                 break;
 555                         }
 556                         /* Fall through */
 557                 case MONO_TYPE_VALUETYPE:
 558 #ifdef SPARCV9
 559                         if (sig->pinvoke)
 560                                 NOT_IMPLEMENTED;
 561 #endif
 562                         add_general (&gr, &stack_size, ainfo, FALSE);
 563                         break;
 564                 case MONO_TYPE_TYPEDBYREF:
 565                         add_general (&gr, &stack_size, ainfo, FALSE);
 566                         break;
 567                 case MONO_TYPE_U8:
 568                 case MONO_TYPE_I8:
 569 #ifdef SPARCV9
 570                         add_general (&gr, &stack_size, ainfo, FALSE);
 571 #else
 572                         add_general (&gr, &stack_size, ainfo, TRUE);
 573 #endif
 574                         break;
 575                 case MONO_TYPE_R4:
 576 #ifdef SPARCV9
 577                         add_float (&fr, &stack_size, ainfo, TRUE);
 578                         gr ++;
 579 #else
 580                         /* single precision values are passed in integer registers */
 581                         add_general (&gr, &stack_size, ainfo, FALSE);
 582 #endif
 583                         break;
 584                 case MONO_TYPE_R8:
 585 #ifdef SPARCV9
 586                         add_float (&fr, &stack_size, ainfo, FALSE);
 587                         gr ++;
 588 #else
 589                         /* double precision values are passed in a pair of registers */
 590                         add_general (&gr, &stack_size, ainfo, TRUE);
 591 #endif
 592                         break;
 593                 default:
 594                         g_assert_not_reached ();
 595                 }
 596         }
 597
 598         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 599                 gr = PARAM_REGS;
 600
 601                 /* Emit the signature cookie just before the implicit arguments */
 602                 add_general (&gr, &stack_size, &cinfo->sig_cookie, FALSE);
 603         }
 604
 605         /* return value */
 606         {
 607                 switch (mono_type_get_underlying_type (sig->ret)->type) {
 608                 case MONO_TYPE_BOOLEAN:
 609                 case MONO_TYPE_I1:
 610                 case MONO_TYPE_U1:
 611                 case MONO_TYPE_I2:
 612                 case MONO_TYPE_U2:
 613                 case MONO_TYPE_CHAR:
 614                 case MONO_TYPE_I4:
 615                 case MONO_TYPE_U4:
 616                 case MONO_TYPE_I:
 617                 case MONO_TYPE_U:
 618                 case MONO_TYPE_PTR:
 619                 case MONO_TYPE_FNPTR:
 620                 case MONO_TYPE_CLASS:
 621                 case MONO_TYPE_OBJECT:
 622                 case MONO_TYPE_SZARRAY:
 623                 case MONO_TYPE_ARRAY:
 624                 case MONO_TYPE_STRING:
 625                         cinfo->ret.storage = ArgInIReg;
 626                         cinfo->ret.reg = sparc_i0;
 627                         if (gr < 1)
 628                                 gr = 1;
 629                         break;
 630                 case MONO_TYPE_U8:
 631                 case MONO_TYPE_I8:
 632 #ifdef SPARCV9
 633                         cinfo->ret.storage = ArgInIReg;
 634                         cinfo->ret.reg = sparc_i0;
 635                         if (gr < 1)
 636                                 gr = 1;
 637 #else
 638                         cinfo->ret.storage = ArgInIRegPair;
 639                         cinfo->ret.reg = sparc_i0;
 640                         if (gr < 2)
 641                                 gr = 2;
 642 #endif
 643                         break;
 644                 case MONO_TYPE_R4:
 645                 case MONO_TYPE_R8:
 646                         cinfo->ret.storage = ArgInFReg;
 647                         cinfo->ret.reg = sparc_f0;
 648                         break;
 649                 case MONO_TYPE_GENERICINST:
 650                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 651                                 cinfo->ret.storage = ArgInIReg;
 652                                 cinfo->ret.reg = sparc_i0;
 653                                 if (gr < 1)
 654                                         gr = 1;
 655                                 break;
 656                         }
 657                         /* Fall through */
 658                 case MONO_TYPE_VALUETYPE:
 659                         if (v64) {
 660                                 if (sig->pinvoke)
 661                                         NOT_IMPLEMENTED;
 662                                 else
 663                                         /* Already done */
 664                                         ;
 665                         }
 666                         else
 667                                 cinfo->ret.storage = ArgOnStack;
 668                         break;
 669                 case MONO_TYPE_TYPEDBYREF:
 670                         if (v64) {
 671                                 if (sig->pinvoke)
 672                                         /* Same as a valuetype with size 24 */
 673                                         NOT_IMPLEMENTED;
 674                                 else
 675                                         /* Already done */
 676                                         ;
 677                         }
 678                         else
 679                                 cinfo->ret.storage = ArgOnStack;
 680                         break;
 681                 case MONO_TYPE_VOID:
 682                         break;
 683                 default:
 684                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 685                 }
 686         }
 687
 688         cinfo->stack_usage = stack_size;
 689         cinfo->reg_usage = gr;
 690         return cinfo;
 691 }
 692
 693 static gboolean
 694 is_regsize_var (MonoType *t) {
 695         if (t->byref)
 696                 return TRUE;
 697         switch (mono_type_get_underlying_type (t)->type) {
 698         case MONO_TYPE_BOOLEAN:
 699         case MONO_TYPE_CHAR:
 700         case MONO_TYPE_I1:
 701         case MONO_TYPE_U1:
 702         case MONO_TYPE_I2:
 703         case MONO_TYPE_U2:
 704         case MONO_TYPE_I4:
 705         case MONO_TYPE_U4:
 706         case MONO_TYPE_I:
 707         case MONO_TYPE_U:
 708         case MONO_TYPE_PTR:
 709         case MONO_TYPE_FNPTR:
 710                 return TRUE;
 711         case MONO_TYPE_OBJECT:
 712         case MONO_TYPE_STRING:
 713         case MONO_TYPE_CLASS:
 714         case MONO_TYPE_SZARRAY:
 715         case MONO_TYPE_ARRAY:
 716                 return TRUE;
 717         case MONO_TYPE_VALUETYPE:
 718                 return FALSE;
 719 #ifdef SPARCV9
 720         case MONO_TYPE_I8:
 721         case MONO_TYPE_U8:
 722                 return TRUE;
 723 #endif
 724         }
 725         return FALSE;
 726 }
 727
 728 GList *
 729 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 730 {
 731         GList *vars = NULL;
 732         int i;
 733
 734         /*
 735          * FIXME: If an argument is allocated to a register, then load it from the
 736          * stack in the prolog.
 737          */
 738
 739         for (i = 0; i < cfg->num_varinfo; i++) {
 740                 MonoInst *ins = cfg->varinfo [i];
 741                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 742
 743                 /* unused vars */
 744                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 745                         continue;
 746
 747                 /* FIXME: Make arguments on stack allocateable to registers */
 748                 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode == OP_REGVAR) || (ins->opcode == OP_ARG))
 749                         continue;
 750
 751                 if (is_regsize_var (ins->inst_vtype)) {
 752                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 753                         g_assert (i == vmv->idx);
 754
 755                         vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
 756                 }
 757         }
 758
 759         return vars;
 760 }
 761
 762 GList *
 763 mono_arch_get_global_int_regs (MonoCompile *cfg)
 764 {
 765         GList *regs = NULL;
 766         int i;
 767         MonoMethodSignature *sig;
 768         CallInfo *cinfo;
 769
 770         sig = mono_method_signature (cfg->method);
 771
 772         cinfo = get_call_info (sig, FALSE);
 773
 774         /* Use unused input registers */
 775         for (i = cinfo->reg_usage; i < 6; ++i)
 776                 regs = g_list_prepend (regs, GUINT_TO_POINTER (sparc_i0 + i));
 777
 778         /* Use %l0..%l6 as global registers */
 779         for (i = sparc_l0; i < sparc_l7; ++i)
 780                 regs = g_list_prepend (regs, GUINT_TO_POINTER (i));
 781
 782         g_free (cinfo);
 783
 784         return regs;
 785 }
 786
 787 /*
 788  * mono_arch_regalloc_cost:
 789  *
 790  *  Return the cost, in number of memory references, of the action of
 791  * allocating the variable VMV into a register during global register
 792  * allocation.
 793  */
 794 guint32
 795 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 796 {
 797         return 0;
 798 }
 799
 800 /*
 801  * Set var information according to the calling convention. sparc version.
 802  * The locals var stuff should most likely be split in another method.
 803  */
 804 void
 805 mono_arch_allocate_vars (MonoCompile *m)
 806 {
 807         MonoMethodSignature *sig;
 808         MonoMethodHeader *header;
 809         MonoInst *inst;
 810         int i, offset, size, align, curinst;
 811         CallInfo *cinfo;
 812
 813         header = mono_method_get_header (m->method);
 814
 815         sig = mono_method_signature (m->method);
 816
 817         cinfo = get_call_info (sig, FALSE);
 818
 819         if (sig->ret->type != MONO_TYPE_VOID) {
 820                 switch (cinfo->ret.storage) {
 821                 case ArgInIReg:
 822                 case ArgInFReg:
 823                 case ArgInIRegPair:
 824                         m->ret->opcode = OP_REGVAR;
 825                         m->ret->inst_c0 = cinfo->ret.reg;
 826                         break;
 827                 case ArgOnStack:
 828 #ifdef SPARCV9
 829                         g_assert_not_reached ();
 830 #else
 831                         /* valuetypes */
 832                         m->ret->opcode = OP_REGOFFSET;
 833                         m->ret->inst_basereg = sparc_fp;
 834                         m->ret->inst_offset = 64;
 835 #endif
 836                         break;
 837                 default:
 838                         NOT_IMPLEMENTED;
 839                 }
 840                 m->ret->dreg = m->ret->inst_c0;
 841         }
 842
 843         /*
 844          * We use the ABI calling conventions for managed code as well.
 845          * Exception: valuetypes are never returned in registers on V9.
 846          * FIXME: Use something more optimized.
 847          */
 848
 849         /* Locals are allocated backwards from %fp */
 850         m->frame_reg = sparc_fp;
 851         offset = 0;
 852
 853         /*
 854          * Reserve a stack slot for holding information used during exception
 855          * handling.
 856          */
 857         if (header->num_clauses)
 858                 offset += sizeof (gpointer) * 2;
 859
 860         if (m->method->save_lmf) {
 861                 offset += sizeof (MonoLMF);
 862                 m->arch.lmf_offset = offset;
 863         }
 864
 865         curinst = m->locals_start;
 866         for (i = curinst; i < m->num_varinfo; ++i) {
 867                 inst = m->varinfo [i];
 868
 869                 if (inst->opcode == OP_REGVAR) {
 870                         //g_print ("allocating local %d to %s\n", i, mono_arch_regname (inst->dreg));
 871                         continue;
 872                 }
 873
 874                 if (inst->flags & MONO_INST_IS_DEAD)
 875                         continue;
 876
 877                 /* inst->backend.is_pinvoke indicates native sized value types, this is used by the
 878                 * pinvoke wrappers when they call functions returning structure */
 879                 if (inst->backend.is_pinvoke && MONO_TYPE_ISSTRUCT (inst->inst_vtype) && inst->inst_vtype->type != MONO_TYPE_TYPEDBYREF)
 880                         size = mono_class_native_size (inst->inst_vtype->data.klass, &align);
 881                 else
 882                         size = mono_type_stack_size (inst->inst_vtype, &align);
 883
 884                 /*
 885                  * This is needed since structures containing doubles must be doubleword
 886          * aligned.
 887                  * FIXME: Do this only if needed.
 888                  */
 889                 if (MONO_TYPE_ISSTRUCT (inst->inst_vtype))
 890                         align = 8;
 891
 892                 /*
 893                  * variables are accessed as negative offsets from %fp, so increase
 894                  * the offset before assigning it to a variable
 895                  */
 896                 offset += size;
 897
 898                 offset += align - 1;
 899                 offset &= ~(align - 1);
 900                 inst->opcode = OP_REGOFFSET;
 901                 inst->inst_basereg = sparc_fp;
 902                 inst->inst_offset = STACK_BIAS + -offset;
 903
 904                 //g_print ("allocating local %d to [%s - %d]\n", i, mono_arch_regname (inst->inst_basereg), - inst->inst_offset);
 905         }
 906
 907         if (sig->call_convention == MONO_CALL_VARARG) {
 908                 m->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
 909         }
 910
 911         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 912                 inst = m->varinfo [i];
 913                 if (inst->opcode != OP_REGVAR) {
 914                         ArgInfo *ainfo = &cinfo->args [i];
 915                         gboolean inreg = TRUE;
 916                         MonoType *arg_type;
 917                         ArgStorage storage;
 918
 919                         if (sig->hasthis && (i == 0))
 920                                 arg_type = &mono_defaults.object_class->byval_arg;
 921                         else
 922                                 arg_type = sig->params [i - sig->hasthis];
 923
 924 #ifndef SPARCV9
 925                         if (!arg_type->byref && ((arg_type->type == MONO_TYPE_R4)
 926                                                                          || (arg_type->type == MONO_TYPE_R8)))
 927                                 /*
 928                                  * Since float arguments are passed in integer registers, we need to
 929                                  * save them to the stack in the prolog.
 930                                  */
 931                                 inreg = FALSE;
 932 #endif
 933
 934                         /* FIXME: Allocate volatile arguments to registers */
 935                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 936                                 inreg = FALSE;
 937
 938                         if (MONO_TYPE_ISSTRUCT (arg_type))
 939                                 /* FIXME: this isn't needed */
 940                                 inreg = FALSE;
 941
 942                         inst->opcode = OP_REGOFFSET;
 943
 944                         if (!inreg)
 945                                 storage = ArgOnStack;
 946                         else
 947                                 storage = ainfo->storage;
 948
 949                         switch (storage) {
 950                         case ArgInIReg:
 951                         case ArgInIRegPair:
 952                                 inst->opcode = OP_REGVAR;
 953                                 inst->dreg = sparc_i0 + ainfo->reg;
 954                                 break;
 955                         case ArgInFloatReg:
 956                         case ArgInDoubleReg:
 957                                 /*
 958                                  * Since float regs are volatile, we save the arguments to
 959                                  * the stack in the prolog.
 960                                  * FIXME: Avoid this if the method contains no calls.
 961                                  */
 962                         case ArgOnStack:
 963                         case ArgOnStackPair:
 964                         case ArgInSplitRegStack:
 965                                 /* Split arguments are saved to the stack in the prolog */
 966                                 inst->opcode = OP_REGOFFSET;
 967                                 /* in parent frame */
 968                                 inst->inst_basereg = sparc_fp;
 969                                 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
 970
 971                                 if (!arg_type->byref && (arg_type->type == MONO_TYPE_R8)) {
 972                                         /*
 973                                          * It is very hard to load doubles from non-doubleword aligned
 974                                          * memory locations. So if the offset is misaligned, we copy the
 975                                          * argument to a stack location in the prolog.
 976                                          */
 977                                         if ((inst->inst_offset - STACK_BIAS) % 8) {
 978                                                 inst->inst_basereg = sparc_fp;
 979                                                 offset += 8;
 980                                                 align = 8;
 981                                                 offset += align - 1;
 982                                                 offset &= ~(align - 1);
 983                                                 inst->inst_offset = STACK_BIAS + -offset;
 984
 985                                         }
 986                                 }
 987                                 break;
 988                         default:
 989                                 NOT_IMPLEMENTED;
 990                         }
 991
 992                         if (MONO_TYPE_ISSTRUCT (arg_type)) {
 993                                 /* Add a level of indirection */
 994                                 /*
 995                                  * It would be easier to add OP_LDIND_I here, but ldind_i instructions
 996                                  * are destructively modified in a lot of places in inssel.brg.
 997                                  */
 998                                 MonoInst *indir;
 999                                 MONO_INST_NEW (m, indir, 0);
1000                                 *indir = *inst;
1001                                 inst->opcode = OP_SPARC_INARG_VT;
1002                                 inst->inst_left = indir;
1003                         }
1004                 }
1005         }
1006
1007         /*
1008          * spillvars are stored between the normal locals and the storage reserved
1009          * by the ABI.
1010          */
1011
1012         m->stack_offset = offset;
1013
1014         /* Add a properly aligned dword for use by int<->float conversion opcodes */
1015         m->spill_count ++;
1016         mono_spillvar_offset_float (m, 0);
1017
1018         g_free (cinfo);
1019 }
1020
1021 static MonoInst *
1022 make_group (MonoCompile *cfg, MonoInst *left, int basereg, int offset)
1023 {
1024         MonoInst *group;
1025
1026         MONO_INST_NEW (cfg, group, OP_GROUP);
1027         group->inst_left = left;
1028         group->inst_basereg = basereg;
1029         group->inst_imm = offset;
1030
1031         return group;
1032 }
1033
1034 static void
1035 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1036 {
1037         MonoInst *arg;
1038         MonoMethodSignature *tmp_sig;
1039         MonoInst *sig_arg;
1040
1041         /*
1042          * mono_ArgIterator_Setup assumes the signature cookie is
1043          * passed first and all the arguments which were before it are
1044          * passed on the stack after the signature. So compensate by
1045          * passing a different signature.
1046          */
1047         tmp_sig = mono_metadata_signature_dup (call->signature);
1048         tmp_sig->param_count -= call->signature->sentinelpos;
1049         tmp_sig->sentinelpos = 0;
1050         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1051
1052         /* FIXME: Add support for signature tokens to AOT */
1053         cfg->disable_aot = TRUE;
1054         /* We allways pass the signature on the stack for simplicity */
1055         MONO_INST_NEW (cfg, arg, OP_SPARC_OUTARG_MEM);
1056         arg->inst_right = make_group (cfg, (MonoInst*)call, sparc_sp, ARGS_OFFSET + cinfo->sig_cookie.offset);
1057         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1058         sig_arg->inst_p0 = tmp_sig;
1059         arg->inst_left = sig_arg;
1060         arg->type = STACK_PTR;
1061         /* prepend, so they get reversed */
1062         arg->next = call->out_args;
1063         call->out_args = arg;
1064 }
1065
1066 /*
1067  * take the arguments and generate the arch-specific
1068  * instructions to properly call the function in call.
1069  * This includes pushing, moving arguments to the right register
1070  * etc.
1071  */
1072 MonoCallInst*
1073 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1074         MonoInst *arg, *in;
1075         MonoMethodSignature *sig;
1076         int i, n;
1077         CallInfo *cinfo;
1078         ArgInfo *ainfo;
1079         guint32 extra_space = 0;
1080
1081         sig = call->signature;
1082         n = sig->param_count + sig->hasthis;
1083
1084         cinfo = get_call_info (sig, sig->pinvoke);
1085
1086         for (i = 0; i < n; ++i) {
1087                 ainfo = cinfo->args + i;
1088
1089                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1090                         /* Emit the signature cookie just before the first implicit argument */
1091                         emit_sig_cookie (cfg, call, cinfo);
1092                 }
1093
1094                 if (is_virtual && i == 0) {
1095                         /* the argument will be attached to the call instruction */
1096                         in = call->args [i];
1097                 } else {
1098                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1099                         in = call->args [i];
1100                         arg->cil_code = in->cil_code;
1101                         arg->inst_left = in;
1102                         arg->type = in->type;
1103                         /* prepend, we'll need to reverse them later */
1104                         arg->next = call->out_args;
1105                         call->out_args = arg;
1106
1107                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1108                                 MonoInst *inst;
1109                                 gint align;
1110                                 guint32 offset, pad;
1111                                 guint32 size;
1112
1113 #ifdef SPARCV9
1114                                 if (sig->pinvoke)
1115                                         NOT_IMPLEMENTED;
1116 #endif
1117
1118                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1119                                         size = sizeof (MonoTypedRef);
1120                                         align = sizeof (gpointer);
1121                                 }
1122                                 else
1123                                 if (sig->pinvoke)
1124                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1125                                 else {
1126                                         /*
1127                                          * Can't use mono_type_stack_size (), but that
1128                                          * aligns the size to sizeof (gpointer), which is larger
1129                                          * than the size of the source, leading to reads of invalid
1130                                          * memory if the source is at the end of address space or
1131                                          * misaligned reads.
1132                                          */
1133                                         size = mono_class_value_size (in->klass, &align);
1134                                 }
1135
1136                                 /*
1137                                  * We use OP_OUTARG_VT to copy the valuetype to a stack location, then
1138                                  * use the normal OUTARG opcodes to pass the address of the location to
1139                                  * the callee.
1140                                  */
1141                                 MONO_INST_NEW (cfg, inst, OP_OUTARG_VT);
1142                                 inst->inst_left = in;
1143
1144                                 /* The first 6 argument locations are reserved */
1145                                 if (cinfo->stack_usage < 6 * sizeof (gpointer))
1146                                         cinfo->stack_usage = 6 * sizeof (gpointer);
1147
1148                                 offset = ALIGN_TO ((ARGS_OFFSET - STACK_BIAS) + cinfo->stack_usage, align);
1149                                 pad = offset - ((ARGS_OFFSET - STACK_BIAS) + cinfo->stack_usage);
1150
1151                                 inst->inst_c1 = STACK_BIAS + offset;
1152                                 inst->backend.size = size;
1153                                 arg->inst_left = inst;
1154
1155                                 cinfo->stack_usage += size;
1156                                 cinfo->stack_usage += pad;
1157                         }
1158
1159                         arg->inst_right = make_group (cfg, (MonoInst*)call, sparc_sp, ARGS_OFFSET + ainfo->offset);
1160
1161                         switch (ainfo->storage) {
1162                         case ArgInIReg:
1163                         case ArgInFReg:
1164                         case ArgInIRegPair:
1165                                 if (ainfo->storage == ArgInIRegPair)
1166                                         arg->opcode = OP_SPARC_OUTARG_REGPAIR;
1167                                 arg->backend.reg3 = sparc_o0 + ainfo->reg;
1168                                 call->used_iregs |= 1 << ainfo->reg;
1169
1170                                 if ((i >= sig->hasthis) && !sig->params [i - sig->hasthis]->byref && ((sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) || (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4))) {
1171                                         /* An fp value is passed in an ireg */
1172
1173                                         if (arg->opcode == OP_SPARC_OUTARG_REGPAIR)
1174                                                 arg->opcode = OP_SPARC_OUTARG_REGPAIR_FLOAT;
1175                                         else
1176                                                 arg->opcode = OP_SPARC_OUTARG_FLOAT;
1177
1178                                         /*
1179                                          * The OUTARG (freg) implementation needs an extra dword to store
1180                                          * the temporary value.
1181                                          */
1182                                         extra_space += 8;
1183                                 }
1184                                 break;
1185                         case ArgOnStack:
1186                                 arg->opcode = OP_SPARC_OUTARG_MEM;
1187                                 break;
1188                         case ArgOnStackPair:
1189                                 arg->opcode = OP_SPARC_OUTARG_MEMPAIR;
1190                                 break;
1191                         case ArgInSplitRegStack:
1192                                 arg->opcode = OP_SPARC_OUTARG_SPLIT_REG_STACK;
1193                                 arg->backend.reg3 = sparc_o0 + ainfo->reg;
1194                                 call->used_iregs |= 1 << ainfo->reg;
1195                                 break;
1196                         case ArgInFloatReg:
1197                                 arg->opcode = OP_SPARC_OUTARG_FLOAT_REG;
1198                                 arg->backend.reg3 = sparc_f0 + ainfo->reg;
1199                                 break;
1200                         case ArgInDoubleReg:
1201                                 arg->opcode = OP_SPARC_OUTARG_DOUBLE_REG;
1202                                 arg->backend.reg3 = sparc_f0 + ainfo->reg;
1203                                 break;
1204                         default:
1205                                 NOT_IMPLEMENTED;
1206                         }
1207                 }
1208         }
1209
1210         /* Handle the case where there are no implicit arguments */
1211         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1212                 emit_sig_cookie (cfg, call, cinfo);
1213         }
1214
1215         /*
1216          * Reverse the call->out_args list.
1217          */
1218         {
1219                 MonoInst *prev = NULL, *list = call->out_args, *next;
1220                 while (list) {
1221                         next = list->next;
1222                         list->next = prev;
1223                         prev = list;
1224                         list = next;
1225                 }
1226                 call->out_args = prev;
1227         }
1228         call->stack_usage = cinfo->stack_usage + extra_space;
1229         call->out_ireg_args = NULL;
1230         call->out_freg_args = NULL;
1231         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1232         cfg->flags |= MONO_CFG_HAS_CALLS;
1233
1234         g_free (cinfo);
1235         return call;
1236 }
1237
1238 /* Map opcode to the sparc condition codes */
1239 static inline SparcCond
1240 opcode_to_sparc_cond (int opcode)
1241 {
1242         switch (opcode) {
1243         case OP_FBGE:
1244                 return sparc_fbge;
1245         case OP_FBLE:
1246                 return sparc_fble;
1247         case OP_FBEQ:
1248         case OP_FCEQ:
1249                 return sparc_fbe;
1250         case OP_FBLT:
1251         case OP_FCLT:
1252         case OP_FCLT_UN:
1253                 return sparc_fbl;
1254         case OP_FBGT:
1255         case OP_FCGT:
1256         case OP_FCGT_UN:
1257                 return sparc_fbg;
1258         case CEE_BEQ:
1259         case OP_IBEQ:
1260         case OP_CEQ:
1261         case OP_ICEQ:
1262         case OP_COND_EXC_EQ:
1263                 return sparc_be;
1264         case CEE_BNE_UN:
1265         case OP_COND_EXC_NE_UN:
1266         case OP_IBNE_UN:
1267                 return sparc_bne;
1268         case CEE_BLT:
1269         case OP_IBLT:
1270         case OP_CLT:
1271         case OP_ICLT:
1272         case OP_COND_EXC_LT:
1273                 return sparc_bl;
1274         case CEE_BLT_UN:
1275         case OP_IBLT_UN:
1276         case OP_CLT_UN:
1277         case OP_ICLT_UN:
1278         case OP_COND_EXC_LT_UN:
1279                 return sparc_blu;
1280         case CEE_BGT:
1281         case OP_IBGT:
1282         case OP_CGT:
1283         case OP_ICGT:
1284         case OP_COND_EXC_GT:
1285                 return sparc_bg;
1286         case CEE_BGT_UN:
1287         case OP_IBGT_UN:
1288         case OP_CGT_UN:
1289         case OP_ICGT_UN:
1290         case OP_COND_EXC_GT_UN:
1291                 return sparc_bgu;
1292         case CEE_BGE:
1293         case OP_IBGE:
1294         case OP_COND_EXC_GE:
1295                 return sparc_bge;
1296         case CEE_BGE_UN:
1297         case OP_IBGE_UN:
1298         case OP_COND_EXC_GE_UN:
1299                 return sparc_beu;
1300         case CEE_BLE:
1301         case OP_IBLE:
1302         case OP_COND_EXC_LE:
1303                 return sparc_ble;
1304         case CEE_BLE_UN:
1305         case OP_IBLE_UN:
1306         case OP_COND_EXC_LE_UN:
1307                 return sparc_bleu;
1308         case OP_COND_EXC_OV:
1309         case OP_COND_EXC_IOV:
1310                 return sparc_bvs;
1311         case OP_COND_EXC_C:
1312         case OP_COND_EXC_IC:
1313                 return sparc_bcs;
1314         case OP_COND_EXC_NO:
1315         case OP_COND_EXC_NC:
1316                 NOT_IMPLEMENTED;
1317         default:
1318                 g_assert_not_reached ();
1319                 return sparc_be;
1320         }
1321 }
1322
1323 #define COMPUTE_DISP(ins) \
1324 if (ins->flags & MONO_INST_BRLABEL) { \
1325         if (ins->inst_i0->inst_c0) \
1326            disp = (ins->inst_i0->inst_c0 - ((guint8*)code - cfg->native_code)) >> 2; \
1327         else { \
1328             disp = 0; \
1329                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1330         } \
1331 } else { \
1332         if (ins->inst_true_bb->native_offset) \
1333            disp = (ins->inst_true_bb->native_offset - ((guint8*)code - cfg->native_code)) >> 2; \
1334         else { \
1335             disp = 0; \
1336                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1337         } \
1338 }
1339
1340 #ifdef SPARCV9
1341 #define DEFAULT_ICC sparc_xcc_short
1342 #else
1343 #define DEFAULT_ICC sparc_icc_short
1344 #endif
1345
1346 #ifdef SPARCV9
1347 #define EMIT_COND_BRANCH_ICC(ins,cond,annul,filldelay,icc) \
1348     do { \
1349         gint32 disp; \
1350         guint32 predict; \
1351         COMPUTE_DISP(ins); \
1352         predict = (disp != 0) ? 1 : 0; \
1353         g_assert (sparc_is_imm19 (disp)); \
1354         sparc_branchp (code, (annul), cond, icc, (predict), disp); \
1355         if (filldelay) sparc_nop (code); \
1356     } while (0)
1357 #define EMIT_COND_BRANCH(ins,cond,annul,filldelay) EMIT_COND_BRANCH_ICC ((ins), (cond), (annul), (filldelay), (sparc_xcc_short))
1358 #define EMIT_FLOAT_COND_BRANCH(ins,cond,annul,filldelay) \
1359     do { \
1360         gint32 disp; \
1361         guint32 predict; \
1362         COMPUTE_DISP(ins); \
1363         predict = (disp != 0) ? 1 : 0; \
1364         g_assert (sparc_is_imm19 (disp)); \
1365         sparc_fbranch (code, (annul), cond, disp); \
1366         if (filldelay) sparc_nop (code); \
1367     } while (0)
1368 #else
1369 #define EMIT_COND_BRANCH_ICC(ins,cond,annul,filldelay,icc) g_assert_not_reached ()
1370 #define EMIT_COND_BRANCH_GENERAL(ins,bop,cond,annul,filldelay) \
1371     do { \
1372         gint32 disp; \
1373         COMPUTE_DISP(ins); \
1374         g_assert (sparc_is_imm22 (disp)); \
1375         sparc_ ## bop (code, (annul), cond, disp); \
1376         if (filldelay) sparc_nop (code); \
1377     } while (0)
1378 #define EMIT_COND_BRANCH(ins,cond,annul,filldelay) EMIT_COND_BRANCH_GENERAL((ins),branch,(cond),annul,filldelay)
1379 #define EMIT_FLOAT_COND_BRANCH(ins,cond,annul,filldelay) EMIT_COND_BRANCH_GENERAL((ins),fbranch,(cond),annul,filldelay)
1380 #endif
1381
1382 #define EMIT_COND_BRANCH_PREDICTED(ins,cond,annul,filldelay) \
1383     do { \
1384             gint32 disp; \
1385         guint32 predict; \
1386         COMPUTE_DISP(ins); \
1387         predict = (disp != 0) ? 1 : 0; \
1388         g_assert (sparc_is_imm19 (disp)); \
1389                 sparc_branchp (code, (annul), (cond), DEFAULT_ICC, (predict), disp); \
1390         if (filldelay) sparc_nop (code); \
1391     } while (0)
1392
1393 #define EMIT_COND_BRANCH_BPR(ins,bop,predict,annul,filldelay) \
1394     do { \
1395             gint32 disp; \
1396         COMPUTE_DISP(ins); \
1397                 g_assert (sparc_is_imm22 (disp)); \
1398                 sparc_ ## bop (code, (annul), (predict), ins->sreg1, disp); \
1399         if (filldelay) sparc_nop (code); \
1400     } while (0)
1401
1402 /* emit an exception if condition is fail */
1403 /*
1404  * We put the exception throwing code out-of-line, at the end of the method
1405  */
1406 #define EMIT_COND_SYSTEM_EXCEPTION_GENERAL(ins,cond,sexc_name,filldelay,icc) do {     \
1407                 mono_add_patch_info (cfg, (guint8*)(code) - (cfg)->native_code,   \
1408                                     MONO_PATCH_INFO_EXC, sexc_name);  \
1409         if (sparcv9) { \
1410            sparc_branchp (code, 0, (cond), (icc), 0, 0); \
1411         } \
1412         else { \
1413                         sparc_branch (code, 0, cond, 0);     \
1414         } \
1415         if (filldelay) sparc_nop (code);     \
1416         } while (0);
1417
1418 #define EMIT_COND_SYSTEM_EXCEPTION(ins,cond,sexc_name) EMIT_COND_SYSTEM_EXCEPTION_GENERAL(ins,cond,sexc_name,TRUE,DEFAULT_ICC)
1419
1420 #define EMIT_COND_SYSTEM_EXCEPTION_BPR(ins,bop,sexc_name) do { \
1421                 mono_add_patch_info (cfg, (guint8*)(code) - (cfg)->native_code,   \
1422                                     MONO_PATCH_INFO_EXC, sexc_name);  \
1423                 sparc_ ## bop (code, FALSE, FALSE, ins->sreg1, 0); \
1424         sparc_nop (code);    \
1425 } while (0);
1426
1427 #define EMIT_ALU_IMM(ins,op,setcc) do { \
1428                         if (sparc_is_imm13 ((ins)->inst_imm)) \
1429                                 sparc_ ## op ## _imm (code, (setcc), (ins)->sreg1, ins->inst_imm, (ins)->dreg); \
1430                         else { \
1431                                 sparc_set (code, ins->inst_imm, sparc_o7); \
1432                                 sparc_ ## op (code, (setcc), (ins)->sreg1, sparc_o7, (ins)->dreg); \
1433                         } \
1434 } while (0);
1435
1436 #define EMIT_LOAD_MEMBASE(ins,op) do { \
1437                         if (sparc_is_imm13 (ins->inst_offset)) \
1438                                 sparc_ ## op ## _imm (code, ins->inst_basereg, ins->inst_offset, ins->dreg); \
1439                         else { \
1440                                 sparc_set (code, ins->inst_offset, sparc_o7); \
1441                                 sparc_ ## op (code, ins->inst_basereg, sparc_o7, ins->dreg); \
1442                         } \
1443 } while (0);
1444
1445 /* max len = 5 */
1446 #define EMIT_STORE_MEMBASE_IMM(ins,op) do { \
1447                         guint32 sreg; \
1448                         if (ins->inst_imm == 0) \
1449                                 sreg = sparc_g0; \
1450                         else { \
1451                                 sparc_set (code, ins->inst_imm, sparc_o7); \
1452                                 sreg = sparc_o7; \
1453                         } \
1454                         if (!sparc_is_imm13 (ins->inst_offset)) { \
1455                                 sparc_set (code, ins->inst_offset, GP_SCRATCH_REG); \
1456                                 sparc_ ## op (code, sreg, ins->inst_destbasereg, GP_SCRATCH_REG); \
1457                         } \
1458                         else \
1459                                 sparc_ ## op ## _imm (code, sreg, ins->inst_destbasereg, ins->inst_offset); \
1460                                                                                                                                                                                  } while (0);
1461
1462 #define EMIT_STORE_MEMBASE_REG(ins,op) do { \
1463                         if (!sparc_is_imm13 (ins->inst_offset)) { \
1464                                 sparc_set (code, ins->inst_offset, sparc_o7); \
1465                                 sparc_ ## op (code, ins->sreg1, ins->inst_destbasereg, sparc_o7); \
1466                         } \
1467                                   else \
1468                                 sparc_ ## op ## _imm (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset); \
1469                                                                                                                                                                                  } while (0);
1470
1471 #define EMIT_CALL() do { \
1472     if (v64) { \
1473         sparc_set_template (code, sparc_o7); \
1474         sparc_jmpl (code, sparc_o7, sparc_g0, sparc_o7); \
1475     } \
1476     else { \
1477         sparc_call_simple (code, 0); \
1478     } \
1479     sparc_nop (code); \
1480 } while (0);
1481
1482 /*
1483  * A call template is 7 instructions long, so we want to avoid it if possible.
1484  */
1485 static guint32*
1486 emit_call (MonoCompile *cfg, guint32 *code, guint32 patch_type, gconstpointer data)
1487 {
1488         gpointer target;
1489
1490         /* FIXME: This only works if the target method is already compiled */
1491         if (0 && v64 && !cfg->compile_aot) {
1492                 MonoJumpInfo patch_info;
1493
1494                 patch_info.type = patch_type;
1495                 patch_info.data.target = data;
1496
1497                 target = mono_resolve_patch_target (cfg->method, cfg->domain, NULL, &patch_info, FALSE);
1498
1499                 /* FIXME: Add optimizations if the target is close enough */
1500                 sparc_set (code, target, sparc_o7);
1501                 sparc_jmpl (code, sparc_o7, sparc_g0, sparc_o7);
1502                 sparc_nop (code);
1503         }
1504         else {
1505                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, patch_type, data);
1506                 EMIT_CALL ();
1507         }
1508
1509         return code;
1510 }
1511
1512 static void
1513 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1514 {
1515         MonoInst *ins, *last_ins = NULL;
1516         ins = bb->code;
1517
1518         while (ins) {
1519
1520                 switch (ins->opcode) {
1521                 case OP_MUL_IMM:
1522                         /* remove unnecessary multiplication with 1 */
1523                         if (ins->inst_imm == 1) {
1524                                 if (ins->dreg != ins->sreg1) {
1525                                         ins->opcode = OP_MOVE;
1526                                 } else {
1527                                         last_ins->next = ins->next;
1528                                         ins = ins->next;
1529                                         continue;
1530                                 }
1531                         }
1532                         break;
1533 #ifndef SPARCV9
1534                 case OP_LOAD_MEMBASE:
1535                 case OP_LOADI4_MEMBASE:
1536                         /*
1537                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1538                          * OP_LOAD_MEMBASE offset(basereg), reg
1539                          */
1540                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1541                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1542                             ins->inst_basereg == last_ins->inst_destbasereg &&
1543                             ins->inst_offset == last_ins->inst_offset) {
1544                                 if (ins->dreg == last_ins->sreg1) {
1545                                         last_ins->next = ins->next;
1546                                         ins = ins->next;
1547                                         continue;
1548                                 } else {
1549                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1550                                         ins->opcode = OP_MOVE;
1551                                         ins->sreg1 = last_ins->sreg1;
1552                                 }
1553
1554                         /*
1555                          * Note: reg1 must be different from the basereg in the second load
1556                          * OP_LOAD_MEMBASE offset(basereg), reg1
1557                          * OP_LOAD_MEMBASE offset(basereg), reg2
1558                          * -->
1559                          * OP_LOAD_MEMBASE offset(basereg), reg1
1560                          * OP_MOVE reg1, reg2
1561                          */
1562                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
1563                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
1564                               ins->inst_basereg != last_ins->dreg &&
1565                               ins->inst_basereg == last_ins->inst_basereg &&
1566                               ins->inst_offset == last_ins->inst_offset) {
1567
1568                                 if (ins->dreg == last_ins->dreg) {
1569                                         last_ins->next = ins->next;
1570                                         ins = ins->next;
1571                                         continue;
1572                                 } else {
1573                                         ins->opcode = OP_MOVE;
1574                                         ins->sreg1 = last_ins->dreg;
1575                                 }
1576
1577                                 //g_assert_not_reached ();
1578
1579 #if 0
1580                         /*
1581                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1582                          * OP_LOAD_MEMBASE offset(basereg), reg
1583                          * -->
1584                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1585                          * OP_ICONST reg, imm
1586                          */
1587                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
1588                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
1589                                    ins->inst_basereg == last_ins->inst_destbasereg &&
1590                                    ins->inst_offset == last_ins->inst_offset) {
1591                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1592                                 ins->opcode = OP_ICONST;
1593                                 ins->inst_c0 = last_ins->inst_imm;
1594                                 g_assert_not_reached (); // check this rule
1595 #endif
1596                         }
1597                         break;
1598 #endif
1599                 case OP_LOADU1_MEMBASE:
1600                 case OP_LOADI1_MEMBASE:
1601                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
1602                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1603                                         ins->inst_offset == last_ins->inst_offset) {
1604                                 if (ins->dreg == last_ins->sreg1) {
1605                                         last_ins->next = ins->next;
1606                                         ins = ins->next;
1607                                         continue;
1608                                 } else {
1609                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1610                                         ins->opcode = OP_MOVE;
1611                                         ins->sreg1 = last_ins->sreg1;
1612                                 }
1613                         }
1614                         break;
1615                 case OP_LOADU2_MEMBASE:
1616                 case OP_LOADI2_MEMBASE:
1617                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
1618                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1619                                         ins->inst_offset == last_ins->inst_offset) {
1620                                 if (ins->dreg == last_ins->sreg1) {
1621                                         last_ins->next = ins->next;
1622                                         ins = ins->next;
1623                                         continue;
1624                                 } else {
1625                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1626                                         ins->opcode = OP_MOVE;
1627                                         ins->sreg1 = last_ins->sreg1;
1628                                 }
1629                         }
1630                         break;
1631                 case OP_STOREI4_MEMBASE_IMM:
1632                         /* Convert pairs of 0 stores to a dword 0 store */
1633                         /* Used when initializing temporaries */
1634                         /* We know sparc_fp is dword aligned */
1635                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM) &&
1636                                 (ins->inst_destbasereg == last_ins->inst_destbasereg) &&
1637                                 (ins->inst_destbasereg == sparc_fp) &&
1638                                 (ins->inst_offset < 0) &&
1639                                 ((ins->inst_offset % 8) == 0) &&
1640                                 ((ins->inst_offset == last_ins->inst_offset - 4)) &&
1641                                 (ins->inst_imm == 0) &&
1642                                 (last_ins->inst_imm == 0)) {
1643                                 if (sparcv9) {
1644                                         last_ins->opcode = OP_STOREI8_MEMBASE_IMM;
1645                                         last_ins->inst_offset = ins->inst_offset;
1646                                         last_ins->next = ins->next;
1647                                         ins = ins->next;
1648                                         continue;
1649                                 }
1650                         }
1651                         break;
1652                 case CEE_BEQ:
1653                 case CEE_BNE_UN:
1654                 case CEE_BLT:
1655                 case CEE_BGT:
1656                 case CEE_BGE:
1657                 case CEE_BLE:
1658                 case OP_COND_EXC_EQ:
1659                 case OP_COND_EXC_GE:
1660                 case OP_COND_EXC_GT:
1661                 case OP_COND_EXC_LE:
1662                 case OP_COND_EXC_LT:
1663                 case OP_COND_EXC_NE_UN:
1664                         /*
1665                          * Convert compare with zero+branch to BRcc
1666                          */
1667                         /*
1668                          * This only works in 64 bit mode, since it examines all 64
1669                          * bits of the register.
1670                          * Only do this if the method is small since BPr only has a 16bit
1671                          * displacement.
1672                          */
1673                         if (v64 && (mono_method_get_header (cfg->method)->code_size < 10000) && last_ins &&
1674                                 (last_ins->opcode == OP_COMPARE_IMM) &&
1675                                 (last_ins->inst_imm == 0)) {
1676                                 MonoInst *next = ins->next;
1677                                 switch (ins->opcode) {
1678                                 case CEE_BEQ:
1679                                         ins->opcode = OP_SPARC_BRZ;
1680                                         break;
1681                                 case CEE_BNE_UN:
1682                                         ins->opcode = OP_SPARC_BRNZ;
1683                                         break;
1684                                 case CEE_BLT:
1685                                         ins->opcode = OP_SPARC_BRLZ;
1686                                         break;
1687                                 case CEE_BGT:
1688                                         ins->opcode = OP_SPARC_BRGZ;
1689                                         break;
1690                                 case CEE_BGE:
1691                                         ins->opcode = OP_SPARC_BRGEZ;
1692                                         break;
1693                                 case CEE_BLE:
1694                                         ins->opcode = OP_SPARC_BRLEZ;
1695                                         break;
1696                                 case OP_COND_EXC_EQ:
1697                                         ins->opcode = OP_SPARC_COND_EXC_EQZ;
1698                                         break;
1699                                 case OP_COND_EXC_GE:
1700                                         ins->opcode = OP_SPARC_COND_EXC_GEZ;
1701                                         break;
1702                                 case OP_COND_EXC_GT:
1703                                         ins->opcode = OP_SPARC_COND_EXC_GTZ;
1704                                         break;
1705                                 case OP_COND_EXC_LE:
1706                                         ins->opcode = OP_SPARC_COND_EXC_LEZ;
1707                                         break;
1708                                 case OP_COND_EXC_LT:
1709                                         ins->opcode = OP_SPARC_COND_EXC_LTZ;
1710                                         break;
1711                                 case OP_COND_EXC_NE_UN:
1712                                         ins->opcode = OP_SPARC_COND_EXC_NEZ;
1713                                         break;
1714                                 default:
1715                                         g_assert_not_reached ();
1716                                 }
1717                                 ins->sreg1 = last_ins->sreg1;
1718                                 *last_ins = *ins;
1719                                 last_ins->next = next;
1720                                 ins = next;
1721                                 continue;
1722                         }
1723                         break;
1724                 case CEE_CONV_I4:
1725                 case CEE_CONV_U4:
1726                 case OP_MOVE:
1727                         /*
1728                          * OP_MOVE reg, reg
1729                          */
1730                         if (ins->dreg == ins->sreg1) {
1731                                 if (last_ins)
1732                                         last_ins->next = ins->next;
1733                                 ins = ins->next;
1734                                 continue;
1735                         }
1736                         /*
1737                          * OP_MOVE sreg, dreg
1738                          * OP_MOVE dreg, sreg
1739                          */
1740                         if (last_ins && last_ins->opcode == OP_MOVE &&
1741                             ins->sreg1 == last_ins->dreg &&
1742                             ins->dreg == last_ins->sreg1) {
1743                                 last_ins->next = ins->next;
1744                                 ins = ins->next;
1745                                 continue;
1746                         }
1747                         break;
1748                 }
1749                 last_ins = ins;
1750                 ins = ins->next;
1751         }
1752         bb->last_ins = last_ins;
1753 }
1754
1755 static const char*const * ins_spec = sparc_desc;
1756
1757 static inline const char*
1758 get_ins_spec (int opcode)
1759 {
1760         if (ins_spec [opcode])
1761                 return ins_spec [opcode];
1762         else
1763                 return ins_spec [CEE_ADD];
1764 }
1765
1766 static int
1767 mono_spillvar_offset_float (MonoCompile *cfg, int spillvar)
1768 {
1769         MonoSpillInfo **si, *info;
1770         int i = 0;
1771
1772         si = &cfg->spill_info_float;
1773
1774         while (i <= spillvar) {
1775
1776                 if (!*si) {
1777                         *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
1778                         info->next = NULL;
1779                         cfg->stack_offset += sizeof (double);
1780                         cfg->stack_offset = ALIGN_TO (cfg->stack_offset, 8);
1781                         info->offset = - cfg->stack_offset;
1782                 }
1783
1784                 if (i == spillvar)
1785                         return MONO_SPARC_STACK_BIAS + (*si)->offset;
1786
1787                 i++;
1788                 si = &(*si)->next;
1789         }
1790
1791         g_assert_not_reached ();
1792         return 0;
1793 }
1794
1795 /* FIXME: Strange loads from the stack in basic-float.cs:test_2_rem */
1796
1797 void
1798 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1799 {
1800         mono_local_regalloc (cfg, bb);
1801 }
1802
1803 static void
1804 sparc_patch (guint32 *code, const gpointer target)
1805 {
1806         guint32 *c = code;
1807         guint32 ins = *code;
1808         guint32 op = ins >> 30;
1809         guint32 op2 = (ins >> 22) & 0x7;
1810         guint32 rd = (ins >> 25) & 0x1f;
1811         guint8* target8 = (guint8*)target;
1812         gint64 disp = (target8 - (guint8*)code) >> 2;
1813         int reg;
1814
1815 //      g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
1816
1817         if ((op == 0) && (op2 == 2)) {
1818                 if (!sparc_is_imm22 (disp))
1819                         NOT_IMPLEMENTED;
1820                 /* Bicc */
1821                 *code = ((ins >> 22) << 22) | (disp & 0x3fffff);
1822         }
1823         else if ((op == 0) && (op2 == 1)) {
1824                 if (!sparc_is_imm19 (disp))
1825                         NOT_IMPLEMENTED;
1826                 /* BPcc */
1827                 *code = ((ins >> 19) << 19) | (disp & 0x7ffff);
1828         }
1829         else if ((op == 0) && (op2 == 3)) {
1830                 if (!sparc_is_imm16 (disp))
1831                         NOT_IMPLEMENTED;
1832                 /* BPr */
1833                 *code &= ~(0x180000 | 0x3fff);
1834                 *code |= ((disp << 21) & (0x180000)) | (disp & 0x3fff);
1835         }
1836         else if ((op == 0) && (op2 == 6)) {
1837                 if (!sparc_is_imm22 (disp))
1838                         NOT_IMPLEMENTED;
1839                 /* FBicc */
1840                 *code = ((ins >> 22) << 22) | (disp & 0x3fffff);
1841         }
1842         else if ((op == 0) && (op2 == 4)) {
1843                 guint32 ins2 = code [1];
1844
1845                 if (((ins2 >> 30) == 2) && (((ins2 >> 19) & 0x3f) == 2)) {
1846                         /* sethi followed by or */
1847                         guint32 *p = code;
1848                         sparc_set (p, target8, rd);
1849                         while (p <= (code + 1))
1850                                 sparc_nop (p);
1851                 }
1852                 else if (ins2 == 0x01000000) {
1853                         /* sethi followed by nop */
1854                         guint32 *p = code;
1855                         sparc_set (p, target8, rd);
1856                         while (p <= (code + 1))
1857                                 sparc_nop (p);
1858                 }
1859                 else if ((sparc_inst_op (ins2) == 3) && (sparc_inst_imm (ins2))) {
1860                         /* sethi followed by load/store */
1861 #ifndef SPARCV9
1862                         guint32 t = (guint32)target8;
1863                         *code &= ~(0x3fffff);
1864                         *code |= (t >> 10);
1865                         *(code + 1) &= ~(0x3ff);
1866                         *(code + 1) |= (t & 0x3ff);
1867 #endif
1868                 }
1869                 else if (v64 &&
1870                                  (sparc_inst_rd (ins) == sparc_g1) &&
1871                                  (sparc_inst_op (c [1]) == 0) && (sparc_inst_op2 (c [1]) == 4) &&
1872                                  (sparc_inst_op (c [2]) == 2) && (sparc_inst_op3 (c [2]) == 2) &&
1873                                  (sparc_inst_op (c [3]) == 2) && (sparc_inst_op3 (c [3]) == 2))
1874                 {
1875                         /* sparc_set */
1876                         guint32 *p = c;
1877                         reg = sparc_inst_rd (c [1]);
1878                         sparc_set (p, target8, reg);
1879                         while (p < (c + 6))
1880                                 sparc_nop (p);
1881                 }
1882                 else if ((sparc_inst_op (ins2) == 2) && (sparc_inst_op3 (ins2) == 0x38) &&
1883                                  (sparc_inst_imm (ins2))) {
1884                         /* sethi followed by jmpl */
1885 #ifndef SPARCV9
1886                         guint32 t = (guint32)target8;
1887                         *code &= ~(0x3fffff);
1888                         *code |= (t >> 10);
1889                         *(code + 1) &= ~(0x3ff);
1890                         *(code + 1) |= (t & 0x3ff);
1891 #endif
1892                 }
1893                 else
1894                         NOT_IMPLEMENTED;
1895         }
1896         else if (op == 01) {
1897                 gint64 disp = (target8 - (guint8*)code) >> 2;
1898
1899                 if (!sparc_is_imm30 (disp))
1900                         NOT_IMPLEMENTED;
1901                 sparc_call_simple (code, target8 - (guint8*)code);
1902         }
1903         else if ((op == 2) && (sparc_inst_op3 (ins) == 0x2) && sparc_inst_imm (ins)) {
1904                 /* mov imm, reg */
1905                 g_assert (sparc_is_imm13 (target8));
1906                 *code &= ~(0x1fff);
1907                 *code |= (guint32)target8;
1908         }
1909         else if ((sparc_inst_op (ins) == 2) && (sparc_inst_op3 (ins) == 0x7)) {
1910                 /* sparc_set case 5. */
1911                 guint32 *p = c;
1912
1913                 g_assert (v64);
1914                 reg = sparc_inst_rd (c [3]);
1915                 sparc_set (p, target, reg);
1916                 while (p < (c + 6))
1917                         sparc_nop (p);
1918         }
1919         else
1920                 NOT_IMPLEMENTED;
1921
1922 //      g_print ("patched with 0x%08x\n", ins);
1923 }
1924
1925 /*
1926  * mono_sparc_emit_save_lmf:
1927  *
1928  *  Emit the code neccesary to push a new entry onto the lmf stack. Used by
1929  * trampolines as well.
1930  */
1931 guint32*
1932 mono_sparc_emit_save_lmf (guint32 *code, guint32 lmf_offset)
1933 {
1934         /* Save lmf_addr */
1935         sparc_sti_imm (code, sparc_o0, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr));
1936         /* Save previous_lmf */
1937         sparc_ldi (code, sparc_o0, sparc_g0, sparc_o7);
1938         sparc_sti_imm (code, sparc_o7, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf));
1939         /* Set new lmf */
1940         sparc_add_imm (code, FALSE, sparc_fp, lmf_offset, sparc_o7);
1941         sparc_sti (code, sparc_o7, sparc_o0, sparc_g0);
1942
1943         return code;
1944 }
1945
1946 guint32*
1947 mono_sparc_emit_restore_lmf (guint32 *code, guint32 lmf_offset)
1948 {
1949         /* Load previous_lmf */
1950         sparc_ldi_imm (code, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sparc_l0);
1951         /* Load lmf_addr */
1952         sparc_ldi_imm (code, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), sparc_l1);
1953         /* *(lmf) = previous_lmf */
1954         sparc_sti (code, sparc_l0, sparc_l1, sparc_g0);
1955         return code;
1956 }
1957
1958 static guint32*
1959 emit_save_sp_to_lmf (MonoCompile *cfg, guint32 *code)
1960 {
1961         /*
1962          * Since register windows are saved to the current value of %sp, we need to
1963          * set the sp field in the lmf before the call, not in the prolog.
1964          */
1965         if (cfg->method->save_lmf) {
1966                 gint32 lmf_offset = MONO_SPARC_STACK_BIAS - cfg->arch.lmf_offset;
1967
1968                 /* Save sp */
1969                 sparc_sti_imm (code, sparc_sp, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, sp));
1970         }
1971
1972         return code;
1973 }
1974
1975 static guint32*
1976 emit_vret_token (MonoInst *ins, guint32 *code)
1977 {
1978         MonoCallInst *call = (MonoCallInst*)ins;
1979         guint32 size;
1980
1981         /*
1982          * The sparc ABI requires that calls to functions which return a structure
1983          * contain an additional unimpl instruction which is checked by the callee.
1984          */
1985         if (call->signature->pinvoke && MONO_TYPE_ISSTRUCT(call->signature->ret)) {
1986                 if (call->signature->ret->type == MONO_TYPE_TYPEDBYREF)
1987                         size = mono_type_stack_size (call->signature->ret, NULL);
1988                 else
1989                         size = mono_class_native_size (call->signature->ret->data.klass, NULL);
1990                 sparc_unimp (code, size & 0xfff);
1991         }
1992
1993         return code;
1994 }
1995
1996 static guint32*
1997 emit_move_return_value (MonoInst *ins, guint32 *code)
1998 {
1999         /* Move return value to the target register */
2000         /* FIXME: do more things in the local reg allocator */
2001         switch (ins->opcode) {
2002         case OP_VOIDCALL:
2003         case OP_VOIDCALL_REG:
2004         case OP_VOIDCALL_MEMBASE:
2005                 break;
2006         case CEE_CALL:
2007         case OP_CALL_REG:
2008         case OP_CALL_MEMBASE:
2009                 g_assert (ins->dreg == sparc_o0);
2010                 break;
2011         case OP_LCALL:
2012         case OP_LCALL_REG:
2013         case OP_LCALL_MEMBASE:
2014                 /*
2015                  * ins->dreg is the least significant reg due to the lreg: LCALL rule
2016                  * in inssel-long32.brg.
2017                  */
2018 #ifdef SPARCV9
2019                 sparc_mov_reg_reg (code, sparc_o0, ins->dreg);
2020 #else
2021                 g_assert (ins->dreg == sparc_o1);
2022 #endif
2023                 break;
2024         case OP_FCALL:
2025         case OP_FCALL_REG:
2026         case OP_FCALL_MEMBASE:
2027 #ifdef SPARCV9
2028                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2029                         sparc_fmovs (code, sparc_f0, ins->dreg);
2030                         sparc_fstod (code, ins->dreg, ins->dreg);
2031                 }
2032                 else
2033                         sparc_fmovd (code, sparc_f0, ins->dreg);
2034 #else
2035                 sparc_fmovs (code, sparc_f0, ins->dreg);
2036                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4)
2037                         sparc_fstod (code, ins->dreg, ins->dreg);
2038                 else
2039                         sparc_fmovs (code, sparc_f1, ins->dreg + 1);
2040 #endif
2041                 break;
2042         case OP_VCALL:
2043         case OP_VCALL_REG:
2044         case OP_VCALL_MEMBASE:
2045                 break;
2046         default:
2047                 NOT_IMPLEMENTED;
2048         }
2049
2050         return code;
2051 }
2052
2053 /*
2054  * emit_load_volatile_arguments:
2055  *
2056  *  Load volatile arguments from the stack to the original input registers.
2057  * Required before a tail call.
2058  */
2059 static guint32*
2060 emit_load_volatile_arguments (MonoCompile *cfg, guint32 *code)
2061 {
2062         MonoMethod *method = cfg->method;
2063         MonoMethodSignature *sig;
2064         MonoInst *inst;
2065         CallInfo *cinfo;
2066         guint32 i, ireg;
2067
2068         /* FIXME: Generate intermediate code instead */
2069
2070         sig = mono_method_signature (method);
2071
2072         cinfo = get_call_info (sig, FALSE);
2073
2074         /* This is the opposite of the code in emit_prolog */
2075
2076         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2077                 ArgInfo *ainfo = cinfo->args + i;
2078                 gint32 stack_offset;
2079                 MonoType *arg_type;
2080                 inst = cfg->varinfo [i];
2081
2082                 if (sig->hasthis && (i == 0))
2083                         arg_type = &mono_defaults.object_class->byval_arg;
2084                 else
2085                         arg_type = sig->params [i - sig->hasthis];
2086
2087                 stack_offset = ainfo->offset + ARGS_OFFSET;
2088                 ireg = sparc_i0 + ainfo->reg;
2089
2090                 if (ainfo->storage == ArgInSplitRegStack) {
2091                         g_assert (inst->opcode == OP_REGOFFSET);
2092
2093                         if (!sparc_is_imm13 (stack_offset))
2094                                 NOT_IMPLEMENTED;
2095                         sparc_st_imm (code, inst->inst_basereg, stack_offset, sparc_i5);
2096                 }
2097
2098                 if (!v64 && !arg_type->byref && (arg_type->type == MONO_TYPE_R8)) {
2099                         if (ainfo->storage == ArgInIRegPair) {
2100                                 if (!sparc_is_imm13 (inst->inst_offset + 4))
2101                                         NOT_IMPLEMENTED;
2102                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset, ireg);
2103                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset + 4, ireg + 1);
2104                         }
2105                         else
2106                                 if (ainfo->storage == ArgInSplitRegStack) {
2107                                         if (stack_offset != inst->inst_offset) {
2108                                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset, sparc_i5);
2109                                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset + 4, sparc_o7);
2110                                                 sparc_st_imm (code, sparc_o7, sparc_fp, stack_offset + 4);
2111
2112                                         }
2113                                 }
2114                         else
2115                                 if (ainfo->storage == ArgOnStackPair) {
2116                                         if (stack_offset != inst->inst_offset) {
2117                                                 /* stack_offset is not dword aligned, so we need to make a copy */
2118                                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset, sparc_o7);
2119                                                 sparc_st_imm (code, sparc_o7, sparc_fp, stack_offset);
2120
2121                                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset + 4, sparc_o7);
2122                                                 sparc_st_imm (code, sparc_o7, sparc_fp, stack_offset + 4);
2123
2124                                         }
2125                                 }
2126                          else
2127                                 g_assert_not_reached ();
2128                 }
2129                 else
2130                         if ((ainfo->storage == ArgInIReg) && (inst->opcode != OP_REGVAR)) {
2131                                 /* Argument in register, but need to be saved to stack */
2132                                 if (!sparc_is_imm13 (stack_offset))
2133                                         NOT_IMPLEMENTED;
2134                                 if ((stack_offset - ARGS_OFFSET) & 0x1)
2135                                         /* FIXME: Is this ldsb or ldub ? */
2136                                         sparc_ldsb_imm (code, inst->inst_basereg, stack_offset, ireg);
2137                                 else
2138                                         if ((stack_offset - ARGS_OFFSET) & 0x2)
2139                                                 sparc_ldsh_imm (code, inst->inst_basereg, stack_offset, ireg);
2140                                 else
2141                                         if ((stack_offset - ARGS_OFFSET) & 0x4)
2142                                                 sparc_ld_imm (code, inst->inst_basereg, stack_offset, ireg);
2143                                         else {
2144                                                 if (v64)
2145                                                         sparc_ldx_imm (code, inst->inst_basereg, stack_offset, ireg);
2146                                                 else
2147                                                         sparc_ld_imm (code, inst->inst_basereg, stack_offset, ireg);
2148                                         }
2149                         }
2150                         else if ((ainfo->storage == ArgInIRegPair) && (inst->opcode != OP_REGVAR)) {
2151                                 /* Argument in regpair, but need to be saved to stack */
2152                                 if (!sparc_is_imm13 (inst->inst_offset + 4))
2153                                         NOT_IMPLEMENTED;
2154                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset, ireg);
2155                                 sparc_st_imm (code, inst->inst_basereg, inst->inst_offset + 4, ireg + 1);
2156                         }
2157                         else if ((ainfo->storage == ArgInFloatReg) && (inst->opcode != OP_REGVAR)) {
2158                                 NOT_IMPLEMENTED;
2159                         }
2160                         else if ((ainfo->storage == ArgInDoubleReg) && (inst->opcode != OP_REGVAR)) {
2161                                 NOT_IMPLEMENTED;
2162                         }
2163
2164                 if ((ainfo->storage == ArgInSplitRegStack) || (ainfo->storage == ArgOnStack))
2165                         if (inst->opcode == OP_REGVAR)
2166                                 /* FIXME: Load the argument into memory */
2167                                 NOT_IMPLEMENTED;
2168         }
2169
2170         g_free (cinfo);
2171
2172         return code;
2173 }
2174
2175 /*
2176  * mono_sparc_is_virtual_call:
2177  *
2178  *  Determine whenever the instruction at CODE is a virtual call.
2179  */
2180 gboolean
2181 mono_sparc_is_virtual_call (guint32 *code)
2182 {
2183         guint32 buf[1];
2184         guint32 *p;
2185
2186         p = buf;
2187
2188         if ((sparc_inst_op (*code) == 0x2) && (sparc_inst_op3 (*code) == 0x38)) {
2189                 /*
2190                  * Register indirect call. If it is a virtual call, then the
2191                  * instruction in the delay slot is a special kind of nop.
2192                  */
2193
2194                 /* Construct special nop */
2195                 sparc_or_imm (p, FALSE, sparc_g0, 0xca, sparc_g0);
2196                 p --;
2197
2198                 if (code [1] == p [0])
2199                         return TRUE;
2200         }
2201
2202         return FALSE;
2203 }
2204
2205 /*
2206  * mono_arch_get_vcall_slot_addr:
2207  *
2208  *  Determine the vtable slot used by a virtual call.
2209  */
2210 gpointer*
2211 mono_arch_get_vcall_slot_addr (guint8 *code8, gpointer *regs)
2212 {
2213         guint32 *code = (guint32*)(gpointer)code8;
2214         guint32 ins = code [0];
2215         guint32 prev_ins = code [-1];
2216
2217         mono_sparc_flushw ();
2218
2219         if (!mono_sparc_is_virtual_call (code))
2220                 return NULL;
2221
2222         if ((sparc_inst_op (ins) == 0x2) && (sparc_inst_op3 (ins) == 0x38)) {
2223                 if ((sparc_inst_op (prev_ins) == 0x3) && (sparc_inst_i (prev_ins) == 1) && (sparc_inst_op3 (prev_ins) == 0 || sparc_inst_op3 (prev_ins) == 0xb)) {
2224                         /* ld [r1 + CONST ], r2; call r2 */
2225                         guint32 base = sparc_inst_rs1 (prev_ins);
2226                         guint32 disp = sparc_inst_imm13 (prev_ins);
2227                         gpointer base_val;
2228
2229                         g_assert (sparc_inst_rd (prev_ins) == sparc_inst_rs1 (ins));
2230
2231                         g_assert ((base >= sparc_o0) && (base <= sparc_i7));
2232
2233                         base_val = regs [base - sparc_o0];
2234
2235                         return (gpointer)((guint8*)base_val + disp);
2236                 }
2237                 else if ((sparc_inst_op (prev_ins) == 0x3) && (sparc_inst_i (prev_ins) == 0) && (sparc_inst_op3 (prev_ins) == 0)) {
2238                         /* set r1, ICONST; ld [r1 + r2], r2; call r2 */
2239                         /* Decode a sparc_set32 */
2240                         guint32 base = sparc_inst_rs1 (prev_ins);
2241                         guint32 disp;
2242                         gpointer base_val;
2243                         guint32 s1 = code [-3];
2244                         guint32 s2 = code [-2];
2245
2246 #ifdef SPARCV9
2247                         NOT_IMPLEMENTED;
2248 #endif
2249
2250                         /* sparc_sethi */
2251                         g_assert (sparc_inst_op (s1) == 0);
2252                         g_assert (sparc_inst_op2 (s1) == 4);
2253
2254                         /* sparc_or_imm */
2255                         g_assert (sparc_inst_op (s2) == 2);
2256                         g_assert (sparc_inst_op3 (s2) == 2);
2257                         g_assert (sparc_inst_i (s2) == 1);
2258                         g_assert (sparc_inst_rs1 (s2) == sparc_inst_rd (s2));
2259                         g_assert (sparc_inst_rd (s1) == sparc_inst_rs1 (s2));
2260
2261                         disp = ((s1 & 0x3fffff) << 10) | sparc_inst_imm13 (s2);
2262
2263                         g_assert ((base >= sparc_o0) && (base <= sparc_i7));
2264
2265                         base_val = regs [base - sparc_o0];
2266
2267                         return (gpointer)((guint8*)base_val + disp);
2268                 } else
2269                         g_assert_not_reached ();
2270         }
2271         else
2272                 g_assert_not_reached ();
2273
2274         return NULL;
2275 }
2276
2277 /*
2278  * Some conventions used in the following code.
2279  * 2) The only scratch registers we have are o7 and g1.  We try to
2280  * stick to o7 when we can, and use g1 when necessary.
2281  */
2282
2283 void
2284 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2285 {
2286         MonoInst *ins;
2287         MonoCallInst *call;
2288         guint offset;
2289         guint32 *code = (guint32*)(cfg->native_code + cfg->code_len);
2290         MonoInst *last_ins = NULL;
2291         int max_len, cpos;
2292         const char *spec;
2293
2294         if (cfg->opt & MONO_OPT_PEEPHOLE)
2295                 peephole_pass (cfg, bb);
2296
2297         if (cfg->verbose_level > 2)
2298                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2299
2300         cpos = bb->max_offset;
2301
2302         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2303                 NOT_IMPLEMENTED;
2304         }
2305
2306         ins = bb->code;
2307         while (ins) {
2308                 guint8* code_start;
2309
2310                 offset = (guint8*)code - cfg->native_code;
2311
2312                 spec = ins_spec [ins->opcode];
2313                 if (!spec)
2314                         spec = ins_spec [CEE_ADD];
2315
2316                 max_len = ((guint8 *)spec)[MONO_INST_LEN];
2317
2318                 if (offset > (cfg->code_size - max_len - 16)) {
2319                         cfg->code_size *= 2;
2320                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2321                         code = (guint32*)(cfg->native_code + offset);
2322                 }
2323                 code_start = (guint8*)code;
2324                 //      if (ins->cil_code)
2325                 //              g_print ("cil code\n");
2326                 mono_debug_record_line_number (cfg, ins, offset);
2327
2328                 switch (ins->opcode) {
2329                 case OP_STOREI1_MEMBASE_IMM:
2330                         EMIT_STORE_MEMBASE_IMM (ins, stb);
2331                         break;
2332                 case OP_STOREI2_MEMBASE_IMM:
2333                         EMIT_STORE_MEMBASE_IMM (ins, sth);
2334                         break;
2335                 case OP_STORE_MEMBASE_IMM:
2336                         EMIT_STORE_MEMBASE_IMM (ins, sti);
2337                         break;
2338                 case OP_STOREI4_MEMBASE_IMM:
2339                         EMIT_STORE_MEMBASE_IMM (ins, st);
2340                         break;
2341                 case OP_STOREI8_MEMBASE_IMM:
2342 #ifdef SPARCV9
2343                         EMIT_STORE_MEMBASE_IMM (ins, stx);
2344 #else
2345                         /* Only generated by peephole opts */
2346                         g_assert ((ins->inst_offset % 8) == 0);
2347                         g_assert (ins->inst_imm == 0);
2348                         EMIT_STORE_MEMBASE_IMM (ins, stx);
2349 #endif
2350                         break;
2351                 case OP_STOREI1_MEMBASE_REG:
2352                         EMIT_STORE_MEMBASE_REG (ins, stb);
2353                         break;
2354                 case OP_STOREI2_MEMBASE_REG:
2355                         EMIT_STORE_MEMBASE_REG (ins, sth);
2356                         break;
2357                 case OP_STOREI4_MEMBASE_REG:
2358                         EMIT_STORE_MEMBASE_REG (ins, st);
2359                         break;
2360                 case OP_STOREI8_MEMBASE_REG:
2361 #ifdef SPARCV9
2362                         EMIT_STORE_MEMBASE_REG (ins, stx);
2363 #else
2364                         /* Only used by OP_MEMSET */
2365                         EMIT_STORE_MEMBASE_REG (ins, std);
2366 #endif
2367                         break;
2368                 case OP_STORE_MEMBASE_REG:
2369                         EMIT_STORE_MEMBASE_REG (ins, sti);
2370                         break;
2371                 case CEE_LDIND_I:
2372 #ifdef SPARCV9
2373                         sparc_ldx (code, ins->inst_c0, sparc_g0, ins->dreg);
2374 #else
2375                         sparc_ld (code, ins->inst_c0, sparc_g0, ins->dreg);
2376 #endif
2377                         break;
2378                 case CEE_LDIND_I4:
2379 #ifdef SPARCV9
2380                         sparc_ldsw (code, ins->inst_c0, sparc_g0, ins->dreg);
2381 #else
2382                         sparc_ld (code, ins->inst_c0, sparc_g0, ins->dreg);
2383 #endif
2384                         break;
2385                 case CEE_LDIND_U4:
2386                         sparc_ld (code, ins->inst_c0, sparc_g0, ins->dreg);
2387                         break;
2388                 case OP_LOADU4_MEM:
2389                         sparc_set (code, ins->inst_c0, ins->dreg);
2390                         sparc_ld (code, ins->dreg, sparc_g0, ins->dreg);
2391                         break;
2392                 case OP_LOADI4_MEMBASE:
2393 #ifdef SPARCV9
2394                         EMIT_LOAD_MEMBASE (ins, ldsw);
2395 #else
2396                         EMIT_LOAD_MEMBASE (ins, ld);
2397 #endif
2398                         break;
2399                 case OP_LOADU4_MEMBASE:
2400                         EMIT_LOAD_MEMBASE (ins, ld);
2401                         break;
2402                 case OP_LOADU1_MEMBASE:
2403                         EMIT_LOAD_MEMBASE (ins, ldub);
2404                         break;
2405                 case OP_LOADI1_MEMBASE:
2406                         EMIT_LOAD_MEMBASE (ins, ldsb);
2407                         break;
2408                 case OP_LOADU2_MEMBASE:
2409                         EMIT_LOAD_MEMBASE (ins, lduh);
2410                         break;
2411                 case OP_LOADI2_MEMBASE:
2412                         EMIT_LOAD_MEMBASE (ins, ldsh);
2413                         break;
2414                 case OP_LOAD_MEMBASE:
2415 #ifdef SPARCV9
2416                                 EMIT_LOAD_MEMBASE (ins, ldx);
2417 #else
2418                                 EMIT_LOAD_MEMBASE (ins, ld);
2419 #endif
2420                         break;
2421 #ifdef SPARCV9
2422                 case OP_LOADI8_MEMBASE:
2423                         EMIT_LOAD_MEMBASE (ins, ldx);
2424                         break;
2425 #endif
2426                 case CEE_CONV_I1:
2427                         sparc_sll_imm (code, ins->sreg1, 24, sparc_o7);
2428                         sparc_sra_imm (code, sparc_o7, 24, ins->dreg);
2429                         break;
2430                 case CEE_CONV_I2:
2431                         sparc_sll_imm (code, ins->sreg1, 16, sparc_o7);
2432                         sparc_sra_imm (code, sparc_o7, 16, ins->dreg);
2433                         break;
2434                 case CEE_CONV_U1:
2435                         sparc_and_imm (code, FALSE, ins->sreg1, 0xff, ins->dreg);
2436                         break;
2437                 case CEE_CONV_U2:
2438                         sparc_sll_imm (code, ins->sreg1, 16, sparc_o7);
2439                         sparc_srl_imm (code, sparc_o7, 16, ins->dreg);
2440                         break;
2441                 case CEE_CONV_OVF_U4:
2442                         /* Only used on V9 */
2443                         sparc_cmp_imm (code, ins->sreg1, 0);
2444                         mono_add_patch_info (cfg, (guint8*)(code) - (cfg)->native_code,
2445                                                                  MONO_PATCH_INFO_EXC, "OverflowException");
2446                         sparc_branchp (code, 0, sparc_bl, sparc_xcc_short, 0, 0);
2447                         /* Delay slot */
2448                         sparc_set (code, 1, sparc_o7);
2449                         sparc_sllx_imm (code, sparc_o7, 32, sparc_o7);
2450                         sparc_cmp (code, ins->sreg1, sparc_o7);
2451                         mono_add_patch_info (cfg, (guint8*)(code) - (cfg)->native_code,
2452                                                                  MONO_PATCH_INFO_EXC, "OverflowException");
2453                         sparc_branchp (code, 0, sparc_bge, sparc_xcc_short, 0, 0);
2454                         sparc_nop (code);
2455                         sparc_mov_reg_reg (code, ins->sreg1, ins->dreg);
2456                         break;
2457                 case CEE_CONV_OVF_I4_UN:
2458                         /* Only used on V9 */
2459                         NOT_IMPLEMENTED;
2460                         break;
2461                 case CEE_CONV_U:
2462                 case CEE_CONV_U8:
2463                         /* Only used on V9 */
2464                         sparc_srl_imm (code, ins->sreg1, 0, ins->dreg);
2465                         break;
2466                 case CEE_CONV_I:
2467                 case CEE_CONV_I8:
2468                         /* Only used on V9 */
2469                         sparc_sra_imm (code, ins->sreg1, 0, ins->dreg);
2470                         break;
2471                 case OP_COMPARE:
2472                 case OP_LCOMPARE:
2473                 case OP_ICOMPARE:
2474                         sparc_cmp (code, ins->sreg1, ins->sreg2);
2475                         break;
2476                 case OP_COMPARE_IMM:
2477                 case OP_ICOMPARE_IMM:
2478                         if (sparc_is_imm13 (ins->inst_imm))
2479                                 sparc_cmp_imm (code, ins->sreg1, ins->inst_imm);
2480                         else {
2481                                 sparc_set (code, ins->inst_imm, sparc_o7);
2482                                 sparc_cmp (code, ins->sreg1, sparc_o7);
2483                         }
2484                         break;
2485                 case CEE_BREAK:
2486                         /*
2487                          * gdb does not like encountering 'ta 1' in the debugged code. So
2488                          * instead of emitting a trap, we emit a call a C function and place a
2489                          * breakpoint there.
2490                          */
2491                         //sparc_ta (code, 1);
2492                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, mono_arch_break);
2493                         EMIT_CALL();
2494                         break;
2495                 case OP_ADDCC:
2496                 case OP_IADDCC:
2497                         sparc_add (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
2498                         break;
2499                 case CEE_ADD:
2500                 case OP_IADD:
2501                         sparc_add (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
2502                         break;
2503                 case OP_ADDCC_IMM:
2504                 case OP_ADD_IMM:
2505                 case OP_IADD_IMM:
2506                         /* according to inssel-long32.brg, this should set cc */
2507                         EMIT_ALU_IMM (ins, add, TRUE);
2508                         break;
2509                 case OP_ADC:
2510                 case OP_IADC:
2511                         /* according to inssel-long32.brg, this should set cc */
2512                         sparc_addx (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
2513                         break;
2514                 case OP_ADC_IMM:
2515                 case OP_IADC_IMM:
2516                         EMIT_ALU_IMM (ins, addx, TRUE);
2517                         break;
2518                 case OP_SUBCC:
2519                 case OP_ISUBCC:
2520                         sparc_sub (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
2521                         break;
2522                 case CEE_SUB:
2523                 case OP_ISUB:
2524                         sparc_sub (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
2525                         break;
2526                 case OP_SUBCC_IMM:
2527                 case OP_SUB_IMM:
2528                 case OP_ISUB_IMM:
2529                         /* according to inssel-long32.brg, this should set cc */
2530                         EMIT_ALU_IMM (ins, sub, TRUE);
2531                         break;
2532                 case OP_SBB:
2533                 case OP_ISBB:
2534                         /* according to inssel-long32.brg, this should set cc */
2535                         sparc_subx (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
2536                         break;
2537                 case OP_SBB_IMM:
2538                 case OP_ISBB_IMM:
2539                         EMIT_ALU_IMM (ins, subx, TRUE);
2540                         break;
2541                 case CEE_AND:
2542                 case OP_IAND:
2543                         sparc_and (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
2544                         break;
2545                 case OP_AND_IMM:
2546                 case OP_IAND_IMM:
2547                         EMIT_ALU_IMM (ins, and, FALSE);
2548                         break;
2549                 case CEE_DIV:
2550                 case OP_IDIV:
2551                         /* Sign extend sreg1 into %y */
2552                         sparc_sra_imm (code, ins->sreg1, 31, sparc_o7);
2553                         sparc_wry (code, sparc_o7, sparc_g0);
2554                         sparc_sdiv (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
2555                         EMIT_COND_SYSTEM_EXCEPTION_GENERAL (code, sparc_boverflow, "ArithmeticException", TRUE, sparc_icc_short);
2556                         break;
2557                 case CEE_DIV_UN:
2558                 case OP_IDIV_UN:
2559                         sparc_wry (code, sparc_g0, sparc_g0);
2560                         sparc_udiv (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
2561                         break;
2562                 case OP_DIV_IMM: {
2563                         int i, imm;
2564
2565                         /* Transform division into a shift */
2566                         for (i = 1; i < 30; ++i) {
2567                                 imm = (1 << i);
2568                                 if (ins->inst_imm == imm)
2569                                         break;
2570                         }
2571                         if (i < 30) {
2572                                 if (i == 1) {
2573                                         /* gcc 2.95.3 */
2574                                         sparc_srl_imm (code, ins->sreg1, 31, sparc_o7);
2575                                         sparc_add (code, FALSE, ins->sreg1, sparc_o7, ins->dreg);
2576                                         sparc_sra_imm (code, ins->dreg, 1, ins->dreg);
2577                                 }
2578                                 else {
2579                                         /* http://compilers.iecc.com/comparch/article/93-04-079 */
2580                                         sparc_sra_imm (code, ins->sreg1, 31, sparc_o7);
2581                                         sparc_srl_imm (code, sparc_o7, 32 - i, sparc_o7);
2582                                         sparc_add (code, FALSE, ins->sreg1, sparc_o7, ins->dreg);
2583                                         sparc_sra_imm (code, ins->dreg, i, ins->dreg);
2584                                 }
2585                         }
2586                         else {
2587                                 /* Sign extend sreg1 into %y */
2588                                 sparc_sra_imm (code, ins->sreg1, 31, sparc_o7);
2589                                 sparc_wry (code, sparc_o7, sparc_g0);
2590                                 EMIT_ALU_IMM (ins, sdiv, TRUE);
2591                                 EMIT_COND_SYSTEM_EXCEPTION_GENERAL (code, sparc_boverflow, "ArithmeticException", TRUE, sparc_icc_short);
2592                         }
2593                         break;
2594                 }
2595                 case CEE_REM:
2596                 case OP_IREM:
2597                         /* Sign extend sreg1 into %y */
2598                         sparc_sra_imm (code, ins->sreg1, 31, sparc_o7);
2599                         sparc_wry (code, sparc_o7, sparc_g0);
2600                         sparc_sdiv (code, TRUE, ins->sreg1, ins->sreg2, sparc_o7);
2601                         EMIT_COND_SYSTEM_EXCEPTION_GENERAL (code, sparc_boverflow, "ArithmeticException", TRUE, sparc_icc_short);
2602                         sparc_smul (code, FALSE, ins->sreg2, sparc_o7, sparc_o7);
2603                         sparc_sub (code, FALSE, ins->sreg1, sparc_o7, ins->dreg);
2604                         break;
2605                 case CEE_REM_UN:
2606                 case OP_IREM_UN:
2607                         sparc_wry (code, sparc_g0, sparc_g0);
2608                         sparc_udiv (code, FALSE, ins->sreg1, ins->sreg2, sparc_o7);
2609                         sparc_umul (code, FALSE, ins->sreg2, sparc_o7, sparc_o7);
2610                         sparc_sub (code, FALSE, ins->sreg1, sparc_o7, ins->dreg);
2611                         break;
2612                 case OP_REM_IMM:
2613                 case OP_IREM_IMM:
2614                         /* Sign extend sreg1 into %y */
2615                         sparc_sra_imm (code, ins->sreg1, 31, sparc_o7);
2616                         sparc_wry (code, sparc_o7, sparc_g0);
2617                         if (!sparc_is_imm13 (ins->inst_imm)) {
2618                                 sparc_set (code, ins->inst_imm, GP_SCRATCH_REG);
2619                                 sparc_sdiv (code, TRUE, ins->sreg1, GP_SCRATCH_REG, sparc_o7);
2620                                 EMIT_COND_SYSTEM_EXCEPTION_GENERAL (code, sparc_boverflow, "ArithmeticException", TRUE, sparc_icc_short);
2621                                 sparc_smul (code, FALSE, sparc_o7, GP_SCRATCH_REG, sparc_o7);
2622                         }
2623                         else {
2624                                 sparc_sdiv_imm (code, TRUE, ins->sreg1, ins->inst_imm, sparc_o7);
2625                                 EMIT_COND_SYSTEM_EXCEPTION_GENERAL (code, sparc_boverflow, "ArithmeticException", TRUE, sparc_icc_short);
2626                                 sparc_smul_imm (code, FALSE, sparc_o7, ins->inst_imm, sparc_o7);
2627                         }
2628                         sparc_sub (code, FALSE, ins->sreg1, sparc_o7, ins->dreg);
2629                         break;
2630                 case CEE_OR:
2631                 case OP_IOR:
2632                         sparc_or (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
2633                         break;
2634                 case OP_OR_IMM:
2635                 case OP_IOR_IMM:
2636                         EMIT_ALU_IMM (ins, or, FALSE);
2637                         break;
2638                 case CEE_XOR:
2639                 case OP_IXOR:
2640                         sparc_xor (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
2641                         break;
2642                 case OP_XOR_IMM:
2643                 case OP_IXOR_IMM:
2644                         EMIT_ALU_IMM (ins, xor, FALSE);
2645                         break;
2646                 case CEE_SHL:
2647                 case OP_ISHL:
2648                         sparc_sll (code, ins->sreg1, ins->sreg2, ins->dreg);
2649                         break;
2650                 case OP_SHL_IMM:
2651                 case OP_ISHL_IMM:
2652                         if (ins->inst_imm < (1 << 5))
2653                                 sparc_sll_imm (code, ins->sreg1, ins->inst_imm, ins->dreg);
2654                         else {
2655                                 sparc_set (code, ins->inst_imm, sparc_o7);
2656                                 sparc_sll (code, ins->sreg1, sparc_o7, ins->dreg);
2657                         }
2658                         break;
2659                 case CEE_SHR:
2660                 case OP_ISHR:
2661                         sparc_sra (code, ins->sreg1, ins->sreg2, ins->dreg);
2662                         break;
2663                 case OP_ISHR_IMM:
2664                 case OP_SHR_IMM:
2665                         if (ins->inst_imm < (1 << 5))
2666                                 sparc_sra_imm (code, ins->sreg1, ins->inst_imm, ins->dreg);
2667                         else {
2668                                 sparc_set (code, ins->inst_imm, sparc_o7);
2669                                 sparc_sra (code, ins->sreg1, sparc_o7, ins->dreg);
2670                         }
2671                         break;
2672                 case OP_SHR_UN_IMM:
2673                 case OP_ISHR_UN_IMM:
2674                         if (ins->inst_imm < (1 << 5))
2675                                 sparc_srl_imm (code, ins->sreg1, ins->inst_imm, ins->dreg);
2676                         else {
2677                                 sparc_set (code, ins->inst_imm, sparc_o7);
2678                                 sparc_srl (code, ins->sreg1, sparc_o7, ins->dreg);
2679                         }
2680                         break;
2681                 case CEE_SHR_UN:
2682                 case OP_ISHR_UN:
2683                         sparc_srl (code, ins->sreg1, ins->sreg2, ins->dreg);
2684                         break;
2685                 case OP_LSHL:
2686                         sparc_sllx (code, ins->sreg1, ins->sreg2, ins->dreg);
2687                         break;
2688                 case OP_LSHL_IMM:
2689                         if (ins->inst_imm < (1 << 6))
2690                                 sparc_sllx_imm (code, ins->sreg1, ins->inst_imm, ins->dreg);
2691                         else {
2692                                 sparc_set (code, ins->inst_imm, sparc_o7);
2693                                 sparc_sllx (code, ins->sreg1, sparc_o7, ins->dreg);
2694                         }
2695                         break;
2696                 case OP_LSHR:
2697                         sparc_srax (code, ins->sreg1, ins->sreg2, ins->dreg);
2698                         break;
2699                 case OP_LSHR_IMM:
2700                         if (ins->inst_imm < (1 << 6))
2701                                 sparc_srax_imm (code, ins->sreg1, ins->inst_imm, ins->dreg);
2702                         else {
2703                                 sparc_set (code, ins->inst_imm, sparc_o7);
2704                                 sparc_srax (code, ins->sreg1, sparc_o7, ins->dreg);
2705                         }
2706                         break;
2707                 case OP_LSHR_UN:
2708                         sparc_srlx (code, ins->sreg1, ins->sreg2, ins->dreg);
2709                         break;
2710                 case OP_LSHR_UN_IMM:
2711                         if (ins->inst_imm < (1 << 6))
2712                                 sparc_srlx_imm (code, ins->sreg1, ins->inst_imm, ins->dreg);
2713                         else {
2714                                 sparc_set (code, ins->inst_imm, sparc_o7);
2715                                 sparc_srlx (code, ins->sreg1, sparc_o7, ins->dreg);
2716                         }
2717                         break;
2718                 case CEE_NOT:
2719                 case OP_INOT:
2720                         /* can't use sparc_not */
2721                         sparc_xnor (code, FALSE, ins->sreg1, sparc_g0, ins->dreg);
2722                         break;
2723                 case CEE_NEG:
2724                 case OP_INEG:
2725                         /* can't use sparc_neg */
2726                         sparc_sub (code, FALSE, sparc_g0, ins->sreg1, ins->dreg);
2727                         break;
2728                 case CEE_MUL:
2729                 case OP_IMUL:
2730                         sparc_smul (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
2731                         break;
2732                 case OP_IMUL_IMM:
2733                 case OP_MUL_IMM: {
2734                         int i, imm;
2735
2736                         if ((ins->inst_imm == 1) && (ins->sreg1 == ins->dreg))
2737                                 break;
2738
2739                         /* Transform multiplication into a shift */
2740                         for (i = 0; i < 30; ++i) {
2741                                 imm = (1 << i);
2742                                 if (ins->inst_imm == imm)
2743                                         break;
2744                         }
2745                         if (i < 30)
2746                                 sparc_sll_imm (code, ins->sreg1, i, ins->dreg);
2747                         else
2748                                 EMIT_ALU_IMM (ins, smul, FALSE);
2749                         break;
2750                 }
2751                 case CEE_MUL_OVF:
2752                 case OP_IMUL_OVF:
2753                         sparc_smul (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
2754                         sparc_rdy (code, sparc_g1);
2755                         sparc_sra_imm (code, ins->dreg, 31, sparc_o7);
2756                         sparc_cmp (code, sparc_g1, sparc_o7);
2757                         EMIT_COND_SYSTEM_EXCEPTION_GENERAL (ins, sparc_bne, "OverflowException", TRUE, sparc_icc_short);
2758                         break;
2759                 case CEE_MUL_OVF_UN:
2760                 case OP_IMUL_OVF_UN:
2761                         sparc_umul (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
2762                         sparc_rdy (code, sparc_o7);
2763                         sparc_cmp (code, sparc_o7, sparc_g0);
2764                         EMIT_COND_SYSTEM_EXCEPTION_GENERAL (ins, sparc_bne, "OverflowException", TRUE, sparc_icc_short);
2765                         break;
2766                 case OP_ICONST:
2767                 case OP_SETREGIMM:
2768                         sparc_set (code, ins->inst_c0, ins->dreg);
2769                         break;
2770                 case OP_I8CONST:
2771                         sparc_set (code, ins->inst_l, ins->dreg);
2772                         break;
2773                 case OP_AOTCONST:
2774                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2775                         sparc_set_template (code, ins->dreg);
2776                         break;
2777                 case CEE_CONV_I4:
2778                 case CEE_CONV_U4:
2779                 case OP_MOVE:
2780                 case OP_SETREG:
2781                         if (ins->sreg1 != ins->dreg)
2782                                 sparc_mov_reg_reg (code, ins->sreg1, ins->dreg);
2783                         break;
2784                 case OP_SETFREG:
2785                         /* Only used on V9 */
2786                         if (ins->sreg1 != ins->dreg)
2787                                 sparc_fmovd (code, ins->sreg1, ins->dreg);
2788                         break;
2789                 case OP_SPARC_SETFREG_FLOAT:
2790                         /* Only used on V9 */
2791                         sparc_fdtos (code, ins->sreg1, ins->dreg);
2792                         break;
2793                 case CEE_JMP:
2794                         if (cfg->method->save_lmf)
2795                                 NOT_IMPLEMENTED;
2796
2797                         code = emit_load_volatile_arguments (cfg, code);
2798                         mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2799                         sparc_set_template (code, sparc_o7);
2800                         sparc_jmpl (code, sparc_o7, sparc_g0, sparc_g0);
2801                         /* Restore parent frame in delay slot */
2802                         sparc_restore_imm (code, sparc_g0, 0, sparc_g0);
2803                         break;
2804                 case OP_CHECK_THIS:
2805                         /* ensure ins->sreg1 is not NULL */
2806                         sparc_ld_imm (code, ins->sreg1, 0, sparc_g0);
2807                         break;
2808                 case OP_ARGLIST:
2809                         sparc_add_imm (code, FALSE, sparc_fp, cfg->sig_cookie, sparc_o7);
2810                         sparc_sti_imm (code, sparc_o7, ins->sreg1, 0);
2811                         break;
2812                 case OP_FCALL:
2813                 case OP_LCALL:
2814                 case OP_VCALL:
2815                 case OP_VOIDCALL:
2816                 case CEE_CALL:
2817                         call = (MonoCallInst*)ins;
2818                         g_assert (!call->virtual);
2819                         code = emit_save_sp_to_lmf (cfg, code);
2820                         if (ins->flags & MONO_INST_HAS_METHOD)
2821                             code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2822                         else
2823                             code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2824
2825                         code = emit_vret_token (ins, code);
2826                         code = emit_move_return_value (ins, code);
2827                         break;
2828                 case OP_FCALL_REG:
2829                 case OP_LCALL_REG:
2830                 case OP_VCALL_REG:
2831                 case OP_VOIDCALL_REG:
2832                 case OP_CALL_REG:
2833                         call = (MonoCallInst*)ins;
2834                         code = emit_save_sp_to_lmf (cfg, code);
2835                         sparc_jmpl (code, ins->sreg1, sparc_g0, sparc_callsite);
2836                         /*
2837                          * We emit a special kind of nop in the delay slot to tell the
2838                          * trampoline code that this is a virtual call, thus an unbox
2839                          * trampoline might need to be called.
2840                          */
2841                         if (call->virtual)
2842                                 sparc_or_imm (code, FALSE, sparc_g0, 0xca, sparc_g0);
2843                         else
2844                                 sparc_nop (code);
2845
2846                         code = emit_vret_token (ins, code);
2847                         code = emit_move_return_value (ins, code);
2848                         break;
2849                 case OP_FCALL_MEMBASE:
2850                 case OP_LCALL_MEMBASE:
2851                 case OP_VCALL_MEMBASE:
2852                 case OP_VOIDCALL_MEMBASE:
2853                 case OP_CALL_MEMBASE:
2854                         call = (MonoCallInst*)ins;
2855                         code = emit_save_sp_to_lmf (cfg, code);
2856                         if (sparc_is_imm13 (ins->inst_offset)) {
2857                                 sparc_ldi_imm (code, ins->inst_basereg, ins->inst_offset, sparc_o7);
2858                         } else {
2859                                 sparc_set (code, ins->inst_offset, sparc_o7);
2860                                 sparc_ldi (code, ins->inst_basereg, sparc_o7, sparc_o7);
2861                         }
2862                         sparc_jmpl (code, sparc_o7, sparc_g0, sparc_callsite);
2863                         if (call->virtual)
2864                                 sparc_or_imm (code, FALSE, sparc_g0, 0xca, sparc_g0);
2865                         else
2866                                 sparc_nop (code);
2867
2868                         code = emit_vret_token (ins, code);
2869                         code = emit_move_return_value (ins, code);
2870                         break;
2871                 case OP_SETFRET:
2872                         if (mono_method_signature (cfg->method)->ret->type == MONO_TYPE_R4)
2873                                 sparc_fdtos (code, ins->sreg1, sparc_f0);
2874                         else {
2875 #ifdef SPARCV9
2876                                 sparc_fmovd (code, ins->sreg1, ins->dreg);
2877 #else
2878                                 /* FIXME: Why not use fmovd ? */
2879                                 sparc_fmovs (code, ins->sreg1, ins->dreg);
2880                                 sparc_fmovs (code, ins->sreg1 + 1, ins->dreg + 1);
2881 #endif
2882                         }
2883                         break;
2884                 case OP_OUTARG:
2885                         g_assert_not_reached ();
2886                         break;
2887                 case OP_LOCALLOC: {
2888                         guint32 size_reg;
2889
2890 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
2891                         /* Perform stack touching */
2892                         NOT_IMPLEMENTED;
2893 #endif
2894
2895                         /* Keep alignment */
2896                         sparc_add_imm (code, FALSE, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1, ins->dreg);
2897                         sparc_set (code, ~(MONO_ARCH_FRAME_ALIGNMENT - 1), sparc_o7);
2898                         sparc_and (code, FALSE, ins->dreg, sparc_o7, ins->dreg);
2899
2900                         if ((ins->flags & MONO_INST_INIT) && (ins->sreg1 == ins->dreg)) {
2901 #ifdef SPARCV9
2902                                 size_reg = sparc_g4;
2903 #else
2904                                 size_reg = sparc_g1;
2905 #endif
2906                                 sparc_mov_reg_reg (code, ins->dreg, size_reg);
2907                         }
2908                         else
2909                                 size_reg = ins->sreg1;
2910
2911                         sparc_sub (code, FALSE, sparc_sp, ins->dreg, ins->dreg);
2912                         /* Keep %sp valid at all times */
2913                         sparc_mov_reg_reg (code, ins->dreg, sparc_sp);
2914                         g_assert (sparc_is_imm13 (MONO_SPARC_STACK_BIAS + cfg->arch.localloc_offset));
2915                         sparc_add_imm (code, FALSE, ins->dreg, MONO_SPARC_STACK_BIAS + cfg->arch.localloc_offset, ins->dreg);
2916
2917                         if (ins->flags & MONO_INST_INIT) {
2918                                 guint32 *br [3];
2919                                 /* Initialize memory region */
2920                                 sparc_cmp_imm (code, size_reg, 0);
2921                                 br [0] = code;
2922                                 sparc_branch (code, 0, sparc_be, 0);
2923                                 /* delay slot */
2924                                 sparc_set (code, 0, sparc_o7);
2925                                 sparc_sub_imm (code, 0, size_reg, sparcv9 ? 8 : 4, size_reg);
2926                                 /* start of loop */
2927                                 br [1] = code;
2928                                 if (sparcv9)
2929                                         sparc_stx (code, sparc_g0, ins->dreg, sparc_o7);
2930                                 else
2931                                         sparc_st (code, sparc_g0, ins->dreg, sparc_o7);
2932                                 sparc_cmp (code, sparc_o7, size_reg);
2933                                 br [2] = code;
2934                                 sparc_branch (code, 0, sparc_bl, 0);
2935                                 sparc_patch (br [2], br [1]);
2936                                 /* delay slot */
2937                                 sparc_add_imm (code, 0, sparc_o7, sparcv9 ? 8 : 4, sparc_o7);
2938                                 sparc_patch (br [0], code);
2939                         }
2940                         break;
2941                 }
2942                 case OP_SPARC_LOCALLOC_IMM: {
2943                         gint32 offset = ins->inst_c0;
2944
2945 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
2946                         /* Perform stack touching */
2947                         NOT_IMPLEMENTED;
2948 #endif
2949
2950                         offset = ALIGN_TO (offset, MONO_ARCH_FRAME_ALIGNMENT);
2951                         if (sparc_is_imm13 (offset))
2952                                 sparc_sub_imm (code, FALSE, sparc_sp, offset, sparc_sp);
2953                         else {
2954                                 sparc_set (code, offset, sparc_o7);
2955                                 sparc_sub (code, FALSE, sparc_sp, sparc_o7, sparc_sp);
2956                         }
2957                         g_assert (sparc_is_imm13 (MONO_SPARC_STACK_BIAS + cfg->arch.localloc_offset));
2958                         sparc_add_imm (code, FALSE, sparc_sp, MONO_SPARC_STACK_BIAS + cfg->arch.localloc_offset, ins->dreg);
2959                         if ((ins->flags & MONO_INST_INIT) && (offset > 0)) {
2960                                 guint32 *br [2];
2961                                 int i;
2962
2963                                 if (offset <= 16) {
2964                                         i = 0;
2965                                         while (i < offset) {
2966                                                 if (sparcv9) {
2967                                                         sparc_stx_imm (code, sparc_g0, ins->dreg, i);
2968                                                         i += 8;
2969                                                 }
2970                                                 else {
2971                                                         sparc_st_imm (code, sparc_g0, ins->dreg, i);
2972                                                         i += 4;
2973                                                 }
2974                                         }
2975                                 }
2976                                 else {
2977                                         sparc_set (code, offset, sparc_o7);
2978                                         sparc_sub_imm (code, 0, sparc_o7, sparcv9 ? 8 : 4, sparc_o7);
2979                                         /* beginning of loop */
2980                                         br [0] = code;
2981                                         if (sparcv9)
2982                                                 sparc_stx (code, sparc_g0, ins->dreg, sparc_o7);
2983                                         else
2984                                                 sparc_st (code, sparc_g0, ins->dreg, sparc_o7);
2985                                         sparc_cmp_imm (code, sparc_o7, 0);
2986                                         br [1] = code;
2987                                         sparc_branch (code, 0, sparc_bne, 0);
2988                                         /* delay slot */
2989                                         sparc_sub_imm (code, 0, sparc_o7, sparcv9 ? 8 : 4, sparc_o7);
2990                                         sparc_patch (br [1], br [0]);
2991                                 }
2992                         }
2993                         break;
2994                 }
2995                 case CEE_RET:
2996                         /* The return is done in the epilog */
2997                         g_assert_not_reached ();
2998                         break;
2999                 case CEE_THROW:
3000                         sparc_mov_reg_reg (code, ins->sreg1, sparc_o0);
3001                         mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3002                                              (gpointer)"mono_arch_throw_exception");
3003                         EMIT_CALL ();
3004                         break;
3005                 case OP_RETHROW:
3006                         sparc_mov_reg_reg (code, ins->sreg1, sparc_o0);
3007                         mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3008                                              (gpointer)"mono_arch_rethrow_exception");
3009                         EMIT_CALL ();
3010                         break;
3011                 case OP_START_HANDLER: {
3012                         /*
3013                          * The START_HANDLER instruction marks the beginning of a handler
3014                          * block. It is called using a call instruction, so %o7 contains
3015                          * the return address. Since the handler executes in the same stack
3016              * frame as the method itself, we can't use save/restore to save
3017                          * the return address. Instead, we save it into a dedicated
3018                          * variable.
3019                          */
3020                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3021                         if (!sparc_is_imm13 (spvar->inst_offset)) {
3022                                 sparc_set (code, spvar->inst_offset, GP_SCRATCH_REG);
3023                                 sparc_sti (code, sparc_o7, spvar->inst_basereg, GP_SCRATCH_REG);
3024                         }
3025                         else
3026                                 sparc_sti_imm (code, sparc_o7, spvar->inst_basereg, spvar->inst_offset);
3027                         break;
3028                 }
3029                 case OP_ENDFILTER: {
3030                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3031                         if (!sparc_is_imm13 (spvar->inst_offset)) {
3032                                 sparc_set (code, spvar->inst_offset, GP_SCRATCH_REG);
3033                                 sparc_ldi (code, spvar->inst_basereg, GP_SCRATCH_REG, sparc_o7);
3034                         }
3035                         else
3036                                 sparc_ldi_imm (code, spvar->inst_basereg, spvar->inst_offset, sparc_o7);
3037                         sparc_jmpl_imm (code, sparc_o7, 8, sparc_g0);
3038                         /* Delay slot */
3039                         sparc_mov_reg_reg (code, ins->sreg1, sparc_o0);
3040                         break;
3041                 }
3042                 case CEE_ENDFINALLY: {
3043                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3044                         if (!sparc_is_imm13 (spvar->inst_offset)) {
3045                                 sparc_set (code, spvar->inst_offset, GP_SCRATCH_REG);
3046                                 sparc_ldi (code, spvar->inst_basereg, GP_SCRATCH_REG, sparc_o7);
3047                         }
3048                         else
3049                                 sparc_ldi_imm (code, spvar->inst_basereg, spvar->inst_offset, sparc_o7);
3050                         sparc_jmpl_imm (code, sparc_o7, 8, sparc_g0);
3051                         sparc_nop (code);
3052                         break;
3053                 }
3054                 case OP_CALL_HANDLER:
3055                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3056                         /* This is a jump inside the method, so call_simple works even on V9 */
3057                         sparc_call_simple (code, 0);
3058                         sparc_nop (code);
3059                         break;
3060                 case OP_LABEL:
3061                         ins->inst_c0 = (guint8*)code - cfg->native_code;
3062                         break;
3063                 case CEE_BR:
3064                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3065                         if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3066                                 break;
3067                         if (ins->flags & MONO_INST_BRLABEL) {
3068                                 if (ins->inst_i0->inst_c0) {
3069                                         gint32 disp = (ins->inst_i0->inst_c0 - ((guint8*)code - cfg->native_code)) >> 2;
3070                                         g_assert (sparc_is_imm22 (disp));
3071                                         sparc_branch (code, 1, sparc_ba, disp);
3072                                 } else {
3073                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3074                                         sparc_branch (code, 1, sparc_ba, 0);
3075                                 }
3076                         } else {
3077                                 if (ins->inst_target_bb->native_offset) {
3078                                         gint32 disp = (ins->inst_target_bb->native_offset - ((guint8*)code - cfg->native_code)) >> 2;
3079                                         g_assert (sparc_is_imm22 (disp));
3080                                         sparc_branch (code, 1, sparc_ba, disp);
3081                                 } else {
3082                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3083                                         sparc_branch (code, 1, sparc_ba, 0);
3084                                 }
3085                         }
3086                         sparc_nop (code);
3087                         break;
3088                 case OP_BR_REG:
3089                         sparc_jmp (code, ins->sreg1, sparc_g0);
3090                         sparc_nop (code);
3091                         break;
3092                 case OP_CEQ:
3093                 case OP_CLT:
3094                 case OP_CLT_UN:
3095                 case OP_CGT:
3096                 case OP_CGT_UN:
3097                         if (v64 && (cfg->opt & MONO_OPT_CMOV)) {
3098                                 sparc_clr_reg (code, ins->dreg);
3099                                 sparc_movcc_imm (code, sparc_xcc, opcode_to_sparc_cond (ins->opcode), 1, ins->dreg);
3100                         }
3101                         else {
3102                                 sparc_clr_reg (code, ins->dreg);
3103 #ifdef SPARCV9
3104                                 sparc_branchp (code, 1, opcode_to_sparc_cond (ins->opcode), DEFAULT_ICC, 0, 2);
3105 #else
3106                                 sparc_branch (code, 1, opcode_to_sparc_cond (ins->opcode), 2);
3107 #endif
3108                                 /* delay slot */
3109                                 sparc_set (code, 1, ins->dreg);
3110                         }
3111                         break;
3112                 case OP_ICEQ:
3113                 case OP_ICLT:
3114                 case OP_ICLT_UN:
3115                 case OP_ICGT:
3116                 case OP_ICGT_UN:
3117                     if (v64 && (cfg->opt & MONO_OPT_CMOV)) {
3118                                 sparc_clr_reg (code, ins->dreg);
3119                                 sparc_movcc_imm (code, sparc_icc, opcode_to_sparc_cond (ins->opcode), 1, ins->dreg);
3120                     }
3121                     else {
3122                         sparc_clr_reg (code, ins->dreg);
3123                         sparc_branchp (code, 1, opcode_to_sparc_cond (ins->opcode), sparc_icc_short, 0, 2);
3124                         /* delay slot */
3125                         sparc_set (code, 1, ins->dreg);
3126                     }
3127                     break;
3128                 case OP_COND_EXC_EQ:
3129                 case OP_COND_EXC_NE_UN:
3130                 case OP_COND_EXC_LT:
3131                 case OP_COND_EXC_LT_UN:
3132                 case OP_COND_EXC_GT:
3133                 case OP_COND_EXC_GT_UN:
3134                 case OP_COND_EXC_GE:
3135                 case OP_COND_EXC_GE_UN:
3136                 case OP_COND_EXC_LE:
3137                 case OP_COND_EXC_LE_UN:
3138                 case OP_COND_EXC_OV:
3139                 case OP_COND_EXC_NO:
3140                 case OP_COND_EXC_C:
3141                 case OP_COND_EXC_NC:
3142                         EMIT_COND_SYSTEM_EXCEPTION (ins, opcode_to_sparc_cond (ins->opcode), ins->inst_p1);
3143                         break;
3144                 case OP_SPARC_COND_EXC_EQZ:
3145                         EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brz, ins->inst_p1);
3146                         break;
3147                 case OP_SPARC_COND_EXC_GEZ:
3148                         EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brgez, ins->inst_p1);
3149                         break;
3150                 case OP_SPARC_COND_EXC_GTZ:
3151                         EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brgz, ins->inst_p1);
3152                         break;
3153                 case OP_SPARC_COND_EXC_LEZ:
3154                         EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brlez, ins->inst_p1);
3155                         break;
3156                 case OP_SPARC_COND_EXC_LTZ:
3157                         EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brlz, ins->inst_p1);
3158                         break;
3159                 case OP_SPARC_COND_EXC_NEZ:
3160                         EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brnz, ins->inst_p1);
3161                         break;
3162                 case OP_COND_EXC_IOV:
3163                 case OP_COND_EXC_IC:
3164                         EMIT_COND_SYSTEM_EXCEPTION_GENERAL (ins, opcode_to_sparc_cond (ins->opcode), ins->inst_p1, TRUE, sparc_icc_short);
3165                         break;
3166                 case CEE_BEQ:
3167                 case CEE_BNE_UN:
3168                 case CEE_BLT:
3169                 case CEE_BLT_UN:
3170                 case CEE_BGT:
3171                 case CEE_BGT_UN:
3172                 case CEE_BGE:
3173                 case CEE_BGE_UN:
3174                 case CEE_BLE:
3175                 case CEE_BLE_UN: {
3176                         if (sparcv9)
3177                                 EMIT_COND_BRANCH_PREDICTED (ins, opcode_to_sparc_cond (ins->opcode), 1, 1);
3178                         else
3179                                 EMIT_COND_BRANCH (ins, opcode_to_sparc_cond (ins->opcode), 1, 1);
3180                         break;
3181                 }
3182
3183                 case OP_IBEQ:
3184                 case OP_IBNE_UN:
3185                 case OP_IBLT:
3186                 case OP_IBLT_UN:
3187                 case OP_IBGT:
3188                 case OP_IBGT_UN:
3189                 case OP_IBGE:
3190                 case OP_IBGE_UN:
3191                 case OP_IBLE:
3192                 case OP_IBLE_UN: {
3193                         /* Only used on V9 */
3194                         EMIT_COND_BRANCH_ICC (ins, opcode_to_sparc_cond (ins->opcode), 1, 1, sparc_icc_short);
3195                         break;
3196                 }
3197
3198                 case OP_SPARC_BRZ:
3199                         EMIT_COND_BRANCH_BPR (ins, brz, 1, 1, 1);
3200                         break;
3201                 case OP_SPARC_BRLEZ:
3202                         EMIT_COND_BRANCH_BPR (ins, brlez, 1, 1, 1);
3203                         break;
3204                 case OP_SPARC_BRLZ:
3205                         EMIT_COND_BRANCH_BPR (ins, brlz, 1, 1, 1);
3206                         break;
3207                 case OP_SPARC_BRNZ:
3208                         EMIT_COND_BRANCH_BPR (ins, brnz, 1, 1, 1);
3209                         break;
3210                 case OP_SPARC_BRGZ:
3211                         EMIT_COND_BRANCH_BPR (ins, brgz, 1, 1, 1);
3212                         break;
3213                 case OP_SPARC_BRGEZ:
3214                         EMIT_COND_BRANCH_BPR (ins, brgez, 1, 1, 1);
3215                         break;
3216
3217                 /* floating point opcodes */
3218                 case OP_R8CONST:
3219                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3220 #ifdef SPARCV9
3221                         sparc_set_template (code, sparc_o7);
3222 #else
3223                         sparc_sethi (code, 0, sparc_o7);
3224 #endif
3225                         sparc_lddf_imm (code, sparc_o7, 0, ins->dreg);
3226                         break;
3227                 case OP_R4CONST:
3228                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3229 #ifdef SPARCV9
3230                         sparc_set_template (code, sparc_o7);
3231 #else
3232                         sparc_sethi (code, 0, sparc_o7);
3233 #endif
3234                         sparc_ldf_imm (code, sparc_o7, 0, FP_SCRATCH_REG);
3235
3236                         /* Extend to double */
3237                         sparc_fstod (code, FP_SCRATCH_REG, ins->dreg);
3238                         break;
3239                 case OP_STORER8_MEMBASE_REG:
3240                         if (!sparc_is_imm13 (ins->inst_offset + 4)) {
3241                                 sparc_set (code, ins->inst_offset, sparc_o7);
3242                                 /* SPARCV9 handles misaligned fp loads/stores */
3243                                 if (!v64 && (ins->inst_offset % 8)) {
3244                                         /* Misaligned */
3245                                         sparc_add (code, FALSE, ins->inst_destbasereg, sparc_o7, sparc_o7);
3246                                         sparc_stf (code, ins->sreg1, sparc_o7, sparc_g0);
3247                                         sparc_stf_imm (code, ins->sreg1 + 1, sparc_o7, 4);
3248                                 } else
3249                                         sparc_stdf (code, ins->sreg1, ins->inst_destbasereg, sparc_o7);
3250                         }
3251                         else {
3252                                 if (!v64 && (ins->inst_offset % 8)) {
3253                                         /* Misaligned */
3254                                         sparc_stf_imm (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3255                                         sparc_stf_imm (code, ins->sreg1 + 1, ins->inst_destbasereg, ins->inst_offset + 4);
3256                                 } else
3257                                         sparc_stdf_imm (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3258                         }
3259                         break;
3260                 case OP_LOADR8_MEMBASE:
3261                         EMIT_LOAD_MEMBASE (ins, lddf);
3262                         break;
3263                 case OP_STORER4_MEMBASE_REG:
3264                         /* This requires a double->single conversion */
3265                         sparc_fdtos (code, ins->sreg1, FP_SCRATCH_REG);
3266                         if (!sparc_is_imm13 (ins->inst_offset)) {
3267                                 sparc_set (code, ins->inst_offset, sparc_o7);
3268                                 sparc_stf (code, FP_SCRATCH_REG, ins->inst_destbasereg, sparc_o7);
3269                         }
3270                         else
3271                                 sparc_stf_imm (code, FP_SCRATCH_REG, ins->inst_destbasereg, ins->inst_offset);
3272                         break;
3273                 case OP_LOADR4_MEMBASE: {
3274                         /* ldf needs a single precision register */
3275                         int dreg = ins->dreg;
3276                         ins->dreg = FP_SCRATCH_REG;
3277                         EMIT_LOAD_MEMBASE (ins, ldf);
3278                         ins->dreg = dreg;
3279                         /* Extend to double */
3280                         sparc_fstod (code, FP_SCRATCH_REG, ins->dreg);
3281                         break;
3282                 }
3283                 case OP_FMOVE:
3284 #ifdef SPARCV9
3285                         sparc_fmovd (code, ins->sreg1, ins->dreg);
3286 #else
3287                         sparc_fmovs (code, ins->sreg1, ins->dreg);
3288                         sparc_fmovs (code, ins->sreg1 + 1, ins->dreg + 1);
3289 #endif
3290                         break;
3291                 case CEE_CONV_R4: {
3292                         gint32 offset = mono_spillvar_offset_float (cfg, 0);
3293 #ifdef SPARCV9
3294                         if (!sparc_is_imm13 (offset)) {
3295                                 sparc_set (code, offset, sparc_o7);
3296                                 sparc_stx (code, ins->sreg1, sparc_sp, offset);
3297                                 sparc_lddf (code, sparc_sp, offset, FP_SCRATCH_REG);
3298                         } else {
3299                                 sparc_stx_imm (code, ins->sreg1, sparc_sp, offset);
3300                                 sparc_lddf_imm (code, sparc_sp, offset, FP_SCRATCH_REG);
3301                         }
3302                         sparc_fxtos (code, FP_SCRATCH_REG, FP_SCRATCH_REG);
3303 #else
3304                         if (!sparc_is_imm13 (offset)) {
3305                                 sparc_set (code, offset, sparc_o7);
3306                                 sparc_st (code, ins->sreg1, sparc_sp, sparc_o7);
3307                                 sparc_ldf (code, sparc_sp, sparc_o7, FP_SCRATCH_REG);
3308                         } else {
3309                                 sparc_st_imm (code, ins->sreg1, sparc_sp, offset);
3310                                 sparc_ldf_imm (code, sparc_sp, offset, FP_SCRATCH_REG);
3311                         }
3312                         sparc_fitos (code, FP_SCRATCH_REG, FP_SCRATCH_REG);
3313 #endif
3314                         sparc_fstod (code, FP_SCRATCH_REG, ins->dreg);
3315                         break;
3316                 }
3317                 case CEE_CONV_R8: {
3318                         gint32 offset = mono_spillvar_offset_float (cfg, 0);
3319 #ifdef SPARCV9
3320                         if (!sparc_is_imm13 (offset)) {
3321                                 sparc_set (code, offset, sparc_o7);
3322                                 sparc_stx (code, ins->sreg1, sparc_sp, sparc_o7);
3323                                 sparc_lddf (code, sparc_sp, sparc_o7, FP_SCRATCH_REG);
3324                         } else {
3325                                 sparc_stx_imm (code, ins->sreg1, sparc_sp, offset);
3326                                 sparc_lddf_imm (code, sparc_sp, offset, FP_SCRATCH_REG);
3327                         }
3328                         sparc_fxtod (code, FP_SCRATCH_REG, ins->dreg);
3329 #else
3330                         if (!sparc_is_imm13 (offset)) {
3331                                 sparc_set (code, offset, sparc_o7);
3332                                 sparc_st (code, ins->sreg1, sparc_sp, sparc_o7);
3333                                 sparc_ldf (code, sparc_sp, sparc_o7, FP_SCRATCH_REG);
3334                         } else {
3335                                 sparc_st_imm (code, ins->sreg1, sparc_sp, offset);
3336                                 sparc_ldf_imm (code, sparc_sp, offset, FP_SCRATCH_REG);
3337                         }
3338                         sparc_fitod (code, FP_SCRATCH_REG, ins->dreg);
3339 #endif
3340                         break;
3341                 }
3342                 case OP_FCONV_TO_I1:
3343                 case OP_FCONV_TO_U1:
3344                 case OP_FCONV_TO_I2:
3345                 case OP_FCONV_TO_U2:
3346 #ifndef SPARCV9
3347                 case OP_FCONV_TO_I:
3348                 case OP_FCONV_TO_U:
3349 #endif
3350                 case OP_FCONV_TO_I4:
3351                 case OP_FCONV_TO_U4: {
3352                         gint32 offset = mono_spillvar_offset_float (cfg, 0);
3353                         sparc_fdtoi (code, ins->sreg1, FP_SCRATCH_REG);
3354                         if (!sparc_is_imm13 (offset)) {
3355                                 sparc_set (code, offset, sparc_o7);
3356                                 sparc_stdf (code, FP_SCRATCH_REG, sparc_sp, sparc_o7);
3357                                 sparc_ld (code, sparc_sp, sparc_o7, ins->dreg);
3358                         } else {
3359                                 sparc_stdf_imm (code, FP_SCRATCH_REG, sparc_sp, offset);
3360                                 sparc_ld_imm (code, sparc_sp, offset, ins->dreg);
3361                         }
3362
3363                         switch (ins->opcode) {
3364                         case OP_FCONV_TO_I1:
3365                         case OP_FCONV_TO_U1:
3366                                 sparc_and_imm (code, 0, ins->dreg, 0xff, ins->dreg);
3367                                 break;
3368                         case OP_FCONV_TO_I2:
3369                         case OP_FCONV_TO_U2:
3370                                 sparc_set (code, 0xffff, sparc_o7);
3371                                 sparc_and (code, 0, ins->dreg, sparc_o7, ins->dreg);
3372                                 break;
3373                         default:
3374                                 break;
3375                         }
3376                         break;
3377                 }
3378                 case OP_FCONV_TO_I8:
3379                 case OP_FCONV_TO_U8:
3380                         /* Emulated */
3381                         g_assert_not_reached ();
3382                         break;
3383                 case CEE_CONV_R_UN:
3384                         /* Emulated */
3385                         g_assert_not_reached ();
3386                         break;
3387                 case OP_LCONV_TO_R_UN: {
3388                         /* Emulated */
3389                         g_assert_not_reached ();
3390                         break;
3391                 }
3392                 case OP_LCONV_TO_OVF_I: {
3393                         guint32 *br [3], *label [1];
3394
3395                         /*
3396                          * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3397                          */
3398                         sparc_cmp_imm (code, ins->sreg1, 0);
3399                         br [0] = code;
3400                         sparc_branch (code, 1, sparc_bneg, 0);
3401                         sparc_nop (code);
3402
3403                         /* positive */
3404                         /* ms word must be 0 */
3405                         sparc_cmp_imm (code, ins->sreg2, 0);
3406                         br [1] = code;
3407                         sparc_branch (code, 1, sparc_be, 0);
3408                         sparc_nop (code);
3409
3410                         label [0] = code;
3411
3412                         EMIT_COND_SYSTEM_EXCEPTION (ins, sparc_ba, "OverflowException");
3413
3414                         /* negative */
3415                         sparc_patch (br [0], code);
3416
3417                         /* ms word must 0xfffffff */
3418                         sparc_cmp_imm (code, ins->sreg2, -1);
3419                         br [2] = code;
3420                         sparc_branch (code, 1, sparc_bne, 0);
3421                         sparc_nop (code);
3422                         sparc_patch (br [2], label [0]);
3423
3424                         /* Ok */
3425                         sparc_patch (br [1], code);
3426                         if (ins->sreg1 != ins->dreg)
3427                                 sparc_mov_reg_reg (code, ins->sreg1, ins->dreg);
3428                         break;
3429                 }
3430                 case OP_FADD:
3431                         sparc_faddd (code, ins->sreg1, ins->sreg2, ins->dreg);
3432                         break;
3433                 case OP_FSUB:
3434                         sparc_fsubd (code, ins->sreg1, ins->sreg2, ins->dreg);
3435                         break;
3436                 case OP_FMUL:
3437                         sparc_fmuld (code, ins->sreg1, ins->sreg2, ins->dreg);
3438                         break;
3439                 case OP_FDIV:
3440                         sparc_fdivd (code, ins->sreg1, ins->sreg2, ins->dreg);
3441                         break;
3442                 case OP_FNEG:
3443 #ifdef SPARCV9
3444                         sparc_fnegd (code, ins->sreg1, ins->dreg);
3445 #else
3446                         /* FIXME: why don't use fnegd ? */
3447                         sparc_fnegs (code, ins->sreg1, ins->dreg);
3448 #endif
3449                         break;
3450                 case OP_FREM:
3451                         sparc_fdivd (code, ins->sreg1, ins->sreg2, FP_SCRATCH_REG);
3452                         sparc_fmuld (code, ins->sreg2, FP_SCRATCH_REG, FP_SCRATCH_REG);
3453                         sparc_fsubd (code, ins->sreg1, FP_SCRATCH_REG, ins->dreg);
3454                         break;
3455                 case OP_FCOMPARE:
3456                         sparc_fcmpd (code, ins->sreg1, ins->sreg2);
3457                         break;
3458                 case OP_FCEQ:
3459                 case OP_FCLT:
3460                 case OP_FCLT_UN:
3461                 case OP_FCGT:
3462                 case OP_FCGT_UN:
3463                         sparc_fcmpd (code, ins->sreg1, ins->sreg2);
3464                         sparc_clr_reg (code, ins->dreg);
3465                         switch (ins->opcode) {
3466                         case OP_FCLT_UN:
3467                         case OP_FCGT_UN:
3468                                 sparc_fbranch (code, 1, opcode_to_sparc_cond (ins->opcode), 4);
3469                                 /* delay slot */
3470                                 sparc_set (code, 1, ins->dreg);
3471                                 sparc_fbranch (code, 1, sparc_fbu, 2);
3472                                 /* delay slot */
3473                                 sparc_set (code, 1, ins->dreg);
3474                                 break;
3475                         default:
3476                                 sparc_fbranch (code, 1, opcode_to_sparc_cond (ins->opcode), 2);
3477                                 /* delay slot */
3478                                 sparc_set (code, 1, ins->dreg);
3479                         }
3480                         break;
3481                 case OP_FBEQ:
3482                 case OP_FBLT:
3483                 case OP_FBGT:
3484                         EMIT_FLOAT_COND_BRANCH (ins, opcode_to_sparc_cond (ins->opcode), 1, 1);
3485                         break;
3486                 case OP_FBGE: {
3487                         /* clt.un + brfalse */
3488                         guint32 *p = code;
3489                         sparc_fbranch (code, 1, sparc_fbul, 0);
3490                         /* delay slot */
3491                         sparc_nop (code);
3492                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fba, 1, 1);
3493                         sparc_patch (p, (guint8*)code);
3494                         break;
3495                 }
3496                 case OP_FBLE: {
3497                         /* cgt.un + brfalse */
3498                         guint32 *p = code;
3499                         sparc_fbranch (code, 1, sparc_fbug, 0);
3500                         /* delay slot */
3501                         sparc_nop (code);
3502                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fba, 1, 1);
3503                         sparc_patch (p, (guint8*)code);
3504                         break;
3505                 }
3506                 case OP_FBNE_UN:
3507                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbne, 1, 1);
3508                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbu, 1, 1);
3509                         break;
3510                 case OP_FBLT_UN:
3511                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbl, 1, 1);
3512                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbu, 1, 1);
3513                         break;
3514                 case OP_FBGT_UN:
3515                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbg, 1, 1);
3516                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbu, 1, 1);
3517                         break;
3518                 case OP_FBGE_UN:
3519                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbge, 1, 1);
3520                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbu, 1, 1);
3521                         break;
3522                 case OP_FBLE_UN:
3523                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fble, 1, 1);
3524                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbu, 1, 1);
3525                         break;
3526                 case CEE_CKFINITE: {
3527                         gint32 offset = mono_spillvar_offset_float (cfg, 0);
3528                         if (!sparc_is_imm13 (offset)) {
3529                                 sparc_set (code, offset, sparc_o7);
3530                                 sparc_stdf (code, ins->sreg1, sparc_sp, sparc_o7);
3531                                 sparc_lduh (code, sparc_sp, sparc_o7, sparc_o7);
3532                         } else {
3533                                 sparc_stdf_imm (code, ins->sreg1, sparc_sp, offset);
3534                                 sparc_lduh_imm (code, sparc_sp, offset, sparc_o7);
3535                         }
3536                         sparc_srl_imm (code, sparc_o7, 4, sparc_o7);
3537                         sparc_and_imm (code, FALSE, sparc_o7, 2047, sparc_o7);
3538                         sparc_cmp_imm (code, sparc_o7, 2047);
3539                         EMIT_COND_SYSTEM_EXCEPTION (ins, sparc_be, "ArithmeticException");
3540 #ifdef SPARCV9
3541                         sparc_fmovd (code, ins->sreg1, ins->dreg);
3542 #else
3543                         sparc_fmovs (code, ins->sreg1, ins->dreg);
3544                         sparc_fmovs (code, ins->sreg1 + 1, ins->dreg + 1);
3545 #endif
3546                         break;
3547                 }
3548
3549                 case OP_MEMORY_BARRIER:
3550                         sparc_membar (code, sparc_membar_all);
3551                         break;
3552
3553                 default:
3554 #ifdef __GNUC__
3555                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3556 #else
3557                         g_warning ("%s:%d: unknown opcode %s\n", __FILE__, __LINE__, mono_inst_name (ins->opcode));
3558 #endif
3559                         g_assert_not_reached ();
3560                 }
3561
3562                 if ((((guint8*)code) - code_start) > max_len) {
3563                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
3564                                    mono_inst_name (ins->opcode), max_len, ((guint8*)code) - code_start);
3565                         g_assert_not_reached ();
3566                 }
3567
3568                 cpos += max_len;
3569
3570                 last_ins = ins;
3571
3572                 ins = ins->next;
3573         }
3574
3575         cfg->code_len = (guint8*)code - cfg->native_code;
3576 }
3577
3578 void
3579 mono_arch_register_lowlevel_calls (void)
3580 {
3581         mono_register_jit_icall (mono_arch_break, "mono_arch_break", NULL, TRUE);
3582         mono_register_jit_icall (mono_arch_get_lmf_addr, "mono_arch_get_lmf_addr", NULL, TRUE);
3583 }
3584
3585 void
3586 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3587 {
3588         MonoJumpInfo *patch_info;
3589
3590         /* FIXME: Move part of this to arch independent code */
3591         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3592                 unsigned char *ip = patch_info->ip.i + code;
3593                 gpointer target;
3594
3595                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3596
3597                 switch (patch_info->type) {
3598                 case MONO_PATCH_INFO_NONE:
3599                         continue;
3600                 case MONO_PATCH_INFO_CLASS_INIT: {
3601                         guint32 *ip2 = (guint32*)ip;
3602                         /* Might already been changed to a nop */
3603 #ifdef SPARCV9
3604                         sparc_set_template (ip2, sparc_o7);
3605                         sparc_jmpl (ip2, sparc_o7, sparc_g0, sparc_o7);
3606 #else
3607                         sparc_call_simple (ip2, 0);
3608 #endif
3609                         break;
3610                 }
3611                 case MONO_PATCH_INFO_METHOD_JUMP: {
3612                         guint32 *ip2 = (guint32*)ip;
3613                         /* Might already been patched */
3614                         sparc_set_template (ip2, sparc_o7);
3615                         break;
3616                 }
3617                 default:
3618                         break;
3619                 }
3620                 sparc_patch ((guint32*)ip, target);
3621         }
3622 }
3623
3624 void*
3625 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3626 {
3627         int i;
3628         guint32 *code = (guint32*)p;
3629         MonoMethodSignature *sig = mono_method_signature (cfg->method);
3630         CallInfo *cinfo;
3631
3632         /* Save registers to stack */
3633         for (i = 0; i < 6; ++i)
3634                 sparc_sti_imm (code, sparc_i0 + i, sparc_fp, ARGS_OFFSET + (i * sizeof (gpointer)));
3635
3636         cinfo = get_call_info (sig, FALSE);
3637
3638         /* Save float regs on V9, since they are caller saved */
3639         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3640                 ArgInfo *ainfo = cinfo->args + i;
3641                 gint32 stack_offset;
3642
3643                 stack_offset = ainfo->offset + ARGS_OFFSET;
3644
3645                 if (ainfo->storage == ArgInFloatReg) {
3646                         if (!sparc_is_imm13 (stack_offset))
3647                                 NOT_IMPLEMENTED;
3648                         sparc_stf_imm (code, ainfo->reg, sparc_fp, stack_offset);
3649                 }
3650                 else if (ainfo->storage == ArgInDoubleReg) {
3651                         /* The offset is guaranteed to be aligned by the ABI rules */
3652                         sparc_stdf_imm (code, ainfo->reg, sparc_fp, stack_offset);
3653                 }
3654         }
3655
3656         sparc_set (code, cfg->method, sparc_o0);
3657         sparc_add_imm (code, FALSE, sparc_fp, MONO_SPARC_STACK_BIAS, sparc_o1);
3658
3659         mono_add_patch_info (cfg, (guint8*)code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
3660         EMIT_CALL ();
3661
3662         /* Restore float regs on V9 */
3663         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3664                 ArgInfo *ainfo = cinfo->args + i;
3665                 gint32 stack_offset;
3666
3667                 stack_offset = ainfo->offset + ARGS_OFFSET;
3668
3669                 if (ainfo->storage == ArgInFloatReg) {
3670                         if (!sparc_is_imm13 (stack_offset))
3671                                 NOT_IMPLEMENTED;
3672                         sparc_ldf_imm (code, sparc_fp, stack_offset, ainfo->reg);
3673                 }
3674                 else if (ainfo->storage == ArgInDoubleReg) {
3675                         /* The offset is guaranteed to be aligned by the ABI rules */
3676                         sparc_lddf_imm (code, sparc_fp, stack_offset, ainfo->reg);
3677                 }
3678         }
3679
3680         g_free (cinfo);
3681
3682         return code;
3683 }
3684
3685 enum {
3686         SAVE_NONE,
3687         SAVE_STRUCT,
3688         SAVE_ONE,
3689         SAVE_TWO,
3690         SAVE_FP
3691 };
3692
3693 void*
3694 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3695 {
3696         guint32 *code = (guint32*)p;
3697         int save_mode = SAVE_NONE;
3698         MonoMethod *method = cfg->method;
3699
3700         switch (mono_type_get_underlying_type (mono_method_signature (method)->ret)->type) {
3701         case MONO_TYPE_VOID:
3702                 /* special case string .ctor icall */
3703                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3704                         save_mode = SAVE_ONE;
3705                 else
3706                         save_mode = SAVE_NONE;
3707                 break;
3708         case MONO_TYPE_I8:
3709         case MONO_TYPE_U8:
3710 #ifdef SPARCV9
3711                 save_mode = SAVE_ONE;
3712 #else
3713                 save_mode = SAVE_TWO;
3714 #endif
3715                 break;
3716         case MONO_TYPE_R4:
3717         case MONO_TYPE_R8:
3718                 save_mode = SAVE_FP;
3719                 break;
3720         case MONO_TYPE_VALUETYPE:
3721                 save_mode = SAVE_STRUCT;
3722                 break;
3723         default:
3724                 save_mode = SAVE_ONE;
3725                 break;
3726         }
3727
3728         /* Save the result to the stack and also put it into the output registers */
3729
3730         switch (save_mode) {
3731         case SAVE_TWO:
3732                 /* V8 only */
3733                 sparc_st_imm (code, sparc_i0, sparc_fp, 68);
3734                 sparc_st_imm (code, sparc_i0, sparc_fp, 72);
3735                 sparc_mov_reg_reg (code, sparc_i0, sparc_o1);
3736                 sparc_mov_reg_reg (code, sparc_i1, sparc_o2);
3737                 break;
3738         case SAVE_ONE:
3739                 sparc_sti_imm (code, sparc_i0, sparc_fp, ARGS_OFFSET);
3740                 sparc_mov_reg_reg (code, sparc_i0, sparc_o1);
3741                 break;
3742         case SAVE_FP:
3743 #ifdef SPARCV9
3744                 sparc_stdf_imm (code, sparc_f0, sparc_fp, ARGS_OFFSET);
3745 #else
3746                 sparc_stdf_imm (code, sparc_f0, sparc_fp, 72);
3747                 sparc_ld_imm (code, sparc_fp, 72, sparc_o1);
3748                 sparc_ld_imm (code, sparc_fp, 72 + 4, sparc_o2);
3749 #endif
3750                 break;
3751         case SAVE_STRUCT:
3752 #ifdef SPARCV9
3753                 sparc_mov_reg_reg (code, sparc_i0, sparc_o1);
3754 #else
3755                 sparc_ld_imm (code, sparc_fp, 64, sparc_o1);
3756 #endif
3757                 break;
3758         case SAVE_NONE:
3759         default:
3760                 break;
3761         }
3762
3763         sparc_set (code, cfg->method, sparc_o0);
3764
3765         mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_ABS, func);
3766         EMIT_CALL ();
3767
3768         /* Restore result */
3769
3770         switch (save_mode) {
3771         case SAVE_TWO:
3772                 sparc_ld_imm (code, sparc_fp, 68, sparc_i0);
3773                 sparc_ld_imm (code, sparc_fp, 72, sparc_i0);
3774                 break;
3775         case SAVE_ONE:
3776                 sparc_ldi_imm (code, sparc_fp, ARGS_OFFSET, sparc_i0);
3777                 break;
3778         case SAVE_FP:
3779                 sparc_lddf_imm (code, sparc_fp, ARGS_OFFSET, sparc_f0);
3780                 break;
3781         case SAVE_NONE:
3782         default:
3783                 break;
3784         }
3785
3786         return code;
3787 }
3788
3789 guint8 *
3790 mono_arch_emit_prolog (MonoCompile *cfg)
3791 {
3792         MonoMethod *method = cfg->method;
3793         MonoMethodSignature *sig;
3794         MonoInst *inst;
3795         guint32 *code;
3796         CallInfo *cinfo;
3797         guint32 i, offset;
3798
3799         cfg->code_size = 256;
3800         cfg->native_code = g_malloc (cfg->code_size);
3801         code = (guint32*)cfg->native_code;
3802
3803         /* FIXME: Generate intermediate code instead */
3804
3805         offset = cfg->stack_offset;
3806         offset += (16 * sizeof (gpointer)); /* register save area */
3807 #ifndef SPARCV9
3808         offset += 4; /* struct/union return pointer */
3809 #endif
3810
3811         /* add parameter area size for called functions */
3812         if (cfg->param_area < (6 * sizeof (gpointer)))
3813                 /* Reserve space for the first 6 arguments even if it is unused */
3814                 offset += 6 * sizeof (gpointer);
3815         else
3816                 offset += cfg->param_area;
3817
3818         /* align the stack size */
3819         offset = ALIGN_TO (offset, MONO_ARCH_FRAME_ALIGNMENT);
3820
3821         /*
3822          * localloc'd memory is stored between the local variables (whose
3823          * size is given by cfg->stack_offset), and between the space reserved
3824          * by the ABI.
3825          */
3826         cfg->arch.localloc_offset = offset - cfg->stack_offset;
3827
3828         cfg->stack_offset = offset;
3829
3830 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3831                         /* Perform stack touching */
3832                         NOT_IMPLEMENTED;
3833 #endif
3834
3835         if (!sparc_is_imm13 (- cfg->stack_offset)) {
3836                 /* Can't use sparc_o7 here, since we're still in the caller's frame */
3837                 sparc_set (code, (- cfg->stack_offset), GP_SCRATCH_REG);
3838                 sparc_save (code, sparc_sp, GP_SCRATCH_REG, sparc_sp);
3839         }
3840         else
3841                 sparc_save_imm (code, sparc_sp, - cfg->stack_offset, sparc_sp);
3842
3843 /*
3844         if (strstr (cfg->method->name, "foo")) {
3845                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_ABS, mono_sparc_break);
3846                 sparc_call_simple (code, 0);
3847                 sparc_nop (code);
3848         }
3849 */
3850
3851         sig = mono_method_signature (method);
3852
3853         cinfo = get_call_info (sig, FALSE);
3854
3855         /* Keep in sync with emit_load_volatile_arguments */
3856         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3857                 ArgInfo *ainfo = cinfo->args + i;
3858                 gint32 stack_offset;
3859                 MonoType *arg_type;
3860                 inst = cfg->varinfo [i];
3861
3862                 if (sig->hasthis && (i == 0))
3863                         arg_type = &mono_defaults.object_class->byval_arg;
3864                 else
3865                         arg_type = sig->params [i - sig->hasthis];
3866
3867                 stack_offset = ainfo->offset + ARGS_OFFSET;
3868
3869                 /* Save the split arguments so they will reside entirely on the stack */
3870                 if (ainfo->storage == ArgInSplitRegStack) {
3871                         /* Save the register to the stack */
3872                         g_assert (inst->opcode == OP_REGOFFSET);
3873                         if (!sparc_is_imm13 (stack_offset))
3874                                 NOT_IMPLEMENTED;
3875                         sparc_st_imm (code, sparc_i5, inst->inst_basereg, stack_offset);
3876                 }
3877
3878                 if (!v64 && !arg_type->byref && (arg_type->type == MONO_TYPE_R8)) {
3879                         /* Save the argument to a dword aligned stack location */
3880                         /*
3881                          * stack_offset contains the offset of the argument on the stack.
3882                          * inst->inst_offset contains the dword aligned offset where the value
3883                          * should be stored.
3884                          */
3885                         if (ainfo->storage == ArgInIRegPair) {
3886                                 if (!sparc_is_imm13 (inst->inst_offset + 4))
3887                                         NOT_IMPLEMENTED;
3888                                 sparc_st_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, inst->inst_offset);
3889                                 sparc_st_imm (code, sparc_i0 + ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
3890                         }
3891                         else
3892                                 if (ainfo->storage == ArgInSplitRegStack) {
3893 #ifdef SPARCV9
3894                                         g_assert_not_reached ();
3895 #endif
3896                                         if (stack_offset != inst->inst_offset) {
3897                                                 /* stack_offset is not dword aligned, so we need to make a copy */
3898                                                 sparc_st_imm (code, sparc_i5, inst->inst_basereg, inst->inst_offset);
3899                                                 sparc_ld_imm (code, sparc_fp, stack_offset + 4, sparc_o7);
3900                                                 sparc_st_imm (code, sparc_o7, inst->inst_basereg, inst->inst_offset + 4);
3901                                         }
3902                                 }
3903                         else
3904                                 if (ainfo->storage == ArgOnStackPair) {
3905 #ifdef SPARCV9
3906                                         g_assert_not_reached ();
3907 #endif
3908                                         if (stack_offset != inst->inst_offset) {
3909                                                 /* stack_offset is not dword aligned, so we need to make a copy */
3910                                                 sparc_ld_imm (code, sparc_fp, stack_offset, sparc_o7);
3911                                                 sparc_st_imm (code, sparc_o7, inst->inst_basereg, inst->inst_offset);
3912                                                 sparc_ld_imm (code, sparc_fp, stack_offset + 4, sparc_o7);
3913                                                 sparc_st_imm (code, sparc_o7, inst->inst_basereg, inst->inst_offset + 4);
3914                                         }
3915                                 }
3916                         else
3917                                 g_assert_not_reached ();
3918                 }
3919                 else
3920                         if ((ainfo->storage == ArgInIReg) && (inst->opcode != OP_REGVAR)) {
3921                                 /* Argument in register, but need to be saved to stack */
3922                                 if (!sparc_is_imm13 (stack_offset))
3923                                         NOT_IMPLEMENTED;
3924                                 if ((stack_offset - ARGS_OFFSET) & 0x1)
3925                                         sparc_stb_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, stack_offset);
3926                                 else
3927                                         if ((stack_offset - ARGS_OFFSET) & 0x2)
3928                                                 sparc_sth_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, stack_offset);
3929                                 else
3930                                         if ((stack_offset - ARGS_OFFSET) & 0x4)
3931                                                 sparc_st_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, stack_offset);
3932                                         else {
3933                                                 if (v64)
3934                                                         sparc_stx_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, stack_offset);
3935                                                 else
3936                                                         sparc_st_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, stack_offset);
3937                                         }
3938                         }
3939                 else
3940                         if ((ainfo->storage == ArgInIRegPair) && (inst->opcode != OP_REGVAR)) {
3941 #ifdef SPARCV9
3942                                 NOT_IMPLEMENTED;
3943 #endif
3944                                 /* Argument in regpair, but need to be saved to stack */
3945                                 if (!sparc_is_imm13 (inst->inst_offset + 4))
3946                                         NOT_IMPLEMENTED;
3947                                 sparc_st_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, inst->inst_offset);
3948                                 sparc_st_imm (code, sparc_i0 + ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
3949                         }
3950                 else if ((ainfo->storage == ArgInFloatReg) && (inst->opcode != OP_REGVAR)) {
3951                                 if (!sparc_is_imm13 (stack_offset))
3952                                         NOT_IMPLEMENTED;
3953                                 sparc_stf_imm (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3954                                 }
3955                         else if ((ainfo->storage == ArgInDoubleReg) && (inst->opcode != OP_REGVAR)) {
3956                                 /* The offset is guaranteed to be aligned by the ABI rules */
3957                                 sparc_stdf_imm (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3958                         }
3959
3960                 if ((ainfo->storage == ArgInFloatReg) && (inst->opcode == OP_REGVAR)) {
3961                         /* Need to move into the a double precision register */
3962                         sparc_fstod (code, ainfo->reg, ainfo->reg - 1);
3963                 }
3964
3965                 if ((ainfo->storage == ArgInSplitRegStack) || (ainfo->storage == ArgOnStack))
3966                         if (inst->opcode == OP_REGVAR)
3967                                 /* FIXME: Load the argument into memory */
3968                                 NOT_IMPLEMENTED;
3969         }
3970
3971         g_free (cinfo);
3972
3973         if (cfg->method->save_lmf) {
3974                 gint32 lmf_offset = STACK_BIAS - cfg->arch.lmf_offset;
3975
3976                 /* Save ip */
3977                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
3978                 sparc_set_template (code, sparc_o7);
3979                 sparc_sti_imm (code, sparc_o7, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ip));
3980                 /* Save sp */
3981                 sparc_sti_imm (code, sparc_sp, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, sp));
3982                 /* Save fp */
3983                 sparc_sti_imm (code, sparc_fp, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp));
3984                 /* Save method */
3985                 /* FIXME: add a relocation for this */
3986                 sparc_set (code, cfg->method, sparc_o7);
3987                 sparc_sti_imm (code, sparc_o7, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method));
3988
3989                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3990                                                          (gpointer)"mono_arch_get_lmf_addr");
3991                 EMIT_CALL ();
3992
3993                 code = (guint32*)mono_sparc_emit_save_lmf (code, lmf_offset);
3994         }
3995
3996         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3997                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
3998
3999         cfg->code_len = (guint8*)code - cfg->native_code;
4000
4001         g_assert (cfg->code_len <= cfg->code_size);
4002
4003         return (guint8*)code;
4004 }
4005
4006 void
4007 mono_arch_emit_epilog (MonoCompile *cfg)
4008 {
4009         MonoMethod *method = cfg->method;
4010         guint32 *code;
4011         int can_fold = 0;
4012         int max_epilog_size = 16 + 20 * 4;
4013
4014         if (cfg->method->save_lmf)
4015                 max_epilog_size += 128;
4016
4017         if (mono_jit_trace_calls != NULL)
4018                 max_epilog_size += 50;
4019
4020         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4021                 max_epilog_size += 50;
4022
4023         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4024                 cfg->code_size *= 2;
4025                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4026                 mono_jit_stats.code_reallocs++;
4027         }
4028
4029         code = (guint32*)(cfg->native_code + cfg->code_len);
4030
4031         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4032                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4033
4034         if (cfg->method->save_lmf) {
4035                 gint32 lmf_offset = STACK_BIAS - cfg->arch.lmf_offset;
4036
4037                 code = mono_sparc_emit_restore_lmf (code, lmf_offset);
4038         }
4039
4040         /*
4041          * The V8 ABI requires that calls to functions which return a structure
4042          * return to %i7+12
4043          */
4044         if (!v64 && mono_method_signature (cfg->method)->pinvoke && MONO_TYPE_ISSTRUCT(mono_method_signature (cfg->method)->ret))
4045                 sparc_jmpl_imm (code, sparc_i7, 12, sparc_g0);
4046         else
4047                 sparc_ret (code);
4048
4049         /* Only fold last instruction into the restore if the exit block has an in count of 1
4050            and the previous block hasn't been optimized away since it may have an in count > 1 */
4051         if (cfg->bb_exit->in_count == 1 && cfg->bb_exit->in_bb[0]->native_offset != cfg->bb_exit->native_offset)
4052                 can_fold = 1;
4053
4054         /* Try folding last instruction into the restore */
4055         if (can_fold && (sparc_inst_op (code [-2]) == 0x2) && (sparc_inst_op3 (code [-2]) == 0x2) && sparc_inst_imm (code [-2]) && (sparc_inst_rd (code [-2]) == sparc_i0)) {
4056                 /* or reg, imm, %i0 */
4057                 int reg = sparc_inst_rs1 (code [-2]);
4058                 int imm = sparc_inst_imm13 (code [-2]);
4059                 code [-2] = code [-1];
4060                 code --;
4061                 sparc_restore_imm (code, reg, imm, sparc_o0);
4062         }
4063         else
4064         if (can_fold && (sparc_inst_op (code [-2]) == 0x2) && (sparc_inst_op3 (code [-2]) == 0x2) && (!sparc_inst_imm (code [-2])) && (sparc_inst_rd (code [-2]) == sparc_i0)) {
4065                 /* or reg, reg, %i0 */
4066                 int reg1 = sparc_inst_rs1 (code [-2]);
4067                 int reg2 = sparc_inst_rs2 (code [-2]);
4068                 code [-2] = code [-1];
4069                 code --;
4070                 sparc_restore (code, reg1, reg2, sparc_o0);
4071         }
4072         else
4073                 sparc_restore_imm (code, sparc_g0, 0, sparc_g0);
4074
4075         cfg->code_len = (guint8*)code - cfg->native_code;
4076
4077         g_assert (cfg->code_len < cfg->code_size);
4078
4079 }
4080
4081 void
4082 mono_arch_emit_exceptions (MonoCompile *cfg)
4083 {
4084         MonoJumpInfo *patch_info;
4085         guint32 *code;
4086         int nthrows = 0, i;
4087         int exc_count = 0;
4088         guint32 code_size;
4089         MonoClass *exc_classes [16];
4090         guint8 *exc_throw_start [16], *exc_throw_end [16];
4091
4092         /* Compute needed space */
4093         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4094                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4095                         exc_count++;
4096         }
4097
4098         /*
4099          * make sure we have enough space for exceptions
4100          */
4101 #ifdef SPARCV9
4102         code_size = exc_count * (20 * 4);
4103 #else
4104         code_size = exc_count * 24;
4105 #endif
4106
4107         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4108                 cfg->code_size *= 2;
4109                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4110                 mono_jit_stats.code_reallocs++;
4111         }
4112
4113         code = (guint32*)(cfg->native_code + cfg->code_len);
4114
4115         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4116                 switch (patch_info->type) {
4117                 case MONO_PATCH_INFO_EXC: {
4118                         MonoClass *exc_class;
4119                         guint32 *buf, *buf2;
4120                         guint32 throw_ip, type_idx;
4121                         gint32 disp;
4122
4123                         sparc_patch ((guint32*)(cfg->native_code + patch_info->ip.i), code);
4124
4125                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4126                         type_idx = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
4127                         g_assert (exc_class);
4128                         throw_ip = patch_info->ip.i;
4129
4130                         /* Find a throw sequence for the same exception class */
4131                         for (i = 0; i < nthrows; ++i)
4132                                 if (exc_classes [i] == exc_class)
4133                                         break;
4134
4135                         if (i < nthrows) {
4136                                 guint32 throw_offset = (((guint8*)exc_throw_end [i] - cfg->native_code) - throw_ip) >> 2;
4137                                 if (!sparc_is_imm13 (throw_offset))
4138                                         sparc_set32 (code, throw_offset, sparc_o1);
4139
4140                                 disp = (exc_throw_start [i] - (guint8*)code) >> 2;
4141                                 g_assert (sparc_is_imm22 (disp));
4142                                 sparc_branch (code, 0, sparc_ba, disp);
4143                                 if (sparc_is_imm13 (throw_offset))
4144                                         sparc_set32 (code, throw_offset, sparc_o1);
4145                                 else
4146                                         sparc_nop (code);
4147                                 patch_info->type = MONO_PATCH_INFO_NONE;
4148                         }
4149                         else {
4150                                 /* Emit the template for setting o1 */
4151                                 buf = code;
4152                                 if (sparc_is_imm13 (((((guint8*)code - cfg->native_code) - throw_ip) >> 2) - 8))
4153                                         /* Can use a short form */
4154                                         sparc_nop (code);
4155                                 else
4156                                         sparc_set_template (code, sparc_o1);
4157                                 buf2 = code;
4158
4159                                 if (nthrows < 16) {
4160                                         exc_classes [nthrows] = exc_class;
4161                                         exc_throw_start [nthrows] = (guint8*)code;
4162                                 }
4163
4164                                 /*
4165                                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_ABS, mono_sparc_break);
4166                                 EMIT_CALL();
4167                                 */
4168
4169                                 /* first arg = type token */
4170                                 /* Pass the type index to reduce the size of the sparc_set */
4171                                 if (!sparc_is_imm13 (type_idx))
4172                                         sparc_set32 (code, type_idx, sparc_o0);
4173
4174                                 /* second arg = offset between the throw ip and the current ip */
4175                                 /* On sparc, the saved ip points to the call instruction */
4176                                 disp = (((guint8*)code - cfg->native_code) - throw_ip) >> 2;
4177                                 sparc_set32 (buf, disp, sparc_o1);
4178                                 while (buf < buf2)
4179                                         sparc_nop (buf);
4180
4181                                 if (nthrows < 16) {
4182                                         exc_throw_end [nthrows] = (guint8*)code;
4183                                         nthrows ++;
4184                                 }
4185
4186                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4187                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4188                                 patch_info->ip.i = (guint8*)code - cfg->native_code;
4189
4190                                 EMIT_CALL ();
4191
4192                                 if (sparc_is_imm13 (type_idx)) {
4193                                         /* Put it into the delay slot */
4194                                         code --;
4195                                         buf = code;
4196                                         sparc_set32 (code, type_idx, sparc_o0);
4197                                         g_assert (code - buf == 1);
4198                                 }
4199                         }
4200                         break;
4201                 }
4202                 default:
4203                         /* do nothing */
4204                         break;
4205                 }
4206         }
4207
4208         cfg->code_len = (guint8*)code - cfg->native_code;
4209
4210         g_assert (cfg->code_len < cfg->code_size);
4211
4212 }
4213
4214 gboolean lmf_addr_key_inited = FALSE;
4215
4216 #ifdef MONO_SPARC_THR_TLS
4217 thread_key_t lmf_addr_key;
4218 #else
4219 pthread_key_t lmf_addr_key;
4220 #endif
4221
4222 gpointer
4223 mono_arch_get_lmf_addr (void)
4224 {
4225         /* This is perf critical so we bypass the IO layer */
4226         /* The thr_... functions seem to be somewhat faster */
4227 #ifdef MONO_SPARC_THR_TLS
4228         gpointer res;
4229         thr_getspecific (lmf_addr_key, &res);
4230         return res;
4231 #else
4232         return pthread_getspecific (lmf_addr_key);
4233 #endif
4234 }
4235
4236 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
4237
4238 /*
4239  * There seems to be no way to determine stack boundaries under solaris,
4240  * so it's not possible to determine whenever a SIGSEGV is caused by stack
4241  * overflow or not.
4242  */
4243 #error "--with-sigaltstack=yes not supported on solaris"
4244
4245 #endif
4246
4247 void
4248 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
4249 {
4250         if (!lmf_addr_key_inited) {
4251                 int res;
4252
4253                 lmf_addr_key_inited = TRUE;
4254
4255 #ifdef MONO_SPARC_THR_TLS
4256                 res = thr_keycreate (&lmf_addr_key, NULL);
4257 #else
4258                 res = pthread_key_create (&lmf_addr_key, NULL);
4259 #endif
4260                 g_assert (res == 0);
4261
4262         }
4263
4264 #ifdef MONO_SPARC_THR_TLS
4265         thr_setspecific (lmf_addr_key, &tls->lmf);
4266 #else
4267         pthread_setspecific (lmf_addr_key, &tls->lmf);
4268 #endif
4269 }
4270
4271 void
4272 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4273 {
4274 }
4275
4276 void
4277 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *call, int this_reg, int this_type, int vt_reg)
4278 {
4279         int this_out_reg = sparc_o0;
4280
4281         if (vt_reg != -1) {
4282 #ifdef SPARCV9
4283                 MonoInst *ins;
4284                 MONO_INST_NEW (cfg, ins, OP_SETREG);
4285                 ins->sreg1 = vt_reg;
4286                 ins->dreg = mono_regstate_next_int (cfg->rs);
4287                 mono_bblock_add_inst (cfg->cbb, ins);
4288
4289                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, sparc_o0, FALSE);
4290
4291                 this_out_reg = sparc_o1;
4292 #else
4293                 /* Set the 'struct/union return pointer' location on the stack */
4294                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, sparc_sp, 64, vt_reg);
4295 #endif
4296         }
4297
4298         /* add the this argument */
4299         if (this_reg != -1) {
4300                 MonoInst *this;
4301                 MONO_INST_NEW (cfg, this, OP_SETREG);
4302                 this->type = this_type;
4303                 this->sreg1 = this_reg;
4304                 this->dreg = mono_regstate_next_int (cfg->rs);
4305                 mono_bblock_add_inst (cfg->cbb, this);
4306
4307                 mono_call_inst_add_outarg_reg (cfg, call, this->dreg, this_out_reg, FALSE);
4308         }
4309 }
4310
4311
4312 MonoInst*
4313 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4314 {
4315         MonoInst *ins = NULL;
4316
4317         if (cmethod->klass == mono_defaults.thread_class &&
4318                 strcmp (cmethod->name, "MemoryBarrier") == 0) {
4319                 if (sparcv9)
4320                         MONO_INST_NEW (cfg, ins, OP_MEMORY_BARRIER);
4321         }
4322
4323         return ins;
4324 }
4325
4326 /*
4327  * mono_arch_get_argument_info:
4328  * @csig:  a method signature
4329  * @param_count: the number of parameters to consider
4330  * @arg_info: an array to store the result infos
4331  *
4332  * Gathers information on parameters such as size, alignment and
4333  * padding. arg_info should be large enought to hold param_count + 1 entries.
4334  *
4335  * Returns the size of the activation frame.
4336  */
4337 int
4338 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
4339 {
4340         int k, align;
4341         CallInfo *cinfo;
4342         ArgInfo *ainfo;
4343
4344         cinfo = get_call_info (csig, FALSE);
4345
4346         if (csig->hasthis) {
4347                 ainfo = &cinfo->args [0];
4348                 arg_info [0].offset = ARGS_OFFSET - MONO_SPARC_STACK_BIAS + ainfo->offset;
4349         }
4350
4351         for (k = 0; k < param_count; k++) {
4352                 ainfo = &cinfo->args [k + csig->hasthis];
4353
4354                 arg_info [k + 1].offset = ARGS_OFFSET - MONO_SPARC_STACK_BIAS + ainfo->offset;
4355                 arg_info [k + 1].size = mono_type_size (csig->params [k], &align);
4356         }
4357
4358         g_free (cinfo);
4359
4360         return 0;
4361 }
4362
4363 gboolean
4364 mono_arch_print_tree (MonoInst *tree, int arity)
4365 {
4366         return 0;
4367 }
4368
4369 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
4370 {
4371         return NULL;
4372 }
4373
4374 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
4375 {
4376         return NULL;
4377 }