mono/mini/mini-sparc.c

   1 /*
   2  * mini-sparc.c: Sparc backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Paolo Molaro (lupus@ximian.com)
   6  *   Dietmar Maurer (dietmar@ximian.com)
   7  *
   8  * Modified for SPARC:
   9  *   Christopher Taylor (ct@gentoo.org)
  10  *   Mark Crichton (crichton@gimp.org)
  11  *   Zoltan Varga (vargaz@freemail.hu)
  12  *
  13  * (C) 2003 Ximian, Inc.
  14  */
  15 #include "mini.h"
  16 #include <string.h>
  17 #include <pthread.h>
  18 #include <unistd.h>
  19
  20 #ifndef __linux__
  21 #include <sys/systeminfo.h>
  22 #include <thread.h>
  23 #endif
  24
  25 #include <unistd.h>
  26 #include <sys/mman.h>
  27
  28 #include <mono/metadata/appdomain.h>
  29 #include <mono/metadata/debug-helpers.h>
  30 #include <mono/metadata/tokentype.h>
  31 #include <mono/utils/mono-math.h>
  32
  33 #include "mini-sparc.h"
  34 #include "inssel.h"
  35 #include "trace.h"
  36 #include "cpu-sparc.h"
  37
  38 /*
  39  * Sparc V9 means two things:
  40  * - the instruction set
  41  * - the ABI
  42  *
  43  * V9 instructions are only usable if the underlying processor is 64 bit. Most Sparc
  44  * processors in use are 64 bit processors. The V9 ABI is only usable if the
  45  * mono executable is a 64 bit executable. So it would make sense to use the 64 bit
  46  * instructions without using the 64 bit ABI.
  47  */
  48
  49 /*
  50  * Register usage:
  51  * - %i0..%i<n> hold the incoming arguments, these are never written by JITted
  52  * code. Unused input registers are used for global register allocation.
  53  * - %o0..%o5 and %l7 is used for local register allocation and passing arguments
  54  * - %l0..%l6 is used for global register allocation
  55  * - %o7 and %g1 is used as scratch registers in opcodes
  56  * - all floating point registers are used for local register allocation except %f0.
  57  *   Only double precision registers are used.
  58  * In 64 bit mode:
  59  * - fp registers %d0..%d30 are used for parameter passing, and %d32..%d62 are
  60  *   used for local allocation.
  61  */
  62
  63 /*
  64  * Alignment:
  65  * - doubles and longs must be stored in dword aligned locations
  66  */
  67
  68 /*
  69  * The following things are not implemented or do not work:
  70  *  - some fp arithmetic corner cases
  71  * The following tests in mono/mini are expected to fail:
  72  *  - test_0_simple_double_casts
  73  *      This test casts (guint64)-1 to double and then back to guint64 again.
  74  *    Under x86, it returns 0, while under sparc it returns -1.
  75  *
  76  * In addition to this, the runtime requires the trunc function, or its
  77  * solaris counterpart, aintl, to do some double->int conversions. If this
  78  * function is not available, it is emulated somewhat, but the results can be
  79  * strange.
  80  */
  81
  82 /*
  83  * SPARCV9 FIXME:
  84  * - optimize sparc_set according to the memory model
  85  * - when non-AOT compiling, compute patch targets immediately so we don't
  86  *   have to emit the 6 byte template.
  87  * - varags
  88  * - struct arguments/returns
  89  */
  90
  91 /*
  92  * SPARCV9 ISSUES:
  93  * - sparc_call_simple can't be used in a lot of places since the displacement
  94  *   might not fit into an imm30.
  95  * - g1 can't be used in a lot of places since it is used as a scratch reg in
  96  *   sparc_set.
  97  * - sparc_f0 can't be used as a scratch register on V9
  98  * - the %d34..%d62 fp registers are encoded as: %dx = %f(x - 32 + 1), ie.
  99  *   %d36 = %f5.
 100  * - ldind.i4/u4 needs to sign extend/clear out upper word -> slows things down
 101  * - ins->dreg can't be used as a scatch register in r4 opcodes since it might
 102  *   be a double precision register which has no single precision part.
 103  * - passing/returning structs is hard to implement, because:
 104  *   - the spec is very hard to understand
 105  *   - it requires knowledge about the fields of structure, needs to handle
 106  *     nested structures etc.
 107  */
 108
 109 /*
 110  * Possible optimizations:
 111  * - delay slot scheduling
 112  * - allocate large constants to registers
 113  * - add more mul/div/rem optimizations
 114  */
 115
 116 #ifndef __linux__
 117 #define MONO_SPARC_THR_TLS 1
 118 #endif
 119
 120 /*
 121  * There was a 64 bit bug in glib-2.2: g_bit_nth_msf (0, -1) would return 32,
 122  * causing infinite loops in dominator computation. So glib-2.4 is required.
 123  */
 124 #ifdef SPARCV9
 125 #if GLIB_MAJOR_VERSION == 2 && GLIB_MINOR_VERSION < 4
 126 #error "glib 2.4 or later is required for 64 bit mode."
 127 #endif
 128 #endif
 129
 130 #define NOT_IMPLEMENTED do { g_assert_not_reached (); } while (0)
 131
 132 #define ALIGN_TO(val,align) (((val) + ((align) - 1)) & ~((align) - 1))
 133
 134 #define SIGNAL_STACK_SIZE (64 * 1024)
 135
 136 #define STACK_BIAS MONO_SPARC_STACK_BIAS
 137
 138 #ifdef SPARCV9
 139
 140 /* %g1 is used by sparc_set */
 141 #define GP_SCRATCH_REG sparc_g4
 142 /* %f0 is used for parameter passing */
 143 #define FP_SCRATCH_REG sparc_f30
 144 #define ARGS_OFFSET (STACK_BIAS + 128)
 145
 146 #else
 147
 148 #define FP_SCRATCH_REG sparc_f0
 149 #define ARGS_OFFSET 68
 150 #define GP_SCRATCH_REG sparc_g1
 151
 152 #endif
 153
 154 /* Whenever the CPU supports v9 instructions */
 155 static gboolean sparcv9 = FALSE;
 156
 157 /* Whenever this is a 64bit executable */
 158 #if SPARCV9
 159 static gboolean v64 = TRUE;
 160 #else
 161 static gboolean v64 = FALSE;
 162 #endif
 163
 164 static gpointer mono_arch_get_lmf_addr (void);
 165
 166 static int
 167 mono_spillvar_offset_float (MonoCompile *cfg, int spillvar);
 168
 169 const char*
 170 mono_arch_regname (int reg) {
 171         static const char * rnames[] = {
 172                 "sparc_g0", "sparc_g1", "sparc_g2", "sparc_g3", "sparc_g4",
 173                 "sparc_g5", "sparc_g6", "sparc_g7", "sparc_o0", "sparc_o1",
 174                 "sparc_o2", "sparc_o3", "sparc_o4", "sparc_o5", "sparc_sp",
 175                 "sparc_call", "sparc_l0", "sparc_l1", "sparc_l2", "sparc_l3",
 176                 "sparc_l4", "sparc_l5", "sparc_l6", "sparc_l7", "sparc_i0",
 177                 "sparc_i1", "sparc_i2", "sparc_i3", "sparc_i4", "sparc_i5",
 178                 "sparc_fp", "sparc_retadr"
 179         };
 180         if (reg >= 0 && reg < 32)
 181                 return rnames [reg];
 182         return "unknown";
 183 }
 184
 185 const char*
 186 mono_arch_fregname (int reg) {
 187         static const char *rnames [] = {
 188                 "sparc_f0", "sparc_f1", "sparc_f2", "sparc_f3", "sparc_f4",
 189                 "sparc_f5", "sparc_f6", "sparc_f7", "sparc_f8", "sparc_f9",
 190                 "sparc_f10", "sparc_f11", "sparc_f12", "sparc_f13", "sparc_f14",
 191                 "sparc_f15", "sparc_f16", "sparc_f17", "sparc_f18", "sparc_f19",
 192                 "sparc_f20", "sparc_f21", "sparc_f22", "sparc_f23", "sparc_f24",
 193                 "sparc_f25", "sparc_f26", "sparc_f27", "sparc_f28", "sparc_f29",
 194                 "sparc_f30", "sparc_f31"
 195         };
 196
 197         if (reg >= 0 && reg < 32)
 198                 return rnames [reg];
 199         else
 200                 return "unknown";
 201 }
 202
 203 /*
 204  * Initialize the cpu to execute managed code.
 205  */
 206 void
 207 mono_arch_cpu_init (void)
 208 {
 209         guint32 dummy;
 210         /* make sure sparcv9 is initialized for embedded use */
 211         mono_arch_cpu_optimizazions(&dummy);
 212 }
 213
 214 /*
 215  * This function returns the optimizations supported on this cpu.
 216  */
 217 guint32
 218 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 219 {
 220         char buf [1024];
 221         guint32 opts = 0;
 222
 223         *exclude_mask = 0;
 224
 225 #ifndef __linux__
 226         if (!sysinfo (SI_ISALIST, buf, 1024))
 227                 g_assert_not_reached ();
 228 #else
 229         /* From glibc.  If the getpagesize is 8192, we're on sparc64, which
 230          * (in)directly implies that we're a v9 or better.
 231          * Improvements to this are greatly accepted...
 232          * Also, we don't differentiate between v7 and v8.  I sense SIGILL
 233          * sniffing in my future.
 234          */
 235         if (getpagesize() == 8192)
 236                 strcpy (buf, "sparcv9");
 237         else
 238                 strcpy (buf, "sparcv8");
 239 #endif
 240
 241         /*
 242          * On some processors, the cmov instructions are even slower than the
 243          * normal ones...
 244          */
 245         if (strstr (buf, "sparcv9")) {
 246                 opts |= MONO_OPT_CMOV | MONO_OPT_FCMOV;
 247                 sparcv9 = TRUE;
 248         }
 249         else
 250                 *exclude_mask |= MONO_OPT_CMOV | MONO_OPT_FCMOV;
 251
 252         return opts;
 253 }
 254
 255 static void
 256 mono_arch_break (void)
 257 {
 258 }
 259
 260 #ifdef __GNUC__
 261 #define flushi(addr)    __asm__ __volatile__ ("iflush %0"::"r"(addr):"memory")
 262 #else /* assume Sun's compiler */
 263 static void flushi(void *addr)
 264 {
 265     asm("flush %i0");
 266 }
 267 #endif
 268
 269 #ifndef __linux__
 270 void sync_instruction_memory(caddr_t addr, int len);
 271 #endif
 272
 273 void
 274 mono_arch_flush_icache (guint8 *code, gint size)
 275 {
 276 #ifndef __linux__
 277         /* Hopefully this is optimized based on the actual CPU */
 278         sync_instruction_memory (code, size);
 279 #else
 280         guint64 *p = (guint64*)code;
 281         guint64 *end = (guint64*)(code + ((size + 8) /8));
 282
 283         /*
 284          * FIXME: Flushing code in dword chunks in _slow_.
 285          */
 286         while (p < end)
 287 #ifdef __GNUC__
 288                 __asm__ __volatile__ ("iflush %0"::"r"(p++));
 289 #else
 290                         flushi (p ++);
 291 #endif
 292 #endif
 293 }
 294
 295 /*
 296  * mono_sparc_flushw:
 297  *
 298  * Flush all register windows to memory. Every register window is saved to
 299  * a 16 word area on the stack pointed to by its %sp register.
 300  */
 301 void
 302 mono_sparc_flushw (void)
 303 {
 304         static guint32 start [64];
 305         static int inited = 0;
 306         guint32 *code;
 307         static void (*flushw) (void);
 308
 309         if (!inited) {
 310                 code = start;
 311
 312                 sparc_save_imm (code, sparc_sp, -160, sparc_sp);
 313                 sparc_flushw (code);
 314                 sparc_ret (code);
 315                 sparc_restore_simple (code);
 316
 317                 g_assert ((code - start) < 64);
 318
 319                 flushw = (gpointer)start;
 320
 321                 inited = 1;
 322         }
 323
 324         flushw ();
 325 }
 326
 327 void
 328 mono_arch_flush_register_windows (void)
 329 {
 330         mono_sparc_flushw ();
 331 }
 332
 333 gboolean
 334 mono_arch_is_inst_imm (gint64 imm)
 335 {
 336         return sparc_is_imm13 (imm);
 337 }
 338
 339 gboolean
 340 mono_sparc_is_v9 (void) {
 341         return sparcv9;
 342 }
 343
 344 gboolean
 345 mono_sparc_is_sparc64 (void) {
 346         return v64;
 347 }
 348
 349 typedef enum {
 350         ArgInIReg,
 351         ArgInIRegPair,
 352         ArgInSplitRegStack,
 353         ArgInFReg,
 354         ArgInFRegPair,
 355         ArgOnStack,
 356         ArgOnStackPair,
 357         ArgInFloatReg,  /* V9 only */
 358         ArgInDoubleReg  /* V9 only */
 359 } ArgStorage;
 360
 361 typedef struct {
 362         gint16 offset;
 363         /* This needs to be offset by %i0 or %o0 depending on caller/callee */
 364         gint8  reg;
 365         ArgStorage storage;
 366         guint32 vt_offset; /* for valuetypes */
 367 } ArgInfo;
 368
 369 typedef struct {
 370         int nargs;
 371         guint32 stack_usage;
 372         guint32 reg_usage;
 373         ArgInfo ret;
 374         ArgInfo sig_cookie;
 375         ArgInfo args [1];
 376 } CallInfo;
 377
 378 #define DEBUG(a)
 379
 380 /* %o0..%o5 */
 381 #define PARAM_REGS 6
 382
 383 static void inline
 384 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean pair)
 385 {
 386         ainfo->offset = *stack_size;
 387
 388         if (!pair) {
 389                 if (*gr >= PARAM_REGS) {
 390                         ainfo->storage = ArgOnStack;
 391                 }
 392                 else {
 393                         ainfo->storage = ArgInIReg;
 394                         ainfo->reg = *gr;
 395                         (*gr) ++;
 396                 }
 397
 398                 /* Allways reserve stack space for parameters passed in registers */
 399                 (*stack_size) += sizeof (gpointer);
 400         }
 401         else {
 402                 if (*gr < PARAM_REGS - 1) {
 403                         /* A pair of registers */
 404                         ainfo->storage = ArgInIRegPair;
 405                         ainfo->reg = *gr;
 406                         (*gr) += 2;
 407                 }
 408                 else if (*gr >= PARAM_REGS) {
 409                         /* A pair of stack locations */
 410                         ainfo->storage = ArgOnStackPair;
 411                 }
 412                 else {
 413                         ainfo->storage = ArgInSplitRegStack;
 414                         ainfo->reg = *gr;
 415                         (*gr) ++;
 416                 }
 417
 418                 (*stack_size) += 2 * sizeof (gpointer);
 419         }
 420 }
 421
 422 #ifdef SPARCV9
 423
 424 #define FLOAT_PARAM_REGS 32
 425
 426 static void inline
 427 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean single)
 428 {
 429         ainfo->offset = *stack_size;
 430
 431         if (single) {
 432                 if (*gr >= FLOAT_PARAM_REGS) {
 433                         ainfo->storage = ArgOnStack;
 434                 }
 435                 else {
 436                         /* A single is passed in an even numbered fp register */
 437                         ainfo->storage = ArgInFloatReg;
 438                         ainfo->reg = *gr + 1;
 439                         (*gr) += 2;
 440                 }
 441         }
 442         else {
 443                 if (*gr < FLOAT_PARAM_REGS) {
 444                         /* A double register */
 445                         ainfo->storage = ArgInDoubleReg;
 446                         ainfo->reg = *gr;
 447                         (*gr) += 2;
 448                 }
 449                 else {
 450                         ainfo->storage = ArgOnStack;
 451                 }
 452         }
 453
 454         (*stack_size) += sizeof (gpointer);
 455 }
 456
 457 #endif
 458
 459 /*
 460  * get_call_info:
 461  *
 462  *  Obtain information about a call according to the calling convention.
 463  * For V8, see the "System V ABI, Sparc Processor Supplement" Sparc V8 version
 464  * document for more information.
 465  * For V9, see the "Low Level System Information (64-bit psABI)" chapter in
 466  * the 'Sparc Compliance Definition 2.4' document.
 467  */
 468 static CallInfo*
 469 get_call_info (MonoMethodSignature *sig, gboolean is_pinvoke)
 470 {
 471         guint32 i, gr, fr;
 472         int n = sig->hasthis + sig->param_count;
 473         guint32 stack_size = 0;
 474         CallInfo *cinfo;
 475
 476         cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 477
 478         gr = 0;
 479         fr = 0;
 480
 481 #ifdef SPARCV9
 482         if (MONO_TYPE_ISSTRUCT ((sig->ret))) {
 483                 /* The address of the return value is passed in %o0 */
 484                 add_general (&gr, &stack_size, &cinfo->ret, FALSE);
 485                 cinfo->ret.reg += sparc_i0;
 486         }
 487 #endif
 488
 489         /* this */
 490         if (sig->hasthis)
 491                 add_general (&gr, &stack_size, cinfo->args + 0, FALSE);
 492
 493         if ((sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 494                 gr = PARAM_REGS;
 495
 496                 /* Emit the signature cookie just before the implicit arguments */
 497                 add_general (&gr, &stack_size, &cinfo->sig_cookie, FALSE);
 498         }
 499
 500         for (i = 0; i < sig->param_count; ++i) {
 501                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 502
 503                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 504                         gr = PARAM_REGS;
 505
 506                         /* Emit the signature cookie just before the implicit arguments */
 507                         add_general (&gr, &stack_size, &cinfo->sig_cookie, FALSE);
 508                 }
 509
 510                 DEBUG(printf("param %d: ", i));
 511                 if (sig->params [i]->byref) {
 512                         DEBUG(printf("byref\n"));
 513
 514                         add_general (&gr, &stack_size, ainfo, FALSE);
 515                         continue;
 516                 }
 517                 switch (mono_type_get_underlying_type (sig->params [i])->type) {
 518                 case MONO_TYPE_BOOLEAN:
 519                 case MONO_TYPE_I1:
 520                 case MONO_TYPE_U1:
 521                         add_general (&gr, &stack_size, ainfo, FALSE);
 522                         /* the value is in the ls byte */
 523                         ainfo->offset += sizeof (gpointer) - 1;
 524                         break;
 525                 case MONO_TYPE_I2:
 526                 case MONO_TYPE_U2:
 527                 case MONO_TYPE_CHAR:
 528                         add_general (&gr, &stack_size, ainfo, FALSE);
 529                         /* the value is in the ls word */
 530                         ainfo->offset += sizeof (gpointer) - 2;
 531                         break;
 532                 case MONO_TYPE_I4:
 533                 case MONO_TYPE_U4:
 534                         add_general (&gr, &stack_size, ainfo, FALSE);
 535                         /* the value is in the ls dword */
 536                         ainfo->offset += sizeof (gpointer) - 4;
 537                         break;
 538                 case MONO_TYPE_I:
 539                 case MONO_TYPE_U:
 540                 case MONO_TYPE_PTR:
 541                 case MONO_TYPE_FNPTR:
 542                 case MONO_TYPE_CLASS:
 543                 case MONO_TYPE_OBJECT:
 544                 case MONO_TYPE_STRING:
 545                 case MONO_TYPE_SZARRAY:
 546                 case MONO_TYPE_ARRAY:
 547                         add_general (&gr, &stack_size, ainfo, FALSE);
 548                         break;
 549                 case MONO_TYPE_GENERICINST:
 550                         if (!mono_type_generic_inst_is_valuetype (sig->params [i])) {
 551                                 add_general (&gr, &stack_size, ainfo, FALSE);
 552                                 break;
 553                         }
 554                         /* Fall through */
 555                 case MONO_TYPE_VALUETYPE:
 556 #ifdef SPARCV9
 557                         if (sig->pinvoke)
 558                                 NOT_IMPLEMENTED;
 559 #endif
 560                         add_general (&gr, &stack_size, ainfo, FALSE);
 561                         break;
 562                 case MONO_TYPE_TYPEDBYREF:
 563                         add_general (&gr, &stack_size, ainfo, FALSE);
 564                         break;
 565                 case MONO_TYPE_U8:
 566                 case MONO_TYPE_I8:
 567 #ifdef SPARCV9
 568                         add_general (&gr, &stack_size, ainfo, FALSE);
 569 #else
 570                         add_general (&gr, &stack_size, ainfo, TRUE);
 571 #endif
 572                         break;
 573                 case MONO_TYPE_R4:
 574 #ifdef SPARCV9
 575                         add_float (&fr, &stack_size, ainfo, TRUE);
 576                         gr ++;
 577 #else
 578                         /* single precision values are passed in integer registers */
 579                         add_general (&gr, &stack_size, ainfo, FALSE);
 580 #endif
 581                         break;
 582                 case MONO_TYPE_R8:
 583 #ifdef SPARCV9
 584                         add_float (&fr, &stack_size, ainfo, FALSE);
 585                         gr ++;
 586 #else
 587                         /* double precision values are passed in a pair of registers */
 588                         add_general (&gr, &stack_size, ainfo, TRUE);
 589 #endif
 590                         break;
 591                 default:
 592                         g_assert_not_reached ();
 593                 }
 594         }
 595
 596         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 597                 gr = PARAM_REGS;
 598
 599                 /* Emit the signature cookie just before the implicit arguments */
 600                 add_general (&gr, &stack_size, &cinfo->sig_cookie, FALSE);
 601         }
 602
 603         /* return value */
 604         {
 605                 switch (mono_type_get_underlying_type (sig->ret)->type) {
 606                 case MONO_TYPE_BOOLEAN:
 607                 case MONO_TYPE_I1:
 608                 case MONO_TYPE_U1:
 609                 case MONO_TYPE_I2:
 610                 case MONO_TYPE_U2:
 611                 case MONO_TYPE_CHAR:
 612                 case MONO_TYPE_I4:
 613                 case MONO_TYPE_U4:
 614                 case MONO_TYPE_I:
 615                 case MONO_TYPE_U:
 616                 case MONO_TYPE_PTR:
 617                 case MONO_TYPE_FNPTR:
 618                 case MONO_TYPE_CLASS:
 619                 case MONO_TYPE_OBJECT:
 620                 case MONO_TYPE_SZARRAY:
 621                 case MONO_TYPE_ARRAY:
 622                 case MONO_TYPE_STRING:
 623                         cinfo->ret.storage = ArgInIReg;
 624                         cinfo->ret.reg = sparc_i0;
 625                         if (gr < 1)
 626                                 gr = 1;
 627                         break;
 628                 case MONO_TYPE_U8:
 629                 case MONO_TYPE_I8:
 630 #ifdef SPARCV9
 631                         cinfo->ret.storage = ArgInIReg;
 632                         cinfo->ret.reg = sparc_i0;
 633                         if (gr < 1)
 634                                 gr = 1;
 635 #else
 636                         cinfo->ret.storage = ArgInIRegPair;
 637                         cinfo->ret.reg = sparc_i0;
 638                         if (gr < 2)
 639                                 gr = 2;
 640 #endif
 641                         break;
 642                 case MONO_TYPE_R4:
 643                 case MONO_TYPE_R8:
 644                         cinfo->ret.storage = ArgInFReg;
 645                         cinfo->ret.reg = sparc_f0;
 646                         break;
 647                 case MONO_TYPE_GENERICINST:
 648                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 649                                 cinfo->ret.storage = ArgInIReg;
 650                                 cinfo->ret.reg = sparc_i0;
 651                                 if (gr < 1)
 652                                         gr = 1;
 653                                 break;
 654                         }
 655                         /* Fall through */
 656                 case MONO_TYPE_VALUETYPE:
 657                         if (v64) {
 658                                 if (sig->pinvoke)
 659                                         NOT_IMPLEMENTED;
 660                                 else
 661                                         /* Already done */
 662                                         ;
 663                         }
 664                         else
 665                                 cinfo->ret.storage = ArgOnStack;
 666                         break;
 667                 case MONO_TYPE_TYPEDBYREF:
 668                         if (v64) {
 669                                 if (sig->pinvoke)
 670                                         /* Same as a valuetype with size 24 */
 671                                         NOT_IMPLEMENTED;
 672                                 else
 673                                         /* Already done */
 674                                         ;
 675                         }
 676                         else
 677                                 cinfo->ret.storage = ArgOnStack;
 678                         break;
 679                 case MONO_TYPE_VOID:
 680                         break;
 681                 default:
 682                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 683                 }
 684         }
 685
 686         cinfo->stack_usage = stack_size;
 687         cinfo->reg_usage = gr;
 688         return cinfo;
 689 }
 690
 691 static gboolean
 692 is_regsize_var (MonoType *t) {
 693         if (t->byref)
 694                 return TRUE;
 695         switch (mono_type_get_underlying_type (t)->type) {
 696         case MONO_TYPE_BOOLEAN:
 697         case MONO_TYPE_CHAR:
 698         case MONO_TYPE_I1:
 699         case MONO_TYPE_U1:
 700         case MONO_TYPE_I2:
 701         case MONO_TYPE_U2:
 702         case MONO_TYPE_I4:
 703         case MONO_TYPE_U4:
 704         case MONO_TYPE_I:
 705         case MONO_TYPE_U:
 706                 return TRUE;
 707         case MONO_TYPE_OBJECT:
 708         case MONO_TYPE_STRING:
 709         case MONO_TYPE_CLASS:
 710         case MONO_TYPE_SZARRAY:
 711         case MONO_TYPE_ARRAY:
 712                 return TRUE;
 713         case MONO_TYPE_VALUETYPE:
 714                 return FALSE;
 715 #ifdef SPARCV9
 716         case MONO_TYPE_I8:
 717         case MONO_TYPE_U8:
 718                 return TRUE;
 719 #endif
 720         }
 721         return FALSE;
 722 }
 723
 724 GList *
 725 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 726 {
 727         GList *vars = NULL;
 728         int i;
 729
 730         /*
 731          * FIXME: If an argument is allocated to a register, then load it from the
 732          * stack in the prolog.
 733          */
 734
 735         for (i = 0; i < cfg->num_varinfo; i++) {
 736                 MonoInst *ins = cfg->varinfo [i];
 737                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 738
 739                 /* unused vars */
 740                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 741                         continue;
 742
 743                 /* FIXME: Make arguments on stack allocateable to registers */
 744                 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode == OP_REGVAR) || (ins->opcode == OP_ARG))
 745                         continue;
 746
 747                 if (is_regsize_var (ins->inst_vtype)) {
 748                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 749                         g_assert (i == vmv->idx);
 750
 751                         vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
 752                 }
 753         }
 754
 755         return vars;
 756 }
 757
 758 GList *
 759 mono_arch_get_global_int_regs (MonoCompile *cfg)
 760 {
 761         GList *regs = NULL;
 762         int i;
 763         MonoMethodSignature *sig;
 764         CallInfo *cinfo;
 765
 766         sig = mono_method_signature (cfg->method);
 767
 768         cinfo = get_call_info (sig, FALSE);
 769
 770         /* Use unused input registers */
 771         for (i = cinfo->reg_usage; i < 6; ++i)
 772                 regs = g_list_prepend (regs, GUINT_TO_POINTER (sparc_i0 + i));
 773
 774         /* Use %l0..%l6 as global registers */
 775         for (i = sparc_l0; i < sparc_l7; ++i)
 776                 regs = g_list_prepend (regs, GUINT_TO_POINTER (i));
 777
 778         g_free (cinfo);
 779
 780         return regs;
 781 }
 782
 783 /*
 784  * mono_arch_regalloc_cost:
 785  *
 786  *  Return the cost, in number of memory references, of the action of
 787  * allocating the variable VMV into a register during global register
 788  * allocation.
 789  */
 790 guint32
 791 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 792 {
 793         return 0;
 794 }
 795
 796 /*
 797  * Set var information according to the calling convention. sparc version.
 798  * The locals var stuff should most likely be split in another method.
 799  */
 800 void
 801 mono_arch_allocate_vars (MonoCompile *m)
 802 {
 803         MonoMethodSignature *sig;
 804         MonoMethodHeader *header;
 805         MonoInst *inst;
 806         int i, offset, size, align, curinst;
 807         CallInfo *cinfo;
 808
 809         header = mono_method_get_header (m->method);
 810
 811         sig = mono_method_signature (m->method);
 812
 813         cinfo = get_call_info (sig, FALSE);
 814
 815         if (sig->ret->type != MONO_TYPE_VOID) {
 816                 switch (cinfo->ret.storage) {
 817                 case ArgInIReg:
 818                 case ArgInFReg:
 819                 case ArgInIRegPair:
 820                         m->ret->opcode = OP_REGVAR;
 821                         m->ret->inst_c0 = cinfo->ret.reg;
 822                         break;
 823                 case ArgOnStack:
 824 #ifdef SPARCV9
 825                         g_assert_not_reached ();
 826 #else
 827                         /* valuetypes */
 828                         m->ret->opcode = OP_REGOFFSET;
 829                         m->ret->inst_basereg = sparc_fp;
 830                         m->ret->inst_offset = 64;
 831 #endif
 832                         break;
 833                 default:
 834                         NOT_IMPLEMENTED;
 835                 }
 836                 m->ret->dreg = m->ret->inst_c0;
 837         }
 838
 839         /*
 840          * We use the ABI calling conventions for managed code as well.
 841          * Exception: valuetypes are never returned in registers on V9.
 842          * FIXME: Use something more optimized.
 843          */
 844
 845         /* Locals are allocated backwards from %fp */
 846         m->frame_reg = sparc_fp;
 847         offset = 0;
 848
 849         /*
 850          * Reserve a stack slot for holding information used during exception
 851          * handling.
 852          */
 853         if (header->num_clauses)
 854                 offset += sizeof (gpointer) * 2;
 855
 856         if (m->method->save_lmf) {
 857                 offset += sizeof (MonoLMF);
 858                 m->arch.lmf_offset = offset;
 859         }
 860
 861         curinst = m->locals_start;
 862         for (i = curinst; i < m->num_varinfo; ++i) {
 863                 inst = m->varinfo [i];
 864
 865                 if (inst->opcode == OP_REGVAR) {
 866                         //g_print ("allocating local %d to %s\n", i, mono_arch_regname (inst->dreg));
 867                         continue;
 868                 }
 869
 870                 if (inst->flags & MONO_INST_IS_DEAD)
 871                         continue;
 872
 873                 /* inst->unused indicates native sized value types, this is used by the
 874                 * pinvoke wrappers when they call functions returning structure */
 875                 if (inst->unused && MONO_TYPE_ISSTRUCT (inst->inst_vtype) && inst->inst_vtype->type != MONO_TYPE_TYPEDBYREF)
 876                         size = mono_class_native_size (inst->inst_vtype->data.klass, &align);
 877                 else
 878                         size = mono_type_stack_size (inst->inst_vtype, &align);
 879
 880                 /*
 881                  * This is needed since structures containing doubles must be doubleword
 882          * aligned.
 883                  * FIXME: Do this only if needed.
 884                  */
 885                 if (MONO_TYPE_ISSTRUCT (inst->inst_vtype))
 886                         align = 8;
 887
 888                 /*
 889                  * variables are accessed as negative offsets from %fp, so increase
 890                  * the offset before assigning it to a variable
 891                  */
 892                 offset += size;
 893
 894                 offset += align - 1;
 895                 offset &= ~(align - 1);
 896                 inst->opcode = OP_REGOFFSET;
 897                 inst->inst_basereg = sparc_fp;
 898                 inst->inst_offset = STACK_BIAS + -offset;
 899
 900                 //g_print ("allocating local %d to [%s - %d]\n", i, mono_arch_regname (inst->inst_basereg), - inst->inst_offset);
 901         }
 902
 903         if (sig->call_convention == MONO_CALL_VARARG) {
 904                 m->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
 905         }
 906
 907         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 908                 inst = m->varinfo [i];
 909                 if (inst->opcode != OP_REGVAR) {
 910                         ArgInfo *ainfo = &cinfo->args [i];
 911                         gboolean inreg = TRUE;
 912                         MonoType *arg_type;
 913                         ArgStorage storage;
 914
 915                         if (sig->hasthis && (i == 0))
 916                                 arg_type = &mono_defaults.object_class->byval_arg;
 917                         else
 918                                 arg_type = sig->params [i - sig->hasthis];
 919
 920 #ifndef SPARCV9
 921                         if (!arg_type->byref && ((arg_type->type == MONO_TYPE_R4)
 922                                                                          || (arg_type->type == MONO_TYPE_R8)))
 923                                 /*
 924                                  * Since float arguments are passed in integer registers, we need to
 925                                  * save them to the stack in the prolog.
 926                                  */
 927                                 inreg = FALSE;
 928 #endif
 929
 930                         /* FIXME: Allocate volatile arguments to registers */
 931                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 932                                 inreg = FALSE;
 933
 934                         if (MONO_TYPE_ISSTRUCT (arg_type))
 935                                 /* FIXME: this isn't needed */
 936                                 inreg = FALSE;
 937
 938                         inst->opcode = OP_REGOFFSET;
 939
 940                         if (!inreg)
 941                                 storage = ArgOnStack;
 942                         else
 943                                 storage = ainfo->storage;
 944
 945                         switch (storage) {
 946                         case ArgInIReg:
 947                         case ArgInIRegPair:
 948                                 inst->opcode = OP_REGVAR;
 949                                 inst->dreg = sparc_i0 + ainfo->reg;
 950                                 break;
 951                         case ArgInFloatReg:
 952                         case ArgInDoubleReg:
 953                                 /*
 954                                  * Since float regs are volatile, we save the arguments to
 955                                  * the stack in the prolog.
 956                                  * FIXME: Avoid this if the method contains no calls.
 957                                  */
 958                         case ArgOnStack:
 959                         case ArgOnStackPair:
 960                         case ArgInSplitRegStack:
 961                                 /* Split arguments are saved to the stack in the prolog */
 962                                 inst->opcode = OP_REGOFFSET;
 963                                 /* in parent frame */
 964                                 inst->inst_basereg = sparc_fp;
 965                                 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
 966
 967                                 if (!arg_type->byref && (arg_type->type == MONO_TYPE_R8)) {
 968                                         /*
 969                                          * It is very hard to load doubles from non-doubleword aligned
 970                                          * memory locations. So if the offset is misaligned, we copy the
 971                                          * argument to a stack location in the prolog.
 972                                          */
 973                                         if ((inst->inst_offset - STACK_BIAS) % 8) {
 974                                                 inst->inst_basereg = sparc_fp;
 975                                                 offset += 8;
 976                                                 align = 8;
 977                                                 offset += align - 1;
 978                                                 offset &= ~(align - 1);
 979                                                 inst->inst_offset = STACK_BIAS + -offset;
 980
 981                                         }
 982                                 }
 983                                 break;
 984                         default:
 985                                 NOT_IMPLEMENTED;
 986                         }
 987
 988                         if (MONO_TYPE_ISSTRUCT (arg_type)) {
 989                                 /* Add a level of indirection */
 990                                 /*
 991                                  * It would be easier to add OP_LDIND_I here, but ldind_i instructions
 992                                  * are destructively modified in a lot of places in inssel.brg.
 993                                  */
 994                                 MonoInst *indir;
 995                                 MONO_INST_NEW (m, indir, 0);
 996                                 *indir = *inst;
 997                                 inst->opcode = OP_SPARC_INARG_VT;
 998                                 inst->inst_left = indir;
 999                         }
1000                 }
1001         }
1002
1003         /*
1004          * spillvars are stored between the normal locals and the storage reserved
1005          * by the ABI.
1006          */
1007
1008         m->stack_offset = offset;
1009
1010         /* Add a properly aligned dword for use by int<->float conversion opcodes */
1011         m->spill_count ++;
1012         mono_spillvar_offset_float (m, 0);
1013
1014         g_free (cinfo);
1015 }
1016
1017 static MonoInst *
1018 make_group (MonoCompile *cfg, MonoInst *left, int basereg, int offset)
1019 {
1020         MonoInst *group;
1021
1022         MONO_INST_NEW (cfg, group, OP_GROUP);
1023         group->inst_left = left;
1024         group->inst_basereg = basereg;
1025         group->inst_imm = offset;
1026
1027         return group;
1028 }
1029
1030 /*
1031  * take the arguments and generate the arch-specific
1032  * instructions to properly call the function in call.
1033  * This includes pushing, moving arguments to the right register
1034  * etc.
1035  */
1036 MonoCallInst*
1037 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1038         MonoInst *arg, *in;
1039         MonoMethodSignature *sig;
1040         int i, n;
1041         CallInfo *cinfo;
1042         ArgInfo *ainfo;
1043         guint32 extra_space = 0;
1044
1045         sig = call->signature;
1046         n = sig->param_count + sig->hasthis;
1047
1048         cinfo = get_call_info (sig, sig->pinvoke);
1049
1050         for (i = 0; i < n; ++i) {
1051                 ainfo = cinfo->args + i;
1052
1053                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1054                         /* Emit the signature cookie just before the first implicit argument */
1055                         MonoInst *sig_arg;
1056                         MonoMethodSignature *tmp_sig;
1057
1058                         /*
1059                          * mono_ArgIterator_Setup assumes the signature cookie is
1060                          * passed first and all the arguments which were before it are
1061                          * passed on the stack after the signature. So compensate by
1062                          * passing a different signature.
1063                          */
1064                         tmp_sig = mono_metadata_signature_dup (call->signature);
1065                         tmp_sig->param_count -= call->signature->sentinelpos;
1066                         tmp_sig->sentinelpos = 0;
1067                         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1068
1069                         /* FIXME: Add support for signature tokens to AOT */
1070                         cfg->disable_aot = TRUE;
1071                         /* We allways pass the signature on the stack for simplicity */
1072                         MONO_INST_NEW (cfg, arg, OP_SPARC_OUTARG_MEM);
1073                         arg->inst_right = make_group (cfg, (MonoInst*)call, sparc_sp, ARGS_OFFSET + cinfo->sig_cookie.offset);
1074                         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1075                         sig_arg->inst_p0 = tmp_sig;
1076                         arg->inst_left = sig_arg;
1077                         arg->type = STACK_PTR;
1078                         /* prepend, so they get reversed */
1079                         arg->next = call->out_args;
1080                         call->out_args = arg;
1081                 }
1082
1083                 if (is_virtual && i == 0) {
1084                         /* the argument will be attached to the call instruction */
1085                         in = call->args [i];
1086                 } else {
1087                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1088                         in = call->args [i];
1089                         arg->cil_code = in->cil_code;
1090                         arg->inst_left = in;
1091                         arg->type = in->type;
1092                         /* prepend, we'll need to reverse them later */
1093                         arg->next = call->out_args;
1094                         call->out_args = arg;
1095
1096                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1097                                 MonoInst *inst;
1098                                 gint align;
1099                                 guint32 offset, pad;
1100                                 guint32 size;
1101
1102 #ifdef SPARCV9
1103                                 if (sig->pinvoke)
1104                                         NOT_IMPLEMENTED;
1105 #endif
1106
1107                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1108                                         size = sizeof (MonoTypedRef);
1109                                         align = sizeof (gpointer);
1110                                 }
1111                                 else
1112                                 if (sig->pinvoke)
1113                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1114                                 else {
1115                                         /*
1116                                          * Can't use mono_type_stack_size (), but that
1117                                          * aligns the size to sizeof (gpointer), which is larger
1118                                          * than the size of the source, leading to reads of invalid
1119                                          * memory if the source is at the end of address space or
1120                                          * misaligned reads.
1121                                          */
1122                                         size = mono_class_value_size (in->klass, &align);
1123                                 }
1124
1125                                 /*
1126                                  * We use OP_OUTARG_VT to copy the valuetype to a stack location, then
1127                                  * use the normal OUTARG opcodes to pass the address of the location to
1128                                  * the callee.
1129                                  */
1130                                 MONO_INST_NEW (cfg, inst, OP_OUTARG_VT);
1131                                 inst->inst_left = in;
1132
1133                                 /* The first 6 argument locations are reserved */
1134                                 if (cinfo->stack_usage < 6 * sizeof (gpointer))
1135                                         cinfo->stack_usage = 6 * sizeof (gpointer);
1136
1137                                 offset = ALIGN_TO ((ARGS_OFFSET - STACK_BIAS) + cinfo->stack_usage, align);
1138                                 pad = offset - ((ARGS_OFFSET - STACK_BIAS) + cinfo->stack_usage);
1139
1140                                 inst->inst_c1 = STACK_BIAS + offset;
1141                                 inst->unused = size;
1142                                 arg->inst_left = inst;
1143
1144                                 cinfo->stack_usage += size;
1145                                 cinfo->stack_usage += pad;
1146                         }
1147
1148                         arg->inst_right = make_group (cfg, (MonoInst*)call, sparc_sp, ARGS_OFFSET + ainfo->offset);
1149
1150                         switch (ainfo->storage) {
1151                         case ArgInIReg:
1152                         case ArgInFReg:
1153                         case ArgInIRegPair:
1154                                 if (ainfo->storage == ArgInIRegPair)
1155                                         arg->opcode = OP_SPARC_OUTARG_REGPAIR;
1156                                 arg->unused = sparc_o0 + ainfo->reg;
1157                                 call->used_iregs |= 1 << ainfo->reg;
1158
1159                                 if ((i >= sig->hasthis) && !sig->params [i - sig->hasthis]->byref && ((sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) || (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4))) {
1160                                         /* An fp value is passed in an ireg */
1161
1162                                         if (arg->opcode == OP_SPARC_OUTARG_REGPAIR)
1163                                                 arg->opcode = OP_SPARC_OUTARG_REGPAIR_FLOAT;
1164                                         else
1165                                                 arg->opcode = OP_SPARC_OUTARG_FLOAT;
1166
1167                                         /*
1168                                          * The OUTARG (freg) implementation needs an extra dword to store
1169                                          * the temporary value.
1170                                          */
1171                                         extra_space += 8;
1172                                 }
1173                                 break;
1174                         case ArgOnStack:
1175                                 arg->opcode = OP_SPARC_OUTARG_MEM;
1176                                 break;
1177                         case ArgOnStackPair:
1178                                 arg->opcode = OP_SPARC_OUTARG_MEMPAIR;
1179                                 break;
1180                         case ArgInSplitRegStack:
1181                                 arg->opcode = OP_SPARC_OUTARG_SPLIT_REG_STACK;
1182                                 arg->unused = sparc_o0 + ainfo->reg;
1183                                 call->used_iregs |= 1 << ainfo->reg;
1184                                 break;
1185                         case ArgInFloatReg:
1186                                 arg->opcode = OP_SPARC_OUTARG_FLOAT_REG;
1187                                 arg->unused = sparc_f0 + ainfo->reg;
1188                                 break;
1189                         case ArgInDoubleReg:
1190                                 arg->opcode = OP_SPARC_OUTARG_DOUBLE_REG;
1191                                 arg->unused = sparc_f0 + ainfo->reg;
1192                                 break;
1193                         default:
1194                                 NOT_IMPLEMENTED;
1195                         }
1196                 }
1197         }
1198
1199         /*
1200          * Reverse the call->out_args list.
1201          */
1202         {
1203                 MonoInst *prev = NULL, *list = call->out_args, *next;
1204                 while (list) {
1205                         next = list->next;
1206                         list->next = prev;
1207                         prev = list;
1208                         list = next;
1209                 }
1210                 call->out_args = prev;
1211         }
1212         call->stack_usage = cinfo->stack_usage + extra_space;
1213         call->out_ireg_args = NULL;
1214         call->out_freg_args = NULL;
1215         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1216         cfg->flags |= MONO_CFG_HAS_CALLS;
1217
1218         g_free (cinfo);
1219         return call;
1220 }
1221
1222 /* Map opcode to the sparc condition codes */
1223 static inline SparcCond
1224 opcode_to_sparc_cond (int opcode)
1225 {
1226         switch (opcode) {
1227         case OP_FBGE:
1228                 return sparc_fbge;
1229         case OP_FBLE:
1230                 return sparc_fble;
1231         case OP_FBEQ:
1232         case OP_FCEQ:
1233                 return sparc_fbe;
1234         case OP_FBLT:
1235         case OP_FCLT:
1236         case OP_FCLT_UN:
1237                 return sparc_fbl;
1238         case OP_FBGT:
1239         case OP_FCGT:
1240         case OP_FCGT_UN:
1241                 return sparc_fbg;
1242         case CEE_BEQ:
1243         case OP_IBEQ:
1244         case OP_CEQ:
1245         case OP_ICEQ:
1246         case OP_COND_EXC_EQ:
1247                 return sparc_be;
1248         case CEE_BNE_UN:
1249         case OP_COND_EXC_NE_UN:
1250         case OP_IBNE_UN:
1251                 return sparc_bne;
1252         case CEE_BLT:
1253         case OP_IBLT:
1254         case OP_CLT:
1255         case OP_ICLT:
1256         case OP_COND_EXC_LT:
1257                 return sparc_bl;
1258         case CEE_BLT_UN:
1259         case OP_IBLT_UN:
1260         case OP_CLT_UN:
1261         case OP_ICLT_UN:
1262         case OP_COND_EXC_LT_UN:
1263                 return sparc_blu;
1264         case CEE_BGT:
1265         case OP_IBGT:
1266         case OP_CGT:
1267         case OP_ICGT:
1268         case OP_COND_EXC_GT:
1269                 return sparc_bg;
1270         case CEE_BGT_UN:
1271         case OP_IBGT_UN:
1272         case OP_CGT_UN:
1273         case OP_ICGT_UN:
1274         case OP_COND_EXC_GT_UN:
1275                 return sparc_bgu;
1276         case CEE_BGE:
1277         case OP_IBGE:
1278         case OP_COND_EXC_GE:
1279                 return sparc_bge;
1280         case CEE_BGE_UN:
1281         case OP_IBGE_UN:
1282         case OP_COND_EXC_GE_UN:
1283                 return sparc_beu;
1284         case CEE_BLE:
1285         case OP_IBLE:
1286         case OP_COND_EXC_LE:
1287                 return sparc_ble;
1288         case CEE_BLE_UN:
1289         case OP_IBLE_UN:
1290         case OP_COND_EXC_LE_UN:
1291                 return sparc_bleu;
1292         case OP_COND_EXC_OV:
1293         case OP_COND_EXC_IOV:
1294                 return sparc_bvs;
1295         case OP_COND_EXC_C:
1296         case OP_COND_EXC_IC:
1297                 return sparc_bcs;
1298         case OP_COND_EXC_NO:
1299         case OP_COND_EXC_NC:
1300                 NOT_IMPLEMENTED;
1301         default:
1302                 g_assert_not_reached ();
1303                 return sparc_be;
1304         }
1305 }
1306
1307 #define COMPUTE_DISP(ins) \
1308 if (ins->flags & MONO_INST_BRLABEL) { \
1309         if (ins->inst_i0->inst_c0) \
1310            disp = (ins->inst_i0->inst_c0 - ((guint8*)code - cfg->native_code)) >> 2; \
1311         else { \
1312             disp = 0; \
1313                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1314         } \
1315 } else { \
1316         if (ins->inst_true_bb->native_offset) \
1317            disp = (ins->inst_true_bb->native_offset - ((guint8*)code - cfg->native_code)) >> 2; \
1318         else { \
1319             disp = 0; \
1320                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1321         } \
1322 }
1323
1324 #ifdef SPARCV9
1325 #define DEFAULT_ICC sparc_xcc_short
1326 #else
1327 #define DEFAULT_ICC sparc_icc_short
1328 #endif
1329
1330 #ifdef SPARCV9
1331 #define EMIT_COND_BRANCH_ICC(ins,cond,annul,filldelay,icc) \
1332     do { \
1333         gint32 disp; \
1334         guint32 predict; \
1335         COMPUTE_DISP(ins); \
1336         predict = (disp != 0) ? 1 : 0; \
1337         g_assert (sparc_is_imm19 (disp)); \
1338         sparc_branchp (code, (annul), cond, icc, (predict), disp); \
1339         if (filldelay) sparc_nop (code); \
1340     } while (0)
1341 #define EMIT_COND_BRANCH(ins,cond,annul,filldelay) EMIT_COND_BRANCH_ICC ((ins), (cond), (annul), (filldelay), (sparc_xcc_short))
1342 #define EMIT_FLOAT_COND_BRANCH(ins,cond,annul,filldelay) \
1343     do { \
1344         gint32 disp; \
1345         guint32 predict; \
1346         COMPUTE_DISP(ins); \
1347         predict = (disp != 0) ? 1 : 0; \
1348         g_assert (sparc_is_imm19 (disp)); \
1349         sparc_fbranch (code, (annul), cond, disp); \
1350         if (filldelay) sparc_nop (code); \
1351     } while (0)
1352 #else
1353 #define EMIT_COND_BRANCH_ICC(ins,cond,annul,filldelay,icc) g_assert_not_reached ()
1354 #define EMIT_COND_BRANCH_GENERAL(ins,bop,cond,annul,filldelay) \
1355     do { \
1356         gint32 disp; \
1357         COMPUTE_DISP(ins); \
1358         g_assert (sparc_is_imm22 (disp)); \
1359         sparc_ ## bop (code, (annul), cond, disp); \
1360         if (filldelay) sparc_nop (code); \
1361     } while (0)
1362 #define EMIT_COND_BRANCH(ins,cond,annul,filldelay) EMIT_COND_BRANCH_GENERAL((ins),branch,(cond),annul,filldelay)
1363 #define EMIT_FLOAT_COND_BRANCH(ins,cond,annul,filldelay) EMIT_COND_BRANCH_GENERAL((ins),fbranch,(cond),annul,filldelay)
1364 #endif
1365
1366 #define EMIT_COND_BRANCH_PREDICTED(ins,cond,annul,filldelay) \
1367     do { \
1368             gint32 disp; \
1369         guint32 predict; \
1370         COMPUTE_DISP(ins); \
1371         predict = (disp != 0) ? 1 : 0; \
1372         g_assert (sparc_is_imm19 (disp)); \
1373                 sparc_branchp (code, (annul), (cond), DEFAULT_ICC, (predict), disp); \
1374         if (filldelay) sparc_nop (code); \
1375     } while (0)
1376
1377 #define EMIT_COND_BRANCH_BPR(ins,bop,predict,annul,filldelay) \
1378     do { \
1379             gint32 disp; \
1380         COMPUTE_DISP(ins); \
1381                 g_assert (sparc_is_imm22 (disp)); \
1382                 sparc_ ## bop (code, (annul), (predict), ins->sreg1, disp); \
1383         if (filldelay) sparc_nop (code); \
1384     } while (0)
1385
1386 /* emit an exception if condition is fail */
1387 /*
1388  * We put the exception throwing code out-of-line, at the end of the method
1389  */
1390 #define EMIT_COND_SYSTEM_EXCEPTION_GENERAL(ins,cond,sexc_name,filldelay,icc) do {     \
1391                 mono_add_patch_info (cfg, (guint8*)(code) - (cfg)->native_code,   \
1392                                     MONO_PATCH_INFO_EXC, sexc_name);  \
1393         if (sparcv9) { \
1394            sparc_branchp (code, 0, (cond), (icc), 0, 0); \
1395         } \
1396         else { \
1397                         sparc_branch (code, 0, cond, 0);     \
1398         } \
1399         if (filldelay) sparc_nop (code);     \
1400         } while (0);
1401
1402 #define EMIT_COND_SYSTEM_EXCEPTION(ins,cond,sexc_name) EMIT_COND_SYSTEM_EXCEPTION_GENERAL(ins,cond,sexc_name,TRUE,DEFAULT_ICC)
1403
1404 #define EMIT_COND_SYSTEM_EXCEPTION_BPR(ins,bop,sexc_name) do { \
1405                 mono_add_patch_info (cfg, (guint8*)(code) - (cfg)->native_code,   \
1406                                     MONO_PATCH_INFO_EXC, sexc_name);  \
1407                 sparc_ ## bop (code, FALSE, FALSE, ins->sreg1, 0); \
1408         sparc_nop (code);    \
1409 } while (0);
1410
1411 #define EMIT_ALU_IMM(ins,op,setcc) do { \
1412                         if (sparc_is_imm13 ((ins)->inst_imm)) \
1413                                 sparc_ ## op ## _imm (code, (setcc), (ins)->sreg1, ins->inst_imm, (ins)->dreg); \
1414                         else { \
1415                                 sparc_set (code, ins->inst_imm, sparc_o7); \
1416                                 sparc_ ## op (code, (setcc), (ins)->sreg1, sparc_o7, (ins)->dreg); \
1417                         } \
1418 } while (0);
1419
1420 #define EMIT_LOAD_MEMBASE(ins,op) do { \
1421                         if (sparc_is_imm13 (ins->inst_offset)) \
1422                                 sparc_ ## op ## _imm (code, ins->inst_basereg, ins->inst_offset, ins->dreg); \
1423                         else { \
1424                                 sparc_set (code, ins->inst_offset, sparc_o7); \
1425                                 sparc_ ## op (code, ins->inst_basereg, sparc_o7, ins->dreg); \
1426                         } \
1427 } while (0);
1428
1429 /* max len = 5 */
1430 #define EMIT_STORE_MEMBASE_IMM(ins,op) do { \
1431                         guint32 sreg; \
1432                         if (ins->inst_imm == 0) \
1433                                 sreg = sparc_g0; \
1434                         else { \
1435                                 sparc_set (code, ins->inst_imm, sparc_o7); \
1436                                 sreg = sparc_o7; \
1437                         } \
1438                         if (!sparc_is_imm13 (ins->inst_offset)) { \
1439                                 sparc_set (code, ins->inst_offset, GP_SCRATCH_REG); \
1440                                 sparc_ ## op (code, sreg, ins->inst_destbasereg, GP_SCRATCH_REG); \
1441                         } \
1442                         else \
1443                                 sparc_ ## op ## _imm (code, sreg, ins->inst_destbasereg, ins->inst_offset); \
1444                                                                                                                                                                                  } while (0);
1445
1446 #define EMIT_STORE_MEMBASE_REG(ins,op) do { \
1447                         if (!sparc_is_imm13 (ins->inst_offset)) { \
1448                                 sparc_set (code, ins->inst_offset, sparc_o7); \
1449                                 sparc_ ## op (code, ins->sreg1, ins->inst_destbasereg, sparc_o7); \
1450                         } \
1451                                   else \
1452                                 sparc_ ## op ## _imm (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset); \
1453                                                                                                                                                                                  } while (0);
1454
1455 #define EMIT_CALL() do { \
1456     if (v64) { \
1457         sparc_set_template (code, sparc_o7); \
1458         sparc_jmpl (code, sparc_o7, sparc_g0, sparc_o7); \
1459     } \
1460     else { \
1461         sparc_call_simple (code, 0); \
1462     } \
1463     sparc_nop (code); \
1464 } while (0);
1465
1466 /*
1467  * A call template is 7 instructions long, so we want to avoid it if possible.
1468  */
1469 static guint32*
1470 emit_call (MonoCompile *cfg, guint32 *code, guint32 patch_type, gconstpointer data)
1471 {
1472         gpointer target;
1473
1474         /* FIXME: This only works if the target method is already compiled */
1475         if (0 && v64 && !cfg->compile_aot) {
1476                 MonoJumpInfo patch_info;
1477
1478                 patch_info.type = patch_type;
1479                 patch_info.data.target = data;
1480
1481                 target = mono_resolve_patch_target (cfg->method, cfg->domain, NULL, &patch_info, FALSE);
1482
1483                 /* FIXME: Add optimizations if the target is close enough */
1484                 sparc_set (code, target, sparc_o7);
1485                 sparc_jmpl (code, sparc_o7, sparc_g0, sparc_o7);
1486                 sparc_nop (code);
1487         }
1488         else {
1489                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, patch_type, data);
1490                 EMIT_CALL ();
1491         }
1492
1493         return code;
1494 }
1495
1496 static void
1497 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1498 {
1499         MonoInst *ins, *last_ins = NULL;
1500         ins = bb->code;
1501
1502         while (ins) {
1503
1504                 switch (ins->opcode) {
1505                 case OP_MUL_IMM:
1506                         /* remove unnecessary multiplication with 1 */
1507                         if (ins->inst_imm == 1) {
1508                                 if (ins->dreg != ins->sreg1) {
1509                                         ins->opcode = OP_MOVE;
1510                                 } else {
1511                                         last_ins->next = ins->next;
1512                                         ins = ins->next;
1513                                         continue;
1514                                 }
1515                         }
1516                         break;
1517 #ifndef SPARCV9
1518                 case OP_LOAD_MEMBASE:
1519                 case OP_LOADI4_MEMBASE:
1520                         /*
1521                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1522                          * OP_LOAD_MEMBASE offset(basereg), reg
1523                          */
1524                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1525                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1526                             ins->inst_basereg == last_ins->inst_destbasereg &&
1527                             ins->inst_offset == last_ins->inst_offset) {
1528                                 if (ins->dreg == last_ins->sreg1) {
1529                                         last_ins->next = ins->next;
1530                                         ins = ins->next;
1531                                         continue;
1532                                 } else {
1533                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1534                                         ins->opcode = OP_MOVE;
1535                                         ins->sreg1 = last_ins->sreg1;
1536                                 }
1537
1538                         /*
1539                          * Note: reg1 must be different from the basereg in the second load
1540                          * OP_LOAD_MEMBASE offset(basereg), reg1
1541                          * OP_LOAD_MEMBASE offset(basereg), reg2
1542                          * -->
1543                          * OP_LOAD_MEMBASE offset(basereg), reg1
1544                          * OP_MOVE reg1, reg2
1545                          */
1546                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
1547                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
1548                               ins->inst_basereg != last_ins->dreg &&
1549                               ins->inst_basereg == last_ins->inst_basereg &&
1550                               ins->inst_offset == last_ins->inst_offset) {
1551
1552                                 if (ins->dreg == last_ins->dreg) {
1553                                         last_ins->next = ins->next;
1554                                         ins = ins->next;
1555                                         continue;
1556                                 } else {
1557                                         ins->opcode = OP_MOVE;
1558                                         ins->sreg1 = last_ins->dreg;
1559                                 }
1560
1561                                 //g_assert_not_reached ();
1562
1563 #if 0
1564                         /*
1565                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1566                          * OP_LOAD_MEMBASE offset(basereg), reg
1567                          * -->
1568                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1569                          * OP_ICONST reg, imm
1570                          */
1571                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
1572                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
1573                                    ins->inst_basereg == last_ins->inst_destbasereg &&
1574                                    ins->inst_offset == last_ins->inst_offset) {
1575                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1576                                 ins->opcode = OP_ICONST;
1577                                 ins->inst_c0 = last_ins->inst_imm;
1578                                 g_assert_not_reached (); // check this rule
1579 #endif
1580                         }
1581                         break;
1582 #endif
1583                 case OP_LOADU1_MEMBASE:
1584                 case OP_LOADI1_MEMBASE:
1585                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
1586                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1587                                         ins->inst_offset == last_ins->inst_offset) {
1588                                 if (ins->dreg == last_ins->sreg1) {
1589                                         last_ins->next = ins->next;
1590                                         ins = ins->next;
1591                                         continue;
1592                                 } else {
1593                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1594                                         ins->opcode = OP_MOVE;
1595                                         ins->sreg1 = last_ins->sreg1;
1596                                 }
1597                         }
1598                         break;
1599                 case OP_LOADU2_MEMBASE:
1600                 case OP_LOADI2_MEMBASE:
1601                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
1602                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1603                                         ins->inst_offset == last_ins->inst_offset) {
1604                                 if (ins->dreg == last_ins->sreg1) {
1605                                         last_ins->next = ins->next;
1606                                         ins = ins->next;
1607                                         continue;
1608                                 } else {
1609                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1610                                         ins->opcode = OP_MOVE;
1611                                         ins->sreg1 = last_ins->sreg1;
1612                                 }
1613                         }
1614                         break;
1615                 case OP_STOREI4_MEMBASE_IMM:
1616                         /* Convert pairs of 0 stores to a dword 0 store */
1617                         /* Used when initializing temporaries */
1618                         /* We know sparc_fp is dword aligned */
1619                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM) &&
1620                                 (ins->inst_destbasereg == last_ins->inst_destbasereg) &&
1621                                 (ins->inst_destbasereg == sparc_fp) &&
1622                                 (ins->inst_offset < 0) &&
1623                                 ((ins->inst_offset % 8) == 0) &&
1624                                 ((ins->inst_offset == last_ins->inst_offset - 4)) &&
1625                                 (ins->inst_imm == 0) &&
1626                                 (last_ins->inst_imm == 0)) {
1627                                 if (sparcv9) {
1628                                         last_ins->opcode = OP_STOREI8_MEMBASE_IMM;
1629                                         last_ins->inst_offset = ins->inst_offset;
1630                                         last_ins->next = ins->next;
1631                                         ins = ins->next;
1632                                         continue;
1633                                 }
1634                         }
1635                         break;
1636                 case CEE_BEQ:
1637                 case CEE_BNE_UN:
1638                 case CEE_BLT:
1639                 case CEE_BGT:
1640                 case CEE_BGE:
1641                 case CEE_BLE:
1642                 case OP_COND_EXC_EQ:
1643                 case OP_COND_EXC_GE:
1644                 case OP_COND_EXC_GT:
1645                 case OP_COND_EXC_LE:
1646                 case OP_COND_EXC_LT:
1647                 case OP_COND_EXC_NE_UN:
1648                         /*
1649                          * Convert compare with zero+branch to BRcc
1650                          */
1651                         /*
1652                          * This only works in 64 bit mode, since it examines all 64
1653                          * bits of the register.
1654                          * Only do this if the method is small since BPr only has a 16bit
1655                          * displacement.
1656                          */
1657                         if (v64 && (mono_method_get_header (cfg->method)->code_size < 10000) && last_ins &&
1658                                 (last_ins->opcode == OP_COMPARE_IMM) &&
1659                                 (last_ins->inst_imm == 0)) {
1660                                 MonoInst *next = ins->next;
1661                                 switch (ins->opcode) {
1662                                 case CEE_BEQ:
1663                                         ins->opcode = OP_SPARC_BRZ;
1664                                         break;
1665                                 case CEE_BNE_UN:
1666                                         ins->opcode = OP_SPARC_BRNZ;
1667                                         break;
1668                                 case CEE_BLT:
1669                                         ins->opcode = OP_SPARC_BRLZ;
1670                                         break;
1671                                 case CEE_BGT:
1672                                         ins->opcode = OP_SPARC_BRGZ;
1673                                         break;
1674                                 case CEE_BGE:
1675                                         ins->opcode = OP_SPARC_BRGEZ;
1676                                         break;
1677                                 case CEE_BLE:
1678                                         ins->opcode = OP_SPARC_BRLEZ;
1679                                         break;
1680                                 case OP_COND_EXC_EQ:
1681                                         ins->opcode = OP_SPARC_COND_EXC_EQZ;
1682                                         break;
1683                                 case OP_COND_EXC_GE:
1684                                         ins->opcode = OP_SPARC_COND_EXC_GEZ;
1685                                         break;
1686                                 case OP_COND_EXC_GT:
1687                                         ins->opcode = OP_SPARC_COND_EXC_GTZ;
1688                                         break;
1689                                 case OP_COND_EXC_LE:
1690                                         ins->opcode = OP_SPARC_COND_EXC_LEZ;
1691                                         break;
1692                                 case OP_COND_EXC_LT:
1693                                         ins->opcode = OP_SPARC_COND_EXC_LTZ;
1694                                         break;
1695                                 case OP_COND_EXC_NE_UN:
1696                                         ins->opcode = OP_SPARC_COND_EXC_NEZ;
1697                                         break;
1698                                 default:
1699                                         g_assert_not_reached ();
1700                                 }
1701                                 ins->sreg1 = last_ins->sreg1;
1702                                 *last_ins = *ins;
1703                                 last_ins->next = next;
1704                                 ins = next;
1705                                 continue;
1706                         }
1707                         break;
1708                 case CEE_CONV_I4:
1709                 case CEE_CONV_U4:
1710                 case OP_MOVE:
1711                         /*
1712                          * OP_MOVE reg, reg
1713                          */
1714                         if (ins->dreg == ins->sreg1) {
1715                                 if (last_ins)
1716                                         last_ins->next = ins->next;
1717                                 ins = ins->next;
1718                                 continue;
1719                         }
1720                         /*
1721                          * OP_MOVE sreg, dreg
1722                          * OP_MOVE dreg, sreg
1723                          */
1724                         if (last_ins && last_ins->opcode == OP_MOVE &&
1725                             ins->sreg1 == last_ins->dreg &&
1726                             ins->dreg == last_ins->sreg1) {
1727                                 last_ins->next = ins->next;
1728                                 ins = ins->next;
1729                                 continue;
1730                         }
1731                         break;
1732                 }
1733                 last_ins = ins;
1734                 ins = ins->next;
1735         }
1736         bb->last_ins = last_ins;
1737 }
1738
1739 static const char*const * ins_spec = sparc_desc;
1740
1741 static inline const char*
1742 get_ins_spec (int opcode)
1743 {
1744         if (ins_spec [opcode])
1745                 return ins_spec [opcode];
1746         else
1747                 return ins_spec [CEE_ADD];
1748 }
1749
1750 static int
1751 mono_spillvar_offset_float (MonoCompile *cfg, int spillvar)
1752 {
1753         MonoSpillInfo **si, *info;
1754         int i = 0;
1755
1756         si = &cfg->spill_info_float;
1757
1758         while (i <= spillvar) {
1759
1760                 if (!*si) {
1761                         *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
1762                         info->next = NULL;
1763                         cfg->stack_offset += sizeof (double);
1764                         cfg->stack_offset = ALIGN_TO (cfg->stack_offset, 8);
1765                         info->offset = - cfg->stack_offset;
1766                 }
1767
1768                 if (i == spillvar)
1769                         return MONO_SPARC_STACK_BIAS + (*si)->offset;
1770
1771                 i++;
1772                 si = &(*si)->next;
1773         }
1774
1775         g_assert_not_reached ();
1776         return 0;
1777 }
1778
1779 /* FIXME: Strange loads from the stack in basic-float.cs:test_2_rem */
1780
1781 void
1782 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1783 {
1784         mono_local_regalloc (cfg, bb);
1785 }
1786
1787 static void
1788 sparc_patch (guint32 *code, const gpointer target)
1789 {
1790         guint32 *c = code;
1791         guint32 ins = *code;
1792         guint32 op = ins >> 30;
1793         guint32 op2 = (ins >> 22) & 0x7;
1794         guint32 rd = (ins >> 25) & 0x1f;
1795         guint8* target8 = (guint8*)target;
1796         gint64 disp = (target8 - (guint8*)code) >> 2;
1797         int reg;
1798
1799 //      g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
1800
1801         if ((op == 0) && (op2 == 2)) {
1802                 if (!sparc_is_imm22 (disp))
1803                         NOT_IMPLEMENTED;
1804                 /* Bicc */
1805                 *code = ((ins >> 22) << 22) | (disp & 0x3fffff);
1806         }
1807         else if ((op == 0) && (op2 == 1)) {
1808                 if (!sparc_is_imm19 (disp))
1809                         NOT_IMPLEMENTED;
1810                 /* BPcc */
1811                 *code = ((ins >> 19) << 19) | (disp & 0x7ffff);
1812         }
1813         else if ((op == 0) && (op2 == 3)) {
1814                 if (!sparc_is_imm16 (disp))
1815                         NOT_IMPLEMENTED;
1816                 /* BPr */
1817                 *code &= ~(0x180000 | 0x3fff);
1818                 *code |= ((disp << 21) & (0x180000)) | (disp & 0x3fff);
1819         }
1820         else if ((op == 0) && (op2 == 6)) {
1821                 if (!sparc_is_imm22 (disp))
1822                         NOT_IMPLEMENTED;
1823                 /* FBicc */
1824                 *code = ((ins >> 22) << 22) | (disp & 0x3fffff);
1825         }
1826         else if ((op == 0) && (op2 == 4)) {
1827                 guint32 ins2 = code [1];
1828
1829                 if (((ins2 >> 30) == 2) && (((ins2 >> 19) & 0x3f) == 2)) {
1830                         /* sethi followed by or */
1831                         guint32 *p = code;
1832                         sparc_set (p, target8, rd);
1833                         while (p <= (code + 1))
1834                                 sparc_nop (p);
1835                 }
1836                 else if (ins2 == 0x01000000) {
1837                         /* sethi followed by nop */
1838                         guint32 *p = code;
1839                         sparc_set (p, target8, rd);
1840                         while (p <= (code + 1))
1841                                 sparc_nop (p);
1842                 }
1843                 else if ((sparc_inst_op (ins2) == 3) && (sparc_inst_imm (ins2))) {
1844                         /* sethi followed by load/store */
1845 #ifndef SPARCV9
1846                         guint32 t = (guint32)target8;
1847                         *code &= ~(0x3fffff);
1848                         *code |= (t >> 10);
1849                         *(code + 1) &= ~(0x3ff);
1850                         *(code + 1) |= (t & 0x3ff);
1851 #endif
1852                 }
1853                 else if (v64 &&
1854                                  (sparc_inst_rd (ins) == sparc_g1) &&
1855                                  (sparc_inst_op (c [1]) == 0) && (sparc_inst_op2 (c [1]) == 4) &&
1856                                  (sparc_inst_op (c [2]) == 2) && (sparc_inst_op3 (c [2]) == 2) &&
1857                                  (sparc_inst_op (c [3]) == 2) && (sparc_inst_op3 (c [3]) == 2))
1858                 {
1859                         /* sparc_set */
1860                         guint32 *p = c;
1861                         reg = sparc_inst_rd (c [1]);
1862                         sparc_set (p, target8, reg);
1863                         while (p < (c + 6))
1864                                 sparc_nop (p);
1865                 }
1866                 else if ((sparc_inst_op (ins2) == 2) && (sparc_inst_op3 (ins2) == 0x38) &&
1867                                  (sparc_inst_imm (ins2))) {
1868                         /* sethi followed by jmpl */
1869 #ifndef SPARCV9
1870                         guint32 t = (guint32)target8;
1871                         *code &= ~(0x3fffff);
1872                         *code |= (t >> 10);
1873                         *(code + 1) &= ~(0x3ff);
1874                         *(code + 1) |= (t & 0x3ff);
1875 #endif
1876                 }
1877                 else
1878                         NOT_IMPLEMENTED;
1879         }
1880         else if (op == 01) {
1881                 gint64 disp = (target8 - (guint8*)code) >> 2;
1882
1883                 if (!sparc_is_imm30 (disp))
1884                         NOT_IMPLEMENTED;
1885                 sparc_call_simple (code, target8 - (guint8*)code);
1886         }
1887         else if ((op == 2) && (sparc_inst_op3 (ins) == 0x2) && sparc_inst_imm (ins)) {
1888                 /* mov imm, reg */
1889                 g_assert (sparc_is_imm13 (target8));
1890                 *code &= ~(0x1fff);
1891                 *code |= (guint32)target8;
1892         }
1893         else if ((sparc_inst_op (ins) == 2) && (sparc_inst_op3 (ins) == 0x7)) {
1894                 /* sparc_set case 5. */
1895                 guint32 *p = c;
1896
1897                 g_assert (v64);
1898                 reg = sparc_inst_rd (c [3]);
1899                 sparc_set (p, target, reg);
1900                 while (p < (c + 6))
1901                         sparc_nop (p);
1902         }
1903         else
1904                 NOT_IMPLEMENTED;
1905
1906 //      g_print ("patched with 0x%08x\n", ins);
1907 }
1908
1909 /*
1910  * mono_sparc_emit_save_lmf:
1911  *
1912  *  Emit the code neccesary to push a new entry onto the lmf stack. Used by
1913  * trampolines as well.
1914  */
1915 guint32*
1916 mono_sparc_emit_save_lmf (guint32 *code, guint32 lmf_offset)
1917 {
1918         /* Save lmf_addr */
1919         sparc_sti_imm (code, sparc_o0, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr));
1920         /* Save previous_lmf */
1921         sparc_ldi (code, sparc_o0, sparc_g0, sparc_o7);
1922         sparc_sti_imm (code, sparc_o7, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf));
1923         /* Set new lmf */
1924         sparc_add_imm (code, FALSE, sparc_fp, lmf_offset, sparc_o7);
1925         sparc_sti (code, sparc_o7, sparc_o0, sparc_g0);
1926
1927         return code;
1928 }
1929
1930 guint32*
1931 mono_sparc_emit_restore_lmf (guint32 *code, guint32 lmf_offset)
1932 {
1933         /* Load previous_lmf */
1934         sparc_ldi_imm (code, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sparc_l0);
1935         /* Load lmf_addr */
1936         sparc_ldi_imm (code, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), sparc_l1);
1937         /* *(lmf) = previous_lmf */
1938         sparc_sti (code, sparc_l0, sparc_l1, sparc_g0);
1939         return code;
1940 }
1941
1942 static guint32*
1943 emit_save_sp_to_lmf (MonoCompile *cfg, guint32 *code)
1944 {
1945         /*
1946          * Since register windows are saved to the current value of %sp, we need to
1947          * set the sp field in the lmf before the call, not in the prolog.
1948          */
1949         if (cfg->method->save_lmf) {
1950                 gint32 lmf_offset = MONO_SPARC_STACK_BIAS - cfg->arch.lmf_offset;
1951
1952                 /* Save sp */
1953                 sparc_sti_imm (code, sparc_sp, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, sp));
1954         }
1955
1956         return code;
1957 }
1958
1959 static guint32*
1960 emit_vret_token (MonoInst *ins, guint32 *code)
1961 {
1962         MonoCallInst *call = (MonoCallInst*)ins;
1963         guint32 size;
1964
1965         /*
1966          * The sparc ABI requires that calls to functions which return a structure
1967          * contain an additional unimpl instruction which is checked by the callee.
1968          */
1969         if (call->signature->pinvoke && MONO_TYPE_ISSTRUCT(call->signature->ret)) {
1970                 if (call->signature->ret->type == MONO_TYPE_TYPEDBYREF)
1971                         size = mono_type_stack_size (call->signature->ret, NULL);
1972                 else
1973                         size = mono_class_native_size (call->signature->ret->data.klass, NULL);
1974                 sparc_unimp (code, size & 0xfff);
1975         }
1976
1977         return code;
1978 }
1979
1980 static guint32*
1981 emit_move_return_value (MonoInst *ins, guint32 *code)
1982 {
1983         /* Move return value to the target register */
1984         /* FIXME: do more things in the local reg allocator */
1985         switch (ins->opcode) {
1986         case OP_VOIDCALL:
1987         case OP_VOIDCALL_REG:
1988         case OP_VOIDCALL_MEMBASE:
1989                 break;
1990         case CEE_CALL:
1991         case OP_CALL_REG:
1992         case OP_CALL_MEMBASE:
1993                 g_assert (ins->dreg == sparc_o0);
1994                 break;
1995         case OP_LCALL:
1996         case OP_LCALL_REG:
1997         case OP_LCALL_MEMBASE:
1998                 /*
1999                  * ins->dreg is the least significant reg due to the lreg: LCALL rule
2000                  * in inssel-long32.brg.
2001                  */
2002 #ifdef SPARCV9
2003                 sparc_mov_reg_reg (code, sparc_o0, ins->dreg);
2004 #else
2005                 g_assert (ins->dreg == sparc_o1);
2006 #endif
2007                 break;
2008         case OP_FCALL:
2009         case OP_FCALL_REG:
2010         case OP_FCALL_MEMBASE:
2011 #ifdef SPARCV9
2012                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2013                         sparc_fmovs (code, sparc_f0, ins->dreg);
2014                         sparc_fstod (code, ins->dreg, ins->dreg);
2015                 }
2016                 else
2017                         sparc_fmovd (code, sparc_f0, ins->dreg);
2018 #else
2019                 sparc_fmovs (code, sparc_f0, ins->dreg);
2020                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4)
2021                         sparc_fstod (code, ins->dreg, ins->dreg);
2022                 else
2023                         sparc_fmovs (code, sparc_f1, ins->dreg + 1);
2024 #endif
2025                 break;
2026         case OP_VCALL:
2027         case OP_VCALL_REG:
2028         case OP_VCALL_MEMBASE:
2029                 break;
2030         default:
2031                 NOT_IMPLEMENTED;
2032         }
2033
2034         return code;
2035 }
2036
2037 /*
2038  * emit_load_volatile_arguments:
2039  *
2040  *  Load volatile arguments from the stack to the original input registers.
2041  * Required before a tail call.
2042  */
2043 static guint32*
2044 emit_load_volatile_arguments (MonoCompile *cfg, guint32 *code)
2045 {
2046         MonoMethod *method = cfg->method;
2047         MonoMethodSignature *sig;
2048         MonoInst *inst;
2049         CallInfo *cinfo;
2050         guint32 i, ireg;
2051
2052         /* FIXME: Generate intermediate code instead */
2053
2054         sig = mono_method_signature (method);
2055
2056         cinfo = get_call_info (sig, FALSE);
2057
2058         /* This is the opposite of the code in emit_prolog */
2059
2060         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2061                 ArgInfo *ainfo = cinfo->args + i;
2062                 gint32 stack_offset;
2063                 MonoType *arg_type;
2064                 inst = cfg->varinfo [i];
2065
2066                 if (sig->hasthis && (i == 0))
2067                         arg_type = &mono_defaults.object_class->byval_arg;
2068                 else
2069                         arg_type = sig->params [i - sig->hasthis];
2070
2071                 stack_offset = ainfo->offset + ARGS_OFFSET;
2072                 ireg = sparc_i0 + ainfo->reg;
2073
2074                 if (ainfo->storage == ArgInSplitRegStack) {
2075                         g_assert (inst->opcode == OP_REGOFFSET);
2076
2077                         if (!sparc_is_imm13 (stack_offset))
2078                                 NOT_IMPLEMENTED;
2079                         sparc_st_imm (code, inst->inst_basereg, stack_offset, sparc_i5);
2080                 }
2081
2082                 if (!v64 && !arg_type->byref && (arg_type->type == MONO_TYPE_R8)) {
2083                         if (ainfo->storage == ArgInIRegPair) {
2084                                 if (!sparc_is_imm13 (inst->inst_offset + 4))
2085                                         NOT_IMPLEMENTED;
2086                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset, ireg);
2087                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset + 4, ireg + 1);
2088                         }
2089                         else
2090                                 if (ainfo->storage == ArgInSplitRegStack) {
2091                                         if (stack_offset != inst->inst_offset) {
2092                                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset, sparc_i5);
2093                                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset + 4, sparc_o7);
2094                                                 sparc_st_imm (code, sparc_o7, sparc_fp, stack_offset + 4);
2095
2096                                         }
2097                                 }
2098                         else
2099                                 if (ainfo->storage == ArgOnStackPair) {
2100                                         if (stack_offset != inst->inst_offset) {
2101                                                 /* stack_offset is not dword aligned, so we need to make a copy */
2102                                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset, sparc_o7);
2103                                                 sparc_st_imm (code, sparc_o7, sparc_fp, stack_offset);
2104
2105                                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset + 4, sparc_o7);
2106                                                 sparc_st_imm (code, sparc_o7, sparc_fp, stack_offset + 4);
2107
2108                                         }
2109                                 }
2110                          else
2111                                 g_assert_not_reached ();
2112                 }
2113                 else
2114                         if ((ainfo->storage == ArgInIReg) && (inst->opcode != OP_REGVAR)) {
2115                                 /* Argument in register, but need to be saved to stack */
2116                                 if (!sparc_is_imm13 (stack_offset))
2117                                         NOT_IMPLEMENTED;
2118                                 if ((stack_offset - ARGS_OFFSET) & 0x1)
2119                                         /* FIXME: Is this ldsb or ldub ? */
2120                                         sparc_ldsb_imm (code, inst->inst_basereg, stack_offset, ireg);
2121                                 else
2122                                         if ((stack_offset - ARGS_OFFSET) & 0x2)
2123                                                 sparc_ldsh_imm (code, inst->inst_basereg, stack_offset, ireg);
2124                                 else
2125                                         if ((stack_offset - ARGS_OFFSET) & 0x4)
2126                                                 sparc_ld_imm (code, inst->inst_basereg, stack_offset, ireg);
2127                                         else {
2128                                                 if (v64)
2129                                                         sparc_ldx_imm (code, inst->inst_basereg, stack_offset, ireg);
2130                                                 else
2131                                                         sparc_ld_imm (code, inst->inst_basereg, stack_offset, ireg);
2132                                         }
2133                         }
2134                         else if ((ainfo->storage == ArgInIRegPair) && (inst->opcode != OP_REGVAR)) {
2135                                 /* Argument in regpair, but need to be saved to stack */
2136                                 if (!sparc_is_imm13 (inst->inst_offset + 4))
2137                                         NOT_IMPLEMENTED;
2138                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset, ireg);
2139                                 sparc_st_imm (code, inst->inst_basereg, inst->inst_offset + 4, ireg + 1);
2140                         }
2141                         else if ((ainfo->storage == ArgInFloatReg) && (inst->opcode != OP_REGVAR)) {
2142                                 NOT_IMPLEMENTED;
2143                         }
2144                         else if ((ainfo->storage == ArgInDoubleReg) && (inst->opcode != OP_REGVAR)) {
2145                                 NOT_IMPLEMENTED;
2146                         }
2147
2148                 if ((ainfo->storage == ArgInSplitRegStack) || (ainfo->storage == ArgOnStack))
2149                         if (inst->opcode == OP_REGVAR)
2150                                 /* FIXME: Load the argument into memory */
2151                                 NOT_IMPLEMENTED;
2152         }
2153
2154         g_free (cinfo);
2155
2156         return code;
2157 }
2158
2159 /*
2160  * mono_sparc_is_virtual_call:
2161  *
2162  *  Determine whenever the instruction at CODE is a virtual call.
2163  */
2164 gboolean
2165 mono_sparc_is_virtual_call (guint32 *code)
2166 {
2167         guint32 buf[1];
2168         guint32 *p;
2169
2170         p = buf;
2171
2172         if ((sparc_inst_op (*code) == 0x2) && (sparc_inst_op3 (*code) == 0x38)) {
2173                 /*
2174                  * Register indirect call. If it is a virtual call, then the
2175                  * instruction in the delay slot is a special kind of nop.
2176                  */
2177
2178                 /* Construct special nop */
2179                 sparc_or_imm (p, FALSE, sparc_g0, 0xca, sparc_g0);
2180                 p --;
2181
2182                 if (code [1] == p [0])
2183                         return TRUE;
2184         }
2185
2186         return FALSE;
2187 }
2188
2189 /*
2190  * mono_arch_get_vcall_slot_addr:
2191  *
2192  *  Determine the vtable slot used by a virtual call.
2193  */
2194 gpointer*
2195 mono_arch_get_vcall_slot_addr (guint8 *code8, gpointer *regs)
2196 {
2197         guint32 *code = (guint32*)(gpointer)code8;
2198         guint32 ins = code [0];
2199         guint32 prev_ins = code [-1];
2200
2201         mono_sparc_flushw ();
2202
2203         if (!mono_sparc_is_virtual_call (code))
2204                 return NULL;
2205
2206         if ((sparc_inst_op (ins) == 0x2) && (sparc_inst_op3 (ins) == 0x38)) {
2207                 if ((sparc_inst_op (prev_ins) == 0x3) && (sparc_inst_i (prev_ins) == 1) && (sparc_inst_op3 (prev_ins) == 0 || sparc_inst_op3 (prev_ins) == 0xb)) {
2208                         /* ld [r1 + CONST ], r2; call r2 */
2209                         guint32 base = sparc_inst_rs1 (prev_ins);
2210                         guint32 disp = sparc_inst_imm13 (prev_ins);
2211                         gpointer base_val;
2212
2213                         g_assert (sparc_inst_rd (prev_ins) == sparc_inst_rs1 (ins));
2214
2215                         g_assert ((base >= sparc_o0) && (base <= sparc_i7));
2216
2217                         base_val = regs [base - sparc_o0];
2218
2219                         return (gpointer)((guint8*)base_val + disp);
2220                 }
2221                 else if ((sparc_inst_op (prev_ins) == 0x3) && (sparc_inst_i (prev_ins) == 0) && (sparc_inst_op3 (prev_ins) == 0)) {
2222                         /* set r1, ICONST; ld [r1 + r2], r2; call r2 */
2223                         /* Decode a sparc_set32 */
2224                         guint32 base = sparc_inst_rs1 (prev_ins);
2225                         guint32 disp;
2226                         gpointer base_val;
2227                         guint32 s1 = code [-3];
2228                         guint32 s2 = code [-2];
2229
2230 #ifdef SPARCV9
2231                         NOT_IMPLEMENTED;
2232 #endif
2233
2234                         /* sparc_sethi */
2235                         g_assert (sparc_inst_op (s1) == 0);
2236                         g_assert (sparc_inst_op2 (s1) == 4);
2237
2238                         /* sparc_or_imm */
2239                         g_assert (sparc_inst_op (s2) == 2);
2240                         g_assert (sparc_inst_op3 (s2) == 2);
2241                         g_assert (sparc_inst_i (s2) == 1);
2242                         g_assert (sparc_inst_rs1 (s2) == sparc_inst_rd (s2));
2243                         g_assert (sparc_inst_rd (s1) == sparc_inst_rs1 (s2));
2244
2245                         disp = ((s1 & 0x3fffff) << 10) | sparc_inst_imm13 (s2);
2246
2247                         g_assert ((base >= sparc_o0) && (base <= sparc_i7));
2248
2249                         base_val = regs [base - sparc_o0];
2250
2251                         return (gpointer)((guint8*)base_val + disp);
2252                 } else
2253                         g_assert_not_reached ();
2254         }
2255         else
2256                 g_assert_not_reached ();
2257
2258         return NULL;
2259 }
2260
2261 /*
2262  * Some conventions used in the following code.
2263  * 2) The only scratch registers we have are o7 and g1.  We try to
2264  * stick to o7 when we can, and use g1 when necessary.
2265  */
2266
2267 void
2268 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2269 {
2270         MonoInst *ins;
2271         MonoCallInst *call;
2272         guint offset;
2273         guint32 *code = (guint32*)(cfg->native_code + cfg->code_len);
2274         MonoInst *last_ins = NULL;
2275         int max_len, cpos;
2276         const char *spec;
2277
2278         if (cfg->opt & MONO_OPT_PEEPHOLE)
2279                 peephole_pass (cfg, bb);
2280
2281         if (cfg->verbose_level > 2)
2282                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2283
2284         cpos = bb->max_offset;
2285
2286         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2287                 NOT_IMPLEMENTED;
2288         }
2289
2290         ins = bb->code;
2291         while (ins) {
2292                 guint8* code_start;
2293
2294                 offset = (guint8*)code - cfg->native_code;
2295
2296                 spec = ins_spec [ins->opcode];
2297                 if (!spec)
2298                         spec = ins_spec [CEE_ADD];
2299
2300                 max_len = ((guint8 *)spec)[MONO_INST_LEN];
2301
2302                 if (offset > (cfg->code_size - max_len - 16)) {
2303                         cfg->code_size *= 2;
2304                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2305                         code = (guint32*)(cfg->native_code + offset);
2306                 }
2307                 code_start = (guint8*)code;
2308                 //      if (ins->cil_code)
2309                 //              g_print ("cil code\n");
2310                 mono_debug_record_line_number (cfg, ins, offset);
2311
2312                 switch (ins->opcode) {
2313                 case OP_STOREI1_MEMBASE_IMM:
2314                         EMIT_STORE_MEMBASE_IMM (ins, stb);
2315                         break;
2316                 case OP_STOREI2_MEMBASE_IMM:
2317                         EMIT_STORE_MEMBASE_IMM (ins, sth);
2318                         break;
2319                 case OP_STORE_MEMBASE_IMM:
2320                         EMIT_STORE_MEMBASE_IMM (ins, sti);
2321                         break;
2322                 case OP_STOREI4_MEMBASE_IMM:
2323                         EMIT_STORE_MEMBASE_IMM (ins, st);
2324                         break;
2325                 case OP_STOREI8_MEMBASE_IMM:
2326 #ifdef SPARCV9
2327                         EMIT_STORE_MEMBASE_IMM (ins, stx);
2328 #else
2329                         /* Only generated by peephole opts */
2330                         g_assert ((ins->inst_offset % 8) == 0);
2331                         g_assert (ins->inst_imm == 0);
2332                         EMIT_STORE_MEMBASE_IMM (ins, stx);
2333 #endif
2334                         break;
2335                 case OP_STOREI1_MEMBASE_REG:
2336                         EMIT_STORE_MEMBASE_REG (ins, stb);
2337                         break;
2338                 case OP_STOREI2_MEMBASE_REG:
2339                         EMIT_STORE_MEMBASE_REG (ins, sth);
2340                         break;
2341                 case OP_STOREI4_MEMBASE_REG:
2342                         EMIT_STORE_MEMBASE_REG (ins, st);
2343                         break;
2344                 case OP_STOREI8_MEMBASE_REG:
2345 #ifdef SPARCV9
2346                         EMIT_STORE_MEMBASE_REG (ins, stx);
2347 #else
2348                         /* Only used by OP_MEMSET */
2349                         EMIT_STORE_MEMBASE_REG (ins, std);
2350 #endif
2351                         break;
2352                 case OP_STORE_MEMBASE_REG:
2353                         EMIT_STORE_MEMBASE_REG (ins, sti);
2354                         break;
2355                 case CEE_LDIND_I:
2356 #ifdef SPARCV9
2357                         sparc_ldx (code, ins->inst_c0, sparc_g0, ins->dreg);
2358 #else
2359                         sparc_ld (code, ins->inst_c0, sparc_g0, ins->dreg);
2360 #endif
2361                         break;
2362                 case CEE_LDIND_I4:
2363 #ifdef SPARCV9
2364                         sparc_ldsw (code, ins->inst_c0, sparc_g0, ins->dreg);
2365 #else
2366                         sparc_ld (code, ins->inst_c0, sparc_g0, ins->dreg);
2367 #endif
2368                         break;
2369                 case CEE_LDIND_U4:
2370                         sparc_ld (code, ins->inst_c0, sparc_g0, ins->dreg);
2371                         break;
2372                 case OP_LOADU4_MEM:
2373                         sparc_set (code, ins->inst_c0, ins->dreg);
2374                         sparc_ld (code, ins->dreg, sparc_g0, ins->dreg);
2375                         break;
2376                 case OP_LOADI4_MEMBASE:
2377 #ifdef SPARCV9
2378                         EMIT_LOAD_MEMBASE (ins, ldsw);
2379 #else
2380                         EMIT_LOAD_MEMBASE (ins, ld);
2381 #endif
2382                         break;
2383                 case OP_LOADU4_MEMBASE:
2384                         EMIT_LOAD_MEMBASE (ins, ld);
2385                         break;
2386                 case OP_LOADU1_MEMBASE:
2387                         EMIT_LOAD_MEMBASE (ins, ldub);
2388                         break;
2389                 case OP_LOADI1_MEMBASE:
2390                         EMIT_LOAD_MEMBASE (ins, ldsb);
2391                         break;
2392                 case OP_LOADU2_MEMBASE:
2393                         EMIT_LOAD_MEMBASE (ins, lduh);
2394                         break;
2395                 case OP_LOADI2_MEMBASE:
2396                         EMIT_LOAD_MEMBASE (ins, ldsh);
2397                         break;
2398                 case OP_LOAD_MEMBASE:
2399 #ifdef SPARCV9
2400                                 EMIT_LOAD_MEMBASE (ins, ldx);
2401 #else
2402                                 EMIT_LOAD_MEMBASE (ins, ld);
2403 #endif
2404                         break;
2405 #ifdef SPARCV9
2406                 case OP_LOADI8_MEMBASE:
2407                         EMIT_LOAD_MEMBASE (ins, ldx);
2408                         break;
2409 #endif
2410                 case CEE_CONV_I1:
2411                         sparc_sll_imm (code, ins->sreg1, 24, sparc_o7);
2412                         sparc_sra_imm (code, sparc_o7, 24, ins->dreg);
2413                         break;
2414                 case CEE_CONV_I2:
2415                         sparc_sll_imm (code, ins->sreg1, 16, sparc_o7);
2416                         sparc_sra_imm (code, sparc_o7, 16, ins->dreg);
2417                         break;
2418                 case CEE_CONV_U1:
2419                         sparc_and_imm (code, FALSE, ins->sreg1, 0xff, ins->dreg);
2420                         break;
2421                 case CEE_CONV_U2:
2422                         sparc_sll_imm (code, ins->sreg1, 16, sparc_o7);
2423                         sparc_srl_imm (code, sparc_o7, 16, ins->dreg);
2424                         break;
2425                 case CEE_CONV_OVF_U4:
2426                         /* Only used on V9 */
2427                         sparc_cmp_imm (code, ins->sreg1, 0);
2428                         mono_add_patch_info (cfg, (guint8*)(code) - (cfg)->native_code,
2429                                                                  MONO_PATCH_INFO_EXC, "OverflowException");
2430                         sparc_branchp (code, 0, sparc_bl, sparc_xcc_short, 0, 0);
2431                         /* Delay slot */
2432                         sparc_set (code, 1, sparc_o7);
2433                         sparc_sllx_imm (code, sparc_o7, 32, sparc_o7);
2434                         sparc_cmp (code, ins->sreg1, sparc_o7);
2435                         mono_add_patch_info (cfg, (guint8*)(code) - (cfg)->native_code,
2436                                                                  MONO_PATCH_INFO_EXC, "OverflowException");
2437                         sparc_branchp (code, 0, sparc_bge, sparc_xcc_short, 0, 0);
2438                         sparc_nop (code);
2439                         sparc_mov_reg_reg (code, ins->sreg1, ins->dreg);
2440                         break;
2441                 case CEE_CONV_OVF_I4_UN:
2442                         /* Only used on V9 */
2443                         NOT_IMPLEMENTED;
2444                         break;
2445                 case CEE_CONV_U:
2446                 case CEE_CONV_U8:
2447                         /* Only used on V9 */
2448                         sparc_srl_imm (code, ins->sreg1, 0, ins->dreg);
2449                         break;
2450                 case CEE_CONV_I:
2451                 case CEE_CONV_I8:
2452                         /* Only used on V9 */
2453                         sparc_sra_imm (code, ins->sreg1, 0, ins->dreg);
2454                         break;
2455                 case OP_COMPARE:
2456                 case OP_LCOMPARE:
2457                 case OP_ICOMPARE:
2458                         sparc_cmp (code, ins->sreg1, ins->sreg2);
2459                         break;
2460                 case OP_COMPARE_IMM:
2461                 case OP_ICOMPARE_IMM:
2462                         if (sparc_is_imm13 (ins->inst_imm))
2463                                 sparc_cmp_imm (code, ins->sreg1, ins->inst_imm);
2464                         else {
2465                                 sparc_set (code, ins->inst_imm, sparc_o7);
2466                                 sparc_cmp (code, ins->sreg1, sparc_o7);
2467                         }
2468                         break;
2469                 case CEE_BREAK:
2470                         /*
2471                          * gdb does not like encountering 'ta 1' in the debugged code. So
2472                          * instead of emitting a trap, we emit a call a C function and place a
2473                          * breakpoint there.
2474                          */
2475                         //sparc_ta (code, 1);
2476                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, mono_arch_break);
2477                         EMIT_CALL();
2478                         break;
2479                 case OP_ADDCC:
2480                 case OP_IADDCC:
2481                         sparc_add (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
2482                         break;
2483                 case CEE_ADD:
2484                 case OP_IADD:
2485                         sparc_add (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
2486                         break;
2487                 case OP_ADDCC_IMM:
2488                 case OP_ADD_IMM:
2489                 case OP_IADD_IMM:
2490                         /* according to inssel-long32.brg, this should set cc */
2491                         EMIT_ALU_IMM (ins, add, TRUE);
2492                         break;
2493                 case OP_ADC:
2494                 case OP_IADC:
2495                         /* according to inssel-long32.brg, this should set cc */
2496                         sparc_addx (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
2497                         break;
2498                 case OP_ADC_IMM:
2499                 case OP_IADC_IMM:
2500                         EMIT_ALU_IMM (ins, addx, TRUE);
2501                         break;
2502                 case OP_SUBCC:
2503                 case OP_ISUBCC:
2504                         sparc_sub (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
2505                         break;
2506                 case CEE_SUB:
2507                 case OP_ISUB:
2508                         sparc_sub (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
2509                         break;
2510                 case OP_SUBCC_IMM:
2511                 case OP_SUB_IMM:
2512                 case OP_ISUB_IMM:
2513                         /* according to inssel-long32.brg, this should set cc */
2514                         EMIT_ALU_IMM (ins, sub, TRUE);
2515                         break;
2516                 case OP_SBB:
2517                 case OP_ISBB:
2518                         /* according to inssel-long32.brg, this should set cc */
2519                         sparc_subx (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
2520                         break;
2521                 case OP_SBB_IMM:
2522                 case OP_ISBB_IMM:
2523                         EMIT_ALU_IMM (ins, subx, TRUE);
2524                         break;
2525                 case CEE_AND:
2526                 case OP_IAND:
2527                         sparc_and (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
2528                         break;
2529                 case OP_AND_IMM:
2530                 case OP_IAND_IMM:
2531                         EMIT_ALU_IMM (ins, and, FALSE);
2532                         break;
2533                 case CEE_DIV:
2534                 case OP_IDIV:
2535                         /* Sign extend sreg1 into %y */
2536                         sparc_sra_imm (code, ins->sreg1, 31, sparc_o7);
2537                         sparc_wry (code, sparc_o7, sparc_g0);
2538                         sparc_sdiv (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
2539                         EMIT_COND_SYSTEM_EXCEPTION_GENERAL (code, sparc_boverflow, "ArithmeticException", TRUE, sparc_icc_short);
2540                         break;
2541                 case CEE_DIV_UN:
2542                 case OP_IDIV_UN:
2543                         sparc_wry (code, sparc_g0, sparc_g0);
2544                         sparc_udiv (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
2545                         break;
2546                 case OP_DIV_IMM: {
2547                         int i, imm;
2548
2549                         /* Transform division into a shift */
2550                         for (i = 1; i < 30; ++i) {
2551                                 imm = (1 << i);
2552                                 if (ins->inst_imm == imm)
2553                                         break;
2554                         }
2555                         if (i < 30) {
2556                                 if (i == 1) {
2557                                         /* gcc 2.95.3 */
2558                                         sparc_srl_imm (code, ins->sreg1, 31, sparc_o7);
2559                                         sparc_add (code, FALSE, ins->sreg1, sparc_o7, ins->dreg);
2560                                         sparc_sra_imm (code, ins->dreg, 1, ins->dreg);
2561                                 }
2562                                 else {
2563                                         /* http://compilers.iecc.com/comparch/article/93-04-079 */
2564                                         sparc_sra_imm (code, ins->sreg1, 31, sparc_o7);
2565                                         sparc_srl_imm (code, sparc_o7, 32 - i, sparc_o7);
2566                                         sparc_add (code, FALSE, ins->sreg1, sparc_o7, ins->dreg);
2567                                         sparc_sra_imm (code, ins->dreg, i, ins->dreg);
2568                                 }
2569                         }
2570                         else {
2571                                 /* Sign extend sreg1 into %y */
2572                                 sparc_sra_imm (code, ins->sreg1, 31, sparc_o7);
2573                                 sparc_wry (code, sparc_o7, sparc_g0);
2574                                 EMIT_ALU_IMM (ins, sdiv, TRUE);
2575                                 EMIT_COND_SYSTEM_EXCEPTION_GENERAL (code, sparc_boverflow, "ArithmeticException", TRUE, sparc_icc_short);
2576                         }
2577                         break;
2578                 }
2579                 case CEE_REM:
2580                 case OP_IREM:
2581                         /* Sign extend sreg1 into %y */
2582                         sparc_sra_imm (code, ins->sreg1, 31, sparc_o7);
2583                         sparc_wry (code, sparc_o7, sparc_g0);
2584                         sparc_sdiv (code, TRUE, ins->sreg1, ins->sreg2, sparc_o7);
2585                         EMIT_COND_SYSTEM_EXCEPTION_GENERAL (code, sparc_boverflow, "ArithmeticException", TRUE, sparc_icc_short);
2586                         sparc_smul (code, FALSE, ins->sreg2, sparc_o7, sparc_o7);
2587                         sparc_sub (code, FALSE, ins->sreg1, sparc_o7, ins->dreg);
2588                         break;
2589                 case CEE_REM_UN:
2590                 case OP_IREM_UN:
2591                         sparc_wry (code, sparc_g0, sparc_g0);
2592                         sparc_udiv (code, FALSE, ins->sreg1, ins->sreg2, sparc_o7);
2593                         sparc_umul (code, FALSE, ins->sreg2, sparc_o7, sparc_o7);
2594                         sparc_sub (code, FALSE, ins->sreg1, sparc_o7, ins->dreg);
2595                         break;
2596                 case OP_REM_IMM:
2597                 case OP_IREM_IMM:
2598                         /* Sign extend sreg1 into %y */
2599                         sparc_sra_imm (code, ins->sreg1, 31, sparc_o7);
2600                         sparc_wry (code, sparc_o7, sparc_g0);
2601                         if (!sparc_is_imm13 (ins->inst_imm)) {
2602                                 sparc_set (code, ins->inst_imm, GP_SCRATCH_REG);
2603                                 sparc_sdiv (code, TRUE, ins->sreg1, GP_SCRATCH_REG, sparc_o7);
2604                                 EMIT_COND_SYSTEM_EXCEPTION_GENERAL (code, sparc_boverflow, "ArithmeticException", TRUE, sparc_icc_short);
2605                                 sparc_smul (code, FALSE, sparc_o7, GP_SCRATCH_REG, sparc_o7);
2606                         }
2607                         else {
2608                                 sparc_sdiv_imm (code, TRUE, ins->sreg1, ins->inst_imm, sparc_o7);
2609                                 EMIT_COND_SYSTEM_EXCEPTION_GENERAL (code, sparc_boverflow, "ArithmeticException", TRUE, sparc_icc_short);
2610                                 sparc_smul_imm (code, FALSE, sparc_o7, ins->inst_imm, sparc_o7);
2611                         }
2612                         sparc_sub (code, FALSE, ins->sreg1, sparc_o7, ins->dreg);
2613                         break;
2614                 case CEE_OR:
2615                 case OP_IOR:
2616                         sparc_or (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
2617                         break;
2618                 case OP_OR_IMM:
2619                 case OP_IOR_IMM:
2620                         EMIT_ALU_IMM (ins, or, FALSE);
2621                         break;
2622                 case CEE_XOR:
2623                 case OP_IXOR:
2624                         sparc_xor (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
2625                         break;
2626                 case OP_XOR_IMM:
2627                 case OP_IXOR_IMM:
2628                         EMIT_ALU_IMM (ins, xor, FALSE);
2629                         break;
2630                 case CEE_SHL:
2631                 case OP_ISHL:
2632                         sparc_sll (code, ins->sreg1, ins->sreg2, ins->dreg);
2633                         break;
2634                 case OP_SHL_IMM:
2635                 case OP_ISHL_IMM:
2636                         if (ins->inst_imm < (1 << 5))
2637                                 sparc_sll_imm (code, ins->sreg1, ins->inst_imm, ins->dreg);
2638                         else {
2639                                 sparc_set (code, ins->inst_imm, sparc_o7);
2640                                 sparc_sll (code, ins->sreg1, sparc_o7, ins->dreg);
2641                         }
2642                         break;
2643                 case CEE_SHR:
2644                 case OP_ISHR:
2645                         sparc_sra (code, ins->sreg1, ins->sreg2, ins->dreg);
2646                         break;
2647                 case OP_ISHR_IMM:
2648                 case OP_SHR_IMM:
2649                         if (ins->inst_imm < (1 << 5))
2650                                 sparc_sra_imm (code, ins->sreg1, ins->inst_imm, ins->dreg);
2651                         else {
2652                                 sparc_set (code, ins->inst_imm, sparc_o7);
2653                                 sparc_sra (code, ins->sreg1, sparc_o7, ins->dreg);
2654                         }
2655                         break;
2656                 case OP_SHR_UN_IMM:
2657                 case OP_ISHR_UN_IMM:
2658                         if (ins->inst_imm < (1 << 5))
2659                                 sparc_srl_imm (code, ins->sreg1, ins->inst_imm, ins->dreg);
2660                         else {
2661                                 sparc_set (code, ins->inst_imm, sparc_o7);
2662                                 sparc_srl (code, ins->sreg1, sparc_o7, ins->dreg);
2663                         }
2664                         break;
2665                 case CEE_SHR_UN:
2666                 case OP_ISHR_UN:
2667                         sparc_srl (code, ins->sreg1, ins->sreg2, ins->dreg);
2668                         break;
2669                 case OP_LSHL:
2670                         sparc_sllx (code, ins->sreg1, ins->sreg2, ins->dreg);
2671                         break;
2672                 case OP_LSHL_IMM:
2673                         if (ins->inst_imm < (1 << 6))
2674                                 sparc_sllx_imm (code, ins->sreg1, ins->inst_imm, ins->dreg);
2675                         else {
2676                                 sparc_set (code, ins->inst_imm, sparc_o7);
2677                                 sparc_sllx (code, ins->sreg1, sparc_o7, ins->dreg);
2678                         }
2679                         break;
2680                 case OP_LSHR:
2681                         sparc_srax (code, ins->sreg1, ins->sreg2, ins->dreg);
2682                         break;
2683                 case OP_LSHR_IMM:
2684                         if (ins->inst_imm < (1 << 6))
2685                                 sparc_srax_imm (code, ins->sreg1, ins->inst_imm, ins->dreg);
2686                         else {
2687                                 sparc_set (code, ins->inst_imm, sparc_o7);
2688                                 sparc_srax (code, ins->sreg1, sparc_o7, ins->dreg);
2689                         }
2690                         break;
2691                 case OP_LSHR_UN:
2692                         sparc_srlx (code, ins->sreg1, ins->sreg2, ins->dreg);
2693                         break;
2694                 case OP_LSHR_UN_IMM:
2695                         if (ins->inst_imm < (1 << 6))
2696                                 sparc_srlx_imm (code, ins->sreg1, ins->inst_imm, ins->dreg);
2697                         else {
2698                                 sparc_set (code, ins->inst_imm, sparc_o7);
2699                                 sparc_srlx (code, ins->sreg1, sparc_o7, ins->dreg);
2700                         }
2701                         break;
2702                 case CEE_NOT:
2703                 case OP_INOT:
2704                         /* can't use sparc_not */
2705                         sparc_xnor (code, FALSE, ins->sreg1, sparc_g0, ins->dreg);
2706                         break;
2707                 case CEE_NEG:
2708                 case OP_INEG:
2709                         /* can't use sparc_neg */
2710                         sparc_sub (code, FALSE, sparc_g0, ins->sreg1, ins->dreg);
2711                         break;
2712                 case CEE_MUL:
2713                 case OP_IMUL:
2714                         sparc_smul (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
2715                         break;
2716                 case OP_IMUL_IMM:
2717                 case OP_MUL_IMM: {
2718                         int i, imm;
2719
2720                         if ((ins->inst_imm == 1) && (ins->sreg1 == ins->dreg))
2721                                 break;
2722
2723                         /* Transform multiplication into a shift */
2724                         for (i = 0; i < 30; ++i) {
2725                                 imm = (1 << i);
2726                                 if (ins->inst_imm == imm)
2727                                         break;
2728                         }
2729                         if (i < 30)
2730                                 sparc_sll_imm (code, ins->sreg1, i, ins->dreg);
2731                         else
2732                                 EMIT_ALU_IMM (ins, smul, FALSE);
2733                         break;
2734                 }
2735                 case CEE_MUL_OVF:
2736                 case OP_IMUL_OVF:
2737                         sparc_smul (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
2738                         sparc_rdy (code, sparc_g1);
2739                         sparc_sra_imm (code, ins->dreg, 31, sparc_o7);
2740                         sparc_cmp (code, sparc_g1, sparc_o7);
2741                         EMIT_COND_SYSTEM_EXCEPTION_GENERAL (ins, sparc_bne, "OverflowException", TRUE, sparc_icc_short);
2742                         break;
2743                 case CEE_MUL_OVF_UN:
2744                 case OP_IMUL_OVF_UN:
2745                         sparc_umul (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
2746                         sparc_rdy (code, sparc_o7);
2747                         sparc_cmp (code, sparc_o7, sparc_g0);
2748                         EMIT_COND_SYSTEM_EXCEPTION_GENERAL (ins, sparc_bne, "OverflowException", TRUE, sparc_icc_short);
2749                         break;
2750                 case OP_ICONST:
2751                 case OP_SETREGIMM:
2752                         sparc_set (code, ins->inst_c0, ins->dreg);
2753                         break;
2754                 case OP_I8CONST:
2755                         sparc_set (code, ins->inst_l, ins->dreg);
2756                         break;
2757                 case OP_AOTCONST:
2758                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2759                         sparc_set_template (code, ins->dreg);
2760                         break;
2761                 case CEE_CONV_I4:
2762                 case CEE_CONV_U4:
2763                 case OP_MOVE:
2764                 case OP_SETREG:
2765                         if (ins->sreg1 != ins->dreg)
2766                                 sparc_mov_reg_reg (code, ins->sreg1, ins->dreg);
2767                         break;
2768                 case OP_SETFREG:
2769                         /* Only used on V9 */
2770                         if (ins->sreg1 != ins->dreg)
2771                                 sparc_fmovd (code, ins->sreg1, ins->dreg);
2772                         break;
2773                 case OP_SPARC_SETFREG_FLOAT:
2774                         /* Only used on V9 */
2775                         sparc_fdtos (code, ins->sreg1, ins->dreg);
2776                         break;
2777                 case CEE_JMP:
2778                         if (cfg->method->save_lmf)
2779                                 NOT_IMPLEMENTED;
2780
2781                         code = emit_load_volatile_arguments (cfg, code);
2782                         mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2783                         sparc_set_template (code, sparc_o7);
2784                         sparc_jmpl (code, sparc_o7, sparc_g0, sparc_g0);
2785                         /* Restore parent frame in delay slot */
2786                         sparc_restore_imm (code, sparc_g0, 0, sparc_g0);
2787                         break;
2788                 case OP_CHECK_THIS:
2789                         /* ensure ins->sreg1 is not NULL */
2790                         sparc_ld_imm (code, ins->sreg1, 0, sparc_g0);
2791                         break;
2792                 case OP_ARGLIST:
2793                         sparc_add_imm (code, FALSE, sparc_fp, cfg->sig_cookie, sparc_o7);
2794                         sparc_sti_imm (code, sparc_o7, ins->sreg1, 0);
2795                         break;
2796                 case OP_FCALL:
2797                 case OP_LCALL:
2798                 case OP_VCALL:
2799                 case OP_VOIDCALL:
2800                 case CEE_CALL:
2801                         call = (MonoCallInst*)ins;
2802                         g_assert (!call->virtual);
2803                         code = emit_save_sp_to_lmf (cfg, code);
2804                         if (ins->flags & MONO_INST_HAS_METHOD)
2805                             code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2806                         else
2807                             code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2808
2809                         code = emit_vret_token (ins, code);
2810                         code = emit_move_return_value (ins, code);
2811                         break;
2812                 case OP_FCALL_REG:
2813                 case OP_LCALL_REG:
2814                 case OP_VCALL_REG:
2815                 case OP_VOIDCALL_REG:
2816                 case OP_CALL_REG:
2817                         call = (MonoCallInst*)ins;
2818                         code = emit_save_sp_to_lmf (cfg, code);
2819                         sparc_jmpl (code, ins->sreg1, sparc_g0, sparc_callsite);
2820                         /*
2821                          * We emit a special kind of nop in the delay slot to tell the
2822                          * trampoline code that this is a virtual call, thus an unbox
2823                          * trampoline might need to be called.
2824                          */
2825                         if (call->virtual)
2826                                 sparc_or_imm (code, FALSE, sparc_g0, 0xca, sparc_g0);
2827                         else
2828                                 sparc_nop (code);
2829
2830                         code = emit_vret_token (ins, code);
2831                         code = emit_move_return_value (ins, code);
2832                         break;
2833                 case OP_FCALL_MEMBASE:
2834                 case OP_LCALL_MEMBASE:
2835                 case OP_VCALL_MEMBASE:
2836                 case OP_VOIDCALL_MEMBASE:
2837                 case OP_CALL_MEMBASE:
2838                         call = (MonoCallInst*)ins;
2839                         code = emit_save_sp_to_lmf (cfg, code);
2840                         if (sparc_is_imm13 (ins->inst_offset)) {
2841                                 sparc_ldi_imm (code, ins->inst_basereg, ins->inst_offset, sparc_o7);
2842                         } else {
2843                                 sparc_set (code, ins->inst_offset, sparc_o7);
2844                                 sparc_ldi (code, ins->inst_basereg, sparc_o7, sparc_o7);
2845                         }
2846                         sparc_jmpl (code, sparc_o7, sparc_g0, sparc_callsite);
2847                         if (call->virtual)
2848                                 sparc_or_imm (code, FALSE, sparc_g0, 0xca, sparc_g0);
2849                         else
2850                                 sparc_nop (code);
2851
2852                         code = emit_vret_token (ins, code);
2853                         code = emit_move_return_value (ins, code);
2854                         break;
2855                 case OP_SETFRET:
2856                         if (mono_method_signature (cfg->method)->ret->type == MONO_TYPE_R4)
2857                                 sparc_fdtos (code, ins->sreg1, sparc_f0);
2858                         else {
2859 #ifdef SPARCV9
2860                                 sparc_fmovd (code, ins->sreg1, ins->dreg);
2861 #else
2862                                 /* FIXME: Why not use fmovd ? */
2863                                 sparc_fmovs (code, ins->sreg1, ins->dreg);
2864                                 sparc_fmovs (code, ins->sreg1 + 1, ins->dreg + 1);
2865 #endif
2866                         }
2867                         break;
2868                 case OP_OUTARG:
2869                         g_assert_not_reached ();
2870                         break;
2871                 case OP_LOCALLOC: {
2872                         guint32 size_reg;
2873
2874 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
2875                         /* Perform stack touching */
2876                         NOT_IMPLEMENTED;
2877 #endif
2878
2879                         /* Keep alignment */
2880                         sparc_add_imm (code, FALSE, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1, ins->dreg);
2881                         sparc_set (code, ~(MONO_ARCH_FRAME_ALIGNMENT - 1), sparc_o7);
2882                         sparc_and (code, FALSE, ins->dreg, sparc_o7, ins->dreg);
2883
2884                         if ((ins->flags & MONO_INST_INIT) && (ins->sreg1 == ins->dreg)) {
2885 #ifdef SPARCV9
2886                                 size_reg = sparc_g4;
2887 #else
2888                                 size_reg = sparc_g1;
2889 #endif
2890                                 sparc_mov_reg_reg (code, ins->dreg, size_reg);
2891                         }
2892                         else
2893                                 size_reg = ins->sreg1;
2894
2895                         sparc_sub (code, FALSE, sparc_sp, ins->dreg, ins->dreg);
2896                         /* Keep %sp valid at all times */
2897                         sparc_mov_reg_reg (code, ins->dreg, sparc_sp);
2898                         g_assert (sparc_is_imm13 (MONO_SPARC_STACK_BIAS + cfg->arch.localloc_offset));
2899                         sparc_add_imm (code, FALSE, ins->dreg, MONO_SPARC_STACK_BIAS + cfg->arch.localloc_offset, ins->dreg);
2900
2901                         if (ins->flags & MONO_INST_INIT) {
2902                                 guint32 *br [3];
2903                                 /* Initialize memory region */
2904                                 sparc_cmp_imm (code, size_reg, 0);
2905                                 br [0] = code;
2906                                 sparc_branch (code, 0, sparc_be, 0);
2907                                 /* delay slot */
2908                                 sparc_set (code, 0, sparc_o7);
2909                                 sparc_sub_imm (code, 0, size_reg, sparcv9 ? 8 : 4, size_reg);
2910                                 /* start of loop */
2911                                 br [1] = code;
2912                                 if (sparcv9)
2913                                         sparc_stx (code, sparc_g0, ins->dreg, sparc_o7);
2914                                 else
2915                                         sparc_st (code, sparc_g0, ins->dreg, sparc_o7);
2916                                 sparc_cmp (code, sparc_o7, size_reg);
2917                                 br [2] = code;
2918                                 sparc_branch (code, 0, sparc_bl, 0);
2919                                 sparc_patch (br [2], br [1]);
2920                                 /* delay slot */
2921                                 sparc_add_imm (code, 0, sparc_o7, sparcv9 ? 8 : 4, sparc_o7);
2922                                 sparc_patch (br [0], code);
2923                         }
2924                         break;
2925                 }
2926                 case OP_SPARC_LOCALLOC_IMM: {
2927                         gint32 offset = ins->inst_c0;
2928
2929 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
2930                         /* Perform stack touching */
2931                         NOT_IMPLEMENTED;
2932 #endif
2933
2934                         offset = ALIGN_TO (offset, MONO_ARCH_FRAME_ALIGNMENT);
2935                         if (sparc_is_imm13 (offset))
2936                                 sparc_sub_imm (code, FALSE, sparc_sp, offset, sparc_sp);
2937                         else {
2938                                 sparc_set (code, offset, sparc_o7);
2939                                 sparc_sub (code, FALSE, sparc_sp, sparc_o7, sparc_sp);
2940                         }
2941                         g_assert (sparc_is_imm13 (MONO_SPARC_STACK_BIAS + cfg->arch.localloc_offset));
2942                         sparc_add_imm (code, FALSE, sparc_sp, MONO_SPARC_STACK_BIAS + cfg->arch.localloc_offset, ins->dreg);
2943                         if ((ins->flags & MONO_INST_INIT) && (offset > 0)) {
2944                                 guint32 *br [2];
2945                                 int i;
2946
2947                                 if (offset <= 16) {
2948                                         i = 0;
2949                                         while (i < offset) {
2950                                                 if (sparcv9) {
2951                                                         sparc_stx_imm (code, sparc_g0, ins->dreg, i);
2952                                                         i += 8;
2953                                                 }
2954                                                 else {
2955                                                         sparc_st_imm (code, sparc_g0, ins->dreg, i);
2956                                                         i += 4;
2957                                                 }
2958                                         }
2959                                 }
2960                                 else {
2961                                         sparc_set (code, offset, sparc_o7);
2962                                         sparc_sub_imm (code, 0, sparc_o7, sparcv9 ? 8 : 4, sparc_o7);
2963                                         /* beginning of loop */
2964                                         br [0] = code;
2965                                         if (sparcv9)
2966                                                 sparc_stx (code, sparc_g0, ins->dreg, sparc_o7);
2967                                         else
2968                                                 sparc_st (code, sparc_g0, ins->dreg, sparc_o7);
2969                                         sparc_cmp_imm (code, sparc_o7, 0);
2970                                         br [1] = code;
2971                                         sparc_branch (code, 0, sparc_bne, 0);
2972                                         /* delay slot */
2973                                         sparc_sub_imm (code, 0, sparc_o7, sparcv9 ? 8 : 4, sparc_o7);
2974                                         sparc_patch (br [1], br [0]);
2975                                 }
2976                         }
2977                         break;
2978                 }
2979                 case CEE_RET:
2980                         /* The return is done in the epilog */
2981                         g_assert_not_reached ();
2982                         break;
2983                 case CEE_THROW:
2984                         sparc_mov_reg_reg (code, ins->sreg1, sparc_o0);
2985                         mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2986                                              (gpointer)"mono_arch_throw_exception");
2987                         EMIT_CALL ();
2988                         break;
2989                 case OP_RETHROW:
2990                         sparc_mov_reg_reg (code, ins->sreg1, sparc_o0);
2991                         mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
2992                                              (gpointer)"mono_arch_rethrow_exception");
2993                         EMIT_CALL ();
2994                         break;
2995                 case OP_START_HANDLER: {
2996                         /*
2997                          * The START_HANDLER instruction marks the beginning of a handler
2998                          * block. It is called using a call instruction, so %o7 contains
2999                          * the return address. Since the handler executes in the same stack
3000              * frame as the method itself, we can't use save/restore to save
3001                          * the return address. Instead, we save it into a dedicated
3002                          * variable.
3003                          */
3004                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3005                         if (!sparc_is_imm13 (spvar->inst_offset)) {
3006                                 sparc_set (code, spvar->inst_offset, GP_SCRATCH_REG);
3007                                 sparc_sti (code, sparc_o7, spvar->inst_basereg, GP_SCRATCH_REG);
3008                         }
3009                         else
3010                                 sparc_sti_imm (code, sparc_o7, spvar->inst_basereg, spvar->inst_offset);
3011                         break;
3012                 }
3013                 case OP_ENDFILTER: {
3014                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3015                         if (!sparc_is_imm13 (spvar->inst_offset)) {
3016                                 sparc_set (code, spvar->inst_offset, GP_SCRATCH_REG);
3017                                 sparc_ldi (code, spvar->inst_basereg, GP_SCRATCH_REG, sparc_o7);
3018                         }
3019                         else
3020                                 sparc_ldi_imm (code, spvar->inst_basereg, spvar->inst_offset, sparc_o7);
3021                         sparc_jmpl_imm (code, sparc_o7, 8, sparc_g0);
3022                         /* Delay slot */
3023                         sparc_mov_reg_reg (code, ins->sreg1, sparc_o0);
3024                         break;
3025                 }
3026                 case CEE_ENDFINALLY: {
3027                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3028                         if (!sparc_is_imm13 (spvar->inst_offset)) {
3029                                 sparc_set (code, spvar->inst_offset, GP_SCRATCH_REG);
3030                                 sparc_ldi (code, spvar->inst_basereg, GP_SCRATCH_REG, sparc_o7);
3031                         }
3032                         else
3033                                 sparc_ldi_imm (code, spvar->inst_basereg, spvar->inst_offset, sparc_o7);
3034                         sparc_jmpl_imm (code, sparc_o7, 8, sparc_g0);
3035                         sparc_nop (code);
3036                         break;
3037                 }
3038                 case OP_CALL_HANDLER:
3039                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3040                         /* This is a jump inside the method, so call_simple works even on V9 */
3041                         sparc_call_simple (code, 0);
3042                         sparc_nop (code);
3043                         break;
3044                 case OP_LABEL:
3045                         ins->inst_c0 = (guint8*)code - cfg->native_code;
3046                         break;
3047                 case CEE_BR:
3048                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3049                         if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3050                                 break;
3051                         if (ins->flags & MONO_INST_BRLABEL) {
3052                                 if (ins->inst_i0->inst_c0) {
3053                                         gint32 disp = (ins->inst_i0->inst_c0 - ((guint8*)code - cfg->native_code)) >> 2;
3054                                         g_assert (sparc_is_imm22 (disp));
3055                                         sparc_branch (code, 1, sparc_ba, disp);
3056                                 } else {
3057                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3058                                         sparc_branch (code, 1, sparc_ba, 0);
3059                                 }
3060                         } else {
3061                                 if (ins->inst_target_bb->native_offset) {
3062                                         gint32 disp = (ins->inst_target_bb->native_offset - ((guint8*)code - cfg->native_code)) >> 2;
3063                                         g_assert (sparc_is_imm22 (disp));
3064                                         sparc_branch (code, 1, sparc_ba, disp);
3065                                 } else {
3066                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3067                                         sparc_branch (code, 1, sparc_ba, 0);
3068                                 }
3069                         }
3070                         sparc_nop (code);
3071                         break;
3072                 case OP_BR_REG:
3073                         sparc_jmp (code, ins->sreg1, sparc_g0);
3074                         sparc_nop (code);
3075                         break;
3076                 case OP_CEQ:
3077                 case OP_CLT:
3078                 case OP_CLT_UN:
3079                 case OP_CGT:
3080                 case OP_CGT_UN:
3081                         if (v64 && (cfg->opt & MONO_OPT_CMOV)) {
3082                                 sparc_clr_reg (code, ins->dreg);
3083                                 sparc_movcc_imm (code, sparc_xcc, opcode_to_sparc_cond (ins->opcode), 1, ins->dreg);
3084                         }
3085                         else {
3086                                 sparc_clr_reg (code, ins->dreg);
3087 #ifdef SPARCV9
3088                                 sparc_branchp (code, 1, opcode_to_sparc_cond (ins->opcode), DEFAULT_ICC, 0, 2);
3089 #else
3090                                 sparc_branch (code, 1, opcode_to_sparc_cond (ins->opcode), 2);
3091 #endif
3092                                 /* delay slot */
3093                                 sparc_set (code, 1, ins->dreg);
3094                         }
3095                         break;
3096                 case OP_ICEQ:
3097                 case OP_ICLT:
3098                 case OP_ICLT_UN:
3099                 case OP_ICGT:
3100                 case OP_ICGT_UN:
3101                     if (v64 && (cfg->opt & MONO_OPT_CMOV)) {
3102                                 sparc_clr_reg (code, ins->dreg);
3103                                 sparc_movcc_imm (code, sparc_icc, opcode_to_sparc_cond (ins->opcode), 1, ins->dreg);
3104                     }
3105                     else {
3106                         sparc_clr_reg (code, ins->dreg);
3107                         sparc_branchp (code, 1, opcode_to_sparc_cond (ins->opcode), sparc_icc_short, 0, 2);
3108                         /* delay slot */
3109                         sparc_set (code, 1, ins->dreg);
3110                     }
3111                     break;
3112                 case OP_COND_EXC_EQ:
3113                 case OP_COND_EXC_NE_UN:
3114                 case OP_COND_EXC_LT:
3115                 case OP_COND_EXC_LT_UN:
3116                 case OP_COND_EXC_GT:
3117                 case OP_COND_EXC_GT_UN:
3118                 case OP_COND_EXC_GE:
3119                 case OP_COND_EXC_GE_UN:
3120                 case OP_COND_EXC_LE:
3121                 case OP_COND_EXC_LE_UN:
3122                 case OP_COND_EXC_OV:
3123                 case OP_COND_EXC_NO:
3124                 case OP_COND_EXC_C:
3125                 case OP_COND_EXC_NC:
3126                         EMIT_COND_SYSTEM_EXCEPTION (ins, opcode_to_sparc_cond (ins->opcode), ins->inst_p1);
3127                         break;
3128                 case OP_SPARC_COND_EXC_EQZ:
3129                         EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brz, ins->inst_p1);
3130                         break;
3131                 case OP_SPARC_COND_EXC_GEZ:
3132                         EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brgez, ins->inst_p1);
3133                         break;
3134                 case OP_SPARC_COND_EXC_GTZ:
3135                         EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brgz, ins->inst_p1);
3136                         break;
3137                 case OP_SPARC_COND_EXC_LEZ:
3138                         EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brlez, ins->inst_p1);
3139                         break;
3140                 case OP_SPARC_COND_EXC_LTZ:
3141                         EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brlz, ins->inst_p1);
3142                         break;
3143                 case OP_SPARC_COND_EXC_NEZ:
3144                         EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brnz, ins->inst_p1);
3145                         break;
3146                 case OP_COND_EXC_IOV:
3147                 case OP_COND_EXC_IC:
3148                         EMIT_COND_SYSTEM_EXCEPTION_GENERAL (ins, opcode_to_sparc_cond (ins->opcode), ins->inst_p1, TRUE, sparc_icc_short);
3149                         break;
3150                 case CEE_BEQ:
3151                 case CEE_BNE_UN:
3152                 case CEE_BLT:
3153                 case CEE_BLT_UN:
3154                 case CEE_BGT:
3155                 case CEE_BGT_UN:
3156                 case CEE_BGE:
3157                 case CEE_BGE_UN:
3158                 case CEE_BLE:
3159                 case CEE_BLE_UN: {
3160                         if (sparcv9)
3161                                 EMIT_COND_BRANCH_PREDICTED (ins, opcode_to_sparc_cond (ins->opcode), 1, 1);
3162                         else
3163                                 EMIT_COND_BRANCH (ins, opcode_to_sparc_cond (ins->opcode), 1, 1);
3164                         break;
3165                 }
3166
3167                 case OP_IBEQ:
3168                 case OP_IBNE_UN:
3169                 case OP_IBLT:
3170                 case OP_IBLT_UN:
3171                 case OP_IBGT:
3172                 case OP_IBGT_UN:
3173                 case OP_IBGE:
3174                 case OP_IBGE_UN:
3175                 case OP_IBLE:
3176                 case OP_IBLE_UN: {
3177                         /* Only used on V9 */
3178                         EMIT_COND_BRANCH_ICC (ins, opcode_to_sparc_cond (ins->opcode), 1, 1, sparc_icc_short);
3179                         break;
3180                 }
3181
3182                 case OP_SPARC_BRZ:
3183                         EMIT_COND_BRANCH_BPR (ins, brz, 1, 1, 1);
3184                         break;
3185                 case OP_SPARC_BRLEZ:
3186                         EMIT_COND_BRANCH_BPR (ins, brlez, 1, 1, 1);
3187                         break;
3188                 case OP_SPARC_BRLZ:
3189                         EMIT_COND_BRANCH_BPR (ins, brlz, 1, 1, 1);
3190                         break;
3191                 case OP_SPARC_BRNZ:
3192                         EMIT_COND_BRANCH_BPR (ins, brnz, 1, 1, 1);
3193                         break;
3194                 case OP_SPARC_BRGZ:
3195                         EMIT_COND_BRANCH_BPR (ins, brgz, 1, 1, 1);
3196                         break;
3197                 case OP_SPARC_BRGEZ:
3198                         EMIT_COND_BRANCH_BPR (ins, brgez, 1, 1, 1);
3199                         break;
3200
3201                 /* floating point opcodes */
3202                 case OP_R8CONST:
3203                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3204 #ifdef SPARCV9
3205                         sparc_set_template (code, sparc_o7);
3206 #else
3207                         sparc_sethi (code, 0, sparc_o7);
3208 #endif
3209                         sparc_lddf_imm (code, sparc_o7, 0, ins->dreg);
3210                         break;
3211                 case OP_R4CONST:
3212                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3213 #ifdef SPARCV9
3214                         sparc_set_template (code, sparc_o7);
3215 #else
3216                         sparc_sethi (code, 0, sparc_o7);
3217 #endif
3218                         sparc_ldf_imm (code, sparc_o7, 0, FP_SCRATCH_REG);
3219
3220                         /* Extend to double */
3221                         sparc_fstod (code, FP_SCRATCH_REG, ins->dreg);
3222                         break;
3223                 case OP_STORER8_MEMBASE_REG:
3224                         if (!sparc_is_imm13 (ins->inst_offset + 4)) {
3225                                 sparc_set (code, ins->inst_offset, sparc_o7);
3226                                 /* SPARCV9 handles misaligned fp loads/stores */
3227                                 if (!v64 && (ins->inst_offset % 8)) {
3228                                         /* Misaligned */
3229                                         sparc_add (code, FALSE, ins->inst_destbasereg, sparc_o7, sparc_o7);
3230                                         sparc_stf (code, ins->sreg1, sparc_o7, sparc_g0);
3231                                         sparc_stf_imm (code, ins->sreg1 + 1, sparc_o7, 4);
3232                                 } else
3233                                         sparc_stdf (code, ins->sreg1, ins->inst_destbasereg, sparc_o7);
3234                         }
3235                         else {
3236                                 if (!v64 && (ins->inst_offset % 8)) {
3237                                         /* Misaligned */
3238                                         sparc_stf_imm (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3239                                         sparc_stf_imm (code, ins->sreg1 + 1, ins->inst_destbasereg, ins->inst_offset + 4);
3240                                 } else
3241                                         sparc_stdf_imm (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3242                         }
3243                         break;
3244                 case OP_LOADR8_MEMBASE:
3245                         EMIT_LOAD_MEMBASE (ins, lddf);
3246                         break;
3247                 case OP_STORER4_MEMBASE_REG:
3248                         /* This requires a double->single conversion */
3249                         sparc_fdtos (code, ins->sreg1, FP_SCRATCH_REG);
3250                         if (!sparc_is_imm13 (ins->inst_offset)) {
3251                                 sparc_set (code, ins->inst_offset, sparc_o7);
3252                                 sparc_stf (code, FP_SCRATCH_REG, ins->inst_destbasereg, sparc_o7);
3253                         }
3254                         else
3255                                 sparc_stf_imm (code, FP_SCRATCH_REG, ins->inst_destbasereg, ins->inst_offset);
3256                         break;
3257                 case OP_LOADR4_MEMBASE: {
3258                         /* ldf needs a single precision register */
3259                         int dreg = ins->dreg;
3260                         ins->dreg = FP_SCRATCH_REG;
3261                         EMIT_LOAD_MEMBASE (ins, ldf);
3262                         ins->dreg = dreg;
3263                         /* Extend to double */
3264                         sparc_fstod (code, FP_SCRATCH_REG, ins->dreg);
3265                         break;
3266                 }
3267                 case OP_FMOVE:
3268 #ifdef SPARCV9
3269                         sparc_fmovd (code, ins->sreg1, ins->dreg);
3270 #else
3271                         sparc_fmovs (code, ins->sreg1, ins->dreg);
3272                         sparc_fmovs (code, ins->sreg1 + 1, ins->dreg + 1);
3273 #endif
3274                         break;
3275                 case CEE_CONV_R4: {
3276                         gint32 offset = mono_spillvar_offset_float (cfg, 0);
3277 #ifdef SPARCV9
3278                         if (!sparc_is_imm13 (offset)) {
3279                                 sparc_set (code, offset, sparc_o7);
3280                                 sparc_stx (code, ins->sreg1, sparc_sp, offset);
3281                                 sparc_lddf (code, sparc_sp, offset, FP_SCRATCH_REG);
3282                         } else {
3283                                 sparc_stx_imm (code, ins->sreg1, sparc_sp, offset);
3284                                 sparc_lddf_imm (code, sparc_sp, offset, FP_SCRATCH_REG);
3285                         }
3286                         sparc_fxtos (code, FP_SCRATCH_REG, FP_SCRATCH_REG);
3287 #else
3288                         if (!sparc_is_imm13 (offset)) {
3289                                 sparc_set (code, offset, sparc_o7);
3290                                 sparc_st (code, ins->sreg1, sparc_sp, sparc_o7);
3291                                 sparc_ldf (code, sparc_sp, sparc_o7, FP_SCRATCH_REG);
3292                         } else {
3293                                 sparc_st_imm (code, ins->sreg1, sparc_sp, offset);
3294                                 sparc_ldf_imm (code, sparc_sp, offset, FP_SCRATCH_REG);
3295                         }
3296                         sparc_fitos (code, FP_SCRATCH_REG, FP_SCRATCH_REG);
3297 #endif
3298                         sparc_fstod (code, FP_SCRATCH_REG, ins->dreg);
3299                         break;
3300                 }
3301                 case CEE_CONV_R8: {
3302                         gint32 offset = mono_spillvar_offset_float (cfg, 0);
3303 #ifdef SPARCV9
3304                         if (!sparc_is_imm13 (offset)) {
3305                                 sparc_set (code, offset, sparc_o7);
3306                                 sparc_stx (code, ins->sreg1, sparc_sp, sparc_o7);
3307                                 sparc_lddf (code, sparc_sp, sparc_o7, FP_SCRATCH_REG);
3308                         } else {
3309                                 sparc_stx_imm (code, ins->sreg1, sparc_sp, offset);
3310                                 sparc_lddf_imm (code, sparc_sp, offset, FP_SCRATCH_REG);
3311                         }
3312                         sparc_fxtod (code, FP_SCRATCH_REG, ins->dreg);
3313 #else
3314                         if (!sparc_is_imm13 (offset)) {
3315                                 sparc_set (code, offset, sparc_o7);
3316                                 sparc_st (code, ins->sreg1, sparc_sp, sparc_o7);
3317                                 sparc_ldf (code, sparc_sp, sparc_o7, FP_SCRATCH_REG);
3318                         } else {
3319                                 sparc_st_imm (code, ins->sreg1, sparc_sp, offset);
3320                                 sparc_ldf_imm (code, sparc_sp, offset, FP_SCRATCH_REG);
3321                         }
3322                         sparc_fitod (code, FP_SCRATCH_REG, ins->dreg);
3323 #endif
3324                         break;
3325                 }
3326                 case OP_FCONV_TO_I1:
3327                 case OP_FCONV_TO_U1:
3328                 case OP_FCONV_TO_I2:
3329                 case OP_FCONV_TO_U2:
3330 #ifndef SPARCV9
3331                 case OP_FCONV_TO_I:
3332                 case OP_FCONV_TO_U:
3333 #endif
3334                 case OP_FCONV_TO_I4:
3335                 case OP_FCONV_TO_U4: {
3336                         gint32 offset = mono_spillvar_offset_float (cfg, 0);
3337                         sparc_fdtoi (code, ins->sreg1, FP_SCRATCH_REG);
3338                         if (!sparc_is_imm13 (offset)) {
3339                                 sparc_set (code, offset, sparc_o7);
3340                                 sparc_stdf (code, FP_SCRATCH_REG, sparc_sp, sparc_o7);
3341                                 sparc_ld (code, sparc_sp, sparc_o7, ins->dreg);
3342                         } else {
3343                                 sparc_stdf_imm (code, FP_SCRATCH_REG, sparc_sp, offset);
3344                                 sparc_ld_imm (code, sparc_sp, offset, ins->dreg);
3345                         }
3346
3347                         switch (ins->opcode) {
3348                         case OP_FCONV_TO_I1:
3349                         case OP_FCONV_TO_U1:
3350                                 sparc_and_imm (code, 0, ins->dreg, 0xff, ins->dreg);
3351                                 break;
3352                         case OP_FCONV_TO_I2:
3353                         case OP_FCONV_TO_U2:
3354                                 sparc_set (code, 0xffff, sparc_o7);
3355                                 sparc_and (code, 0, ins->dreg, sparc_o7, ins->dreg);
3356                                 break;
3357                         default:
3358                                 break;
3359                         }
3360                         break;
3361                 }
3362                 case OP_FCONV_TO_I8:
3363                 case OP_FCONV_TO_U8:
3364                         /* Emulated */
3365                         g_assert_not_reached ();
3366                         break;
3367                 case CEE_CONV_R_UN:
3368                         /* Emulated */
3369                         g_assert_not_reached ();
3370                         break;
3371                 case OP_LCONV_TO_R_UN: {
3372                         /* Emulated */
3373                         g_assert_not_reached ();
3374                         break;
3375                 }
3376                 case OP_LCONV_TO_OVF_I: {
3377                         guint32 *br [3], *label [1];
3378
3379                         /*
3380                          * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3381                          */
3382                         sparc_cmp_imm (code, ins->sreg1, 0);
3383                         br [0] = code;
3384                         sparc_branch (code, 1, sparc_bneg, 0);
3385                         sparc_nop (code);
3386
3387                         /* positive */
3388                         /* ms word must be 0 */
3389                         sparc_cmp_imm (code, ins->sreg2, 0);
3390                         br [1] = code;
3391                         sparc_branch (code, 1, sparc_be, 0);
3392                         sparc_nop (code);
3393
3394                         label [0] = code;
3395
3396                         EMIT_COND_SYSTEM_EXCEPTION (ins, sparc_ba, "OverflowException");
3397
3398                         /* negative */
3399                         sparc_patch (br [0], code);
3400
3401                         /* ms word must 0xfffffff */
3402                         sparc_cmp_imm (code, ins->sreg2, -1);
3403                         br [2] = code;
3404                         sparc_branch (code, 1, sparc_bne, 0);
3405                         sparc_nop (code);
3406                         sparc_patch (br [2], label [0]);
3407
3408                         /* Ok */
3409                         sparc_patch (br [1], code);
3410                         if (ins->sreg1 != ins->dreg)
3411                                 sparc_mov_reg_reg (code, ins->sreg1, ins->dreg);
3412                         break;
3413                 }
3414                 case OP_FADD:
3415                         sparc_faddd (code, ins->sreg1, ins->sreg2, ins->dreg);
3416                         break;
3417                 case OP_FSUB:
3418                         sparc_fsubd (code, ins->sreg1, ins->sreg2, ins->dreg);
3419                         break;
3420                 case OP_FMUL:
3421                         sparc_fmuld (code, ins->sreg1, ins->sreg2, ins->dreg);
3422                         break;
3423                 case OP_FDIV:
3424                         sparc_fdivd (code, ins->sreg1, ins->sreg2, ins->dreg);
3425                         break;
3426                 case OP_FNEG:
3427 #ifdef SPARCV9
3428                         sparc_fnegd (code, ins->sreg1, ins->dreg);
3429 #else
3430                         /* FIXME: why don't use fnegd ? */
3431                         sparc_fnegs (code, ins->sreg1, ins->dreg);
3432 #endif
3433                         break;
3434                 case OP_FREM:
3435                         sparc_fdivd (code, ins->sreg1, ins->sreg2, FP_SCRATCH_REG);
3436                         sparc_fmuld (code, ins->sreg2, FP_SCRATCH_REG, FP_SCRATCH_REG);
3437                         sparc_fsubd (code, ins->sreg1, FP_SCRATCH_REG, ins->dreg);
3438                         break;
3439                 case OP_FCOMPARE:
3440                         sparc_fcmpd (code, ins->sreg1, ins->sreg2);
3441                         break;
3442                 case OP_FCEQ:
3443                 case OP_FCLT:
3444                 case OP_FCLT_UN:
3445                 case OP_FCGT:
3446                 case OP_FCGT_UN:
3447                         sparc_fcmpd (code, ins->sreg1, ins->sreg2);
3448                         sparc_clr_reg (code, ins->dreg);
3449                         switch (ins->opcode) {
3450                         case OP_FCLT_UN:
3451                         case OP_FCGT_UN:
3452                                 sparc_fbranch (code, 1, opcode_to_sparc_cond (ins->opcode), 4);
3453                                 /* delay slot */
3454                                 sparc_set (code, 1, ins->dreg);
3455                                 sparc_fbranch (code, 1, sparc_fbu, 2);
3456                                 /* delay slot */
3457                                 sparc_set (code, 1, ins->dreg);
3458                                 break;
3459                         default:
3460                                 sparc_fbranch (code, 1, opcode_to_sparc_cond (ins->opcode), 2);
3461                                 /* delay slot */
3462                                 sparc_set (code, 1, ins->dreg);
3463                         }
3464                         break;
3465                 case OP_FBEQ:
3466                 case OP_FBLT:
3467                 case OP_FBGT:
3468                         EMIT_FLOAT_COND_BRANCH (ins, opcode_to_sparc_cond (ins->opcode), 1, 1);
3469                         break;
3470                 case OP_FBGE: {
3471                         /* clt.un + brfalse */
3472                         guint32 *p = code;
3473                         sparc_fbranch (code, 1, sparc_fbul, 0);
3474                         /* delay slot */
3475                         sparc_nop (code);
3476                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fba, 1, 1);
3477                         sparc_patch (p, (guint8*)code);
3478                         break;
3479                 }
3480                 case OP_FBLE: {
3481                         /* cgt.un + brfalse */
3482                         guint32 *p = code;
3483                         sparc_fbranch (code, 1, sparc_fbug, 0);
3484                         /* delay slot */
3485                         sparc_nop (code);
3486                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fba, 1, 1);
3487                         sparc_patch (p, (guint8*)code);
3488                         break;
3489                 }
3490                 case OP_FBNE_UN:
3491                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbne, 1, 1);
3492                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbu, 1, 1);
3493                         break;
3494                 case OP_FBLT_UN:
3495                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbl, 1, 1);
3496                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbu, 1, 1);
3497                         break;
3498                 case OP_FBGT_UN:
3499                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbg, 1, 1);
3500                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbu, 1, 1);
3501                         break;
3502                 case OP_FBGE_UN:
3503                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbge, 1, 1);
3504                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbu, 1, 1);
3505                         break;
3506                 case OP_FBLE_UN:
3507                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fble, 1, 1);
3508                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbu, 1, 1);
3509                         break;
3510                 case CEE_CKFINITE: {
3511                         gint32 offset = mono_spillvar_offset_float (cfg, 0);
3512                         if (!sparc_is_imm13 (offset)) {
3513                                 sparc_set (code, offset, sparc_o7);
3514                                 sparc_stdf (code, ins->sreg1, sparc_sp, sparc_o7);
3515                                 sparc_lduh (code, sparc_sp, sparc_o7, sparc_o7);
3516                         } else {
3517                                 sparc_stdf_imm (code, ins->sreg1, sparc_sp, offset);
3518                                 sparc_lduh_imm (code, sparc_sp, offset, sparc_o7);
3519                         }
3520                         sparc_srl_imm (code, sparc_o7, 4, sparc_o7);
3521                         sparc_and_imm (code, FALSE, sparc_o7, 2047, sparc_o7);
3522                         sparc_cmp_imm (code, sparc_o7, 2047);
3523                         EMIT_COND_SYSTEM_EXCEPTION (ins, sparc_be, "ArithmeticException");
3524 #ifdef SPARCV9
3525                         sparc_fmovd (code, ins->sreg1, ins->dreg);
3526 #else
3527                         sparc_fmovs (code, ins->sreg1, ins->dreg);
3528                         sparc_fmovs (code, ins->sreg1 + 1, ins->dreg + 1);
3529 #endif
3530                         break;
3531                 }
3532
3533                 case OP_MEMORY_BARRIER:
3534                         sparc_membar (code, sparc_membar_all);
3535                         break;
3536
3537                 default:
3538 #ifdef __GNUC__
3539                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3540 #else
3541                         g_warning ("%s:%d: unknown opcode %s\n", __FILE__, __LINE__, mono_inst_name (ins->opcode));
3542 #endif
3543                         g_assert_not_reached ();
3544                 }
3545
3546                 if ((((guint8*)code) - code_start) > max_len) {
3547                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
3548                                    mono_inst_name (ins->opcode), max_len, ((guint8*)code) - code_start);
3549                         g_assert_not_reached ();
3550                 }
3551
3552                 cpos += max_len;
3553
3554                 last_ins = ins;
3555
3556                 ins = ins->next;
3557         }
3558
3559         cfg->code_len = (guint8*)code - cfg->native_code;
3560 }
3561
3562 void
3563 mono_arch_register_lowlevel_calls (void)
3564 {
3565         mono_register_jit_icall (mono_arch_break, "mono_arch_break", NULL, TRUE);
3566         mono_register_jit_icall (mono_arch_get_lmf_addr, "mono_arch_get_lmf_addr", NULL, TRUE);
3567 }
3568
3569 void
3570 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3571 {
3572         MonoJumpInfo *patch_info;
3573
3574         /* FIXME: Move part of this to arch independent code */
3575         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3576                 unsigned char *ip = patch_info->ip.i + code;
3577                 gpointer target;
3578
3579                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3580
3581                 switch (patch_info->type) {
3582                 case MONO_PATCH_INFO_NONE:
3583                         continue;
3584                 case MONO_PATCH_INFO_CLASS_INIT: {
3585                         guint32 *ip2 = (guint32*)ip;
3586                         /* Might already been changed to a nop */
3587 #ifdef SPARCV9
3588                         sparc_set_template (ip2, sparc_o7);
3589                         sparc_jmpl (ip2, sparc_o7, sparc_g0, sparc_o7);
3590 #else
3591                         sparc_call_simple (ip2, 0);
3592 #endif
3593                         break;
3594                 }
3595                 case MONO_PATCH_INFO_METHOD_JUMP: {
3596                         guint32 *ip2 = (guint32*)ip;
3597                         /* Might already been patched */
3598                         sparc_set_template (ip2, sparc_o7);
3599                         break;
3600                 }
3601                 default:
3602                         break;
3603                 }
3604                 sparc_patch ((guint32*)ip, target);
3605         }
3606 }
3607
3608 void*
3609 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3610 {
3611         int i;
3612         guint32 *code = (guint32*)p;
3613         MonoMethodSignature *sig = mono_method_signature (cfg->method);
3614         CallInfo *cinfo;
3615
3616         /* Save registers to stack */
3617         for (i = 0; i < 6; ++i)
3618                 sparc_sti_imm (code, sparc_i0 + i, sparc_fp, ARGS_OFFSET + (i * sizeof (gpointer)));
3619
3620         cinfo = get_call_info (sig, FALSE);
3621
3622         /* Save float regs on V9, since they are caller saved */
3623         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3624                 ArgInfo *ainfo = cinfo->args + i;
3625                 gint32 stack_offset;
3626
3627                 stack_offset = ainfo->offset + ARGS_OFFSET;
3628
3629                 if (ainfo->storage == ArgInFloatReg) {
3630                         if (!sparc_is_imm13 (stack_offset))
3631                                 NOT_IMPLEMENTED;
3632                         sparc_stf_imm (code, ainfo->reg, sparc_fp, stack_offset);
3633                 }
3634                 else if (ainfo->storage == ArgInDoubleReg) {
3635                         /* The offset is guaranteed to be aligned by the ABI rules */
3636                         sparc_stdf_imm (code, ainfo->reg, sparc_fp, stack_offset);
3637                 }
3638         }
3639
3640         sparc_set (code, cfg->method, sparc_o0);
3641         sparc_add_imm (code, FALSE, sparc_fp, MONO_SPARC_STACK_BIAS, sparc_o1);
3642
3643         mono_add_patch_info (cfg, (guint8*)code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
3644         EMIT_CALL ();
3645
3646         /* Restore float regs on V9 */
3647         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3648                 ArgInfo *ainfo = cinfo->args + i;
3649                 gint32 stack_offset;
3650
3651                 stack_offset = ainfo->offset + ARGS_OFFSET;
3652
3653                 if (ainfo->storage == ArgInFloatReg) {
3654                         if (!sparc_is_imm13 (stack_offset))
3655                                 NOT_IMPLEMENTED;
3656                         sparc_ldf_imm (code, sparc_fp, stack_offset, ainfo->reg);
3657                 }
3658                 else if (ainfo->storage == ArgInDoubleReg) {
3659                         /* The offset is guaranteed to be aligned by the ABI rules */
3660                         sparc_lddf_imm (code, sparc_fp, stack_offset, ainfo->reg);
3661                 }
3662         }
3663
3664         g_free (cinfo);
3665
3666         return code;
3667 }
3668
3669 enum {
3670         SAVE_NONE,
3671         SAVE_STRUCT,
3672         SAVE_ONE,
3673         SAVE_TWO,
3674         SAVE_FP
3675 };
3676
3677 void*
3678 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
3679 {
3680         guint32 *code = (guint32*)p;
3681         int save_mode = SAVE_NONE;
3682         MonoMethod *method = cfg->method;
3683
3684         switch (mono_type_get_underlying_type (mono_method_signature (method)->ret)->type) {
3685         case MONO_TYPE_VOID:
3686                 /* special case string .ctor icall */
3687                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
3688                         save_mode = SAVE_ONE;
3689                 else
3690                         save_mode = SAVE_NONE;
3691                 break;
3692         case MONO_TYPE_I8:
3693         case MONO_TYPE_U8:
3694 #ifdef SPARCV9
3695                 save_mode = SAVE_ONE;
3696 #else
3697                 save_mode = SAVE_TWO;
3698 #endif
3699                 break;
3700         case MONO_TYPE_R4:
3701         case MONO_TYPE_R8:
3702                 save_mode = SAVE_FP;
3703                 break;
3704         case MONO_TYPE_VALUETYPE:
3705                 save_mode = SAVE_STRUCT;
3706                 break;
3707         default:
3708                 save_mode = SAVE_ONE;
3709                 break;
3710         }
3711
3712         /* Save the result to the stack and also put it into the output registers */
3713
3714         switch (save_mode) {
3715         case SAVE_TWO:
3716                 /* V8 only */
3717                 sparc_st_imm (code, sparc_i0, sparc_fp, 68);
3718                 sparc_st_imm (code, sparc_i0, sparc_fp, 72);
3719                 sparc_mov_reg_reg (code, sparc_i0, sparc_o1);
3720                 sparc_mov_reg_reg (code, sparc_i1, sparc_o2);
3721                 break;
3722         case SAVE_ONE:
3723                 sparc_sti_imm (code, sparc_i0, sparc_fp, ARGS_OFFSET);
3724                 sparc_mov_reg_reg (code, sparc_i0, sparc_o1);
3725                 break;
3726         case SAVE_FP:
3727 #ifdef SPARCV9
3728                 sparc_stdf_imm (code, sparc_f0, sparc_fp, ARGS_OFFSET);
3729 #else
3730                 sparc_stdf_imm (code, sparc_f0, sparc_fp, 72);
3731                 sparc_ld_imm (code, sparc_fp, 72, sparc_o1);
3732                 sparc_ld_imm (code, sparc_fp, 72 + 4, sparc_o2);
3733 #endif
3734                 break;
3735         case SAVE_STRUCT:
3736 #ifdef SPARCV9
3737                 sparc_mov_reg_reg (code, sparc_i0, sparc_o1);
3738 #else
3739                 sparc_ld_imm (code, sparc_fp, 64, sparc_o1);
3740 #endif
3741                 break;
3742         case SAVE_NONE:
3743         default:
3744                 break;
3745         }
3746
3747         sparc_set (code, cfg->method, sparc_o0);
3748
3749         mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_ABS, func);
3750         EMIT_CALL ();
3751
3752         /* Restore result */
3753
3754         switch (save_mode) {
3755         case SAVE_TWO:
3756                 sparc_ld_imm (code, sparc_fp, 68, sparc_i0);
3757                 sparc_ld_imm (code, sparc_fp, 72, sparc_i0);
3758                 break;
3759         case SAVE_ONE:
3760                 sparc_ldi_imm (code, sparc_fp, ARGS_OFFSET, sparc_i0);
3761                 break;
3762         case SAVE_FP:
3763                 sparc_lddf_imm (code, sparc_fp, ARGS_OFFSET, sparc_f0);
3764                 break;
3765         case SAVE_NONE:
3766         default:
3767                 break;
3768         }
3769
3770         return code;
3771 }
3772
3773 guint8 *
3774 mono_arch_emit_prolog (MonoCompile *cfg)
3775 {
3776         MonoMethod *method = cfg->method;
3777         MonoMethodSignature *sig;
3778         MonoInst *inst;
3779         guint32 *code;
3780         CallInfo *cinfo;
3781         guint32 i, offset;
3782
3783         cfg->code_size = 256;
3784         cfg->native_code = g_malloc (cfg->code_size);
3785         code = (guint32*)cfg->native_code;
3786
3787         /* FIXME: Generate intermediate code instead */
3788
3789         offset = cfg->stack_offset;
3790         offset += (16 * sizeof (gpointer)); /* register save area */
3791 #ifndef SPARCV9
3792         offset += 4; /* struct/union return pointer */
3793 #endif
3794
3795         /* add parameter area size for called functions */
3796         if (cfg->param_area < (6 * sizeof (gpointer)))
3797                 /* Reserve space for the first 6 arguments even if it is unused */
3798                 offset += 6 * sizeof (gpointer);
3799         else
3800                 offset += cfg->param_area;
3801
3802         /* align the stack size */
3803         offset = ALIGN_TO (offset, MONO_ARCH_FRAME_ALIGNMENT);
3804
3805         /*
3806          * localloc'd memory is stored between the local variables (whose
3807          * size is given by cfg->stack_offset), and between the space reserved
3808          * by the ABI.
3809          */
3810         cfg->arch.localloc_offset = offset - cfg->stack_offset;
3811
3812         cfg->stack_offset = offset;
3813
3814 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
3815                         /* Perform stack touching */
3816                         NOT_IMPLEMENTED;
3817 #endif
3818
3819         if (!sparc_is_imm13 (- cfg->stack_offset)) {
3820                 /* Can't use sparc_o7 here, since we're still in the caller's frame */
3821                 sparc_set (code, (- cfg->stack_offset), GP_SCRATCH_REG);
3822                 sparc_save (code, sparc_sp, GP_SCRATCH_REG, sparc_sp);
3823         }
3824         else
3825                 sparc_save_imm (code, sparc_sp, - cfg->stack_offset, sparc_sp);
3826
3827 /*
3828         if (strstr (cfg->method->name, "foo")) {
3829                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_ABS, mono_sparc_break);
3830                 sparc_call_simple (code, 0);
3831                 sparc_nop (code);
3832         }
3833 */
3834
3835         sig = mono_method_signature (method);
3836
3837         cinfo = get_call_info (sig, FALSE);
3838
3839         /* Keep in sync with emit_load_volatile_arguments */
3840         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3841                 ArgInfo *ainfo = cinfo->args + i;
3842                 gint32 stack_offset;
3843                 MonoType *arg_type;
3844                 inst = cfg->varinfo [i];
3845
3846                 if (sig->hasthis && (i == 0))
3847                         arg_type = &mono_defaults.object_class->byval_arg;
3848                 else
3849                         arg_type = sig->params [i - sig->hasthis];
3850
3851                 stack_offset = ainfo->offset + ARGS_OFFSET;
3852
3853                 /* Save the split arguments so they will reside entirely on the stack */
3854                 if (ainfo->storage == ArgInSplitRegStack) {
3855                         /* Save the register to the stack */
3856                         g_assert (inst->opcode == OP_REGOFFSET);
3857                         if (!sparc_is_imm13 (stack_offset))
3858                                 NOT_IMPLEMENTED;
3859                         sparc_st_imm (code, sparc_i5, inst->inst_basereg, stack_offset);
3860                 }
3861
3862                 if (!v64 && !arg_type->byref && (arg_type->type == MONO_TYPE_R8)) {
3863                         /* Save the argument to a dword aligned stack location */
3864                         /*
3865                          * stack_offset contains the offset of the argument on the stack.
3866                          * inst->inst_offset contains the dword aligned offset where the value
3867                          * should be stored.
3868                          */
3869                         if (ainfo->storage == ArgInIRegPair) {
3870                                 if (!sparc_is_imm13 (inst->inst_offset + 4))
3871                                         NOT_IMPLEMENTED;
3872                                 sparc_st_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, inst->inst_offset);
3873                                 sparc_st_imm (code, sparc_i0 + ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
3874                         }
3875                         else
3876                                 if (ainfo->storage == ArgInSplitRegStack) {
3877 #ifdef SPARCV9
3878                                         g_assert_not_reached ();
3879 #endif
3880                                         if (stack_offset != inst->inst_offset) {
3881                                                 /* stack_offset is not dword aligned, so we need to make a copy */
3882                                                 sparc_st_imm (code, sparc_i5, inst->inst_basereg, inst->inst_offset);
3883                                                 sparc_ld_imm (code, sparc_fp, stack_offset + 4, sparc_o7);
3884                                                 sparc_st_imm (code, sparc_o7, inst->inst_basereg, inst->inst_offset + 4);
3885                                         }
3886                                 }
3887                         else
3888                                 if (ainfo->storage == ArgOnStackPair) {
3889 #ifdef SPARCV9
3890                                         g_assert_not_reached ();
3891 #endif
3892                                         if (stack_offset != inst->inst_offset) {
3893                                                 /* stack_offset is not dword aligned, so we need to make a copy */
3894                                                 sparc_ld_imm (code, sparc_fp, stack_offset, sparc_o7);
3895                                                 sparc_st_imm (code, sparc_o7, inst->inst_basereg, inst->inst_offset);
3896                                                 sparc_ld_imm (code, sparc_fp, stack_offset + 4, sparc_o7);
3897                                                 sparc_st_imm (code, sparc_o7, inst->inst_basereg, inst->inst_offset + 4);
3898                                         }
3899                                 }
3900                         else
3901                                 g_assert_not_reached ();
3902                 }
3903                 else
3904                         if ((ainfo->storage == ArgInIReg) && (inst->opcode != OP_REGVAR)) {
3905                                 /* Argument in register, but need to be saved to stack */
3906                                 if (!sparc_is_imm13 (stack_offset))
3907                                         NOT_IMPLEMENTED;
3908                                 if ((stack_offset - ARGS_OFFSET) & 0x1)
3909                                         sparc_stb_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, stack_offset);
3910                                 else
3911                                         if ((stack_offset - ARGS_OFFSET) & 0x2)
3912                                                 sparc_sth_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, stack_offset);
3913                                 else
3914                                         if ((stack_offset - ARGS_OFFSET) & 0x4)
3915                                                 sparc_st_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, stack_offset);
3916                                         else {
3917                                                 if (v64)
3918                                                         sparc_stx_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, stack_offset);
3919                                                 else
3920                                                         sparc_st_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, stack_offset);
3921                                         }
3922                         }
3923                 else
3924                         if ((ainfo->storage == ArgInIRegPair) && (inst->opcode != OP_REGVAR)) {
3925 #ifdef SPARCV9
3926                                 NOT_IMPLEMENTED;
3927 #endif
3928                                 /* Argument in regpair, but need to be saved to stack */
3929                                 if (!sparc_is_imm13 (inst->inst_offset + 4))
3930                                         NOT_IMPLEMENTED;
3931                                 sparc_st_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, inst->inst_offset);
3932                                 sparc_st_imm (code, sparc_i0 + ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
3933                         }
3934                 else if ((ainfo->storage == ArgInFloatReg) && (inst->opcode != OP_REGVAR)) {
3935                                 if (!sparc_is_imm13 (stack_offset))
3936                                         NOT_IMPLEMENTED;
3937                                 sparc_stf_imm (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3938                                 }
3939                         else if ((ainfo->storage == ArgInDoubleReg) && (inst->opcode != OP_REGVAR)) {
3940                                 /* The offset is guaranteed to be aligned by the ABI rules */
3941                                 sparc_stdf_imm (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3942                         }
3943
3944                 if ((ainfo->storage == ArgInFloatReg) && (inst->opcode == OP_REGVAR)) {
3945                         /* Need to move into the a double precision register */
3946                         sparc_fstod (code, ainfo->reg, ainfo->reg - 1);
3947                 }
3948
3949                 if ((ainfo->storage == ArgInSplitRegStack) || (ainfo->storage == ArgOnStack))
3950                         if (inst->opcode == OP_REGVAR)
3951                                 /* FIXME: Load the argument into memory */
3952                                 NOT_IMPLEMENTED;
3953         }
3954
3955         g_free (cinfo);
3956
3957         if (cfg->method->save_lmf) {
3958                 gint32 lmf_offset = STACK_BIAS - cfg->arch.lmf_offset;
3959
3960                 /* Save ip */
3961                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
3962                 sparc_set_template (code, sparc_o7);
3963                 sparc_sti_imm (code, sparc_o7, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ip));
3964                 /* Save sp */
3965                 sparc_sti_imm (code, sparc_sp, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, sp));
3966                 /* Save fp */
3967                 sparc_sti_imm (code, sparc_fp, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp));
3968                 /* Save method */
3969                 /* FIXME: add a relocation for this */
3970                 sparc_set (code, cfg->method, sparc_o7);
3971                 sparc_sti_imm (code, sparc_o7, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method));
3972
3973                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3974                                                          (gpointer)"mono_arch_get_lmf_addr");
3975                 EMIT_CALL ();
3976
3977                 code = (guint32*)mono_sparc_emit_save_lmf (code, lmf_offset);
3978         }
3979
3980         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3981                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
3982
3983         cfg->code_len = (guint8*)code - cfg->native_code;
3984
3985         g_assert (cfg->code_len <= cfg->code_size);
3986
3987         return (guint8*)code;
3988 }
3989
3990 void
3991 mono_arch_emit_epilog (MonoCompile *cfg)
3992 {
3993         MonoMethod *method = cfg->method;
3994         guint32 *code;
3995         int can_fold = 0;
3996         int max_epilog_size = 16 + 20 * 4;
3997
3998         if (cfg->method->save_lmf)
3999                 max_epilog_size += 128;
4000
4001         if (mono_jit_trace_calls != NULL)
4002                 max_epilog_size += 50;
4003
4004         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4005                 max_epilog_size += 50;
4006
4007         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4008                 cfg->code_size *= 2;
4009                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4010                 mono_jit_stats.code_reallocs++;
4011         }
4012
4013         code = (guint32*)(cfg->native_code + cfg->code_len);
4014
4015         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4016                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4017
4018         if (cfg->method->save_lmf) {
4019                 gint32 lmf_offset = STACK_BIAS - cfg->arch.lmf_offset;
4020
4021                 code = mono_sparc_emit_restore_lmf (code, lmf_offset);
4022         }
4023
4024         /*
4025          * The V8 ABI requires that calls to functions which return a structure
4026          * return to %i7+12
4027          */
4028         if (!v64 && mono_method_signature (cfg->method)->pinvoke && MONO_TYPE_ISSTRUCT(mono_method_signature (cfg->method)->ret))
4029                 sparc_jmpl_imm (code, sparc_i7, 12, sparc_g0);
4030         else
4031                 sparc_ret (code);
4032
4033         /* Only fold last instruction into the restore if the exit block has an in count of 1
4034            and the previous block hasn't been optimized away since it may have an in count > 1 */
4035         if (cfg->bb_exit->in_count == 1 && cfg->bb_exit->in_bb[0]->native_offset != cfg->bb_exit->native_offset)
4036                 can_fold = 1;
4037
4038         /* Try folding last instruction into the restore */
4039         if (can_fold && (sparc_inst_op (code [-2]) == 0x2) && (sparc_inst_op3 (code [-2]) == 0x2) && sparc_inst_imm (code [-2]) && (sparc_inst_rd (code [-2]) == sparc_i0)) {
4040                 /* or reg, imm, %i0 */
4041                 int reg = sparc_inst_rs1 (code [-2]);
4042                 int imm = sparc_inst_imm13 (code [-2]);
4043                 code [-2] = code [-1];
4044                 code --;
4045                 sparc_restore_imm (code, reg, imm, sparc_o0);
4046         }
4047         else
4048         if (can_fold && (sparc_inst_op (code [-2]) == 0x2) && (sparc_inst_op3 (code [-2]) == 0x2) && (!sparc_inst_imm (code [-2])) && (sparc_inst_rd (code [-2]) == sparc_i0)) {
4049                 /* or reg, reg, %i0 */
4050                 int reg1 = sparc_inst_rs1 (code [-2]);
4051                 int reg2 = sparc_inst_rs2 (code [-2]);
4052                 code [-2] = code [-1];
4053                 code --;
4054                 sparc_restore (code, reg1, reg2, sparc_o0);
4055         }
4056         else
4057                 sparc_restore_imm (code, sparc_g0, 0, sparc_g0);
4058
4059         cfg->code_len = (guint8*)code - cfg->native_code;
4060
4061         g_assert (cfg->code_len < cfg->code_size);
4062
4063 }
4064
4065 void
4066 mono_arch_emit_exceptions (MonoCompile *cfg)
4067 {
4068         MonoJumpInfo *patch_info;
4069         guint32 *code;
4070         int nthrows = 0, i;
4071         int exc_count = 0;
4072         guint32 code_size;
4073         MonoClass *exc_classes [16];
4074         guint8 *exc_throw_start [16], *exc_throw_end [16];
4075
4076         /* Compute needed space */
4077         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4078                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4079                         exc_count++;
4080         }
4081
4082         /*
4083          * make sure we have enough space for exceptions
4084          */
4085 #ifdef SPARCV9
4086         code_size = exc_count * (20 * 4);
4087 #else
4088         code_size = exc_count * 24;
4089 #endif
4090
4091         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4092                 cfg->code_size *= 2;
4093                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4094                 mono_jit_stats.code_reallocs++;
4095         }
4096
4097         code = (guint32*)(cfg->native_code + cfg->code_len);
4098
4099         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4100                 switch (patch_info->type) {
4101                 case MONO_PATCH_INFO_EXC: {
4102                         MonoClass *exc_class;
4103                         guint32 *buf, *buf2;
4104                         guint32 throw_ip, type_idx;
4105                         gint32 disp;
4106
4107                         sparc_patch ((guint32*)(cfg->native_code + patch_info->ip.i), code);
4108
4109                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4110                         type_idx = exc_class->type_token - MONO_TOKEN_TYPE_DEF;
4111                         g_assert (exc_class);
4112                         throw_ip = patch_info->ip.i;
4113
4114                         /* Find a throw sequence for the same exception class */
4115                         for (i = 0; i < nthrows; ++i)
4116                                 if (exc_classes [i] == exc_class)
4117                                         break;
4118
4119                         if (i < nthrows) {
4120                                 guint32 throw_offset = (((guint8*)exc_throw_end [i] - cfg->native_code) - throw_ip) >> 2;
4121                                 if (!sparc_is_imm13 (throw_offset))
4122                                         sparc_set32 (code, throw_offset, sparc_o1);
4123
4124                                 disp = (exc_throw_start [i] - (guint8*)code) >> 2;
4125                                 g_assert (sparc_is_imm22 (disp));
4126                                 sparc_branch (code, 0, sparc_ba, disp);
4127                                 if (sparc_is_imm13 (throw_offset))
4128                                         sparc_set32 (code, throw_offset, sparc_o1);
4129                                 else
4130                                         sparc_nop (code);
4131                                 patch_info->type = MONO_PATCH_INFO_NONE;
4132                         }
4133                         else {
4134                                 /* Emit the template for setting o1 */
4135                                 buf = code;
4136                                 if (sparc_is_imm13 (((((guint8*)code - cfg->native_code) - throw_ip) >> 2) - 8))
4137                                         /* Can use a short form */
4138                                         sparc_nop (code);
4139                                 else
4140                                         sparc_set_template (code, sparc_o1);
4141                                 buf2 = code;
4142
4143                                 if (nthrows < 16) {
4144                                         exc_classes [nthrows] = exc_class;
4145                                         exc_throw_start [nthrows] = (guint8*)code;
4146                                 }
4147
4148                                 /*
4149                                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_ABS, mono_sparc_break);
4150                                 EMIT_CALL();
4151                                 */
4152
4153                                 /* first arg = type token */
4154                                 /* Pass the type index to reduce the size of the sparc_set */
4155                                 if (!sparc_is_imm13 (type_idx))
4156                                         sparc_set32 (code, type_idx, sparc_o0);
4157
4158                                 /* second arg = offset between the throw ip and the current ip */
4159                                 /* On sparc, the saved ip points to the call instruction */
4160                                 disp = (((guint8*)code - cfg->native_code) - throw_ip) >> 2;
4161                                 sparc_set32 (buf, disp, sparc_o1);
4162                                 while (buf < buf2)
4163                                         sparc_nop (buf);
4164
4165                                 if (nthrows < 16) {
4166                                         exc_throw_end [nthrows] = (guint8*)code;
4167                                         nthrows ++;
4168                                 }
4169
4170                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4171                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4172                                 patch_info->ip.i = (guint8*)code - cfg->native_code;
4173
4174                                 EMIT_CALL ();
4175
4176                                 if (sparc_is_imm13 (type_idx)) {
4177                                         /* Put it into the delay slot */
4178                                         code --;
4179                                         buf = code;
4180                                         sparc_set32 (code, type_idx, sparc_o0);
4181                                         g_assert (code - buf == 1);
4182                                 }
4183                         }
4184                         break;
4185                 }
4186                 default:
4187                         /* do nothing */
4188                         break;
4189                 }
4190         }
4191
4192         cfg->code_len = (guint8*)code - cfg->native_code;
4193
4194         g_assert (cfg->code_len < cfg->code_size);
4195
4196 }
4197
4198 gboolean lmf_addr_key_inited = FALSE;
4199
4200 #ifdef MONO_SPARC_THR_TLS
4201 thread_key_t lmf_addr_key;
4202 #else
4203 pthread_key_t lmf_addr_key;
4204 #endif
4205
4206 gpointer
4207 mono_arch_get_lmf_addr (void)
4208 {
4209         /* This is perf critical so we bypass the IO layer */
4210         /* The thr_... functions seem to be somewhat faster */
4211 #ifdef MONO_SPARC_THR_TLS
4212         gpointer res;
4213         thr_getspecific (lmf_addr_key, &res);
4214         return res;
4215 #else
4216         return pthread_getspecific (lmf_addr_key);
4217 #endif
4218 }
4219
4220 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
4221
4222 /*
4223  * There seems to be no way to determine stack boundaries under solaris,
4224  * so it's not possible to determine whenever a SIGSEGV is caused by stack
4225  * overflow or not.
4226  */
4227 #error "--with-sigaltstack=yes not supported on solaris"
4228
4229 static void
4230 setup_stack (MonoJitTlsData *tls)
4231 {
4232 #ifdef __linux__
4233         struct sigaltstack sa;
4234 #else
4235         stack_t         sigstk;
4236 #endif
4237
4238         /* Setup an alternate signal stack */
4239         tls->signal_stack = mmap (0, SIGNAL_STACK_SIZE, PROT_READ|PROT_WRITE|PROT_EXEC, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0);
4240         tls->signal_stack_size = SIGNAL_STACK_SIZE;
4241
4242 #ifdef __linux__
4243         sa.ss_sp = tls->signal_stack;
4244         sa.ss_size = SIGNAL_STACK_SIZE;
4245         sa.ss_flags = 0;
4246         g_assert (sigaltstack (&sa, NULL) == 0);
4247 #else
4248         sigstk.ss_sp = tls->signal_stack;
4249         sigstk.ss_size = SIGNAL_STACK_SIZE;
4250         sigstk.ss_flags = 0;
4251         g_assert (sigaltstack (&sigstk, NULL) == 0);
4252 #endif
4253 }
4254
4255 #endif
4256
4257 void
4258 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
4259 {
4260         if (!lmf_addr_key_inited) {
4261                 int res;
4262
4263                 lmf_addr_key_inited = TRUE;
4264
4265 #ifdef MONO_SPARC_THR_TLS
4266                 res = thr_keycreate (&lmf_addr_key, NULL);
4267 #else
4268                 res = pthread_key_create (&lmf_addr_key, NULL);
4269 #endif
4270                 g_assert (res == 0);
4271
4272         }
4273
4274 #ifdef MONO_SPARC_THR_TLS
4275         thr_setspecific (lmf_addr_key, &tls->lmf);
4276 #else
4277         pthread_setspecific (lmf_addr_key, &tls->lmf);
4278 #endif
4279
4280 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
4281         setup_stack (tls);
4282 #endif
4283 }
4284
4285 void
4286 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4287 {
4288 }
4289
4290 void
4291 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *call, int this_reg, int this_type, int vt_reg)
4292 {
4293         int this_out_reg = sparc_o0;
4294
4295         if (vt_reg != -1) {
4296 #ifdef SPARCV9
4297                 MonoInst *ins;
4298                 MONO_INST_NEW (cfg, ins, OP_SETREG);
4299                 ins->sreg1 = vt_reg;
4300                 ins->dreg = mono_regstate_next_int (cfg->rs);
4301                 mono_bblock_add_inst (cfg->cbb, ins);
4302
4303                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, sparc_o0, FALSE);
4304
4305                 this_out_reg = sparc_o1;
4306 #else
4307                 /* Set the 'struct/union return pointer' location on the stack */
4308                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, sparc_sp, 64, vt_reg);
4309 #endif
4310         }
4311
4312         /* add the this argument */
4313         if (this_reg != -1) {
4314                 MonoInst *this;
4315                 MONO_INST_NEW (cfg, this, OP_SETREG);
4316                 this->type = this_type;
4317                 this->sreg1 = this_reg;
4318                 this->dreg = mono_regstate_next_int (cfg->rs);
4319                 mono_bblock_add_inst (cfg->cbb, this);
4320
4321                 mono_call_inst_add_outarg_reg (cfg, call, this->dreg, this_out_reg, FALSE);
4322         }
4323 }
4324
4325
4326 MonoInst*
4327 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4328 {
4329         MonoInst *ins = NULL;
4330
4331         if (cmethod->klass == mono_defaults.thread_class &&
4332                 strcmp (cmethod->name, "MemoryBarrier") == 0) {
4333                 if (sparcv9)
4334                         MONO_INST_NEW (cfg, ins, OP_MEMORY_BARRIER);
4335         }
4336
4337         return ins;
4338 }
4339
4340 /*
4341  * mono_arch_get_argument_info:
4342  * @csig:  a method signature
4343  * @param_count: the number of parameters to consider
4344  * @arg_info: an array to store the result infos
4345  *
4346  * Gathers information on parameters such as size, alignment and
4347  * padding. arg_info should be large enought to hold param_count + 1 entries.
4348  *
4349  * Returns the size of the activation frame.
4350  */
4351 int
4352 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
4353 {
4354         int k, align;
4355         CallInfo *cinfo;
4356         ArgInfo *ainfo;
4357
4358         cinfo = get_call_info (csig, FALSE);
4359
4360         if (csig->hasthis) {
4361                 ainfo = &cinfo->args [0];
4362                 arg_info [0].offset = ARGS_OFFSET - MONO_SPARC_STACK_BIAS + ainfo->offset;
4363         }
4364
4365         for (k = 0; k < param_count; k++) {
4366                 ainfo = &cinfo->args [k + csig->hasthis];
4367
4368                 arg_info [k + 1].offset = ARGS_OFFSET - MONO_SPARC_STACK_BIAS + ainfo->offset;
4369                 arg_info [k + 1].size = mono_type_size (csig->params [k], &align);
4370         }
4371
4372         g_free (cinfo);
4373
4374         return 0;
4375 }
4376
4377 gboolean
4378 mono_arch_print_tree (MonoInst *tree, int arity)
4379 {
4380         return 0;
4381 }
4382
4383 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
4384 {
4385         return NULL;
4386 }
4387
4388 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
4389 {
4390         return NULL;
4391 }