mono/mini/mini-sparc.c

   1 /*
   2  * mini-sparc.c: Sparc backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Paolo Molaro (lupus@ximian.com)
   6  *   Dietmar Maurer (dietmar@ximian.com)
   7  *
   8  * Modified for SPARC:
   9  *   Christopher Taylor (ct@gentoo.org)
  10  *   Mark Crichton (crichton@gimp.org)
  11  *   Zoltan Varga (vargaz@freemail.hu)
  12  *
  13  * (C) 2003 Ximian, Inc.
  14  */
  15 #include "mini.h"
  16 #include <string.h>
  17 #include <pthread.h>
  18 #include <unistd.h>
  19
  20 #ifndef __linux__
  21 #include <sys/systeminfo.h>
  22 #include <thread.h>
  23 #endif
  24
  25 #include <mono/metadata/appdomain.h>
  26 #include <mono/metadata/debug-helpers.h>
  27 #include <mono/utils/mono-math.h>
  28
  29 #include "mini-sparc.h"
  30 #include "inssel.h"
  31 #include "trace.h"
  32 #include "cpu-sparc.h"
  33
  34 /*
  35  * Sparc V9 means two things:
  36  * - the instruction set
  37  * - the ABI
  38  *
  39  * V9 instructions are only usable if the underlying processor is 64 bit. Most Sparc
  40  * processors in use are 64 bit processors. The V9 ABI is only usable if the
  41  * mono executable is a 64 bit executable. So it would make sense to use the 64 bit
  42  * instructions without using the 64 bit ABI.
  43  */
  44
  45 /*
  46  * Register usage:
  47  * - %i0..%i<n> hold the incoming arguments, these are never written by JITted
  48  * code. Unused input registers are used for global register allocation.
  49  * - %l0..%l7 is used for local register allocation
  50  * - %o0..%o6 is used for outgoing arguments
  51  * - %o7 and %g1 is used as scratch registers in opcodes
  52  * - all floating point registers are used for local register allocation except %f0.
  53  *   Only double precision registers are used.
  54  * In 64 bit mode:
  55  * - fp registers %d0..%d30 are used for parameter passing, and %d32..%d62 are
  56  *   used for local allocation.
  57  */
  58
  59 /*
  60  * Alignment:
  61  * - doubles and longs must be stored in dword aligned locations
  62  */
  63
  64 /*
  65  * The following things are not implemented or do not work:
  66  *  - some fp arithmetic corner cases
  67  * The following tests in mono/mini are expected to fail:
  68  *  - test_0_simple_double_casts
  69  *      This test casts (guint64)-1 to double and then back to guint64 again.
  70  *    Under x86, it returns 0, while under sparc it returns -1.
  71  *
  72  * In addition to this, the runtime requires the trunc function, or its
  73  * solaris counterpart, aintl, to do some double->int conversions. If this
  74  * function is not available, it is emulated somewhat, but the results can be
  75  * strange.
  76  */
  77
  78 /*
  79  * SPARCV9 FIXME:
  80  * - optimize sparc_set according to the memory model
  81  * - when non-AOT compiling, compute patch targets immediately so we don't
  82  *   have to emit the 6 byte template.
  83  * - varags
  84  * - struct arguments/returns
  85  */
  86
  87 /*
  88  * SPARCV9 ISSUES:
  89  * - sparc_call_simple can't be used in a lot of places since the displacement
  90  *   might not fit into an imm30.
  91  * - g1 can't be used in a lot of places since it is used as a scratch reg in
  92  *   sparc_set.
  93  * - sparc_f0 can't be used as a scratch register on V9
  94  * - the %d34..%d62 fp registers are encoded as: %dx = %f(x - 32 + 1), ie.
  95  *   %d36 = %f5.
  96  * - ldind.i4/u4 needs to sign extend/clear out upper word -> slows things down
  97  * - ins->dreg can't be used as a scatch register in r4 opcodes since it might
  98  *   be a double precision register which has no single precision part.
  99  * - passing/returning structs is hard to implement, because:
 100  *   - the spec is very hard to understand
 101  *   - it requires knowledge about the fields of structure, needs to handle
 102  *     nested structures etc.
 103  */
 104
 105 /*
 106  * Possible optimizations:
 107  * - delay slot scheduling
 108  * - allocate large constants to registers
 109  * - use %o registers for local allocation
 110  * - implement unwinding through native frames
 111  * - add more mul/div/rem optimizations
 112  */
 113
 114 #ifndef __linux__
 115 #define MONO_SPARC_THR_TLS 1
 116 #endif
 117
 118 /*
 119  * There was a 64 bit bug in glib-2.2: g_bit_nth_msf (0, -1) would return 32,
 120  * causing infinite loops in dominator computation. So glib-2.4 is required.
 121  */
 122 #ifdef SPARCV9
 123 #if GLIB_MAJOR_VERSION == 2 && GLIB_MINOR_VERSION < 4
 124 #error "glib 2.4 or later is required for 64 bit mode."
 125 #endif
 126 #endif
 127
 128 #define NOT_IMPLEMENTED do { g_assert_not_reached (); } while (0)
 129
 130 #define ALIGN_TO(val,align) (((val) + ((align) - 1)) & ~((align) - 1))
 131
 132 #define SIGNAL_STACK_SIZE (64 * 1024)
 133
 134 #define STACK_BIAS MONO_SPARC_STACK_BIAS
 135
 136 #ifdef SPARCV9
 137
 138 /* %g1 is used by sparc_set */
 139 #define GP_SCRATCH_REG sparc_g4
 140 /* %f0 is used for parameter passing */
 141 #define FP_SCRATCH_REG sparc_f30
 142 #define ARGS_OFFSET (STACK_BIAS + 128)
 143
 144 #else
 145
 146 #define FP_SCRATCH_REG sparc_f0
 147 #define ARGS_OFFSET 68
 148 #define GP_SCRATCH_REG sparc_g1
 149
 150 #endif
 151
 152 /* Whenever the CPU supports v9 instructions */
 153 static gboolean sparcv9 = FALSE;
 154
 155 /* Whenever this is a 64bit executable */
 156 #if SPARCV9
 157 static gboolean v64 = TRUE;
 158 #else
 159 static gboolean v64 = FALSE;
 160 #endif
 161
 162 static gpointer mono_arch_get_lmf_addr (void);
 163
 164 static int
 165 mono_spillvar_offset_float (MonoCompile *cfg, int spillvar);
 166
 167 const char*
 168 mono_arch_regname (int reg) {
 169         static const char * rnames[] = {
 170                 "sparc_g0", "sparc_g1", "sparc_g2", "sparc_g3", "sparc_g4",
 171                 "sparc_g5", "sparc_g6", "sparc_g7", "sparc_o0", "sparc_o1",
 172                 "sparc_o2", "sparc_o3", "sparc_o4", "sparc_o5", "sparc_sp",
 173                 "sparc_call", "sparc_l0", "sparc_l1", "sparc_l2", "sparc_l3",
 174                 "sparc_l4", "sparc_l5", "sparc_l6", "sparc_l7", "sparc_i0",
 175                 "sparc_i1", "sparc_i2", "sparc_i3", "sparc_i4", "sparc_i5",
 176                 "sparc_fp", "sparc_retadr"
 177         };
 178         if (reg >= 0 && reg < 32)
 179                 return rnames [reg];
 180         return "unknown";
 181 }
 182
 183 /*
 184  * Initialize the cpu to execute managed code.
 185  */
 186 void
 187 mono_arch_cpu_init (void)
 188 {
 189         guint32 dummy;
 190         /* make sure sparcv9 is initialized for embedded use */
 191         mono_arch_cpu_optimizazions(&dummy);
 192 }
 193
 194 /*
 195  * This function returns the optimizations supported on this cpu.
 196  */
 197 guint32
 198 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 199 {
 200         char buf [1024];
 201         guint32 opts = 0;
 202
 203         *exclude_mask = 0;
 204
 205 #ifndef __linux__
 206         if (!sysinfo (SI_ISALIST, buf, 1024))
 207                 g_assert_not_reached ();
 208 #else
 209         /* From glibc.  If the getpagesize is 8192, we're on sparc64, which
 210          * (in)directly implies that we're a v9 or better.
 211          * Improvements to this are greatly accepted...
 212          * Also, we don't differentiate between v7 and v8.  I sense SIGILL
 213          * sniffing in my future.
 214          */
 215         if (getpagesize() == 8192)
 216                 strcpy (buf, "sparcv9");
 217         else
 218                 strcpy (buf, "sparcv8");
 219 #endif
 220
 221         /*
 222          * On some processors, the cmov instructions are even slower than the
 223          * normal ones...
 224          */
 225         if (strstr (buf, "sparcv9")) {
 226                 opts |= MONO_OPT_CMOV | MONO_OPT_FCMOV;
 227                 sparcv9 = TRUE;
 228         }
 229         else
 230                 *exclude_mask |= MONO_OPT_CMOV | MONO_OPT_FCMOV;
 231
 232         return opts;
 233 }
 234
 235 static void
 236 mono_sparc_break (void)
 237 {
 238 }
 239
 240 #ifdef __GNUC__
 241 #define flushi(addr)    __asm__ __volatile__ ("iflush %0"::"r"(addr):"memory")
 242 #else /* assume Sun's compiler */
 243 static void flushi(void *addr)
 244 {
 245     asm("flush %i0");
 246 }
 247 #endif
 248
 249 #ifndef __linux__
 250 void sync_instruction_memory(caddr_t addr, int len);
 251 #endif
 252
 253 void
 254 mono_arch_flush_icache (guint8 *code, gint size)
 255 {
 256 #ifndef __linux__
 257         /* Hopefully this is optimized based on the actual CPU */
 258         sync_instruction_memory (code, size);
 259 #else
 260         guint64 *p = (guint64*)code;
 261         guint64 *end = (guint64*)(code + ((size + 8) /8));
 262
 263         /*
 264          * FIXME: Flushing code in dword chunks in _slow_.
 265          */
 266         while (p < end)
 267 #ifdef __GNUC__
 268                 __asm__ __volatile__ ("iflush %0"::"r"(p++));
 269 #else
 270                         flushi (p ++);
 271 #endif
 272 #endif
 273 }
 274
 275 /*
 276  * mono_sparc_flushw:
 277  *
 278  * Flush all register windows to memory. Every register window is saved to
 279  * a 16 word area on the stack pointed to by its %sp register.
 280  */
 281 void
 282 mono_sparc_flushw (void)
 283 {
 284         static guint32 start [64];
 285         static int inited = 0;
 286         guint32 *code;
 287         static void (*flushw) (void);
 288
 289         if (!inited) {
 290                 code = start;
 291
 292                 sparc_save_imm (code, sparc_sp, -160, sparc_sp);
 293                 sparc_flushw (code);
 294                 sparc_ret (code);
 295                 sparc_restore_simple (code);
 296
 297                 g_assert ((code - start) < 64);
 298
 299                 flushw = (gpointer)start;
 300
 301                 inited = 1;
 302         }
 303
 304         flushw ();
 305 }
 306
 307 void
 308 mono_arch_flush_register_windows (void)
 309 {
 310         mono_sparc_flushw ();
 311 }
 312
 313 gboolean
 314 mono_arch_is_inst_imm (gint64 imm)
 315 {
 316         return sparc_is_imm13 (imm);
 317 }
 318
 319 gboolean
 320 mono_sparc_is_v9 (void) {
 321         return sparcv9;
 322 }
 323
 324 gboolean
 325 mono_sparc_is_sparc64 (void) {
 326         return v64;
 327 }
 328
 329 typedef enum {
 330         ArgInIReg,
 331         ArgInIRegPair,
 332         ArgInSplitRegStack,
 333         ArgInFReg,
 334         ArgInFRegPair,
 335         ArgOnStack,
 336         ArgOnStackPair,
 337         ArgInFloatReg,  /* V9 only */
 338         ArgInDoubleReg  /* V9 only */
 339 } ArgStorage;
 340
 341 typedef struct {
 342         gint16 offset;
 343         /* This needs to be offset by %i0 or %o0 depending on caller/callee */
 344         gint8  reg;
 345         ArgStorage storage;
 346         guint32 vt_offset; /* for valuetypes */
 347 } ArgInfo;
 348
 349 typedef struct {
 350         int nargs;
 351         guint32 stack_usage;
 352         guint32 reg_usage;
 353         ArgInfo ret;
 354         ArgInfo sig_cookie;
 355         ArgInfo args [1];
 356 } CallInfo;
 357
 358 #define DEBUG(a)
 359
 360 /* %o0..%o5 */
 361 #define PARAM_REGS 6
 362
 363 static void inline
 364 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean pair)
 365 {
 366         ainfo->offset = *stack_size;
 367
 368         if (!pair) {
 369                 if (*gr >= PARAM_REGS) {
 370                         ainfo->storage = ArgOnStack;
 371                 }
 372                 else {
 373                         ainfo->storage = ArgInIReg;
 374                         ainfo->reg = *gr;
 375                         (*gr) ++;
 376                 }
 377
 378                 /* Allways reserve stack space for parameters passed in registers */
 379                 (*stack_size) += sizeof (gpointer);
 380         }
 381         else {
 382                 if (*gr < PARAM_REGS - 1) {
 383                         /* A pair of registers */
 384                         ainfo->storage = ArgInIRegPair;
 385                         ainfo->reg = *gr;
 386                         (*gr) += 2;
 387                 }
 388                 else if (*gr >= PARAM_REGS) {
 389                         /* A pair of stack locations */
 390                         ainfo->storage = ArgOnStackPair;
 391                 }
 392                 else {
 393                         ainfo->storage = ArgInSplitRegStack;
 394                         ainfo->reg = *gr;
 395                         (*gr) ++;
 396                 }
 397
 398                 (*stack_size) += 2 * sizeof (gpointer);
 399         }
 400 }
 401
 402 #ifdef SPARCV9
 403
 404 #define FLOAT_PARAM_REGS 32
 405
 406 static void inline
 407 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean single)
 408 {
 409         ainfo->offset = *stack_size;
 410
 411         if (single) {
 412                 if (*gr >= FLOAT_PARAM_REGS) {
 413                         ainfo->storage = ArgOnStack;
 414                 }
 415                 else {
 416                         /* A single is passed in an even numbered fp register */
 417                         ainfo->storage = ArgInFloatReg;
 418                         ainfo->reg = *gr + 1;
 419                         (*gr) += 2;
 420                 }
 421         }
 422         else {
 423                 if (*gr < FLOAT_PARAM_REGS) {
 424                         /* A double register */
 425                         ainfo->storage = ArgInDoubleReg;
 426                         ainfo->reg = *gr;
 427                         (*gr) += 2;
 428                 }
 429                 else {
 430                         ainfo->storage = ArgOnStack;
 431                 }
 432         }
 433
 434         (*stack_size) += sizeof (gpointer);
 435 }
 436
 437 #endif
 438
 439 /*
 440  * get_call_info:
 441  *
 442  *  Obtain information about a call according to the calling convention.
 443  * For V8, see the "System V ABI, Sparc Processor Supplement" Sparc V8 version
 444  * document for more information.
 445  * For V9, see the "Low Level System Information (64-bit psABI)" chapter in
 446  * the 'Sparc Compliance Definition 2.4' document.
 447  */
 448 static CallInfo*
 449 get_call_info (MonoMethodSignature *sig, gboolean is_pinvoke)
 450 {
 451         guint32 i, gr, fr, simpletype;
 452         int n = sig->hasthis + sig->param_count;
 453         guint32 stack_size = 0;
 454         CallInfo *cinfo;
 455
 456         cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 457
 458         gr = 0;
 459         fr = 0;
 460
 461 #ifdef SPARCV9
 462         if (((sig->ret->type == MONO_TYPE_VALUETYPE) && !sig->ret->data.klass->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
 463                 /* The address of the return value is passed in %o0 */
 464                 add_general (&gr, &stack_size, &cinfo->ret, FALSE);
 465                 cinfo->ret.reg += sparc_i0;
 466         }
 467 #endif
 468
 469         /* this */
 470         if (sig->hasthis)
 471                 add_general (&gr, &stack_size, cinfo->args + 0, FALSE);
 472
 473         for (i = 0; i < sig->param_count; ++i) {
 474                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 475
 476                 if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 477                         /* Emit the signature cookie just before the implicit arguments */
 478                         add_general (&gr, &stack_size, &cinfo->sig_cookie, FALSE);
 479                         /* Prevent implicit arguments from being passed in registers */
 480                         gr = PARAM_REGS;
 481                 }
 482
 483                 DEBUG(printf("param %d: ", i));
 484                 if (sig->params [i]->byref) {
 485                         DEBUG(printf("byref\n"));
 486
 487                         add_general (&gr, &stack_size, ainfo, FALSE);
 488                         continue;
 489                 }
 490                 simpletype = sig->params [i]->type;
 491         enum_calc_size:
 492                 switch (simpletype) {
 493                 case MONO_TYPE_BOOLEAN:
 494                 case MONO_TYPE_I1:
 495                 case MONO_TYPE_U1:
 496                         add_general (&gr, &stack_size, ainfo, FALSE);
 497                         /* the value is in the ls byte */
 498                         ainfo->offset += sizeof (gpointer) - 1;
 499                         break;
 500                 case MONO_TYPE_I2:
 501                 case MONO_TYPE_U2:
 502                 case MONO_TYPE_CHAR:
 503                         add_general (&gr, &stack_size, ainfo, FALSE);
 504                         /* the value is in the ls word */
 505                         ainfo->offset += sizeof (gpointer) - 2;
 506                         break;
 507                 case MONO_TYPE_I4:
 508                 case MONO_TYPE_U4:
 509                         add_general (&gr, &stack_size, ainfo, FALSE);
 510                         /* the value is in the ls dword */
 511                         ainfo->offset += sizeof (gpointer) - 4;
 512                         break;
 513                 case MONO_TYPE_I:
 514                 case MONO_TYPE_U:
 515                 case MONO_TYPE_PTR:
 516                 case MONO_TYPE_CLASS:
 517                 case MONO_TYPE_OBJECT:
 518                 case MONO_TYPE_STRING:
 519                 case MONO_TYPE_SZARRAY:
 520                 case MONO_TYPE_ARRAY:
 521                         add_general (&gr, &stack_size, ainfo, FALSE);
 522                         break;
 523                 case MONO_TYPE_VALUETYPE:
 524                         if (sig->params [i]->data.klass->enumtype) {
 525                                 simpletype = sig->params [i]->data.klass->enum_basetype->type;
 526                                 goto enum_calc_size;
 527                         }
 528
 529 #ifdef SPARCV9
 530                         if (sig->pinvoke)
 531                                 NOT_IMPLEMENTED;
 532 #endif
 533                         add_general (&gr, &stack_size, ainfo, FALSE);
 534                         break;
 535                 case MONO_TYPE_TYPEDBYREF:
 536                         add_general (&gr, &stack_size, ainfo, FALSE);
 537                         break;
 538                 case MONO_TYPE_U8:
 539                 case MONO_TYPE_I8:
 540 #ifdef SPARCV9
 541                         add_general (&gr, &stack_size, ainfo, FALSE);
 542 #else
 543                         add_general (&gr, &stack_size, ainfo, TRUE);
 544 #endif
 545                         break;
 546                 case MONO_TYPE_R4:
 547 #ifdef SPARCV9
 548                         add_float (&fr, &stack_size, ainfo, TRUE);
 549                         gr ++;
 550 #else
 551                         /* single precision values are passed in integer registers */
 552                         add_general (&gr, &stack_size, ainfo, FALSE);
 553 #endif
 554                         break;
 555                 case MONO_TYPE_R8:
 556 #ifdef SPARCV9
 557                         add_float (&fr, &stack_size, ainfo, FALSE);
 558                         gr ++;
 559 #else
 560                         /* double precision values are passed in a pair of registers */
 561                         add_general (&gr, &stack_size, ainfo, TRUE);
 562 #endif
 563                         break;
 564                 default:
 565                         g_assert_not_reached ();
 566                 }
 567         }
 568
 569         /* return value */
 570         {
 571                 simpletype = sig->ret->type;
 572 enum_retvalue:
 573                 switch (simpletype) {
 574                 case MONO_TYPE_BOOLEAN:
 575                 case MONO_TYPE_I1:
 576                 case MONO_TYPE_U1:
 577                 case MONO_TYPE_I2:
 578                 case MONO_TYPE_U2:
 579                 case MONO_TYPE_CHAR:
 580                 case MONO_TYPE_I4:
 581                 case MONO_TYPE_U4:
 582                 case MONO_TYPE_I:
 583                 case MONO_TYPE_U:
 584                 case MONO_TYPE_PTR:
 585                 case MONO_TYPE_CLASS:
 586                 case MONO_TYPE_OBJECT:
 587                 case MONO_TYPE_SZARRAY:
 588                 case MONO_TYPE_ARRAY:
 589                 case MONO_TYPE_STRING:
 590                         cinfo->ret.storage = ArgInIReg;
 591                         cinfo->ret.reg = sparc_i0;
 592                         if (gr < 1)
 593                                 gr = 1;
 594                         break;
 595                 case MONO_TYPE_U8:
 596                 case MONO_TYPE_I8:
 597 #ifdef SPARCV9
 598                         cinfo->ret.storage = ArgInIReg;
 599                         cinfo->ret.reg = sparc_i0;
 600                         if (gr < 1)
 601                                 gr = 1;
 602 #else
 603                         cinfo->ret.storage = ArgInIRegPair;
 604                         cinfo->ret.reg = sparc_i0;
 605                         if (gr < 2)
 606                                 gr = 2;
 607 #endif
 608                         break;
 609                 case MONO_TYPE_R4:
 610                 case MONO_TYPE_R8:
 611                         cinfo->ret.storage = ArgInFReg;
 612                         cinfo->ret.reg = sparc_f0;
 613                         break;
 614                 case MONO_TYPE_VALUETYPE:
 615                         if (sig->ret->data.klass->enumtype) {
 616                                 simpletype = sig->ret->data.klass->enum_basetype->type;
 617                                 goto enum_retvalue;
 618                         }
 619                         if (v64) {
 620                                 if (sig->pinvoke)
 621                                         NOT_IMPLEMENTED;
 622                                 else
 623                                         /* Already done */
 624                                         ;
 625                         }
 626                         else
 627                                 cinfo->ret.storage = ArgOnStack;
 628                         break;
 629                 case MONO_TYPE_TYPEDBYREF:
 630                         if (v64) {
 631                                 if (sig->pinvoke)
 632                                         /* Same as a valuetype with size 24 */
 633                                         NOT_IMPLEMENTED;
 634                                 else
 635                                         /* Already done */
 636                                         ;
 637                         }
 638                         else
 639                                 cinfo->ret.storage = ArgOnStack;
 640                         break;
 641                 case MONO_TYPE_VOID:
 642                         break;
 643                 default:
 644                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 645                 }
 646         }
 647
 648         cinfo->stack_usage = stack_size;
 649         cinfo->reg_usage = gr;
 650         return cinfo;
 651 }
 652
 653 static gboolean
 654 is_regsize_var (MonoType *t) {
 655         if (t->byref)
 656                 return TRUE;
 657         switch (t->type) {
 658         case MONO_TYPE_BOOLEAN:
 659         case MONO_TYPE_CHAR:
 660         case MONO_TYPE_I1:
 661         case MONO_TYPE_U1:
 662         case MONO_TYPE_I2:
 663         case MONO_TYPE_U2:
 664         case MONO_TYPE_I4:
 665         case MONO_TYPE_U4:
 666         case MONO_TYPE_I:
 667         case MONO_TYPE_U:
 668                 return TRUE;
 669         case MONO_TYPE_OBJECT:
 670         case MONO_TYPE_STRING:
 671         case MONO_TYPE_CLASS:
 672         case MONO_TYPE_SZARRAY:
 673         case MONO_TYPE_ARRAY:
 674                 return TRUE;
 675         case MONO_TYPE_VALUETYPE:
 676                 if (t->data.klass->enumtype)
 677                         return is_regsize_var (t->data.klass->enum_basetype);
 678                 return FALSE;
 679 #ifdef SPARCV9
 680         case MONO_TYPE_I8:
 681         case MONO_TYPE_U8:
 682                 return TRUE;
 683 #endif
 684         }
 685         return FALSE;
 686 }
 687
 688 GList *
 689 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 690 {
 691         GList *vars = NULL;
 692         int i;
 693
 694         /*
 695          * FIXME: If an argument is allocated to a register, then load it from the
 696          * stack in the prolog.
 697          */
 698
 699         for (i = 0; i < cfg->num_varinfo; i++) {
 700                 MonoInst *ins = cfg->varinfo [i];
 701                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 702
 703                 /* unused vars */
 704                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 705                         continue;
 706
 707                 /* FIXME: Make arguments on stack allocateable to registers */
 708                 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT) || (ins->opcode == OP_REGVAR) || (ins->opcode == OP_ARG))
 709                         continue;
 710
 711                 if (is_regsize_var (ins->inst_vtype)) {
 712                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 713                         g_assert (i == vmv->idx);
 714
 715                         vars = mono_varlist_insert_sorted (cfg, vars, vmv, FALSE);
 716                 }
 717         }
 718
 719         return vars;
 720 }
 721
 722 GList *
 723 mono_arch_get_global_int_regs (MonoCompile *cfg)
 724 {
 725         GList *regs = NULL;
 726         int i;
 727         MonoMethodSignature *sig;
 728         CallInfo *cinfo;
 729
 730         sig = cfg->method->signature;
 731
 732         cinfo = get_call_info (sig, FALSE);
 733
 734         /* Use unused input registers */
 735         for (i = cinfo->reg_usage; i < 6; ++i)
 736                 regs = g_list_prepend (regs, GUINT_TO_POINTER (sparc_i0 + i));
 737
 738         /* Use %l0..%l3 as global registers */
 739         for (i = sparc_l0; i < sparc_l4; ++i)
 740                 regs = g_list_prepend (regs, GUINT_TO_POINTER (i));
 741
 742         g_free (cinfo);
 743
 744         return regs;
 745 }
 746
 747 /*
 748  * mono_arch_regalloc_cost:
 749  *
 750  *  Return the cost, in number of memory references, of the action of
 751  * allocating the variable VMV into a register during global register
 752  * allocation.
 753  */
 754 guint32
 755 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 756 {
 757         return 0;
 758 }
 759
 760 /*
 761  * Set var information according to the calling convention. sparc version.
 762  * The locals var stuff should most likely be split in another method.
 763  */
 764 void
 765 mono_arch_allocate_vars (MonoCompile *m)
 766 {
 767         MonoMethodSignature *sig;
 768         MonoMethodHeader *header;
 769         MonoInst *inst;
 770         int i, offset, size, align, curinst;
 771         CallInfo *cinfo;
 772
 773         header = ((MonoMethodNormal *)m->method)->header;
 774
 775         sig = m->method->signature;
 776
 777         cinfo = get_call_info (sig, FALSE);
 778
 779         if (sig->ret->type != MONO_TYPE_VOID) {
 780                 switch (cinfo->ret.storage) {
 781                 case ArgInIReg:
 782                 case ArgInFReg:
 783                 case ArgInIRegPair:
 784                         m->ret->opcode = OP_REGVAR;
 785                         m->ret->inst_c0 = cinfo->ret.reg;
 786                         break;
 787                 case ArgOnStack:
 788 #ifdef SPARCV9
 789                         g_assert_not_reached ();
 790 #else
 791                         /* valuetypes */
 792                         m->ret->opcode = OP_REGOFFSET;
 793                         m->ret->inst_basereg = sparc_fp;
 794                         m->ret->inst_offset = 64;
 795 #endif
 796                         break;
 797                 default:
 798                         NOT_IMPLEMENTED;
 799                 }
 800                 m->ret->dreg = m->ret->inst_c0;
 801         }
 802
 803         /*
 804          * We use the ABI calling conventions for managed code as well.
 805          * Exception: valuetypes are never returned in registers on V9.
 806          * FIXME: Use something more optimized.
 807          */
 808
 809         /* Locals are allocated backwards from %fp */
 810         m->frame_reg = sparc_fp;
 811         offset = 0;
 812
 813         /*
 814          * Reserve a stack slot for holding information used during exception
 815          * handling.
 816          */
 817         if (header->num_clauses)
 818                 offset += sizeof (gpointer) * 2;
 819
 820         if (m->method->save_lmf) {
 821                 offset += sizeof (MonoLMF);
 822                 m->arch.lmf_offset = offset;
 823         }
 824
 825         curinst = m->locals_start;
 826         for (i = curinst; i < m->num_varinfo; ++i) {
 827                 inst = m->varinfo [i];
 828
 829                 if (inst->opcode == OP_REGVAR) {
 830                         //g_print ("allocating local %d to %s\n", i, mono_arch_regname (inst->dreg));
 831                         continue;
 832                 }
 833
 834                 /* inst->unused indicates native sized value types, this is used by the
 835                 * pinvoke wrappers when they call functions returning structure */
 836                 if (inst->unused && MONO_TYPE_ISSTRUCT (inst->inst_vtype) && inst->inst_vtype->type != MONO_TYPE_TYPEDBYREF)
 837                         size = mono_class_native_size (inst->inst_vtype->data.klass, &align);
 838                 else
 839                         size = mono_type_stack_size (inst->inst_vtype, &align);
 840
 841                 /*
 842                  * This is needed since structures containing doubles must be doubleword
 843          * aligned.
 844                  * FIXME: Do this only if needed.
 845                  */
 846                 if (MONO_TYPE_ISSTRUCT (inst->inst_vtype))
 847                         align = 8;
 848
 849                 /*
 850                  * variables are accessed as negative offsets from %fp, so increase
 851                  * the offset before assigning it to a variable
 852                  */
 853                 offset += size;
 854
 855                 offset += align - 1;
 856                 offset &= ~(align - 1);
 857                 inst->opcode = OP_REGOFFSET;
 858                 inst->inst_basereg = sparc_fp;
 859                 inst->inst_offset = STACK_BIAS + -offset;
 860
 861                 //g_print ("allocating local %d to [%s - %d]\n", i, mono_arch_regname (inst->inst_basereg), - inst->inst_offset);
 862         }
 863
 864         if (sig->call_convention == MONO_CALL_VARARG) {
 865                 m->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
 866         }
 867
 868         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 869                 inst = m->varinfo [i];
 870                 if (inst->opcode != OP_REGVAR) {
 871                         ArgInfo *ainfo = &cinfo->args [i];
 872                         gboolean inreg = TRUE;
 873                         MonoType *arg_type;
 874                         ArgStorage storage;
 875
 876                         if (sig->hasthis && (i == 0))
 877                                 arg_type = &mono_defaults.object_class->byval_arg;
 878                         else
 879                                 arg_type = sig->params [i - sig->hasthis];
 880
 881 #ifndef SPARCV9
 882                         if (!arg_type->byref && ((arg_type->type == MONO_TYPE_R4)
 883                                                                          || (arg_type->type == MONO_TYPE_R8)))
 884                                 /*
 885                                  * Since float arguments are passed in integer registers, we need to
 886                                  * save them to the stack in the prolog.
 887                                  */
 888                                 inreg = FALSE;
 889 #endif
 890
 891                         /* FIXME: Allocate volatile arguments to registers */
 892                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 893                                 inreg = FALSE;
 894
 895                         if (MONO_TYPE_ISSTRUCT (arg_type))
 896                                 /* FIXME: this isn't needed */
 897                                 inreg = FALSE;
 898
 899                         inst->opcode = OP_REGOFFSET;
 900
 901                         if (!inreg)
 902                                 storage = ArgOnStack;
 903                         else
 904                                 storage = ainfo->storage;
 905
 906                         switch (storage) {
 907                         case ArgInIReg:
 908                         case ArgInIRegPair:
 909                                 inst->opcode = OP_REGVAR;
 910                                 inst->dreg = sparc_i0 + ainfo->reg;
 911                                 break;
 912                         case ArgInFloatReg:
 913                         case ArgInDoubleReg:
 914                                 /*
 915                                  * Since float regs are volatile, we save the arguments to
 916                                  * the stack in the prolog.
 917                                  * FIXME: Avoid this if the method contains no calls.
 918                                  */
 919                         case ArgOnStack:
 920                         case ArgOnStackPair:
 921                         case ArgInSplitRegStack:
 922                                 /* Split arguments are saved to the stack in the prolog */
 923                                 inst->opcode = OP_REGOFFSET;
 924                                 /* in parent frame */
 925                                 inst->inst_basereg = sparc_fp;
 926                                 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
 927
 928                                 if (!arg_type->byref && (arg_type->type == MONO_TYPE_R8)) {
 929                                         /*
 930                                          * It is very hard to load doubles from non-doubleword aligned
 931                                          * memory locations. So if the offset is misaligned, we copy the
 932                                          * argument to a stack location in the prolog.
 933                                          */
 934                                         if ((inst->inst_offset - STACK_BIAS) % 8) {
 935                                                 inst->inst_basereg = sparc_fp;
 936                                                 offset += 8;
 937                                                 align = 8;
 938                                                 offset += align - 1;
 939                                                 offset &= ~(align - 1);
 940                                                 inst->inst_offset = STACK_BIAS + -offset;
 941
 942                                         }
 943                                 }
 944                                 break;
 945                         default:
 946                                 NOT_IMPLEMENTED;
 947                         }
 948
 949                         if (MONO_TYPE_ISSTRUCT (arg_type)) {
 950                                 /* Add a level of indirection */
 951                                 /*
 952                                  * It would be easier to add OP_LDIND_I here, but ldind_i instructions
 953                                  * are destructively modified in a lot of places in inssel.brg.
 954                                  */
 955                                 MonoInst *indir;
 956                                 MONO_INST_NEW (m, indir, 0);
 957                                 *indir = *inst;
 958                                 inst->opcode = OP_SPARC_INARG_VT;
 959                                 inst->inst_left = indir;
 960                         }
 961                 }
 962         }
 963
 964         /*
 965          * spillvars are stored between the normal locals and the storage reserved
 966          * by the ABI.
 967          */
 968
 969         m->stack_offset = offset;
 970
 971         /* Add a properly aligned dword for use by int<->float conversion opcodes */
 972         m->spill_count ++;
 973         mono_spillvar_offset_float (m, 0);
 974
 975         g_free (cinfo);
 976 }
 977
 978 /*
 979  * take the arguments and generate the arch-specific
 980  * instructions to properly call the function in call.
 981  * This includes pushing, moving arguments to the right register
 982  * etc.
 983  */
 984 MonoCallInst*
 985 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
 986         MonoInst *arg, *in;
 987         MonoMethodSignature *sig;
 988         int i, n;
 989         CallInfo *cinfo;
 990         ArgInfo *ainfo;
 991         guint32 extra_space = 0;
 992
 993         sig = call->signature;
 994         n = sig->param_count + sig->hasthis;
 995
 996         cinfo = get_call_info (sig, sig->pinvoke);
 997
 998         for (i = 0; i < n; ++i) {
 999                 ainfo = cinfo->args + i;
1000                 if (is_virtual && i == 0) {
1001                         /* the argument will be attached to the call instruction */
1002                         in = call->args [i];
1003                 } else {
1004                         if ((sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1005                                 /* FIXME: Test varargs with 0 implicit args */
1006                                 /* FIXME: Test interaction with hasthis */
1007                                 /* Emit the signature cookie just before the first implicit argument */
1008                                 MonoInst *sig_arg;
1009                                 /* FIXME: Add support for signature tokens to AOT */
1010                                 cfg->disable_aot = TRUE;
1011                                 /* We allways pass the signature on the stack for simplicity */
1012                                 MONO_INST_NEW (cfg, arg, OP_SPARC_OUTARG_MEM);
1013                                 arg->inst_basereg = sparc_sp;
1014                                 arg->inst_imm = ARGS_OFFSET + cinfo->sig_cookie.offset;
1015                                 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1016                                 sig_arg->inst_p0 = call->signature;
1017                                 arg->inst_left = sig_arg;
1018                                 arg->type = STACK_PTR;
1019                                 /* prepend, so they get reversed */
1020                                 arg->next = call->out_args;
1021                                 call->out_args = arg;
1022                         }
1023
1024                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1025                         in = call->args [i];
1026                         arg->cil_code = in->cil_code;
1027                         arg->inst_left = in;
1028                         arg->type = in->type;
1029                         /* prepend, we'll need to reverse them later */
1030                         arg->next = call->out_args;
1031                         call->out_args = arg;
1032
1033                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1034                                 MonoInst *inst;
1035                                 gint align;
1036                                 guint32 offset, pad;
1037                                 guint32 size;
1038
1039 #ifdef SPARCV9
1040                                 if (sig->pinvoke)
1041                                         NOT_IMPLEMENTED;
1042 #endif
1043
1044                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1045                                         size = sizeof (MonoTypedRef);
1046                                         align = sizeof (gpointer);
1047                                 }
1048                                 else
1049                                 if (sig->pinvoke)
1050                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1051                                 else
1052                                         size = mono_type_stack_size (&in->klass->byval_arg, &align);
1053
1054                                 /*
1055                                  * We use OP_OUTARG_VT to copy the valuetype to a stack location, then
1056                                  * use the normal OUTARG opcodes to pass the address of the location to
1057                                  * the callee.
1058                                  */
1059                                 MONO_INST_NEW (cfg, inst, OP_OUTARG_VT);
1060                                 inst->inst_left = in;
1061
1062                                 /* The first 6 argument locations are reserved */
1063                                 if (cinfo->stack_usage < 6 * sizeof (gpointer))
1064                                         cinfo->stack_usage = 6 * sizeof (gpointer);
1065
1066                                 offset = ALIGN_TO ((ARGS_OFFSET - STACK_BIAS) + cinfo->stack_usage, align);
1067                                 pad = offset - ((ARGS_OFFSET - STACK_BIAS) + cinfo->stack_usage);
1068
1069                                 inst->inst_c1 = STACK_BIAS + offset;
1070                                 inst->unused = size;
1071                                 arg->inst_left = inst;
1072
1073                                 cinfo->stack_usage += size;
1074                                 cinfo->stack_usage += pad;
1075                         }
1076
1077                         switch (ainfo->storage) {
1078                         case ArgInIReg:
1079                         case ArgInFReg:
1080                         case ArgInIRegPair:
1081                                 if (ainfo->storage == ArgInIRegPair)
1082                                         arg->opcode = OP_SPARC_OUTARG_REGPAIR;
1083                                 arg->unused = sparc_o0 + ainfo->reg;
1084                                 call->used_iregs |= 1 << ainfo->reg;
1085
1086                                 if ((i >= sig->hasthis) && (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)) {
1087                                         /*
1088                                          * The OUTARG (freg) implementation needs an extra dword to store
1089                                          * the temporary value.
1090                                          */
1091                                         extra_space += 8;
1092                                 }
1093                                 break;
1094                         case ArgOnStack:
1095                                 arg->opcode = OP_SPARC_OUTARG_MEM;
1096                                 break;
1097                         case ArgOnStackPair:
1098                                 arg->opcode = OP_SPARC_OUTARG_MEMPAIR;
1099                                 break;
1100                         case ArgInSplitRegStack:
1101                                 arg->opcode = OP_SPARC_OUTARG_SPLIT_REG_STACK;
1102                                 arg->unused = sparc_o0 + ainfo->reg;
1103                                 call->used_iregs |= 1 << ainfo->reg;
1104                                 break;
1105                         case ArgInFloatReg:
1106                                 arg->opcode = OP_SPARC_OUTARG_FLOAT_REG;
1107                                 arg->unused = sparc_f0 + ainfo->reg;
1108                                 break;
1109                         case ArgInDoubleReg:
1110                                 arg->opcode = OP_SPARC_OUTARG_DOUBLE_REG;
1111                                 arg->unused = sparc_f0 + ainfo->reg;
1112                                 break;
1113                         default:
1114                                 NOT_IMPLEMENTED;
1115                         }
1116
1117                         arg->inst_basereg = sparc_sp;
1118                         arg->inst_imm = ARGS_OFFSET + ainfo->offset;
1119                 }
1120         }
1121
1122         /*
1123          * Reverse the call->out_args list.
1124          */
1125         {
1126                 MonoInst *prev = NULL, *list = call->out_args, *next;
1127                 while (list) {
1128                         next = list->next;
1129                         list->next = prev;
1130                         prev = list;
1131                         list = next;
1132                 }
1133                 call->out_args = prev;
1134         }
1135         call->stack_usage = cinfo->stack_usage + extra_space;
1136         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1137         cfg->flags |= MONO_CFG_HAS_CALLS;
1138
1139         g_free (cinfo);
1140         return call;
1141 }
1142
1143 /* Map opcode to the sparc condition codes */
1144 static inline SparcCond
1145 opcode_to_sparc_cond (int opcode)
1146 {
1147         switch (opcode) {
1148         case OP_FBGE:
1149                 return sparc_fbge;
1150         case OP_FBLE:
1151                 return sparc_fble;
1152         case OP_FBEQ:
1153         case OP_FCEQ:
1154                 return sparc_fbe;
1155         case OP_FBLT:
1156         case OP_FCLT:
1157         case OP_FCLT_UN:
1158                 return sparc_fbl;
1159         case OP_FBGT:
1160         case OP_FCGT:
1161         case OP_FCGT_UN:
1162                 return sparc_fbg;
1163         case CEE_BEQ:
1164         case OP_IBEQ:
1165         case OP_CEQ:
1166         case OP_ICEQ:
1167         case OP_COND_EXC_EQ:
1168                 return sparc_be;
1169         case CEE_BNE_UN:
1170         case OP_COND_EXC_NE_UN:
1171         case OP_IBNE_UN:
1172                 return sparc_bne;
1173         case CEE_BLT:
1174         case OP_IBLT:
1175         case OP_CLT:
1176         case OP_ICLT:
1177         case OP_COND_EXC_LT:
1178                 return sparc_bl;
1179         case CEE_BLT_UN:
1180         case OP_IBLT_UN:
1181         case OP_CLT_UN:
1182         case OP_ICLT_UN:
1183         case OP_COND_EXC_LT_UN:
1184                 return sparc_blu;
1185         case CEE_BGT:
1186         case OP_IBGT:
1187         case OP_CGT:
1188         case OP_ICGT:
1189         case OP_COND_EXC_GT:
1190                 return sparc_bg;
1191         case CEE_BGT_UN:
1192         case OP_IBGT_UN:
1193         case OP_CGT_UN:
1194         case OP_ICGT_UN:
1195         case OP_COND_EXC_GT_UN:
1196                 return sparc_bgu;
1197         case CEE_BGE:
1198         case OP_IBGE:
1199         case OP_COND_EXC_GE:
1200                 return sparc_bge;
1201         case CEE_BGE_UN:
1202         case OP_IBGE_UN:
1203         case OP_COND_EXC_GE_UN:
1204                 return sparc_beu;
1205         case CEE_BLE:
1206         case OP_IBLE:
1207         case OP_COND_EXC_LE:
1208                 return sparc_ble;
1209         case CEE_BLE_UN:
1210         case OP_IBLE_UN:
1211         case OP_COND_EXC_LE_UN:
1212                 return sparc_bleu;
1213         case OP_COND_EXC_OV:
1214         case OP_COND_EXC_IOV:
1215                 return sparc_bvs;
1216         case OP_COND_EXC_C:
1217         case OP_COND_EXC_IC:
1218                 return sparc_bcs;
1219         case OP_COND_EXC_NO:
1220         case OP_COND_EXC_NC:
1221                 NOT_IMPLEMENTED;
1222         default:
1223                 g_assert_not_reached ();
1224                 return sparc_be;
1225         }
1226 }
1227
1228 #define COMPUTE_DISP(ins) \
1229 if (ins->flags & MONO_INST_BRLABEL) { \
1230         if (ins->inst_i0->inst_c0) \
1231            disp = (ins->inst_i0->inst_c0 - ((guint8*)code - cfg->native_code)) >> 2; \
1232         else { \
1233             disp = 0; \
1234                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1235         } \
1236 } else { \
1237         if (ins->inst_true_bb->native_offset) \
1238            disp = (ins->inst_true_bb->native_offset - ((guint8*)code - cfg->native_code)) >> 2; \
1239         else { \
1240             disp = 0; \
1241                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1242         } \
1243 }
1244
1245 #ifdef SPARCV9
1246 #define DEFAULT_ICC sparc_xcc_short
1247 #else
1248 #define DEFAULT_ICC sparc_icc_short
1249 #endif
1250
1251 #ifdef SPARCV9
1252 #define EMIT_COND_BRANCH_ICC(ins,cond,annul,filldelay,icc) \
1253     do { \
1254         gint32 disp; \
1255         guint32 predict; \
1256         COMPUTE_DISP(ins); \
1257         predict = (disp != 0) ? 1 : 0; \
1258         g_assert (sparc_is_imm19 (disp)); \
1259         sparc_branchp (code, (annul), cond, icc, (predict), disp); \
1260         if (filldelay) sparc_nop (code); \
1261     } while (0)
1262 #define EMIT_COND_BRANCH(ins,cond,annul,filldelay) EMIT_COND_BRANCH_ICC ((ins), (cond), (annul), (filldelay), (sparc_xcc_short))
1263 #define EMIT_FLOAT_COND_BRANCH(ins,cond,annul,filldelay) \
1264     do { \
1265         gint32 disp; \
1266         guint32 predict; \
1267         COMPUTE_DISP(ins); \
1268         predict = (disp != 0) ? 1 : 0; \
1269         g_assert (sparc_is_imm19 (disp)); \
1270         sparc_fbranch (code, (annul), cond, disp); \
1271         if (filldelay) sparc_nop (code); \
1272     } while (0)
1273 #else
1274 #define EMIT_COND_BRANCH_ICC(ins,cond,annul,filldelay,icc) g_assert_not_reached ()
1275 #define EMIT_COND_BRANCH_GENERAL(ins,bop,cond,annul,filldelay) \
1276     do { \
1277         gint32 disp; \
1278         COMPUTE_DISP(ins); \
1279         g_assert (sparc_is_imm22 (disp)); \
1280         sparc_ ## bop (code, (annul), cond, disp); \
1281         if (filldelay) sparc_nop (code); \
1282     } while (0)
1283 #define EMIT_COND_BRANCH(ins,cond,annul,filldelay) EMIT_COND_BRANCH_GENERAL((ins),branch,(cond),annul,filldelay)
1284 #define EMIT_FLOAT_COND_BRANCH(ins,cond,annul,filldelay) EMIT_COND_BRANCH_GENERAL((ins),fbranch,(cond),annul,filldelay)
1285 #endif
1286
1287 #define EMIT_COND_BRANCH_PREDICTED(ins,cond,annul,filldelay) \
1288     do { \
1289             gint32 disp; \
1290         guint32 predict; \
1291         COMPUTE_DISP(ins); \
1292         predict = (disp != 0) ? 1 : 0; \
1293         g_assert (sparc_is_imm19 (disp)); \
1294                 sparc_branchp (code, (annul), (cond), DEFAULT_ICC, (predict), disp); \
1295         if (filldelay) sparc_nop (code); \
1296     } while (0)
1297
1298 #define EMIT_COND_BRANCH_BPR(ins,bop,predict,annul,filldelay) \
1299     do { \
1300             gint32 disp; \
1301         COMPUTE_DISP(ins); \
1302                 g_assert (sparc_is_imm22 (disp)); \
1303                 sparc_ ## bop (code, (annul), (predict), ins->sreg1, disp); \
1304         if (filldelay) sparc_nop (code); \
1305     } while (0)
1306
1307 /* emit an exception if condition is fail */
1308 /*
1309  * We put the exception throwing code out-of-line, at the end of the method
1310  */
1311 #define EMIT_COND_SYSTEM_EXCEPTION_GENERAL(ins,cond,sexc_name,filldelay,icc) do {     \
1312                 mono_add_patch_info (cfg, (guint8*)(code) - (cfg)->native_code,   \
1313                                     MONO_PATCH_INFO_EXC, sexc_name);  \
1314         if (sparcv9) { \
1315            sparc_branchp (code, 0, (cond), (icc), 0, 0); \
1316         } \
1317         else { \
1318                         sparc_branch (code, 0, cond, 0);     \
1319         } \
1320         if (filldelay) sparc_nop (code);     \
1321         } while (0);
1322
1323 #define EMIT_COND_SYSTEM_EXCEPTION(ins,cond,sexc_name) EMIT_COND_SYSTEM_EXCEPTION_GENERAL(ins,cond,sexc_name,TRUE,DEFAULT_ICC)
1324
1325 #define EMIT_COND_SYSTEM_EXCEPTION_BPR(ins,bop,sexc_name) do { \
1326                 mono_add_patch_info (cfg, (guint8*)(code) - (cfg)->native_code,   \
1327                                     MONO_PATCH_INFO_EXC, sexc_name);  \
1328                 sparc_ ## bop (code, FALSE, FALSE, ins->sreg1, 0); \
1329         sparc_nop (code);    \
1330 } while (0);
1331
1332 #define EMIT_ALU_IMM(ins,op,setcc) do { \
1333                         if (sparc_is_imm13 ((ins)->inst_imm)) \
1334                                 sparc_ ## op ## _imm (code, (setcc), (ins)->sreg1, ins->inst_imm, (ins)->dreg); \
1335                         else { \
1336                                 sparc_set (code, ins->inst_imm, sparc_o7); \
1337                                 sparc_ ## op (code, (setcc), (ins)->sreg1, sparc_o7, (ins)->dreg); \
1338                         } \
1339 } while (0);
1340
1341 #define EMIT_LOAD_MEMBASE(ins,op) do { \
1342                         if (sparc_is_imm13 (ins->inst_offset)) \
1343                                 sparc_ ## op ## _imm (code, ins->inst_basereg, ins->inst_offset, ins->dreg); \
1344                         else { \
1345                                 sparc_set (code, ins->inst_offset, sparc_o7); \
1346                                 sparc_ ## op (code, ins->inst_basereg, sparc_o7, ins->dreg); \
1347                         } \
1348 } while (0);
1349
1350 /* max len = 5 */
1351 #define EMIT_STORE_MEMBASE_IMM(ins,op) do { \
1352                         guint32 sreg; \
1353                         if (ins->inst_imm == 0) \
1354                                 sreg = sparc_g0; \
1355                         else { \
1356                                 sparc_set (code, ins->inst_imm, sparc_o7); \
1357                                 sreg = sparc_o7; \
1358                         } \
1359                         if (!sparc_is_imm13 (ins->inst_offset)) { \
1360                                 sparc_set (code, ins->inst_offset, GP_SCRATCH_REG); \
1361                                 sparc_ ## op (code, sreg, ins->inst_destbasereg, GP_SCRATCH_REG); \
1362                         } \
1363                         else \
1364                                 sparc_ ## op ## _imm (code, sreg, ins->inst_destbasereg, ins->inst_offset); \
1365                                                                                                                                                                                  } while (0);
1366
1367 #define EMIT_STORE_MEMBASE_REG(ins,op) do { \
1368                         if (!sparc_is_imm13 (ins->inst_offset)) { \
1369                                 sparc_set (code, ins->inst_offset, sparc_o7); \
1370                                 sparc_ ## op (code, ins->sreg1, ins->inst_destbasereg, sparc_o7); \
1371                         } \
1372                                   else \
1373                                 sparc_ ## op ## _imm (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset); \
1374                                                                                                                                                                                  } while (0);
1375
1376 #define EMIT_CALL() do { \
1377     if (v64) { \
1378         sparc_set_template (code, sparc_o7); \
1379         sparc_jmpl (code, sparc_o7, sparc_g0, sparc_o7); \
1380     } \
1381     else { \
1382         sparc_call_simple (code, 0); \
1383     } \
1384     sparc_nop (code); \
1385 } while (0);
1386
1387 extern gboolean mono_compile_aot;
1388
1389 /*
1390  * A call template is 7 instructions long, so we want to avoid it if possible.
1391  */
1392 static guint32*
1393 emit_call (MonoCompile *cfg, guint32 *code, guint32 patch_type, gconstpointer data)
1394 {
1395         gpointer target;
1396
1397         /* FIXME: This only works if the target method is already compiled */
1398         if (0 && v64 && !mono_compile_aot) {
1399                 MonoJumpInfo patch_info;
1400
1401                 patch_info.type = patch_type;
1402                 patch_info.data.target = data;
1403
1404                 target = mono_resolve_patch_target (cfg->method, cfg->domain, NULL, &patch_info, FALSE);
1405
1406                 /* FIXME: Add optimizations if the target is close enough */
1407                 sparc_set (code, target, sparc_o7);
1408                 sparc_jmpl (code, sparc_o7, sparc_g0, sparc_o7);
1409                 sparc_nop (code);
1410         }
1411         else {
1412                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, patch_type, data);
1413                 EMIT_CALL ();
1414         }
1415
1416         return code;
1417 }
1418
1419 static void
1420 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1421 {
1422         MonoInst *ins, *last_ins = NULL;
1423         ins = bb->code;
1424
1425         while (ins) {
1426
1427                 switch (ins->opcode) {
1428                 case OP_MUL_IMM:
1429                         /* remove unnecessary multiplication with 1 */
1430                         if (ins->inst_imm == 1) {
1431                                 if (ins->dreg != ins->sreg1) {
1432                                         ins->opcode = OP_MOVE;
1433                                 } else {
1434                                         last_ins->next = ins->next;
1435                                         ins = ins->next;
1436                                         continue;
1437                                 }
1438                         }
1439                         break;
1440 #ifndef SPARCV9
1441                 case OP_LOAD_MEMBASE:
1442                 case OP_LOADI4_MEMBASE:
1443                         /*
1444                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1445                          * OP_LOAD_MEMBASE offset(basereg), reg
1446                          */
1447                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1448                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1449                             ins->inst_basereg == last_ins->inst_destbasereg &&
1450                             ins->inst_offset == last_ins->inst_offset) {
1451                                 if (ins->dreg == last_ins->sreg1) {
1452                                         last_ins->next = ins->next;
1453                                         ins = ins->next;
1454                                         continue;
1455                                 } else {
1456                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1457                                         ins->opcode = OP_MOVE;
1458                                         ins->sreg1 = last_ins->sreg1;
1459                                 }
1460
1461                         /*
1462                          * Note: reg1 must be different from the basereg in the second load
1463                          * OP_LOAD_MEMBASE offset(basereg), reg1
1464                          * OP_LOAD_MEMBASE offset(basereg), reg2
1465                          * -->
1466                          * OP_LOAD_MEMBASE offset(basereg), reg1
1467                          * OP_MOVE reg1, reg2
1468                          */
1469                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
1470                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
1471                               ins->inst_basereg != last_ins->dreg &&
1472                               ins->inst_basereg == last_ins->inst_basereg &&
1473                               ins->inst_offset == last_ins->inst_offset) {
1474
1475                                 if (ins->dreg == last_ins->dreg) {
1476                                         last_ins->next = ins->next;
1477                                         ins = ins->next;
1478                                         continue;
1479                                 } else {
1480                                         ins->opcode = OP_MOVE;
1481                                         ins->sreg1 = last_ins->dreg;
1482                                 }
1483
1484                                 //g_assert_not_reached ();
1485
1486 #if 0
1487                         /*
1488                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1489                          * OP_LOAD_MEMBASE offset(basereg), reg
1490                          * -->
1491                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1492                          * OP_ICONST reg, imm
1493                          */
1494                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
1495                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
1496                                    ins->inst_basereg == last_ins->inst_destbasereg &&
1497                                    ins->inst_offset == last_ins->inst_offset) {
1498                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1499                                 ins->opcode = OP_ICONST;
1500                                 ins->inst_c0 = last_ins->inst_imm;
1501                                 g_assert_not_reached (); // check this rule
1502 #endif
1503                         }
1504                         break;
1505 #endif
1506                 case OP_LOADU1_MEMBASE:
1507                 case OP_LOADI1_MEMBASE:
1508                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
1509                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1510                                         ins->inst_offset == last_ins->inst_offset) {
1511                                 if (ins->dreg == last_ins->sreg1) {
1512                                         last_ins->next = ins->next;
1513                                         ins = ins->next;
1514                                         continue;
1515                                 } else {
1516                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1517                                         ins->opcode = OP_MOVE;
1518                                         ins->sreg1 = last_ins->sreg1;
1519                                 }
1520                         }
1521                         break;
1522                 case OP_LOADU2_MEMBASE:
1523                 case OP_LOADI2_MEMBASE:
1524                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
1525                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1526                                         ins->inst_offset == last_ins->inst_offset) {
1527                                 if (ins->dreg == last_ins->sreg1) {
1528                                         last_ins->next = ins->next;
1529                                         ins = ins->next;
1530                                         continue;
1531                                 } else {
1532                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1533                                         ins->opcode = OP_MOVE;
1534                                         ins->sreg1 = last_ins->sreg1;
1535                                 }
1536                         }
1537                         break;
1538                 case OP_STOREI4_MEMBASE_IMM:
1539                         /* Convert pairs of 0 stores to a dword 0 store */
1540                         /* Used when initializing temporaries */
1541                         /* We know sparc_fp is dword aligned */
1542                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM) &&
1543                                 (ins->inst_destbasereg == last_ins->inst_destbasereg) &&
1544                                 (ins->inst_destbasereg == sparc_fp) &&
1545                                 (ins->inst_offset < 0) &&
1546                                 ((ins->inst_offset % 8) == 0) &&
1547                                 ((ins->inst_offset == last_ins->inst_offset - 4)) &&
1548                                 (ins->inst_imm == 0) &&
1549                                 (last_ins->inst_imm == 0)) {
1550                                 if (sparcv9) {
1551                                         last_ins->opcode = OP_STOREI8_MEMBASE_IMM;
1552                                         last_ins->inst_offset = ins->inst_offset;
1553                                         last_ins->next = ins->next;
1554                                         ins = ins->next;
1555                                         continue;
1556                                 }
1557                         }
1558                         break;
1559                 case CEE_BEQ:
1560                 case CEE_BNE_UN:
1561                 case CEE_BLT:
1562                 case CEE_BGT:
1563                 case CEE_BGE:
1564                 case CEE_BLE:
1565                 case OP_COND_EXC_EQ:
1566                 case OP_COND_EXC_GE:
1567                 case OP_COND_EXC_GT:
1568                 case OP_COND_EXC_LE:
1569                 case OP_COND_EXC_LT:
1570                 case OP_COND_EXC_NE_UN:
1571                         /*
1572                          * Convert compare with zero+branch to BRcc
1573                          */
1574                         /*
1575                          * This only works in 64 bit mode, since it examines all 64
1576                          * bits of the register.
1577                          * Only do this if the method is small since BPr only has a 16bit
1578                          * displacement.
1579                          */
1580                         if (v64 && (((MonoMethodNormal*)cfg->method)->header->code_size < 10000) && last_ins &&
1581                                 (last_ins->opcode == OP_COMPARE_IMM) &&
1582                                 (last_ins->inst_imm == 0)) {
1583                                 MonoInst *next = ins->next;
1584                                 switch (ins->opcode) {
1585                                 case CEE_BEQ:
1586                                         ins->opcode = OP_SPARC_BRZ;
1587                                         break;
1588                                 case CEE_BNE_UN:
1589                                         ins->opcode = OP_SPARC_BRNZ;
1590                                         break;
1591                                 case CEE_BLT:
1592                                         ins->opcode = OP_SPARC_BRLZ;
1593                                         break;
1594                                 case CEE_BGT:
1595                                         ins->opcode = OP_SPARC_BRGZ;
1596                                         break;
1597                                 case CEE_BGE:
1598                                         ins->opcode = OP_SPARC_BRGEZ;
1599                                         break;
1600                                 case CEE_BLE:
1601                                         ins->opcode = OP_SPARC_BRLEZ;
1602                                         break;
1603                                 case OP_COND_EXC_EQ:
1604                                         ins->opcode = OP_SPARC_COND_EXC_EQZ;
1605                                         break;
1606                                 case OP_COND_EXC_GE:
1607                                         ins->opcode = OP_SPARC_COND_EXC_GEZ;
1608                                         break;
1609                                 case OP_COND_EXC_GT:
1610                                         ins->opcode = OP_SPARC_COND_EXC_GTZ;
1611                                         break;
1612                                 case OP_COND_EXC_LE:
1613                                         ins->opcode = OP_SPARC_COND_EXC_LEZ;
1614                                         break;
1615                                 case OP_COND_EXC_LT:
1616                                         ins->opcode = OP_SPARC_COND_EXC_LTZ;
1617                                         break;
1618                                 case OP_COND_EXC_NE_UN:
1619                                         ins->opcode = OP_SPARC_COND_EXC_NEZ;
1620                                         break;
1621                                 default:
1622                                         g_assert_not_reached ();
1623                                 }
1624                                 ins->sreg1 = last_ins->sreg1;
1625                                 *last_ins = *ins;
1626                                 last_ins->next = next;
1627                                 ins = next;
1628                                 continue;
1629                         }
1630                         break;
1631                 case CEE_CONV_I4:
1632                 case CEE_CONV_U4:
1633                 case OP_MOVE:
1634                         /*
1635                          * OP_MOVE reg, reg
1636                          */
1637                         if (ins->dreg == ins->sreg1) {
1638                                 if (last_ins)
1639                                         last_ins->next = ins->next;
1640                                 ins = ins->next;
1641                                 continue;
1642                         }
1643                         /*
1644                          * OP_MOVE sreg, dreg
1645                          * OP_MOVE dreg, sreg
1646                          */
1647                         if (last_ins && last_ins->opcode == OP_MOVE &&
1648                             ins->sreg1 == last_ins->dreg &&
1649                             ins->dreg == last_ins->sreg1) {
1650                                 last_ins->next = ins->next;
1651                                 ins = ins->next;
1652                                 continue;
1653                         }
1654                         break;
1655                 }
1656                 last_ins = ins;
1657                 ins = ins->next;
1658         }
1659         bb->last_ins = last_ins;
1660 }
1661
1662 /* Parameters used by the register allocator */
1663
1664 /* Use %l4..%l7 as local registers */
1665 #define ARCH_CALLER_REGS (0xf0<<16)
1666
1667 #ifdef SPARCV9
1668 /* Use %d34..%d62 as the double precision floating point local registers */
1669 /* %d32 has the same encoding as %f1, so %d36%d38 == 0b1010 == 0xa */
1670 #define ARCH_CALLER_FREGS (0xaaaaaaa8)
1671 #else
1672 /* Use %f2..%f30 as the double precision floating point local registers */
1673 #define ARCH_CALLER_FREGS (0x55555554)
1674 #endif
1675
1676 #undef DEBUG
1677 #define DEBUG(a) if (cfg->verbose_level > 1) a
1678 //#define DEBUG(a)
1679 #define reg_is_freeable(r) ((1 << (r)) & ARCH_CALLER_REGS)
1680 #define freg_is_freeable(r) (((1) << (r)) & ARCH_CALLER_FREGS)
1681
1682 typedef struct {
1683         int born_in;
1684         int killed_in;
1685         int last_use;
1686         int prev_use;
1687 } RegTrack;
1688
1689 static const char*const * ins_spec = sparc_desc;
1690
1691 static inline const char*
1692 get_ins_spec (int opcode)
1693 {
1694         if (ins_spec [opcode])
1695                 return ins_spec [opcode];
1696         else
1697                 return ins_spec [CEE_ADD];
1698 }
1699
1700 static void
1701 print_ins (int i, MonoInst *ins)
1702 {
1703         const char *spec = get_ins_spec (ins->opcode);
1704         g_print ("\t%-2d %s", i, mono_inst_name (ins->opcode));
1705         if (spec [MONO_INST_DEST]) {
1706                 if (ins->dreg >= MONO_MAX_IREGS)
1707                         g_print (" R%d <-", ins->dreg);
1708                 else
1709                         if (spec [MONO_INST_DEST] == 'b')
1710                                 g_print (" [%s + 0x%lx] <-", mono_arch_regname (ins->dreg), (long)ins->inst_offset);
1711                 else
1712                         g_print (" %s <-", mono_arch_regname (ins->dreg));
1713         }
1714         if (spec [MONO_INST_SRC1]) {
1715                 if (ins->sreg1 >= MONO_MAX_IREGS)
1716                         g_print (" R%d", ins->sreg1);
1717                 else
1718                         if (spec [MONO_INST_SRC1] == 'b')
1719                                 g_print (" [%s + 0x%lx]", mono_arch_regname (ins->sreg1), (long)ins->inst_offset);
1720                 else
1721                         g_print (" %s", mono_arch_regname (ins->sreg1));
1722         }
1723         if (spec [MONO_INST_SRC2]) {
1724                 if (ins->sreg2 >= MONO_MAX_IREGS)
1725                         g_print (" R%d", ins->sreg2);
1726                 else
1727                         g_print (" %s", mono_arch_regname (ins->sreg2));
1728         }
1729         if (spec [MONO_INST_CLOB])
1730                 g_print (" clobbers: %c", spec [MONO_INST_CLOB]);
1731         g_print ("\n");
1732 }
1733
1734 static void
1735 print_regtrack (RegTrack *t, int num)
1736 {
1737         int i;
1738         char buf [32];
1739         const char *r;
1740
1741         for (i = 0; i < num; ++i) {
1742                 if (!t [i].born_in)
1743                         continue;
1744                 if (i >= MONO_MAX_IREGS) {
1745                         g_snprintf (buf, sizeof(buf), "R%d", i);
1746                         r = buf;
1747                 } else
1748                         r = mono_arch_regname (i);
1749                 g_print ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].last_use);
1750         }
1751 }
1752
1753 typedef struct InstList InstList;
1754
1755 struct InstList {
1756         InstList *prev;
1757         InstList *next;
1758         MonoInst *data;
1759 };
1760
1761 static inline InstList*
1762 inst_list_prepend (MonoMemPool *pool, InstList *list, MonoInst *data)
1763 {
1764         InstList *item = mono_mempool_alloc (pool, sizeof (InstList));
1765         item->data = data;
1766         item->prev = NULL;
1767         item->next = list;
1768         if (list)
1769                 list->prev = item;
1770         return item;
1771 }
1772
1773 #define STACK_OFFSETS_POSITIVE
1774
1775 /*
1776  * returns the offset used by spillvar. It allocates a new
1777  * spill variable if necessary.
1778  */
1779 static int
1780 mono_spillvar_offset (MonoCompile *cfg, int spillvar)
1781 {
1782         MonoSpillInfo **si, *info;
1783         int i = 0;
1784
1785         si = &cfg->spill_info;
1786
1787         while (i <= spillvar) {
1788
1789                 if (!*si) {
1790                         *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
1791                         info->next = NULL;
1792                         cfg->stack_offset += sizeof (gpointer);
1793                         info->offset = - cfg->stack_offset;
1794                 }
1795
1796                 if (i == spillvar)
1797                         return MONO_SPARC_STACK_BIAS + (*si)->offset;
1798
1799                 i++;
1800                 si = &(*si)->next;
1801         }
1802
1803         g_assert_not_reached ();
1804         return 0;
1805 }
1806
1807 static int
1808 mono_spillvar_offset_float (MonoCompile *cfg, int spillvar)
1809 {
1810         MonoSpillInfo **si, *info;
1811         int i = 0;
1812
1813         si = &cfg->spill_info_float;
1814
1815         while (i <= spillvar) {
1816
1817                 if (!*si) {
1818                         *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
1819                         info->next = NULL;
1820                         cfg->stack_offset += sizeof (double);
1821                         cfg->stack_offset = ALIGN_TO (cfg->stack_offset, 8);
1822                         info->offset = - cfg->stack_offset;
1823                 }
1824
1825                 if (i == spillvar)
1826                         return MONO_SPARC_STACK_BIAS + (*si)->offset;
1827
1828                 i++;
1829                 si = &(*si)->next;
1830         }
1831
1832         g_assert_not_reached ();
1833         return 0;
1834 }
1835
1836 /*
1837  * Force the spilling of the variable in the symbolic register 'reg'.
1838  */
1839 G_GNUC_UNUSED static int
1840 get_register_force_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, int reg)
1841 {
1842         MonoInst *load;
1843         int i, sel, spill;
1844
1845         sel = cfg->rs->iassign [reg];
1846         /*i = cfg->rs->isymbolic [sel];
1847         g_assert (i == reg);*/
1848         i = reg;
1849         spill = ++cfg->spill_count;
1850         cfg->rs->iassign [i] = -spill - 1;
1851         mono_regstate_free_int (cfg->rs, sel);
1852         /* we need to create a spill var and insert a load to sel after the current instruction */
1853         MONO_INST_NEW (cfg, load, OP_LOAD_MEMBASE);
1854         load->dreg = sel;
1855         load->inst_basereg = cfg->frame_reg;
1856         load->inst_offset = mono_spillvar_offset (cfg, spill);
1857         if (item->prev) {
1858                 while (ins->next != item->prev->data)
1859                         ins = ins->next;
1860         }
1861         load->next = ins->next;
1862         ins->next = load;
1863         DEBUG (g_print ("SPILLED LOAD (%d at 0x%08lx(%%sp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_arch_regname (sel)));
1864         i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
1865         g_assert (i == sel);
1866
1867         return sel;
1868 }
1869
1870 static int
1871 get_register_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, guint32 regmask, int reg)
1872 {
1873         MonoInst *load;
1874         int i, sel, spill;
1875
1876         DEBUG (g_print ("start regmask to assign R%d: 0x%08x (R%d <- R%d R%d)\n", reg, regmask, ins->dreg, ins->sreg1, ins->sreg2));
1877         /* exclude the registers in the current instruction */
1878         if (reg != ins->sreg1 && (reg_is_freeable (ins->sreg1) || (ins->sreg1 >= MONO_MAX_IREGS && cfg->rs->iassign [ins->sreg1] >= 0))) {
1879                 if (ins->sreg1 >= MONO_MAX_IREGS)
1880                         regmask &= ~ (1 << cfg->rs->iassign [ins->sreg1]);
1881                 else
1882                         regmask &= ~ (1 << ins->sreg1);
1883                 DEBUG (g_print ("excluding sreg1 %s\n", mono_arch_regname (ins->sreg1)));
1884         }
1885         if (reg != ins->sreg2 && (reg_is_freeable (ins->sreg2) || (ins->sreg2 >= MONO_MAX_IREGS && cfg->rs->iassign [ins->sreg2] >= 0))) {
1886                 if (ins->sreg2 >= MONO_MAX_IREGS)
1887                         regmask &= ~ (1 << cfg->rs->iassign [ins->sreg2]);
1888                 else
1889                         regmask &= ~ (1 << ins->sreg2);
1890                 DEBUG (g_print ("excluding sreg2 %s %d\n", mono_arch_regname (ins->sreg2), ins->sreg2));
1891         }
1892         if (reg != ins->dreg && reg_is_freeable (ins->dreg)) {
1893                 regmask &= ~ (1 << ins->dreg);
1894                 DEBUG (g_print ("excluding dreg %s\n", mono_arch_regname (ins->dreg)));
1895         }
1896
1897         DEBUG (g_print ("available regmask: 0x%08x\n", regmask));
1898         g_assert (regmask); /* need at least a register we can free */
1899         sel = -1;
1900         /* we should track prev_use and spill the register that's farther */
1901         for (i = 0; i < MONO_MAX_IREGS; ++i) {
1902                 if (regmask & (1 << i)) {
1903                         sel = i;
1904                         DEBUG (g_print ("selected register %s has assignment %d\n", mono_arch_regname (sel), cfg->rs->iassign [sel]));
1905                         break;
1906                 }
1907         }
1908         i = cfg->rs->isymbolic [sel];
1909         spill = ++cfg->spill_count;
1910         cfg->rs->iassign [i] = -spill - 1;
1911         mono_regstate_free_int (cfg->rs, sel);
1912         /* we need to create a spill var and insert a load to sel after the current instruction */
1913         MONO_INST_NEW (cfg, load, OP_LOAD_MEMBASE);
1914         load->dreg = sel;
1915         load->inst_basereg = cfg->frame_reg;
1916         load->inst_offset = mono_spillvar_offset (cfg, spill);
1917         if (item->prev) {
1918                 while (ins->next != item->prev->data)
1919                         ins = ins->next;
1920         }
1921         load->next = ins->next;
1922         ins->next = load;
1923         DEBUG (g_print ("SPILLED LOAD (%d at 0x%08lx(%%sp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_arch_regname (sel)));
1924         i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
1925         g_assert (i == sel);
1926
1927         return sel;
1928 }
1929
1930 static int
1931 get_float_register_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, guint32 regmask, int reg)
1932 {
1933         MonoInst *load;
1934         int i, sel, spill;
1935
1936         DEBUG (g_print ("start regmask to assign R%d: 0x%08x (R%d <- R%d R%d)\n", reg, regmask, ins->dreg, ins->sreg1, ins->sreg2));
1937         /* exclude the registers in the current instruction */
1938         if (reg != ins->sreg1 && (freg_is_freeable (ins->sreg1) || (ins->sreg1 >= MONO_MAX_FREGS && cfg->rs->fassign [ins->sreg1] >= 0))) {
1939                 if (ins->sreg1 >= MONO_MAX_FREGS)
1940                         regmask &= ~ (1 << cfg->rs->fassign [ins->sreg1]);
1941                 else
1942                         regmask &= ~ (1 << ins->sreg1);
1943                 DEBUG (g_print ("excluding sreg1 %s\n", mono_arch_regname (ins->sreg1)));
1944         }
1945         if (reg != ins->sreg2 && (freg_is_freeable (ins->sreg2) || (ins->sreg2 >= MONO_MAX_FREGS && cfg->rs->fassign [ins->sreg2] >= 0))) {
1946                 if (ins->sreg2 >= MONO_MAX_FREGS)
1947                         regmask &= ~ (1 << cfg->rs->fassign [ins->sreg2]);
1948                 else
1949                         regmask &= ~ (1 << ins->sreg2);
1950                 DEBUG (g_print ("excluding sreg2 %s %d\n", mono_arch_regname (ins->sreg2), ins->sreg2));
1951         }
1952         if (reg != ins->dreg && freg_is_freeable (ins->dreg)) {
1953                 regmask &= ~ (1 << ins->dreg);
1954                 DEBUG (g_print ("excluding dreg %s\n", mono_arch_regname (ins->dreg)));
1955         }
1956
1957         DEBUG (g_print ("available regmask: 0x%08x\n", regmask));
1958         g_assert (regmask); /* need at least a register we can free */
1959         sel = -1;
1960         /* we should track prev_use and spill the register that's farther */
1961         for (i = 0; i < MONO_MAX_FREGS; ++i) {
1962                 if (regmask & (1 << i)) {
1963                         sel = i;
1964                         DEBUG (g_print ("selected register %s has assignment %d\n", mono_arch_regname (sel), cfg->rs->fassign [sel]));
1965                         break;
1966                 }
1967         }
1968         i = cfg->rs->fsymbolic [sel];
1969         spill = ++cfg->spill_count;
1970         cfg->rs->fassign [i] = -spill - 1;
1971         mono_regstate_free_float(cfg->rs, sel);
1972         /* we need to create a spill var and insert a load to sel after the current instruction */
1973         MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
1974         load->dreg = sel;
1975         load->inst_basereg = cfg->frame_reg;
1976         load->inst_offset = mono_spillvar_offset_float (cfg, spill);
1977         if (item->prev) {
1978                 while (ins->next != item->prev->data)
1979                         ins = ins->next;
1980         }
1981         load->next = ins->next;
1982         ins->next = load;
1983         DEBUG (g_print ("SPILLED LOAD (%d at 0x%08lx(%%sp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_arch_regname (sel)));
1984         i = mono_regstate_alloc_float (cfg->rs, 1 << sel);
1985         g_assert (i == sel);
1986
1987         return sel;
1988 }
1989
1990 static MonoInst*
1991 create_copy_ins (MonoCompile *cfg, int dest, int src, MonoInst *ins)
1992 {
1993         MonoInst *copy;
1994         MONO_INST_NEW (cfg, copy, OP_MOVE);
1995         copy->dreg = dest;
1996         copy->sreg1 = src;
1997         if (ins) {
1998                 copy->next = ins->next;
1999                 ins->next = copy;
2000         }
2001         DEBUG (g_print ("\tforced copy from %s to %s\n", mono_arch_regname (src), mono_arch_regname (dest)));
2002         return copy;
2003 }
2004
2005 G_GNUC_UNUSED static MonoInst*
2006 create_copy_ins_float (MonoCompile *cfg, int dest, int src, MonoInst *ins)
2007 {
2008         MonoInst *copy;
2009         MONO_INST_NEW (cfg, copy, OP_FMOVE);
2010         copy->dreg = dest;
2011         copy->sreg1 = src;
2012         if (ins) {
2013                 copy->next = ins->next;
2014                 ins->next = copy;
2015         }
2016         DEBUG (g_print ("\tforced copy from %s to %s\n", mono_arch_regname (src), mono_arch_regname (dest)));
2017         return copy;
2018 }
2019
2020 static MonoInst*
2021 create_spilled_store (MonoCompile *cfg, int spill, int reg, int prev_reg, MonoInst *ins)
2022 {
2023         MonoInst *store;
2024         MONO_INST_NEW (cfg, store, OP_STORE_MEMBASE_REG);
2025         store->sreg1 = reg;
2026         store->inst_destbasereg = cfg->frame_reg;
2027         store->inst_offset = mono_spillvar_offset (cfg, spill);
2028         if (ins) {
2029                 store->next = ins->next;
2030                 ins->next = store;
2031         }
2032         DEBUG (g_print ("SPILLED STORE (%d at 0x%08lx(%%sp)) R%d (from %s)\n", spill, (long)store->inst_offset, prev_reg, mono_arch_regname (reg)));
2033         return store;
2034 }
2035
2036 static MonoInst*
2037 create_spilled_store_float (MonoCompile *cfg, int spill, int reg, int prev_reg, MonoInst *ins)
2038 {
2039         MonoInst *store;
2040         MONO_INST_NEW (cfg, store, OP_STORER8_MEMBASE_REG);
2041         store->sreg1 = reg;
2042         store->inst_destbasereg = cfg->frame_reg;
2043         store->inst_offset = mono_spillvar_offset_float (cfg, spill);
2044         if (ins) {
2045                 store->next = ins->next;
2046                 ins->next = store;
2047         }
2048         DEBUG (g_print ("SPILLED STORE (%d at 0x%08lx(%%sp)) R%d (from %s)\n", spill, (long)store->inst_offset, prev_reg, mono_arch_regname (reg)));
2049         return store;
2050 }
2051
2052 static void
2053 insert_before_ins (MonoInst *ins, InstList *item, MonoInst* to_insert)
2054 {
2055         MonoInst *prev;
2056         g_assert (item->next);
2057         prev = item->next->data;
2058
2059         while (prev->next != ins)
2060                 prev = prev->next;
2061         to_insert->next = ins;
2062         prev->next = to_insert;
2063         /*
2064          * needed otherwise in the next instruction we can add an ins to the
2065          * end and that would get past this instruction.
2066          */
2067         item->data = to_insert;
2068 }
2069
2070 G_GNUC_UNUSED static int
2071 alloc_int_reg (MonoCompile *cfg, InstList *curinst, MonoInst *ins, int sym_reg, guint32 allow_mask)
2072 {
2073         int val = cfg->rs->iassign [sym_reg];
2074         if (val < 0) {
2075                 int spill = 0;
2076                 if (val < -1) {
2077                         /* the register gets spilled after this inst */
2078                         spill = -val -1;
2079                 }
2080                 val = mono_regstate_alloc_int (cfg->rs, allow_mask);
2081                 if (val < 0)
2082                         val = get_register_spilling (cfg, curinst, ins, allow_mask, sym_reg);
2083                 cfg->rs->iassign [sym_reg] = val;
2084                 /* add option to store before the instruction for src registers */
2085                 if (spill)
2086                         create_spilled_store (cfg, spill, val, sym_reg, ins);
2087         }
2088         cfg->rs->isymbolic [val] = sym_reg;
2089         return val;
2090 }
2091
2092 /* FIXME: Strange loads from the stack in basic-float.cs:test_2_rem */
2093
2094 /*
2095  * Local register allocation.
2096  * We first scan the list of instructions and we save the liveness info of
2097  * each register (when the register is first used, when it's value is set etc.).
2098  * We also reverse the list of instructions (in the InstList list) because assigning
2099  * registers backwards allows for more tricks to be used.
2100  */
2101 void
2102 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
2103 {
2104         MonoInst *ins;
2105         MonoRegState *rs = cfg->rs;
2106         int i, val;
2107         RegTrack *reginfo, *reginfof;
2108         RegTrack *reginfo1, *reginfo2, *reginfod;
2109         InstList *tmp, *reversed = NULL;
2110         const char *spec;
2111         guint32 src1_mask, src2_mask, dest_mask;
2112         guint32 cur_iregs, cur_fregs;
2113
2114         /* FIXME: Use caller saved regs and %i1-%2 for allocation */
2115
2116         if (!bb->code)
2117                 return;
2118         rs->next_vireg = bb->max_ireg;
2119         rs->next_vfreg = bb->max_freg;
2120         mono_regstate_assign (rs);
2121         reginfo = mono_mempool_alloc0 (cfg->mempool, sizeof (RegTrack) * rs->next_vireg);
2122         reginfof = mono_mempool_alloc0 (cfg->mempool, sizeof (RegTrack) * rs->next_vfreg);
2123         rs->ifree_mask = ARCH_CALLER_REGS;
2124         rs->ffree_mask = ARCH_CALLER_FREGS;
2125
2126         ins = bb->code;
2127         i = 1;
2128         DEBUG (g_print ("LOCAL regalloc: basic block: %d\n", bb->block_num));
2129         /* forward pass on the instructions to collect register liveness info */
2130         while (ins) {
2131                 spec = ins_spec [ins->opcode];
2132                 if (!spec) {
2133                         /* Use a default */
2134                         spec = ins_spec [CEE_ADD];
2135                 }
2136                 DEBUG (print_ins (i, ins));
2137
2138                 if (spec [MONO_INST_SRC1]) {
2139                         if (spec [MONO_INST_SRC1] == 'f')
2140                                 reginfo1 = reginfof;
2141                         else
2142                                 reginfo1 = reginfo;
2143                         reginfo1 [ins->sreg1].prev_use = reginfo1 [ins->sreg1].last_use;
2144                         reginfo1 [ins->sreg1].last_use = i;
2145                 } else {
2146                         ins->sreg1 = -1;
2147                 }
2148                 if (spec [MONO_INST_SRC2]) {
2149                         if (spec [MONO_INST_SRC2] == 'f')
2150                                 reginfo2 = reginfof;
2151                         else
2152                                 reginfo2 = reginfo;
2153                         reginfo2 [ins->sreg2].prev_use = reginfo2 [ins->sreg2].last_use;
2154                         reginfo2 [ins->sreg2].last_use = i;
2155                 } else {
2156                         ins->sreg2 = -1;
2157                 }
2158                 if (spec [MONO_INST_DEST]) {
2159                         if (spec [MONO_INST_DEST] == 'f')
2160                                 reginfod = reginfof;
2161                         else
2162                                 reginfod = reginfo;
2163                         if (spec [MONO_INST_DEST] != 'b') /* it's not just a base register */
2164                                 reginfod [ins->dreg].killed_in = i;
2165                         reginfod [ins->dreg].prev_use = reginfod [ins->dreg].last_use;
2166                         reginfod [ins->dreg].last_use = i;
2167                         if (reginfod [ins->dreg].born_in == 0 || reginfod [ins->dreg].born_in > i)
2168                                 reginfod [ins->dreg].born_in = i;
2169                         if (!v64 && (spec [MONO_INST_DEST] == 'l')) {
2170                                 /* result in a regpair, the virtual register is allocated sequentially */
2171                                 reginfod [ins->dreg + 1].prev_use = reginfod [ins->dreg + 1].last_use;
2172                                 reginfod [ins->dreg + 1].last_use = i;
2173                                 if (reginfod [ins->dreg + 1].born_in == 0 || reginfod [ins->dreg + 1].born_in > i)
2174                                         reginfod [ins->dreg + 1].born_in = i;
2175                         }
2176                 } else {
2177                         ins->dreg = -1;
2178                 }
2179                 reversed = inst_list_prepend (cfg->mempool, reversed, ins);
2180                 ++i;
2181                 ins = ins->next;
2182         }
2183
2184         cur_iregs = ARCH_CALLER_REGS;
2185         cur_fregs = ARCH_CALLER_FREGS;
2186
2187         DEBUG (print_regtrack (reginfo, rs->next_vireg));
2188         DEBUG (print_regtrack (reginfof, rs->next_vfreg));
2189         tmp = reversed;
2190         while (tmp) {
2191                 int prev_dreg, prev_sreg1, prev_sreg2;
2192                 --i;
2193                 ins = tmp->data;
2194                 spec = ins_spec [ins->opcode];
2195                 if (!spec)
2196                         spec = ins_spec [CEE_ADD];
2197                 DEBUG (g_print ("processing:"));
2198                 DEBUG (print_ins (i, ins));
2199
2200                 /* make the register available for allocation: FIXME add fp reg */
2201                 if (ins->opcode == OP_SETREG || ins->opcode == OP_SETREGIMM) {
2202                         /* Dont free register which can't be allocated */
2203                         if (reg_is_freeable (ins->dreg)) {
2204                                 cur_iregs |= 1 << ins->dreg;
2205                                 DEBUG (g_print ("adding %d to cur_iregs\n", ins->dreg));
2206                         }
2207                 } else if (ins->opcode == OP_SETFREG) {
2208                         if (freg_is_freeable (ins->dreg)) {
2209                                 cur_fregs |= 1 << ins->dreg;
2210                                 DEBUG (g_print ("adding %d to cur_fregs\n", ins->dreg));
2211                         }
2212                 } else if (spec [MONO_INST_CLOB] == 'c') {
2213                         MonoCallInst *cinst = (MonoCallInst*)ins;
2214                         DEBUG (g_print ("excluding regs 0x%lx from cur_iregs (0x%x)\n", (long)cinst->used_iregs, cur_iregs));
2215                         cur_iregs &= ~cinst->used_iregs;
2216                         cur_fregs &= ~cinst->used_fregs;
2217                         DEBUG (g_print ("available cur_iregs: 0x%x\n", cur_iregs));
2218                         /* registers used by the calling convention are excluded from
2219                          * allocation: they will be selectively enabled when they are
2220                          * assigned by the special SETREG opcodes.
2221                          */
2222                 }
2223                 dest_mask = src1_mask = src2_mask = cur_iregs;
2224
2225                 /*
2226                  * DEST
2227                  */
2228                 /* update for use with FP regs... */
2229                 if (spec [MONO_INST_DEST] == 'f') {
2230                         if (ins->dreg >= MONO_MAX_FREGS) {
2231                                 val = rs->fassign [ins->dreg];
2232                                 prev_dreg = ins->dreg;
2233                                 if (val < 0) {
2234                                         int spill = 0;
2235                                         if (val < -1) {
2236                                                 /* the register gets spilled after this inst */
2237                                                 spill = -val -1;
2238                                         }
2239                                         dest_mask = cur_fregs;
2240                                         val = mono_regstate_alloc_float (rs, dest_mask);
2241                                         if (val < 0)
2242                                                 val = get_float_register_spilling (cfg, tmp, ins, dest_mask, ins->dreg);
2243                                         rs->fassign [ins->dreg] = val;
2244                                         if (spill)
2245                                                 create_spilled_store_float (cfg, spill, val, prev_dreg, ins);
2246                                 }
2247                                 DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_arch_regname (val), ins->dreg));
2248                                 rs->fsymbolic [val] = prev_dreg;
2249                                 ins->dreg = val;
2250                         } else {
2251                                 prev_dreg = -1;
2252                         }
2253                         if (freg_is_freeable (ins->dreg) && prev_dreg >= 0 && (reginfo [prev_dreg].born_in >= i || !(cur_fregs & (1 << ins->dreg)))) {
2254                                 DEBUG (g_print ("\tfreeable %s (R%d) (born in %d)\n", mono_arch_regname (ins->dreg), prev_dreg, reginfo [prev_dreg].born_in));
2255                                 mono_regstate_free_float (rs, ins->dreg);
2256                         }
2257                 } else if (ins->dreg >= MONO_MAX_IREGS) {
2258                         val = rs->iassign [ins->dreg];
2259                         prev_dreg = ins->dreg;
2260                         if (val < 0) {
2261                                 int spill = 0;
2262                                 if (val < -1) {
2263                                         /* the register gets spilled after this inst */
2264                                         spill = -val -1;
2265                                 }
2266                                 val = mono_regstate_alloc_int (rs, dest_mask);
2267                                 if (val < 0)
2268                                         val = get_register_spilling (cfg, tmp, ins, dest_mask, ins->dreg);
2269                                 rs->iassign [ins->dreg] = val;
2270                                 if (spill)
2271                                         create_spilled_store (cfg, spill, val, prev_dreg, ins);
2272                         }
2273                         DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_arch_regname (val), ins->dreg));
2274                         rs->isymbolic [val] = prev_dreg;
2275                         ins->dreg = val;
2276                         if (!v64 && spec [MONO_INST_DEST] == 'l') {
2277                                 int hreg = prev_dreg + 1;
2278                                 val = rs->iassign [hreg];
2279                                 if (val < 0) {
2280                                         int spill = 0;
2281                                         if (val < -1) {
2282                                                 /* the register gets spilled after this inst */
2283                                                 spill = -val -1;
2284                                         }
2285                                         /* The second register must be a pair of the first */
2286                                         dest_mask = 1 << (rs->iassign [prev_dreg] + 1);
2287                                         val = mono_regstate_alloc_int (rs, dest_mask);
2288                                         if (val < 0)
2289                                                 val = get_register_spilling (cfg, tmp, ins, dest_mask, hreg);
2290                                         rs->iassign [hreg] = val;
2291                                         if (spill)
2292                                                 create_spilled_store (cfg, spill, val, hreg, ins);
2293                                 }
2294                                 else {
2295                                         /* The second register must be a pair of the first */
2296                                         if (val != rs->iassign [prev_dreg] + 1) {
2297                                                 dest_mask = 1 << (rs->iassign [prev_dreg] + 1);
2298
2299                                                 val = mono_regstate_alloc_int (rs, dest_mask);
2300                                                 if (val < 0)
2301                                                         val = get_register_spilling (cfg, tmp, ins, dest_mask, hreg);
2302
2303                                                 create_copy_ins (cfg, rs->iassign [hreg], val, ins);
2304
2305                                                 rs->iassign [hreg] = val;
2306                                         }
2307                                 }
2308
2309                                 DEBUG (g_print ("\tassigned hreg %s to dest R%d\n", mono_arch_regname (val), hreg));
2310                                 rs->isymbolic [val] = hreg;
2311
2312                                 if (reg_is_freeable (val) && hreg >= 0 && (reginfo [hreg].born_in >= i && !(cur_iregs & (1 << val)))) {
2313                                         DEBUG (g_print ("\tfreeable %s (R%d)\n", mono_arch_regname (val), hreg));
2314                                         mono_regstate_free_int (rs, val);
2315                                 }
2316                         }
2317                 } else {
2318                         prev_dreg = -1;
2319                 }
2320                 if (spec [MONO_INST_DEST] != 'f' && reg_is_freeable (ins->dreg) && prev_dreg >= 0 && (reginfo [prev_dreg].born_in >= i)) {
2321                         DEBUG (g_print ("\tfreeable %s (R%d) (born in %d)\n", mono_arch_regname (ins->dreg), prev_dreg, reginfo [prev_dreg].born_in));
2322                         mono_regstate_free_int (rs, ins->dreg);
2323                 }
2324
2325                 /**
2326                  * SRC1
2327                  */
2328                 if (spec [MONO_INST_SRC1] == 'f') {
2329                         if (ins->sreg1 >= MONO_MAX_FREGS) {
2330                                 val = rs->fassign [ins->sreg1];
2331                                 prev_sreg1 = ins->sreg1;
2332                                 if (val < 0) {
2333                                         int spill = 0;
2334                                         if (val < -1) {
2335                                                 /* the register gets spilled after this inst */
2336                                                 spill = -val -1;
2337                                         }
2338                                         //g_assert (val == -1); /* source cannot be spilled */
2339                                         src1_mask = cur_fregs;
2340                                         val = mono_regstate_alloc_float (rs, src1_mask);
2341                                         if (val < 0)
2342                                                 val = get_float_register_spilling (cfg, tmp, ins, src1_mask, ins->sreg1);
2343                                         rs->fassign [ins->sreg1] = val;
2344                                         DEBUG (g_print ("\tassigned sreg1 %s to R%d\n", mono_arch_regname (val), ins->sreg1));
2345                                         if (spill) {
2346                                                 MonoInst *store = create_spilled_store_float (cfg, spill, val, prev_sreg1, NULL);
2347                                                 insert_before_ins (ins, tmp, store);
2348                                         }
2349                                 }
2350                                 rs->fsymbolic [val] = prev_sreg1;
2351                                 ins->sreg1 = val;
2352                         } else {
2353                                 prev_sreg1 = -1;
2354                         }
2355                 } else if (ins->sreg1 >= MONO_MAX_IREGS) {
2356                         val = rs->iassign [ins->sreg1];
2357                         prev_sreg1 = ins->sreg1;
2358                         if (val < 0) {
2359                                 int spill = 0;
2360                                 if (val < -1) {
2361                                         /* the register gets spilled after this inst */
2362                                         spill = -val -1;
2363                                 }
2364                                 if (0 && (ins->opcode == OP_MOVE) && reg_is_freeable (ins->dreg)) {
2365                                         /*
2366                                          * small optimization: the dest register is already allocated
2367                                          * but the src one is not: we can simply assign the same register
2368                                          * here and peephole will get rid of the instruction later.
2369                                          * This optimization may interfere with the clobbering handling:
2370                                          * it removes a mov operation that will be added again to handle clobbering.
2371                                          * There are also some other issues that should with make testjit.
2372                                          */
2373                                         mono_regstate_alloc_int (rs, 1 << ins->dreg);
2374                                         val = rs->iassign [ins->sreg1] = ins->dreg;
2375                                         //g_assert (val >= 0);
2376                                         DEBUG (g_print ("\tfast assigned sreg1 %s to R%d\n", mono_arch_regname (val), ins->sreg1));
2377                                 } else {
2378                                         //g_assert (val == -1); /* source cannot be spilled */
2379                                         val = mono_regstate_alloc_int (rs, src1_mask);
2380                                         if (val < 0)
2381                                                 val = get_register_spilling (cfg, tmp, ins, src1_mask, ins->sreg1);
2382                                         rs->iassign [ins->sreg1] = val;
2383                                         DEBUG (g_print ("\tassigned sreg1 %s to R%d\n", mono_arch_regname (val), ins->sreg1));
2384                                 }
2385                                 if (spill) {
2386                                         MonoInst *store = create_spilled_store (cfg, spill, val, prev_sreg1, NULL);
2387                                         insert_before_ins (ins, tmp, store);
2388                                 }
2389                         }
2390                         rs->isymbolic [val] = prev_sreg1;
2391                         ins->sreg1 = val;
2392                 } else {
2393                         prev_sreg1 = -1;
2394                 }
2395
2396                 /*
2397                  * SRC2
2398                  */
2399                 if (spec [MONO_INST_SRC2] == 'f') {
2400                         if (ins->sreg2 >= MONO_MAX_FREGS) {
2401                                 val = rs->fassign [ins->sreg2];
2402                                 prev_sreg2 = ins->sreg2;
2403                                 if (val < 0) {
2404                                         int spill = 0;
2405                                         if (val < -1) {
2406                                                 /* the register gets spilled after this inst */
2407                                                 spill = -val -1;
2408                                         }
2409                                         src2_mask = cur_fregs;
2410                                         val = mono_regstate_alloc_float (rs, src2_mask);
2411                                         if (val < 0)
2412                                                 val = get_float_register_spilling (cfg, tmp, ins, src2_mask, ins->sreg2);
2413                                         rs->fassign [ins->sreg2] = val;
2414                                         DEBUG (g_print ("\tassigned sreg2 %s to R%d\n", mono_arch_regname (val), ins->sreg2));
2415                                         if (spill)
2416                                                 create_spilled_store_float (cfg, spill, val, prev_sreg2, ins);
2417                                 }
2418                                 rs->fsymbolic [val] = prev_sreg2;
2419                                 ins->sreg2 = val;
2420                         } else {
2421                                 prev_sreg2 = -1;
2422                         }
2423                 } else if (ins->sreg2 >= MONO_MAX_IREGS) {
2424                         val = rs->iassign [ins->sreg2];
2425                         prev_sreg2 = ins->sreg2;
2426                         if (val < 0) {
2427                                 int spill = 0;
2428                                 if (val < -1) {
2429                                         /* the register gets spilled after this inst */
2430                                         spill = -val -1;
2431                                 }
2432                                 val = mono_regstate_alloc_int (rs, src2_mask);
2433                                 if (val < 0)
2434                                         val = get_register_spilling (cfg, tmp, ins, src2_mask, ins->sreg2);
2435                                 rs->iassign [ins->sreg2] = val;
2436                                 DEBUG (g_print ("\tassigned sreg2 %s to R%d\n", mono_arch_regname (val), ins->sreg2));
2437                                 if (spill)
2438                                         create_spilled_store (cfg, spill, val, prev_sreg2, ins);
2439                         }
2440                         rs->isymbolic [val] = prev_sreg2;
2441                         ins->sreg2 = val;
2442                 } else {
2443                         prev_sreg2 = -1;
2444                 }
2445
2446                 if (spec [MONO_INST_CLOB] == 'c') {
2447                         int j, s;
2448                         guint32 clob_mask = ARCH_CALLER_REGS;
2449                         for (j = 0; j < MONO_MAX_IREGS; ++j) {
2450                                 s = 1 << j;
2451                                 if ((clob_mask & s) && !(rs->ifree_mask & s) && j != ins->sreg1) {
2452                                         //g_warning ("register %s busy at call site\n", mono_arch_regname (j));
2453                                 }
2454                         }
2455                 }
2456                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2457                         DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2458                         mono_regstate_free_int (rs, ins->sreg1);
2459                 }
2460                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2461                         DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2462                         mono_regstate_free_int (rs, ins->sreg2);
2463                 }*/
2464
2465                 //DEBUG (print_ins (i, ins));
2466
2467                 tmp = tmp->next;
2468         }
2469 }
2470
2471 static void
2472 sparc_patch (guint32 *code, const gpointer target)
2473 {
2474         guint32 *c = code;
2475         guint32 ins = *code;
2476         guint32 op = ins >> 30;
2477         guint32 op2 = (ins >> 22) & 0x7;
2478         guint32 rd = (ins >> 25) & 0x1f;
2479         guint8* target8 = (guint8*)target;
2480         gint64 disp = (target8 - (guint8*)code) >> 2;
2481         int reg;
2482
2483 //      g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
2484
2485         if ((op == 0) && (op2 == 2)) {
2486                 if (!sparc_is_imm22 (disp))
2487                         NOT_IMPLEMENTED;
2488                 /* Bicc */
2489                 *code = ((ins >> 22) << 22) | (disp & 0x3fffff);
2490         }
2491         else if ((op == 0) && (op2 == 1)) {
2492                 if (!sparc_is_imm19 (disp))
2493                         NOT_IMPLEMENTED;
2494                 /* BPcc */
2495                 *code = ((ins >> 19) << 19) | (disp & 0x7ffff);
2496         }
2497         else if ((op == 0) && (op2 == 3)) {
2498                 if (!sparc_is_imm16 (disp))
2499                         NOT_IMPLEMENTED;
2500                 /* BPr */
2501                 *code &= ~(0x180000 | 0x3fff);
2502                 *code |= ((disp << 21) & (0x180000)) | (disp & 0x3fff);
2503         }
2504         else if ((op == 0) && (op2 == 6)) {
2505                 if (!sparc_is_imm22 (disp))
2506                         NOT_IMPLEMENTED;
2507                 /* FBicc */
2508                 *code = ((ins >> 22) << 22) | (disp & 0x3fffff);
2509         }
2510         else if ((op == 0) && (op2 == 4)) {
2511                 guint32 ins2 = code [1];
2512
2513                 if (((ins2 >> 30) == 2) && (((ins2 >> 19) & 0x3f) == 2)) {
2514                         /* sethi followed by or */
2515                         guint32 *p = code;
2516                         sparc_set (p, target8, rd);
2517                         while (p <= (code + 1))
2518                                 sparc_nop (p);
2519                 }
2520                 else if (ins2 == 0x01000000) {
2521                         /* sethi followed by nop */
2522                         guint32 *p = code;
2523                         sparc_set (p, target8, rd);
2524                         while (p <= (code + 1))
2525                                 sparc_nop (p);
2526                 }
2527                 else if ((sparc_inst_op (ins2) == 3) && (sparc_inst_imm (ins2))) {
2528                         /* sethi followed by load/store */
2529 #ifndef SPARCV9
2530                         guint32 t = (guint32)target8;
2531                         *code &= ~(0x3fffff);
2532                         *code |= (t >> 10);
2533                         *(code + 1) &= ~(0x3ff);
2534                         *(code + 1) |= (t & 0x3ff);
2535 #endif
2536                 }
2537                 else if (v64 &&
2538                                  (sparc_inst_rd (ins) == sparc_g1) &&
2539                                  (sparc_inst_op (c [1]) == 0) && (sparc_inst_op2 (c [1]) == 4) &&
2540                                  (sparc_inst_op (c [2]) == 2) && (sparc_inst_op3 (c [2]) == 2) &&
2541                                  (sparc_inst_op (c [3]) == 2) && (sparc_inst_op3 (c [3]) == 2))
2542                 {
2543                         /* sparc_set */
2544                         guint32 *p = c;
2545                         reg = sparc_inst_rd (c [1]);
2546                         sparc_set (p, target8, reg);
2547                         while (p < (c + 6))
2548                                 sparc_nop (p);
2549                 }
2550                 else if ((sparc_inst_op (ins2) == 2) && (sparc_inst_op3 (ins2) == 0x38) &&
2551                                  (sparc_inst_imm (ins2))) {
2552                         /* sethi followed by jmpl */
2553 #ifndef SPARCV9
2554                         guint32 t = (guint32)target8;
2555                         *code &= ~(0x3fffff);
2556                         *code |= (t >> 10);
2557                         *(code + 1) &= ~(0x3ff);
2558                         *(code + 1) |= (t & 0x3ff);
2559 #endif
2560                 }
2561                 else
2562                         NOT_IMPLEMENTED;
2563         }
2564         else if (op == 01) {
2565                 gint64 disp = (target8 - (guint8*)code) >> 2;
2566
2567                 if (!sparc_is_imm30 (disp))
2568                         NOT_IMPLEMENTED;
2569                 sparc_call_simple (code, target8 - (guint8*)code);
2570         }
2571         else if ((op == 2) && (sparc_inst_op3 (ins) == 0x2) && sparc_inst_imm (ins)) {
2572                 /* mov imm, reg */
2573                 g_assert (sparc_is_imm13 (target8));
2574                 *code &= ~(0x1fff);
2575                 *code |= (guint32)target8;
2576         }
2577         else if ((sparc_inst_op (ins) == 2) && (sparc_inst_op3 (ins) == 0x7)) {
2578                 /* sparc_set case 5. */
2579                 guint32 *p = c;
2580
2581                 g_assert (v64);
2582                 reg = sparc_inst_rd (c [3]);
2583                 sparc_set (p, target, reg);
2584                 while (p < (c + 6))
2585                         sparc_nop (p);
2586         }
2587         else
2588                 NOT_IMPLEMENTED;
2589
2590 //      g_print ("patched with 0x%08x\n", ins);
2591 }
2592
2593 /*
2594  * mono_sparc_emit_save_lmf:
2595  *
2596  *  Emit the code neccesary to push a new entry onto the lmf stack. Used by
2597  * trampolines as well.
2598  */
2599 guint32*
2600 mono_sparc_emit_save_lmf (guint32 *code, guint32 lmf_offset)
2601 {
2602         /* Save lmf_addr */
2603         sparc_sti_imm (code, sparc_o0, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr));
2604         /* Save previous_lmf */
2605         sparc_ldi (code, sparc_o0, sparc_g0, sparc_o7);
2606         sparc_sti_imm (code, sparc_o7, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf));
2607         /* Set new lmf */
2608         sparc_add_imm (code, FALSE, sparc_fp, lmf_offset, sparc_o7);
2609         sparc_sti (code, sparc_o7, sparc_o0, sparc_g0);
2610
2611         return code;
2612 }
2613
2614 guint32*
2615 mono_sparc_emit_restore_lmf (guint32 *code, guint32 lmf_offset)
2616 {
2617         /* Load previous_lmf */
2618         sparc_ldi_imm (code, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sparc_l0);
2619         /* Load lmf_addr */
2620         sparc_ldi_imm (code, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), sparc_l1);
2621         /* *(lmf) = previous_lmf */
2622         sparc_sti (code, sparc_l0, sparc_l1, sparc_g0);
2623         return code;
2624 }
2625
2626 static guint32*
2627 emit_save_sp_to_lmf (MonoCompile *cfg, guint32 *code)
2628 {
2629         /*
2630          * Since register windows are saved to the current value of %sp, we need to
2631          * set the sp field in the lmf before the call, not in the prolog.
2632          */
2633         if (cfg->method->save_lmf) {
2634                 gint32 lmf_offset = MONO_SPARC_STACK_BIAS - cfg->arch.lmf_offset;
2635
2636                 /* Save sp */
2637                 sparc_sti_imm (code, sparc_sp, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, sp));
2638         }
2639
2640         return code;
2641 }
2642
2643 static guint32*
2644 emit_vret_token (MonoInst *ins, guint32 *code)
2645 {
2646         MonoCallInst *call = (MonoCallInst*)ins;
2647         guint32 size;
2648
2649         /*
2650          * The sparc ABI requires that calls to functions which return a structure
2651          * contain an additional unimpl instruction which is checked by the callee.
2652          */
2653         if (call->signature->pinvoke && MONO_TYPE_ISSTRUCT(call->signature->ret)) {
2654                 if (call->signature->ret->type == MONO_TYPE_TYPEDBYREF)
2655                         size = mono_type_stack_size (call->signature->ret, NULL);
2656                 else
2657                         size = mono_class_native_size (call->signature->ret->data.klass, NULL);
2658                 sparc_unimp (code, size & 0xfff);
2659         }
2660
2661         return code;
2662 }
2663
2664 static guint32*
2665 emit_move_return_value (MonoInst *ins, guint32 *code)
2666 {
2667         /* Move return value to the target register */
2668         /* FIXME: do this in the local reg allocator */
2669         switch (ins->opcode) {
2670         case OP_VOIDCALL:
2671         case OP_VOIDCALL_REG:
2672         case OP_VOIDCALL_MEMBASE:
2673                 break;
2674         case CEE_CALL:
2675         case OP_CALL_REG:
2676         case OP_CALL_MEMBASE:
2677                 sparc_mov_reg_reg (code, sparc_o0, ins->dreg);
2678                 break;
2679         case OP_LCALL:
2680         case OP_LCALL_REG:
2681         case OP_LCALL_MEMBASE:
2682                 /*
2683                  * ins->dreg is the least significant reg due to the lreg: LCALL rule
2684                  * in inssel.brg.
2685                  */
2686 #ifdef SPARCV9
2687                 sparc_mov_reg_reg (code, sparc_o0, ins->dreg);
2688 #else
2689                 sparc_mov_reg_reg (code, sparc_o0, ins->dreg + 1);
2690                 sparc_mov_reg_reg (code, sparc_o1, ins->dreg);
2691 #endif
2692                 break;
2693         case OP_FCALL:
2694         case OP_FCALL_REG:
2695         case OP_FCALL_MEMBASE:
2696 #ifdef SPARCV9
2697                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2698                         sparc_fmovs (code, sparc_f0, ins->dreg);
2699                         sparc_fstod (code, ins->dreg, ins->dreg);
2700                 }
2701                 else
2702                         sparc_fmovd (code, sparc_f0, ins->dreg);
2703 #else
2704                 sparc_fmovs (code, sparc_f0, ins->dreg);
2705                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4)
2706                         sparc_fstod (code, ins->dreg, ins->dreg);
2707                 else
2708                         sparc_fmovs (code, sparc_f1, ins->dreg + 1);
2709 #endif
2710                 break;
2711         case OP_VCALL:
2712         case OP_VCALL_REG:
2713         case OP_VCALL_MEMBASE:
2714                 break;
2715         default:
2716                 NOT_IMPLEMENTED;
2717         }
2718
2719         return code;
2720 }
2721
2722 /*
2723  * emit_load_volatile_arguments:
2724  *
2725  *  Load volatile arguments from the stack to the original input registers.
2726  * Required before a tail call.
2727  */
2728 static guint32*
2729 emit_load_volatile_arguments (MonoCompile *cfg, guint32 *code)
2730 {
2731         MonoMethod *method = cfg->method;
2732         MonoMethodSignature *sig;
2733         MonoInst *inst;
2734         CallInfo *cinfo;
2735         guint32 i, ireg;
2736
2737         /* FIXME: Generate intermediate code instead */
2738
2739         sig = method->signature;
2740
2741         cinfo = get_call_info (sig, FALSE);
2742
2743         /* This is the opposite of the code in emit_prolog */
2744
2745         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2746                 ArgInfo *ainfo = cinfo->args + i;
2747                 gint32 stack_offset;
2748                 MonoType *arg_type;
2749                 inst = cfg->varinfo [i];
2750
2751                 if (sig->hasthis && (i == 0))
2752                         arg_type = &mono_defaults.object_class->byval_arg;
2753                 else
2754                         arg_type = sig->params [i - sig->hasthis];
2755
2756                 stack_offset = ainfo->offset + ARGS_OFFSET;
2757                 ireg = sparc_i0 + ainfo->reg;
2758
2759                 if (ainfo->storage == ArgInSplitRegStack) {
2760                         g_assert (inst->opcode == OP_REGOFFSET);
2761
2762                         if (!sparc_is_imm13 (stack_offset))
2763                                 NOT_IMPLEMENTED;
2764                         sparc_st_imm (code, inst->inst_basereg, stack_offset, sparc_i5);
2765                 }
2766
2767                 if (!v64 && !arg_type->byref && (arg_type->type == MONO_TYPE_R8)) {
2768                         if (ainfo->storage == ArgInIRegPair) {
2769                                 if (!sparc_is_imm13 (inst->inst_offset + 4))
2770                                         NOT_IMPLEMENTED;
2771                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset, ireg);
2772                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset + 4, ireg + 1);
2773                         }
2774                         else
2775                                 if (ainfo->storage == ArgInSplitRegStack) {
2776                                         if (stack_offset != inst->inst_offset) {
2777                                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset, sparc_i5);
2778                                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset + 4, sparc_o7);
2779                                                 sparc_st_imm (code, sparc_o7, sparc_fp, stack_offset + 4);
2780
2781                                         }
2782                                 }
2783                         else
2784                                 if (ainfo->storage == ArgOnStackPair) {
2785                                         if (stack_offset != inst->inst_offset) {
2786                                                 /* stack_offset is not dword aligned, so we need to make a copy */
2787                                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset, sparc_o7);
2788                                                 sparc_st_imm (code, sparc_o7, sparc_fp, stack_offset);
2789
2790                                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset + 4, sparc_o7);
2791                                                 sparc_st_imm (code, sparc_o7, sparc_fp, stack_offset + 4);
2792
2793                                         }
2794                                 }
2795                          else
2796                                 g_assert_not_reached ();
2797                 }
2798                 else
2799                         if ((ainfo->storage == ArgInIReg) && (inst->opcode != OP_REGVAR)) {
2800                                 /* Argument in register, but need to be saved to stack */
2801                                 if (!sparc_is_imm13 (stack_offset))
2802                                         NOT_IMPLEMENTED;
2803                                 if ((stack_offset - ARGS_OFFSET) & 0x1)
2804                                         /* FIXME: Is this ldsb or ldub ? */
2805                                         sparc_ldsb_imm (code, inst->inst_basereg, stack_offset, ireg);
2806                                 else
2807                                         if ((stack_offset - ARGS_OFFSET) & 0x2)
2808                                                 sparc_ldsh_imm (code, inst->inst_basereg, stack_offset, ireg);
2809                                 else
2810                                         if ((stack_offset - ARGS_OFFSET) & 0x4)
2811                                                 sparc_ld_imm (code, inst->inst_basereg, stack_offset, ireg);
2812                                         else {
2813                                                 if (v64)
2814                                                         sparc_ldx_imm (code, inst->inst_basereg, stack_offset, ireg);
2815                                                 else
2816                                                         sparc_ld_imm (code, inst->inst_basereg, stack_offset, ireg);
2817                                         }
2818                         }
2819                         else if ((ainfo->storage == ArgInIRegPair) && (inst->opcode != OP_REGVAR)) {
2820                                 /* Argument in regpair, but need to be saved to stack */
2821                                 if (!sparc_is_imm13 (inst->inst_offset + 4))
2822                                         NOT_IMPLEMENTED;
2823                                 sparc_ld_imm (code, inst->inst_basereg, inst->inst_offset, ireg);
2824                                 sparc_st_imm (code, inst->inst_basereg, inst->inst_offset + 4, ireg + 1);
2825                         }
2826                         else if ((ainfo->storage == ArgInFloatReg) && (inst->opcode != OP_REGVAR)) {
2827                                 NOT_IMPLEMENTED;
2828                         }
2829                         else if ((ainfo->storage == ArgInDoubleReg) && (inst->opcode != OP_REGVAR)) {
2830                                 NOT_IMPLEMENTED;
2831                         }
2832
2833                 if ((ainfo->storage == ArgInSplitRegStack) || (ainfo->storage == ArgOnStack))
2834                         if (inst->opcode == OP_REGVAR)
2835                                 /* FIXME: Load the argument into memory */
2836                                 NOT_IMPLEMENTED;
2837         }
2838
2839         g_free (cinfo);
2840
2841         return code;
2842 }
2843
2844 /*
2845  * mono_sparc_is_virtual_call:
2846  *
2847  *  Determine whenever the instruction at CODE is a virtual call.
2848  */
2849 gboolean
2850 mono_sparc_is_virtual_call (guint32 *code)
2851 {
2852         guint32 buf[1];
2853         guint32 *p;
2854
2855         p = buf;
2856
2857         if ((sparc_inst_op (*code) == 0x2) && (sparc_inst_op3 (*code) == 0x38)) {
2858                 /*
2859                  * Register indirect call. If it is a virtual call, then the
2860                  * instruction in the delay slot is a special kind of nop.
2861                  */
2862
2863                 /* Construct special nop */
2864                 sparc_or_imm (p, FALSE, sparc_g0, 0xca, sparc_g0);
2865                 p --;
2866
2867                 if (code [1] == p [0])
2868                         return TRUE;
2869         }
2870
2871         return FALSE;
2872 }
2873
2874 /*
2875  * mono_sparc_get_vcall_slot_addr:
2876  *
2877  *  Determine the vtable slot used by a virtual call.
2878  */
2879 gpointer*
2880 mono_sparc_get_vcall_slot_addr (guint32 *code, gpointer *fp)
2881 {
2882         guint32 ins = code [0];
2883         guint32 prev_ins = code [-1];
2884
2885         mono_sparc_flushw ();
2886
2887         fp = (gpointer*)((guint8*)fp + MONO_SPARC_STACK_BIAS);
2888
2889         if ((sparc_inst_op (ins) == 0x2) && (sparc_inst_op3 (ins) == 0x38)) {
2890                 if ((sparc_inst_op (prev_ins) == 0x3) && (sparc_inst_op3 (prev_ins) == 0 || sparc_inst_op3 (prev_ins) == 0xb)) {
2891                         /* ld [r1 + CONST ], r2; call r2 */
2892                         guint32 base = sparc_inst_rs1 (prev_ins);
2893                         guint32 disp = sparc_inst_imm13 (prev_ins);
2894                         gpointer base_val;
2895
2896                         g_assert (sparc_inst_rd (prev_ins) == sparc_inst_rs1 (ins));
2897
2898                         g_assert ((base >= sparc_o0) && (base <= sparc_i7));
2899
2900                         base_val = fp [base - 16];
2901
2902                         return (gpointer)((guint8*)base_val + disp);
2903                 }
2904                 else
2905                         g_assert_not_reached ();
2906         }
2907         else
2908                 g_assert_not_reached ();
2909
2910         return FALSE;
2911 }
2912
2913 /*
2914  * Some conventions used in the following code.
2915  * 2) The only scratch registers we have are o7 and g1.  We try to
2916  * stick to o7 when we can, and use g1 when necessary.
2917  */
2918
2919 void
2920 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2921 {
2922         MonoInst *ins;
2923         MonoCallInst *call;
2924         guint offset;
2925         guint32 *code = (guint32*)(cfg->native_code + cfg->code_len);
2926         MonoInst *last_ins = NULL;
2927         int max_len, cpos;
2928         const char *spec;
2929
2930         if (cfg->opt & MONO_OPT_PEEPHOLE)
2931                 peephole_pass (cfg, bb);
2932
2933         if (cfg->verbose_level > 2)
2934                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2935
2936         cpos = bb->max_offset;
2937
2938         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2939                 NOT_IMPLEMENTED;
2940         }
2941
2942         ins = bb->code;
2943         while (ins) {
2944                 guint8* code_start;
2945
2946                 offset = (guint8*)code - cfg->native_code;
2947
2948                 spec = ins_spec [ins->opcode];
2949                 if (!spec)
2950                         spec = ins_spec [CEE_ADD];
2951
2952                 max_len = ((guint8 *)spec)[MONO_INST_LEN];
2953
2954                 if (offset > (cfg->code_size - max_len - 16)) {
2955                         cfg->code_size *= 2;
2956                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2957                         code = (guint32*)(cfg->native_code + offset);
2958                 }
2959                 code_start = (guint8*)code;
2960                 //      if (ins->cil_code)
2961                 //              g_print ("cil code\n");
2962                 mono_debug_record_line_number (cfg, ins, offset);
2963
2964                 switch (ins->opcode) {
2965                 case OP_STOREI1_MEMBASE_IMM:
2966                         EMIT_STORE_MEMBASE_IMM (ins, stb);
2967                         break;
2968                 case OP_STOREI2_MEMBASE_IMM:
2969                         EMIT_STORE_MEMBASE_IMM (ins, sth);
2970                         break;
2971                 case OP_STORE_MEMBASE_IMM:
2972                         EMIT_STORE_MEMBASE_IMM (ins, sti);
2973                         break;
2974                 case OP_STOREI4_MEMBASE_IMM:
2975                         EMIT_STORE_MEMBASE_IMM (ins, st);
2976                         break;
2977                 case OP_STOREI8_MEMBASE_IMM:
2978 #ifdef SPARCV9
2979                         EMIT_STORE_MEMBASE_IMM (ins, stx);
2980 #else
2981                         /* Only generated by peephole opts */
2982                         g_assert ((ins->inst_offset % 8) == 0);
2983                         g_assert (ins->inst_imm == 0);
2984                         EMIT_STORE_MEMBASE_IMM (ins, stx);
2985 #endif
2986                         break;
2987                 case OP_STOREI1_MEMBASE_REG:
2988                         EMIT_STORE_MEMBASE_REG (ins, stb);
2989                         break;
2990                 case OP_STOREI2_MEMBASE_REG:
2991                         EMIT_STORE_MEMBASE_REG (ins, sth);
2992                         break;
2993                 case OP_STOREI4_MEMBASE_REG:
2994                         EMIT_STORE_MEMBASE_REG (ins, st);
2995                         break;
2996                 case OP_STOREI8_MEMBASE_REG:
2997 #ifdef SPARCV9
2998                         EMIT_STORE_MEMBASE_REG (ins, stx);
2999 #else
3000                         /* Only used by OP_MEMSET */
3001                         EMIT_STORE_MEMBASE_REG (ins, std);
3002 #endif
3003                         break;
3004                 case OP_STORE_MEMBASE_REG:
3005                         EMIT_STORE_MEMBASE_REG (ins, sti);
3006                         break;
3007                 case CEE_LDIND_I:
3008 #ifdef SPARCV9
3009                         sparc_ldx (code, ins->inst_c0, sparc_g0, ins->dreg);
3010 #else
3011                         sparc_ld (code, ins->inst_c0, sparc_g0, ins->dreg);
3012 #endif
3013                         break;
3014                 case CEE_LDIND_I4:
3015 #ifdef SPARCV9
3016                         sparc_ldsw (code, ins->inst_c0, sparc_g0, ins->dreg);
3017 #else
3018                         sparc_ld (code, ins->inst_c0, sparc_g0, ins->dreg);
3019 #endif
3020                         break;
3021                 case CEE_LDIND_U4:
3022                         sparc_ld (code, ins->inst_c0, sparc_g0, ins->dreg);
3023                         break;
3024                 case OP_LOADU4_MEM:
3025                         sparc_set (code, ins->inst_c0, ins->dreg);
3026                         sparc_ld (code, ins->dreg, sparc_g0, ins->dreg);
3027                         break;
3028                 case OP_LOADI4_MEMBASE:
3029 #ifdef SPARCV9
3030                         EMIT_LOAD_MEMBASE (ins, ldsw);
3031 #else
3032                         EMIT_LOAD_MEMBASE (ins, ld);
3033 #endif
3034                         break;
3035                 case OP_LOADU4_MEMBASE:
3036                         EMIT_LOAD_MEMBASE (ins, ld);
3037                         break;
3038                 case OP_LOADU1_MEMBASE:
3039                         EMIT_LOAD_MEMBASE (ins, ldub);
3040                         break;
3041                 case OP_LOADI1_MEMBASE:
3042                         EMIT_LOAD_MEMBASE (ins, ldsb);
3043                         break;
3044                 case OP_LOADU2_MEMBASE:
3045                         EMIT_LOAD_MEMBASE (ins, lduh);
3046                         break;
3047                 case OP_LOADI2_MEMBASE:
3048                         EMIT_LOAD_MEMBASE (ins, ldsh);
3049                         break;
3050                 case OP_LOAD_MEMBASE:
3051 #ifdef SPARCV9
3052                                 EMIT_LOAD_MEMBASE (ins, ldx);
3053 #else
3054                                 EMIT_LOAD_MEMBASE (ins, ld);
3055 #endif
3056                         break;
3057 #ifdef SPARCV9
3058                 case OP_LOADI8_MEMBASE:
3059                         EMIT_LOAD_MEMBASE (ins, ldx);
3060                         break;
3061 #endif
3062                 case CEE_CONV_I1:
3063                         sparc_sll_imm (code, ins->sreg1, 24, sparc_o7);
3064                         sparc_sra_imm (code, sparc_o7, 24, ins->dreg);
3065                         break;
3066                 case CEE_CONV_I2:
3067                         sparc_sll_imm (code, ins->sreg1, 16, sparc_o7);
3068                         sparc_sra_imm (code, sparc_o7, 16, ins->dreg);
3069                         break;
3070                 case CEE_CONV_U1:
3071                         sparc_and_imm (code, FALSE, ins->sreg1, 0xff, ins->dreg);
3072                         break;
3073                 case CEE_CONV_U2:
3074                         sparc_sll_imm (code, ins->sreg1, 16, sparc_o7);
3075                         sparc_srl_imm (code, sparc_o7, 16, ins->dreg);
3076                         break;
3077                 case CEE_CONV_OVF_U4:
3078                         /* Only used on V9 */
3079                         sparc_cmp_imm (code, ins->sreg1, 0);
3080                         mono_add_patch_info (cfg, (guint8*)(code) - (cfg)->native_code,
3081                                                                  MONO_PATCH_INFO_EXC, "OverflowException");
3082                         sparc_branchp (code, 0, sparc_bl, sparc_xcc_short, 0, 0);
3083                         /* Delay slot */
3084                         sparc_set (code, 1, sparc_o7);
3085                         sparc_sllx_imm (code, sparc_o7, 32, sparc_o7);
3086                         sparc_cmp (code, ins->sreg1, sparc_o7);
3087                         mono_add_patch_info (cfg, (guint8*)(code) - (cfg)->native_code,
3088                                                                  MONO_PATCH_INFO_EXC, "OverflowException");
3089                         sparc_branchp (code, 0, sparc_bge, sparc_xcc_short, 0, 0);
3090                         sparc_nop (code);
3091                         sparc_mov_reg_reg (code, ins->sreg1, ins->dreg);
3092                         break;
3093                 case CEE_CONV_OVF_I4_UN:
3094                         /* Only used on V9 */
3095                         NOT_IMPLEMENTED;
3096                         break;
3097                 case CEE_CONV_U:
3098                 case CEE_CONV_U8:
3099                         /* Only used on V9 */
3100                         sparc_srl_imm (code, ins->sreg1, 0, ins->dreg);
3101                         break;
3102                 case CEE_CONV_I:
3103                 case CEE_CONV_I8:
3104                         /* Only used on V9 */
3105                         sparc_sra_imm (code, ins->sreg1, 0, ins->dreg);
3106                         break;
3107                 case OP_COMPARE:
3108                 case OP_LCOMPARE:
3109                 case OP_ICOMPARE:
3110                         sparc_cmp (code, ins->sreg1, ins->sreg2);
3111                         break;
3112                 case OP_COMPARE_IMM:
3113                 case OP_ICOMPARE_IMM:
3114                         if (sparc_is_imm13 (ins->inst_imm))
3115                                 sparc_cmp_imm (code, ins->sreg1, ins->inst_imm);
3116                         else {
3117                                 sparc_set (code, ins->inst_imm, sparc_o7);
3118                                 sparc_cmp (code, ins->sreg1, sparc_o7);
3119                         }
3120                         break;
3121                 case OP_X86_TEST_NULL:
3122                         sparc_cmp_imm (code, ins->sreg1, 0);
3123                         break;
3124                 case CEE_BREAK:
3125                         /*
3126                          * gdb does not like encountering 'ta 1' in the debugged code. So
3127                          * instead of emitting a trap, we emit a call a C function and place a
3128                          * breakpoint there.
3129                          */
3130                         //sparc_ta (code, 1);
3131                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_ABS, mono_sparc_break);
3132                         EMIT_CALL();
3133                         break;
3134                 case OP_ADDCC:
3135                 case OP_IADDCC:
3136                         sparc_add (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
3137                         break;
3138                 case CEE_ADD:
3139                 case OP_IADD:
3140                         sparc_add (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
3141                         break;
3142                 case OP_ADDCC_IMM:
3143                 case OP_ADD_IMM:
3144                 case OP_IADD_IMM:
3145                         /* according to inssel-long32.brg, this should set cc */
3146                         EMIT_ALU_IMM (ins, add, TRUE);
3147                         break;
3148                 case OP_ADC:
3149                 case OP_IADC:
3150                         /* according to inssel-long32.brg, this should set cc */
3151                         sparc_addx (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
3152                         break;
3153                 case OP_ADC_IMM:
3154                 case OP_IADC_IMM:
3155                         EMIT_ALU_IMM (ins, addx, TRUE);
3156                         break;
3157                 case OP_SUBCC:
3158                 case OP_ISUBCC:
3159                         sparc_sub (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
3160                         break;
3161                 case CEE_SUB:
3162                 case OP_ISUB:
3163                         sparc_sub (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
3164                         break;
3165                 case OP_SUBCC_IMM:
3166                 case OP_SUB_IMM:
3167                 case OP_ISUB_IMM:
3168                         /* according to inssel-long32.brg, this should set cc */
3169                         EMIT_ALU_IMM (ins, sub, TRUE);
3170                         break;
3171                 case OP_SBB:
3172                 case OP_ISBB:
3173                         /* according to inssel-long32.brg, this should set cc */
3174                         sparc_subx (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
3175                         break;
3176                 case OP_SBB_IMM:
3177                 case OP_ISBB_IMM:
3178                         EMIT_ALU_IMM (ins, subx, TRUE);
3179                         break;
3180                 case CEE_AND:
3181                 case OP_IAND:
3182                         sparc_and (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
3183                         break;
3184                 case OP_AND_IMM:
3185                 case OP_IAND_IMM:
3186                         EMIT_ALU_IMM (ins, and, FALSE);
3187                         break;
3188                 case CEE_DIV:
3189                 case OP_IDIV:
3190                         /* Sign extend sreg1 into %y */
3191                         sparc_sra_imm (code, ins->sreg1, 31, sparc_o7);
3192                         sparc_wry (code, sparc_o7, sparc_g0);
3193                         sparc_sdiv (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
3194                         EMIT_COND_SYSTEM_EXCEPTION_GENERAL (code, sparc_boverflow, "ArithmeticException", TRUE, sparc_icc_short);
3195                         break;
3196                 case CEE_DIV_UN:
3197                 case OP_IDIV_UN:
3198                         sparc_wry (code, sparc_g0, sparc_g0);
3199                         sparc_udiv (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
3200                         break;
3201                 case OP_DIV_IMM: {
3202                         int i, imm;
3203
3204                         /* Transform division into a shift */
3205                         for (i = 1; i < 30; ++i) {
3206                                 imm = (1 << i);
3207                                 if (ins->inst_imm == imm)
3208                                         break;
3209                         }
3210                         if (i < 30) {
3211                                 if (i == 1) {
3212                                         /* gcc 2.95.3 */
3213                                         sparc_srl_imm (code, ins->sreg1, 31, sparc_o7);
3214                                         sparc_add (code, FALSE, ins->sreg1, sparc_o7, ins->dreg);
3215                                         sparc_sra_imm (code, ins->dreg, 1, ins->dreg);
3216                                 }
3217                                 else {
3218                                         /* http://compilers.iecc.com/comparch/article/93-04-079 */
3219                                         sparc_sra_imm (code, ins->sreg1, 31, sparc_o7);
3220                                         sparc_srl_imm (code, sparc_o7, 32 - i, sparc_o7);
3221                                         sparc_add (code, FALSE, ins->sreg1, sparc_o7, ins->dreg);
3222                                         sparc_sra_imm (code, ins->dreg, i, ins->dreg);
3223                                 }
3224                         }
3225                         else {
3226                                 /* Sign extend sreg1 into %y */
3227                                 sparc_sra_imm (code, ins->sreg1, 31, sparc_o7);
3228                                 sparc_wry (code, sparc_o7, sparc_g0);
3229                                 EMIT_ALU_IMM (ins, sdiv, TRUE);
3230                                 EMIT_COND_SYSTEM_EXCEPTION_GENERAL (code, sparc_boverflow, "ArithmeticException", TRUE, sparc_icc_short);
3231                         }
3232                         break;
3233                 }
3234                 case CEE_REM:
3235                 case OP_IREM:
3236                         /* Sign extend sreg1 into %y */
3237                         sparc_sra_imm (code, ins->sreg1, 31, sparc_o7);
3238                         sparc_wry (code, sparc_o7, sparc_g0);
3239                         sparc_sdiv (code, TRUE, ins->sreg1, ins->sreg2, sparc_o7);
3240                         EMIT_COND_SYSTEM_EXCEPTION_GENERAL (code, sparc_boverflow, "ArithmeticException", TRUE, sparc_icc_short);
3241                         sparc_smul (code, FALSE, ins->sreg2, sparc_o7, sparc_o7);
3242                         sparc_sub (code, FALSE, ins->sreg1, sparc_o7, ins->dreg);
3243                         break;
3244                 case CEE_REM_UN:
3245                 case OP_IREM_UN:
3246                         sparc_wry (code, sparc_g0, sparc_g0);
3247                         sparc_udiv (code, FALSE, ins->sreg1, ins->sreg2, sparc_o7);
3248                         sparc_umul (code, FALSE, ins->sreg2, sparc_o7, sparc_o7);
3249                         sparc_sub (code, FALSE, ins->sreg1, sparc_o7, ins->dreg);
3250                         break;
3251                 case OP_REM_IMM:
3252                 case OP_IREM_IMM:
3253                         /* Sign extend sreg1 into %y */
3254                         sparc_sra_imm (code, ins->sreg1, 31, sparc_o7);
3255                         sparc_wry (code, sparc_o7, sparc_g0);
3256                         if (!sparc_is_imm13 (ins->inst_imm)) {
3257                                 sparc_set (code, ins->inst_imm, GP_SCRATCH_REG);
3258                                 sparc_sdiv (code, TRUE, ins->sreg1, GP_SCRATCH_REG, sparc_o7);
3259                                 EMIT_COND_SYSTEM_EXCEPTION_GENERAL (code, sparc_boverflow, "ArithmeticException", TRUE, sparc_icc_short);
3260                                 sparc_smul (code, FALSE, sparc_o7, GP_SCRATCH_REG, sparc_o7);
3261                         }
3262                         else {
3263                                 sparc_sdiv_imm (code, TRUE, ins->sreg1, ins->inst_imm, sparc_o7);
3264                                 EMIT_COND_SYSTEM_EXCEPTION_GENERAL (code, sparc_boverflow, "ArithmeticException", TRUE, sparc_icc_short);
3265                                 sparc_smul_imm (code, FALSE, sparc_o7, ins->inst_imm, sparc_o7);
3266                         }
3267                         sparc_sub (code, FALSE, ins->sreg1, sparc_o7, ins->dreg);
3268                         break;
3269                 case CEE_OR:
3270                 case OP_IOR:
3271                         sparc_or (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
3272                         break;
3273                 case OP_OR_IMM:
3274                 case OP_IOR_IMM:
3275                         EMIT_ALU_IMM (ins, or, FALSE);
3276                         break;
3277                 case CEE_XOR:
3278                 case OP_IXOR:
3279                         sparc_xor (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
3280                         break;
3281                 case OP_XOR_IMM:
3282                 case OP_IXOR_IMM:
3283                         EMIT_ALU_IMM (ins, xor, FALSE);
3284                         break;
3285                 case CEE_SHL:
3286                 case OP_ISHL:
3287                         sparc_sll (code, ins->sreg1, ins->sreg2, ins->dreg);
3288                         break;
3289                 case OP_SHL_IMM:
3290                 case OP_ISHL_IMM:
3291                         if (ins->inst_imm < (1 << 5))
3292                                 sparc_sll_imm (code, ins->sreg1, ins->inst_imm, ins->dreg);
3293                         else {
3294                                 sparc_set (code, ins->inst_imm, sparc_o7);
3295                                 sparc_sll (code, ins->sreg1, sparc_o7, ins->dreg);
3296                         }
3297                         break;
3298                 case CEE_SHR:
3299                 case OP_ISHR:
3300                         sparc_sra (code, ins->sreg1, ins->sreg2, ins->dreg);
3301                         break;
3302                 case OP_ISHR_IMM:
3303                 case OP_SHR_IMM:
3304                         if (ins->inst_imm < (1 << 5))
3305                                 sparc_sra_imm (code, ins->sreg1, ins->inst_imm, ins->dreg);
3306                         else {
3307                                 sparc_set (code, ins->inst_imm, sparc_o7);
3308                                 sparc_sra (code, ins->sreg1, sparc_o7, ins->dreg);
3309                         }
3310                         break;
3311                 case OP_SHR_UN_IMM:
3312                 case OP_ISHR_UN_IMM:
3313                         if (ins->inst_imm < (1 << 5))
3314                                 sparc_srl_imm (code, ins->sreg1, ins->inst_imm, ins->dreg);
3315                         else {
3316                                 sparc_set (code, ins->inst_imm, sparc_o7);
3317                                 sparc_srl (code, ins->sreg1, sparc_o7, ins->dreg);
3318                         }
3319                         break;
3320                 case CEE_SHR_UN:
3321                 case OP_ISHR_UN:
3322                         sparc_srl (code, ins->sreg1, ins->sreg2, ins->dreg);
3323                         break;
3324                 case OP_LSHL:
3325                         sparc_sllx (code, ins->sreg1, ins->sreg2, ins->dreg);
3326                         break;
3327                 case OP_LSHL_IMM:
3328                         if (ins->inst_imm < (1 << 6))
3329                                 sparc_sllx_imm (code, ins->sreg1, ins->inst_imm, ins->dreg);
3330                         else {
3331                                 sparc_set (code, ins->inst_imm, sparc_o7);
3332                                 sparc_sllx (code, ins->sreg1, sparc_o7, ins->dreg);
3333                         }
3334                         break;
3335                 case OP_LSHR:
3336                         sparc_srax (code, ins->sreg1, ins->sreg2, ins->dreg);
3337                         break;
3338                 case OP_LSHR_IMM:
3339                         if (ins->inst_imm < (1 << 6))
3340                                 sparc_srax_imm (code, ins->sreg1, ins->inst_imm, ins->dreg);
3341                         else {
3342                                 sparc_set (code, ins->inst_imm, sparc_o7);
3343                                 sparc_srax (code, ins->sreg1, sparc_o7, ins->dreg);
3344                         }
3345                         break;
3346                 case OP_LSHR_UN:
3347                         sparc_srlx (code, ins->sreg1, ins->sreg2, ins->dreg);
3348                         break;
3349                 case OP_LSHR_UN_IMM:
3350                         if (ins->inst_imm < (1 << 6))
3351                                 sparc_srlx_imm (code, ins->sreg1, ins->inst_imm, ins->dreg);
3352                         else {
3353                                 sparc_set (code, ins->inst_imm, sparc_o7);
3354                                 sparc_srlx (code, ins->sreg1, sparc_o7, ins->dreg);
3355                         }
3356                         break;
3357                 case CEE_NOT:
3358                 case OP_INOT:
3359                         /* can't use sparc_not */
3360                         sparc_xnor (code, FALSE, ins->sreg1, sparc_g0, ins->dreg);
3361                         break;
3362                 case CEE_NEG:
3363                 case OP_INEG:
3364                         /* can't use sparc_neg */
3365                         sparc_sub (code, FALSE, sparc_g0, ins->sreg1, ins->dreg);
3366                         break;
3367                 case CEE_MUL:
3368                 case OP_IMUL:
3369                         sparc_smul (code, FALSE, ins->sreg1, ins->sreg2, ins->dreg);
3370                         break;
3371                 case OP_IMUL_IMM:
3372                 case OP_MUL_IMM: {
3373                         int i, imm;
3374
3375                         if ((ins->inst_imm == 1) && (ins->sreg1 == ins->dreg))
3376                                 break;
3377
3378                         /* Transform multiplication into a shift */
3379                         for (i = 0; i < 30; ++i) {
3380                                 imm = (1 << i);
3381                                 if (ins->inst_imm == imm)
3382                                         break;
3383                         }
3384                         if (i < 30)
3385                                 sparc_sll_imm (code, ins->sreg1, i, ins->dreg);
3386                         else
3387                                 EMIT_ALU_IMM (ins, smul, FALSE);
3388                         break;
3389                 }
3390                 case CEE_MUL_OVF:
3391                 case OP_IMUL_OVF:
3392                         sparc_smul (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
3393                         sparc_rdy (code, sparc_g1);
3394                         sparc_sra_imm (code, ins->dreg, 31, sparc_o7);
3395                         sparc_cmp (code, sparc_g1, sparc_o7);
3396                         EMIT_COND_SYSTEM_EXCEPTION_GENERAL (ins, sparc_bne, "OverflowException", TRUE, sparc_icc_short);
3397                         break;
3398                 case CEE_MUL_OVF_UN:
3399                 case OP_IMUL_OVF_UN:
3400                         sparc_umul (code, TRUE, ins->sreg1, ins->sreg2, ins->dreg);
3401                         sparc_rdy (code, sparc_o7);
3402                         sparc_cmp (code, sparc_o7, sparc_g0);
3403                         EMIT_COND_SYSTEM_EXCEPTION_GENERAL (ins, sparc_bne, "OverflowException", TRUE, sparc_icc_short);
3404                         break;
3405                 case OP_ICONST:
3406                 case OP_SETREGIMM:
3407                         sparc_set (code, ins->inst_c0, ins->dreg);
3408                         break;
3409                 case OP_I8CONST:
3410                         sparc_set (code, ins->inst_l, ins->dreg);
3411                         break;
3412                 case OP_AOTCONST:
3413                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3414                         sparc_set_template (code, ins->dreg);
3415                         break;
3416                 case CEE_CONV_I4:
3417                 case CEE_CONV_U4:
3418                 case OP_MOVE:
3419                 case OP_SETREG:
3420                         if (ins->sreg1 != ins->dreg)
3421                                 sparc_mov_reg_reg (code, ins->sreg1, ins->dreg);
3422                         break;
3423                 case OP_SETFREG:
3424                         /* Only used on V9 */
3425                         if (ins->sreg1 != ins->dreg)
3426                                 sparc_fmovd (code, ins->sreg1, ins->dreg);
3427                         break;
3428                 case OP_SPARC_SETFREG_FLOAT:
3429                         /* Only used on V9 */
3430                         sparc_fdtos (code, ins->sreg1, ins->dreg);
3431                         break;
3432                 case CEE_JMP:
3433                         if (cfg->method->save_lmf)
3434                                 NOT_IMPLEMENTED;
3435
3436                         code = emit_load_volatile_arguments (cfg, code);
3437                         mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3438                         sparc_set_template (code, sparc_o7);
3439                         sparc_jmpl (code, sparc_o7, sparc_g0, sparc_g0);
3440                         /* Restore parent frame in delay slot */
3441                         sparc_restore_imm (code, sparc_g0, 0, sparc_g0);
3442                         break;
3443                 case OP_CHECK_THIS:
3444                         /* ensure ins->sreg1 is not NULL */
3445                         sparc_ld_imm (code, ins->sreg1, 0, sparc_g0);
3446                         break;
3447                 case OP_ARGLIST:
3448                         sparc_add_imm (code, FALSE, sparc_fp, cfg->sig_cookie, sparc_o7);
3449                         sparc_sti_imm (code, sparc_o7, ins->sreg1, 0);
3450                         break;
3451                 case OP_FCALL:
3452                 case OP_LCALL:
3453                 case OP_VCALL:
3454                 case OP_VOIDCALL:
3455                 case CEE_CALL:
3456                         call = (MonoCallInst*)ins;
3457                         g_assert (!call->virtual);
3458                         code = emit_save_sp_to_lmf (cfg, code);
3459                         if (ins->flags & MONO_INST_HAS_METHOD)
3460                             code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3461                         else
3462                             code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3463
3464                         code = emit_vret_token (ins, code);
3465                         code = emit_move_return_value (ins, code);
3466                         break;
3467                 case OP_FCALL_REG:
3468                 case OP_LCALL_REG:
3469                 case OP_VCALL_REG:
3470                 case OP_VOIDCALL_REG:
3471                 case OP_CALL_REG:
3472                         call = (MonoCallInst*)ins;
3473                         code = emit_save_sp_to_lmf (cfg, code);
3474                         sparc_jmpl (code, ins->sreg1, sparc_g0, sparc_callsite);
3475                         /*
3476                          * We emit a special kind of nop in the delay slot to tell the
3477                          * trampoline code that this is a virtual call, thus an unbox
3478                          * trampoline might need to be called.
3479                          */
3480                         if (call->virtual)
3481                                 sparc_or_imm (code, FALSE, sparc_g0, 0xca, sparc_g0);
3482                         else
3483                                 sparc_nop (code);
3484
3485                         code = emit_vret_token (ins, code);
3486                         code = emit_move_return_value (ins, code);
3487                         break;
3488                 case OP_FCALL_MEMBASE:
3489                 case OP_LCALL_MEMBASE:
3490                 case OP_VCALL_MEMBASE:
3491                 case OP_VOIDCALL_MEMBASE:
3492                 case OP_CALL_MEMBASE:
3493                         call = (MonoCallInst*)ins;
3494                         g_assert (sparc_is_imm13 (ins->inst_offset));
3495                         code = emit_save_sp_to_lmf (cfg, code);
3496                         sparc_ldi_imm (code, ins->inst_basereg, ins->inst_offset, sparc_o7);
3497                         sparc_jmpl (code, sparc_o7, sparc_g0, sparc_callsite);
3498                         if (call->virtual)
3499                                 sparc_or_imm (code, FALSE, sparc_g0, 0xca, sparc_g0);
3500                         else
3501                                 sparc_nop (code);
3502
3503                         code = emit_vret_token (ins, code);
3504                         code = emit_move_return_value (ins, code);
3505                         break;
3506                 case OP_SETFRET:
3507                         if (cfg->method->signature->ret->type == MONO_TYPE_R4)
3508                                 sparc_fdtos (code, ins->sreg1, sparc_f0);
3509                         else {
3510 #ifdef SPARCV9
3511                                 sparc_fmovd (code, ins->sreg1, ins->dreg);
3512 #else
3513                                 /* FIXME: Why not use fmovd ? */
3514                                 sparc_fmovs (code, ins->sreg1, ins->dreg);
3515                                 sparc_fmovs (code, ins->sreg1 + 1, ins->dreg + 1);
3516 #endif
3517                         }
3518                         break;
3519                 case OP_OUTARG:
3520                         g_assert_not_reached ();
3521                         break;
3522                 case OP_LOCALLOC:
3523                         /* Keep alignment */
3524                         sparc_add_imm (code, FALSE, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1, ins->dreg);
3525                         sparc_set (code, ~(MONO_ARCH_FRAME_ALIGNMENT - 1), sparc_o7);
3526                         sparc_and (code, FALSE, ins->dreg, sparc_o7, ins->dreg);
3527                         sparc_sub (code, FALSE, sparc_sp, ins->dreg, ins->dreg);
3528                         /* Keep %sp valid at all times */
3529                         sparc_mov_reg_reg (code, ins->dreg, sparc_sp);
3530                         g_assert (sparc_is_imm13 (cfg->arch.localloc_offset));
3531                         sparc_add_imm (code, FALSE, ins->dreg, MONO_SPARC_STACK_BIAS + cfg->arch.localloc_offset, ins->dreg);
3532                         break;
3533                 case OP_SPARC_LOCALLOC_IMM: {
3534                         gint32 offset = ins->inst_c0;
3535                         offset = ALIGN_TO (offset, MONO_ARCH_FRAME_ALIGNMENT);
3536                         if (sparc_is_imm13 (offset))
3537                                 sparc_sub_imm (code, FALSE, sparc_sp, offset, sparc_sp);
3538                         else {
3539                                 sparc_set (code, offset, sparc_o7);
3540                                 sparc_sub (code, FALSE, sparc_sp, sparc_o7, sparc_sp);
3541                         }
3542                         sparc_mov_reg_reg (code, sparc_sp, ins->dreg);
3543                         g_assert (sparc_is_imm13 (cfg->arch.localloc_offset));
3544                         sparc_add_imm (code, FALSE, ins->dreg, MONO_SPARC_STACK_BIAS + cfg->arch.localloc_offset, ins->dreg);
3545                         break;
3546                 }
3547                 case CEE_RET:
3548                         /* The return is done in the epilog */
3549                         g_assert_not_reached ();
3550                         break;
3551                 case CEE_THROW:
3552                         sparc_mov_reg_reg (code, ins->sreg1, sparc_o0);
3553                         mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
3554                                              (gpointer)"mono_arch_throw_exception");
3555                         EMIT_CALL ();
3556                         break;
3557                 case OP_START_HANDLER: {
3558                         /*
3559                          * The START_HANDLER instruction marks the beginning of a handler
3560                          * block. It is called using a call instruction, so %o7 contains
3561                          * the return address. Since the handler executes in the same stack
3562              * frame as the method itself, we can't use save/restore to save
3563                          * the return address. Instead, we save it into a dedicated
3564                          * variable.
3565                          */
3566                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3567                         if (!sparc_is_imm13 (spvar->inst_offset)) {
3568                                 sparc_set (code, spvar->inst_offset, GP_SCRATCH_REG);
3569                                 sparc_sti (code, sparc_o7, spvar->inst_basereg, GP_SCRATCH_REG);
3570                         }
3571                         else
3572                                 sparc_sti_imm (code, sparc_o7, spvar->inst_basereg, spvar->inst_offset);
3573                         break;
3574                 }
3575                 case OP_ENDFILTER: {
3576                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3577                         if (!sparc_is_imm13 (spvar->inst_offset)) {
3578                                 sparc_set (code, spvar->inst_offset, GP_SCRATCH_REG);
3579                                 sparc_ldi (code, spvar->inst_basereg, GP_SCRATCH_REG, sparc_o7);
3580                         }
3581                         else
3582                                 sparc_ldi_imm (code, spvar->inst_basereg, spvar->inst_offset, sparc_o7);
3583                         sparc_jmpl_imm (code, sparc_o7, 8, sparc_g0);
3584                         /* Delay slot */
3585                         sparc_mov_reg_reg (code, ins->sreg1, sparc_o0);
3586                         break;
3587                 }
3588                 case CEE_ENDFINALLY: {
3589                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3590                         if (!sparc_is_imm13 (spvar->inst_offset)) {
3591                                 sparc_set (code, spvar->inst_offset, GP_SCRATCH_REG);
3592                                 sparc_ldi (code, spvar->inst_basereg, GP_SCRATCH_REG, sparc_o7);
3593                         }
3594                         else
3595                                 sparc_ldi_imm (code, spvar->inst_basereg, spvar->inst_offset, sparc_o7);
3596                         sparc_jmpl_imm (code, sparc_o7, 8, sparc_g0);
3597                         sparc_nop (code);
3598                         break;
3599                 }
3600                 case OP_CALL_HANDLER:
3601                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3602                         /* This is a jump inside the method, so call_simple works even on V9 */
3603                         sparc_call_simple (code, 0);
3604                         sparc_nop (code);
3605                         break;
3606                 case OP_LABEL:
3607                         ins->inst_c0 = (guint8*)code - cfg->native_code;
3608                         break;
3609                 case CEE_BR:
3610                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3611                         if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3612                                 break;
3613                         if (ins->flags & MONO_INST_BRLABEL) {
3614                                 if (ins->inst_i0->inst_c0) {
3615                                         gint32 disp = (ins->inst_i0->inst_c0 - ((guint8*)code - cfg->native_code)) >> 2;
3616                                         g_assert (sparc_is_imm22 (disp));
3617                                         sparc_branch (code, 1, sparc_ba, disp);
3618                                 } else {
3619                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3620                                         sparc_branch (code, 1, sparc_ba, 0);
3621                                 }
3622                         } else {
3623                                 if (ins->inst_target_bb->native_offset) {
3624                                         gint32 disp = (ins->inst_target_bb->native_offset - ((guint8*)code - cfg->native_code)) >> 2;
3625                                         g_assert (sparc_is_imm22 (disp));
3626                                         sparc_branch (code, 1, sparc_ba, disp);
3627                                 } else {
3628                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3629                                         sparc_branch (code, 1, sparc_ba, 0);
3630                                 }
3631                         }
3632                         sparc_nop (code);
3633                         break;
3634                 case OP_BR_REG:
3635                         sparc_jmp (code, ins->sreg1, sparc_g0);
3636                         sparc_nop (code);
3637                         break;
3638                 case OP_CEQ:
3639                 case OP_CLT:
3640                 case OP_CLT_UN:
3641                 case OP_CGT:
3642                 case OP_CGT_UN:
3643                         if (v64 && (cfg->opt & MONO_OPT_CMOV)) {
3644                                 sparc_clr_reg (code, ins->dreg);
3645                                 sparc_movcc_imm (code, sparc_xcc, opcode_to_sparc_cond (ins->opcode), 1, ins->dreg);
3646                         }
3647                         else {
3648                                 sparc_clr_reg (code, ins->dreg);
3649 #ifdef SPARCV9
3650                                 sparc_branchp (code, 1, opcode_to_sparc_cond (ins->opcode), DEFAULT_ICC, 0, 2);
3651 #else
3652                                 sparc_branch (code, 1, opcode_to_sparc_cond (ins->opcode), 2);
3653 #endif
3654                                 /* delay slot */
3655                                 sparc_set (code, 1, ins->dreg);
3656                         }
3657                         break;
3658                 case OP_ICEQ:
3659                 case OP_ICLT:
3660                 case OP_ICLT_UN:
3661                 case OP_ICGT:
3662                 case OP_ICGT_UN:
3663                     if (v64 && (cfg->opt & MONO_OPT_CMOV)) {
3664                                 sparc_clr_reg (code, ins->dreg);
3665                                 sparc_movcc_imm (code, sparc_icc, opcode_to_sparc_cond (ins->opcode), 1, ins->dreg);
3666                     }
3667                     else {
3668                         sparc_clr_reg (code, ins->dreg);
3669                         sparc_branchp (code, 1, opcode_to_sparc_cond (ins->opcode), sparc_icc_short, 0, 2);
3670                         /* delay slot */
3671                         sparc_set (code, 1, ins->dreg);
3672                     }
3673                     break;
3674                 case OP_COND_EXC_EQ:
3675                 case OP_COND_EXC_NE_UN:
3676                 case OP_COND_EXC_LT:
3677                 case OP_COND_EXC_LT_UN:
3678                 case OP_COND_EXC_GT:
3679                 case OP_COND_EXC_GT_UN:
3680                 case OP_COND_EXC_GE:
3681                 case OP_COND_EXC_GE_UN:
3682                 case OP_COND_EXC_LE:
3683                 case OP_COND_EXC_LE_UN:
3684                 case OP_COND_EXC_OV:
3685                 case OP_COND_EXC_NO:
3686                 case OP_COND_EXC_C:
3687                 case OP_COND_EXC_NC:
3688                         EMIT_COND_SYSTEM_EXCEPTION (ins, opcode_to_sparc_cond (ins->opcode), ins->inst_p1);
3689                         break;
3690                 case OP_SPARC_COND_EXC_EQZ:
3691                         EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brz, ins->inst_p1);
3692                         break;
3693                 case OP_SPARC_COND_EXC_GEZ:
3694                         EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brgez, ins->inst_p1);
3695                         break;
3696                 case OP_SPARC_COND_EXC_GTZ:
3697                         EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brgz, ins->inst_p1);
3698                         break;
3699                 case OP_SPARC_COND_EXC_LEZ:
3700                         EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brlez, ins->inst_p1);
3701                         break;
3702                 case OP_SPARC_COND_EXC_LTZ:
3703                         EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brlz, ins->inst_p1);
3704                         break;
3705                 case OP_SPARC_COND_EXC_NEZ:
3706                         EMIT_COND_SYSTEM_EXCEPTION_BPR (ins, brnz, ins->inst_p1);
3707                         break;
3708                 case OP_COND_EXC_IOV:
3709                 case OP_COND_EXC_IC:
3710                         EMIT_COND_SYSTEM_EXCEPTION_GENERAL (ins, opcode_to_sparc_cond (ins->opcode), ins->inst_p1, TRUE, sparc_icc_short);
3711                         break;
3712                 case CEE_BEQ:
3713                 case CEE_BNE_UN:
3714                 case CEE_BLT:
3715                 case CEE_BLT_UN:
3716                 case CEE_BGT:
3717                 case CEE_BGT_UN:
3718                 case CEE_BGE:
3719                 case CEE_BGE_UN:
3720                 case CEE_BLE:
3721                 case CEE_BLE_UN: {
3722                         if (sparcv9)
3723                                 EMIT_COND_BRANCH_PREDICTED (ins, opcode_to_sparc_cond (ins->opcode), 1, 1);
3724                         else
3725                                 EMIT_COND_BRANCH (ins, opcode_to_sparc_cond (ins->opcode), 1, 1);
3726                         break;
3727                 }
3728
3729                 case OP_IBEQ:
3730                 case OP_IBNE_UN:
3731                 case OP_IBLT:
3732                 case OP_IBLT_UN:
3733                 case OP_IBGT:
3734                 case OP_IBGT_UN:
3735                 case OP_IBGE:
3736                 case OP_IBGE_UN:
3737                 case OP_IBLE:
3738                 case OP_IBLE_UN: {
3739                         /* Only used on V9 */
3740                         EMIT_COND_BRANCH_ICC (ins, opcode_to_sparc_cond (ins->opcode), 1, 1, sparc_icc_short);
3741                         break;
3742                 }
3743
3744                 case OP_SPARC_BRZ:
3745                         EMIT_COND_BRANCH_BPR (ins, brz, 1, 1, 1);
3746                         break;
3747                 case OP_SPARC_BRLEZ:
3748                         EMIT_COND_BRANCH_BPR (ins, brlez, 1, 1, 1);
3749                         break;
3750                 case OP_SPARC_BRLZ:
3751                         EMIT_COND_BRANCH_BPR (ins, brlz, 1, 1, 1);
3752                         break;
3753                 case OP_SPARC_BRNZ:
3754                         EMIT_COND_BRANCH_BPR (ins, brnz, 1, 1, 1);
3755                         break;
3756                 case OP_SPARC_BRGZ:
3757                         EMIT_COND_BRANCH_BPR (ins, brgz, 1, 1, 1);
3758                         break;
3759                 case OP_SPARC_BRGEZ:
3760                         EMIT_COND_BRANCH_BPR (ins, brgez, 1, 1, 1);
3761                         break;
3762
3763                 /* floating point opcodes */
3764                 case OP_R8CONST:
3765                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3766 #ifdef SPARCV9
3767                         sparc_set_template (code, sparc_o7);
3768 #else
3769                         sparc_sethi (code, 0, sparc_o7);
3770 #endif
3771                         sparc_lddf_imm (code, sparc_o7, 0, ins->dreg);
3772                         break;
3773                 case OP_R4CONST:
3774                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3775 #ifdef SPARCV9
3776                         sparc_set_template (code, sparc_o7);
3777 #else
3778                         sparc_sethi (code, 0, sparc_o7);
3779 #endif
3780                         sparc_ldf_imm (code, sparc_o7, 0, FP_SCRATCH_REG);
3781
3782                         /* Extend to double */
3783                         sparc_fstod (code, FP_SCRATCH_REG, ins->dreg);
3784                         break;
3785                 case OP_STORER8_MEMBASE_REG:
3786                         if (!sparc_is_imm13 (ins->inst_offset + 4)) {
3787                                 sparc_set (code, ins->inst_offset, sparc_o7);
3788                                 /* SPARCV9 handles misaligned fp loads/stores */
3789                                 if (!v64 && (ins->inst_offset % 8)) {
3790                                         /* Misaligned */
3791                                         sparc_add (code, FALSE, ins->inst_destbasereg, sparc_o7, sparc_o7);
3792                                         sparc_stf (code, ins->sreg1, sparc_o7, sparc_g0);
3793                                         sparc_stf_imm (code, ins->sreg1 + 1, sparc_o7, 4);
3794                                 } else
3795                                         sparc_stdf (code, ins->sreg1, ins->inst_destbasereg, sparc_o7);
3796                         }
3797                         else {
3798                                 if (!v64 && (ins->inst_offset % 8)) {
3799                                         /* Misaligned */
3800                                         sparc_stf_imm (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3801                                         sparc_stf_imm (code, ins->sreg1 + 1, ins->inst_destbasereg, ins->inst_offset + 4);
3802                                 } else
3803                                         sparc_stdf_imm (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
3804                         }
3805                         break;
3806                 case OP_LOADR8_MEMBASE:
3807                         EMIT_LOAD_MEMBASE (ins, lddf);
3808                         break;
3809                 case OP_STORER4_MEMBASE_REG:
3810                         /* This requires a double->single conversion */
3811                         sparc_fdtos (code, ins->sreg1, FP_SCRATCH_REG);
3812                         if (!sparc_is_imm13 (ins->inst_offset)) {
3813                                 sparc_set (code, ins->inst_offset, sparc_o7);
3814                                 sparc_stf (code, FP_SCRATCH_REG, ins->inst_destbasereg, sparc_o7);
3815                         }
3816                         else
3817                                 sparc_stf_imm (code, FP_SCRATCH_REG, ins->inst_destbasereg, ins->inst_offset);
3818                         break;
3819                 case OP_LOADR4_MEMBASE: {
3820                         /* ldf needs a single precision register */
3821                         int dreg = ins->dreg;
3822                         ins->dreg = FP_SCRATCH_REG;
3823                         EMIT_LOAD_MEMBASE (ins, ldf);
3824                         ins->dreg = dreg;
3825                         /* Extend to double */
3826                         sparc_fstod (code, FP_SCRATCH_REG, ins->dreg);
3827                         break;
3828                 }
3829                 case OP_FMOVE:
3830 #ifdef SPARCV9
3831                         sparc_fmovd (code, ins->sreg1, ins->dreg);
3832 #else
3833                         sparc_fmovs (code, ins->sreg1, ins->dreg);
3834                         sparc_fmovs (code, ins->sreg1 + 1, ins->dreg + 1);
3835 #endif
3836                         break;
3837                 case CEE_CONV_R4: {
3838                         gint32 offset = mono_spillvar_offset_float (cfg, 0);
3839                         if (!sparc_is_imm13 (offset))
3840                                 NOT_IMPLEMENTED;
3841 #ifdef SPARCV9
3842                         sparc_stx_imm (code, ins->sreg1, sparc_sp, offset);
3843                         sparc_lddf_imm (code, sparc_sp, offset, FP_SCRATCH_REG);
3844                         sparc_fxtos (code, FP_SCRATCH_REG, FP_SCRATCH_REG);
3845 #else
3846                         sparc_st_imm (code, ins->sreg1, sparc_sp, offset);
3847                         sparc_ldf_imm (code, sparc_sp, offset, FP_SCRATCH_REG);
3848                         sparc_fitos (code, FP_SCRATCH_REG, FP_SCRATCH_REG);
3849 #endif
3850                         sparc_fstod (code, FP_SCRATCH_REG, ins->dreg);
3851                         break;
3852                 }
3853                 case CEE_CONV_R8: {
3854                         gint32 offset = mono_spillvar_offset_float (cfg, 0);
3855                         if (!sparc_is_imm13 (offset))
3856                                 NOT_IMPLEMENTED;
3857 #ifdef SPARCV9
3858                         sparc_stx_imm (code, ins->sreg1, sparc_sp, offset);
3859                         sparc_lddf_imm (code, sparc_sp, offset, FP_SCRATCH_REG);
3860                         sparc_fxtod (code, FP_SCRATCH_REG, ins->dreg);
3861 #else
3862                         sparc_st_imm (code, ins->sreg1, sparc_sp, offset);
3863                         sparc_ldf_imm (code, sparc_sp, offset, FP_SCRATCH_REG);
3864                         sparc_fitod (code, FP_SCRATCH_REG, ins->dreg);
3865 #endif
3866                         break;
3867                 }
3868                 case OP_FCONV_TO_I1:
3869                 case OP_FCONV_TO_U1:
3870                 case OP_FCONV_TO_I2:
3871                 case OP_FCONV_TO_U2:
3872 #ifndef SPARCV9
3873                 case OP_FCONV_TO_I:
3874                 case OP_FCONV_TO_U:
3875 #endif
3876                 case OP_FCONV_TO_I4:
3877                 case OP_FCONV_TO_U4: {
3878                         gint32 offset = mono_spillvar_offset_float (cfg, 0);
3879                         if (!sparc_is_imm13 (offset))
3880                                 NOT_IMPLEMENTED;
3881                         /* FIXME: Is having the same code for all of these ok ? */
3882                         sparc_fdtoi (code, ins->sreg1, FP_SCRATCH_REG);
3883                         sparc_stdf_imm (code, FP_SCRATCH_REG, sparc_sp, offset);
3884                         sparc_ld_imm (code, sparc_sp, offset, ins->dreg);
3885                         break;
3886                 }
3887                 case OP_FCONV_TO_I8:
3888                 case OP_FCONV_TO_U8:
3889                         /* Emulated */
3890                         g_assert_not_reached ();
3891                         break;
3892                 case CEE_CONV_R_UN:
3893                         /* Emulated */
3894                         g_assert_not_reached ();
3895                         break;
3896                 case OP_LCONV_TO_R_UN: {
3897                         /* Emulated */
3898                         g_assert_not_reached ();
3899                         break;
3900                 }
3901                 case OP_LCONV_TO_OVF_I: {
3902                         guint32 *br [3], *label [1];
3903
3904                         /*
3905                          * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3906                          */
3907                         sparc_cmp_imm (code, ins->sreg1, 0);
3908                         br [0] = code;
3909                         sparc_branch (code, 1, sparc_bneg, 0);
3910                         sparc_nop (code);
3911
3912                         /* positive */
3913                         /* ms word must be 0 */
3914                         sparc_cmp_imm (code, ins->sreg2, 0);
3915                         br [1] = code;
3916                         sparc_branch (code, 1, sparc_be, 0);
3917                         sparc_nop (code);
3918
3919                         label [0] = code;
3920
3921                         EMIT_COND_SYSTEM_EXCEPTION (ins, sparc_ba, "OverflowException");
3922
3923                         /* negative */
3924                         sparc_patch (br [0], code);
3925
3926                         /* ms word must 0xfffffff */
3927                         sparc_cmp_imm (code, ins->sreg2, -1);
3928                         br [2] = code;
3929                         sparc_branch (code, 1, sparc_bne, 0);
3930                         sparc_patch (br [2], label [0]);
3931
3932                         /* Ok */
3933                         sparc_patch (br [1], code);
3934                         if (ins->sreg1 != ins->dreg)
3935                                 sparc_mov_reg_reg (code, ins->sreg1, ins->dreg);
3936                         break;
3937                 }
3938                 case OP_FADD:
3939                         sparc_faddd (code, ins->sreg1, ins->sreg2, ins->dreg);
3940                         break;
3941                 case OP_FSUB:
3942                         sparc_fsubd (code, ins->sreg1, ins->sreg2, ins->dreg);
3943                         break;
3944                 case OP_FMUL:
3945                         sparc_fmuld (code, ins->sreg1, ins->sreg2, ins->dreg);
3946                         break;
3947                 case OP_FDIV:
3948                         sparc_fdivd (code, ins->sreg1, ins->sreg2, ins->dreg);
3949                         break;
3950                 case OP_FNEG:
3951 #ifdef SPARCV9
3952                         sparc_fnegd (code, ins->sreg1, ins->dreg);
3953 #else
3954                         /* FIXME: why don't use fnegd ? */
3955                         sparc_fnegs (code, ins->sreg1, ins->dreg);
3956 #endif
3957                         break;
3958                 case OP_FREM:
3959                         sparc_fdivd (code, ins->sreg1, ins->sreg2, FP_SCRATCH_REG);
3960                         sparc_fmuld (code, ins->sreg2, FP_SCRATCH_REG, FP_SCRATCH_REG);
3961                         sparc_fsubd (code, ins->sreg1, FP_SCRATCH_REG, ins->dreg);
3962                         break;
3963                 case OP_FCOMPARE:
3964                         sparc_fcmpd (code, ins->sreg1, ins->sreg2);
3965                         break;
3966                 case OP_FCEQ:
3967                 case OP_FCLT:
3968                 case OP_FCLT_UN:
3969                 case OP_FCGT:
3970                 case OP_FCGT_UN:
3971                         sparc_fcmpd (code, ins->sreg1, ins->sreg2);
3972                         sparc_clr_reg (code, ins->dreg);
3973                         switch (ins->opcode) {
3974                         case OP_FCLT_UN:
3975                         case OP_FCGT_UN:
3976                                 sparc_fbranch (code, 1, opcode_to_sparc_cond (ins->opcode), 4);
3977                                 /* delay slot */
3978                                 sparc_set (code, 1, ins->dreg);
3979                                 sparc_fbranch (code, 1, sparc_fbu, 2);
3980                                 /* delay slot */
3981                                 sparc_set (code, 1, ins->dreg);
3982                                 break;
3983                         default:
3984                                 sparc_fbranch (code, 1, opcode_to_sparc_cond (ins->opcode), 2);
3985                                 /* delay slot */
3986                                 sparc_set (code, 1, ins->dreg);
3987                         }
3988                         break;
3989                 case OP_FBEQ:
3990                 case OP_FBLT:
3991                 case OP_FBGT:
3992                         EMIT_FLOAT_COND_BRANCH (ins, opcode_to_sparc_cond (ins->opcode), 1, 1);
3993                         break;
3994                 case OP_FBGE: {
3995                         /* clt.un + brfalse */
3996                         guint32 *p = code;
3997                         sparc_fbranch (code, 1, sparc_fbul, 0);
3998                         /* delay slot */
3999                         sparc_nop (code);
4000                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fba, 1, 1);
4001                         sparc_patch (p, (guint8*)code);
4002                         break;
4003                 }
4004                 case OP_FBLE: {
4005                         /* cgt.un + brfalse */
4006                         guint32 *p = code;
4007                         sparc_fbranch (code, 1, sparc_fbug, 0);
4008                         /* delay slot */
4009                         sparc_nop (code);
4010                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fba, 1, 1);
4011                         sparc_patch (p, (guint8*)code);
4012                         break;
4013                 }
4014                 case OP_FBNE_UN:
4015                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbne, 1, 1);
4016                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbu, 1, 1);
4017                         break;
4018                 case OP_FBLT_UN:
4019                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbl, 1, 1);
4020                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbu, 1, 1);
4021                         break;
4022                 case OP_FBGT_UN:
4023                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbg, 1, 1);
4024                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbu, 1, 1);
4025                         break;
4026                 case OP_FBGE_UN:
4027                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbge, 1, 1);
4028                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbu, 1, 1);
4029                         break;
4030                 case OP_FBLE_UN:
4031                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fble, 1, 1);
4032                         EMIT_FLOAT_COND_BRANCH (ins, sparc_fbu, 1, 1);
4033                         break;
4034                 case CEE_CKFINITE: {
4035                         gint32 offset = mono_spillvar_offset_float (cfg, 0);
4036                         if (!sparc_is_imm13 (offset))
4037                                 NOT_IMPLEMENTED;
4038                         sparc_stdf_imm (code, ins->sreg1, sparc_sp, offset);
4039                         sparc_lduh_imm (code, sparc_sp, offset, sparc_o7);
4040                         sparc_srl_imm (code, sparc_o7, 4, sparc_o7);
4041                         sparc_and_imm (code, FALSE, sparc_o7, 2047, sparc_o7);
4042                         sparc_cmp_imm (code, sparc_o7, 2047);
4043                         EMIT_COND_SYSTEM_EXCEPTION (ins, sparc_be, "ArithmeticException");
4044 #ifdef SPARCV9
4045                         sparc_fmovd (code, ins->sreg1, ins->dreg);
4046 #else
4047                         sparc_fmovs (code, ins->sreg1, ins->dreg);
4048                         sparc_fmovs (code, ins->sreg1 + 1, ins->dreg + 1);
4049 #endif
4050                         break;
4051                 }
4052                 default:
4053 #ifdef __GNUC__
4054                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4055 #else
4056                         g_warning ("%s:%d: unknown opcode %s\n", __FILE__, __LINE__, mono_inst_name (ins->opcode));
4057 #endif
4058                         g_assert_not_reached ();
4059                 }
4060
4061                 if ((((guint8*)code) - code_start) > max_len) {
4062                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4063                                    mono_inst_name (ins->opcode), max_len, ((guint8*)code) - code_start);
4064                         g_assert_not_reached ();
4065                 }
4066
4067                 cpos += max_len;
4068
4069                 last_ins = ins;
4070
4071                 ins = ins->next;
4072         }
4073
4074         cfg->code_len = (guint8*)code - cfg->native_code;
4075 }
4076
4077 void
4078 mono_arch_register_lowlevel_calls (void)
4079 {
4080         mono_register_jit_icall (mono_sparc_break, "mono_sparc_break", NULL, TRUE);
4081         mono_register_jit_icall (mono_arch_get_lmf_addr, "mono_arch_get_lmf_addr", NULL, TRUE);
4082 }
4083
4084 void
4085 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4086 {
4087         MonoJumpInfo *patch_info;
4088
4089         /* FIXME: Move part of this to arch independent code */
4090         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4091                 unsigned char *ip = patch_info->ip.i + code;
4092                 gpointer target;
4093
4094                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4095
4096                 switch (patch_info->type) {
4097                 case MONO_PATCH_INFO_CLASS_INIT: {
4098                         guint32 *ip2 = (guint32*)ip;
4099                         /* Might already been changed to a nop */
4100 #ifdef SPARCV9
4101                         sparc_set_template (ip2, sparc_o7);
4102                         sparc_jmpl (ip2, sparc_o7, sparc_g0, sparc_o7);
4103 #else
4104                         sparc_call_simple (ip2, 0);
4105 #endif
4106                         break;
4107                 }
4108                 case MONO_PATCH_INFO_METHOD_JUMP: {
4109                         guint32 *ip2 = (guint32*)ip;
4110                         /* Might already been patched */
4111                         sparc_set_template (ip2, sparc_o7);
4112                         break;
4113                 }
4114                 default:
4115                         break;
4116                 }
4117                 sparc_patch ((guint32*)ip, target);
4118         }
4119 }
4120
4121 void
4122 mono_arch_instrument_mem_needs (MonoMethod *method, int *stack, int *code)
4123 {
4124         *stack = 0;
4125         *code = 512;
4126 }
4127
4128 void*
4129 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4130 {
4131         int i, stack, code_size;
4132         guint32 *code = (guint32*)p;
4133         MonoMethodSignature *sig = cfg->method->signature;
4134         CallInfo *cinfo;
4135
4136         /* Save registers to stack */
4137         for (i = 0; i < 6; ++i)
4138                 sparc_sti_imm (code, sparc_i0 + i, sparc_fp, ARGS_OFFSET + (i * sizeof (gpointer)));
4139
4140         cinfo = get_call_info (sig, FALSE);
4141
4142         /* Save float regs on V9, since they are caller saved */
4143         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4144                 ArgInfo *ainfo = cinfo->args + i;
4145                 gint32 stack_offset;
4146
4147                 stack_offset = ainfo->offset + ARGS_OFFSET;
4148
4149                 if (ainfo->storage == ArgInFloatReg) {
4150                         if (!sparc_is_imm13 (stack_offset))
4151                                 NOT_IMPLEMENTED;
4152                         sparc_stf_imm (code, ainfo->reg, sparc_fp, stack_offset);
4153                 }
4154                 else if (ainfo->storage == ArgInDoubleReg) {
4155                         /* The offset is guaranteed to be aligned by the ABI rules */
4156                         sparc_stdf_imm (code, ainfo->reg, sparc_fp, stack_offset);
4157                 }
4158         }
4159
4160         sparc_set (code, cfg->method, sparc_o0);
4161         sparc_add_imm (code, FALSE, sparc_fp, MONO_SPARC_STACK_BIAS, sparc_o1);
4162
4163         mono_add_patch_info (cfg, (guint8*)code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
4164         EMIT_CALL ();
4165
4166         /* Restore float regs on V9 */
4167         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4168                 ArgInfo *ainfo = cinfo->args + i;
4169                 gint32 stack_offset;
4170
4171                 stack_offset = ainfo->offset + ARGS_OFFSET;
4172
4173                 if (ainfo->storage == ArgInFloatReg) {
4174                         if (!sparc_is_imm13 (stack_offset))
4175                                 NOT_IMPLEMENTED;
4176                         sparc_ldf_imm (code, sparc_fp, stack_offset, ainfo->reg);
4177                 }
4178                 else if (ainfo->storage == ArgInDoubleReg) {
4179                         /* The offset is guaranteed to be aligned by the ABI rules */
4180                         sparc_lddf_imm (code, sparc_fp, stack_offset, ainfo->reg);
4181                 }
4182         }
4183
4184         mono_arch_instrument_mem_needs (cfg->method, &stack, &code_size);
4185
4186         g_assert ((code - (guint32*)p) <= (code_size * 4));
4187
4188         g_free (cinfo);
4189
4190         return code;
4191 }
4192
4193 enum {
4194         SAVE_NONE,
4195         SAVE_STRUCT,
4196         SAVE_ONE,
4197         SAVE_TWO,
4198         SAVE_FP
4199 };
4200
4201 void*
4202 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4203 {
4204         guint32 *code = (guint32*)p;
4205         int save_mode = SAVE_NONE;
4206         MonoMethod *method = cfg->method;
4207         int rtype = method->signature->ret->type;
4208
4209 handle_enum:
4210         switch (rtype) {
4211         case MONO_TYPE_VOID:
4212                 /* special case string .ctor icall */
4213                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
4214                         save_mode = SAVE_ONE;
4215                 else
4216                         save_mode = SAVE_NONE;
4217                 break;
4218         case MONO_TYPE_I8:
4219         case MONO_TYPE_U8:
4220 #ifdef SPARCV9
4221                 save_mode = SAVE_ONE;
4222 #else
4223                 save_mode = SAVE_TWO;
4224 #endif
4225                 break;
4226         case MONO_TYPE_R4:
4227         case MONO_TYPE_R8:
4228                 save_mode = SAVE_FP;
4229                 break;
4230         case MONO_TYPE_VALUETYPE:
4231                 if (method->signature->ret->data.klass->enumtype) {
4232                         rtype = method->signature->ret->data.klass->enum_basetype->type;
4233                         goto handle_enum;
4234                 }
4235                 save_mode = SAVE_STRUCT;
4236                 break;
4237         default:
4238                 save_mode = SAVE_ONE;
4239                 break;
4240         }
4241
4242         /* Save the result to the stack and also put it into the output registers */
4243
4244         switch (save_mode) {
4245         case SAVE_TWO:
4246                 /* V8 only */
4247                 sparc_st_imm (code, sparc_i0, sparc_fp, 68);
4248                 sparc_st_imm (code, sparc_i0, sparc_fp, 72);
4249                 sparc_mov_reg_reg (code, sparc_i0, sparc_o1);
4250                 sparc_mov_reg_reg (code, sparc_i1, sparc_o2);
4251                 break;
4252         case SAVE_ONE:
4253                 sparc_sti_imm (code, sparc_i0, sparc_fp, ARGS_OFFSET);
4254                 sparc_mov_reg_reg (code, sparc_i0, sparc_o1);
4255                 break;
4256         case SAVE_FP:
4257 #ifdef SPARCV9
4258                 sparc_stdf_imm (code, sparc_f0, sparc_fp, ARGS_OFFSET);
4259 #else
4260                 sparc_stdf_imm (code, sparc_f0, sparc_fp, 72);
4261                 sparc_ld_imm (code, sparc_fp, 72, sparc_o1);
4262                 sparc_ld_imm (code, sparc_fp, 72 + 4, sparc_o2);
4263 #endif
4264                 break;
4265         case SAVE_STRUCT:
4266 #ifdef SPARCV9
4267                 sparc_mov_reg_reg (code, sparc_i0, sparc_o1);
4268 #else
4269                 sparc_ld_imm (code, sparc_fp, 64, sparc_o1);
4270 #endif
4271                 break;
4272         case SAVE_NONE:
4273         default:
4274                 break;
4275         }
4276
4277         sparc_set (code, cfg->method, sparc_o0);
4278
4279         mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_ABS, func);
4280         EMIT_CALL ();
4281
4282         /* Restore result */
4283
4284         switch (save_mode) {
4285         case SAVE_TWO:
4286                 sparc_ld_imm (code, sparc_fp, 68, sparc_i0);
4287                 sparc_ld_imm (code, sparc_fp, 72, sparc_i0);
4288                 break;
4289         case SAVE_ONE:
4290                 sparc_ldi_imm (code, sparc_fp, ARGS_OFFSET, sparc_i0);
4291                 break;
4292         case SAVE_FP:
4293                 sparc_lddf_imm (code, sparc_fp, ARGS_OFFSET, sparc_f0);
4294                 break;
4295         case SAVE_NONE:
4296         default:
4297                 break;
4298         }
4299
4300         return code;
4301 }
4302
4303 int
4304 mono_arch_max_epilog_size (MonoCompile *cfg)
4305 {
4306         int exc_count = 0, max_epilog_size = 16 + 20*4;
4307         MonoJumpInfo *patch_info;
4308
4309         if (cfg->method->save_lmf)
4310                 max_epilog_size += 128;
4311
4312         if (mono_jit_trace_calls != NULL)
4313                 max_epilog_size += 50;
4314
4315         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4316                 max_epilog_size += 50;
4317
4318         /* count the number of exception infos */
4319
4320         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4321                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4322                         exc_count++;
4323         }
4324
4325         /*
4326          * make sure we have enough space for exceptions
4327          */
4328 #ifdef SPARCV9
4329         max_epilog_size += exc_count * (20 * 4);
4330 #else
4331         max_epilog_size += exc_count * 24;
4332 #endif
4333
4334         return max_epilog_size;
4335 }
4336
4337 guint8 *
4338 mono_arch_emit_prolog (MonoCompile *cfg)
4339 {
4340         MonoMethod *method = cfg->method;
4341         MonoMethodSignature *sig;
4342         MonoInst *inst;
4343         guint32 *code;
4344         CallInfo *cinfo;
4345         guint32 i, offset;
4346
4347         cfg->code_size = 256;
4348         cfg->native_code = g_malloc (cfg->code_size);
4349         code = (guint32*)cfg->native_code;
4350
4351         /* FIXME: Generate intermediate code instead */
4352
4353         offset = cfg->stack_offset;
4354         offset += (16 * sizeof (gpointer)); /* register save area */
4355 #ifndef SPARCV9
4356         offset += 4; /* struct/union return pointer */
4357 #endif
4358
4359         /* add parameter area size for called functions */
4360         if (cfg->param_area < (6 * sizeof (gpointer)))
4361                 /* Reserve space for the first 6 arguments even if it is unused */
4362                 offset += 6 * sizeof (gpointer);
4363         else
4364                 offset += cfg->param_area;
4365
4366         /* align the stack size */
4367         offset = ALIGN_TO (offset, MONO_ARCH_FRAME_ALIGNMENT);
4368
4369         /*
4370          * localloc'd memory is stored between the local variables (whose
4371          * size is given by cfg->stack_offset), and between the space reserved
4372          * by the ABI.
4373          */
4374         cfg->arch.localloc_offset = offset - cfg->stack_offset;
4375
4376         cfg->stack_offset = offset;
4377
4378         if (!sparc_is_imm13 (- cfg->stack_offset)) {
4379                 /* Can't use sparc_o7 here, since we're still in the caller's frame */
4380                 sparc_set (code, (- cfg->stack_offset), GP_SCRATCH_REG);
4381                 sparc_save (code, sparc_sp, GP_SCRATCH_REG, sparc_sp);
4382         }
4383         else
4384                 sparc_save_imm (code, sparc_sp, - cfg->stack_offset, sparc_sp);
4385
4386 /*
4387         if (strstr (cfg->method->name, "test_marshal_struct")) {
4388                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_ABS, mono_sparc_break);
4389                 sparc_call_simple (code, 0);
4390                 sparc_nop (code);
4391         }
4392 */
4393
4394         sig = method->signature;
4395
4396         cinfo = get_call_info (sig, FALSE);
4397
4398         /* Keep in sync with emit_load_volatile_arguments */
4399         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4400                 ArgInfo *ainfo = cinfo->args + i;
4401                 gint32 stack_offset;
4402                 MonoType *arg_type;
4403                 inst = cfg->varinfo [i];
4404
4405                 if (sig->hasthis && (i == 0))
4406                         arg_type = &mono_defaults.object_class->byval_arg;
4407                 else
4408                         arg_type = sig->params [i - sig->hasthis];
4409
4410                 stack_offset = ainfo->offset + ARGS_OFFSET;
4411
4412                 /* Save the split arguments so they will reside entirely on the stack */
4413                 if (ainfo->storage == ArgInSplitRegStack) {
4414                         /* Save the register to the stack */
4415                         g_assert (inst->opcode == OP_REGOFFSET);
4416                         if (!sparc_is_imm13 (stack_offset))
4417                                 NOT_IMPLEMENTED;
4418                         sparc_st_imm (code, sparc_i5, inst->inst_basereg, stack_offset);
4419                 }
4420
4421                 if (!v64 && !arg_type->byref && (arg_type->type == MONO_TYPE_R8)) {
4422                         /* Save the argument to a dword aligned stack location */
4423                         /*
4424                          * stack_offset contains the offset of the argument on the stack.
4425                          * inst->inst_offset contains the dword aligned offset where the value
4426                          * should be stored.
4427                          */
4428                         if (ainfo->storage == ArgInIRegPair) {
4429                                 if (!sparc_is_imm13 (inst->inst_offset + 4))
4430                                         NOT_IMPLEMENTED;
4431                                 sparc_st_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, inst->inst_offset);
4432                                 sparc_st_imm (code, sparc_i0 + ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
4433                         }
4434                         else
4435                                 if (ainfo->storage == ArgInSplitRegStack) {
4436 #ifdef SPARCV9
4437                                         g_assert_not_reached ();
4438 #endif
4439                                         if (stack_offset != inst->inst_offset) {
4440                                                 /* stack_offset is not dword aligned, so we need to make a copy */
4441                                                 sparc_st_imm (code, sparc_i5, inst->inst_basereg, inst->inst_offset);
4442                                                 sparc_ld_imm (code, sparc_fp, stack_offset + 4, sparc_o7);
4443                                                 sparc_st_imm (code, sparc_o7, inst->inst_basereg, inst->inst_offset + 4);
4444                                         }
4445                                 }
4446                         else
4447                                 if (ainfo->storage == ArgOnStackPair) {
4448 #ifdef SPARCV9
4449                                         g_assert_not_reached ();
4450 #endif
4451                                         if (stack_offset != inst->inst_offset) {
4452                                                 /* stack_offset is not dword aligned, so we need to make a copy */
4453                                                 sparc_ld_imm (code, sparc_fp, stack_offset, sparc_o7);
4454                                                 sparc_st_imm (code, sparc_o7, inst->inst_basereg, inst->inst_offset);
4455                                                 sparc_ld_imm (code, sparc_fp, stack_offset + 4, sparc_o7);
4456                                                 sparc_st_imm (code, sparc_o7, inst->inst_basereg, inst->inst_offset + 4);
4457                                         }
4458                                 }
4459                         else
4460                                 g_assert_not_reached ();
4461                 }
4462                 else
4463                         if ((ainfo->storage == ArgInIReg) && (inst->opcode != OP_REGVAR)) {
4464                                 /* Argument in register, but need to be saved to stack */
4465                                 if (!sparc_is_imm13 (stack_offset))
4466                                         NOT_IMPLEMENTED;
4467                                 if ((stack_offset - ARGS_OFFSET) & 0x1)
4468                                         sparc_stb_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, stack_offset);
4469                                 else
4470                                         if ((stack_offset - ARGS_OFFSET) & 0x2)
4471                                                 sparc_sth_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, stack_offset);
4472                                 else
4473                                         if ((stack_offset - ARGS_OFFSET) & 0x4)
4474                                                 sparc_st_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, stack_offset);
4475                                         else {
4476                                                 if (v64)
4477                                                         sparc_stx_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, stack_offset);
4478                                                 else
4479                                                         sparc_st_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, stack_offset);
4480                                         }
4481                         }
4482                 else
4483                         if ((ainfo->storage == ArgInIRegPair) && (inst->opcode != OP_REGVAR)) {
4484 #ifdef SPARCV9
4485                                 NOT_IMPLEMENTED;
4486 #endif
4487                                 /* Argument in regpair, but need to be saved to stack */
4488                                 if (!sparc_is_imm13 (inst->inst_offset + 4))
4489                                         NOT_IMPLEMENTED;
4490                                 sparc_st_imm (code, sparc_i0 + ainfo->reg, inst->inst_basereg, inst->inst_offset);
4491                                 sparc_st_imm (code, sparc_i0 + ainfo->reg + 1, inst->inst_basereg, inst->inst_offset + 4);
4492                         }
4493                 else if ((ainfo->storage == ArgInFloatReg) && (inst->opcode != OP_REGVAR)) {
4494                                 if (!sparc_is_imm13 (stack_offset))
4495                                         NOT_IMPLEMENTED;
4496                                 sparc_stf_imm (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4497                                 }
4498                         else if ((ainfo->storage == ArgInDoubleReg) && (inst->opcode != OP_REGVAR)) {
4499                                 /* The offset is guaranteed to be aligned by the ABI rules */
4500                                 sparc_stdf_imm (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
4501                         }
4502
4503                 if ((ainfo->storage == ArgInFloatReg) && (inst->opcode == OP_REGVAR)) {
4504                         /* Need to move into the a double precision register */
4505                         sparc_fstod (code, ainfo->reg, ainfo->reg - 1);
4506                 }
4507
4508                 if ((ainfo->storage == ArgInSplitRegStack) || (ainfo->storage == ArgOnStack))
4509                         if (inst->opcode == OP_REGVAR)
4510                                 /* FIXME: Load the argument into memory */
4511                                 NOT_IMPLEMENTED;
4512         }
4513
4514         g_free (cinfo);
4515
4516         if (cfg->method->save_lmf) {
4517                 gint32 lmf_offset = STACK_BIAS - cfg->arch.lmf_offset;
4518
4519                 /* Save ip */
4520                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
4521                 sparc_set_template (code, sparc_o7);
4522                 sparc_sti_imm (code, sparc_o7, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ip));
4523                 /* Save sp */
4524                 sparc_sti_imm (code, sparc_sp, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, sp));
4525                 /* Save fp */
4526                 sparc_sti_imm (code, sparc_fp, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp));
4527                 /* Save method */
4528                 /* FIXME: add a relocation for this */
4529                 sparc_set (code, cfg->method, sparc_o7);
4530                 sparc_sti_imm (code, sparc_o7, sparc_fp, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method));
4531
4532                 mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
4533                                                          (gpointer)"mono_arch_get_lmf_addr");
4534                 EMIT_CALL ();
4535
4536                 code = (guint32*)mono_sparc_emit_save_lmf (code, lmf_offset);
4537         }
4538
4539         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4540                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4541
4542         cfg->code_len = (guint8*)code - cfg->native_code;
4543
4544         g_assert (cfg->code_len <= cfg->code_size);
4545
4546         return (guint8*)code;
4547 }
4548
4549 void
4550 mono_arch_emit_epilog (MonoCompile *cfg)
4551 {
4552         MonoJumpInfo *patch_info;
4553         MonoMethod *method = cfg->method;
4554         guint32 *code;
4555         int can_fold = 0;
4556
4557         code = (guint32*)(cfg->native_code + cfg->code_len);
4558
4559         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4560                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4561
4562         if (cfg->method->save_lmf) {
4563                 gint32 lmf_offset = STACK_BIAS - cfg->arch.lmf_offset;
4564
4565                 code = mono_sparc_emit_restore_lmf (code, lmf_offset);
4566         }
4567
4568         /*
4569          * The V8 ABI requires that calls to functions which return a structure
4570          * return to %i7+12
4571          */
4572         if (!v64 && cfg->method->signature->pinvoke && MONO_TYPE_ISSTRUCT(cfg->method->signature->ret))
4573                 sparc_jmpl_imm (code, sparc_i7, 12, sparc_g0);
4574         else
4575                 sparc_ret (code);
4576
4577         /* Only fold last instruction into the restore if the exit block has an in count of 1
4578            and the previous block hasn't been optimized away since it may have an in count > 1 */
4579         if (cfg->bb_exit->in_count == 1 && cfg->bb_exit->in_bb[0]->native_offset != cfg->bb_exit->native_offset)
4580                 can_fold = 1;
4581
4582         /* Try folding last instruction into the restore */
4583         if (can_fold && (sparc_inst_op (code [-2]) == 0x2) && (sparc_inst_op3 (code [-2]) == 0x2) && sparc_inst_imm (code [-2]) && (sparc_inst_rd (code [-2]) == sparc_i0)) {
4584                 /* or reg, imm, %i0 */
4585                 int reg = sparc_inst_rs1 (code [-2]);
4586                 int imm = sparc_inst_imm13 (code [-2]);
4587                 code [-2] = code [-1];
4588                 code --;
4589                 sparc_restore_imm (code, reg, imm, sparc_o0);
4590         }
4591         else
4592         if (can_fold && (sparc_inst_op (code [-2]) == 0x2) && (sparc_inst_op3 (code [-2]) == 0x2) && (!sparc_inst_imm (code [-2])) && (sparc_inst_rd (code [-2]) == sparc_i0)) {
4593                 /* or reg, reg, %i0 */
4594                 int reg1 = sparc_inst_rs1 (code [-2]);
4595                 int reg2 = sparc_inst_rs2 (code [-2]);
4596                 code [-2] = code [-1];
4597                 code --;
4598                 sparc_restore (code, reg1, reg2, sparc_o0);
4599         }
4600         else
4601                 sparc_restore_imm (code, sparc_g0, 0, sparc_g0);
4602
4603         /* add code to raise exceptions */
4604         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4605                 glong offset = patch_info->ip.i;
4606
4607                 switch (patch_info->type) {
4608                 case MONO_PATCH_INFO_EXC:
4609                         sparc_patch ((guint32*)(cfg->native_code + patch_info->ip.i), code);
4610                         mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_EXC_NAME, patch_info->data.target);
4611                         sparc_set_template (code, sparc_o0);
4612                         mono_add_patch_info (cfg, (guint8*)code - cfg->native_code, MONO_PATCH_INFO_METHOD_REL, (gpointer)offset);
4613                         sparc_set_template (code, sparc_o1);
4614                         patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4615                         patch_info->data.name = "mono_arch_throw_exception_by_name";
4616                         patch_info->ip.i = (guint8*)code - cfg->native_code;
4617                         EMIT_CALL ();
4618                         break;
4619                 default:
4620                         /* do nothing */
4621                         break;
4622                 }
4623         }
4624
4625         cfg->code_len = (guint8*)code - cfg->native_code;
4626
4627         g_assert (cfg->code_len < cfg->code_size);
4628
4629 }
4630
4631 gboolean lmf_addr_key_inited = FALSE;
4632
4633 #ifdef MONO_SPARC_THR_TLS
4634 thread_key_t lmf_addr_key;
4635 #else
4636 pthread_key_t lmf_addr_key;
4637 #endif
4638
4639 gpointer
4640 mono_arch_get_lmf_addr (void)
4641 {
4642         /* This is perf critical so we bypass the IO layer */
4643         /* The thr_... functions seem to be somewhat faster */
4644 #ifdef MONO_SPARC_THR_TLS
4645         gpointer res;
4646         thr_getspecific (lmf_addr_key, &res);
4647         return res;
4648 #else
4649         return pthread_getspecific (lmf_addr_key);
4650 #endif
4651 }
4652
4653 void
4654 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
4655 {
4656 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
4657 #ifdef __linux__
4658         struct sigaltstack sa;
4659 #else
4660         stack_t         sigstk;
4661 #endif
4662
4663         printf ("SIGALT!\n");
4664         /* Setup an alternate signal stack */
4665         tls->signal_stack = g_malloc (SIGNAL_STACK_SIZE);
4666         tls->signal_stack_size = SIGNAL_STACK_SIZE;
4667
4668 #ifdef __linux__
4669         sa.ss_sp = tls->signal_stack;
4670         sa.ss_size = SIGNAL_STACK_SIZE;
4671         sa.ss_flags = 0;
4672         g_assert (sigaltstack (&sa, NULL) == 0);
4673 #else
4674         sigstk.ss_sp = tls->signal_stack;
4675         sigstk.ss_size = SIGNAL_STACK_SIZE;
4676         sigstk.ss_flags = 0;
4677         g_assert (sigaltstack (&sigstk, NULL) == 0);
4678 #endif
4679 #endif
4680
4681         if (!lmf_addr_key_inited) {
4682                 int res;
4683
4684                 lmf_addr_key_inited = TRUE;
4685
4686 #ifdef MONO_SPARC_THR_TLS
4687                 res = thr_keycreate (&lmf_addr_key, NULL);
4688 #else
4689                 res = pthread_key_create (&lmf_addr_key, NULL);
4690 #endif
4691                 g_assert (res == 0);
4692
4693         }
4694
4695 #ifdef MONO_SPARC_THR_TLS
4696         thr_setspecific (lmf_addr_key, &tls->lmf);
4697 #else
4698         pthread_setspecific (lmf_addr_key, &tls->lmf);
4699 #endif
4700 }
4701
4702 void
4703 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4704 {
4705 }
4706
4707 void
4708 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
4709 {
4710         int this_out_reg = sparc_o0;
4711
4712         if (vt_reg != -1) {
4713 #ifdef SPARCV9
4714                 MonoInst *ins;
4715                 MONO_INST_NEW (cfg, ins, OP_SETREG);
4716                 ins->sreg1 = vt_reg;
4717                 ins->dreg = sparc_o0;
4718                 mono_bblock_add_inst (cfg->cbb, ins);
4719                 this_out_reg = sparc_o1;
4720 #else
4721                 /* Set the 'struct/union return pointer' location on the stack */
4722                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI4_MEMBASE_REG, sparc_sp, 64, vt_reg);
4723 #endif
4724         }
4725
4726         /* add the this argument */
4727         if (this_reg != -1) {
4728                 MonoInst *this;
4729                 MONO_INST_NEW (cfg, this, OP_SETREG);
4730                 this->type = this_type;
4731                 this->sreg1 = this_reg;
4732                 this->dreg = this_out_reg;
4733                 mono_bblock_add_inst (cfg->cbb, this);
4734         }
4735 }
4736
4737
4738 gint
4739 mono_arch_get_opcode_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4740 {
4741         return -1;
4742 }
4743
4744 /*
4745  * mono_arch_get_argument_info:
4746  * @csig:  a method signature
4747  * @param_count: the number of parameters to consider
4748  * @arg_info: an array to store the result infos
4749  *
4750  * Gathers information on parameters such as size, alignment and
4751  * padding. arg_info should be large enought to hold param_count + 1 entries.
4752  *
4753  * Returns the size of the activation frame.
4754  */
4755 int
4756 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
4757 {
4758         int k, align;
4759         CallInfo *cinfo;
4760         ArgInfo *ainfo;
4761
4762         cinfo = get_call_info (csig, FALSE);
4763
4764         if (csig->hasthis) {
4765                 ainfo = &cinfo->args [0];
4766                 arg_info [0].offset = ARGS_OFFSET - MONO_SPARC_STACK_BIAS + ainfo->offset;
4767         }
4768
4769         for (k = 0; k < param_count; k++) {
4770                 ainfo = &cinfo->args [k + csig->hasthis];
4771
4772                 arg_info [k + 1].offset = ARGS_OFFSET - MONO_SPARC_STACK_BIAS + ainfo->offset;
4773                 arg_info [k + 1].size = mono_type_size (csig->params [k], &align);
4774         }
4775
4776         g_free (cinfo);
4777
4778         return 0;
4779 }
4780
4781 gboolean
4782 mono_arch_print_tree (MonoInst *tree, int arity)
4783 {
4784         return 0;
4785 }
4786
4787 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
4788 {
4789         return NULL;
4790 }
4791
4792 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
4793 {
4794         return NULL;
4795 }