1 #ifndef __MONO_MINI_MIPS_H__
2 #define __MONO_MINI_MIPS_H__
4 #include <mono/arch/mips/mips-codegen.h>
7 #define MONO_ARCH_CPU_SPEC mips_desc
9 #define MONO_MAX_IREGS 32
10 #define MONO_MAX_FREGS 32
12 #define MONO_SAVED_GREGS 32
13 #define MONO_SAVED_FREGS 32
16 * at and t0 used internally
17 * v0, v1 aren't here for clarity reasons
18 * a0, a1, a2, a3 are for arguments
19 * Use t9 for indirect calls to match the ABI
22 #define MIPS_V_REGS ((1 << mips_v0) | \
24 #define MIPS_T_REGS ((1 << mips_t0) | \
32 #define MIPS_S_REGS ((1 << mips_s0) | \
41 #define MIPS_A_REGS ((1 << mips_a0) | \
46 #define mips_temp mips_t8
48 #define MONO_ARCH_CALLEE_REGS (MIPS_T_REGS | MIPS_V_REGS)
49 #define MONO_ARCH_CALLEE_SAVED_REGS MIPS_S_REGS
50 #define MIPS_ARG_REGS MIPS_A_REGS
53 #define MIPS_FP_PAIR(reg) ((1 << (reg)) | (1 << ((reg)+1)))
55 /* Only put the even regs in */
56 #define MIPS_FP_PAIR(reg) (1 << (reg))
59 #define MONO_ARCH_CALLEE_FREGS (MIPS_FP_PAIR(mips_f0) | \
60 MIPS_FP_PAIR(mips_f2) | \
61 MIPS_FP_PAIR(mips_f4) | \
62 MIPS_FP_PAIR(mips_f6) | \
63 MIPS_FP_PAIR(mips_f8) | \
64 MIPS_FP_PAIR(mips_f10) | \
65 MIPS_FP_PAIR(mips_f12) | \
66 MIPS_FP_PAIR(mips_f14) | \
67 MIPS_FP_PAIR(mips_f16) | \
68 MIPS_FP_PAIR(mips_f18))
70 #define MONO_ARCH_CALLEE_SAVED_FREGS (MIPS_FP_PAIR(mips_f20) | \
71 MIPS_FP_PAIR(mips_f22) | \
72 MIPS_FP_PAIR(mips_f24) | \
73 MIPS_FP_PAIR(mips_f26) | \
74 MIPS_FP_PAIR(mips_f28) | \
75 MIPS_FP_PAIR(mips_f30))
77 #define mips_ftemp mips_f18
79 #define MONO_ARCH_USE_FPSTACK FALSE
80 #define MONO_ARCH_FPSTACK_SIZE 0
82 /* Parameters used by the register allocator */
84 /* On Mips, for regpairs, the lower-numbered reg is most significant
85 * This is true in both big and little endian
88 #if G_BYTE_ORDER == G_LITTLE_ENDIAN
89 #define RET_REG1 mips_v0
90 #define RET_REG2 mips_v1
92 #define RET_REG1 mips_v1
93 #define RET_REG2 mips_v0
96 #define MONO_ARCH_INST_SREG2_MASK(ins) (0)
97 #define MONO_ARCH_INST_IS_REGPAIR(desc) ((desc) == 'V' || (desc) == 'l')
98 #define MONO_ARCH_INST_REGPAIR_REG2(desc,hreg1) (((desc) == 'l') ? ((hreg1) + 1) : (((desc) == 'V') ? RET_REG2 : -1))
99 #define MONO_ARCH_INST_IS_FLOAT(desc) ((desc == 'f') || (desc == 'g'))
101 // This define is called to get specific dest register as defined
102 // by md file (letter after "dest"). Overwise return -1
104 #define MONO_ARCH_INST_FIXED_REG(desc) (((desc) == '0') ? mips_zero : (((desc) == 'a') ? mips_at : ((((desc) == 'v')) ? mips_v0 : (((desc) == 'V') ? RET_REG1 : (((desc) == 'g') ? mips_f0 : -1)))))
106 #define MONO_ARCH_FRAME_ALIGNMENT 8
108 /* fixme: align to 16byte instead of 32byte (we align to 32byte to get
109 * reproduceable results for benchmarks */
110 #define MONO_ARCH_CODE_ALIGNMENT 32
112 void mips_patch (guint32 *code, guint32 target);
114 #define MIPS_LMF_MAGIC1 0xa5a5a5a5
115 #define MIPS_LMF_MAGIC2 0xc3c3c3c3
118 gpointer previous_lmf;
123 gulong iregs [MONO_SAVED_GREGS];
124 gfloat fregs [MONO_SAVED_FREGS];
128 /* we define our own structure and we'll copy the data
129 * from sigcontext/ucontext/mach when we need it.
130 * This also makes us save stack space and time when copying
131 * We might also want to add an additional field to propagate
132 * the original context from the signal handler.
136 gulong sc_regs [MONO_SAVED_GREGS];
137 gfloat sc_fpregs [MONO_SAVED_FREGS];
140 typedef struct MonoCompileArch {
143 guint spillvar_offset;
144 guint spillvar_offset_float;
147 #define MONO_ARCH_EMULATE_FCONV_TO_I8 1
148 #define MONO_ARCH_EMULATE_LCONV_TO_R8 1
149 #define MONO_ARCH_EMULATE_LCONV_TO_R4 1
150 #define MONO_ARCH_EMULATE_LCONV_TO_R8_UN 1
151 #define MONO_ARCH_EMULATE_FREM 1
152 #define MONO_ARCH_BIGMUL_INTRINS 1
154 #define MIPS_RET_ADDR_OFFSET (-4)
155 #define MIPS_FP_ADDR_OFFSET (-8)
156 #define MIPS_STACK_ALIGNMENT 16
157 #define MIPS_STACK_PARAM_OFFSET 16 /* from sp to first parameter */
158 #define MIPS_MINIMAL_STACK_SIZE (4*4 + 4*4)
159 #define MIPS_EXTRA_STACK_SIZE 16 /* from last parameter to top of frame */
160 #define MIPS_FIRST_ARG_REG mips_a0
161 #define MIPS_LAST_ARG_REG mips_a3
162 #define MIPS_FIRST_FPARG_REG mips_f12
163 #define MIPS_LAST_FPARG_REG mips_f14
167 /* XXX - a mystery, but it works */
168 #define MONO_GET_CONTEXT \
169 void *ctx = (void *)(((int)context)+24);
171 /* set the next to 0 once inssel-mips.brg is updated */
172 #define MIPS_PASS_STRUCTS_BY_VALUE 1
173 #define MIPS_SMALL_RET_STRUCT_IN_REG 0
175 #define MONO_ARCH_USE_SIGACTION
176 #define MONO_ARCH_NEED_DIV_CHECK 1
178 #define MIPS_NUM_REG_ARGS (MIPS_LAST_ARG_REG-MIPS_FIRST_ARG_REG+1)
179 #define MIPS_NUM_REG_FPARGS (MIPS_LAST_FPARG_REG-MIPS_FIRST_FPARG_REG+1)
181 /* we have the stack pointer, not the base pointer in sigcontext */
182 #define MONO_CONTEXT_SET_IP(ctx,ip) do { (ctx)->sc_pc = (int)(ip); } while (0);
183 #define MONO_CONTEXT_SET_BP(ctx,bp) do { (ctx)->sc_regs[mips_fp] = (int)(bp); } while (0);
184 #define MONO_CONTEXT_SET_SP(ctx,sp) do { (ctx)->sc_regs[mips_sp] = (int)(sp); } while (0);
186 #define MONO_CONTEXT_GET_IP(ctx) ((gpointer)((ctx)->sc_pc))
187 #define MONO_CONTEXT_GET_BP(ctx) ((gpointer)((ctx)->sc_regs[mips_fp]))
188 #define MONO_CONTEXT_GET_SP(ctx) ((gpointer)((ctx)->sc_regs[mips_sp]))
192 unsigned long at; /* assembler temp */
193 unsigned long v0; /* return values */
195 unsigned long a0; /* 4 - func arguments */
199 unsigned long t0; /* 8 temporaries */
207 unsigned long s0; /* 16 calle saved */
215 unsigned long t8; /* 24 temps */
216 unsigned long t9; /* 25 temp / pic call-through register */
217 unsigned long k0; /* 26 kernel-reserved */
219 unsigned long gp; /* 28 */
220 unsigned long sp; /* stack pointer */
221 unsigned long fp; /* frame pointer */
222 unsigned long ra; /* return address */
223 } MonoMipsStackFrame;
225 #define MONO_INIT_CONTEXT_FROM_FUNC(ctx,func) do { \
227 guint32 *code = (guint32 *)(void *)func; \
229 memset ((ctx), 0, sizeof (*(ctx))); \
230 __asm__ volatile("addu %0,$0,$29" : "=r" (sp)); \
231 /* Look for adjustment of sp */ \
232 while ((*code & 0xffff0000) != 0x27bd0000) \
234 imm = (short) (*code & 0xffff); \
235 MONO_CONTEXT_SET_BP ((ctx), sp + (-imm)); \
236 ra = *(guint32 *)(sp + (-imm) + MIPS_RET_ADDR_OFFSET); \
237 MONO_CONTEXT_SET_IP ((ctx),ra); \
238 MONO_CONTEXT_SET_SP ((ctx), MONO_CONTEXT_GET_BP (ctx)); \
241 /* re-attaches with gdb - sometimes causes executable to hang */
242 #undef HAVE_BACKTRACE_SYMBOLS
244 #undef DEBUG_EXCEPTIONS
246 #define MONO_ZERO_REG mips_zero
248 #define MONO_EMIT_NEW_BRANCH_UNREG_LABEL(cfg,op,sr1,label) do { \
250 inst = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
253 inst->inst_i0 = label; \
254 inst->flags = MONO_INST_BRLABEL; \
255 mono_bblock_add_inst ((cfg)->cbb, inst); \
258 #define MONO_EMIT_NEW_BRANCH_BIREG_LABEL(cfg,op,sr1,sr2,label) do { \
260 inst = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
264 inst->inst_i0 = label; \
265 inst->flags = MONO_INST_BRLABEL; \
266 mono_bblock_add_inst ((cfg)->cbb, inst); \
269 #define MONO_EMIT_NEW_BRANCH_NONZERO_LABEL(cfg,op,sr1,targetbb) do { \
271 MonoInst *target_label; \
272 target_label = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
273 target_label->opcode = OP_LABEL; \
274 target_label->next = (targetbb)->code; \
275 target_label->inst_c0 = (targetbb)->native_offset; \
276 (targetbb)->code = target_label; \
277 inst = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
279 (inst)->sreg1 = sr1; \
280 (inst)->sreg2 = sr2; \
281 inst->inst_i0 = target_label; \
282 inst->flags = MONO_INST_BRLABEL; \
283 mono_bblock_add_inst ((cfg)->cbb, inst); \
286 #define MONO_EMIT_NEW_COMPARE_BRANCH_BLOCK(cfg,op,sr1,sr2,targetbb) do { \
288 MonoInst *target_label; \
289 target_label = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
290 target_label->opcode = OP_LABEL; \
291 target_label->next = (targetbb)->code; \
292 target_label->inst_c0 = (targetbb)->native_offset; \
293 (targetbb)->code = target_label; \
294 inst = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
296 (inst)->sreg1 = sr1; \
297 (inst)->sreg2 = sr2; \
298 inst->inst_i0 = target_label; \
299 inst->flags = MONO_INST_BRLABEL; \
300 mono_bblock_add_inst ((cfg)->cbb, inst); \
303 #ifndef MONO_EMIT_NEW_COMPARE_BRANCH_LABEL
304 #define MONO_EMIT_NEW_COMPARE_BRANCH_LABEL(cfg, cmp_op, sreg1, sreg2, label) \
308 MONO_EMIT_NEW_BRANCH_BIREG_LABEL(cfg, OP_MIPS_BEQ, sreg1, sreg2, label); \
311 MONO_EMIT_NEW_BRANCH_BIREG_LABEL(cfg, OP_MIPS_BNE, sreg1, sreg2, label); \
314 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLT, mips_at, sreg1, sreg2); \
315 MONO_EMIT_NEW_BIALU_IMM (s, OP_MIPS_XORI, mips_at, mips_at, 1); \
316 MONO_EMIT_NEW_BRANCH_BIREG_LABEL(cfg, OP_MIPS_BNE, mips_at, mips_zero, label); \
319 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLTU, mips_at, sreg1, sreg2); \
320 MONO_EMIT_NEW_BIALU_IMM (s, OP_MIPS_XORI, mips_at, mips_at, 1); \
321 MONO_EMIT_NEW_BRANCH_BIREG_LABEL(cfg, OP_MIPS_BNE, mips_at, mips_zero, label); \
324 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLT, mips_at, sreg2, sreg1); \
325 MONO_EMIT_NEW_BRANCH_BIREG_LABEL(cfg, OP_MIPS_BNE, mips_at, mips_zero, label); \
328 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLTU, mips_at, sreg2, sreg1); \
329 MONO_EMIT_NEW_BRANCH_BIREG_LABEL(cfg, OP_MIPS_BNE, mips_at, mips_zero, label); \
332 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLT, mips_at, sreg1, sreg2); \
333 MONO_EMIT_NEW_BRANCH_BIREG_LABEL(cfg, OP_MIPS_BNE, mips_at, mips_zero, label); \
336 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLTU, mips_at, sreg1, sreg2); \
337 MONO_EMIT_NEW_BRANCH_BIREG_LABEL(cfg, OP_MIPS_BNE, mips_at, mips_zero, label); \
340 g_assert_not_reached(); \
345 #ifndef MONO_EMIT_NEW_COMPARE_IMM_BRANCH_LABEL
346 #define MONO_EMIT_NEW_COMPARE_IMM_BRANCH_LABEL(cfg, cmp_op, sreg1, imm, label) \
350 cmp_reg = mips_zero; \
354 MONO_EMIT_NEW_ICONST (cfg, cmp_reg, (imm)); \
356 MONO_EMIT_NEW_COMPARE_BRANCH_LABEL(cfg, cmp_op, sreg1, cmp_reg, label); \
360 #ifndef MONO_EMIT_NEW_COMPARE_BRANCH_BLOCK
361 #define MONO_EMIT_NEW_COMPARE_BRANCH_BLOCK(cfg, cmp_op, sreg1, sreg2, block) \
365 MONO_EMIT_NEW_BRANCH_BIREG_BLOCK (cfg, OP_MIPS_BEQ, sreg1, sreg2, block); \
368 MONO_EMIT_NEW_BRANCH_BIREG_BLOCK (cfg, OP_MIPS_BNE, sreg1, sreg2, block); \
371 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLTU, mips_at, sreg1, sreg2); \
372 MONO_EMIT_NEW_BRANCH_BIREG_BLOCK (cfg, OP_MIPS_BNE, mips_at, mips_zero, block); \
375 g_assert_not_reached (); \
380 #ifndef MONO_EMIT_NEW_COMPARE_IMM_BRANCH_BLOCK
381 #define MONO_EMIT_NEW_COMPARE_IMM_BRANCH_BLOCK(cfg, cmp_op, sreg1, imm, block) \
385 cmp_reg = mips_zero; \
389 MONO_EMIT_NEW_ICONST (cfg, cmp_reg, (imm)); \
391 MONO_EMIT_NEW_COMPARE_BRANCH_BLOCK(cfg, cmp_op, sreg1, cmp_reg, block); \
395 #define MONO_EMIT_NEW_MIPS_COND_EXC(cfg,cond,sr1,sr2,name) do { \
397 inst = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
398 inst->opcode = cond; \
399 inst->inst_p1 = (char*)name; \
402 mono_bblock_add_inst ((cfg)->cbb, inst); \
405 #ifndef MONO_EMIT_NEW_COMPARE_EXC
406 #define MONO_EMIT_NEW_COMPARE_EXC(cfg, cmp_op, sreg1, sreg2, exc) do { \
407 switch (OP_MIPS_COND_EXC_##cmp_op) { \
408 case OP_MIPS_COND_EXC_EQ: \
409 MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_EQ, sreg1, sreg2, exc); \
411 case OP_MIPS_COND_EXC_NE_UN: \
412 MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_NE_UN, sreg1, sreg2, exc); \
414 case OP_MIPS_COND_EXC_GT: \
415 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLT, mips_at, sreg2, sreg1); \
416 MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_NE_UN, mips_at, mips_zero, exc); \
418 case OP_MIPS_COND_EXC_GT_UN: \
419 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLTU, mips_at, sreg2, sreg1); \
420 MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_NE_UN, mips_at, mips_zero, exc); \
422 case OP_MIPS_COND_EXC_LE: \
423 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLT, mips_at, sreg2, sreg1); \
424 MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_EQ, mips_at, mips_zero, exc); \
426 case OP_MIPS_COND_EXC_LE_UN: \
427 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLTU, mips_at, sreg2, sreg1); \
428 MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_EQ, mips_at, mips_zero, exc); \
430 case OP_MIPS_COND_EXC_LT: \
431 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLT, mips_at, sreg1, sreg2); \
432 MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_NE_UN, mips_at, mips_zero, exc); \
434 case OP_MIPS_COND_EXC_LT_UN: \
435 MONO_EMIT_NEW_BIALU (cfg, OP_MIPS_SLTU, mips_at, sreg1, sreg2); \
436 MONO_EMIT_NEW_MIPS_COND_EXC (cfg, OP_MIPS_COND_EXC_NE_UN, mips_at, mips_zero, exc); \
439 g_warning ("unknown comparison %s\n", #cmp_op); \
440 g_assert_not_reached (); \
445 #ifndef MONO_EMIT_NEW_COMPARE_IMM_EXC
446 #define MONO_EMIT_NEW_COMPARE_IMM_EXC(cfg, cmp_op, sreg1, imm, exc) do { \
449 cmp_reg = mips_zero; \
453 MONO_EMIT_NEW_ICONST (cfg, cmp_reg, (imm)); \
455 MONO_EMIT_NEW_COMPARE_EXC (cfg, cmp_op, sreg1, cmp_reg, exc); \
459 #ifndef MONO_EMIT_NEW_ICOMPARE_IMM_EXC
460 #define MONO_EMIT_NEW_ICOMPARE_IMM_EXC(cfg, cmp_op, sreg1, imm, exc) do { \
461 MONO_EMIT_NEW_COMPARE_IMM_EXC(cfg, cmp_op, sreg1, imm, exc); \
472 #endif /* __MONO_MINI_MIPS_H__ */