mono/mini/mini-ia64.c

   1 /*
   2  * mini-ia64.c: IA64 backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Zoltan Varga (vargaz@gmail.com)
   6  *
   7  * (C) 2003 Ximian, Inc.
   8  */
   9 #include "mini.h"
  10 #include <string.h>
  11 #include <math.h>
  12 #include <unistd.h>
  13 #include <sys/mman.h>
  14
  15 #ifdef __INTEL_COMPILER
  16 #include <ia64intrin.h>
  17 #endif
  18
  19 #include <mono/metadata/appdomain.h>
  20 #include <mono/metadata/debug-helpers.h>
  21 #include <mono/metadata/threads.h>
  22 #include <mono/metadata/profiler-private.h>
  23 #include <mono/utils/mono-math.h>
  24
  25 #include "trace.h"
  26 #include "mini-ia64.h"
  27 #include "cpu-ia64.h"
  28 #include "jit-icalls.h"
  29 #include "ir-emit.h"
  30
  31 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  32
  33 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  34
  35 /*
  36  * IA64 register usage:
  37  * - local registers are used for global register allocation
  38  * - r8..r11, r14..r30 is used for local register allocation
  39  * - r31 is a scratch register used within opcode implementations
  40  * - FIXME: Use out registers as well
  41  * - the first three locals are used for saving ar.pfst, b0, and sp
  42  * - compare instructions allways set p6 and p7
  43  */
  44
  45 /*
  46  * There are a lot of places where generated code is disassembled/patched.
  47  * The automatic bundling of instructions done by the code generation macros
  48  * could complicate things, so it is best to call
  49  * ia64_codegen_set_one_ins_per_bundle () at those places.
  50  */
  51
  52 #define ARGS_OFFSET 16
  53
  54 #define GP_SCRATCH_REG 31
  55 #define GP_SCRATCH_REG2 30
  56 #define FP_SCRATCH_REG 32
  57 #define FP_SCRATCH_REG2 33
  58
  59 #define LOOP_ALIGNMENT 8
  60 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
  61
  62 static const char* gregs [] = {
  63         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
  64         "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
  65         "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29",
  66         "r30", "r31", "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  67         "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", "r48", "r49",
  68         "r50", "r51", "r52", "r53", "r54", "r55", "r56", "r57", "r58", "r59",
  69         "r60", "r61", "r62", "r63", "r64", "r65", "r66", "r67", "r68", "r69",
  70         "r70", "r71", "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
  71         "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", "r88", "r89",
  72         "r90", "r91", "r92", "r93", "r94", "r95", "r96", "r97", "r98", "r99",
  73         "r100", "r101", "r102", "r103", "r104", "r105", "r106", "r107", "r108", "r109",
  74         "r110", "r111", "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
  75         "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127"
  76 };
  77
  78 const char*
  79 mono_arch_regname (int reg)
  80 {
  81         if (reg < 128)
  82                 return gregs [reg];
  83         else
  84                 return "unknown";
  85 }
  86
  87 static const char* fregs [] = {
  88         "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
  89         "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
  90         "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
  91         "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
  92         "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
  93         "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
  94         "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69",
  95         "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
  96         "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89",
  97         "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99",
  98         "f100", "f101", "f102", "f103", "f104", "f105", "f106", "f107", "f108", "f109",
  99         "f110", "f111", "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
 100         "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127"
 101 };
 102
 103 const char*
 104 mono_arch_fregname (int reg)
 105 {
 106         if (reg < 128)
 107                 return fregs [reg];
 108         else
 109                 return "unknown";
 110 }
 111
 112 static gboolean
 113 debug_ins_sched (void)
 114 {
 115 #if 0
 116         return mono_debug_count ();
 117 #else
 118         return TRUE;
 119 #endif
 120 }
 121
 122 static gboolean
 123 debug_omit_fp (void)
 124 {
 125 #if 0
 126         return mono_debug_count ();
 127 #else
 128         return TRUE;
 129 #endif
 130 }
 131
 132 static void
 133 ia64_patch (unsigned char* code, gpointer target);
 134
 135 typedef enum {
 136         ArgInIReg,
 137         ArgInFloatReg,
 138         ArgInFloatRegR4,
 139         ArgOnStack,
 140         ArgValuetypeAddrInIReg,
 141         ArgAggregate,
 142         ArgSingleHFA,
 143         ArgDoubleHFA,
 144         ArgNone
 145 } ArgStorage;
 146
 147 typedef enum {
 148         AggregateNormal,
 149         AggregateSingleHFA,
 150         AggregateDoubleHFA
 151 } AggregateType;
 152
 153 typedef struct {
 154         gint16 offset;
 155         gint8  reg;
 156         ArgStorage storage;
 157
 158         /* Only if storage == ArgAggregate */
 159         int nregs, nslots;
 160         AggregateType atype;
 161 } ArgInfo;
 162
 163 typedef struct {
 164         int nargs;
 165         guint32 stack_usage;
 166         guint32 reg_usage;
 167         guint32 freg_usage;
 168         gboolean need_stack_align;
 169         gboolean vtype_retaddr;
 170         /* The index of the vret arg in the argument list */
 171         int vret_arg_index;
 172         ArgInfo ret;
 173         ArgInfo sig_cookie;
 174         ArgInfo args [1];
 175 } CallInfo;
 176
 177 #define DEBUG(a) if (cfg->verbose_level > 1) a
 178
 179 #define PARAM_REGS 8
 180
 181 static void inline
 182 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 183 {
 184     ainfo->offset = *stack_size;
 185
 186     if (*gr >= PARAM_REGS) {
 187                 ainfo->storage = ArgOnStack;
 188                 (*stack_size) += sizeof (gpointer);
 189     }
 190     else {
 191                 ainfo->storage = ArgInIReg;
 192                 ainfo->reg = *gr;
 193                 *(gr) += 1;
 194     }
 195 }
 196
 197 #define FLOAT_PARAM_REGS 8
 198
 199 static void inline
 200 add_float (guint32 *gr, guint32 *fr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 201 {
 202     ainfo->offset = *stack_size;
 203
 204     if (*gr >= PARAM_REGS) {
 205                 ainfo->storage = ArgOnStack;
 206                 (*stack_size) += sizeof (gpointer);
 207     }
 208     else {
 209                 ainfo->storage = is_double ? ArgInFloatReg : ArgInFloatRegR4;
 210                 ainfo->reg = 8 + *fr;
 211                 (*fr) += 1;
 212                 (*gr) += 1;
 213     }
 214 }
 215
 216 static void
 217 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 218                gboolean is_return,
 219                guint32 *gr, guint32 *fr, guint32 *stack_size)
 220 {
 221         guint32 size, i;
 222         MonoClass *klass;
 223         MonoMarshalType *info;
 224         gboolean is_hfa = TRUE;
 225         guint32 hfa_type = 0;
 226
 227         klass = mono_class_from_mono_type (type);
 228         if (type->type == MONO_TYPE_TYPEDBYREF)
 229                 size = 3 * sizeof (gpointer);
 230         else if (sig->pinvoke)
 231                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 232         else
 233                 size = mini_type_stack_size (gsctx, &klass->byval_arg, NULL);
 234
 235         if (!sig->pinvoke || (size == 0)) {
 236                 /* Allways pass in memory */
 237                 ainfo->offset = *stack_size;
 238                 *stack_size += ALIGN_TO (size, 8);
 239                 ainfo->storage = ArgOnStack;
 240
 241                 return;
 242         }
 243
 244         /* Determine whenever it is a HFA (Homogeneous Floating Point Aggregate) */
 245         info = mono_marshal_load_type_info (klass);
 246         g_assert (info);
 247         for (i = 0; i < info->num_fields; ++i) {
 248                 guint32 ftype = info->fields [i].field->type->type;
 249                 if (!(info->fields [i].field->type->byref) &&
 250                         ((ftype == MONO_TYPE_R4) || (ftype == MONO_TYPE_R8))) {
 251                         if (hfa_type == 0)
 252                                 hfa_type = ftype;
 253                         else if (hfa_type != ftype)
 254                                 is_hfa = FALSE;
 255                 }
 256                 else
 257                         is_hfa = FALSE;
 258         }
 259         if (hfa_type == 0)
 260                 is_hfa = FALSE;
 261
 262         ainfo->storage = ArgAggregate;
 263         ainfo->atype = AggregateNormal;
 264
 265         if (is_hfa) {
 266                 ainfo->atype = hfa_type == MONO_TYPE_R4 ? AggregateSingleHFA : AggregateDoubleHFA;
 267                 if (is_return) {
 268                         if (info->num_fields <= 8) {
 269                                 ainfo->reg = 8;
 270                                 ainfo->nregs = info->num_fields;
 271                                 ainfo->nslots = ainfo->nregs;
 272                                 return;
 273                         }
 274                         /* Fall through */
 275                 }
 276                 else {
 277                         if ((*fr) + info->num_fields > 8)
 278                                 NOT_IMPLEMENTED;
 279
 280                         ainfo->reg = 8 + (*fr);
 281                         ainfo->nregs = info->num_fields;
 282                         ainfo->nslots = ainfo->nregs;
 283                         (*fr) += info->num_fields;
 284                         if (ainfo->atype == AggregateSingleHFA) {
 285                                 /*
 286                                  * FIXME: Have to keep track of the parameter slot number, which is
 287                                  * not the same as *gr.
 288                                  */
 289                                 (*gr) += ALIGN_TO (info->num_fields, 2) / 2;
 290                         } else {
 291                                 (*gr) += info->num_fields;
 292                         }
 293                         return;
 294                 }
 295         }
 296
 297         /* This also handles returning of TypedByRef used by some icalls */
 298         if (is_return) {
 299                 if (size <= 32) {
 300                         ainfo->reg = IA64_R8;
 301                         ainfo->nregs = (size + 7) / 8;
 302                         ainfo->nslots = ainfo->nregs;
 303                         return;
 304                 }
 305                 NOT_IMPLEMENTED;
 306         }
 307
 308         ainfo->reg = (*gr);
 309         ainfo->offset = *stack_size;
 310         ainfo->nslots = (size + 7) / 8;
 311
 312         if (((*gr) + ainfo->nslots) <= 8) {
 313                 /* Fits entirely in registers */
 314                 ainfo->nregs = ainfo->nslots;
 315                 (*gr) += ainfo->nregs;
 316                 return;
 317         }
 318
 319         ainfo->nregs = 8 - (*gr);
 320         (*gr) = 8;
 321         (*stack_size) += (ainfo->nslots - ainfo->nregs) * 8;
 322 }
 323
 324 /*
 325  * get_call_info:
 326  *
 327  *  Obtain information about a call according to the calling convention.
 328  * For IA64, see the "Itanium Software Conventions and Runtime Architecture
 329  * Gude" document for more information.
 330  */
 331 static CallInfo*
 332 get_call_info (MonoCompile *cfg, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 333 {
 334         guint32 i, gr, fr, pstart;
 335         MonoType *ret_type;
 336         int n = sig->hasthis + sig->param_count;
 337         guint32 stack_size = 0;
 338         CallInfo *cinfo;
 339         MonoGenericSharingContext *gsctx = cfg ? cfg->generic_sharing_context : NULL;
 340
 341         if (mp)
 342                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 343         else
 344                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 345
 346         gr = 0;
 347         fr = 0;
 348
 349         /* return value */
 350         {
 351                 ret_type = mono_type_get_underlying_type (sig->ret);
 352                 ret_type = mini_get_basic_type_from_generic (gsctx, ret_type);
 353                 switch (ret_type->type) {
 354                 case MONO_TYPE_BOOLEAN:
 355                 case MONO_TYPE_I1:
 356                 case MONO_TYPE_U1:
 357                 case MONO_TYPE_I2:
 358                 case MONO_TYPE_U2:
 359                 case MONO_TYPE_CHAR:
 360                 case MONO_TYPE_I4:
 361                 case MONO_TYPE_U4:
 362                 case MONO_TYPE_I:
 363                 case MONO_TYPE_U:
 364                 case MONO_TYPE_PTR:
 365                 case MONO_TYPE_FNPTR:
 366                 case MONO_TYPE_CLASS:
 367                 case MONO_TYPE_OBJECT:
 368                 case MONO_TYPE_SZARRAY:
 369                 case MONO_TYPE_ARRAY:
 370                 case MONO_TYPE_STRING:
 371                         cinfo->ret.storage = ArgInIReg;
 372                         cinfo->ret.reg = IA64_R8;
 373                         break;
 374                 case MONO_TYPE_U8:
 375                 case MONO_TYPE_I8:
 376                         cinfo->ret.storage = ArgInIReg;
 377                         cinfo->ret.reg = IA64_R8;
 378                         break;
 379                 case MONO_TYPE_R4:
 380                 case MONO_TYPE_R8:
 381                         cinfo->ret.storage = ArgInFloatReg;
 382                         cinfo->ret.reg = 8;
 383                         break;
 384                 case MONO_TYPE_GENERICINST:
 385                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 386                                 cinfo->ret.storage = ArgInIReg;
 387                                 cinfo->ret.reg = IA64_R8;
 388                                 break;
 389                         }
 390                         /* Fall through */
 391                 case MONO_TYPE_VALUETYPE:
 392                 case MONO_TYPE_TYPEDBYREF: {
 393                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 394
 395                         if (sig->ret->byref) {
 396                                 /* This seems to happen with ldfld wrappers */
 397                                 cinfo->ret.storage = ArgInIReg;
 398                         } else {
 399                                 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 400                                 if (cinfo->ret.storage == ArgOnStack) {
 401                                         /* The caller passes the address where the value is stored */
 402                                         cinfo->vtype_retaddr = TRUE;
 403                                 }
 404                         }
 405                         break;
 406                 }
 407                 case MONO_TYPE_VOID:
 408                         cinfo->ret.storage = ArgNone;
 409                         break;
 410                 default:
 411                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 412                 }
 413         }
 414
 415         pstart = 0;
 416         /*
 417          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 418          * the first argument, allowing 'this' to be always passed in the first arg reg.
 419          * Also do this if the first argument is a reference type, since virtual calls
 420          * are sometimes made using calli without sig->hasthis set, like in the delegate
 421          * invoke wrappers.
 422          */
 423         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
 424                 if (sig->hasthis) {
 425                         add_general (&gr, &stack_size, cinfo->args + 0);
 426                 } else {
 427                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 428                         pstart = 1;
 429                 }
 430                 add_general (&gr, &stack_size, &cinfo->ret);
 431                 if (cinfo->ret.storage == ArgInIReg)
 432                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
 433                 cinfo->vret_arg_index = 1;
 434         } else {
 435                 /* this */
 436                 if (sig->hasthis)
 437                         add_general (&gr, &stack_size, cinfo->args + 0);
 438
 439                 if (cinfo->vtype_retaddr) {
 440                         add_general (&gr, &stack_size, &cinfo->ret);
 441                         if (cinfo->ret.storage == ArgInIReg)
 442                                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
 443                 }
 444         }
 445
 446         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 447                 gr = PARAM_REGS;
 448                 fr = FLOAT_PARAM_REGS;
 449
 450                 /* Emit the signature cookie just before the implicit arguments */
 451                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 452         }
 453
 454         for (i = pstart; i < sig->param_count; ++i) {
 455                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 456                 MonoType *ptype;
 457
 458                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 459                         /* We allways pass the sig cookie on the stack for simplicity */
 460                         /*
 461                          * Prevent implicit arguments + the sig cookie from being passed
 462                          * in registers.
 463                          */
 464                         gr = PARAM_REGS;
 465                         fr = FLOAT_PARAM_REGS;
 466
 467                         /* Emit the signature cookie just before the implicit arguments */
 468                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 469                 }
 470
 471                 if (sig->params [i]->byref) {
 472                         add_general (&gr, &stack_size, ainfo);
 473                         continue;
 474                 }
 475                 ptype = mono_type_get_underlying_type (sig->params [i]);
 476                 ptype = mini_get_basic_type_from_generic (gsctx, ptype);
 477                 switch (ptype->type) {
 478                 case MONO_TYPE_BOOLEAN:
 479                 case MONO_TYPE_I1:
 480                 case MONO_TYPE_U1:
 481                         add_general (&gr, &stack_size, ainfo);
 482                         break;
 483                 case MONO_TYPE_I2:
 484                 case MONO_TYPE_U2:
 485                 case MONO_TYPE_CHAR:
 486                         add_general (&gr, &stack_size, ainfo);
 487                         break;
 488                 case MONO_TYPE_I4:
 489                 case MONO_TYPE_U4:
 490                         add_general (&gr, &stack_size, ainfo);
 491                         break;
 492                 case MONO_TYPE_I:
 493                 case MONO_TYPE_U:
 494                 case MONO_TYPE_PTR:
 495                 case MONO_TYPE_FNPTR:
 496                 case MONO_TYPE_CLASS:
 497                 case MONO_TYPE_OBJECT:
 498                 case MONO_TYPE_STRING:
 499                 case MONO_TYPE_SZARRAY:
 500                 case MONO_TYPE_ARRAY:
 501                         add_general (&gr, &stack_size, ainfo);
 502                         break;
 503                 case MONO_TYPE_GENERICINST:
 504                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 505                                 add_general (&gr, &stack_size, ainfo);
 506                                 break;
 507                         }
 508                         /* Fall through */
 509                 case MONO_TYPE_VALUETYPE:
 510                 case MONO_TYPE_TYPEDBYREF:
 511                         /* FIXME: */
 512                         /* We allways pass valuetypes on the stack */
 513                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 514                         break;
 515                 case MONO_TYPE_U8:
 516                 case MONO_TYPE_I8:
 517                         add_general (&gr, &stack_size, ainfo);
 518                         break;
 519                 case MONO_TYPE_R4:
 520                         add_float (&gr, &fr, &stack_size, ainfo, FALSE);
 521                         break;
 522                 case MONO_TYPE_R8:
 523                         add_float (&gr, &fr, &stack_size, ainfo, TRUE);
 524                         break;
 525                 default:
 526                         g_assert_not_reached ();
 527                 }
 528         }
 529
 530         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 531                 gr = PARAM_REGS;
 532                 fr = FLOAT_PARAM_REGS;
 533
 534                 /* Emit the signature cookie just before the implicit arguments */
 535                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 536         }
 537
 538         cinfo->stack_usage = stack_size;
 539         cinfo->reg_usage = gr;
 540         cinfo->freg_usage = fr;
 541         return cinfo;
 542 }
 543
 544 /*
 545  * mono_arch_get_argument_info:
 546  * @csig:  a method signature
 547  * @param_count: the number of parameters to consider
 548  * @arg_info: an array to store the result infos
 549  *
 550  * Gathers information on parameters such as size, alignment and
 551  * padding. arg_info should be large enought to hold param_count + 1 entries.
 552  *
 553  * Returns the size of the argument area on the stack.
 554  */
 555 int
 556 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 557 {
 558         int k;
 559         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 560         guint32 args_size = cinfo->stack_usage;
 561
 562         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 563         if (csig->hasthis) {
 564                 arg_info [0].offset = 0;
 565         }
 566
 567         for (k = 0; k < param_count; k++) {
 568                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 569                 /* FIXME: */
 570                 arg_info [k + 1].size = 0;
 571         }
 572
 573         g_free (cinfo);
 574
 575         return args_size;
 576 }
 577
 578 /*
 579  * Initialize the cpu to execute managed code.
 580  */
 581 void
 582 mono_arch_cpu_init (void)
 583 {
 584 }
 585
 586 /*
 587  * Initialize architecture specific code.
 588  */
 589 void
 590 mono_arch_init (void)
 591 {
 592 }
 593
 594 /*
 595  * Cleanup architecture specific code.
 596  */
 597 void
 598 mono_arch_cleanup (void)
 599 {
 600 }
 601
 602 /*
 603  * This function returns the optimizations supported on this cpu.
 604  */
 605 guint32
 606 mono_arch_cpu_optimizations (guint32 *exclude_mask)
 607 {
 608         *exclude_mask = 0;
 609
 610         return 0;
 611 }
 612
 613 gboolean
 614 mono_arch_is_soft_float (void)
 615 {
 616         return FALSE;
 617 }
 618
 619 /*
 620  * This function test for all SIMD functions supported.
 621  *
 622  * Returns a bitmask corresponding to all supported versions.
 623  *
 624  */
 625 guint32
 626 mono_arch_cpu_enumerate_simd_versions (void)
 627 {
 628         /* SIMD is currently unimplemented */
 629         return 0;
 630 }
 631
 632 GList *
 633 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 634 {
 635         GList *vars = NULL;
 636         int i;
 637         MonoMethodSignature *sig;
 638         MonoMethodHeader *header;
 639         CallInfo *cinfo;
 640
 641         header = cfg->header;
 642
 643         sig = mono_method_signature (cfg->method);
 644
 645         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 646
 647         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 648                 MonoInst *ins = cfg->args [i];
 649
 650                 ArgInfo *ainfo = &cinfo->args [i];
 651
 652                 if (ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 653                         continue;
 654
 655                 if (ainfo->storage == ArgInIReg) {
 656                         /* The input registers are non-volatile */
 657                         ins->opcode = OP_REGVAR;
 658                         ins->dreg = 32 + ainfo->reg;
 659                 }
 660         }
 661
 662         for (i = 0; i < cfg->num_varinfo; i++) {
 663                 MonoInst *ins = cfg->varinfo [i];
 664                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 665
 666                 /* unused vars */
 667                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 668                         continue;
 669
 670                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 671                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 672                         continue;
 673
 674                 if (mono_is_regsize_var (ins->inst_vtype)) {
 675                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 676                         g_assert (i == vmv->idx);
 677                         vars = g_list_prepend (vars, vmv);
 678                 }
 679         }
 680
 681         vars = mono_varlist_sort (cfg, vars, 0);
 682
 683         return vars;
 684 }
 685
 686 static void
 687 mono_ia64_alloc_stacked_registers (MonoCompile *cfg)
 688 {
 689         CallInfo *cinfo;
 690         guint32 reserved_regs;
 691         MonoMethodHeader *header;
 692
 693         if (cfg->arch.reg_local0 > 0)
 694                 /* Already done */
 695                 return;
 696
 697         cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (cfg->method), FALSE);
 698
 699         header = cfg->header;
 700
 701         /* Some registers are reserved for use by the prolog/epilog */
 702         reserved_regs = header->num_clauses ? 4 : 3;
 703
 704         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 705                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
 706                 /* One registers is needed by instrument_epilog to save the return value */
 707                 reserved_regs ++;
 708                 if (cinfo->reg_usage < 2)
 709                         /* Number of arguments passed to function call in instrument_prolog */
 710                         cinfo->reg_usage = 2;
 711         }
 712
 713         cfg->arch.reg_in0 = 32;
 714         cfg->arch.reg_local0 = cfg->arch.reg_in0 + cinfo->reg_usage + reserved_regs;
 715         cfg->arch.reg_out0 = cfg->arch.reg_local0 + 16;
 716
 717         cfg->arch.reg_saved_ar_pfs = cfg->arch.reg_local0 - 1;
 718         cfg->arch.reg_saved_b0 = cfg->arch.reg_local0 - 2;
 719         cfg->arch.reg_fp = cfg->arch.reg_local0 - 3;
 720
 721         /*
 722          * Frames without handlers save sp to fp, frames with handlers save it into
 723          * a dedicated register.
 724          */
 725         if (header->num_clauses)
 726                 cfg->arch.reg_saved_sp = cfg->arch.reg_local0 - 4;
 727         else
 728                 cfg->arch.reg_saved_sp = cfg->arch.reg_fp;
 729
 730         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 731                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
 732                 cfg->arch.reg_saved_return_val = cfg->arch.reg_local0 - reserved_regs;
 733         }
 734
 735         /*
 736          * Need to allocate at least 2 out register for use by OP_THROW / the system
 737          * exception throwing code.
 738          */
 739         cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, 2);
 740 }
 741
 742 GList *
 743 mono_arch_get_global_int_regs (MonoCompile *cfg)
 744 {
 745         GList *regs = NULL;
 746         int i;
 747
 748         mono_ia64_alloc_stacked_registers (cfg);
 749
 750         for (i = cfg->arch.reg_local0; i < cfg->arch.reg_out0; ++i) {
 751                 /* FIXME: regmask */
 752                 g_assert (i < 64);
 753                 regs = g_list_prepend (regs, (gpointer)(gssize)(i));
 754         }
 755
 756         return regs;
 757 }
 758
 759 /*
 760  * mono_arch_regalloc_cost:
 761  *
 762  *  Return the cost, in number of memory references, of the action of
 763  * allocating the variable VMV into a register during global register
 764  * allocation.
 765  */
 766 guint32
 767 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 768 {
 769         /* FIXME: Increase costs linearly to avoid using all local registers */
 770
 771         return 0;
 772 }
 773
 774 void
 775 mono_arch_allocate_vars (MonoCompile *cfg)
 776 {
 777         MonoMethodSignature *sig;
 778         MonoMethodHeader *header;
 779         MonoInst *inst;
 780         int i, offset;
 781         guint32 locals_stack_size, locals_stack_align;
 782         gint32 *offsets;
 783         CallInfo *cinfo;
 784
 785         header = cfg->header;
 786
 787         sig = mono_method_signature (cfg->method);
 788
 789         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 790
 791         /*
 792          * Determine whenever the frame pointer can be eliminated.
 793          * FIXME: Remove some of the restrictions.
 794          */
 795         cfg->arch.omit_fp = TRUE;
 796
 797         if (!debug_omit_fp ())
 798                 cfg->arch.omit_fp = FALSE;
 799
 800         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 801                 cfg->arch.omit_fp = FALSE;
 802         if (header->num_clauses)
 803                 cfg->arch.omit_fp = FALSE;
 804         if (cfg->param_area)
 805                 cfg->arch.omit_fp = FALSE;
 806         if ((sig->ret->type != MONO_TYPE_VOID) && (cinfo->ret.storage == ArgAggregate))
 807                 cfg->arch.omit_fp = FALSE;
 808         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 809                 cfg->arch.omit_fp = FALSE;
 810         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 811                 ArgInfo *ainfo = &cinfo->args [i];
 812
 813                 if (ainfo->storage == ArgOnStack) {
 814                         /*
 815                          * The stack offset can only be determined when the frame
 816                          * size is known.
 817                          */
 818                         cfg->arch.omit_fp = FALSE;
 819                 }
 820         }
 821
 822         mono_ia64_alloc_stacked_registers (cfg);
 823
 824         /*
 825          * We use the ABI calling conventions for managed code as well.
 826          * Exception: valuetypes are never passed or returned in registers.
 827          */
 828
 829         if (cfg->arch.omit_fp) {
 830                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
 831                 cfg->frame_reg = IA64_SP;
 832                 offset = ARGS_OFFSET;
 833         }
 834         else {
 835                 /* Locals are allocated backwards from %fp */
 836                 cfg->frame_reg = cfg->arch.reg_fp;
 837                 offset = 0;
 838         }
 839
 840         if (cfg->method->save_lmf) {
 841                 /* No LMF on IA64 */
 842         }
 843
 844         if (sig->ret->type != MONO_TYPE_VOID) {
 845                 switch (cinfo->ret.storage) {
 846                 case ArgInIReg:
 847                         cfg->ret->opcode = OP_REGVAR;
 848                         cfg->ret->inst_c0 = cinfo->ret.reg;
 849                         break;
 850                 case ArgInFloatReg:
 851                         cfg->ret->opcode = OP_REGVAR;
 852                         cfg->ret->inst_c0 = cinfo->ret.reg;
 853                         break;
 854                 case ArgValuetypeAddrInIReg:
 855                         cfg->vret_addr->opcode = OP_REGVAR;
 856                         cfg->vret_addr->dreg = cfg->arch.reg_in0 + cinfo->ret.reg;
 857                         break;
 858                 case ArgAggregate:
 859                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
 860                         if (cfg->arch.omit_fp)
 861                                 g_assert_not_reached ();
 862                         offset = ALIGN_TO (offset, 8);
 863                         offset += cinfo->ret.nslots * 8;
 864                         cfg->ret->opcode = OP_REGOFFSET;
 865                         cfg->ret->inst_basereg = cfg->frame_reg;
 866                         cfg->ret->inst_offset = - offset;
 867                         break;
 868                 default:
 869                         g_assert_not_reached ();
 870                 }
 871                 cfg->ret->dreg = cfg->ret->inst_c0;
 872         }
 873
 874         /* Allocate locals */
 875         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE : TRUE, &locals_stack_size, &locals_stack_align);
 876         if (locals_stack_align) {
 877                 offset = ALIGN_TO (offset, locals_stack_align);
 878         }
 879         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
 880                 if (offsets [i] != -1) {
 881                         MonoInst *inst = cfg->varinfo [i];
 882                         inst->opcode = OP_REGOFFSET;
 883                         inst->inst_basereg = cfg->frame_reg;
 884                         if (cfg->arch.omit_fp)
 885                                 inst->inst_offset = (offset + offsets [i]);
 886                         else
 887                                 inst->inst_offset = - (offset + offsets [i]);
 888                         // printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
 889                 }
 890         }
 891         offset += locals_stack_size;
 892
 893         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
 894                 if (cfg->arch.omit_fp)
 895                         g_assert_not_reached ();
 896                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
 897                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
 898         }
 899
 900         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 901                 inst = cfg->args [i];
 902                 if (inst->opcode != OP_REGVAR) {
 903                         ArgInfo *ainfo = &cinfo->args [i];
 904                         gboolean inreg = TRUE;
 905                         MonoType *arg_type;
 906
 907                         if (sig->hasthis && (i == 0))
 908                                 arg_type = &mono_defaults.object_class->byval_arg;
 909                         else
 910                                 arg_type = sig->params [i - sig->hasthis];
 911
 912                         /* FIXME: VOLATILE is only set if the liveness pass runs */
 913                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 914                                 inreg = FALSE;
 915
 916                         inst->opcode = OP_REGOFFSET;
 917
 918                         switch (ainfo->storage) {
 919                         case ArgInIReg:
 920                                 inst->opcode = OP_REGVAR;
 921                                 inst->dreg = cfg->arch.reg_in0 + ainfo->reg;
 922                                 break;
 923                         case ArgInFloatReg:
 924                         case ArgInFloatRegR4:
 925                                 /*
 926                                  * Since float regs are volatile, we save the arguments to
 927                                  * the stack in the prolog.
 928                                  */
 929                                 inreg = FALSE;
 930                                 break;
 931                         case ArgOnStack:
 932                                 if (cfg->arch.omit_fp)
 933                                         g_assert_not_reached ();
 934                                 inst->opcode = OP_REGOFFSET;
 935                                 inst->inst_basereg = cfg->frame_reg;
 936                                 inst->inst_offset = ARGS_OFFSET + ainfo->offset;
 937                                 break;
 938                         case ArgAggregate:
 939                                 inreg = FALSE;
 940                                 break;
 941                         default:
 942                                 NOT_IMPLEMENTED;
 943                         }
 944
 945                         if (!inreg && (ainfo->storage != ArgOnStack)) {
 946                                 guint32 size = 0;
 947
 948                                 inst->opcode = OP_REGOFFSET;
 949                                 inst->inst_basereg = cfg->frame_reg;
 950                                 /* These arguments are saved to the stack in the prolog */
 951                                 switch (ainfo->storage) {
 952                                 case ArgAggregate:
 953                                         if (ainfo->atype == AggregateSingleHFA)
 954                                                 size = ainfo->nslots * 4;
 955                                         else
 956                                                 size = ainfo->nslots * 8;
 957                                         break;
 958                                 default:
 959                                         size = sizeof (gpointer);
 960                                         break;
 961                                 }
 962
 963                                 offset = ALIGN_TO (offset, sizeof (gpointer));
 964
 965                                 if (cfg->arch.omit_fp) {
 966                                         inst->inst_offset = offset;
 967                                         offset += size;
 968                                 } else {
 969                                         offset += size;
 970                                         inst->inst_offset = - offset;
 971                                 }
 972                         }
 973                 }
 974         }
 975
 976         /*
 977          * FIXME: This doesn't work because some variables are allocated during local
 978          * regalloc.
 979          */
 980         /*
 981         if (cfg->arch.omit_fp && offset == 16)
 982                 offset = 0;
 983         */
 984
 985         cfg->stack_offset = offset;
 986 }
 987
 988 void
 989 mono_arch_create_vars (MonoCompile *cfg)
 990 {
 991         MonoMethodSignature *sig;
 992         CallInfo *cinfo;
 993
 994         sig = mono_method_signature (cfg->method);
 995
 996         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 997
 998         if (cinfo->ret.storage == ArgAggregate)
 999                 cfg->ret_var_is_local = TRUE;
1000         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1001                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1002                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1003                         printf ("vret_addr = ");
1004                         mono_print_ins (cfg->vret_addr);
1005                 }
1006         }
1007 }
1008
1009 static void
1010 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1011 {
1012         MonoInst *arg;
1013
1014         MONO_INST_NEW (cfg, arg, OP_NOP);
1015         arg->sreg1 = tree->dreg;
1016
1017         switch (storage) {
1018         case ArgInIReg:
1019                 arg->opcode = OP_MOVE;
1020                 arg->dreg = mono_alloc_ireg (cfg);
1021
1022                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, FALSE);
1023                 break;
1024         case ArgInFloatReg:
1025                 arg->opcode = OP_FMOVE;
1026                 arg->dreg = mono_alloc_freg (cfg);
1027
1028                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1029                 break;
1030         case ArgInFloatRegR4:
1031                 arg->opcode = OP_FCONV_TO_R4;
1032                 arg->dreg = mono_alloc_freg (cfg);
1033
1034                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1035                 break;
1036         default:
1037                 g_assert_not_reached ();
1038         }
1039
1040         MONO_ADD_INS (cfg->cbb, arg);
1041 }
1042
1043 static void
1044 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1045 {
1046         MonoMethodSignature *tmp_sig;
1047
1048         /* Emit the signature cookie just before the implicit arguments */
1049         MonoInst *sig_arg;
1050         /* FIXME: Add support for signature tokens to AOT */
1051         cfg->disable_aot = TRUE;
1052
1053         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1054
1055         /*
1056          * mono_ArgIterator_Setup assumes the signature cookie is
1057          * passed first and all the arguments which were before it are
1058          * passed on the stack after the signature. So compensate by
1059          * passing a different signature.
1060          */
1061         tmp_sig = mono_metadata_signature_dup (call->signature);
1062         tmp_sig->param_count -= call->signature->sentinelpos;
1063         tmp_sig->sentinelpos = 0;
1064         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1065
1066         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1067         sig_arg->dreg = mono_alloc_ireg (cfg);
1068         sig_arg->inst_p0 = tmp_sig;
1069         MONO_ADD_INS (cfg->cbb, sig_arg);
1070
1071         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + cinfo->sig_cookie.offset, sig_arg->dreg);
1072 }
1073
1074 void
1075 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1076 {
1077         MonoInst *in;
1078         MonoMethodSignature *sig;
1079         int i, n, stack_size;
1080         CallInfo *cinfo;
1081         ArgInfo *ainfo;
1082
1083         stack_size = 0;
1084
1085         mono_ia64_alloc_stacked_registers (cfg);
1086
1087         sig = call->signature;
1088         n = sig->param_count + sig->hasthis;
1089
1090         cinfo = get_call_info (cfg, cfg->mempool, sig, sig->pinvoke);
1091
1092         if (cinfo->ret.storage == ArgAggregate) {
1093                 MonoInst *vtarg;
1094                 MonoInst *local;
1095
1096                 /*
1097                  * The valuetype is in registers after the call, need to be copied
1098                  * to the stack. Save the address to a local here, so the call
1099                  * instruction can access it.
1100                  */
1101                 local = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1102                 local->flags |= MONO_INST_VOLATILE;
1103                 cfg->arch.ret_var_addr_local = local;
1104
1105                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1106                 vtarg->sreg1 = call->vret_var->dreg;
1107                 vtarg->dreg = local->dreg;
1108                 MONO_ADD_INS (cfg->cbb, vtarg);
1109         }
1110
1111         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1112                 add_outarg_reg (cfg, call, ArgInIReg, cfg->arch.reg_out0 + cinfo->ret.reg, call->vret_var);
1113         }
1114
1115         for (i = 0; i < n; ++i) {
1116                 MonoType *arg_type;
1117
1118                 ainfo = cinfo->args + i;
1119
1120                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1121                         /* Emit the signature cookie just before the implicit arguments */
1122                         emit_sig_cookie (cfg, call, cinfo);
1123                 }
1124
1125                 in = call->args [i];
1126
1127                 if (sig->hasthis && (i == 0))
1128                         arg_type = &mono_defaults.object_class->byval_arg;
1129                 else
1130                         arg_type = sig->params [i - sig->hasthis];
1131
1132                 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(arg_type))) {
1133                         guint32 align;
1134                         guint32 size;
1135
1136                         if (arg_type->type == MONO_TYPE_TYPEDBYREF) {
1137                                 size = sizeof (MonoTypedRef);
1138                                 align = sizeof (gpointer);
1139                         }
1140                         else if (sig->pinvoke)
1141                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1142                         else {
1143                                 /*
1144                                  * Other backends use mono_type_stack_size (), but that
1145                                  * aligns the size to 8, which is larger than the size of
1146                                  * the source, leading to reads of invalid memory if the
1147                                  * source is at the end of address space.
1148                                  */
1149                                 size = mono_class_value_size (in->klass, &align);
1150                         }
1151
1152                         if (size > 0) {
1153                                 MonoInst *arg;
1154
1155                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1156                                 arg->sreg1 = in->dreg;
1157                                 arg->klass = in->klass;
1158                                 arg->backend.size = size;
1159                                 arg->inst_p0 = call;
1160                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1161                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1162
1163                                 MONO_ADD_INS (cfg->cbb, arg);
1164                         }
1165                 }
1166                 else {
1167                         switch (ainfo->storage) {
1168                         case ArgInIReg:
1169                                 add_outarg_reg (cfg, call, ainfo->storage, cfg->arch.reg_out0 + ainfo->reg, in);
1170                                 break;
1171                         case ArgInFloatReg:
1172                         case ArgInFloatRegR4:
1173                                 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1174                                 break;
1175                         case ArgOnStack:
1176                                 if (arg_type->type == MONO_TYPE_R4 && !arg_type->byref)
1177                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1178                                 else if (arg_type->type == MONO_TYPE_R8 && !arg_type->byref)
1179                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1180                                 else
1181                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1182                                 break;
1183                         default:
1184                                 g_assert_not_reached ();
1185                         }
1186                 }
1187         }
1188
1189         /* Handle the case where there are no implicit arguments */
1190         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1191                 emit_sig_cookie (cfg, call, cinfo);
1192         }
1193
1194         call->stack_usage = cinfo->stack_usage;
1195         cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, cinfo->reg_usage);
1196 }
1197
1198 void
1199 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1200 {
1201         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1202         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1203         int size = ins->backend.size;
1204
1205         if (ainfo->storage == ArgAggregate) {
1206                 MonoInst *load, *store;
1207                 int i, slot;
1208
1209                 /*
1210                  * Part of the structure is passed in registers.
1211                  */
1212                 for (i = 0; i < ainfo->nregs; ++i) {
1213                         slot = ainfo->reg + i;
1214
1215                         if (ainfo->atype == AggregateSingleHFA) {
1216                                 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
1217                                 load->inst_basereg = src->dreg;
1218                                 load->inst_offset = i * 4;
1219                                 load->dreg = mono_alloc_freg (cfg);
1220
1221                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1222                         } else if (ainfo->atype == AggregateDoubleHFA) {
1223                                 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
1224                                 load->inst_basereg = src->dreg;
1225                                 load->inst_offset = i * 8;
1226                                 load->dreg = mono_alloc_freg (cfg);
1227
1228                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1229                         } else {
1230                                 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1231                                 load->inst_basereg = src->dreg;
1232                                 load->inst_offset = i * 8;
1233                                 load->dreg = mono_alloc_ireg (cfg);
1234
1235                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, cfg->arch.reg_out0 + ainfo->reg + i, FALSE);
1236                         }
1237                         MONO_ADD_INS (cfg->cbb, load);
1238                 }
1239
1240                 /*
1241                  * Part of the structure is passed on the stack.
1242                  */
1243                 for (i = ainfo->nregs; i < ainfo->nslots; ++i) {
1244                         slot = ainfo->reg + i;
1245
1246                         MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1247                         load->inst_basereg = src->dreg;
1248                         load->inst_offset = i * sizeof (gpointer);
1249                         load->dreg = mono_alloc_preg (cfg);
1250                         MONO_ADD_INS (cfg->cbb, load);
1251
1252                         MONO_INST_NEW (cfg, store, OP_STOREI8_MEMBASE_REG);
1253                         store->sreg1 = load->dreg;
1254                         store->inst_destbasereg = IA64_SP;
1255                         store->inst_offset = 16 + ainfo->offset + (slot - 8) * 8;
1256                         MONO_ADD_INS (cfg->cbb, store);
1257                 }
1258         } else {
1259                 mini_emit_memcpy (cfg, IA64_SP, 16 + ainfo->offset, src->dreg, 0, size, 4);
1260         }
1261 }
1262
1263 void
1264 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1265 {
1266         CallInfo *cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
1267
1268         switch (cinfo->ret.storage) {
1269         case ArgInIReg:
1270                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1271                 break;
1272         case ArgInFloatReg:
1273                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1274                 break;
1275         default:
1276                 g_assert_not_reached ();
1277         }
1278 }
1279
1280 void
1281 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1282 {
1283 }
1284
1285 void
1286 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1287 {
1288         MonoInst *ins, *n, *last_ins = NULL;
1289         ins = bb->code;
1290
1291         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1292                 switch (ins->opcode) {
1293                 case OP_MOVE:
1294                 case OP_FMOVE:
1295                         /*
1296                          * Removes:
1297                          *
1298                          * OP_MOVE reg, reg
1299                          */
1300                         if (ins->dreg == ins->sreg1) {
1301                                 MONO_DELETE_INS (bb, ins);
1302                                 continue;
1303                         }
1304                         /*
1305                          * Removes:
1306                          *
1307                          * OP_MOVE sreg, dreg
1308                          * OP_MOVE dreg, sreg
1309                          */
1310                         if (last_ins && last_ins->opcode == OP_MOVE &&
1311                             ins->sreg1 == last_ins->dreg &&
1312                             ins->dreg == last_ins->sreg1) {
1313                                 MONO_DELETE_INS (bb, ins);
1314                                 continue;
1315                         }
1316                         break;
1317                 case OP_MUL_IMM:
1318                 case OP_IMUL_IMM:
1319                         /* remove unnecessary multiplication with 1 */
1320                         if (ins->inst_imm == 1) {
1321                                 if (ins->dreg != ins->sreg1) {
1322                                         ins->opcode = OP_MOVE;
1323                                 } else {
1324                                         MONO_DELETE_INS (bb, ins);
1325                                         continue;
1326                                 }
1327                         }
1328                         break;
1329                 }
1330
1331                 last_ins = ins;
1332                 ins = ins->next;
1333         }
1334         bb->last_ins = last_ins;
1335 }
1336
1337 int cond_to_ia64_cmp [][3] = {
1338         {OP_IA64_CMP_EQ, OP_IA64_CMP4_EQ, OP_IA64_FCMP_EQ},
1339         {OP_IA64_CMP_NE, OP_IA64_CMP4_NE, OP_IA64_FCMP_NE},
1340         {OP_IA64_CMP_LE, OP_IA64_CMP4_LE, OP_IA64_FCMP_LE},
1341         {OP_IA64_CMP_GE, OP_IA64_CMP4_GE, OP_IA64_FCMP_GE},
1342         {OP_IA64_CMP_LT, OP_IA64_CMP4_LT, OP_IA64_FCMP_LT},
1343         {OP_IA64_CMP_GT, OP_IA64_CMP4_GT, OP_IA64_FCMP_GT},
1344         {OP_IA64_CMP_LE_UN, OP_IA64_CMP4_LE_UN, OP_IA64_FCMP_LE_UN},
1345         {OP_IA64_CMP_GE_UN, OP_IA64_CMP4_GE_UN, OP_IA64_FCMP_GE_UN},
1346         {OP_IA64_CMP_LT_UN, OP_IA64_CMP4_LT_UN, OP_IA64_FCMP_LT_UN},
1347         {OP_IA64_CMP_GT_UN, OP_IA64_CMP4_GT_UN, OP_IA64_FCMP_GT_UN}
1348 };
1349
1350 static int
1351 opcode_to_ia64_cmp (int opcode, int cmp_opcode)
1352 {
1353         return cond_to_ia64_cmp [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1354 }
1355
1356 int cond_to_ia64_cmp_imm [][3] = {
1357         {OP_IA64_CMP_EQ_IMM, OP_IA64_CMP4_EQ_IMM, 0},
1358         {OP_IA64_CMP_NE_IMM, OP_IA64_CMP4_NE_IMM, 0},
1359         {OP_IA64_CMP_GE_IMM, OP_IA64_CMP4_GE_IMM, 0},
1360         {OP_IA64_CMP_LE_IMM, OP_IA64_CMP4_LE_IMM, 0},
1361         {OP_IA64_CMP_GT_IMM, OP_IA64_CMP4_GT_IMM, 0},
1362         {OP_IA64_CMP_LT_IMM, OP_IA64_CMP4_LT_IMM, 0},
1363         {OP_IA64_CMP_GE_UN_IMM, OP_IA64_CMP4_GE_UN_IMM, 0},
1364         {OP_IA64_CMP_LE_UN_IMM, OP_IA64_CMP4_LE_UN_IMM, 0},
1365         {OP_IA64_CMP_GT_UN_IMM, OP_IA64_CMP4_GT_UN_IMM, 0},
1366         {OP_IA64_CMP_LT_UN_IMM, OP_IA64_CMP4_LT_UN_IMM, 0},
1367 };
1368
1369 static int
1370 opcode_to_ia64_cmp_imm (int opcode, int cmp_opcode)
1371 {
1372         /* The condition needs to be reversed */
1373         return cond_to_ia64_cmp_imm [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1374 }
1375
1376 #define NEW_INS(cfg,dest,op) do {       \
1377                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1378                 (dest)->opcode = (op);  \
1379         mono_bblock_insert_after_ins (bb, last_ins, (dest)); \
1380         last_ins = (dest); \
1381         } while (0)
1382
1383 /*
1384  * mono_arch_lowering_pass:
1385  *
1386  *  Converts complex opcodes into simpler ones so that each IR instruction
1387  * corresponds to one machine instruction.
1388  */
1389 void
1390 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1391 {
1392         MonoInst *ins, *n, *next, *temp, *temp2, *temp3, *last_ins = NULL;
1393         ins = bb->code;
1394
1395         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1396                 switch (ins->opcode) {
1397                 case OP_STOREI1_MEMBASE_IMM:
1398                 case OP_STOREI2_MEMBASE_IMM:
1399                 case OP_STOREI4_MEMBASE_IMM:
1400                 case OP_STOREI8_MEMBASE_IMM:
1401                 case OP_STORE_MEMBASE_IMM:
1402                         /* There are no store_membase instructions on ia64 */
1403                         if (ins->inst_offset == 0) {
1404                                 temp2 = NULL;
1405                         } else if (ia64_is_imm14 (ins->inst_offset)) {
1406                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1407                                 temp2->sreg1 = ins->inst_destbasereg;
1408                                 temp2->inst_imm = ins->inst_offset;
1409                                 temp2->dreg = mono_alloc_ireg (cfg);
1410                         }
1411                         else {
1412                                 NEW_INS (cfg, temp, OP_I8CONST);
1413                                 temp->inst_c0 = ins->inst_offset;
1414                                 temp->dreg = mono_alloc_ireg (cfg);
1415
1416                                 NEW_INS (cfg, temp2, OP_LADD);
1417                                 temp2->sreg1 = ins->inst_destbasereg;
1418                                 temp2->sreg2 = temp->dreg;
1419                                 temp2->dreg = mono_alloc_ireg (cfg);
1420                         }
1421
1422                         switch (ins->opcode) {
1423                         case OP_STOREI1_MEMBASE_IMM:
1424                                 ins->opcode = OP_STOREI1_MEMBASE_REG;
1425                                 break;
1426                         case OP_STOREI2_MEMBASE_IMM:
1427                                 ins->opcode = OP_STOREI2_MEMBASE_REG;
1428                                 break;
1429                         case OP_STOREI4_MEMBASE_IMM:
1430                                 ins->opcode = OP_STOREI4_MEMBASE_REG;
1431                                 break;
1432                         case OP_STOREI8_MEMBASE_IMM:
1433                         case OP_STORE_MEMBASE_IMM:
1434                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
1435                                 break;
1436                         default:
1437                                 g_assert_not_reached ();
1438                         }
1439
1440                         if (ins->inst_imm == 0)
1441                                 ins->sreg1 = IA64_R0;
1442                         else {
1443                                 NEW_INS (cfg, temp3, OP_I8CONST);
1444                                 temp3->inst_c0 = ins->inst_imm;
1445                                 temp3->dreg = mono_alloc_ireg (cfg);
1446                                 ins->sreg1 = temp3->dreg;
1447                         }
1448
1449                         ins->inst_offset = 0;
1450                         if (temp2)
1451                                 ins->inst_destbasereg = temp2->dreg;
1452                         break;
1453                 case OP_STOREI1_MEMBASE_REG:
1454                 case OP_STOREI2_MEMBASE_REG:
1455                 case OP_STOREI4_MEMBASE_REG:
1456                 case OP_STOREI8_MEMBASE_REG:
1457                 case OP_STORER4_MEMBASE_REG:
1458                 case OP_STORER8_MEMBASE_REG:
1459                 case OP_STORE_MEMBASE_REG:
1460                         /* There are no store_membase instructions on ia64 */
1461                         if (ins->inst_offset == 0) {
1462                                 break;
1463                         }
1464                         else if (ia64_is_imm14 (ins->inst_offset)) {
1465                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1466                                 temp2->sreg1 = ins->inst_destbasereg;
1467                                 temp2->inst_imm = ins->inst_offset;
1468                                 temp2->dreg = mono_alloc_ireg (cfg);
1469                         }
1470                         else {
1471                                 NEW_INS (cfg, temp, OP_I8CONST);
1472                                 temp->inst_c0 = ins->inst_offset;
1473                                 temp->dreg = mono_alloc_ireg (cfg);
1474                                 NEW_INS (cfg, temp2, OP_LADD);
1475                                 temp2->sreg1 = ins->inst_destbasereg;
1476                                 temp2->sreg2 = temp->dreg;
1477                                 temp2->dreg = mono_alloc_ireg (cfg);
1478                         }
1479
1480                         ins->inst_offset = 0;
1481                         ins->inst_destbasereg = temp2->dreg;
1482                         break;
1483                 case OP_LOADI1_MEMBASE:
1484                 case OP_LOADU1_MEMBASE:
1485                 case OP_LOADI2_MEMBASE:
1486                 case OP_LOADU2_MEMBASE:
1487                 case OP_LOADI4_MEMBASE:
1488                 case OP_LOADU4_MEMBASE:
1489                 case OP_LOADI8_MEMBASE:
1490                 case OP_LOAD_MEMBASE:
1491                 case OP_LOADR4_MEMBASE:
1492                 case OP_LOADR8_MEMBASE:
1493                 case OP_ATOMIC_EXCHANGE_I4:
1494                 case OP_ATOMIC_EXCHANGE_I8:
1495                 case OP_ATOMIC_ADD_NEW_I4:
1496                 case OP_ATOMIC_ADD_NEW_I8:
1497                 case OP_ATOMIC_ADD_IMM_NEW_I4:
1498                 case OP_ATOMIC_ADD_IMM_NEW_I8:
1499                         /* There are no membase instructions on ia64 */
1500                         if (ins->inst_offset == 0) {
1501                                 break;
1502                         }
1503                         else if (ia64_is_imm14 (ins->inst_offset)) {
1504                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1505                                 temp2->sreg1 = ins->inst_basereg;
1506                                 temp2->inst_imm = ins->inst_offset;
1507                                 temp2->dreg = mono_alloc_ireg (cfg);
1508                         }
1509                         else {
1510                                 NEW_INS (cfg, temp, OP_I8CONST);
1511                                 temp->inst_c0 = ins->inst_offset;
1512                                 temp->dreg = mono_alloc_ireg (cfg);
1513                                 NEW_INS (cfg, temp2, OP_LADD);
1514                                 temp2->sreg1 = ins->inst_basereg;
1515                                 temp2->sreg2 = temp->dreg;
1516                                 temp2->dreg = mono_alloc_ireg (cfg);
1517                         }
1518
1519                         ins->inst_offset = 0;
1520                         ins->inst_basereg = temp2->dreg;
1521                         break;
1522                 case OP_ADD_IMM:
1523                 case OP_IADD_IMM:
1524                 case OP_LADD_IMM:
1525                 case OP_ISUB_IMM:
1526                 case OP_LSUB_IMM:
1527                 case OP_AND_IMM:
1528                 case OP_IAND_IMM:
1529                 case OP_LAND_IMM:
1530                 case OP_IOR_IMM:
1531                 case OP_LOR_IMM:
1532                 case OP_IXOR_IMM:
1533                 case OP_LXOR_IMM:
1534                 case OP_SHL_IMM:
1535                 case OP_SHR_IMM:
1536                 case OP_ISHL_IMM:
1537                 case OP_LSHL_IMM:
1538                 case OP_ISHR_IMM:
1539                 case OP_LSHR_IMM:
1540                 case OP_ISHR_UN_IMM:
1541                 case OP_LSHR_UN_IMM: {
1542                         gboolean is_imm = FALSE;
1543                         gboolean switched = FALSE;
1544
1545                         if (ins->opcode == OP_AND_IMM && ins->inst_imm == 255) {
1546                                 ins->opcode = OP_ZEXT_I1;
1547                                 break;
1548                         }
1549
1550                         switch (ins->opcode) {
1551                         case OP_ADD_IMM:
1552                         case OP_IADD_IMM:
1553                         case OP_LADD_IMM:
1554                                 is_imm = ia64_is_imm14 (ins->inst_imm);
1555                                 switched = TRUE;
1556                                 break;
1557                         case OP_ISUB_IMM:
1558                         case OP_LSUB_IMM:
1559                                 is_imm = ia64_is_imm14 (- (ins->inst_imm));
1560                                 if (is_imm) {
1561                                         /* A = B - IMM -> A = B + (-IMM) */
1562                                         ins->inst_imm = - ins->inst_imm;
1563                                         ins->opcode = OP_IADD_IMM;
1564                                 }
1565                                 switched = TRUE;
1566                                 break;
1567                         case OP_IAND_IMM:
1568                         case OP_IOR_IMM:
1569                         case OP_IXOR_IMM:
1570                         case OP_AND_IMM:
1571                         case OP_LAND_IMM:
1572                         case OP_LOR_IMM:
1573                         case OP_LXOR_IMM:
1574                                 is_imm = ia64_is_imm8 (ins->inst_imm);
1575                                 switched = TRUE;
1576                                 break;
1577                         case OP_SHL_IMM:
1578                         case OP_SHR_IMM:
1579                         case OP_ISHL_IMM:
1580                         case OP_LSHL_IMM:
1581                         case OP_ISHR_IMM:
1582                         case OP_LSHR_IMM:
1583                         case OP_ISHR_UN_IMM:
1584                         case OP_LSHR_UN_IMM:
1585                                 is_imm = (ins->inst_imm >= 0) && (ins->inst_imm < 64);
1586                                 break;
1587                         default:
1588                                 break;
1589                         }
1590
1591                         if (is_imm) {
1592                                 if (switched)
1593                                         ins->sreg2 = ins->sreg1;
1594                                 break;
1595                         }
1596
1597                         ins->opcode = mono_op_imm_to_op (ins->opcode);
1598
1599                         if (ins->inst_imm == 0)
1600                                 ins->sreg2 = IA64_R0;
1601                         else {
1602                                 NEW_INS (cfg, temp, OP_I8CONST);
1603                                 temp->inst_c0 = ins->inst_imm;
1604                                 temp->dreg = mono_alloc_ireg (cfg);
1605                                 ins->sreg2 = temp->dreg;
1606                         }
1607                         break;
1608                 }
1609                 case OP_COMPARE_IMM:
1610                 case OP_ICOMPARE_IMM:
1611                 case OP_LCOMPARE_IMM: {
1612                         /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1613                         gboolean imm;
1614                         CompRelation cond;
1615
1616                         next = ins->next;
1617
1618                         /* Branch opts can eliminate the branch */
1619                         if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1620                                 NULLIFY_INS (ins);
1621                                 break;
1622                         }
1623
1624                         /*
1625                          * The compare_imm instructions have switched up arguments, and
1626                          * some of them take an imm between -127 and 128.
1627                          */
1628                         next = ins->next;
1629                         cond = mono_opcode_to_cond (next->opcode);
1630                         if ((cond == CMP_LT) || (cond == CMP_GE))
1631                                 imm = ia64_is_imm8 (ins->inst_imm - 1);
1632                         else if ((cond == CMP_LT_UN) || (cond == CMP_GE_UN))
1633                                 imm = ia64_is_imm8 (ins->inst_imm - 1) && (ins->inst_imm > 0);
1634                         else
1635                                 imm = ia64_is_imm8 (ins->inst_imm);
1636
1637                         if (imm) {
1638                                 ins->opcode = opcode_to_ia64_cmp_imm (next->opcode, ins->opcode);
1639                                 ins->sreg2 = ins->sreg1;
1640                         }
1641                         else {
1642                                 ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1643
1644                                 if (ins->inst_imm == 0)
1645                                         ins->sreg2 = IA64_R0;
1646                                 else {
1647                                         NEW_INS (cfg, temp, OP_I8CONST);
1648                                         temp->inst_c0 = ins->inst_imm;
1649                                         temp->dreg = mono_alloc_ireg (cfg);
1650                                         ins->sreg2 = temp->dreg;
1651                                 }
1652                         }
1653
1654                         if (MONO_IS_COND_BRANCH_OP (next)) {
1655                                 next->opcode = OP_IA64_BR_COND;
1656                                 next->inst_target_bb = next->inst_true_bb;
1657                         } else if (MONO_IS_COND_EXC (next)) {
1658                                 next->opcode = OP_IA64_COND_EXC;
1659                         } else if (MONO_IS_SETCC (next)) {
1660                                 next->opcode = OP_IA64_CSET;
1661                         } else {
1662                                 printf ("%s\n", mono_inst_name (next->opcode));
1663                                 NOT_IMPLEMENTED;
1664                         }
1665
1666                         break;
1667                 }
1668                 case OP_COMPARE:
1669                 case OP_ICOMPARE:
1670                 case OP_LCOMPARE:
1671                 case OP_FCOMPARE: {
1672                         /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1673
1674                         next = ins->next;
1675
1676                         /* Branch opts can eliminate the branch */
1677                         if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1678                                 NULLIFY_INS (ins);
1679                                 break;
1680                         }
1681
1682                         ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1683
1684                         if (MONO_IS_COND_BRANCH_OP (next)) {
1685                                 next->opcode = OP_IA64_BR_COND;
1686                                 next->inst_target_bb = next->inst_true_bb;
1687                         } else if (MONO_IS_COND_EXC (next)) {
1688                                 next->opcode = OP_IA64_COND_EXC;
1689                         } else if (MONO_IS_SETCC (next)) {
1690                                 next->opcode = OP_IA64_CSET;
1691                         } else {
1692                                 printf ("%s\n", mono_inst_name (next->opcode));
1693                                 NOT_IMPLEMENTED;
1694                         }
1695
1696                         break;
1697                 }
1698                 case OP_FCEQ:
1699                 case OP_FCGT:
1700                 case OP_FCGT_UN:
1701                 case OP_FCLT:
1702                 case OP_FCLT_UN:
1703                         /* The front end removes the fcompare, so introduce it again */
1704                         NEW_INS (cfg, temp, opcode_to_ia64_cmp (ins->opcode, OP_FCOMPARE));
1705                         temp->sreg1 = ins->sreg1;
1706                         temp->sreg2 = ins->sreg2;
1707
1708                         ins->opcode = OP_IA64_CSET;
1709                         MONO_INST_NULLIFY_SREGS (ins);
1710                         break;
1711                 case OP_MUL_IMM:
1712                 case OP_LMUL_IMM:
1713                 case OP_IMUL_IMM: {
1714                         int i, sum_reg;
1715                         gboolean found = FALSE;
1716                         int shl_op = ins->opcode == OP_IMUL_IMM ? OP_ISHL_IMM : OP_SHL_IMM;
1717
1718                         /* First the easy cases */
1719                         if (ins->inst_imm == 1) {
1720                                 ins->opcode = OP_MOVE;
1721                                 break;
1722                         }
1723                         for (i = 1; i < 64; ++i)
1724                                 if (ins->inst_imm == (((gint64)1) << i)) {
1725                                         ins->opcode = shl_op;
1726                                         ins->inst_imm = i;
1727                                         found = TRUE;
1728                                         break;
1729                                 }
1730
1731                         /* This could be optimized */
1732                         if (!found) {
1733                                 sum_reg = 0;
1734                                 for (i = 0; i < 64; ++i) {
1735                                         if (ins->inst_imm & (((gint64)1) << i)) {
1736                                                 NEW_INS (cfg, temp, shl_op);
1737                                                 temp->dreg = mono_alloc_ireg (cfg);
1738                                                 temp->sreg1 = ins->sreg1;
1739                                                 temp->inst_imm = i;
1740
1741                                                 if (sum_reg == 0)
1742                                                         sum_reg = temp->dreg;
1743                                                 else {
1744                                                         NEW_INS (cfg, temp2, OP_LADD);
1745                                                         temp2->dreg = mono_alloc_ireg (cfg);
1746                                                         temp2->sreg1 = sum_reg;
1747                                                         temp2->sreg2 = temp->dreg;
1748                                                         sum_reg = temp2->dreg;
1749                                                 }
1750                                         }
1751                                 }
1752                                 ins->opcode = OP_MOVE;
1753                                 ins->sreg1 = sum_reg;
1754                         }
1755                         break;
1756                 }
1757                 case OP_LCONV_TO_OVF_U4:
1758                         NEW_INS (cfg, temp, OP_IA64_CMP4_LT);
1759                         temp->sreg1 = ins->sreg1;
1760                         temp->sreg2 = IA64_R0;
1761
1762                         NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1763                         temp->inst_p1 = (char*)"OverflowException";
1764
1765                         ins->opcode = OP_MOVE;
1766                         break;
1767                 case OP_LCONV_TO_OVF_I4_UN:
1768                         NEW_INS (cfg, temp, OP_ICONST);
1769                         temp->inst_c0 = 0x7fffffff;
1770                         temp->dreg = mono_alloc_ireg (cfg);
1771
1772                         NEW_INS (cfg, temp2, OP_IA64_CMP4_GT_UN);
1773                         temp2->sreg1 = ins->sreg1;
1774                         temp2->sreg2 = temp->dreg;
1775
1776                         NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1777                         temp->inst_p1 = (char*)"OverflowException";
1778
1779                         ins->opcode = OP_MOVE;
1780                         break;
1781                 case OP_FCONV_TO_I4:
1782                 case OP_FCONV_TO_I2:
1783                 case OP_FCONV_TO_U2:
1784                 case OP_FCONV_TO_I1:
1785                 case OP_FCONV_TO_U1:
1786                         NEW_INS (cfg, temp, OP_FCONV_TO_I8);
1787                         temp->sreg1 = ins->sreg1;
1788                         temp->dreg = ins->dreg;
1789
1790                         switch (ins->opcode) {
1791                         case OP_FCONV_TO_I4:
1792                                 ins->opcode = OP_SEXT_I4;
1793                                 break;
1794                         case OP_FCONV_TO_I2:
1795                                 ins->opcode = OP_SEXT_I2;
1796                                 break;
1797                         case OP_FCONV_TO_U2:
1798                                 ins->opcode = OP_ZEXT_I4;
1799                                 break;
1800                         case OP_FCONV_TO_I1:
1801                                 ins->opcode = OP_SEXT_I1;
1802                                 break;
1803                         case OP_FCONV_TO_U1:
1804                                 ins->opcode = OP_ZEXT_I1;
1805                                 break;
1806                         default:
1807                                 g_assert_not_reached ();
1808                         }
1809                         ins->sreg1 = ins->dreg;
1810                         break;
1811                 default:
1812                         break;
1813                 }
1814                 last_ins = ins;
1815                 ins = ins->next;
1816         }
1817         bb->last_ins = last_ins;
1818
1819         bb->max_vreg = cfg->next_vreg;
1820 }
1821
1822 /*
1823  * emit_load_volatile_arguments:
1824  *
1825  *  Load volatile arguments from the stack to the original input registers.
1826  * Required before a tail call.
1827  */
1828 static Ia64CodegenState
1829 emit_load_volatile_arguments (MonoCompile *cfg, Ia64CodegenState code)
1830 {
1831         MonoMethod *method = cfg->method;
1832         MonoMethodSignature *sig;
1833         MonoInst *ins;
1834         CallInfo *cinfo;
1835         guint32 i;
1836
1837         /* FIXME: Generate intermediate code instead */
1838
1839         sig = mono_method_signature (method);
1840
1841         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
1842
1843         /* This is the opposite of the code in emit_prolog */
1844         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1845                 ArgInfo *ainfo = cinfo->args + i;
1846                 gint32 stack_offset;
1847                 MonoType *arg_type;
1848
1849                 ins = cfg->args [i];
1850
1851                 if (sig->hasthis && (i == 0))
1852                         arg_type = &mono_defaults.object_class->byval_arg;
1853                 else
1854                         arg_type = sig->params [i - sig->hasthis];
1855
1856                 arg_type = mono_type_get_underlying_type (arg_type);
1857
1858                 stack_offset = ainfo->offset + ARGS_OFFSET;
1859
1860                 /* Save volatile arguments to the stack */
1861                 if (ins->opcode != OP_REGVAR) {
1862                         switch (ainfo->storage) {
1863                         case ArgInIReg:
1864                         case ArgInFloatReg:
1865                                 /* FIXME: big offsets */
1866                                 g_assert (ins->opcode == OP_REGOFFSET);
1867                                 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
1868                                 if (arg_type->byref)
1869                                         ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1870                                 else {
1871                                         switch (arg_type->type) {
1872                                         case MONO_TYPE_R4:
1873                                                 ia64_ldfs (code, ainfo->reg, GP_SCRATCH_REG);
1874                                                 break;
1875                                         case MONO_TYPE_R8:
1876                                                 ia64_ldfd (code, ainfo->reg, GP_SCRATCH_REG);
1877                                                 break;
1878                                         default:
1879                                                 ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1880                                                 break;
1881                                         }
1882                                 }
1883                                 break;
1884                         case ArgOnStack:
1885                                 break;
1886                         default:
1887                                 NOT_IMPLEMENTED;
1888                         }
1889                 }
1890
1891                 if (ins->opcode == OP_REGVAR) {
1892                         /* Argument allocated to (non-volatile) register */
1893                         switch (ainfo->storage) {
1894                         case ArgInIReg:
1895                                 if (ins->dreg != cfg->arch.reg_in0 + ainfo->reg)
1896                                         ia64_mov (code, cfg->arch.reg_in0 + ainfo->reg, ins->dreg);
1897                                 break;
1898                         case ArgOnStack:
1899                                 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
1900                                 ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
1901                                 break;
1902                         default:
1903                                 NOT_IMPLEMENTED;
1904                         }
1905                 }
1906         }
1907
1908         return code;
1909 }
1910
1911 static Ia64CodegenState
1912 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, Ia64CodegenState code)
1913 {
1914         CallInfo *cinfo;
1915         int i;
1916
1917         /* Move return value to the target register */
1918         switch (ins->opcode) {
1919         case OP_VOIDCALL:
1920         case OP_VOIDCALL_REG:
1921         case OP_VOIDCALL_MEMBASE:
1922                 break;
1923         case OP_CALL:
1924         case OP_CALL_REG:
1925         case OP_CALL_MEMBASE:
1926         case OP_LCALL:
1927         case OP_LCALL_REG:
1928         case OP_LCALL_MEMBASE:
1929                 g_assert (ins->dreg == IA64_R8);
1930                 break;
1931         case OP_FCALL:
1932         case OP_FCALL_REG:
1933         case OP_FCALL_MEMBASE:
1934                 g_assert (ins->dreg == 8);
1935                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4)
1936                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
1937                 break;
1938         case OP_VCALL:
1939         case OP_VCALL_REG:
1940         case OP_VCALL_MEMBASE:
1941         case OP_VCALL2:
1942         case OP_VCALL2_REG:
1943         case OP_VCALL2_MEMBASE: {
1944                 ArgStorage storage;
1945
1946                 cinfo = get_call_info (cfg, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
1947                 storage = cinfo->ret.storage;
1948
1949                 if (storage == ArgAggregate) {
1950                         MonoInst *local = (MonoInst*)cfg->arch.ret_var_addr_local;
1951
1952                         /* Load address of stack space allocated for the return value */
1953                         ia64_movl (code, GP_SCRATCH_REG, local->inst_offset);
1954                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, local->inst_basereg);
1955                         ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
1956
1957                         for (i = 0; i < cinfo->ret.nregs; ++i) {
1958                                 switch (cinfo->ret.atype) {
1959                                 case AggregateNormal:
1960                                         ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1961                                         break;
1962                                 case AggregateSingleHFA:
1963                                         ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 4, 0);
1964                                         break;
1965                                 case AggregateDoubleHFA:
1966                                         ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1967                                         break;
1968                                 default:
1969                                         g_assert_not_reached ();
1970                                 }
1971                         }
1972                 }
1973                 break;
1974         }
1975         default:
1976                 g_assert_not_reached ();
1977         }
1978
1979         return code;
1980 }
1981
1982 #define add_patch_info(cfg,code,patch_type,data) do { \
1983         mono_add_patch_info (cfg, code.buf + code.nins - cfg->native_code, patch_type, data); \
1984 } while (0)
1985
1986 #define emit_cond_system_exception(cfg,code,exc_name,predicate) do { \
1987         MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1988     if (tins == NULL) \
1989         add_patch_info (cfg, code, MONO_PATCH_INFO_EXC, exc_name); \
1990     else \
1991                 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, tins->inst_true_bb); \
1992         ia64_br_cond_pred (code, (predicate), 0); \
1993 } while (0)
1994
1995 static Ia64CodegenState
1996 emit_call (MonoCompile *cfg, Ia64CodegenState code, guint32 patch_type, gconstpointer data)
1997 {
1998         add_patch_info (cfg, code, patch_type, data);
1999
2000         if ((patch_type == MONO_PATCH_INFO_ABS) || (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD)) {
2001                 /* Indirect call */
2002                 /* mono_arch_patch_callsite will patch this */
2003                 /* mono_arch_nullify_class_init_trampoline will patch this */
2004                 ia64_movl (code, GP_SCRATCH_REG, 0);
2005                 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
2006                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2007                 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
2008                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2009         }
2010         else {
2011                 /* Can't use a direct call since the displacement might be too small */
2012                 /* mono_arch_patch_callsite will patch this */
2013                 ia64_movl (code, GP_SCRATCH_REG, 0);
2014                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2015                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2016         }
2017
2018         return code;
2019 }
2020
2021 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2022
2023 void
2024 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2025 {
2026         MonoInst *ins;
2027         MonoCallInst *call;
2028         guint offset;
2029         Ia64CodegenState code;
2030         guint8 *code_start = cfg->native_code + cfg->code_len;
2031         MonoInst *last_ins = NULL;
2032         guint last_offset = 0;
2033         int max_len, cpos;
2034
2035         if (cfg->opt & MONO_OPT_LOOP) {
2036                 /* FIXME: */
2037         }
2038
2039         if (cfg->verbose_level > 2)
2040                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2041
2042         cpos = bb->max_offset;
2043
2044         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2045                 NOT_IMPLEMENTED;
2046         }
2047
2048         offset = code_start - cfg->native_code;
2049
2050         ia64_codegen_init (code, code_start);
2051
2052 #if 0
2053         if (strstr (cfg->method->name, "conv_ovf_i1") && (bb->block_num == 2))
2054                 break_count ();
2055 #endif
2056
2057         MONO_BB_FOR_EACH_INS (bb, ins) {
2058                 offset = code.buf - cfg->native_code;
2059
2060                 max_len = ((int)(((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN])) + 128;
2061
2062                 while (offset + max_len + 16 > cfg->code_size) {
2063                         ia64_codegen_close (code);
2064
2065                         offset = code.buf - cfg->native_code;
2066
2067                         cfg->code_size *= 2;
2068                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2069                         code_start = cfg->native_code + offset;
2070                         cfg->stat_code_reallocs++;
2071
2072                         ia64_codegen_init (code, code_start);
2073                 }
2074
2075                 mono_debug_record_line_number (cfg, ins, offset);
2076
2077                 switch (ins->opcode) {
2078                 case OP_ICONST:
2079                 case OP_I8CONST:
2080                         if (ia64_is_imm14 (ins->inst_c0))
2081                                 ia64_adds_imm (code, ins->dreg, ins->inst_c0, IA64_R0);
2082                         else
2083                                 ia64_movl (code, ins->dreg, ins->inst_c0);
2084                         break;
2085                 case OP_JUMP_TABLE:
2086                         add_patch_info (cfg, code, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2087                         ia64_movl (code, ins->dreg, 0);
2088                         break;
2089                 case OP_MOVE:
2090                         ia64_mov (code, ins->dreg, ins->sreg1);
2091                         break;
2092                 case OP_BR:
2093                 case OP_IA64_BR_COND: {
2094                         int pred = 0;
2095                         if (ins->opcode == OP_IA64_BR_COND)
2096                                 pred = 6;
2097                         if (ins->inst_target_bb->native_offset) {
2098                                 guint8 *pos = code.buf + code.nins;
2099
2100                                 ia64_br_cond_pred (code, pred, 0);
2101                                 ia64_begin_bundle (code);
2102                                 ia64_patch (pos, cfg->native_code + ins->inst_target_bb->native_offset);
2103                         } else {
2104                                 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2105                                 ia64_br_cond_pred (code, pred, 0);
2106                         }
2107                         break;
2108                 }
2109                 case OP_LABEL:
2110                         ia64_begin_bundle (code);
2111                         ins->inst_c0 = code.buf - cfg->native_code;
2112                         break;
2113                 case OP_NOP:
2114                 case OP_RELAXED_NOP:
2115                 case OP_DUMMY_USE:
2116                 case OP_DUMMY_STORE:
2117                 case OP_NOT_REACHED:
2118                 case OP_NOT_NULL:
2119                         break;
2120                 case OP_BR_REG:
2121                         ia64_mov_to_br (code, IA64_B6, ins->sreg1);
2122                         ia64_br_cond_reg (code, IA64_B6);
2123                         break;
2124                 case OP_IADD:
2125                 case OP_LADD:
2126                         ia64_add (code, ins->dreg, ins->sreg1, ins->sreg2);
2127                         break;
2128                 case OP_ISUB:
2129                 case OP_LSUB:
2130                         ia64_sub (code, ins->dreg, ins->sreg1, ins->sreg2);
2131                         break;
2132                 case OP_IAND:
2133                 case OP_LAND:
2134                         ia64_and (code, ins->dreg, ins->sreg1, ins->sreg2);
2135                         break;
2136                 case OP_IOR:
2137                 case OP_LOR:
2138                         ia64_or (code, ins->dreg, ins->sreg1, ins->sreg2);
2139                         break;
2140                 case OP_IXOR:
2141                 case OP_LXOR:
2142                         ia64_xor (code, ins->dreg, ins->sreg1, ins->sreg2);
2143                         break;
2144                 case OP_INEG:
2145                 case OP_LNEG:
2146                         ia64_sub (code, ins->dreg, IA64_R0, ins->sreg1);
2147                         break;
2148                 case OP_INOT:
2149                 case OP_LNOT:
2150                         ia64_andcm_imm (code, ins->dreg, -1, ins->sreg1);
2151                         break;
2152                 case OP_ISHL:
2153                 case OP_LSHL:
2154                         ia64_shl (code, ins->dreg, ins->sreg1, ins->sreg2);
2155                         break;
2156                 case OP_ISHR:
2157                         ia64_sxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2158                         ia64_shr (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2159                         break;
2160                 case OP_LSHR:
2161                         ia64_shr (code, ins->dreg, ins->sreg1, ins->sreg2);
2162                         break;
2163                 case OP_ISHR_UN:
2164                         ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2165                         ia64_shr_u (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2166                         break;
2167                 case OP_LSHR_UN:
2168                         ia64_shr_u (code, ins->dreg, ins->sreg1, ins->sreg2);
2169                         break;
2170                 case OP_IADDCC:
2171                         /* p6 and p7 is set if there is signed/unsigned overflow */
2172
2173                         /* Set p8-p9 == (sreg2 > 0) */
2174                         ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2175
2176                         ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2177
2178                         /* (sreg2 > 0) && (res < ins->sreg1) => signed overflow */
2179                         ia64_cmp4_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2180                         /* (sreg2 <= 0) && (res > ins->sreg1) => signed overflow */
2181                         ia64_cmp4_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2182
2183                         /* res <u sreg1 => unsigned overflow */
2184                         ia64_cmp4_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2185
2186                         /* FIXME: Predicate this since this is a side effect */
2187                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2188                         break;
2189                 case OP_ISUBCC:
2190                         /* p6 and p7 is set if there is signed/unsigned overflow */
2191
2192                         /* Set p8-p9 == (sreg2 > 0) */
2193                         ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2194
2195                         ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2196
2197                         /* (sreg2 > 0) && (res > ins->sreg1) => signed overflow */
2198                         ia64_cmp4_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2199                         /* (sreg2 <= 0) && (res < ins->sreg1) => signed overflow */
2200                         ia64_cmp4_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2201
2202                         /* sreg1 <u sreg2 => unsigned overflow */
2203                         ia64_cmp4_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2204
2205                         /* FIXME: Predicate this since this is a side effect */
2206                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2207                         break;
2208                 case OP_ADDCC:
2209                         /* Same as OP_IADDCC */
2210                         ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2211
2212                         ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2213
2214                         ia64_cmp_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2215                         ia64_cmp_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2216
2217                         ia64_cmp_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2218
2219                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2220                         break;
2221                 case OP_SUBCC:
2222                         /* Same as OP_ISUBCC */
2223
2224                         ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2225
2226                         ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2227
2228                         ia64_cmp_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2229                         ia64_cmp_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2230
2231                         ia64_cmp_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2232
2233                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2234                         break;
2235                 case OP_ADD_IMM:
2236                 case OP_IADD_IMM:
2237                 case OP_LADD_IMM:
2238                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2239                         break;
2240                 case OP_IAND_IMM:
2241                 case OP_AND_IMM:
2242                 case OP_LAND_IMM:
2243                         ia64_and_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2244                         break;
2245                 case OP_IOR_IMM:
2246                 case OP_LOR_IMM:
2247                         ia64_or_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2248                         break;
2249                 case OP_IXOR_IMM:
2250                 case OP_LXOR_IMM:
2251                         ia64_xor_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2252                         break;
2253                 case OP_SHL_IMM:
2254                 case OP_ISHL_IMM:
2255                 case OP_LSHL_IMM:
2256                         ia64_shl_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2257                         break;
2258                 case OP_SHR_IMM:
2259                 case OP_LSHR_IMM:
2260                         ia64_shr_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2261                         break;
2262                 case OP_ISHR_IMM:
2263                         g_assert (ins->inst_imm <= 64);
2264                         ia64_extr (code, ins->dreg, ins->sreg1, ins->inst_imm, 32 - ins->inst_imm);
2265                         break;
2266                 case OP_ISHR_UN_IMM:
2267                         ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2268                         ia64_shr_u_imm (code, ins->dreg, GP_SCRATCH_REG, ins->inst_imm);
2269                         break;
2270                 case OP_LSHR_UN_IMM:
2271                         ia64_shr_u_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2272                         break;
2273                 case OP_LMUL:
2274                         /* Based on gcc code */
2275                         ia64_setf_sig (code, FP_SCRATCH_REG, ins->sreg1);
2276                         ia64_setf_sig (code, FP_SCRATCH_REG2, ins->sreg2);
2277                         ia64_xmpy_l (code, FP_SCRATCH_REG, FP_SCRATCH_REG, FP_SCRATCH_REG2);
2278                         ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2279                         break;
2280
2281                 case OP_STOREI1_MEMBASE_REG:
2282                         ia64_st1_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2283                         break;
2284                 case OP_STOREI2_MEMBASE_REG:
2285                         ia64_st2_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2286                         break;
2287                 case OP_STOREI4_MEMBASE_REG:
2288                         ia64_st4_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2289                         break;
2290                 case OP_STOREI8_MEMBASE_REG:
2291                 case OP_STORE_MEMBASE_REG:
2292                         if (ins->inst_offset != 0) {
2293                                 /* This is generated by local regalloc */
2294                                 if (ia64_is_imm14 (ins->inst_offset)) {
2295                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2296                                 } else {
2297                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2298                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2299                                 }
2300                                 ins->inst_destbasereg = GP_SCRATCH_REG;
2301                         }
2302                         ia64_st8_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2303                         break;
2304
2305                 case OP_IA64_STOREI1_MEMBASE_INC_REG:
2306                         ia64_st1_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 1, 0);
2307                         break;
2308                 case OP_IA64_STOREI2_MEMBASE_INC_REG:
2309                         ia64_st2_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 2, 0);
2310                         break;
2311                 case OP_IA64_STOREI4_MEMBASE_INC_REG:
2312                         ia64_st4_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 4, 0);
2313                         break;
2314                 case OP_IA64_STOREI8_MEMBASE_INC_REG:
2315                         ia64_st8_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 8, 0);
2316                         break;
2317
2318                 case OP_LOADU1_MEMBASE:
2319                         ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2320                         break;
2321                 case OP_LOADU2_MEMBASE:
2322                         ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2323                         break;
2324                 case OP_LOADU4_MEMBASE:
2325                         ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2326                         break;
2327                 case OP_LOADI1_MEMBASE:
2328                         ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2329                         ia64_sxt1 (code, ins->dreg, ins->dreg);
2330                         break;
2331                 case OP_LOADI2_MEMBASE:
2332                         ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2333                         ia64_sxt2 (code, ins->dreg, ins->dreg);
2334                         break;
2335                 case OP_LOADI4_MEMBASE:
2336                         ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2337                         ia64_sxt4 (code, ins->dreg, ins->dreg);
2338                         break;
2339                 case OP_LOAD_MEMBASE:
2340                 case OP_LOADI8_MEMBASE:
2341                         if (ins->inst_offset != 0) {
2342                                 /* This is generated by local regalloc */
2343                                 if (ia64_is_imm14 (ins->inst_offset)) {
2344                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2345                                 } else {
2346                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2347                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2348                                 }
2349                                 ins->inst_basereg = GP_SCRATCH_REG;
2350                         }
2351                         ia64_ld8 (code, ins->dreg, ins->inst_basereg);
2352                         break;
2353
2354                 case OP_IA64_LOADU1_MEMBASE_INC:
2355                         ia64_ld1_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 1, 0);
2356                         break;
2357                 case OP_IA64_LOADU2_MEMBASE_INC:
2358                         ia64_ld2_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 2, 0);
2359                         break;
2360                 case OP_IA64_LOADU4_MEMBASE_INC:
2361                         ia64_ld4_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 4, 0);
2362                         break;
2363                 case OP_IA64_LOADI8_MEMBASE_INC:
2364                         ia64_ld8_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 8, 0);
2365                         break;
2366
2367                 case OP_SEXT_I1:
2368                         ia64_sxt1 (code, ins->dreg, ins->sreg1);
2369                         break;
2370                 case OP_SEXT_I2:
2371                         ia64_sxt2 (code, ins->dreg, ins->sreg1);
2372                         break;
2373                 case OP_SEXT_I4:
2374                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2375                         break;
2376                 case OP_ZEXT_I1:
2377                         ia64_zxt1 (code, ins->dreg, ins->sreg1);
2378                         break;
2379                 case OP_ZEXT_I2:
2380                         ia64_zxt2 (code, ins->dreg, ins->sreg1);
2381                         break;
2382                 case OP_ZEXT_I4:
2383                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2384                         break;
2385
2386                         /* Compare opcodes */
2387                 case OP_IA64_CMP4_EQ:
2388                         ia64_cmp4_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2389                         break;
2390                 case OP_IA64_CMP4_NE:
2391                         ia64_cmp4_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2392                         break;
2393                 case OP_IA64_CMP4_LE:
2394                         ia64_cmp4_le (code, 6, 7, ins->sreg1, ins->sreg2);
2395                         break;
2396                 case OP_IA64_CMP4_LT:
2397                         ia64_cmp4_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2398                         break;
2399                 case OP_IA64_CMP4_GE:
2400                         ia64_cmp4_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2401                         break;
2402                 case OP_IA64_CMP4_GT:
2403                         ia64_cmp4_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2404                         break;
2405                 case OP_IA64_CMP4_LT_UN:
2406                         ia64_cmp4_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2407                         break;
2408                 case OP_IA64_CMP4_LE_UN:
2409                         ia64_cmp4_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2410                         break;
2411                 case OP_IA64_CMP4_GT_UN:
2412                         ia64_cmp4_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2413                         break;
2414                 case OP_IA64_CMP4_GE_UN:
2415                         ia64_cmp4_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2416                         break;
2417                 case OP_IA64_CMP_EQ:
2418                         ia64_cmp_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2419                         break;
2420                 case OP_IA64_CMP_NE:
2421                         ia64_cmp_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2422                         break;
2423                 case OP_IA64_CMP_LE:
2424                         ia64_cmp_le (code, 6, 7, ins->sreg1, ins->sreg2);
2425                         break;
2426                 case OP_IA64_CMP_LT:
2427                         ia64_cmp_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2428                         break;
2429                 case OP_IA64_CMP_GE:
2430                         ia64_cmp_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2431                         break;
2432                 case OP_IA64_CMP_GT:
2433                         ia64_cmp_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2434                         break;
2435                 case OP_IA64_CMP_GT_UN:
2436                         ia64_cmp_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2437                         break;
2438                 case OP_IA64_CMP_LT_UN:
2439                         ia64_cmp_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2440                         break;
2441                 case OP_IA64_CMP_GE_UN:
2442                         ia64_cmp_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2443                         break;
2444                 case OP_IA64_CMP_LE_UN:
2445                         ia64_cmp_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2446                         break;
2447                 case OP_IA64_CMP4_EQ_IMM:
2448                         ia64_cmp4_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2449                         break;
2450                 case OP_IA64_CMP4_NE_IMM:
2451                         ia64_cmp4_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2452                         break;
2453                 case OP_IA64_CMP4_LE_IMM:
2454                         ia64_cmp4_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2455                         break;
2456                 case OP_IA64_CMP4_LT_IMM:
2457                         ia64_cmp4_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2458                         break;
2459                 case OP_IA64_CMP4_GE_IMM:
2460                         ia64_cmp4_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2461                         break;
2462                 case OP_IA64_CMP4_GT_IMM:
2463                         ia64_cmp4_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2464                         break;
2465                 case OP_IA64_CMP4_LT_UN_IMM:
2466                         ia64_cmp4_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2467                         break;
2468                 case OP_IA64_CMP4_LE_UN_IMM:
2469                         ia64_cmp4_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2470                         break;
2471                 case OP_IA64_CMP4_GT_UN_IMM:
2472                         ia64_cmp4_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2473                         break;
2474                 case OP_IA64_CMP4_GE_UN_IMM:
2475                         ia64_cmp4_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2476                         break;
2477                 case OP_IA64_CMP_EQ_IMM:
2478                         ia64_cmp_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2479                         break;
2480                 case OP_IA64_CMP_NE_IMM:
2481                         ia64_cmp_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2482                         break;
2483                 case OP_IA64_CMP_LE_IMM:
2484                         ia64_cmp_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2485                         break;
2486                 case OP_IA64_CMP_LT_IMM:
2487                         ia64_cmp_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2488                         break;
2489                 case OP_IA64_CMP_GE_IMM:
2490                         ia64_cmp_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2491                         break;
2492                 case OP_IA64_CMP_GT_IMM:
2493                         ia64_cmp_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2494                         break;
2495                 case OP_IA64_CMP_GT_UN_IMM:
2496                         ia64_cmp_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2497                         break;
2498                 case OP_IA64_CMP_LT_UN_IMM:
2499                         ia64_cmp_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2500                         break;
2501                 case OP_IA64_CMP_GE_UN_IMM:
2502                         ia64_cmp_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2503                         break;
2504                 case OP_IA64_CMP_LE_UN_IMM:
2505                         ia64_cmp_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2506                         break;
2507                 case OP_IA64_FCMP_EQ:
2508                         ia64_fcmp_eq_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2509                         break;
2510                 case OP_IA64_FCMP_NE:
2511                         ia64_fcmp_ne_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2512                         break;
2513                 case OP_IA64_FCMP_LT:
2514                         ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2515                         break;
2516                 case OP_IA64_FCMP_GT:
2517                         ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2518                         break;
2519                 case OP_IA64_FCMP_LE:
2520                         ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2521                         break;
2522                 case OP_IA64_FCMP_GE:
2523                         ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2524                         break;
2525                 case OP_IA64_FCMP_GT_UN:
2526                         ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2527                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2528                         break;
2529                 case OP_IA64_FCMP_LT_UN:
2530                         ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2531                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2532                         break;
2533                 case OP_IA64_FCMP_GE_UN:
2534                         ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2535                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2536                         break;
2537                 case OP_IA64_FCMP_LE_UN:
2538                         ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2539                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2540                         break;
2541
2542                 case OP_COND_EXC_IOV:
2543                 case OP_COND_EXC_OV:
2544                         emit_cond_system_exception (cfg, code, "OverflowException", 6);
2545                         break;
2546                 case OP_COND_EXC_IC:
2547                 case OP_COND_EXC_C:
2548                         emit_cond_system_exception (cfg, code, "OverflowException", 7);
2549                         break;
2550                 case OP_IA64_COND_EXC:
2551                         emit_cond_system_exception (cfg, code, ins->inst_p1, 6);
2552                         break;
2553                 case OP_IA64_CSET:
2554                         ia64_mov_pred (code, 7, ins->dreg, IA64_R0);
2555                         ia64_no_stop (code);
2556                         ia64_add1_pred (code, 6, ins->dreg, IA64_R0, IA64_R0);
2557                         break;
2558                 case OP_ICONV_TO_I1:
2559                 case OP_LCONV_TO_I1:
2560                         /* FIXME: Is this needed ? */
2561                         ia64_sxt1 (code, ins->dreg, ins->sreg1);
2562                         break;
2563                 case OP_ICONV_TO_I2:
2564                 case OP_LCONV_TO_I2:
2565                         /* FIXME: Is this needed ? */
2566                         ia64_sxt2 (code, ins->dreg, ins->sreg1);
2567                         break;
2568                 case OP_LCONV_TO_I4:
2569                         /* FIXME: Is this needed ? */
2570                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2571                         break;
2572                 case OP_ICONV_TO_U1:
2573                 case OP_LCONV_TO_U1:
2574                         /* FIXME: Is this needed */
2575                         ia64_zxt1 (code, ins->dreg, ins->sreg1);
2576                         break;
2577                 case OP_ICONV_TO_U2:
2578                 case OP_LCONV_TO_U2:
2579                         /* FIXME: Is this needed */
2580                         ia64_zxt2 (code, ins->dreg, ins->sreg1);
2581                         break;
2582                 case OP_LCONV_TO_U4:
2583                         /* FIXME: Is this needed */
2584                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2585                         break;
2586                 case OP_ICONV_TO_I8:
2587                 case OP_ICONV_TO_I:
2588                 case OP_LCONV_TO_I8:
2589                 case OP_LCONV_TO_I:
2590                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2591                         break;
2592                 case OP_LCONV_TO_U8:
2593                 case OP_LCONV_TO_U:
2594                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2595                         break;
2596
2597                         /*
2598                          * FLOAT OPCODES
2599                          */
2600                 case OP_R8CONST: {
2601                         double d = *(double *)ins->inst_p0;
2602
2603                         if ((d == 0.0) && (mono_signbit (d) == 0))
2604                                 ia64_fmov (code, ins->dreg, 0);
2605                         else if (d == 1.0)
2606                                 ia64_fmov (code, ins->dreg, 1);
2607                         else {
2608                                 add_patch_info (cfg, code, MONO_PATCH_INFO_R8, ins->inst_p0);
2609                                 ia64_movl (code, GP_SCRATCH_REG, 0);
2610                                 ia64_ldfd (code, ins->dreg, GP_SCRATCH_REG);
2611                         }
2612                         break;
2613                 }
2614                 case OP_R4CONST: {
2615                         float f = *(float *)ins->inst_p0;
2616
2617                         if ((f == 0.0) && (mono_signbit (f) == 0))
2618                                 ia64_fmov (code, ins->dreg, 0);
2619                         else if (f == 1.0)
2620                                 ia64_fmov (code, ins->dreg, 1);
2621                         else {
2622                                 add_patch_info (cfg, code, MONO_PATCH_INFO_R4, ins->inst_p0);
2623                                 ia64_movl (code, GP_SCRATCH_REG, 0);
2624                                 ia64_ldfs (code, ins->dreg, GP_SCRATCH_REG);
2625                         }
2626                         break;
2627                 }
2628                 case OP_FMOVE:
2629                         ia64_fmov (code, ins->dreg, ins->sreg1);
2630                         break;
2631                 case OP_STORER8_MEMBASE_REG:
2632                         if (ins->inst_offset != 0) {
2633                                 /* This is generated by local regalloc */
2634                                 if (ia64_is_imm14 (ins->inst_offset)) {
2635                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2636                                 } else {
2637                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2638                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2639                                 }
2640                                 ins->inst_destbasereg = GP_SCRATCH_REG;
2641                         }
2642                         ia64_stfd_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2643                         break;
2644                 case OP_STORER4_MEMBASE_REG:
2645                         ia64_fnorm_s_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2646                         ia64_stfs_hint (code, ins->inst_destbasereg, FP_SCRATCH_REG, 0);
2647                         break;
2648                 case OP_LOADR8_MEMBASE:
2649                         if (ins->inst_offset != 0) {
2650                                 /* This is generated by local regalloc */
2651                                 if (ia64_is_imm14 (ins->inst_offset)) {
2652                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2653                                 } else {
2654                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2655                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2656                                 }
2657                                 ins->inst_basereg = GP_SCRATCH_REG;
2658                         }
2659                         ia64_ldfd (code, ins->dreg, ins->inst_basereg);
2660                         break;
2661                 case OP_LOADR4_MEMBASE:
2662                         ia64_ldfs (code, ins->dreg, ins->inst_basereg);
2663                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2664                         break;
2665                 case OP_ICONV_TO_R4:
2666                 case OP_LCONV_TO_R4:
2667                         ia64_setf_sig (code, ins->dreg, ins->sreg1);
2668                         ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2669                         ia64_fnorm_s_sf (code, ins->dreg, ins->dreg, 0);
2670                         break;
2671                 case OP_ICONV_TO_R8:
2672                 case OP_LCONV_TO_R8:
2673                         ia64_setf_sig (code, ins->dreg, ins->sreg1);
2674                         ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2675                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2676                         break;
2677                 case OP_FCONV_TO_R4:
2678                         ia64_fnorm_s_sf (code, ins->dreg, ins->sreg1, 0);
2679                         break;
2680                 case OP_FCONV_TO_I8:
2681                 case OP_FCONV_TO_I:
2682                         ia64_fcvt_fx_trunc_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2683                         ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2684                         break;
2685                 case OP_FADD:
2686                         ia64_fma_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2687                         break;
2688                 case OP_FSUB:
2689                         ia64_fms_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2690                         break;
2691                 case OP_FMUL:
2692                         ia64_fma_d_sf (code, ins->dreg, ins->sreg1, ins->sreg2, 0, 0);
2693                         break;
2694                 case OP_FNEG:
2695                         ia64_fmerge_ns (code, ins->dreg, ins->sreg1, ins->sreg1);
2696                         break;
2697                 case OP_CKFINITE:
2698                         /* Quiet NaN */
2699                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x080);
2700                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2701                         /* Signaling NaN */
2702                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x040);
2703                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2704                         /* Positive infinity */
2705                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x021);
2706                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2707                         /* Negative infinity */
2708                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x022);
2709                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2710                         break;
2711
2712                 /* Calls */
2713                 case OP_CHECK_THIS:
2714                         /* ensure ins->sreg1 is not NULL */
2715                         /* Can't use ld8 as this could be a vtype address */
2716                         ia64_ld1 (code, GP_SCRATCH_REG, ins->sreg1);
2717                         break;
2718                 case OP_ARGLIST:
2719                         ia64_adds_imm (code, GP_SCRATCH_REG, cfg->sig_cookie, cfg->frame_reg);
2720                         ia64_st8 (code, ins->sreg1, GP_SCRATCH_REG);
2721                         break;
2722                 case OP_FCALL:
2723                 case OP_LCALL:
2724                 case OP_VCALL:
2725                 case OP_VCALL2:
2726                 case OP_VOIDCALL:
2727                 case OP_CALL:
2728                         call = (MonoCallInst*)ins;
2729
2730                         if (ins->flags & MONO_INST_HAS_METHOD)
2731                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2732                         else
2733                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2734
2735                         code = emit_move_return_value (cfg, ins, code);
2736                         break;
2737
2738                 case OP_CALL_REG:
2739                 case OP_FCALL_REG:
2740                 case OP_LCALL_REG:
2741                 case OP_VCALL_REG:
2742                 case OP_VCALL2_REG:
2743                 case OP_VOIDCALL_REG: {
2744                         MonoCallInst *call = (MonoCallInst*)ins;
2745                         CallInfo *cinfo;
2746                         int out_reg;
2747
2748                         /*
2749                          * mono_arch_get_this_arg_from_call () needs to find the this argument in a global
2750                          * register.
2751                          */
2752                         cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2753                         out_reg = cfg->arch.reg_out0;
2754                         ia64_mov (code, IA64_R10, out_reg);
2755
2756                         /* Indirect call */
2757                         ia64_mov (code, IA64_R8, ins->sreg1);
2758                         ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, IA64_R8, 8);
2759                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2760                         ia64_ld8 (code, IA64_GP, IA64_R8);
2761                         ia64_br_call_reg (code, IA64_B0, IA64_B6);
2762
2763                         code = emit_move_return_value (cfg, ins, code);
2764                         break;
2765                 }
2766                 case OP_FCALL_MEMBASE:
2767                 case OP_LCALL_MEMBASE:
2768                 case OP_VCALL_MEMBASE:
2769                 case OP_VCALL2_MEMBASE:
2770                 case OP_VOIDCALL_MEMBASE:
2771                 case OP_CALL_MEMBASE: {
2772                         MonoCallInst *call = (MonoCallInst*)ins;
2773                         CallInfo *cinfo;
2774                         int out_reg;
2775
2776                         ia64_mov (code, IA64_R11, ins->sreg1);
2777                         if (ia64_is_imm14 (ins->inst_offset))
2778                                 ia64_adds_imm (code, IA64_R8, ins->inst_offset, ins->sreg1);
2779                         else {
2780                                 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2781                                 ia64_add (code, IA64_R8, GP_SCRATCH_REG, ins->sreg1);
2782                         }
2783
2784                         if (call->method && ins->inst_offset < 0) {
2785                                 /*
2786                                  * This is a possible IMT call so save the IMT method in a global
2787                                  * register where mono_arch_find_imt_method () and its friends can
2788                                  * access it.
2789                                  */
2790                                 ia64_movl (code, IA64_R9, call->method);
2791                         }
2792
2793                         /*
2794                          * mono_arch_find_this_arg () needs to find the this argument in a global
2795                          * register.
2796                          */
2797                         cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2798                         out_reg = cfg->arch.reg_out0;
2799                         ia64_mov (code, IA64_R10, out_reg);
2800
2801                         ia64_ld8 (code, GP_SCRATCH_REG, IA64_R8);
2802
2803                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2804
2805                         ia64_br_call_reg (code, IA64_B0, IA64_B6);
2806
2807                         code = emit_move_return_value (cfg, ins, code);
2808                         break;
2809                 }
2810                 case OP_JMP: {
2811                         /*
2812                          * Keep in sync with the code in emit_epilog.
2813                          */
2814
2815                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2816                                 NOT_IMPLEMENTED;
2817
2818                         g_assert (!cfg->method->save_lmf);
2819
2820                         /* Load arguments into their original registers */
2821                         code = emit_load_volatile_arguments (cfg, code);
2822
2823                         if (cfg->arch.stack_alloc_size) {
2824                                 if (cfg->arch.omit_fp) {
2825                                         if (ia64_is_imm14 (cfg->arch.stack_alloc_size))
2826                                                 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
2827                                         else {
2828                                                 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
2829                                                 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
2830                                         }
2831                                 }
2832                                 else
2833                                         ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
2834                         }
2835                         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
2836                         ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
2837
2838                         add_patch_info (cfg, code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2839                         ia64_movl (code, GP_SCRATCH_REG, 0);
2840                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2841                         ia64_br_cond_reg (code, IA64_B6);
2842
2843                         break;
2844                 }
2845                 case OP_BREAK:
2846                         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, mono_break);
2847                         break;
2848
2849                 case OP_LOCALLOC: {
2850                         gint32 abi_offset;
2851
2852                         /* FIXME: Sigaltstack support */
2853
2854                         /* keep alignment */
2855                         ia64_adds_imm (code, GP_SCRATCH_REG, MONO_ARCH_LOCALLOC_ALIGNMENT - 1, ins->sreg1);
2856                         ia64_movl (code, GP_SCRATCH_REG2, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
2857                         ia64_and (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2858
2859                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2860
2861                         ia64_mov (code, ins->dreg, IA64_SP);
2862
2863                         /* An area at sp is reserved by the ABI for parameter passing */
2864                         abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_LOCALLOC_ALIGNMENT);
2865                         if (ia64_is_adds_imm (abi_offset))
2866                                 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2867                         else {
2868                                 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2869                                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2870                         }
2871
2872                         if (ins->flags & MONO_INST_INIT) {
2873                                 /* Upper limit */
2874                                 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2875
2876                                 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2877
2878                                 /* Init loop */
2879                                 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2880                                 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2881                                 ia64_br_cond_pred (code, 8, -2);
2882
2883                                 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2884
2885                                 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2886                         }
2887
2888                         break;
2889                 }
2890                 case OP_LOCALLOC_IMM: {
2891                         gint32 abi_offset;
2892
2893                         /* FIXME: Sigaltstack support */
2894
2895                         gssize size = ins->inst_imm;
2896                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
2897
2898                         if (ia64_is_adds_imm (size))
2899                                 ia64_adds_imm (code, GP_SCRATCH_REG, size, IA64_R0);
2900                         else
2901                                 ia64_movl (code, GP_SCRATCH_REG, size);
2902
2903                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2904                         ia64_mov (code, ins->dreg, IA64_SP);
2905
2906                         /* An area at sp is reserved by the ABI for parameter passing */
2907                         abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_FRAME_ALIGNMENT);
2908                         if (ia64_is_adds_imm (abi_offset))
2909                                 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2910                         else {
2911                                 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2912                                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2913                         }
2914
2915                         if (ins->flags & MONO_INST_INIT) {
2916                                 /* Upper limit */
2917                                 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2918
2919                                 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2920
2921                                 /* Init loop */
2922                                 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2923                                 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2924                                 ia64_br_cond_pred (code, 8, -2);
2925
2926                                 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2927
2928                                 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2929                         }
2930
2931                         break;
2932                 }
2933                 case OP_TLS_GET:
2934                         ia64_adds_imm (code, ins->dreg, ins->inst_offset, IA64_TP);
2935                         ia64_ld8 (code, ins->dreg, ins->dreg);
2936                         break;
2937
2938                         /* Synchronization */
2939                 case OP_MEMORY_BARRIER:
2940                         ia64_mf (code);
2941                         break;
2942                 case OP_ATOMIC_ADD_IMM_NEW_I4:
2943                         g_assert (ins->inst_offset == 0);
2944                         ia64_fetchadd4_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2945                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2946                         break;
2947                 case OP_ATOMIC_ADD_IMM_NEW_I8:
2948                         g_assert (ins->inst_offset == 0);
2949                         ia64_fetchadd8_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2950                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2951                         break;
2952                 case OP_ATOMIC_EXCHANGE_I4:
2953                         ia64_xchg4_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2954                         ia64_sxt4 (code, ins->dreg, ins->dreg);
2955                         break;
2956                 case OP_ATOMIC_EXCHANGE_I8:
2957                         ia64_xchg8_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2958                         break;
2959                 case OP_ATOMIC_ADD_NEW_I4: {
2960                         guint8 *label, *buf;
2961
2962                         /* From libatomic_ops */
2963                         ia64_mf (code);
2964
2965                         ia64_begin_bundle (code);
2966                         label = code.buf + code.nins;
2967                         ia64_ld4_acq (code, GP_SCRATCH_REG, ins->sreg1);
2968                         ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2969                         ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2970                         ia64_cmpxchg4_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2971                         ia64_cmp4_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2972                         buf = code.buf + code.nins;
2973                         ia64_br_cond_pred (code, 7, 0);
2974                         ia64_begin_bundle (code);
2975                         ia64_patch (buf, label);
2976                         ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2977                         break;
2978                 }
2979                 case OP_ATOMIC_ADD_NEW_I8: {
2980                         guint8 *label, *buf;
2981
2982                         /* From libatomic_ops */
2983                         ia64_mf (code);
2984
2985                         ia64_begin_bundle (code);
2986                         label = code.buf + code.nins;
2987                         ia64_ld8_acq (code, GP_SCRATCH_REG, ins->sreg1);
2988                         ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2989                         ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2990                         ia64_cmpxchg8_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2991                         ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2992                         buf = code.buf + code.nins;
2993                         ia64_br_cond_pred (code, 7, 0);
2994                         ia64_begin_bundle (code);
2995                         ia64_patch (buf, label);
2996                         ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2997                         break;
2998                 }
2999
3000                         /* Exception handling */
3001                 case OP_CALL_HANDLER:
3002                         /*
3003                          * Using a call instruction would mess up the register stack, so
3004                          * save the return address to a register and use a
3005                          * branch.
3006                          */
3007                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3008                         ia64_mov (code, IA64_R15, IA64_R0);
3009                         ia64_mov_from_ip (code, GP_SCRATCH_REG);
3010                         /* Add the length of OP_CALL_HANDLER */
3011                         ia64_adds_imm (code, GP_SCRATCH_REG, 5 * 16, GP_SCRATCH_REG);
3012                         add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3013                         ia64_movl (code, GP_SCRATCH_REG2, 0);
3014                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
3015                         ia64_br_cond_reg (code, IA64_B6);
3016                         // FIXME:
3017                         //mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3018                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3019                         break;
3020                 case OP_START_HANDLER: {
3021                         /*
3022                          * We receive the return address in GP_SCRATCH_REG.
3023                          */
3024                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3025
3026                         /*
3027                          * R15 determines our caller. It is used since it is writable using
3028                          * libunwind.
3029                          * R15 == 0 means we are called by OP_CALL_HANDLER or via resume_context ()
3030                          * R15 != 0 means we are called by call_filter ().
3031                          */
3032                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3033                         ia64_cmp_eq (code, 6, 7, IA64_R15, IA64_R0);
3034
3035                         ia64_br_cond_pred (code, 6, 6);
3036
3037                         /*
3038                          * Called by call_filter:
3039                          * Allocate a new stack frame, and set the fp register from the
3040                          * value passed in by the caller.
3041                          * We allocate a similar frame as is done by the prolog, so
3042                          * if an exception is thrown while executing the filter, the
3043                          * unwinder can unwind through the filter frame using the unwind
3044                          * info for the prolog.
3045                          */
3046                         ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3047                         ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3048                         ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3049                         ia64_mov (code, cfg->frame_reg, IA64_R15);
3050                         /* Signal to endfilter that we are called by call_filter */
3051                         ia64_mov (code, GP_SCRATCH_REG, IA64_R0);
3052
3053                         /* Branch target: */
3054                         if (ia64_is_imm14 (spvar->inst_offset))
3055                                 ia64_adds_imm (code, GP_SCRATCH_REG2, spvar->inst_offset, cfg->frame_reg);
3056                         else {
3057                                 ia64_movl (code, GP_SCRATCH_REG2, spvar->inst_offset);
3058                                 ia64_add (code, GP_SCRATCH_REG2, cfg->frame_reg, GP_SCRATCH_REG2);
3059                         }
3060
3061                         /* Save the return address */
3062                         ia64_st8_hint (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 0);
3063                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3064
3065                         break;
3066                 }
3067                 case OP_ENDFINALLY:
3068                 case OP_ENDFILTER: {
3069                         /* FIXME: Return the value in ENDFILTER */
3070                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3071
3072                         /* Load the return address */
3073                         if (ia64_is_imm14 (spvar->inst_offset)) {
3074                                 ia64_adds_imm (code, GP_SCRATCH_REG, spvar->inst_offset, cfg->frame_reg);
3075                         } else {
3076                                 ia64_movl (code, GP_SCRATCH_REG, spvar->inst_offset);
3077                                 ia64_add (code, GP_SCRATCH_REG, cfg->frame_reg, GP_SCRATCH_REG);
3078                         }
3079                         ia64_ld8_hint (code, GP_SCRATCH_REG, GP_SCRATCH_REG, 0);
3080
3081                         /* Test caller */
3082                         ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, IA64_R0);
3083                         ia64_br_cond_pred (code, 7, 4);
3084
3085                         /* Called by call_filter */
3086                         /* Pop frame */
3087                         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
3088                         ia64_mov_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
3089                         ia64_br_ret_reg (code, IA64_B0);
3090
3091                         /* Called by CALL_HANDLER */
3092                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
3093                         ia64_br_cond_reg (code, IA64_B6);
3094                         break;
3095                 }
3096                 case OP_THROW:
3097                         ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3098                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3099                                                           (gpointer)"mono_arch_throw_exception");
3100
3101                         /*
3102                          * This might be the last instruction in the method, so add a dummy
3103                          * instruction so the unwinder will work.
3104                          */
3105                         ia64_break_i (code, 0);
3106                         break;
3107                 case OP_RETHROW:
3108                         ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3109                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3110                                                           (gpointer)"mono_arch_rethrow_exception");
3111
3112                         ia64_break_i (code, 0);
3113                         break;
3114
3115                 default:
3116                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3117                         g_assert_not_reached ();
3118                 }
3119
3120                 if ((code.buf - cfg->native_code - offset) > max_len) {
3121                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3122                                    mono_inst_name (ins->opcode), max_len, code.buf - cfg->native_code - offset);
3123                         g_assert_not_reached ();
3124                 }
3125
3126                 cpos += max_len;
3127
3128                 last_ins = ins;
3129                 last_offset = offset;
3130         }
3131
3132         ia64_codegen_close (code);
3133
3134         cfg->code_len = code.buf - cfg->native_code;
3135 }
3136
3137 void
3138 mono_arch_register_lowlevel_calls (void)
3139 {
3140 }
3141
3142 static Ia64InsType ins_types_in_template [32][3] = {
3143         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3144         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3145         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3146         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3147         {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3148         {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3149         {0, 0, 0},
3150         {0, 0, 0},
3151         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3152         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3153         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3154         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3155         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3156         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3157         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3158         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3159         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3160         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3161         {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3162         {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3163         {0, 0, 0},
3164         {0, 0, 0},
3165         {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3166         {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3167         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3168         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3169         {0, 0, 0},
3170         {0, 0, 0},
3171         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3172         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3173         {0, 0, 0},
3174         {0, 0, 0}
3175 };
3176
3177 static gboolean stops_in_template [32][3] = {
3178         { FALSE, FALSE, FALSE },
3179         { FALSE, FALSE, TRUE },
3180         { FALSE, TRUE, FALSE },
3181         { FALSE, TRUE, TRUE },
3182         { FALSE, FALSE, FALSE },
3183         { FALSE, FALSE, TRUE },
3184         { FALSE, FALSE, FALSE },
3185         { FALSE, FALSE, FALSE },
3186
3187         { FALSE, FALSE, FALSE },
3188         { FALSE, FALSE, TRUE },
3189         { TRUE, FALSE, FALSE },
3190         { TRUE, FALSE, TRUE },
3191         { FALSE, FALSE, FALSE },
3192         { FALSE, FALSE, TRUE },
3193         { FALSE, FALSE, FALSE },
3194         { FALSE, FALSE, TRUE },
3195
3196         { FALSE, FALSE, FALSE },
3197         { FALSE, FALSE, TRUE },
3198         { FALSE, FALSE, FALSE },
3199         { FALSE, FALSE, TRUE },
3200         { FALSE, FALSE, FALSE },
3201         { FALSE, FALSE, FALSE },
3202         { FALSE, FALSE, FALSE },
3203         { FALSE, FALSE, TRUE },
3204
3205         { FALSE, FALSE, FALSE },
3206         { FALSE, FALSE, TRUE },
3207         { FALSE, FALSE, FALSE },
3208         { FALSE, FALSE, FALSE },
3209         { FALSE, FALSE, FALSE },
3210         { FALSE, FALSE, TRUE },
3211         { FALSE, FALSE, FALSE },
3212         { FALSE, FALSE, FALSE }
3213 };
3214
3215 static int last_stop_in_template [32] = {
3216         -1, 2, 1, 2, -1, 2, -1, -1,
3217         -1, 2, 0, 2, -1, 2, -1, 2,
3218         -1, 2, -1, 2, -1, -1, -1, 2,
3219         -1, 2, -1, -1, -1, 2, -1, -1
3220 };
3221
3222 static guint64 nops_for_ins_types [6] = {
3223         IA64_NOP_I,
3224         IA64_NOP_I,
3225         IA64_NOP_M,
3226         IA64_NOP_F,
3227         IA64_NOP_B,
3228         IA64_NOP_X
3229 };
3230
3231 #define ITYPE_MATCH(itype1, itype2) (((itype1) == (itype2)) || (((itype2) == IA64_INS_TYPE_A) && (((itype1) == IA64_INS_TYPE_I) || ((itype1) == IA64_INS_TYPE_M))))
3232
3233 /*
3234  * Debugging support
3235  */
3236
3237 #if 0
3238 #define DEBUG_INS_SCHED(a) do { a; } while (0)
3239 #else
3240 #define DEBUG_INS_SCHED(a)
3241 #endif
3242
3243 static void
3244 ia64_analyze_deps (Ia64CodegenState *code, int *deps_start, int *stops)
3245 {
3246         int i, pos, ins_index, current_deps_start, current_ins_start, reg;
3247         guint8 *deps = code->dep_info;
3248         gboolean need_stop, no_stop;
3249
3250         for (i = 0; i < code->nins; ++i)
3251                 stops [i] = FALSE;
3252
3253         ins_index = 0;
3254         current_deps_start = 0;
3255         current_ins_start = 0;
3256         deps_start [ins_index] = current_ins_start;
3257         pos = 0;
3258         no_stop = FALSE;
3259         DEBUG_INS_SCHED (printf ("BEGIN.\n"));
3260         while (pos < code->dep_info_pos) {
3261                 need_stop = FALSE;
3262                 switch (deps [pos]) {
3263                 case IA64_END_OF_INS:
3264                         ins_index ++;
3265                         current_ins_start = pos + 2;
3266                         deps_start [ins_index] = current_ins_start;
3267                         no_stop = FALSE;
3268                         DEBUG_INS_SCHED (printf ("(%d) END INS.\n", ins_index - 1));
3269                         break;
3270                 case IA64_NONE:
3271                         break;
3272                 case IA64_READ_GR:
3273                         reg = deps [pos + 1];
3274
3275                         DEBUG_INS_SCHED (printf ("READ GR: %d\n", reg));
3276                         for (i = current_deps_start; i < current_ins_start; i += 2)
3277                                 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3278                                         need_stop = TRUE;
3279                         break;
3280                 case IA64_WRITE_GR:
3281                         reg = code->dep_info [pos + 1];
3282
3283                         DEBUG_INS_SCHED (printf ("WRITE GR: %d\n", reg));
3284                         for (i = current_deps_start; i < current_ins_start; i += 2)
3285                                 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3286                                         need_stop = TRUE;
3287                         break;
3288                 case IA64_READ_PR:
3289                         reg = deps [pos + 1];
3290
3291                         DEBUG_INS_SCHED (printf ("READ PR: %d\n", reg));
3292                         for (i = current_deps_start; i < current_ins_start; i += 2)
3293                                 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3294                                         need_stop = TRUE;
3295                         break;
3296                 case IA64_READ_PR_BRANCH:
3297                         reg = deps [pos + 1];
3298
3299                         /* Writes to prs by non-float instructions are visible to branches */
3300                         DEBUG_INS_SCHED (printf ("READ PR BRANCH: %d\n", reg));
3301                         for (i = current_deps_start; i < current_ins_start; i += 2)
3302                                 if (deps [i] == IA64_WRITE_PR_FLOAT && deps [i + 1] == reg)
3303                                         need_stop = TRUE;
3304                         break;
3305                 case IA64_WRITE_PR:
3306                         reg = code->dep_info [pos + 1];
3307
3308                         DEBUG_INS_SCHED (printf ("WRITE PR: %d\n", reg));
3309                         for (i = current_deps_start; i < current_ins_start; i += 2)
3310                                 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3311                                         need_stop = TRUE;
3312                         break;
3313                 case IA64_WRITE_PR_FLOAT:
3314                         reg = code->dep_info [pos + 1];
3315
3316                         DEBUG_INS_SCHED (printf ("WRITE PR FP: %d\n", reg));
3317                         for (i = current_deps_start; i < current_ins_start; i += 2)
3318                                 if (((deps [i] == IA64_WRITE_GR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3319                                         need_stop = TRUE;
3320                         break;
3321                 case IA64_READ_BR:
3322                         reg = deps [pos + 1];
3323
3324                         DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3325                         for (i = current_deps_start; i < current_ins_start; i += 2)
3326                                 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3327                                         need_stop = TRUE;
3328                         break;
3329                 case IA64_WRITE_BR:
3330                         reg = code->dep_info [pos + 1];
3331
3332                         DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3333                         for (i = current_deps_start; i < current_ins_start; i += 2)
3334                                 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3335                                         need_stop = TRUE;
3336                         break;
3337                 case IA64_READ_BR_BRANCH:
3338                         reg = deps [pos + 1];
3339
3340                         /* Writes to brs are visible to branches */
3341                         DEBUG_INS_SCHED (printf ("READ BR BRACH: %d\n", reg));
3342                         break;
3343                 case IA64_READ_FR:
3344                         reg = deps [pos + 1];
3345
3346                         DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3347                         for (i = current_deps_start; i < current_ins_start; i += 2)
3348                                 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3349                                         need_stop = TRUE;
3350                         break;
3351                 case IA64_WRITE_FR:
3352                         reg = code->dep_info [pos + 1];
3353
3354                         DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3355                         for (i = current_deps_start; i < current_ins_start; i += 2)
3356                                 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3357                                         need_stop = TRUE;
3358                         break;
3359                 case IA64_READ_AR:
3360                         reg = deps [pos + 1];
3361
3362                         DEBUG_INS_SCHED (printf ("READ AR: %d\n", reg));
3363                         for (i = current_deps_start; i < current_ins_start; i += 2)
3364                                 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3365                                         need_stop = TRUE;
3366                         break;
3367                 case IA64_WRITE_AR:
3368                         reg = code->dep_info [pos + 1];
3369
3370                         DEBUG_INS_SCHED (printf ("WRITE AR: %d\n", reg));
3371                         for (i = current_deps_start; i < current_ins_start; i += 2)
3372                                 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3373                                         need_stop = TRUE;
3374                         break;
3375                 case IA64_NO_STOP:
3376                         /*
3377                          * Explicitly indicate that a stop is not required. Useful for
3378                          * example when two predicated instructions with negated predicates
3379                          * write the same registers.
3380                          */
3381                         no_stop = TRUE;
3382                         break;
3383                 default:
3384                         g_assert_not_reached ();
3385                 }
3386                 pos += 2;
3387
3388                 if (need_stop && !no_stop) {
3389                         g_assert (ins_index > 0);
3390                         stops [ins_index - 1] = 1;
3391
3392                         DEBUG_INS_SCHED (printf ("STOP\n"));
3393                         current_deps_start = current_ins_start;
3394
3395                         /* Skip remaining deps for this instruction */
3396                         while (deps [pos] != IA64_END_OF_INS)
3397                                 pos += 2;
3398                 }
3399         }
3400
3401         if (code->nins > 0) {
3402                 /* No dependency info for the last instruction */
3403                 stops [code->nins - 1] = 1;
3404         }
3405
3406         deps_start [code->nins] = code->dep_info_pos;
3407 }
3408
3409 static void
3410 ia64_real_emit_bundle (Ia64CodegenState *code, int *deps_start, int *stops, int n, guint64 template, guint64 ins1, guint64 ins2, guint64 ins3, guint8 nops)
3411 {
3412         int stop_pos, i, deps_to_shift, dep_shift;
3413
3414         g_assert (n <= code->nins);
3415
3416         // if (n > 1) printf ("FOUND: %ld.\n", template);
3417
3418         ia64_emit_bundle_template (code, template, ins1, ins2, ins3);
3419
3420         stop_pos = last_stop_in_template [template] + 1;
3421         if (stop_pos > n)
3422                 stop_pos = n;
3423
3424         /* Compute the number of 'real' instructions before the stop */
3425         deps_to_shift = stop_pos;
3426         if (stop_pos >= 3 && (nops & (1 << 2)))
3427                 deps_to_shift --;
3428         if (stop_pos >= 2 && (nops & (1 << 1)))
3429                 deps_to_shift --;
3430         if (stop_pos >= 1 && (nops & (1 << 0)))
3431                 deps_to_shift --;
3432
3433         /*
3434          * We have to keep some dependencies whose instructions have been shifted
3435          * out of the buffer. So nullify the end_of_ins markers in the dependency
3436          * array.
3437          */
3438         for (i = deps_start [deps_to_shift]; i < deps_start [n]; i += 2)
3439                 if (code->dep_info [i] == IA64_END_OF_INS)
3440                         code->dep_info [i] = IA64_NONE;
3441
3442         g_assert (deps_start [deps_to_shift] <= code->dep_info_pos);
3443         memcpy (code->dep_info, &code->dep_info [deps_start [deps_to_shift]], code->dep_info_pos - deps_start [deps_to_shift]);
3444         code->dep_info_pos = code->dep_info_pos - deps_start [deps_to_shift];
3445
3446         dep_shift = deps_start [deps_to_shift];
3447         for (i = 0; i < code->nins + 1 - n; ++i)
3448                 deps_start [i] = deps_start [n + i] - dep_shift;
3449
3450         /* Determine the exact positions of instructions with unwind ops */
3451         if (code->unw_op_count) {
3452                 int ins_pos [16];
3453                 int curr_ins, curr_ins_pos;
3454
3455                 curr_ins = 0;
3456                 curr_ins_pos = ((code->buf - code->region_start - 16) / 16) * 3;
3457                 for (i = 0; i < 3; ++i) {
3458                         if (! (nops & (1 << i))) {
3459                                 ins_pos [curr_ins] = curr_ins_pos + i;
3460                                 curr_ins ++;
3461                         }
3462                 }
3463
3464                 for (i = code->unw_op_pos; i < code->unw_op_count; ++i) {
3465                         if (code->unw_ops_pos [i] < n) {
3466                                 code->unw_ops [i].when = ins_pos [code->unw_ops_pos [i]];
3467                                 //printf ("UNW-OP: %d -> %d\n", code->unw_ops_pos [i], code->unw_ops [i].when);
3468                         }
3469                 }
3470                 if (code->unw_op_pos < code->unw_op_count)
3471                         code->unw_op_pos += n;
3472         }
3473
3474         if (n == code->nins) {
3475                 code->template = 0;
3476                 code->nins = 0;
3477         }
3478         else {
3479                 memcpy (&code->instructions [0], &code->instructions [n], (code->nins - n) * sizeof (guint64));
3480                 memcpy (&code->itypes [0], &code->itypes [n], (code->nins - n) * sizeof (int));
3481                 memcpy (&stops [0], &stops [n], (code->nins - n) * sizeof (int));
3482                 code->nins -= n;
3483         }
3484 }
3485
3486 void
3487 ia64_emit_bundle (Ia64CodegenState *code, gboolean flush)
3488 {
3489         int i, ins_type, template, nins_to_emit;
3490         int deps_start [16];
3491         int stops [16];
3492         gboolean found;
3493
3494         /*
3495          * We implement a simple scheduler which tries to put three instructions
3496          * per bundle, then two, then one.
3497          */
3498         ia64_analyze_deps (code, deps_start, stops);
3499
3500         if ((code->nins >= 3) && !code->one_ins_per_bundle) {
3501                 /* Find a suitable template */
3502                 for (template = 0; template < 32; ++template) {
3503                         if (stops_in_template [template][0] != stops [0] ||
3504                                 stops_in_template [template][1] != stops [1] ||
3505                                 stops_in_template [template][2] != stops [2])
3506                                 continue;
3507
3508                         found = TRUE;
3509                         for (i = 0; i < 3; ++i) {
3510                                 ins_type = ins_types_in_template [template][i];
3511                                 switch (code->itypes [i]) {
3512                                 case IA64_INS_TYPE_A:
3513                                         found &= (ins_type == IA64_INS_TYPE_I) || (ins_type == IA64_INS_TYPE_M);
3514                                         break;
3515                                 default:
3516                                         found &= (ins_type == code->itypes [i]);
3517                                         break;
3518                                 }
3519                         }
3520
3521                         if (found)
3522                                 found = debug_ins_sched ();
3523
3524                         if (found) {
3525                                 ia64_real_emit_bundle (code, deps_start, stops, 3, template, code->instructions [0], code->instructions [1], code->instructions [2], 0);
3526                                 break;
3527                         }
3528                 }
3529         }
3530
3531         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3532                 /* Wait for more instructions */
3533                 return;
3534
3535         /* If it didn't work out, try putting two instructions into one bundle */
3536         if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3537                 /* Try a nop at the end */
3538                 for (template = 0; template < 32; ++template) {
3539                         if (stops_in_template [template][0] != stops [0] ||
3540                                 ((stops_in_template [template][1] != stops [1]) &&
3541                                  (stops_in_template [template][2] != stops [1])))
3542
3543                                 continue;
3544
3545                         if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3546                                 !ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [1]))
3547                                 continue;
3548
3549                         if (!debug_ins_sched ())
3550                                 continue;
3551
3552                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], code->instructions [1], nops_for_ins_types [ins_types_in_template [template][2]], 1 << 2);
3553                         break;
3554                 }
3555         }
3556
3557         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3558                 /* Wait for more instructions */
3559                 return;
3560
3561         if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3562                 /* Try a nop in the middle */
3563                 for (template = 0; template < 32; ++template) {
3564                         if (((stops_in_template [template][0] != stops [0]) &&
3565                                  (stops_in_template [template][1] != stops [0])) ||
3566                                 stops_in_template [template][2] != stops [1])
3567                                 continue;
3568
3569                         if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3570                                 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3571                                 continue;
3572
3573                         if (!debug_ins_sched ())
3574                                 continue;
3575
3576                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], nops_for_ins_types [ins_types_in_template [template][1]], code->instructions [1], 1 << 1);
3577                         break;
3578                 }
3579         }
3580
3581         if ((code->nins >= 2) && flush && !code->one_ins_per_bundle) {
3582                 /* Try a nop at the beginning */
3583                 for (template = 0; template < 32; ++template) {
3584                         if ((stops_in_template [template][1] != stops [0]) ||
3585                                 (stops_in_template [template][2] != stops [1]))
3586                                 continue;
3587
3588                         if (!ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [0]) ||
3589                                 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3590                                 continue;
3591
3592                         if (!debug_ins_sched ())
3593                                 continue;
3594
3595                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, nops_for_ins_types [ins_types_in_template [template][0]], code->instructions [0], code->instructions [1], 1 << 0);
3596                         break;
3597                 }
3598         }
3599
3600         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3601                 /* Wait for more instructions */
3602                 return;
3603
3604         if (flush)
3605                 nins_to_emit = code->nins;
3606         else
3607                 nins_to_emit = 1;
3608
3609         while (nins_to_emit > 0) {
3610                 if (!debug_ins_sched ())
3611                         stops [0] = 1;
3612                 switch (code->itypes [0]) {
3613                 case IA64_INS_TYPE_A:
3614                         if (stops [0])
3615                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3616                         else
3617                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3618                         break;
3619                 case IA64_INS_TYPE_I:
3620                         if (stops [0])
3621                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3622                         else
3623                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3624                         break;
3625                 case IA64_INS_TYPE_M:
3626                         if (stops [0])
3627                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3628                         else
3629                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3630                         break;
3631                 case IA64_INS_TYPE_B:
3632                         if (stops [0])
3633                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIBS, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3634                         else
3635                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIB, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3636                         break;
3637                 case IA64_INS_TYPE_F:
3638                         if (stops [0])
3639                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3640                         else
3641                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFI, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3642                         break;
3643                 case IA64_INS_TYPE_LX:
3644                         if (stops [0] || stops [1])
3645                                 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLXS, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3646                         else
3647                                 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLX, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3648                         nins_to_emit --;
3649                         break;
3650                 default:
3651                         g_assert_not_reached ();
3652                 }
3653                 nins_to_emit --;
3654         }
3655 }
3656
3657 unw_dyn_region_info_t*
3658 mono_ia64_create_unwind_region (Ia64CodegenState *code)
3659 {
3660         unw_dyn_region_info_t *r;
3661
3662         g_assert (code->nins == 0);
3663         r = g_malloc0 (_U_dyn_region_info_size (code->unw_op_count));
3664         memcpy (&r->op, &code->unw_ops, sizeof (unw_dyn_op_t) * code->unw_op_count);
3665         r->op_count = code->unw_op_count;
3666         r->insn_count = ((code->buf - code->region_start) >> 4) * 3;
3667         code->unw_op_count = 0;
3668         code->unw_op_pos = 0;
3669         code->region_start = code->buf;
3670
3671         return r;
3672 }
3673
3674 static void
3675 ia64_patch (unsigned char* code, gpointer target)
3676 {
3677         int template, i;
3678         guint64 instructions [3];
3679         guint8 gen_buf [16];
3680         Ia64CodegenState gen;
3681         int ins_to_skip;
3682         gboolean found;
3683
3684         /*
3685          * code encodes both the position inside the buffer and code.nins when
3686          * the instruction was emitted.
3687          */
3688         ins_to_skip = (guint64)code % 16;
3689         code = (unsigned char*)((guint64)code & ~15);
3690
3691         /*
3692          * Search for the first instruction which is 'patchable', skipping
3693          * ins_to_skip instructions.
3694          */
3695
3696         while (TRUE) {
3697
3698         template = ia64_bundle_template (code);
3699         instructions [0] = ia64_bundle_ins1 (code);
3700         instructions [1] = ia64_bundle_ins2 (code);
3701         instructions [2] = ia64_bundle_ins3 (code);
3702
3703         ia64_codegen_init (gen, gen_buf);
3704
3705         found = FALSE;
3706         for (i = 0; i < 3; ++i) {
3707                 guint64 ins = instructions [i];
3708                 int opcode = ia64_ins_opcode (ins);
3709
3710                 if (ins == nops_for_ins_types [ins_types_in_template [template][i]])
3711                         continue;
3712
3713                 if (ins_to_skip) {
3714                         ins_to_skip --;
3715                         continue;
3716                 }
3717
3718                 switch (ins_types_in_template [template][i]) {
3719                 case IA64_INS_TYPE_A:
3720                 case IA64_INS_TYPE_M:
3721                         if ((opcode == 8) && (ia64_ins_x2a (ins) == 2) && (ia64_ins_ve (ins) == 0)) {
3722                                 /* adds */
3723                                 ia64_adds_imm_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), (guint64)target, ia64_ins_r3 (ins));
3724                                 instructions [i] = gen.instructions [0];
3725                                 found = TRUE;
3726                         }
3727                         else
3728                                 NOT_IMPLEMENTED;
3729                         break;
3730                 case IA64_INS_TYPE_B:
3731                         if ((opcode == 4) && (ia64_ins_btype (ins) == 0)) {
3732                                 /* br.cond */
3733                                 gint64 disp = ((guint8*)target - code) >> 4;
3734
3735                                 /* FIXME: hints */
3736                                 ia64_br_cond_hint_pred (gen, ia64_ins_qp (ins), disp, 0, 0, 0);
3737
3738                                 instructions [i] = gen.instructions [0];
3739                                 found = TRUE;
3740                         }
3741                         else if (opcode == 5) {
3742                                 /* br.call */
3743                                 gint64 disp = ((guint8*)target - code) >> 4;
3744
3745                                 /* FIXME: hints */
3746                                 ia64_br_call_hint_pred (gen, ia64_ins_qp (ins), ia64_ins_b1 (ins), disp, 0, 0, 0);
3747                                 instructions [i] = gen.instructions [0];
3748                                 found = TRUE;
3749                         }
3750                         else
3751                                 NOT_IMPLEMENTED;
3752                         break;
3753                 case IA64_INS_TYPE_LX:
3754                         if (i == 1)
3755                                 break;
3756
3757                         if ((opcode == 6) && (ia64_ins_vc (ins) == 0)) {
3758                                 /* movl */
3759                                 ia64_movl_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), target);
3760                                 instructions [1] = gen.instructions [0];
3761                                 instructions [2] = gen.instructions [1];
3762                                 found = TRUE;
3763                         }
3764                         else
3765                                 NOT_IMPLEMENTED;
3766
3767                         break;
3768                 default:
3769                         NOT_IMPLEMENTED;
3770                 }
3771
3772                 if (found) {
3773                         /* Rewrite code */
3774                         ia64_codegen_init (gen, code);
3775                         ia64_emit_bundle_template (&gen, template, instructions [0], instructions [1], instructions [2]);
3776                         return;
3777                 }
3778         }
3779
3780         code += 16;
3781         }
3782 }
3783
3784 void
3785 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
3786 {
3787         MonoJumpInfo *patch_info;
3788
3789         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3790                 unsigned char *ip = patch_info->ip.i + code;
3791                 const unsigned char *target;
3792
3793                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3794
3795                 if (patch_info->type == MONO_PATCH_INFO_NONE)
3796                         continue;
3797                 if (mono_compile_aot) {
3798                         NOT_IMPLEMENTED;
3799                 }
3800
3801                 ia64_patch (ip, (gpointer)target);
3802         }
3803 }
3804
3805 guint8 *
3806 mono_arch_emit_prolog (MonoCompile *cfg)
3807 {
3808         MonoMethod *method = cfg->method;
3809         MonoMethodSignature *sig;
3810         MonoInst *inst;
3811         int alloc_size, pos, i;
3812         Ia64CodegenState code;
3813         CallInfo *cinfo;
3814
3815         sig = mono_method_signature (method);
3816         pos = 0;
3817
3818         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
3819
3820         cfg->code_size =  MAX (cfg->header->code_size * 4, 512);
3821
3822         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3823                 cfg->code_size += 1024;
3824         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3825                 cfg->code_size += 1024;
3826
3827         cfg->native_code = g_malloc (cfg->code_size);
3828
3829         ia64_codegen_init (code, cfg->native_code);
3830
3831         alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
3832         if (cfg->param_area)
3833                 alloc_size += cfg->param_area;
3834         if (alloc_size)
3835                 /* scratch area */
3836                 alloc_size += 16;
3837         alloc_size = ALIGN_TO (alloc_size, MONO_ARCH_FRAME_ALIGNMENT);
3838
3839         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
3840                 /* Force sp to be saved/restored */
3841                 alloc_size += MONO_ARCH_FRAME_ALIGNMENT;
3842
3843         cfg->arch.stack_alloc_size = alloc_size;
3844
3845         pos = 0;
3846
3847         if (method->save_lmf) {
3848                 /* No LMF on IA64 */
3849         }
3850
3851         alloc_size -= pos;
3852
3853         ia64_unw_save_reg (code, UNW_IA64_AR_PFS, UNW_IA64_GR + cfg->arch.reg_saved_ar_pfs);
3854         ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3855         ia64_unw_save_reg (code, UNW_IA64_RP, UNW_IA64_GR + cfg->arch.reg_saved_b0);
3856         ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3857
3858         if ((alloc_size || cinfo->stack_usage) && !cfg->arch.omit_fp) {
3859                 ia64_unw_save_reg (code, UNW_IA64_SP, UNW_IA64_GR + cfg->arch.reg_saved_sp);
3860                 ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3861                 if (cfg->frame_reg != cfg->arch.reg_saved_sp)
3862                         ia64_mov (code, cfg->frame_reg, IA64_SP);
3863         }
3864
3865         if (alloc_size) {
3866 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3867                 int pagesize = getpagesize ();
3868
3869                 if (alloc_size >= pagesize) {
3870                         gint32 remaining_size = alloc_size;
3871
3872                         /* Generate stack touching code */
3873                         ia64_mov (code, GP_SCRATCH_REG, IA64_SP);
3874                         while (remaining_size >= pagesize) {
3875                                 ia64_movl (code, GP_SCRATCH_REG2, pagesize);
3876                                 ia64_sub (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3877                                 ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
3878                                 remaining_size -= pagesize;
3879                         }
3880                 }
3881 #endif
3882                 if (ia64_is_imm14 (-alloc_size)) {
3883                         if (cfg->arch.omit_fp)
3884                                 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3885                         ia64_adds_imm (code, IA64_SP, (-alloc_size), IA64_SP);
3886                 }
3887                 else {
3888                         ia64_movl (code, GP_SCRATCH_REG, -alloc_size);
3889                         if (cfg->arch.omit_fp)
3890                                 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3891                         ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
3892                 }
3893         }
3894
3895         ia64_begin_bundle (code);
3896
3897         /* Initialize unwind info */
3898         cfg->arch.r_pro = mono_ia64_create_unwind_region (&code);
3899
3900         if (sig->ret->type != MONO_TYPE_VOID) {
3901                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
3902                         /* Save volatile arguments to the stack */
3903                         NOT_IMPLEMENTED;
3904                 }
3905         }
3906
3907         /* Keep this in sync with emit_load_volatile_arguments */
3908         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3909                 ArgInfo *ainfo = cinfo->args + i;
3910                 gint32 stack_offset;
3911                 MonoType *arg_type;
3912
3913                 inst = cfg->args [i];
3914
3915                 if (sig->hasthis && (i == 0))
3916                         arg_type = &mono_defaults.object_class->byval_arg;
3917                 else
3918                         arg_type = sig->params [i - sig->hasthis];
3919
3920                 arg_type = mono_type_get_underlying_type (arg_type);
3921
3922                 stack_offset = ainfo->offset + ARGS_OFFSET;
3923
3924                 /*
3925                  * FIXME: Native code might pass non register sized integers
3926                  * without initializing the upper bits.
3927                  */
3928                 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED && !arg_type->byref && ainfo->storage == ArgInIReg) {
3929                         int reg = cfg->arch.reg_in0 + ainfo->reg;
3930
3931                         switch (mono_type_to_load_membase (cfg, arg_type)) {
3932                         case OP_LOADI1_MEMBASE:
3933                                 ia64_sxt1 (code, reg, reg);
3934                                 break;
3935                         case OP_LOADU1_MEMBASE:
3936                                 ia64_zxt1 (code, reg, reg);
3937                                 break;
3938                         case OP_LOADI2_MEMBASE:
3939                                 ia64_sxt2 (code, reg, reg);
3940                                 break;
3941                         case OP_LOADU2_MEMBASE:
3942                                 ia64_zxt2 (code, reg, reg);
3943                                 break;
3944                         default:
3945                                 break;
3946                         }
3947                 }
3948
3949                 /* Save volatile arguments to the stack */
3950                 if (inst->opcode != OP_REGVAR) {
3951                         switch (ainfo->storage) {
3952                         case ArgInIReg:
3953                         case ArgInFloatReg:
3954                         case ArgInFloatRegR4:
3955                                 g_assert (inst->opcode == OP_REGOFFSET);
3956                                 if (ia64_is_adds_imm (inst->inst_offset))
3957                                         ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3958                                 else {
3959                                         ia64_movl (code, GP_SCRATCH_REG2, inst->inst_offset);
3960                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3961                                 }
3962                                 if (arg_type->byref)
3963                                         ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3964                                 else {
3965                                         switch (arg_type->type) {
3966                                         case MONO_TYPE_R4:
3967                                                 ia64_stfs_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3968                                                 break;
3969                                         case MONO_TYPE_R8:
3970                                                 ia64_stfd_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3971                                                 break;
3972                                         default:
3973                                                 ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3974                                                 break;
3975                                         }
3976                                 }
3977                                 break;
3978                         case ArgOnStack:
3979                                 break;
3980                         case ArgAggregate:
3981                                 if (ainfo->nslots != ainfo->nregs)
3982                                         NOT_IMPLEMENTED;
3983
3984                                 g_assert (inst->opcode == OP_REGOFFSET);
3985                                 ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3986                                 for (i = 0; i < ainfo->nregs; ++i) {
3987                                         switch (ainfo->atype) {
3988                                         case AggregateNormal:
3989                                                 ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg + i, sizeof (gpointer), 0);
3990                                                 break;
3991                                         case AggregateSingleHFA:
3992                                                 ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, 4, 0);
3993                                                 break;
3994                                         case AggregateDoubleHFA:
3995                                                 ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, sizeof (gpointer), 0);
3996                                                 break;
3997                                         default:
3998                                                 NOT_IMPLEMENTED;
3999                                         }
4000                                 }
4001                                 break;
4002                         default:
4003                                 g_assert_not_reached ();
4004                         }
4005                 }
4006
4007                 if (inst->opcode == OP_REGVAR) {
4008                         /* Argument allocated to (non-volatile) register */
4009                         switch (ainfo->storage) {
4010                         case ArgInIReg:
4011                                 if (inst->dreg != cfg->arch.reg_in0 + ainfo->reg)
4012                                         ia64_mov (code, inst->dreg, cfg->arch.reg_in0 + ainfo->reg);
4013                                 break;
4014                         case ArgOnStack:
4015                                 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
4016                                 ia64_ld8 (code, inst->dreg, GP_SCRATCH_REG);
4017                                 break;
4018                         default:
4019                                 NOT_IMPLEMENTED;
4020                         }
4021                 }
4022         }
4023
4024         if (method->save_lmf) {
4025                 /* No LMF on IA64 */
4026         }
4027
4028         ia64_codegen_close (code);
4029
4030         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4031                 code.buf = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code.buf, TRUE);
4032
4033         cfg->code_len = code.buf - cfg->native_code;
4034
4035         g_assert (cfg->code_len < cfg->code_size);
4036
4037         cfg->arch.prolog_end_offset = cfg->code_len;
4038
4039         return code.buf;
4040 }
4041
4042 void
4043 mono_arch_emit_epilog (MonoCompile *cfg)
4044 {
4045         MonoMethod *method = cfg->method;
4046         int i, pos;
4047         int max_epilog_size = 16 * 4;
4048         Ia64CodegenState code;
4049         guint8 *buf;
4050         CallInfo *cinfo;
4051         ArgInfo *ainfo;
4052
4053         if (mono_jit_trace_calls != NULL)
4054                 max_epilog_size += 1024;
4055
4056         cfg->arch.epilog_begin_offset = cfg->code_len;
4057
4058         while (cfg->code_len + max_epilog_size > cfg->code_size) {
4059                 cfg->code_size *= 2;
4060                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4061                 cfg->stat_code_reallocs++;
4062         }
4063
4064         /* FIXME: Emit unwind info */
4065
4066         buf = cfg->native_code + cfg->code_len;
4067
4068         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4069                 buf = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, buf, TRUE);
4070
4071         ia64_codegen_init (code, buf);
4072
4073         /* the code restoring the registers must be kept in sync with OP_JMP */
4074         pos = 0;
4075
4076         if (method->save_lmf) {
4077                 /* No LMF on IA64 */
4078         }
4079
4080         /* Load returned vtypes into registers if needed */
4081         cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
4082         ainfo = &cinfo->ret;
4083         switch (ainfo->storage) {
4084         case ArgAggregate:
4085                 if (ainfo->nslots != ainfo->nregs)
4086                         NOT_IMPLEMENTED;
4087
4088                 g_assert (cfg->ret->opcode == OP_REGOFFSET);
4089                 ia64_adds_imm (code, GP_SCRATCH_REG, cfg->ret->inst_offset, cfg->ret->inst_basereg);
4090                 for (i = 0; i < ainfo->nregs; ++i) {
4091                         switch (ainfo->atype) {
4092                         case AggregateNormal:
4093                                 ia64_ld8_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4094                                 break;
4095                         case AggregateSingleHFA:
4096                                 ia64_ldfs_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, 4, 0);
4097                                 break;
4098                         case AggregateDoubleHFA:
4099                                 ia64_ldfd_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4100                                 break;
4101                         default:
4102                                 g_assert_not_reached ();
4103                         }
4104                 }
4105                 break;
4106         default:
4107                 break;
4108         }
4109
4110         ia64_begin_bundle (code);
4111
4112         code.region_start = cfg->native_code;
4113
4114         /* Label the unwind state at the start of the exception throwing region */
4115         //ia64_unw_label_state (code, 1234);
4116
4117         if (cfg->arch.stack_alloc_size) {
4118                 if (cfg->arch.omit_fp) {
4119                         if (ia64_is_imm14 (cfg->arch.stack_alloc_size)) {
4120                                 ia64_unw_pop_frames (code, 1);
4121                                 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
4122                         } else {
4123                                 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
4124                                 ia64_unw_pop_frames (code, 1);
4125                                 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
4126                         }
4127                 }
4128                 else {
4129                         ia64_unw_pop_frames (code, 1);
4130                         ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
4131                 }
4132         }
4133         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
4134         ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
4135         ia64_br_ret_reg (code, IA64_B0);
4136
4137         ia64_codegen_close (code);
4138
4139         cfg->arch.r_epilog = mono_ia64_create_unwind_region (&code);
4140         cfg->arch.r_pro->next = cfg->arch.r_epilog;
4141
4142         cfg->code_len = code.buf - cfg->native_code;
4143
4144         g_assert (cfg->code_len < cfg->code_size);
4145 }
4146
4147 void
4148 mono_arch_emit_exceptions (MonoCompile *cfg)
4149 {
4150         MonoJumpInfo *patch_info;
4151         int i, nthrows;
4152         Ia64CodegenState code;
4153         gboolean empty = TRUE;
4154         //unw_dyn_region_info_t *r_exceptions;
4155         MonoClass *exc_classes [16];
4156         guint8 *exc_throw_start [16], *exc_throw_end [16];
4157         guint32 code_size = 0;
4158
4159         /* Compute needed space */
4160         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4161                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4162                         code_size += 256;
4163                 if (patch_info->type == MONO_PATCH_INFO_R8)
4164                         code_size += 8 + 7; /* sizeof (double) + alignment */
4165                 if (patch_info->type == MONO_PATCH_INFO_R4)
4166                         code_size += 4 + 7; /* sizeof (float) + alignment */
4167         }
4168
4169         if (code_size == 0)
4170                 return;
4171
4172         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4173                 cfg->code_size *= 2;
4174                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4175                 cfg->stat_code_reallocs++;
4176         }
4177
4178         ia64_codegen_init (code, cfg->native_code + cfg->code_len);
4179
4180         /* The unwind state here is the same as before the epilog */
4181         //ia64_unw_copy_state (code, 1234);
4182
4183         /* add code to raise exceptions */
4184         /* FIXME: Optimize this */
4185         nthrows = 0;
4186         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4187                 switch (patch_info->type) {
4188                 case MONO_PATCH_INFO_EXC: {
4189                         MonoClass *exc_class;
4190                         guint8* throw_ip;
4191                         guint8* buf;
4192                         guint64 exc_token_index;
4193
4194                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4195                         g_assert (exc_class);
4196                         exc_token_index = mono_metadata_token_index (exc_class->type_token);
4197                         throw_ip = cfg->native_code + patch_info->ip.i;
4198
4199                         ia64_begin_bundle (code);
4200
4201                         ia64_patch (cfg->native_code + patch_info->ip.i, code.buf);
4202
4203                         /* Find a throw sequence for the same exception class */
4204                         for (i = 0; i < nthrows; ++i)
4205                                 if (exc_classes [i] == exc_class)
4206                                         break;
4207
4208                         if (i < nthrows) {
4209                                 gint64 offset = exc_throw_end [i] - 16 - throw_ip;
4210
4211                                 if (ia64_is_adds_imm (offset))
4212                                         ia64_adds_imm (code, cfg->arch.reg_out0 + 1, offset, IA64_R0);
4213                                 else
4214                                         ia64_movl (code, cfg->arch.reg_out0 + 1, offset);
4215
4216                                 buf = code.buf + code.nins;
4217                                 ia64_br_cond_pred (code, 0, 0);
4218                                 ia64_begin_bundle (code);
4219                                 ia64_patch (buf, exc_throw_start [i]);
4220
4221                                 patch_info->type = MONO_PATCH_INFO_NONE;
4222                         }
4223                         else {
4224                                 /* Arg1 */
4225                                 buf = code.buf;
4226                                 ia64_movl (code, cfg->arch.reg_out0 + 1, 0);
4227
4228                                 ia64_begin_bundle (code);
4229
4230                                 if (nthrows < 16) {
4231                                         exc_classes [nthrows] = exc_class;
4232                                         exc_throw_start [nthrows] = code.buf;
4233                                 }
4234
4235                                 /* Arg2 */
4236                                 if (ia64_is_adds_imm (exc_token_index))
4237                                         ia64_adds_imm (code, cfg->arch.reg_out0 + 0, exc_token_index, IA64_R0);
4238                                 else
4239                                         ia64_movl (code, cfg->arch.reg_out0 + 0, exc_token_index);
4240
4241                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4242                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4243                                 patch_info->ip.i = code.buf + code.nins - cfg->native_code;
4244
4245                                 /* Indirect call */
4246                                 ia64_movl (code, GP_SCRATCH_REG, 0);
4247                                 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
4248                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
4249                                 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
4250
4251                                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
4252
4253                                 /* Patch up the throw offset */
4254                                 ia64_begin_bundle (code);
4255
4256                                 ia64_patch (buf, (gpointer)(code.buf - 16 - throw_ip));
4257
4258                                 if (nthrows < 16) {
4259                                         exc_throw_end [nthrows] = code.buf;
4260                                         nthrows ++;
4261                                 }
4262                         }
4263
4264                         empty = FALSE;
4265                         break;
4266                 }
4267                 default:
4268                         break;
4269                 }
4270         }
4271
4272         if (!empty)
4273                 /* The unwinder needs this to work */
4274                 ia64_break_i (code, 0);
4275
4276         ia64_codegen_close (code);
4277
4278         /* FIXME: */
4279         //r_exceptions = mono_ia64_create_unwind_region (&code);
4280         //cfg->arch.r_epilog = r_exceptions;
4281
4282         cfg->code_len = code.buf - cfg->native_code;
4283
4284         g_assert (cfg->code_len < cfg->code_size);
4285 }
4286
4287 void*
4288 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4289 {
4290         Ia64CodegenState code;
4291         CallInfo *cinfo = NULL;
4292         MonoMethodSignature *sig;
4293         MonoInst *ins;
4294         int i, n, stack_area = 0;
4295
4296         ia64_codegen_init (code, p);
4297
4298         /* Keep this in sync with mono_arch_get_argument_info */
4299
4300         if (enable_arguments) {
4301                 /* Allocate a new area on the stack and save arguments there */
4302                 sig = mono_method_signature (cfg->method);
4303
4304                 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4305
4306                 n = sig->param_count + sig->hasthis;
4307
4308                 stack_area = ALIGN_TO (n * 8, 16);
4309
4310                 if (n) {
4311                         ia64_movl (code, GP_SCRATCH_REG, stack_area);
4312
4313                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4314
4315                         /* FIXME: Allocate out registers */
4316
4317                         ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_SP);
4318
4319                         /* Required by the ABI */
4320                         ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4321
4322                         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4323                         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4324
4325                         /* Save arguments to the stack */
4326                         for (i = 0; i < n; ++i) {
4327                                 ins = cfg->args [i];
4328
4329                                 if (ins->opcode == OP_REGVAR) {
4330                                         ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4331                                         ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4332                                         ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
4333                                 }
4334                                 else {
4335                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
4336                                         ia64_add (code, GP_SCRATCH_REG, ins->inst_basereg, GP_SCRATCH_REG);
4337                                         ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
4338                                         ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4339                                         ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4340                                         ia64_st8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG2);
4341                                 }
4342                         }
4343                 }
4344                 else
4345                         ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4346         }
4347         else
4348                 ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4349
4350         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4351         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4352
4353         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4354
4355         if (enable_arguments && stack_area) {
4356                 ia64_movl (code, GP_SCRATCH_REG, stack_area);
4357
4358                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4359
4360                 ia64_adds_imm (code, IA64_SP, 16, IA64_SP);
4361         }
4362
4363         ia64_codegen_close (code);
4364
4365         return code.buf;
4366 }
4367
4368 void*
4369 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
4370 {
4371         Ia64CodegenState code;
4372         CallInfo *cinfo = NULL;
4373         MonoMethod *method = cfg->method;
4374         MonoMethodSignature *sig = mono_method_signature (cfg->method);
4375
4376         ia64_codegen_init (code, p);
4377
4378         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4379
4380         /* Save return value + pass it to func */
4381         switch (cinfo->ret.storage) {
4382         case ArgNone:
4383                 break;
4384         case ArgInIReg:
4385                 ia64_mov (code, cfg->arch.reg_saved_return_val, cinfo->ret.reg);
4386                 ia64_mov (code, cfg->arch.reg_out0 + 1, cinfo->ret.reg);
4387                 break;
4388         case ArgInFloatReg:
4389                 ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4390                 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4391                 ia64_stfd_hint (code, GP_SCRATCH_REG, cinfo->ret.reg, 0);
4392                 ia64_fmov (code, 8 + 1, cinfo->ret.reg);
4393                 break;
4394         case ArgValuetypeAddrInIReg:
4395                 ia64_mov (code, cfg->arch.reg_out0 + 1, cfg->arch.reg_in0 + cinfo->ret.reg);
4396                 break;
4397         case ArgAggregate:
4398                 NOT_IMPLEMENTED;
4399                 break;
4400         default:
4401                 break;
4402         }
4403
4404         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, method);
4405         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4406         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4407
4408         /* Restore return value */
4409         switch (cinfo->ret.storage) {
4410         case ArgNone:
4411                 break;
4412         case ArgInIReg:
4413                 ia64_mov (code, cinfo->ret.reg, cfg->arch.reg_saved_return_val);
4414                 break;
4415         case ArgInFloatReg:
4416                 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4417                 ia64_ldfd (code, cinfo->ret.reg, GP_SCRATCH_REG);
4418                 break;
4419         case ArgValuetypeAddrInIReg:
4420                 break;
4421         case ArgAggregate:
4422                 break;
4423         default:
4424                 break;
4425         }
4426
4427         ia64_codegen_close (code);
4428
4429         return code.buf;
4430 }
4431
4432 void
4433 mono_arch_save_unwind_info (MonoCompile *cfg)
4434 {
4435         unw_dyn_info_t *di;
4436
4437         /* FIXME: Unregister this for dynamic methods */
4438
4439         di = g_malloc0 (sizeof (unw_dyn_info_t));
4440         di->start_ip = (unw_word_t) cfg->native_code;
4441         di->end_ip = (unw_word_t) cfg->native_code + cfg->code_len;
4442         di->gp = 0;
4443         di->format = UNW_INFO_FORMAT_DYNAMIC;
4444         di->u.pi.name_ptr = (unw_word_t)mono_method_full_name (cfg->method, TRUE);
4445         di->u.pi.regions = cfg->arch.r_pro;
4446
4447         _U_dyn_register (di);
4448
4449         /*
4450         {
4451                 unw_dyn_region_info_t *region = di->u.pi.regions;
4452
4453                 printf ("Unwind info for method %s:\n", mono_method_full_name (cfg->method, TRUE));
4454                 while (region) {
4455                         printf ("    [Region: %d]\n", region->insn_count);
4456                         region = region->next;
4457                 }
4458         }
4459         */
4460 }
4461
4462 void
4463 mono_arch_flush_icache (guint8 *code, gint size)
4464 {
4465         guint8* p = (guint8*)((guint64)code & ~(0x3f));
4466         guint8* end = (guint8*)((guint64)code + size);
4467
4468 #ifdef __INTEL_COMPILER
4469         /* icc doesn't define an fc.i instrinsic, but fc==fc.i on itanium 2 */
4470         while (p < end) {
4471                 __fc ((guint64)p);
4472                 p += 32;
4473         }
4474 #else
4475         while (p < end) {
4476                 __asm__ __volatile__ ("fc.i %0"::"r"(p));
4477                 /* FIXME: This could be increased to 128 on some cpus */
4478                 p += 32;
4479         }
4480 #endif
4481 }
4482
4483 void
4484 mono_arch_flush_register_windows (void)
4485 {
4486         /* Not needed because of libunwind */
4487 }
4488
4489 gboolean
4490 mono_arch_is_inst_imm (gint64 imm)
4491 {
4492         /* The lowering pass will take care of it */
4493
4494         return TRUE;
4495 }
4496
4497 /*
4498  * Determine whenever the trap whose info is in SIGINFO is caused by
4499  * integer overflow.
4500  */
4501 gboolean
4502 mono_arch_is_int_overflow (void *sigctx, void *info)
4503 {
4504         /* Division is emulated with explicit overflow checks */
4505         return FALSE;
4506 }
4507
4508 guint32
4509 mono_arch_get_patch_offset (guint8 *code)
4510 {
4511         NOT_IMPLEMENTED;
4512
4513         return 0;
4514 }
4515
4516 gpointer*
4517 mono_arch_get_delegate_method_ptr_addr (guint8* code, mgreg_t *regs)
4518 {
4519         NOT_IMPLEMENTED;
4520
4521         return NULL;
4522 }
4523
4524 void
4525 mono_arch_finish_init (void)
4526 {
4527 }
4528
4529 void
4530 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4531 {
4532 }
4533
4534 #ifdef MONO_ARCH_HAVE_IMT
4535
4536 /*
4537  * LOCKING: called with the domain lock held
4538  */
4539 gpointer
4540 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
4541         gpointer fail_tramp)
4542 {
4543         int i;
4544         int size = 0;
4545         guint8 *start, *buf;
4546         Ia64CodegenState code;
4547
4548         size = count * 256;
4549         buf = g_malloc0 (size);
4550         ia64_codegen_init (code, buf);
4551
4552         /* IA64_R9 contains the IMT method */
4553
4554         for (i = 0; i < count; ++i) {
4555                 MonoIMTCheckItem *item = imt_entries [i];
4556                 ia64_begin_bundle (code);
4557                 item->code_target = (guint8*)code.buf + code.nins;
4558                 if (item->is_equals) {
4559                         gboolean fail_case = !item->check_target_idx && fail_tramp;
4560
4561                         if (item->check_target_idx || fail_case) {
4562                                 if (!item->compare_done || fail_case) {
4563                                         ia64_movl (code, GP_SCRATCH_REG, item->key);
4564                                         ia64_cmp_eq (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4565                                 }
4566                                 item->jmp_code = (guint8*)code.buf + code.nins;
4567                                 ia64_br_cond_pred (code, 7, 0);
4568
4569                                 if (item->has_target_code) {
4570                                         ia64_movl (code, GP_SCRATCH_REG, item->value.target_code);
4571                                 } else {
4572                                         ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4573                                         ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4574                                 }
4575                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4576                                 ia64_br_cond_reg (code, IA64_B6);
4577
4578                                 if (fail_case) {
4579                                         ia64_begin_bundle (code);
4580                                         ia64_patch (item->jmp_code, (guint8*)code.buf + code.nins);
4581                                         ia64_movl (code, GP_SCRATCH_REG, fail_tramp);
4582                                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4583                                         ia64_br_cond_reg (code, IA64_B6);
4584                                         item->jmp_code = NULL;
4585                                 }
4586                         } else {
4587                                 /* enable the commented code to assert on wrong method */
4588 #if ENABLE_WRONG_METHOD_CHECK
4589                                 g_assert_not_reached ();
4590 #endif
4591                                 ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4592                                 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4593                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4594                                 ia64_br_cond_reg (code, IA64_B6);
4595 #if ENABLE_WRONG_METHOD_CHECK
4596                                 g_assert_not_reached ();
4597 #endif
4598                         }
4599                 } else {
4600                         ia64_movl (code, GP_SCRATCH_REG, item->key);
4601                         ia64_cmp_geu (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4602                         item->jmp_code = (guint8*)code.buf + code.nins;
4603                         ia64_br_cond_pred (code, 6, 0);
4604                 }
4605         }
4606         /* patch the branches to get to the target items */
4607         for (i = 0; i < count; ++i) {
4608                 MonoIMTCheckItem *item = imt_entries [i];
4609                 if (item->jmp_code) {
4610                         if (item->check_target_idx) {
4611                                 ia64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
4612                         }
4613                 }
4614         }
4615
4616         ia64_codegen_close (code);
4617         g_assert (code.buf - buf <= size);
4618
4619         size = code.buf - buf;
4620         if (fail_tramp) {
4621                 start = mono_method_alloc_generic_virtual_thunk (domain, size + 16);
4622                 start = (gpointer)ALIGN_TO (start, 16);
4623         } else {
4624                 start = mono_domain_code_reserve (domain, size);
4625         }
4626         memcpy (start, buf, size);
4627
4628         mono_arch_flush_icache (start, size);
4629
4630         mono_stats.imt_thunks_size += size;
4631
4632         return start;
4633 }
4634
4635 MonoMethod*
4636 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
4637 {
4638         return (MonoMethod*)regs [IA64_R9];
4639 }
4640
4641 void
4642 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
4643 {
4644         /* Done by the implementation of the CALL_MEMBASE opcodes */
4645 }
4646 #endif
4647
4648 gpointer
4649 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
4650 {
4651         return (gpointer)regs [IA64_R10];
4652 }
4653
4654 gpointer
4655 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
4656 {
4657         return NULL;
4658 }
4659
4660 MonoInst*
4661 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4662 {
4663         MonoInst *ins = NULL;
4664
4665         if (cmethod->klass->image == mono_defaults.corlib &&
4666                 (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
4667                 (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
4668
4669                 /*
4670                  * We don't use the generic version in mini_emit_inst_for_method () since we
4671                  * ia64 has atomic_add_imm opcodes.
4672                  */
4673                 if (strcmp (cmethod->name, "Increment") == 0) {
4674                         guint32 opcode;
4675
4676                         if (fsig->params [0]->type == MONO_TYPE_I4)
4677                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4678                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4679                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4680                         else
4681                                 g_assert_not_reached ();
4682                         MONO_INST_NEW (cfg, ins, opcode);
4683                         ins->dreg = mono_alloc_preg (cfg);
4684                         ins->inst_imm = 1;
4685                         ins->inst_basereg = args [0]->dreg;
4686                         ins->inst_offset = 0;
4687                         MONO_ADD_INS (cfg->cbb, ins);
4688                 } else if (strcmp (cmethod->name, "Decrement") == 0) {
4689                         guint32 opcode;
4690
4691                         if (fsig->params [0]->type == MONO_TYPE_I4)
4692                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4693                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4694                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4695                         else
4696                                 g_assert_not_reached ();
4697                         MONO_INST_NEW (cfg, ins, opcode);
4698                         ins->dreg = mono_alloc_preg (cfg);
4699                         ins->inst_imm = -1;
4700                         ins->inst_basereg = args [0]->dreg;
4701                         ins->inst_offset = 0;
4702                         MONO_ADD_INS (cfg->cbb, ins);
4703                 } else if (strcmp (cmethod->name, "Add") == 0) {
4704                         guint32 opcode;
4705                         gboolean is_imm = FALSE;
4706                         gint64 imm = 0;
4707
4708                         if ((args [1]->opcode == OP_ICONST) || (args [1]->opcode == OP_I8CONST)) {
4709                                 imm = (args [1]->opcode == OP_ICONST) ? args [1]->inst_c0 : args [1]->inst_l;
4710
4711                                 is_imm = (imm == 1 || imm == 4 || imm == 8 || imm == 16 || imm == -1 || imm == -4 || imm == -8 || imm == -16);
4712                         }
4713
4714                         if (is_imm) {
4715                                 if (fsig->params [0]->type == MONO_TYPE_I4)
4716                                         opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4717                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
4718                                         opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4719                                 else
4720                                         g_assert_not_reached ();
4721
4722                                 MONO_INST_NEW (cfg, ins, opcode);
4723                                 ins->dreg = mono_alloc_ireg (cfg);
4724                                 ins->inst_basereg = args [0]->dreg;
4725                                 ins->inst_offset = 0;
4726                                 ins->inst_imm = imm;
4727                                 ins->type = (opcode == OP_ATOMIC_ADD_IMM_NEW_I4) ? STACK_I4 : STACK_I8;
4728                         } else {
4729                                 if (fsig->params [0]->type == MONO_TYPE_I4)
4730                                         opcode = OP_ATOMIC_ADD_NEW_I4;
4731                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
4732                                         opcode = OP_ATOMIC_ADD_NEW_I8;
4733                                 else
4734                                         g_assert_not_reached ();
4735
4736                                 MONO_INST_NEW (cfg, ins, opcode);
4737                                 ins->dreg = mono_alloc_ireg (cfg);
4738                                 ins->inst_basereg = args [0]->dreg;
4739                                 ins->inst_offset = 0;
4740                                 ins->sreg2 = args [1]->dreg;
4741                                 ins->type = (opcode == OP_ATOMIC_ADD_NEW_I4) ? STACK_I4 : STACK_I8;
4742                         }
4743                         MONO_ADD_INS (cfg->cbb, ins);
4744                 }
4745         }
4746
4747         return ins;
4748 }
4749
4750 gboolean
4751 mono_arch_print_tree (MonoInst *tree, int arity)
4752 {
4753         return 0;
4754 }
4755
4756 MonoInst*
4757 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
4758 {
4759         return mono_get_domain_intrinsic (cfg);
4760 }
4761
4762 mgreg_t
4763 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
4764 {
4765         /* FIXME: implement */
4766         g_assert_not_reached ();
4767 }