mono/mini/mini-ia64.c

   1 /*
   2  * mini-ia64.c: IA64 backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Zoltan Varga (vargaz@gmail.com)
   6  *
   7  * (C) 2003 Ximian, Inc.
   8  */
   9 #include "mini.h"
  10 #include <string.h>
  11 #include <math.h>
  12 #include <unistd.h>
  13 #include <sys/mman.h>
  14
  15 #ifdef __INTEL_COMPILER
  16 #include <ia64intrin.h>
  17 #endif
  18
  19 #include <mono/metadata/appdomain.h>
  20 #include <mono/metadata/debug-helpers.h>
  21 #include <mono/metadata/threads.h>
  22 #include <mono/metadata/profiler-private.h>
  23 #include <mono/utils/mono-math.h>
  24
  25 #include "trace.h"
  26 #include "mini-ia64.h"
  27 #include "cpu-ia64.h"
  28 #include "jit-icalls.h"
  29 #include "ir-emit.h"
  30
  31 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  32
  33 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  34
  35 /*
  36  * IA64 register usage:
  37  * - local registers are used for global register allocation
  38  * - r8..r11, r14..r30 is used for local register allocation
  39  * - r31 is a scratch register used within opcode implementations
  40  * - FIXME: Use out registers as well
  41  * - the first three locals are used for saving ar.pfst, b0, and sp
  42  * - compare instructions allways set p6 and p7
  43  */
  44
  45 /*
  46  * There are a lot of places where generated code is disassembled/patched.
  47  * The automatic bundling of instructions done by the code generation macros
  48  * could complicate things, so it is best to call
  49  * ia64_codegen_set_one_ins_per_bundle () at those places.
  50  */
  51
  52 #define ARGS_OFFSET 16
  53
  54 #define GP_SCRATCH_REG 31
  55 #define GP_SCRATCH_REG2 30
  56 #define FP_SCRATCH_REG 32
  57 #define FP_SCRATCH_REG2 33
  58
  59 #define LOOP_ALIGNMENT 8
  60 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
  61
  62 static const char* gregs [] = {
  63         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
  64         "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
  65         "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29",
  66         "r30", "r31", "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  67         "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", "r48", "r49",
  68         "r50", "r51", "r52", "r53", "r54", "r55", "r56", "r57", "r58", "r59",
  69         "r60", "r61", "r62", "r63", "r64", "r65", "r66", "r67", "r68", "r69",
  70         "r70", "r71", "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
  71         "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", "r88", "r89",
  72         "r90", "r91", "r92", "r93", "r94", "r95", "r96", "r97", "r98", "r99",
  73         "r100", "r101", "r102", "r103", "r104", "r105", "r106", "r107", "r108", "r109",
  74         "r110", "r111", "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
  75         "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127"
  76 };
  77
  78 const char*
  79 mono_arch_regname (int reg)
  80 {
  81         if (reg < 128)
  82                 return gregs [reg];
  83         else
  84                 return "unknown";
  85 }
  86
  87 static const char* fregs [] = {
  88         "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
  89         "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
  90         "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
  91         "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
  92         "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
  93         "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
  94         "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69",
  95         "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
  96         "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89",
  97         "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99",
  98         "f100", "f101", "f102", "f103", "f104", "f105", "f106", "f107", "f108", "f109",
  99         "f110", "f111", "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
 100         "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127"
 101 };
 102
 103 const char*
 104 mono_arch_fregname (int reg)
 105 {
 106         if (reg < 128)
 107                 return fregs [reg];
 108         else
 109                 return "unknown";
 110 }
 111
 112 G_GNUC_UNUSED static void
 113 break_count (void)
 114 {
 115 }
 116
 117 G_GNUC_UNUSED static gboolean
 118 debug_count (void)
 119 {
 120         static int count = 0;
 121         count ++;
 122
 123         if (count == atoi (getenv ("COUNT"))) {
 124                 break_count ();
 125         }
 126
 127         if (count > atoi (getenv ("COUNT"))) {
 128                 return FALSE;
 129         }
 130
 131         return TRUE;
 132 }
 133
 134 static gboolean
 135 debug_ins_sched (void)
 136 {
 137 #if 0
 138         return debug_count ();
 139 #else
 140         return TRUE;
 141 #endif
 142 }
 143
 144 static gboolean
 145 debug_omit_fp (void)
 146 {
 147 #if 0
 148         return debug_count ();
 149 #else
 150         return TRUE;
 151 #endif
 152 }
 153
 154 static void
 155 ia64_patch (unsigned char* code, gpointer target);
 156
 157 typedef enum {
 158         ArgInIReg,
 159         ArgInFloatReg,
 160         ArgInFloatRegR4,
 161         ArgOnStack,
 162         ArgValuetypeAddrInIReg,
 163         ArgAggregate,
 164         ArgSingleHFA,
 165         ArgDoubleHFA,
 166         ArgNone
 167 } ArgStorage;
 168
 169 typedef enum {
 170         AggregateNormal,
 171         AggregateSingleHFA,
 172         AggregateDoubleHFA
 173 } AggregateType;
 174
 175 typedef struct {
 176         gint16 offset;
 177         gint8  reg;
 178         ArgStorage storage;
 179
 180         /* Only if storage == ArgAggregate */
 181         int nregs, nslots;
 182         AggregateType atype;
 183 } ArgInfo;
 184
 185 typedef struct {
 186         int nargs;
 187         guint32 stack_usage;
 188         guint32 reg_usage;
 189         guint32 freg_usage;
 190         gboolean need_stack_align;
 191         ArgInfo ret;
 192         ArgInfo sig_cookie;
 193         ArgInfo args [1];
 194 } CallInfo;
 195
 196 #define DEBUG(a) if (cfg->verbose_level > 1) a
 197
 198 #define PARAM_REGS 8
 199
 200 static void inline
 201 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 202 {
 203     ainfo->offset = *stack_size;
 204
 205     if (*gr >= PARAM_REGS) {
 206                 ainfo->storage = ArgOnStack;
 207                 (*stack_size) += sizeof (gpointer);
 208     }
 209     else {
 210                 ainfo->storage = ArgInIReg;
 211                 ainfo->reg = *gr;
 212                 *(gr) += 1;
 213     }
 214 }
 215
 216 #define FLOAT_PARAM_REGS 8
 217
 218 static void inline
 219 add_float (guint32 *gr, guint32 *fr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 220 {
 221     ainfo->offset = *stack_size;
 222
 223     if (*gr >= PARAM_REGS) {
 224                 ainfo->storage = ArgOnStack;
 225                 (*stack_size) += sizeof (gpointer);
 226     }
 227     else {
 228                 ainfo->storage = is_double ? ArgInFloatReg : ArgInFloatRegR4;
 229                 ainfo->reg = 8 + *fr;
 230                 (*fr) += 1;
 231                 (*gr) += 1;
 232     }
 233 }
 234
 235 static void
 236 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 237                gboolean is_return,
 238                guint32 *gr, guint32 *fr, guint32 *stack_size)
 239 {
 240         guint32 size, i;
 241         MonoClass *klass;
 242         MonoMarshalType *info;
 243         gboolean is_hfa = TRUE;
 244         guint32 hfa_type = 0;
 245
 246         klass = mono_class_from_mono_type (type);
 247         if (type->type == MONO_TYPE_TYPEDBYREF)
 248                 size = 3 * sizeof (gpointer);
 249         else if (sig->pinvoke)
 250                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 251         else
 252                 size = mini_type_stack_size (gsctx, &klass->byval_arg, NULL);
 253
 254         if (!sig->pinvoke || (size == 0)) {
 255                 /* Allways pass in memory */
 256                 ainfo->offset = *stack_size;
 257                 *stack_size += ALIGN_TO (size, 8);
 258                 ainfo->storage = ArgOnStack;
 259
 260                 return;
 261         }
 262
 263         /* Determine whenever it is a HFA (Homogeneous Floating Point Aggregate) */
 264         info = mono_marshal_load_type_info (klass);
 265         g_assert (info);
 266         for (i = 0; i < info->num_fields; ++i) {
 267                 guint32 ftype = info->fields [i].field->type->type;
 268                 if (!(info->fields [i].field->type->byref) &&
 269                         ((ftype == MONO_TYPE_R4) || (ftype == MONO_TYPE_R8))) {
 270                         if (hfa_type == 0)
 271                                 hfa_type = ftype;
 272                         else if (hfa_type != ftype)
 273                                 is_hfa = FALSE;
 274                 }
 275                 else
 276                         is_hfa = FALSE;
 277         }
 278         if (hfa_type == 0)
 279                 is_hfa = FALSE;
 280
 281         ainfo->storage = ArgAggregate;
 282         ainfo->atype = AggregateNormal;
 283
 284         if (is_hfa) {
 285                 ainfo->atype = hfa_type == MONO_TYPE_R4 ? AggregateSingleHFA : AggregateDoubleHFA;
 286                 if (is_return) {
 287                         if (info->num_fields <= 8) {
 288                                 ainfo->reg = 8;
 289                                 ainfo->nregs = info->num_fields;
 290                                 ainfo->nslots = ainfo->nregs;
 291                                 return;
 292                         }
 293                         /* Fall through */
 294                 }
 295                 else {
 296                         if ((*fr) + info->num_fields > 8)
 297                                 NOT_IMPLEMENTED;
 298
 299                         ainfo->reg = 8 + (*fr);
 300                         ainfo->nregs = info->num_fields;
 301                         ainfo->nslots = ainfo->nregs;
 302                         (*fr) += info->num_fields;
 303                         if (ainfo->atype == AggregateSingleHFA) {
 304                                 /*
 305                                  * FIXME: Have to keep track of the parameter slot number, which is
 306                                  * not the same as *gr.
 307                                  */
 308                                 (*gr) += ALIGN_TO (info->num_fields, 2) / 2;
 309                         } else {
 310                                 (*gr) += info->num_fields;
 311                         }
 312                         return;
 313                 }
 314         }
 315
 316         /* This also handles returning of TypedByRef used by some icalls */
 317         if (is_return) {
 318                 if (size <= 32) {
 319                         ainfo->reg = IA64_R8;
 320                         ainfo->nregs = (size + 7) / 8;
 321                         ainfo->nslots = ainfo->nregs;
 322                         return;
 323                 }
 324                 NOT_IMPLEMENTED;
 325         }
 326
 327         ainfo->reg = (*gr);
 328         ainfo->offset = *stack_size;
 329         ainfo->nslots = (size + 7) / 8;
 330
 331         if (((*gr) + ainfo->nslots) <= 8) {
 332                 /* Fits entirely in registers */
 333                 ainfo->nregs = ainfo->nslots;
 334                 (*gr) += ainfo->nregs;
 335                 return;
 336         }
 337
 338         ainfo->nregs = 8 - (*gr);
 339         (*gr) = 8;
 340         (*stack_size) += (ainfo->nslots - ainfo->nregs) * 8;
 341 }
 342
 343 /*
 344  * get_call_info:
 345  *
 346  *  Obtain information about a call according to the calling convention.
 347  * For IA64, see the "Itanium Software Conventions and Runtime Architecture
 348  * Gude" document for more information.
 349  */
 350 static CallInfo*
 351 get_call_info (MonoCompile *cfg, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 352 {
 353         guint32 i, gr, fr;
 354         MonoType *ret_type;
 355         int n = sig->hasthis + sig->param_count;
 356         guint32 stack_size = 0;
 357         CallInfo *cinfo;
 358         MonoGenericSharingContext *gsctx = cfg ? cfg->generic_sharing_context : NULL;
 359
 360         if (mp)
 361                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 362         else
 363                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 364
 365         gr = 0;
 366         fr = 0;
 367
 368         /* return value */
 369         {
 370                 ret_type = mono_type_get_underlying_type (sig->ret);
 371                 ret_type = mini_get_basic_type_from_generic (gsctx, ret_type);
 372                 switch (ret_type->type) {
 373                 case MONO_TYPE_BOOLEAN:
 374                 case MONO_TYPE_I1:
 375                 case MONO_TYPE_U1:
 376                 case MONO_TYPE_I2:
 377                 case MONO_TYPE_U2:
 378                 case MONO_TYPE_CHAR:
 379                 case MONO_TYPE_I4:
 380                 case MONO_TYPE_U4:
 381                 case MONO_TYPE_I:
 382                 case MONO_TYPE_U:
 383                 case MONO_TYPE_PTR:
 384                 case MONO_TYPE_FNPTR:
 385                 case MONO_TYPE_CLASS:
 386                 case MONO_TYPE_OBJECT:
 387                 case MONO_TYPE_SZARRAY:
 388                 case MONO_TYPE_ARRAY:
 389                 case MONO_TYPE_STRING:
 390                         cinfo->ret.storage = ArgInIReg;
 391                         cinfo->ret.reg = IA64_R8;
 392                         break;
 393                 case MONO_TYPE_U8:
 394                 case MONO_TYPE_I8:
 395                         cinfo->ret.storage = ArgInIReg;
 396                         cinfo->ret.reg = IA64_R8;
 397                         break;
 398                 case MONO_TYPE_R4:
 399                 case MONO_TYPE_R8:
 400                         cinfo->ret.storage = ArgInFloatReg;
 401                         cinfo->ret.reg = 8;
 402                         break;
 403                 case MONO_TYPE_GENERICINST:
 404                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 405                                 cinfo->ret.storage = ArgInIReg;
 406                                 cinfo->ret.reg = IA64_R8;
 407                                 break;
 408                         }
 409                         /* Fall through */
 410                 case MONO_TYPE_VALUETYPE:
 411                 case MONO_TYPE_TYPEDBYREF: {
 412                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 413
 414                         if (sig->ret->byref) {
 415                                 /* This seems to happen with ldfld wrappers */
 416                                 cinfo->ret.storage = ArgInIReg;
 417                         } else {
 418                                 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 419                                 if (cinfo->ret.storage == ArgOnStack)
 420                                         /* The caller passes the address where the value is stored */
 421                                         add_general (&gr, &stack_size, &cinfo->ret);
 422                                 if (cinfo->ret.storage == ArgInIReg)
 423                                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
 424                         }
 425                         break;
 426                 }
 427                 case MONO_TYPE_VOID:
 428                         cinfo->ret.storage = ArgNone;
 429                         break;
 430                 default:
 431                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 432                 }
 433         }
 434
 435         /* this */
 436         if (sig->hasthis)
 437                 add_general (&gr, &stack_size, cinfo->args + 0);
 438
 439         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 440                 gr = PARAM_REGS;
 441                 fr = FLOAT_PARAM_REGS;
 442
 443                 /* Emit the signature cookie just before the implicit arguments */
 444                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 445         }
 446
 447         for (i = 0; i < sig->param_count; ++i) {
 448                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 449                 MonoType *ptype;
 450
 451                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 452                         /* We allways pass the sig cookie on the stack for simplicity */
 453                         /*
 454                          * Prevent implicit arguments + the sig cookie from being passed
 455                          * in registers.
 456                          */
 457                         gr = PARAM_REGS;
 458                         fr = FLOAT_PARAM_REGS;
 459
 460                         /* Emit the signature cookie just before the implicit arguments */
 461                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 462                 }
 463
 464                 if (sig->params [i]->byref) {
 465                         add_general (&gr, &stack_size, ainfo);
 466                         continue;
 467                 }
 468                 ptype = mono_type_get_underlying_type (sig->params [i]);
 469                 ptype = mini_get_basic_type_from_generic (gsctx, ptype);
 470                 switch (ptype->type) {
 471                 case MONO_TYPE_BOOLEAN:
 472                 case MONO_TYPE_I1:
 473                 case MONO_TYPE_U1:
 474                         add_general (&gr, &stack_size, ainfo);
 475                         break;
 476                 case MONO_TYPE_I2:
 477                 case MONO_TYPE_U2:
 478                 case MONO_TYPE_CHAR:
 479                         add_general (&gr, &stack_size, ainfo);
 480                         break;
 481                 case MONO_TYPE_I4:
 482                 case MONO_TYPE_U4:
 483                         add_general (&gr, &stack_size, ainfo);
 484                         break;
 485                 case MONO_TYPE_I:
 486                 case MONO_TYPE_U:
 487                 case MONO_TYPE_PTR:
 488                 case MONO_TYPE_FNPTR:
 489                 case MONO_TYPE_CLASS:
 490                 case MONO_TYPE_OBJECT:
 491                 case MONO_TYPE_STRING:
 492                 case MONO_TYPE_SZARRAY:
 493                 case MONO_TYPE_ARRAY:
 494                         add_general (&gr, &stack_size, ainfo);
 495                         break;
 496                 case MONO_TYPE_GENERICINST:
 497                         if (!mono_type_generic_inst_is_valuetype (sig->params [i])) {
 498                                 add_general (&gr, &stack_size, ainfo);
 499                                 break;
 500                         }
 501                         /* Fall through */
 502                 case MONO_TYPE_VALUETYPE:
 503                 case MONO_TYPE_TYPEDBYREF:
 504                         /* FIXME: */
 505                         /* We allways pass valuetypes on the stack */
 506                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 507                         break;
 508                 case MONO_TYPE_U8:
 509                 case MONO_TYPE_I8:
 510                         add_general (&gr, &stack_size, ainfo);
 511                         break;
 512                 case MONO_TYPE_R4:
 513                         add_float (&gr, &fr, &stack_size, ainfo, FALSE);
 514                         break;
 515                 case MONO_TYPE_R8:
 516                         add_float (&gr, &fr, &stack_size, ainfo, TRUE);
 517                         break;
 518                 default:
 519                         g_assert_not_reached ();
 520                 }
 521         }
 522
 523         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 524                 gr = PARAM_REGS;
 525                 fr = FLOAT_PARAM_REGS;
 526
 527                 /* Emit the signature cookie just before the implicit arguments */
 528                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 529         }
 530
 531         cinfo->stack_usage = stack_size;
 532         cinfo->reg_usage = gr;
 533         cinfo->freg_usage = fr;
 534         return cinfo;
 535 }
 536
 537 /*
 538  * mono_arch_get_argument_info:
 539  * @csig:  a method signature
 540  * @param_count: the number of parameters to consider
 541  * @arg_info: an array to store the result infos
 542  *
 543  * Gathers information on parameters such as size, alignment and
 544  * padding. arg_info should be large enought to hold param_count + 1 entries.
 545  *
 546  * Returns the size of the argument area on the stack.
 547  */
 548 int
 549 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 550 {
 551         int k;
 552         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 553         guint32 args_size = cinfo->stack_usage;
 554
 555         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 556         if (csig->hasthis) {
 557                 arg_info [0].offset = 0;
 558         }
 559
 560         for (k = 0; k < param_count; k++) {
 561                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 562                 /* FIXME: */
 563                 arg_info [k + 1].size = 0;
 564         }
 565
 566         g_free (cinfo);
 567
 568         return args_size;
 569 }
 570
 571 /*
 572  * Initialize the cpu to execute managed code.
 573  */
 574 void
 575 mono_arch_cpu_init (void)
 576 {
 577 }
 578
 579 /*
 580  * Initialize architecture specific code.
 581  */
 582 void
 583 mono_arch_init (void)
 584 {
 585 }
 586
 587 /*
 588  * Cleanup architecture specific code.
 589  */
 590 void
 591 mono_arch_cleanup (void)
 592 {
 593 }
 594
 595 /*
 596  * This function returns the optimizations supported on this cpu.
 597  */
 598 guint32
 599 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 600 {
 601         *exclude_mask = 0;
 602
 603         return 0;
 604 }
 605
 606 GList *
 607 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 608 {
 609         GList *vars = NULL;
 610         int i;
 611         MonoMethodSignature *sig;
 612         MonoMethodHeader *header;
 613         CallInfo *cinfo;
 614
 615         header = mono_method_get_header (cfg->method);
 616
 617         sig = mono_method_signature (cfg->method);
 618
 619         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 620
 621         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 622                 MonoInst *ins = cfg->args [i];
 623
 624                 ArgInfo *ainfo = &cinfo->args [i];
 625
 626                 if (ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 627                         continue;
 628
 629                 if (ainfo->storage == ArgInIReg) {
 630                         /* The input registers are non-volatile */
 631                         ins->opcode = OP_REGVAR;
 632                         ins->dreg = 32 + ainfo->reg;
 633                 }
 634         }
 635
 636         for (i = 0; i < cfg->num_varinfo; i++) {
 637                 MonoInst *ins = cfg->varinfo [i];
 638                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 639
 640                 /* unused vars */
 641                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 642                         continue;
 643
 644                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 645                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 646                         continue;
 647
 648                 if (mono_is_regsize_var (ins->inst_vtype)) {
 649                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 650                         g_assert (i == vmv->idx);
 651                         vars = g_list_prepend (vars, vmv);
 652                 }
 653         }
 654
 655         vars = mono_varlist_sort (cfg, vars, 0);
 656
 657         return vars;
 658 }
 659
 660 static void
 661 mono_ia64_alloc_stacked_registers (MonoCompile *cfg)
 662 {
 663         CallInfo *cinfo;
 664         guint32 reserved_regs;
 665         MonoMethodHeader *header;
 666
 667         if (cfg->arch.reg_local0 > 0)
 668                 /* Already done */
 669                 return;
 670
 671         cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (cfg->method), FALSE);
 672
 673         header = mono_method_get_header (cfg->method);
 674
 675         /* Some registers are reserved for use by the prolog/epilog */
 676         reserved_regs = header->num_clauses ? 4 : 3;
 677
 678         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 679                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
 680                 /* One registers is needed by instrument_epilog to save the return value */
 681                 reserved_regs ++;
 682                 if (cinfo->reg_usage < 2)
 683                         /* Number of arguments passed to function call in instrument_prolog */
 684                         cinfo->reg_usage = 2;
 685         }
 686
 687         cfg->arch.reg_in0 = 32;
 688         cfg->arch.reg_local0 = cfg->arch.reg_in0 + cinfo->reg_usage + reserved_regs;
 689         cfg->arch.reg_out0 = cfg->arch.reg_local0 + 16;
 690
 691         cfg->arch.reg_saved_ar_pfs = cfg->arch.reg_local0 - 1;
 692         cfg->arch.reg_saved_b0 = cfg->arch.reg_local0 - 2;
 693         cfg->arch.reg_fp = cfg->arch.reg_local0 - 3;
 694
 695         /*
 696          * Frames without handlers save sp to fp, frames with handlers save it into
 697          * a dedicated register.
 698          */
 699         if (header->num_clauses)
 700                 cfg->arch.reg_saved_sp = cfg->arch.reg_local0 - 4;
 701         else
 702                 cfg->arch.reg_saved_sp = cfg->arch.reg_fp;
 703
 704         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 705                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
 706                 cfg->arch.reg_saved_return_val = cfg->arch.reg_local0 - reserved_regs;
 707         }
 708
 709         /*
 710          * Need to allocate at least 2 out register for use by OP_THROW / the system
 711          * exception throwing code.
 712          */
 713         cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, 2);
 714 }
 715
 716 GList *
 717 mono_arch_get_global_int_regs (MonoCompile *cfg)
 718 {
 719         GList *regs = NULL;
 720         int i;
 721
 722         mono_ia64_alloc_stacked_registers (cfg);
 723
 724         for (i = cfg->arch.reg_local0; i < cfg->arch.reg_out0; ++i) {
 725                 /* FIXME: regmask */
 726                 g_assert (i < 64);
 727                 regs = g_list_prepend (regs, (gpointer)(gssize)(i));
 728         }
 729
 730         return regs;
 731 }
 732
 733 /*
 734  * mono_arch_regalloc_cost:
 735  *
 736  *  Return the cost, in number of memory references, of the action of
 737  * allocating the variable VMV into a register during global register
 738  * allocation.
 739  */
 740 guint32
 741 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 742 {
 743         /* FIXME: Increase costs linearly to avoid using all local registers */
 744
 745         return 0;
 746 }
 747
 748 void
 749 mono_arch_allocate_vars (MonoCompile *cfg)
 750 {
 751         MonoMethodSignature *sig;
 752         MonoMethodHeader *header;
 753         MonoInst *inst;
 754         int i, offset;
 755         guint32 locals_stack_size, locals_stack_align;
 756         gint32 *offsets;
 757         CallInfo *cinfo;
 758
 759         header = mono_method_get_header (cfg->method);
 760
 761         sig = mono_method_signature (cfg->method);
 762
 763         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 764
 765         /*
 766          * Determine whenever the frame pointer can be eliminated.
 767          * FIXME: Remove some of the restrictions.
 768          */
 769         cfg->arch.omit_fp = TRUE;
 770
 771         if (!debug_omit_fp ())
 772                 cfg->arch.omit_fp = FALSE;
 773
 774         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 775                 cfg->arch.omit_fp = FALSE;
 776         if (header->num_clauses)
 777                 cfg->arch.omit_fp = FALSE;
 778         if (cfg->param_area)
 779                 cfg->arch.omit_fp = FALSE;
 780         if ((sig->ret->type != MONO_TYPE_VOID) && (cinfo->ret.storage == ArgAggregate))
 781                 cfg->arch.omit_fp = FALSE;
 782         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 783                 cfg->arch.omit_fp = FALSE;
 784         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 785                 ArgInfo *ainfo = &cinfo->args [i];
 786
 787                 if (ainfo->storage == ArgOnStack) {
 788                         /*
 789                          * The stack offset can only be determined when the frame
 790                          * size is known.
 791                          */
 792                         cfg->arch.omit_fp = FALSE;
 793                 }
 794         }
 795
 796         mono_ia64_alloc_stacked_registers (cfg);
 797
 798         /*
 799          * We use the ABI calling conventions for managed code as well.
 800          * Exception: valuetypes are never passed or returned in registers.
 801          */
 802
 803         if (cfg->arch.omit_fp) {
 804                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
 805                 cfg->frame_reg = IA64_SP;
 806                 offset = ARGS_OFFSET;
 807         }
 808         else {
 809                 /* Locals are allocated backwards from %fp */
 810                 cfg->frame_reg = cfg->arch.reg_fp;
 811                 offset = 0;
 812         }
 813
 814         if (cfg->method->save_lmf) {
 815                 /* No LMF on IA64 */
 816         }
 817
 818         if (sig->ret->type != MONO_TYPE_VOID) {
 819                 switch (cinfo->ret.storage) {
 820                 case ArgInIReg:
 821                         cfg->ret->opcode = OP_REGVAR;
 822                         cfg->ret->inst_c0 = cinfo->ret.reg;
 823                         break;
 824                 case ArgInFloatReg:
 825                         cfg->ret->opcode = OP_REGVAR;
 826                         cfg->ret->inst_c0 = cinfo->ret.reg;
 827                         break;
 828                 case ArgValuetypeAddrInIReg:
 829                         cfg->vret_addr->opcode = OP_REGVAR;
 830                         cfg->vret_addr->dreg = cfg->arch.reg_in0 + cinfo->ret.reg;
 831                         break;
 832                 case ArgAggregate:
 833                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
 834                         if (cfg->arch.omit_fp)
 835                                 g_assert_not_reached ();
 836                         offset = ALIGN_TO (offset, 8);
 837                         offset += cinfo->ret.nslots * 8;
 838                         cfg->ret->opcode = OP_REGOFFSET;
 839                         cfg->ret->inst_basereg = cfg->frame_reg;
 840                         cfg->ret->inst_offset = - offset;
 841                         break;
 842                 default:
 843                         g_assert_not_reached ();
 844                 }
 845                 cfg->ret->dreg = cfg->ret->inst_c0;
 846         }
 847
 848         /* Allocate locals */
 849         offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE : TRUE, &locals_stack_size, &locals_stack_align);
 850         if (locals_stack_align) {
 851                 offset = ALIGN_TO (offset, locals_stack_align);
 852         }
 853         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
 854                 if (offsets [i] != -1) {
 855                         MonoInst *inst = cfg->varinfo [i];
 856                         inst->opcode = OP_REGOFFSET;
 857                         inst->inst_basereg = cfg->frame_reg;
 858                         if (cfg->arch.omit_fp)
 859                                 inst->inst_offset = (offset + offsets [i]);
 860                         else
 861                                 inst->inst_offset = - (offset + offsets [i]);
 862                         // printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
 863                 }
 864         }
 865         offset += locals_stack_size;
 866
 867         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
 868                 if (cfg->arch.omit_fp)
 869                         g_assert_not_reached ();
 870                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
 871                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
 872         }
 873
 874         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 875                 inst = cfg->args [i];
 876                 if (inst->opcode != OP_REGVAR) {
 877                         ArgInfo *ainfo = &cinfo->args [i];
 878                         gboolean inreg = TRUE;
 879                         MonoType *arg_type;
 880
 881                         if (sig->hasthis && (i == 0))
 882                                 arg_type = &mono_defaults.object_class->byval_arg;
 883                         else
 884                                 arg_type = sig->params [i - sig->hasthis];
 885
 886                         /* FIXME: VOLATILE is only set if the liveness pass runs */
 887                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 888                                 inreg = FALSE;
 889
 890                         inst->opcode = OP_REGOFFSET;
 891
 892                         switch (ainfo->storage) {
 893                         case ArgInIReg:
 894                                 inst->opcode = OP_REGVAR;
 895                                 inst->dreg = cfg->arch.reg_in0 + ainfo->reg;
 896                                 break;
 897                         case ArgInFloatReg:
 898                         case ArgInFloatRegR4:
 899                                 /*
 900                                  * Since float regs are volatile, we save the arguments to
 901                                  * the stack in the prolog.
 902                                  */
 903                                 inreg = FALSE;
 904                                 break;
 905                         case ArgOnStack:
 906                                 if (cfg->arch.omit_fp)
 907                                         g_assert_not_reached ();
 908                                 inst->opcode = OP_REGOFFSET;
 909                                 inst->inst_basereg = cfg->frame_reg;
 910                                 inst->inst_offset = ARGS_OFFSET + ainfo->offset;
 911                                 break;
 912                         case ArgAggregate:
 913                                 inreg = FALSE;
 914                                 break;
 915                         default:
 916                                 NOT_IMPLEMENTED;
 917                         }
 918
 919                         if (!inreg && (ainfo->storage != ArgOnStack)) {
 920                                 guint32 size = 0;
 921
 922                                 inst->opcode = OP_REGOFFSET;
 923                                 inst->inst_basereg = cfg->frame_reg;
 924                                 /* These arguments are saved to the stack in the prolog */
 925                                 switch (ainfo->storage) {
 926                                 case ArgAggregate:
 927                                         if (ainfo->atype == AggregateSingleHFA)
 928                                                 size = ainfo->nslots * 4;
 929                                         else
 930                                                 size = ainfo->nslots * 8;
 931                                         break;
 932                                 default:
 933                                         size = sizeof (gpointer);
 934                                         break;
 935                                 }
 936
 937                                 offset = ALIGN_TO (offset, sizeof (gpointer));
 938
 939                                 if (cfg->arch.omit_fp) {
 940                                         inst->inst_offset = offset;
 941                                         offset += size;
 942                                 } else {
 943                                         offset += size;
 944                                         inst->inst_offset = - offset;
 945                                 }
 946                         }
 947                 }
 948         }
 949
 950         /*
 951          * FIXME: This doesn't work because some variables are allocated during local
 952          * regalloc.
 953          */
 954         /*
 955         if (cfg->arch.omit_fp && offset == 16)
 956                 offset = 0;
 957         */
 958
 959         cfg->stack_offset = offset;
 960 }
 961
 962 void
 963 mono_arch_create_vars (MonoCompile *cfg)
 964 {
 965         MonoMethodSignature *sig;
 966         CallInfo *cinfo;
 967
 968         sig = mono_method_signature (cfg->method);
 969
 970         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 971
 972         if (cinfo->ret.storage == ArgAggregate)
 973                 cfg->ret_var_is_local = TRUE;
 974         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
 975                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
 976                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
 977                         printf ("vret_addr = ");
 978                         mono_print_ins (cfg->vret_addr);
 979                 }
 980         }
 981 }
 982
 983 static void
 984 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
 985 {
 986         MonoInst *arg;
 987
 988         MONO_INST_NEW (cfg, arg, OP_NOP);
 989         arg->sreg1 = tree->dreg;
 990
 991         switch (storage) {
 992         case ArgInIReg:
 993                 arg->opcode = OP_MOVE;
 994                 arg->dreg = mono_alloc_ireg (cfg);
 995
 996                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, FALSE);
 997                 break;
 998         case ArgInFloatReg:
 999                 arg->opcode = OP_FMOVE;
1000                 arg->dreg = mono_alloc_freg (cfg);
1001
1002                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1003                 break;
1004         case ArgInFloatRegR4:
1005                 arg->opcode = OP_FCONV_TO_R4;
1006                 arg->dreg = mono_alloc_freg (cfg);
1007
1008                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1009                 break;
1010         default:
1011                 g_assert_not_reached ();
1012         }
1013
1014         MONO_ADD_INS (cfg->cbb, arg);
1015 }
1016
1017 static void
1018 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1019 {
1020         MonoMethodSignature *tmp_sig;
1021
1022         /* Emit the signature cookie just before the implicit arguments */
1023         MonoInst *sig_arg;
1024         /* FIXME: Add support for signature tokens to AOT */
1025         cfg->disable_aot = TRUE;
1026
1027         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1028
1029         /*
1030          * mono_ArgIterator_Setup assumes the signature cookie is
1031          * passed first and all the arguments which were before it are
1032          * passed on the stack after the signature. So compensate by
1033          * passing a different signature.
1034          */
1035         tmp_sig = mono_metadata_signature_dup (call->signature);
1036         tmp_sig->param_count -= call->signature->sentinelpos;
1037         tmp_sig->sentinelpos = 0;
1038         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1039
1040         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1041         sig_arg->dreg = mono_alloc_ireg (cfg);
1042         sig_arg->inst_p0 = tmp_sig;
1043         MONO_ADD_INS (cfg->cbb, sig_arg);
1044
1045         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + cinfo->sig_cookie.offset, sig_arg->dreg);
1046 }
1047
1048 void
1049 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1050 {
1051         MonoInst *in;
1052         MonoMethodSignature *sig;
1053         int i, n, stack_size;
1054         CallInfo *cinfo;
1055         ArgInfo *ainfo;
1056
1057         stack_size = 0;
1058
1059         mono_ia64_alloc_stacked_registers (cfg);
1060
1061         sig = call->signature;
1062         n = sig->param_count + sig->hasthis;
1063
1064         cinfo = get_call_info (cfg, cfg->mempool, sig, sig->pinvoke);
1065
1066         if (cinfo->ret.storage == ArgAggregate) {
1067                 MonoInst *vtarg;
1068                 MonoInst *local;
1069
1070                 /*
1071                  * The valuetype is in registers after the call, need to be copied
1072                  * to the stack. Save the address to a local here, so the call
1073                  * instruction can access it.
1074                  */
1075                 local = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1076                 local->flags |= MONO_INST_VOLATILE;
1077                 cfg->arch.ret_var_addr_local = local;
1078
1079                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1080                 vtarg->sreg1 = call->vret_var->dreg;
1081                 vtarg->dreg = local->dreg;
1082                 MONO_ADD_INS (cfg->cbb, vtarg);
1083         }
1084
1085         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1086                 add_outarg_reg (cfg, call, ArgInIReg, cfg->arch.reg_out0 + cinfo->ret.reg, call->vret_var);
1087         }
1088
1089         for (i = 0; i < n; ++i) {
1090                 MonoType *arg_type;
1091
1092                 ainfo = cinfo->args + i;
1093
1094                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1095                         /* Emit the signature cookie just before the implicit arguments */
1096                         emit_sig_cookie (cfg, call, cinfo);
1097                 }
1098
1099                 in = call->args [i];
1100
1101                 if (sig->hasthis && (i == 0))
1102                         arg_type = &mono_defaults.object_class->byval_arg;
1103                 else
1104                         arg_type = sig->params [i - sig->hasthis];
1105
1106                 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(arg_type))) {
1107                         guint32 align;
1108                         guint32 size;
1109
1110                         if (arg_type->type == MONO_TYPE_TYPEDBYREF) {
1111                                 size = sizeof (MonoTypedRef);
1112                                 align = sizeof (gpointer);
1113                         }
1114                         else if (sig->pinvoke)
1115                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1116                         else {
1117                                 /*
1118                                  * Other backends use mono_type_stack_size (), but that
1119                                  * aligns the size to 8, which is larger than the size of
1120                                  * the source, leading to reads of invalid memory if the
1121                                  * source is at the end of address space.
1122                                  */
1123                                 size = mono_class_value_size (in->klass, &align);
1124                         }
1125
1126                         if (size > 0) {
1127                                 MonoInst *arg;
1128
1129                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1130                                 arg->sreg1 = in->dreg;
1131                                 arg->klass = in->klass;
1132                                 arg->backend.size = size;
1133                                 arg->inst_p0 = call;
1134                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1135                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1136
1137                                 MONO_ADD_INS (cfg->cbb, arg);
1138                         }
1139                 }
1140                 else {
1141                         switch (ainfo->storage) {
1142                         case ArgInIReg:
1143                                 add_outarg_reg (cfg, call, ainfo->storage, cfg->arch.reg_out0 + ainfo->reg, in);
1144                                 break;
1145                         case ArgInFloatReg:
1146                         case ArgInFloatRegR4:
1147                                 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1148                                 break;
1149                         case ArgOnStack:
1150                                 if (arg_type->type == MONO_TYPE_R4 && !arg_type->byref)
1151                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1152                                 else if (arg_type->type == MONO_TYPE_R8 && !arg_type->byref)
1153                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1154                                 else
1155                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1156                                 break;
1157                         default:
1158                                 g_assert_not_reached ();
1159                         }
1160                 }
1161         }
1162
1163         /* Handle the case where there are no implicit arguments */
1164         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1165                 emit_sig_cookie (cfg, call, cinfo);
1166         }
1167
1168         call->stack_usage = cinfo->stack_usage;
1169         cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, cinfo->reg_usage);
1170 }
1171
1172 void
1173 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1174 {
1175         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1176         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1177         int size = ins->backend.size;
1178
1179         if (ainfo->storage == ArgAggregate) {
1180                 MonoInst *load, *store;
1181                 int i, slot;
1182
1183                 /*
1184                  * Part of the structure is passed in registers.
1185                  */
1186                 for (i = 0; i < ainfo->nregs; ++i) {
1187                         slot = ainfo->reg + i;
1188
1189                         if (ainfo->atype == AggregateSingleHFA) {
1190                                 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
1191                                 load->inst_basereg = src->dreg;
1192                                 load->inst_offset = i * 4;
1193                                 load->dreg = mono_alloc_freg (cfg);
1194
1195                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1196                         } else if (ainfo->atype == AggregateDoubleHFA) {
1197                                 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
1198                                 load->inst_basereg = src->dreg;
1199                                 load->inst_offset = i * 8;
1200                                 load->dreg = mono_alloc_freg (cfg);
1201
1202                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1203                         } else {
1204                                 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1205                                 load->inst_basereg = src->dreg;
1206                                 load->inst_offset = i * 8;
1207                                 load->dreg = mono_alloc_ireg (cfg);
1208
1209                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, cfg->arch.reg_out0 + ainfo->reg + i, FALSE);
1210                         }
1211                         MONO_ADD_INS (cfg->cbb, load);
1212                 }
1213
1214                 /*
1215                  * Part of the structure is passed on the stack.
1216                  */
1217                 for (i = ainfo->nregs; i < ainfo->nslots; ++i) {
1218                         slot = ainfo->reg + i;
1219
1220                         MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1221                         load->inst_basereg = src->dreg;
1222                         load->inst_offset = i * sizeof (gpointer);
1223                         load->dreg = mono_alloc_preg (cfg);
1224                         MONO_ADD_INS (cfg->cbb, load);
1225
1226                         MONO_INST_NEW (cfg, store, OP_STOREI8_MEMBASE_REG);
1227                         store->sreg1 = load->dreg;
1228                         store->inst_destbasereg = IA64_SP;
1229                         store->inst_offset = 16 + ainfo->offset + (slot - 8) * 8;
1230                         MONO_ADD_INS (cfg->cbb, store);
1231                 }
1232         } else {
1233                 mini_emit_memcpy (cfg, IA64_SP, 16 + ainfo->offset, src->dreg, 0, size, 4);
1234         }
1235 }
1236
1237 void
1238 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1239 {
1240         CallInfo *cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
1241
1242         switch (cinfo->ret.storage) {
1243         case ArgInIReg:
1244                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1245                 break;
1246         case ArgInFloatReg:
1247                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1248                 break;
1249         default:
1250                 g_assert_not_reached ();
1251         }
1252 }
1253
1254 void
1255 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1256 {
1257 }
1258
1259 void
1260 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1261 {
1262         MonoInst *ins, *n, *last_ins = NULL;
1263         ins = bb->code;
1264
1265         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1266                 switch (ins->opcode) {
1267                 case OP_MOVE:
1268                 case OP_FMOVE:
1269                         /*
1270                          * Removes:
1271                          *
1272                          * OP_MOVE reg, reg
1273                          */
1274                         if (ins->dreg == ins->sreg1) {
1275                                 MONO_DELETE_INS (bb, ins);
1276                                 continue;
1277                         }
1278                         /*
1279                          * Removes:
1280                          *
1281                          * OP_MOVE sreg, dreg
1282                          * OP_MOVE dreg, sreg
1283                          */
1284                         if (last_ins && last_ins->opcode == OP_MOVE &&
1285                             ins->sreg1 == last_ins->dreg &&
1286                             ins->dreg == last_ins->sreg1) {
1287                                 MONO_DELETE_INS (bb, ins);
1288                                 continue;
1289                         }
1290                         break;
1291                 case OP_MUL_IMM:
1292                 case OP_IMUL_IMM:
1293                         /* remove unnecessary multiplication with 1 */
1294                         if (ins->inst_imm == 1) {
1295                                 if (ins->dreg != ins->sreg1) {
1296                                         ins->opcode = OP_MOVE;
1297                                 } else {
1298                                         MONO_DELETE_INS (bb, ins);
1299                                         continue;
1300                                 }
1301                         }
1302                         break;
1303                 }
1304
1305                 last_ins = ins;
1306                 ins = ins->next;
1307         }
1308         bb->last_ins = last_ins;
1309 }
1310
1311 int cond_to_ia64_cmp [][3] = {
1312         {OP_IA64_CMP_EQ, OP_IA64_CMP4_EQ, OP_IA64_FCMP_EQ},
1313         {OP_IA64_CMP_NE, OP_IA64_CMP4_NE, OP_IA64_FCMP_NE},
1314         {OP_IA64_CMP_LE, OP_IA64_CMP4_LE, OP_IA64_FCMP_LE},
1315         {OP_IA64_CMP_GE, OP_IA64_CMP4_GE, OP_IA64_FCMP_GE},
1316         {OP_IA64_CMP_LT, OP_IA64_CMP4_LT, OP_IA64_FCMP_LT},
1317         {OP_IA64_CMP_GT, OP_IA64_CMP4_GT, OP_IA64_FCMP_GT},
1318         {OP_IA64_CMP_LE_UN, OP_IA64_CMP4_LE_UN, OP_IA64_FCMP_LE_UN},
1319         {OP_IA64_CMP_GE_UN, OP_IA64_CMP4_GE_UN, OP_IA64_FCMP_GE_UN},
1320         {OP_IA64_CMP_LT_UN, OP_IA64_CMP4_LT_UN, OP_IA64_FCMP_LT_UN},
1321         {OP_IA64_CMP_GT_UN, OP_IA64_CMP4_GT_UN, OP_IA64_FCMP_GT_UN}
1322 };
1323
1324 static int
1325 opcode_to_ia64_cmp (int opcode, int cmp_opcode)
1326 {
1327         return cond_to_ia64_cmp [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1328 }
1329
1330 int cond_to_ia64_cmp_imm [][3] = {
1331         {OP_IA64_CMP_EQ_IMM, OP_IA64_CMP4_EQ_IMM, 0},
1332         {OP_IA64_CMP_NE_IMM, OP_IA64_CMP4_NE_IMM, 0},
1333         {OP_IA64_CMP_GE_IMM, OP_IA64_CMP4_GE_IMM, 0},
1334         {OP_IA64_CMP_LE_IMM, OP_IA64_CMP4_LE_IMM, 0},
1335         {OP_IA64_CMP_GT_IMM, OP_IA64_CMP4_GT_IMM, 0},
1336         {OP_IA64_CMP_LT_IMM, OP_IA64_CMP4_LT_IMM, 0},
1337         {OP_IA64_CMP_GE_UN_IMM, OP_IA64_CMP4_GE_UN_IMM, 0},
1338         {OP_IA64_CMP_LE_UN_IMM, OP_IA64_CMP4_LE_UN_IMM, 0},
1339         {OP_IA64_CMP_GT_UN_IMM, OP_IA64_CMP4_GT_UN_IMM, 0},
1340         {OP_IA64_CMP_LT_UN_IMM, OP_IA64_CMP4_LT_UN_IMM, 0},
1341 };
1342
1343 static int
1344 opcode_to_ia64_cmp_imm (int opcode, int cmp_opcode)
1345 {
1346         /* The condition needs to be reversed */
1347         return cond_to_ia64_cmp_imm [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1348 }
1349
1350 #define NEW_INS(cfg,dest,op) do {       \
1351                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1352                 (dest)->opcode = (op);  \
1353         mono_bblock_insert_after_ins (bb, last_ins, (dest)); \
1354         last_ins = (dest); \
1355         } while (0)
1356
1357 /*
1358  * mono_arch_lowering_pass:
1359  *
1360  *  Converts complex opcodes into simpler ones so that each IR instruction
1361  * corresponds to one machine instruction.
1362  */
1363 void
1364 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1365 {
1366         MonoInst *ins, *n, *next, *temp, *temp2, *temp3, *last_ins = NULL;
1367         ins = bb->code;
1368
1369         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1370                 switch (ins->opcode) {
1371                 case OP_STOREI1_MEMBASE_IMM:
1372                 case OP_STOREI2_MEMBASE_IMM:
1373                 case OP_STOREI4_MEMBASE_IMM:
1374                 case OP_STOREI8_MEMBASE_IMM:
1375                 case OP_STORE_MEMBASE_IMM:
1376                         /* There are no store_membase instructions on ia64 */
1377                         if (ins->inst_offset == 0) {
1378                                 temp2 = NULL;
1379                         } else if (ia64_is_imm14 (ins->inst_offset)) {
1380                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1381                                 temp2->sreg1 = ins->inst_destbasereg;
1382                                 temp2->inst_imm = ins->inst_offset;
1383                                 temp2->dreg = mono_alloc_ireg (cfg);
1384                         }
1385                         else {
1386                                 NEW_INS (cfg, temp, OP_I8CONST);
1387                                 temp->inst_c0 = ins->inst_offset;
1388                                 temp->dreg = mono_alloc_ireg (cfg);
1389
1390                                 NEW_INS (cfg, temp2, OP_LADD);
1391                                 temp2->sreg1 = ins->inst_destbasereg;
1392                                 temp2->sreg2 = temp->dreg;
1393                                 temp2->dreg = mono_alloc_ireg (cfg);
1394                         }
1395
1396                         switch (ins->opcode) {
1397                         case OP_STOREI1_MEMBASE_IMM:
1398                                 ins->opcode = OP_STOREI1_MEMBASE_REG;
1399                                 break;
1400                         case OP_STOREI2_MEMBASE_IMM:
1401                                 ins->opcode = OP_STOREI2_MEMBASE_REG;
1402                                 break;
1403                         case OP_STOREI4_MEMBASE_IMM:
1404                                 ins->opcode = OP_STOREI4_MEMBASE_REG;
1405                                 break;
1406                         case OP_STOREI8_MEMBASE_IMM:
1407                         case OP_STORE_MEMBASE_IMM:
1408                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
1409                                 break;
1410                         default:
1411                                 g_assert_not_reached ();
1412                         }
1413
1414                         if (ins->inst_imm == 0)
1415                                 ins->sreg1 = IA64_R0;
1416                         else {
1417                                 NEW_INS (cfg, temp3, OP_I8CONST);
1418                                 temp3->inst_c0 = ins->inst_imm;
1419                                 temp3->dreg = mono_alloc_ireg (cfg);
1420                                 ins->sreg1 = temp3->dreg;
1421                         }
1422
1423                         ins->inst_offset = 0;
1424                         if (temp2)
1425                                 ins->inst_destbasereg = temp2->dreg;
1426                         break;
1427                 case OP_STOREI1_MEMBASE_REG:
1428                 case OP_STOREI2_MEMBASE_REG:
1429                 case OP_STOREI4_MEMBASE_REG:
1430                 case OP_STOREI8_MEMBASE_REG:
1431                 case OP_STORER4_MEMBASE_REG:
1432                 case OP_STORER8_MEMBASE_REG:
1433                 case OP_STORE_MEMBASE_REG:
1434                         /* There are no store_membase instructions on ia64 */
1435                         if (ins->inst_offset == 0) {
1436                                 break;
1437                         }
1438                         else if (ia64_is_imm14 (ins->inst_offset)) {
1439                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1440                                 temp2->sreg1 = ins->inst_destbasereg;
1441                                 temp2->inst_imm = ins->inst_offset;
1442                                 temp2->dreg = mono_alloc_ireg (cfg);
1443                         }
1444                         else {
1445                                 NEW_INS (cfg, temp, OP_I8CONST);
1446                                 temp->inst_c0 = ins->inst_offset;
1447                                 temp->dreg = mono_alloc_ireg (cfg);
1448                                 NEW_INS (cfg, temp2, OP_LADD);
1449                                 temp2->sreg1 = ins->inst_destbasereg;
1450                                 temp2->sreg2 = temp->dreg;
1451                                 temp2->dreg = mono_alloc_ireg (cfg);
1452                         }
1453
1454                         ins->inst_offset = 0;
1455                         ins->inst_destbasereg = temp2->dreg;
1456                         break;
1457                 case OP_LOADI1_MEMBASE:
1458                 case OP_LOADU1_MEMBASE:
1459                 case OP_LOADI2_MEMBASE:
1460                 case OP_LOADU2_MEMBASE:
1461                 case OP_LOADI4_MEMBASE:
1462                 case OP_LOADU4_MEMBASE:
1463                 case OP_LOADI8_MEMBASE:
1464                 case OP_LOAD_MEMBASE:
1465                 case OP_LOADR4_MEMBASE:
1466                 case OP_LOADR8_MEMBASE:
1467                 case OP_ATOMIC_EXCHANGE_I4:
1468                 case OP_ATOMIC_EXCHANGE_I8:
1469                 case OP_ATOMIC_ADD_NEW_I4:
1470                 case OP_ATOMIC_ADD_NEW_I8:
1471                 case OP_ATOMIC_ADD_IMM_NEW_I4:
1472                 case OP_ATOMIC_ADD_IMM_NEW_I8:
1473                         /* There are no membase instructions on ia64 */
1474                         if (ins->inst_offset == 0) {
1475                                 break;
1476                         }
1477                         else if (ia64_is_imm14 (ins->inst_offset)) {
1478                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1479                                 temp2->sreg1 = ins->inst_basereg;
1480                                 temp2->inst_imm = ins->inst_offset;
1481                                 temp2->dreg = mono_alloc_ireg (cfg);
1482                         }
1483                         else {
1484                                 NEW_INS (cfg, temp, OP_I8CONST);
1485                                 temp->inst_c0 = ins->inst_offset;
1486                                 temp->dreg = mono_alloc_ireg (cfg);
1487                                 NEW_INS (cfg, temp2, OP_LADD);
1488                                 temp2->sreg1 = ins->inst_basereg;
1489                                 temp2->sreg2 = temp->dreg;
1490                                 temp2->dreg = mono_alloc_ireg (cfg);
1491                         }
1492
1493                         ins->inst_offset = 0;
1494                         ins->inst_basereg = temp2->dreg;
1495                         break;
1496                 case OP_ADD_IMM:
1497                 case OP_IADD_IMM:
1498                 case OP_LADD_IMM:
1499                 case OP_ISUB_IMM:
1500                 case OP_LSUB_IMM:
1501                 case OP_AND_IMM:
1502                 case OP_IAND_IMM:
1503                 case OP_LAND_IMM:
1504                 case OP_IOR_IMM:
1505                 case OP_LOR_IMM:
1506                 case OP_IXOR_IMM:
1507                 case OP_LXOR_IMM:
1508                 case OP_SHL_IMM:
1509                 case OP_SHR_IMM:
1510                 case OP_ISHL_IMM:
1511                 case OP_LSHL_IMM:
1512                 case OP_ISHR_IMM:
1513                 case OP_LSHR_IMM:
1514                 case OP_ISHR_UN_IMM:
1515                 case OP_LSHR_UN_IMM: {
1516                         gboolean is_imm = FALSE;
1517                         gboolean switched = FALSE;
1518
1519                         if (ins->opcode == OP_AND_IMM && ins->inst_imm == 255) {
1520                                 ins->opcode = OP_ZEXT_I1;
1521                                 break;
1522                         }
1523
1524                         switch (ins->opcode) {
1525                         case OP_ADD_IMM:
1526                         case OP_IADD_IMM:
1527                         case OP_LADD_IMM:
1528                                 is_imm = ia64_is_imm14 (ins->inst_imm);
1529                                 switched = TRUE;
1530                                 break;
1531                         case OP_ISUB_IMM:
1532                         case OP_LSUB_IMM:
1533                                 is_imm = ia64_is_imm14 (- (ins->inst_imm));
1534                                 if (is_imm) {
1535                                         /* A = B - IMM -> A = B + (-IMM) */
1536                                         ins->inst_imm = - ins->inst_imm;
1537                                         ins->opcode = OP_IADD_IMM;
1538                                 }
1539                                 switched = TRUE;
1540                                 break;
1541                         case OP_IAND_IMM:
1542                         case OP_IOR_IMM:
1543                         case OP_IXOR_IMM:
1544                         case OP_AND_IMM:
1545                         case OP_LAND_IMM:
1546                         case OP_LOR_IMM:
1547                         case OP_LXOR_IMM:
1548                                 is_imm = ia64_is_imm8 (ins->inst_imm);
1549                                 switched = TRUE;
1550                                 break;
1551                         case OP_SHL_IMM:
1552                         case OP_SHR_IMM:
1553                         case OP_ISHL_IMM:
1554                         case OP_LSHL_IMM:
1555                         case OP_ISHR_IMM:
1556                         case OP_LSHR_IMM:
1557                         case OP_ISHR_UN_IMM:
1558                         case OP_LSHR_UN_IMM:
1559                                 is_imm = (ins->inst_imm >= 0) && (ins->inst_imm < 64);
1560                                 break;
1561                         default:
1562                                 break;
1563                         }
1564
1565                         if (is_imm) {
1566                                 if (switched)
1567                                         ins->sreg2 = ins->sreg1;
1568                                 break;
1569                         }
1570
1571                         ins->opcode = mono_op_imm_to_op (ins->opcode);
1572
1573                         if (ins->inst_imm == 0)
1574                                 ins->sreg2 = IA64_R0;
1575                         else {
1576                                 NEW_INS (cfg, temp, OP_I8CONST);
1577                                 temp->inst_c0 = ins->inst_imm;
1578                                 temp->dreg = mono_alloc_ireg (cfg);
1579                                 ins->sreg2 = temp->dreg;
1580                         }
1581                         break;
1582                 }
1583                 case OP_COMPARE_IMM:
1584                 case OP_ICOMPARE_IMM:
1585                 case OP_LCOMPARE_IMM: {
1586                         /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1587                         gboolean imm;
1588                         CompRelation cond;
1589
1590                         next = ins->next;
1591
1592                         /* Branch opts can eliminate the branch */
1593                         if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1594                                 NULLIFY_INS (ins);
1595                                 break;
1596                         }
1597
1598                         /*
1599                          * The compare_imm instructions have switched up arguments, and
1600                          * some of them take an imm between -127 and 128.
1601                          */
1602                         next = ins->next;
1603                         cond = mono_opcode_to_cond (next->opcode);
1604                         if ((cond == CMP_LT) || (cond == CMP_GE))
1605                                 imm = ia64_is_imm8 (ins->inst_imm - 1);
1606                         else if ((cond == CMP_LT_UN) || (cond == CMP_GE_UN))
1607                                 imm = ia64_is_imm8 (ins->inst_imm - 1) && (ins->inst_imm > 0);
1608                         else
1609                                 imm = ia64_is_imm8 (ins->inst_imm);
1610
1611                         if (imm) {
1612                                 ins->opcode = opcode_to_ia64_cmp_imm (next->opcode, ins->opcode);
1613                                 ins->sreg2 = ins->sreg1;
1614                         }
1615                         else {
1616                                 ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1617
1618                                 if (ins->inst_imm == 0)
1619                                         ins->sreg2 = IA64_R0;
1620                                 else {
1621                                         NEW_INS (cfg, temp, OP_I8CONST);
1622                                         temp->inst_c0 = ins->inst_imm;
1623                                         temp->dreg = mono_alloc_ireg (cfg);
1624                                         ins->sreg2 = temp->dreg;
1625                                 }
1626                         }
1627
1628                         if (MONO_IS_COND_BRANCH_OP (next)) {
1629                                 next->opcode = OP_IA64_BR_COND;
1630                                 if (! (next->flags & MONO_INST_BRLABEL))
1631                                         next->inst_target_bb = next->inst_true_bb;
1632                         } else if (MONO_IS_COND_EXC (next)) {
1633                                 next->opcode = OP_IA64_COND_EXC;
1634                         } else if (MONO_IS_SETCC (next)) {
1635                                 next->opcode = OP_IA64_CSET;
1636                         } else {
1637                                 printf ("%s\n", mono_inst_name (next->opcode));
1638                                 NOT_IMPLEMENTED;
1639                         }
1640
1641                         break;
1642                 }
1643                 case OP_COMPARE:
1644                 case OP_ICOMPARE:
1645                 case OP_LCOMPARE:
1646                 case OP_FCOMPARE: {
1647                         /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1648
1649                         next = ins->next;
1650
1651                         /* Branch opts can eliminate the branch */
1652                         if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1653                                 NULLIFY_INS (ins);
1654                                 break;
1655                         }
1656
1657                         ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1658
1659                         if (MONO_IS_COND_BRANCH_OP (next)) {
1660                                 next->opcode = OP_IA64_BR_COND;
1661                                 if (! (next->flags & MONO_INST_BRLABEL))
1662                                         next->inst_target_bb = next->inst_true_bb;
1663                         } else if (MONO_IS_COND_EXC (next)) {
1664                                 next->opcode = OP_IA64_COND_EXC;
1665                         } else if (MONO_IS_SETCC (next)) {
1666                                 next->opcode = OP_IA64_CSET;
1667                         } else {
1668                                 printf ("%s\n", mono_inst_name (next->opcode));
1669                                 NOT_IMPLEMENTED;
1670                         }
1671
1672                         break;
1673                 }
1674                 case OP_FCEQ:
1675                 case OP_FCGT:
1676                 case OP_FCGT_UN:
1677                 case OP_FCLT:
1678                 case OP_FCLT_UN:
1679                         /* The front end removes the fcompare, so introduce it again */
1680                         NEW_INS (cfg, temp, opcode_to_ia64_cmp (ins->opcode, OP_FCOMPARE));
1681                         temp->sreg1 = ins->sreg1;
1682                         temp->sreg2 = ins->sreg2;
1683
1684                         ins->opcode = OP_IA64_CSET;
1685                         break;
1686                 case OP_MUL_IMM:
1687                 case OP_LMUL_IMM:
1688                 case OP_IMUL_IMM: {
1689                         int i, sum_reg;
1690                         gboolean found = FALSE;
1691                         int shl_op = ins->opcode == OP_IMUL_IMM ? OP_ISHL_IMM : OP_SHL_IMM;
1692
1693                         /* First the easy cases */
1694                         if (ins->inst_imm == 1) {
1695                                 ins->opcode = OP_MOVE;
1696                                 break;
1697                         }
1698                         for (i = 1; i < 64; ++i)
1699                                 if (ins->inst_imm == (((gint64)1) << i)) {
1700                                         ins->opcode = shl_op;
1701                                         ins->inst_imm = i;
1702                                         found = TRUE;
1703                                         break;
1704                                 }
1705
1706                         /* This could be optimized */
1707                         if (!found) {
1708                                 sum_reg = 0;
1709                                 for (i = 0; i < 64; ++i) {
1710                                         if (ins->inst_imm & (((gint64)1) << i)) {
1711                                                 NEW_INS (cfg, temp, shl_op);
1712                                                 temp->dreg = mono_alloc_ireg (cfg);
1713                                                 temp->sreg1 = ins->sreg1;
1714                                                 temp->inst_imm = i;
1715
1716                                                 if (sum_reg == 0)
1717                                                         sum_reg = temp->dreg;
1718                                                 else {
1719                                                         NEW_INS (cfg, temp2, OP_LADD);
1720                                                         temp2->dreg = mono_alloc_ireg (cfg);
1721                                                         temp2->sreg1 = sum_reg;
1722                                                         temp2->sreg2 = temp->dreg;
1723                                                         sum_reg = temp2->dreg;
1724                                                 }
1725                                         }
1726                                 }
1727                                 ins->opcode = OP_MOVE;
1728                                 ins->sreg1 = sum_reg;
1729                         }
1730                         break;
1731                 }
1732                 case OP_LCONV_TO_OVF_U4:
1733                         NEW_INS (cfg, temp, OP_IA64_CMP4_LT);
1734                         temp->sreg1 = ins->sreg1;
1735                         temp->sreg2 = IA64_R0;
1736
1737                         NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1738                         temp->inst_p1 = (char*)"OverflowException";
1739
1740                         ins->opcode = OP_MOVE;
1741                         break;
1742                 case OP_LCONV_TO_OVF_I4_UN:
1743                         NEW_INS (cfg, temp, OP_ICONST);
1744                         temp->inst_c0 = 0x7fffffff;
1745                         temp->dreg = mono_alloc_ireg (cfg);
1746
1747                         NEW_INS (cfg, temp2, OP_IA64_CMP4_GT_UN);
1748                         temp2->sreg1 = ins->sreg1;
1749                         temp2->sreg2 = temp->dreg;
1750
1751                         NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1752                         temp->inst_p1 = (char*)"OverflowException";
1753
1754                         ins->opcode = OP_MOVE;
1755                         break;
1756                 case OP_FCONV_TO_I4:
1757                 case OP_FCONV_TO_I2:
1758                 case OP_FCONV_TO_U2:
1759                 case OP_FCONV_TO_I1:
1760                 case OP_FCONV_TO_U1:
1761                         NEW_INS (cfg, temp, OP_FCONV_TO_I8);
1762                         temp->sreg1 = ins->sreg1;
1763                         temp->dreg = ins->dreg;
1764
1765                         switch (ins->opcode) {
1766                         case OP_FCONV_TO_I4:
1767                                 ins->opcode = OP_SEXT_I4;
1768                                 break;
1769                         case OP_FCONV_TO_I2:
1770                                 ins->opcode = OP_SEXT_I2;
1771                                 break;
1772                         case OP_FCONV_TO_U2:
1773                                 ins->opcode = OP_ZEXT_I4;
1774                                 break;
1775                         case OP_FCONV_TO_I1:
1776                                 ins->opcode = OP_SEXT_I1;
1777                                 break;
1778                         case OP_FCONV_TO_U1:
1779                                 ins->opcode = OP_ZEXT_I1;
1780                                 break;
1781                         default:
1782                                 g_assert_not_reached ();
1783                         }
1784                         ins->sreg1 = ins->dreg;
1785                         break;
1786                 default:
1787                         break;
1788                 }
1789                 last_ins = ins;
1790                 ins = ins->next;
1791         }
1792         bb->last_ins = last_ins;
1793
1794         bb->max_vreg = cfg->next_vreg;
1795 }
1796
1797 /*
1798  * emit_load_volatile_arguments:
1799  *
1800  *  Load volatile arguments from the stack to the original input registers.
1801  * Required before a tail call.
1802  */
1803 static Ia64CodegenState
1804 emit_load_volatile_arguments (MonoCompile *cfg, Ia64CodegenState code)
1805 {
1806         MonoMethod *method = cfg->method;
1807         MonoMethodSignature *sig;
1808         MonoInst *ins;
1809         CallInfo *cinfo;
1810         guint32 i;
1811
1812         /* FIXME: Generate intermediate code instead */
1813
1814         sig = mono_method_signature (method);
1815
1816         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
1817
1818         /* This is the opposite of the code in emit_prolog */
1819         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1820                 ArgInfo *ainfo = cinfo->args + i;
1821                 gint32 stack_offset;
1822                 MonoType *arg_type;
1823
1824                 ins = cfg->args [i];
1825
1826                 if (sig->hasthis && (i == 0))
1827                         arg_type = &mono_defaults.object_class->byval_arg;
1828                 else
1829                         arg_type = sig->params [i - sig->hasthis];
1830
1831                 arg_type = mono_type_get_underlying_type (arg_type);
1832
1833                 stack_offset = ainfo->offset + ARGS_OFFSET;
1834
1835                 /* Save volatile arguments to the stack */
1836                 if (ins->opcode != OP_REGVAR) {
1837                         switch (ainfo->storage) {
1838                         case ArgInIReg:
1839                         case ArgInFloatReg:
1840                                 /* FIXME: big offsets */
1841                                 g_assert (ins->opcode == OP_REGOFFSET);
1842                                 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
1843                                 if (arg_type->byref)
1844                                         ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1845                                 else {
1846                                         switch (arg_type->type) {
1847                                         case MONO_TYPE_R4:
1848                                                 ia64_ldfs (code, ainfo->reg, GP_SCRATCH_REG);
1849                                                 break;
1850                                         case MONO_TYPE_R8:
1851                                                 ia64_ldfd (code, ainfo->reg, GP_SCRATCH_REG);
1852                                                 break;
1853                                         default:
1854                                                 ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1855                                                 break;
1856                                         }
1857                                 }
1858                                 break;
1859                         case ArgOnStack:
1860                                 break;
1861                         default:
1862                                 NOT_IMPLEMENTED;
1863                         }
1864                 }
1865
1866                 if (ins->opcode == OP_REGVAR) {
1867                         /* Argument allocated to (non-volatile) register */
1868                         switch (ainfo->storage) {
1869                         case ArgInIReg:
1870                                 if (ins->dreg != cfg->arch.reg_in0 + ainfo->reg)
1871                                         ia64_mov (code, cfg->arch.reg_in0 + ainfo->reg, ins->dreg);
1872                                 break;
1873                         case ArgOnStack:
1874                                 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
1875                                 ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
1876                                 break;
1877                         default:
1878                                 NOT_IMPLEMENTED;
1879                         }
1880                 }
1881         }
1882
1883         return code;
1884 }
1885
1886 static Ia64CodegenState
1887 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, Ia64CodegenState code)
1888 {
1889         CallInfo *cinfo;
1890         int i;
1891
1892         /* Move return value to the target register */
1893         switch (ins->opcode) {
1894         case OP_VOIDCALL:
1895         case OP_VOIDCALL_REG:
1896         case OP_VOIDCALL_MEMBASE:
1897                 break;
1898         case OP_CALL:
1899         case OP_CALL_REG:
1900         case OP_CALL_MEMBASE:
1901         case OP_LCALL:
1902         case OP_LCALL_REG:
1903         case OP_LCALL_MEMBASE:
1904                 g_assert (ins->dreg == IA64_R8);
1905                 break;
1906         case OP_FCALL:
1907         case OP_FCALL_REG:
1908         case OP_FCALL_MEMBASE:
1909                 g_assert (ins->dreg == 8);
1910                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4)
1911                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
1912                 break;
1913         case OP_VCALL:
1914         case OP_VCALL_REG:
1915         case OP_VCALL_MEMBASE:
1916         case OP_VCALL2:
1917         case OP_VCALL2_REG:
1918         case OP_VCALL2_MEMBASE: {
1919                 ArgStorage storage;
1920
1921                 cinfo = get_call_info (cfg, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
1922                 storage = cinfo->ret.storage;
1923
1924                 if (storage == ArgAggregate) {
1925                         MonoInst *local = (MonoInst*)cfg->arch.ret_var_addr_local;
1926
1927                         /* Load address of stack space allocated for the return value */
1928                         ia64_movl (code, GP_SCRATCH_REG, local->inst_offset);
1929                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, local->inst_basereg);
1930                         ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
1931
1932                         for (i = 0; i < cinfo->ret.nregs; ++i) {
1933                                 switch (cinfo->ret.atype) {
1934                                 case AggregateNormal:
1935                                         ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1936                                         break;
1937                                 case AggregateSingleHFA:
1938                                         ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 4, 0);
1939                                         break;
1940                                 case AggregateDoubleHFA:
1941                                         ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1942                                         break;
1943                                 default:
1944                                         g_assert_not_reached ();
1945                                 }
1946                         }
1947                 }
1948                 break;
1949         }
1950         default:
1951                 g_assert_not_reached ();
1952         }
1953
1954         return code;
1955 }
1956
1957 #define add_patch_info(cfg,code,patch_type,data) do { \
1958         mono_add_patch_info (cfg, code.buf + code.nins - cfg->native_code, patch_type, data); \
1959 } while (0)
1960
1961 #define emit_cond_system_exception(cfg,code,exc_name,predicate) do { \
1962         MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1963     if (tins == NULL) \
1964         add_patch_info (cfg, code, MONO_PATCH_INFO_EXC, exc_name); \
1965     else \
1966                 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, tins->inst_true_bb); \
1967         ia64_br_cond_pred (code, (predicate), 0); \
1968 } while (0)
1969
1970 static Ia64CodegenState
1971 emit_call (MonoCompile *cfg, Ia64CodegenState code, guint32 patch_type, gconstpointer data)
1972 {
1973         add_patch_info (cfg, code, patch_type, data);
1974
1975         if ((patch_type == MONO_PATCH_INFO_ABS) || (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD)) {
1976                 /* Indirect call */
1977                 /* mono_arch_patch_callsite will patch this */
1978                 /* mono_arch_nullify_class_init_trampoline will patch this */
1979                 ia64_movl (code, GP_SCRATCH_REG, 0);
1980                 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
1981                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
1982                 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
1983                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
1984         }
1985         else {
1986                 /* Can't use a direct call since the displacement might be too small */
1987                 /* mono_arch_patch_callsite will patch this */
1988                 ia64_movl (code, GP_SCRATCH_REG, 0);
1989                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
1990                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
1991         }
1992
1993         return code;
1994 }
1995
1996 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
1997
1998 void
1999 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2000 {
2001         MonoInst *ins;
2002         MonoCallInst *call;
2003         guint offset;
2004         Ia64CodegenState code;
2005         guint8 *code_start = cfg->native_code + cfg->code_len;
2006         MonoInst *last_ins = NULL;
2007         guint last_offset = 0;
2008         int max_len, cpos;
2009
2010         if (cfg->opt & MONO_OPT_LOOP) {
2011                 /* FIXME: */
2012         }
2013
2014         if (cfg->verbose_level > 2)
2015                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2016
2017         cpos = bb->max_offset;
2018
2019         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2020                 NOT_IMPLEMENTED;
2021         }
2022
2023         offset = code_start - cfg->native_code;
2024
2025         ia64_codegen_init (code, code_start);
2026
2027 #if 0
2028         if (strstr (cfg->method->name, "conv_ovf_i1") && (bb->block_num == 2))
2029                 break_count ();
2030 #endif
2031
2032         MONO_BB_FOR_EACH_INS (bb, ins) {
2033                 offset = code.buf - cfg->native_code;
2034
2035                 max_len = ((int)(((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN])) + 128;
2036
2037                 while (offset + max_len + 16 > cfg->code_size) {
2038                         ia64_codegen_close (code);
2039
2040                         offset = code.buf - cfg->native_code;
2041
2042                         cfg->code_size *= 2;
2043                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2044                         code_start = cfg->native_code + offset;
2045                         mono_jit_stats.code_reallocs++;
2046
2047                         ia64_codegen_init (code, code_start);
2048                 }
2049
2050                 mono_debug_record_line_number (cfg, ins, offset);
2051
2052                 switch (ins->opcode) {
2053                 case OP_ICONST:
2054                 case OP_I8CONST:
2055                         if (ia64_is_imm14 (ins->inst_c0))
2056                                 ia64_adds_imm (code, ins->dreg, ins->inst_c0, IA64_R0);
2057                         else
2058                                 ia64_movl (code, ins->dreg, ins->inst_c0);
2059                         break;
2060                 case OP_JUMP_TABLE:
2061                         add_patch_info (cfg, code, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2062                         ia64_movl (code, ins->dreg, 0);
2063                         break;
2064                 case OP_MOVE:
2065                         ia64_mov (code, ins->dreg, ins->sreg1);
2066                         break;
2067                 case OP_BR:
2068                 case OP_IA64_BR_COND: {
2069                         int pred = 0;
2070                         if (ins->opcode == OP_IA64_BR_COND)
2071                                 pred = 6;
2072                         if (ins->flags & MONO_INST_BRLABEL) {
2073                                 if (ins->inst_i0->inst_c0) {
2074                                         NOT_IMPLEMENTED;
2075                                 } else {
2076                                         add_patch_info (cfg, code, MONO_PATCH_INFO_LABEL, ins->inst_i0);
2077                                         ia64_br_cond_pred (code, pred, 0);
2078                                 }
2079                         } else {
2080                                 if (ins->inst_target_bb->native_offset) {
2081                                         guint8 *pos = code.buf + code.nins;
2082
2083                                         ia64_br_cond_pred (code, pred, 0);
2084                                         ia64_begin_bundle (code);
2085                                         ia64_patch (pos, cfg->native_code + ins->inst_target_bb->native_offset);
2086                                 } else {
2087                                         add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2088                                         ia64_br_cond_pred (code, pred, 0);
2089                                 }
2090                         }
2091                         break;
2092                 }
2093                 case OP_LABEL:
2094                         ia64_begin_bundle (code);
2095                         ins->inst_c0 = code.buf - cfg->native_code;
2096                         break;
2097                 case OP_NOP:
2098                 case OP_RELAXED_NOP:
2099                 case OP_DUMMY_USE:
2100                 case OP_DUMMY_STORE:
2101                 case OP_NOT_REACHED:
2102                 case OP_NOT_NULL:
2103                         break;
2104                 case OP_BR_REG:
2105                         ia64_mov_to_br (code, IA64_B6, ins->sreg1);
2106                         ia64_br_cond_reg (code, IA64_B6);
2107                         break;
2108                 case OP_IADD:
2109                 case OP_LADD:
2110                         ia64_add (code, ins->dreg, ins->sreg1, ins->sreg2);
2111                         break;
2112                 case OP_ISUB:
2113                 case OP_LSUB:
2114                         ia64_sub (code, ins->dreg, ins->sreg1, ins->sreg2);
2115                         break;
2116                 case OP_IAND:
2117                 case OP_LAND:
2118                         ia64_and (code, ins->dreg, ins->sreg1, ins->sreg2);
2119                         break;
2120                 case OP_IOR:
2121                 case OP_LOR:
2122                         ia64_or (code, ins->dreg, ins->sreg1, ins->sreg2);
2123                         break;
2124                 case OP_IXOR:
2125                 case OP_LXOR:
2126                         ia64_xor (code, ins->dreg, ins->sreg1, ins->sreg2);
2127                         break;
2128                 case OP_INEG:
2129                 case OP_LNEG:
2130                         ia64_sub (code, ins->dreg, IA64_R0, ins->sreg1);
2131                         break;
2132                 case OP_INOT:
2133                 case OP_LNOT:
2134                         ia64_andcm_imm (code, ins->dreg, -1, ins->sreg1);
2135                         break;
2136                 case OP_ISHL:
2137                 case OP_LSHL:
2138                         ia64_shl (code, ins->dreg, ins->sreg1, ins->sreg2);
2139                         break;
2140                 case OP_ISHR:
2141                 case OP_LSHR:
2142                         ia64_shr (code, ins->dreg, ins->sreg1, ins->sreg2);
2143                         break;
2144                 case OP_ISHR_UN:
2145                         ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2146                         ia64_shr_u (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2147                         break;
2148                 case OP_LSHR_UN:
2149                         ia64_shr_u (code, ins->dreg, ins->sreg1, ins->sreg2);
2150                         break;
2151                 case OP_IADDCC:
2152                         /* p6 and p7 is set if there is signed/unsigned overflow */
2153
2154                         /* Set p8-p9 == (sreg2 > 0) */
2155                         ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2156
2157                         ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2158
2159                         /* (sreg2 > 0) && (res < ins->sreg1) => signed overflow */
2160                         ia64_cmp4_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2161                         /* (sreg2 <= 0) && (res > ins->sreg1) => signed overflow */
2162                         ia64_cmp4_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2163
2164                         /* res <u sreg1 => unsigned overflow */
2165                         ia64_cmp4_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2166
2167                         /* FIXME: Predicate this since this is a side effect */
2168                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2169                         break;
2170                 case OP_ISUBCC:
2171                         /* p6 and p7 is set if there is signed/unsigned overflow */
2172
2173                         /* Set p8-p9 == (sreg2 > 0) */
2174                         ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2175
2176                         ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2177
2178                         /* (sreg2 > 0) && (res > ins->sreg1) => signed overflow */
2179                         ia64_cmp4_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2180                         /* (sreg2 <= 0) && (res < ins->sreg1) => signed overflow */
2181                         ia64_cmp4_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2182
2183                         /* sreg1 <u sreg2 => unsigned overflow */
2184                         ia64_cmp4_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2185
2186                         /* FIXME: Predicate this since this is a side effect */
2187                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2188                         break;
2189                 case OP_ADDCC:
2190                         /* Same as OP_IADDCC */
2191                         ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2192
2193                         ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2194
2195                         ia64_cmp_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2196                         ia64_cmp_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2197
2198                         ia64_cmp_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2199
2200                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2201                         break;
2202                 case OP_SUBCC:
2203                         /* Same as OP_ISUBCC */
2204
2205                         ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2206
2207                         ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2208
2209                         ia64_cmp_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2210                         ia64_cmp_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2211
2212                         ia64_cmp_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2213
2214                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2215                         break;
2216                 case OP_ADD_IMM:
2217                 case OP_IADD_IMM:
2218                 case OP_LADD_IMM:
2219                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2220                         break;
2221                 case OP_IAND_IMM:
2222                 case OP_AND_IMM:
2223                 case OP_LAND_IMM:
2224                         ia64_and_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2225                         break;
2226                 case OP_IOR_IMM:
2227                 case OP_LOR_IMM:
2228                         ia64_or_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2229                         break;
2230                 case OP_IXOR_IMM:
2231                 case OP_LXOR_IMM:
2232                         ia64_xor_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2233                         break;
2234                 case OP_SHL_IMM:
2235                 case OP_ISHL_IMM:
2236                 case OP_LSHL_IMM:
2237                         ia64_shl_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2238                         break;
2239                 case OP_SHR_IMM:
2240                 case OP_ISHR_IMM:
2241                 case OP_LSHR_IMM:
2242                         ia64_shr_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2243                         break;
2244                 case OP_ISHR_UN_IMM:
2245                         ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2246                         ia64_shr_u_imm (code, ins->dreg, GP_SCRATCH_REG, ins->inst_imm);
2247                         break;
2248                 case OP_LSHR_UN_IMM:
2249                         ia64_shr_u_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2250                         break;
2251                 case OP_LMUL:
2252                         /* Based on gcc code */
2253                         ia64_setf_sig (code, FP_SCRATCH_REG, ins->sreg1);
2254                         ia64_setf_sig (code, FP_SCRATCH_REG2, ins->sreg2);
2255                         ia64_xmpy_l (code, FP_SCRATCH_REG, FP_SCRATCH_REG, FP_SCRATCH_REG2);
2256                         ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2257                         break;
2258
2259                 case OP_STOREI1_MEMBASE_REG:
2260                         ia64_st1_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2261                         break;
2262                 case OP_STOREI2_MEMBASE_REG:
2263                         ia64_st2_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2264                         break;
2265                 case OP_STOREI4_MEMBASE_REG:
2266                         ia64_st4_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2267                         break;
2268                 case OP_STOREI8_MEMBASE_REG:
2269                 case OP_STORE_MEMBASE_REG:
2270                         if (ins->inst_offset != 0) {
2271                                 /* This is generated by local regalloc */
2272                                 if (ia64_is_imm14 (ins->inst_offset)) {
2273                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2274                                 } else {
2275                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2276                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2277                                 }
2278                                 ins->inst_destbasereg = GP_SCRATCH_REG;
2279                         }
2280                         ia64_st8_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2281                         break;
2282
2283                 case OP_IA64_STOREI1_MEMBASE_INC_REG:
2284                         ia64_st1_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 1, 0);
2285                         break;
2286                 case OP_IA64_STOREI2_MEMBASE_INC_REG:
2287                         ia64_st2_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 2, 0);
2288                         break;
2289                 case OP_IA64_STOREI4_MEMBASE_INC_REG:
2290                         ia64_st4_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 4, 0);
2291                         break;
2292                 case OP_IA64_STOREI8_MEMBASE_INC_REG:
2293                         ia64_st8_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 8, 0);
2294                         break;
2295
2296                 case OP_LOADU1_MEMBASE:
2297                         ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2298                         break;
2299                 case OP_LOADU2_MEMBASE:
2300                         ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2301                         break;
2302                 case OP_LOADU4_MEMBASE:
2303                         ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2304                         break;
2305                 case OP_LOADI1_MEMBASE:
2306                         ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2307                         ia64_sxt1 (code, ins->dreg, ins->dreg);
2308                         break;
2309                 case OP_LOADI2_MEMBASE:
2310                         ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2311                         ia64_sxt2 (code, ins->dreg, ins->dreg);
2312                         break;
2313                 case OP_LOADI4_MEMBASE:
2314                         ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2315                         ia64_sxt4 (code, ins->dreg, ins->dreg);
2316                         break;
2317                 case OP_LOAD_MEMBASE:
2318                 case OP_LOADI8_MEMBASE:
2319                         if (ins->inst_offset != 0) {
2320                                 /* This is generated by local regalloc */
2321                                 if (ia64_is_imm14 (ins->inst_offset)) {
2322                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2323                                 } else {
2324                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2325                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2326                                 }
2327                                 ins->inst_basereg = GP_SCRATCH_REG;
2328                         }
2329                         ia64_ld8 (code, ins->dreg, ins->inst_basereg);
2330                         break;
2331
2332                 case OP_IA64_LOADU1_MEMBASE_INC:
2333                         ia64_ld1_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 1, 0);
2334                         break;
2335                 case OP_IA64_LOADU2_MEMBASE_INC:
2336                         ia64_ld2_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 2, 0);
2337                         break;
2338                 case OP_IA64_LOADU4_MEMBASE_INC:
2339                         ia64_ld4_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 4, 0);
2340                         break;
2341                 case OP_IA64_LOADI8_MEMBASE_INC:
2342                         ia64_ld8_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 8, 0);
2343                         break;
2344
2345                 case OP_SEXT_I1:
2346                         ia64_sxt1 (code, ins->dreg, ins->sreg1);
2347                         break;
2348                 case OP_SEXT_I2:
2349                         ia64_sxt2 (code, ins->dreg, ins->sreg1);
2350                         break;
2351                 case OP_SEXT_I4:
2352                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2353                         break;
2354                 case OP_ZEXT_I1:
2355                         ia64_zxt1 (code, ins->dreg, ins->sreg1);
2356                         break;
2357                 case OP_ZEXT_I2:
2358                         ia64_zxt2 (code, ins->dreg, ins->sreg1);
2359                         break;
2360                 case OP_ZEXT_I4:
2361                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2362                         break;
2363
2364                         /* Compare opcodes */
2365                 case OP_IA64_CMP4_EQ:
2366                         ia64_cmp4_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2367                         break;
2368                 case OP_IA64_CMP4_NE:
2369                         ia64_cmp4_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2370                         break;
2371                 case OP_IA64_CMP4_LE:
2372                         ia64_cmp4_le (code, 6, 7, ins->sreg1, ins->sreg2);
2373                         break;
2374                 case OP_IA64_CMP4_LT:
2375                         ia64_cmp4_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2376                         break;
2377                 case OP_IA64_CMP4_GE:
2378                         ia64_cmp4_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2379                         break;
2380                 case OP_IA64_CMP4_GT:
2381                         ia64_cmp4_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2382                         break;
2383                 case OP_IA64_CMP4_LT_UN:
2384                         ia64_cmp4_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2385                         break;
2386                 case OP_IA64_CMP4_LE_UN:
2387                         ia64_cmp4_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2388                         break;
2389                 case OP_IA64_CMP4_GT_UN:
2390                         ia64_cmp4_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2391                         break;
2392                 case OP_IA64_CMP4_GE_UN:
2393                         ia64_cmp4_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2394                         break;
2395                 case OP_IA64_CMP_EQ:
2396                         ia64_cmp_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2397                         break;
2398                 case OP_IA64_CMP_NE:
2399                         ia64_cmp_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2400                         break;
2401                 case OP_IA64_CMP_LE:
2402                         ia64_cmp_le (code, 6, 7, ins->sreg1, ins->sreg2);
2403                         break;
2404                 case OP_IA64_CMP_LT:
2405                         ia64_cmp_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2406                         break;
2407                 case OP_IA64_CMP_GE:
2408                         ia64_cmp_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2409                         break;
2410                 case OP_IA64_CMP_GT:
2411                         ia64_cmp_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2412                         break;
2413                 case OP_IA64_CMP_GT_UN:
2414                         ia64_cmp_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2415                         break;
2416                 case OP_IA64_CMP_LT_UN:
2417                         ia64_cmp_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2418                         break;
2419                 case OP_IA64_CMP_GE_UN:
2420                         ia64_cmp_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2421                         break;
2422                 case OP_IA64_CMP_LE_UN:
2423                         ia64_cmp_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2424                         break;
2425                 case OP_IA64_CMP4_EQ_IMM:
2426                         ia64_cmp4_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2427                         break;
2428                 case OP_IA64_CMP4_NE_IMM:
2429                         ia64_cmp4_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2430                         break;
2431                 case OP_IA64_CMP4_LE_IMM:
2432                         ia64_cmp4_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2433                         break;
2434                 case OP_IA64_CMP4_LT_IMM:
2435                         ia64_cmp4_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2436                         break;
2437                 case OP_IA64_CMP4_GE_IMM:
2438                         ia64_cmp4_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2439                         break;
2440                 case OP_IA64_CMP4_GT_IMM:
2441                         ia64_cmp4_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2442                         break;
2443                 case OP_IA64_CMP4_LT_UN_IMM:
2444                         ia64_cmp4_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2445                         break;
2446                 case OP_IA64_CMP4_LE_UN_IMM:
2447                         ia64_cmp4_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2448                         break;
2449                 case OP_IA64_CMP4_GT_UN_IMM:
2450                         ia64_cmp4_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2451                         break;
2452                 case OP_IA64_CMP4_GE_UN_IMM:
2453                         ia64_cmp4_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2454                         break;
2455                 case OP_IA64_CMP_EQ_IMM:
2456                         ia64_cmp_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2457                         break;
2458                 case OP_IA64_CMP_NE_IMM:
2459                         ia64_cmp_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2460                         break;
2461                 case OP_IA64_CMP_LE_IMM:
2462                         ia64_cmp_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2463                         break;
2464                 case OP_IA64_CMP_LT_IMM:
2465                         ia64_cmp_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2466                         break;
2467                 case OP_IA64_CMP_GE_IMM:
2468                         ia64_cmp_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2469                         break;
2470                 case OP_IA64_CMP_GT_IMM:
2471                         ia64_cmp_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2472                         break;
2473                 case OP_IA64_CMP_GT_UN_IMM:
2474                         ia64_cmp_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2475                         break;
2476                 case OP_IA64_CMP_LT_UN_IMM:
2477                         ia64_cmp_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2478                         break;
2479                 case OP_IA64_CMP_GE_UN_IMM:
2480                         ia64_cmp_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2481                         break;
2482                 case OP_IA64_CMP_LE_UN_IMM:
2483                         ia64_cmp_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2484                         break;
2485                 case OP_IA64_FCMP_EQ:
2486                         ia64_fcmp_eq_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2487                         break;
2488                 case OP_IA64_FCMP_NE:
2489                         ia64_fcmp_ne_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2490                         break;
2491                 case OP_IA64_FCMP_LT:
2492                         ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2493                         break;
2494                 case OP_IA64_FCMP_GT:
2495                         ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2496                         break;
2497                 case OP_IA64_FCMP_LE:
2498                         ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2499                         break;
2500                 case OP_IA64_FCMP_GE:
2501                         ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2502                         break;
2503                 case OP_IA64_FCMP_GT_UN:
2504                         ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2505                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2506                         break;
2507                 case OP_IA64_FCMP_LT_UN:
2508                         ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2509                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2510                         break;
2511                 case OP_IA64_FCMP_GE_UN:
2512                         ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2513                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2514                         break;
2515                 case OP_IA64_FCMP_LE_UN:
2516                         ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2517                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2518                         break;
2519
2520                 case OP_COND_EXC_IOV:
2521                 case OP_COND_EXC_OV:
2522                         emit_cond_system_exception (cfg, code, "OverflowException", 6);
2523                         break;
2524                 case OP_COND_EXC_IC:
2525                 case OP_COND_EXC_C:
2526                         emit_cond_system_exception (cfg, code, "OverflowException", 7);
2527                         break;
2528                 case OP_IA64_COND_EXC:
2529                         emit_cond_system_exception (cfg, code, ins->inst_p1, 6);
2530                         break;
2531                 case OP_IA64_CSET:
2532                         ia64_mov_pred (code, 7, ins->dreg, IA64_R0);
2533                         ia64_no_stop (code);
2534                         ia64_add1_pred (code, 6, ins->dreg, IA64_R0, IA64_R0);
2535                         break;
2536                 case OP_ICONV_TO_I1:
2537                 case OP_LCONV_TO_I1:
2538                         /* FIXME: Is this needed ? */
2539                         ia64_sxt1 (code, ins->dreg, ins->sreg1);
2540                         break;
2541                 case OP_ICONV_TO_I2:
2542                 case OP_LCONV_TO_I2:
2543                         /* FIXME: Is this needed ? */
2544                         ia64_sxt2 (code, ins->dreg, ins->sreg1);
2545                         break;
2546                 case OP_LCONV_TO_I4:
2547                         /* FIXME: Is this needed ? */
2548                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2549                         break;
2550                 case OP_ICONV_TO_U1:
2551                 case OP_LCONV_TO_U1:
2552                         /* FIXME: Is this needed */
2553                         ia64_zxt1 (code, ins->dreg, ins->sreg1);
2554                         break;
2555                 case OP_ICONV_TO_U2:
2556                 case OP_LCONV_TO_U2:
2557                         /* FIXME: Is this needed */
2558                         ia64_zxt2 (code, ins->dreg, ins->sreg1);
2559                         break;
2560                 case OP_LCONV_TO_U4:
2561                         /* FIXME: Is this needed */
2562                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2563                         break;
2564                 case OP_ICONV_TO_I8:
2565                 case OP_ICONV_TO_I:
2566                 case OP_LCONV_TO_I8:
2567                 case OP_LCONV_TO_I:
2568                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2569                         break;
2570                 case OP_LCONV_TO_U8:
2571                 case OP_LCONV_TO_U:
2572                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2573                         break;
2574
2575                         /*
2576                          * FLOAT OPCODES
2577                          */
2578                 case OP_R8CONST: {
2579                         double d = *(double *)ins->inst_p0;
2580
2581                         if ((d == 0.0) && (mono_signbit (d) == 0))
2582                                 ia64_fmov (code, ins->dreg, 0);
2583                         else if (d == 1.0)
2584                                 ia64_fmov (code, ins->dreg, 1);
2585                         else {
2586                                 add_patch_info (cfg, code, MONO_PATCH_INFO_R8, ins->inst_p0);
2587                                 ia64_movl (code, GP_SCRATCH_REG, 0);
2588                                 ia64_ldfd (code, ins->dreg, GP_SCRATCH_REG);
2589                         }
2590                         break;
2591                 }
2592                 case OP_R4CONST: {
2593                         float f = *(float *)ins->inst_p0;
2594
2595                         if ((f == 0.0) && (mono_signbit (f) == 0))
2596                                 ia64_fmov (code, ins->dreg, 0);
2597                         else if (f == 1.0)
2598                                 ia64_fmov (code, ins->dreg, 1);
2599                         else {
2600                                 add_patch_info (cfg, code, MONO_PATCH_INFO_R4, ins->inst_p0);
2601                                 ia64_movl (code, GP_SCRATCH_REG, 0);
2602                                 ia64_ldfs (code, ins->dreg, GP_SCRATCH_REG);
2603                         }
2604                         break;
2605                 }
2606                 case OP_FMOVE:
2607                         ia64_fmov (code, ins->dreg, ins->sreg1);
2608                         break;
2609                 case OP_STORER8_MEMBASE_REG:
2610                         if (ins->inst_offset != 0) {
2611                                 /* This is generated by local regalloc */
2612                                 if (ia64_is_imm14 (ins->inst_offset)) {
2613                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2614                                 } else {
2615                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2616                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2617                                 }
2618                                 ins->inst_destbasereg = GP_SCRATCH_REG;
2619                         }
2620                         ia64_stfd_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2621                         break;
2622                 case OP_STORER4_MEMBASE_REG:
2623                         ia64_fnorm_s_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2624                         ia64_stfs_hint (code, ins->inst_destbasereg, FP_SCRATCH_REG, 0);
2625                         break;
2626                 case OP_LOADR8_MEMBASE:
2627                         if (ins->inst_offset != 0) {
2628                                 /* This is generated by local regalloc */
2629                                 if (ia64_is_imm14 (ins->inst_offset)) {
2630                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2631                                 } else {
2632                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2633                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2634                                 }
2635                                 ins->inst_basereg = GP_SCRATCH_REG;
2636                         }
2637                         ia64_ldfd (code, ins->dreg, ins->inst_basereg);
2638                         break;
2639                 case OP_LOADR4_MEMBASE:
2640                         ia64_ldfs (code, ins->dreg, ins->inst_basereg);
2641                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2642                         break;
2643                 case OP_ICONV_TO_R4:
2644                 case OP_LCONV_TO_R4:
2645                         ia64_setf_sig (code, ins->dreg, ins->sreg1);
2646                         ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2647                         ia64_fnorm_s_sf (code, ins->dreg, ins->dreg, 0);
2648                         break;
2649                 case OP_ICONV_TO_R8:
2650                 case OP_LCONV_TO_R8:
2651                         ia64_setf_sig (code, ins->dreg, ins->sreg1);
2652                         ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2653                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2654                         break;
2655                 case OP_FCONV_TO_R4:
2656                         ia64_fnorm_s_sf (code, ins->dreg, ins->sreg1, 0);
2657                         break;
2658                 case OP_FCONV_TO_I8:
2659                 case OP_FCONV_TO_I:
2660                         ia64_fcvt_fx_trunc_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2661                         ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2662                         break;
2663                 case OP_FADD:
2664                         ia64_fma_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2665                         break;
2666                 case OP_FSUB:
2667                         ia64_fms_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2668                         break;
2669                 case OP_FMUL:
2670                         ia64_fma_d_sf (code, ins->dreg, ins->sreg1, ins->sreg2, 0, 0);
2671                         break;
2672                 case OP_FNEG:
2673                         ia64_fmerge_ns (code, ins->dreg, ins->sreg1, ins->sreg1);
2674                         break;
2675                 case OP_CKFINITE:
2676                         /* Quiet NaN */
2677                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x080);
2678                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2679                         /* Signaling NaN */
2680                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x040);
2681                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2682                         /* Positive infinity */
2683                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x021);
2684                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2685                         /* Negative infinity */
2686                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x022);
2687                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2688                         break;
2689
2690                 /* Calls */
2691                 case OP_CHECK_THIS:
2692                         /* ensure ins->sreg1 is not NULL */
2693                         ia64_ld8 (code, GP_SCRATCH_REG, ins->sreg1);
2694                         break;
2695                 case OP_ARGLIST:
2696                         ia64_adds_imm (code, GP_SCRATCH_REG, cfg->sig_cookie, cfg->frame_reg);
2697                         ia64_st8 (code, ins->sreg1, GP_SCRATCH_REG);
2698                         break;
2699                 case OP_FCALL:
2700                 case OP_LCALL:
2701                 case OP_VCALL:
2702                 case OP_VCALL2:
2703                 case OP_VOIDCALL:
2704                 case OP_CALL:
2705                         call = (MonoCallInst*)ins;
2706
2707                         if (ins->flags & MONO_INST_HAS_METHOD)
2708                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2709                         else
2710                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2711
2712                         code = emit_move_return_value (cfg, ins, code);
2713                         break;
2714
2715                 case OP_CALL_REG:
2716                 case OP_FCALL_REG:
2717                 case OP_LCALL_REG:
2718                 case OP_VCALL_REG:
2719                 case OP_VCALL2_REG:
2720                 case OP_VOIDCALL_REG: {
2721                         MonoCallInst *call = (MonoCallInst*)ins;
2722                         CallInfo *cinfo;
2723                         int out_reg;
2724
2725                         /*
2726                          * mono_arch_find_this_arg () needs to find the this argument in a global
2727                          * register.
2728                          */
2729                         cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2730                         out_reg = cfg->arch.reg_out0;
2731                         if (cinfo->ret.storage == ArgValuetypeAddrInIReg)
2732                                 out_reg ++;
2733                         ia64_mov (code, IA64_R10, out_reg);
2734
2735                         /* Indirect call */
2736                         ia64_mov (code, IA64_R8, ins->sreg1);
2737                         ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, IA64_R8, 8);
2738                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2739                         ia64_ld8 (code, IA64_GP, IA64_R8);
2740                         ia64_br_call_reg (code, IA64_B0, IA64_B6);
2741
2742                         code = emit_move_return_value (cfg, ins, code);
2743                         break;
2744                 }
2745                 case OP_FCALL_MEMBASE:
2746                 case OP_LCALL_MEMBASE:
2747                 case OP_VCALL_MEMBASE:
2748                 case OP_VCALL2_MEMBASE:
2749                 case OP_VOIDCALL_MEMBASE:
2750                 case OP_CALL_MEMBASE: {
2751                         MonoCallInst *call = (MonoCallInst*)ins;
2752                         CallInfo *cinfo;
2753                         int out_reg;
2754
2755                         /*
2756                          * There are no membase instructions on ia64, but we can't
2757                          * lower this since get_vcall_slot_addr () needs to decode it.
2758                          */
2759
2760                         /* Keep this in synch with get_vcall_slot_addr */
2761                         ia64_mov (code, IA64_R11, ins->sreg1);
2762                         if (ia64_is_imm14 (ins->inst_offset))
2763                                 ia64_adds_imm (code, IA64_R8, ins->inst_offset, ins->sreg1);
2764                         else {
2765                                 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2766                                 ia64_add (code, IA64_R8, GP_SCRATCH_REG, ins->sreg1);
2767                         }
2768
2769                         if (call->method && ins->inst_offset < 0) {
2770                                 /*
2771                                  * This is a possible IMT call so save the IMT method in a global
2772                                  * register where mono_arch_find_imt_method () and its friends can
2773                                  * access it.
2774                                  */
2775                                 ia64_movl (code, IA64_R9, call->method);
2776                         }
2777
2778                         /*
2779                          * mono_arch_find_this_arg () needs to find the this argument in a global
2780                          * register.
2781                          */
2782                         cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2783                         out_reg = cfg->arch.reg_out0;
2784                         if (cinfo->ret.storage == ArgValuetypeAddrInIReg)
2785                                 out_reg ++;
2786                         ia64_mov (code, IA64_R10, out_reg);
2787
2788                         ia64_begin_bundle (code);
2789                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2790
2791                         ia64_ld8 (code, GP_SCRATCH_REG, IA64_R8);
2792
2793                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2794
2795                         /*
2796                          * This nop will tell get_vcall_slot_addr that this is a virtual
2797                          * call.
2798                          */
2799                         ia64_nop_i (code, 0x12345);
2800
2801                         ia64_br_call_reg (code, IA64_B0, IA64_B6);
2802
2803                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2804
2805                         code = emit_move_return_value (cfg, ins, code);
2806                         break;
2807                 }
2808                 case OP_JMP: {
2809                         /*
2810                          * Keep in sync with the code in emit_epilog.
2811                          */
2812
2813                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2814                                 NOT_IMPLEMENTED;
2815
2816                         g_assert (!cfg->method->save_lmf);
2817
2818                         /* Load arguments into their original registers */
2819                         code = emit_load_volatile_arguments (cfg, code);
2820
2821                         if (cfg->arch.stack_alloc_size) {
2822                                 if (cfg->arch.omit_fp) {
2823                                         if (ia64_is_imm14 (cfg->arch.stack_alloc_size))
2824                                                 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
2825                                         else {
2826                                                 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
2827                                                 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
2828                                         }
2829                                 }
2830                                 else
2831                                         ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
2832                         }
2833                         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
2834                         ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
2835
2836                         add_patch_info (cfg, code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2837                         ia64_movl (code, GP_SCRATCH_REG, 0);
2838                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2839                         ia64_br_cond_reg (code, IA64_B6);
2840
2841                         break;
2842                 }
2843                 case OP_BREAK:
2844                         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, mono_break);
2845                         break;
2846
2847                 case OP_LOCALLOC: {
2848                         gint32 abi_offset;
2849
2850                         /* FIXME: Sigaltstack support */
2851
2852                         /* keep alignment */
2853                         ia64_adds_imm (code, GP_SCRATCH_REG, MONO_ARCH_LOCALLOC_ALIGNMENT - 1, ins->sreg1);
2854                         ia64_movl (code, GP_SCRATCH_REG2, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
2855                         ia64_and (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2856
2857                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2858
2859                         ia64_mov (code, ins->dreg, IA64_SP);
2860
2861                         /* An area at sp is reserved by the ABI for parameter passing */
2862                         abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_LOCALLOC_ALIGNMENT);
2863                         if (ia64_is_adds_imm (abi_offset))
2864                                 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2865                         else {
2866                                 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2867                                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2868                         }
2869
2870                         if (ins->flags & MONO_INST_INIT) {
2871                                 /* Upper limit */
2872                                 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2873
2874                                 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2875
2876                                 /* Init loop */
2877                                 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2878                                 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2879                                 ia64_br_cond_pred (code, 8, -2);
2880
2881                                 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2882
2883                                 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2884                         }
2885
2886                         break;
2887                 }
2888                 case OP_LOCALLOC_IMM: {
2889                         gint32 abi_offset;
2890
2891                         /* FIXME: Sigaltstack support */
2892
2893                         gssize size = ins->inst_imm;
2894                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
2895
2896                         if (ia64_is_adds_imm (size))
2897                                 ia64_adds_imm (code, GP_SCRATCH_REG, size, IA64_R0);
2898                         else
2899                                 ia64_movl (code, GP_SCRATCH_REG, size);
2900
2901                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2902                         ia64_mov (code, ins->dreg, IA64_SP);
2903
2904                         /* An area at sp is reserved by the ABI for parameter passing */
2905                         abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_FRAME_ALIGNMENT);
2906                         if (ia64_is_adds_imm (abi_offset))
2907                                 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2908                         else {
2909                                 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2910                                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2911                         }
2912
2913                         if (ins->flags & MONO_INST_INIT) {
2914                                 /* Upper limit */
2915                                 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2916
2917                                 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2918
2919                                 /* Init loop */
2920                                 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2921                                 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2922                                 ia64_br_cond_pred (code, 8, -2);
2923
2924                                 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2925
2926                                 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2927                         }
2928
2929                         break;
2930                 }
2931                 case OP_TLS_GET:
2932                         ia64_adds_imm (code, ins->dreg, ins->inst_offset, IA64_TP);
2933                         ia64_ld8 (code, ins->dreg, ins->dreg);
2934                         break;
2935
2936                         /* Synchronization */
2937                 case OP_MEMORY_BARRIER:
2938                         ia64_mf (code);
2939                         break;
2940                 case OP_ATOMIC_ADD_IMM_NEW_I4:
2941                         g_assert (ins->inst_offset == 0);
2942                         ia64_fetchadd4_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2943                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2944                         break;
2945                 case OP_ATOMIC_ADD_IMM_NEW_I8:
2946                         g_assert (ins->inst_offset == 0);
2947                         ia64_fetchadd8_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2948                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2949                         break;
2950                 case OP_ATOMIC_EXCHANGE_I4:
2951                         ia64_xchg4_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2952                         ia64_sxt4 (code, ins->dreg, ins->dreg);
2953                         break;
2954                 case OP_ATOMIC_EXCHANGE_I8:
2955                         ia64_xchg8_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2956                         break;
2957                 case OP_ATOMIC_ADD_NEW_I4: {
2958                         guint8 *label, *buf;
2959
2960                         /* From libatomic_ops */
2961                         ia64_mf (code);
2962
2963                         ia64_begin_bundle (code);
2964                         label = code.buf + code.nins;
2965                         ia64_ld4_acq (code, GP_SCRATCH_REG, ins->sreg1);
2966                         ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2967                         ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2968                         ia64_cmpxchg4_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2969                         ia64_cmp4_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2970                         buf = code.buf + code.nins;
2971                         ia64_br_cond_pred (code, 7, 0);
2972                         ia64_begin_bundle (code);
2973                         ia64_patch (buf, label);
2974                         ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2975                         break;
2976                 }
2977                 case OP_ATOMIC_ADD_NEW_I8: {
2978                         guint8 *label, *buf;
2979
2980                         /* From libatomic_ops */
2981                         ia64_mf (code);
2982
2983                         ia64_begin_bundle (code);
2984                         label = code.buf + code.nins;
2985                         ia64_ld8_acq (code, GP_SCRATCH_REG, ins->sreg1);
2986                         ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2987                         ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2988                         ia64_cmpxchg8_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2989                         ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2990                         buf = code.buf + code.nins;
2991                         ia64_br_cond_pred (code, 7, 0);
2992                         ia64_begin_bundle (code);
2993                         ia64_patch (buf, label);
2994                         ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2995                         break;
2996                 }
2997
2998                         /* Exception handling */
2999                 case OP_CALL_HANDLER:
3000                         /*
3001                          * Using a call instruction would mess up the register stack, so
3002                          * save the return address to a register and use a
3003                          * branch.
3004                          */
3005                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3006                         ia64_mov (code, IA64_R15, IA64_R0);
3007                         ia64_mov_from_ip (code, GP_SCRATCH_REG);
3008                         /* Add the length of OP_CALL_HANDLER */
3009                         ia64_adds_imm (code, GP_SCRATCH_REG, 5 * 16, GP_SCRATCH_REG);
3010                         add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3011                         ia64_movl (code, GP_SCRATCH_REG2, 0);
3012                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
3013                         ia64_br_cond_reg (code, IA64_B6);
3014                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3015                         break;
3016                 case OP_START_HANDLER: {
3017                         /*
3018                          * We receive the return address in GP_SCRATCH_REG.
3019                          */
3020                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3021
3022                         /*
3023                          * R15 determines our caller. It is used since it is writable using
3024                          * libunwind.
3025                          * R15 == 0 means we are called by OP_CALL_HANDLER or via resume_context ()
3026                          * R15 != 0 means we are called by call_filter ().
3027                          */
3028                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3029                         ia64_cmp_eq (code, 6, 7, IA64_R15, IA64_R0);
3030
3031                         ia64_br_cond_pred (code, 6, 6);
3032
3033                         /*
3034                          * Called by call_filter:
3035                          * Allocate a new stack frame, and set the fp register from the
3036                          * value passed in by the caller.
3037                          * We allocate a similar frame as is done by the prolog, so
3038                          * if an exception is thrown while executing the filter, the
3039                          * unwinder can unwind through the filter frame using the unwind
3040                          * info for the prolog.
3041                          */
3042                         ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3043                         ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3044                         ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3045                         ia64_mov (code, cfg->frame_reg, IA64_R15);
3046                         /* Signal to endfilter that we are called by call_filter */
3047                         ia64_mov (code, GP_SCRATCH_REG, IA64_R0);
3048
3049                         /* Branch target: */
3050                         if (ia64_is_imm14 (spvar->inst_offset))
3051                                 ia64_adds_imm (code, GP_SCRATCH_REG2, spvar->inst_offset, cfg->frame_reg);
3052                         else {
3053                                 ia64_movl (code, GP_SCRATCH_REG2, spvar->inst_offset);
3054                                 ia64_add (code, GP_SCRATCH_REG2, cfg->frame_reg, GP_SCRATCH_REG2);
3055                         }
3056
3057                         /* Save the return address */
3058                         ia64_st8_hint (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 0);
3059                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3060
3061                         break;
3062                 }
3063                 case OP_ENDFINALLY:
3064                 case OP_ENDFILTER: {
3065                         /* FIXME: Return the value in ENDFILTER */
3066                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3067
3068                         /* Load the return address */
3069                         if (ia64_is_imm14 (spvar->inst_offset)) {
3070                                 ia64_adds_imm (code, GP_SCRATCH_REG, spvar->inst_offset, cfg->frame_reg);
3071                         } else {
3072                                 ia64_movl (code, GP_SCRATCH_REG, spvar->inst_offset);
3073                                 ia64_add (code, GP_SCRATCH_REG, cfg->frame_reg, GP_SCRATCH_REG);
3074                         }
3075                         ia64_ld8_hint (code, GP_SCRATCH_REG, GP_SCRATCH_REG, 0);
3076
3077                         /* Test caller */
3078                         ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, IA64_R0);
3079                         ia64_br_cond_pred (code, 7, 4);
3080
3081                         /* Called by call_filter */
3082                         /* Pop frame */
3083                         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
3084                         ia64_mov_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
3085                         ia64_br_ret_reg (code, IA64_B0);
3086
3087                         /* Called by CALL_HANDLER */
3088                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
3089                         ia64_br_cond_reg (code, IA64_B6);
3090                         break;
3091                 }
3092                 case OP_THROW:
3093                         ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3094                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3095                                                           (gpointer)"mono_arch_throw_exception");
3096
3097                         /*
3098                          * This might be the last instruction in the method, so add a dummy
3099                          * instruction so the unwinder will work.
3100                          */
3101                         ia64_break_i (code, 0);
3102                         break;
3103                 case OP_RETHROW:
3104                         ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3105                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3106                                                           (gpointer)"mono_arch_rethrow_exception");
3107
3108                         ia64_break_i (code, 0);
3109                         break;
3110
3111                 default:
3112                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3113                         g_assert_not_reached ();
3114                 }
3115
3116                 if ((code.buf - cfg->native_code - offset) > max_len) {
3117                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3118                                    mono_inst_name (ins->opcode), max_len, code.buf - cfg->native_code - offset);
3119                         g_assert_not_reached ();
3120                 }
3121
3122                 cpos += max_len;
3123
3124                 last_ins = ins;
3125                 last_offset = offset;
3126         }
3127
3128         ia64_codegen_close (code);
3129
3130         cfg->code_len = code.buf - cfg->native_code;
3131 }
3132
3133 void
3134 mono_arch_register_lowlevel_calls (void)
3135 {
3136 }
3137
3138 static Ia64InsType ins_types_in_template [32][3] = {
3139         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3140         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3141         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3142         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3143         {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3144         {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3145         {0, 0, 0},
3146         {0, 0, 0},
3147         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3148         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3149         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3150         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3151         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3152         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3153         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3154         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3155         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3156         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3157         {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3158         {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3159         {0, 0, 0},
3160         {0, 0, 0},
3161         {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3162         {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3163         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3164         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3165         {0, 0, 0},
3166         {0, 0, 0},
3167         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3168         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3169         {0, 0, 0},
3170         {0, 0, 0}
3171 };
3172
3173 static gboolean stops_in_template [32][3] = {
3174         { FALSE, FALSE, FALSE },
3175         { FALSE, FALSE, TRUE },
3176         { FALSE, TRUE, FALSE },
3177         { FALSE, TRUE, TRUE },
3178         { FALSE, FALSE, FALSE },
3179         { FALSE, FALSE, TRUE },
3180         { FALSE, FALSE, FALSE },
3181         { FALSE, FALSE, FALSE },
3182
3183         { FALSE, FALSE, FALSE },
3184         { FALSE, FALSE, TRUE },
3185         { TRUE, FALSE, FALSE },
3186         { TRUE, FALSE, TRUE },
3187         { FALSE, FALSE, FALSE },
3188         { FALSE, FALSE, TRUE },
3189         { FALSE, FALSE, FALSE },
3190         { FALSE, FALSE, TRUE },
3191
3192         { FALSE, FALSE, FALSE },
3193         { FALSE, FALSE, TRUE },
3194         { FALSE, FALSE, FALSE },
3195         { FALSE, FALSE, TRUE },
3196         { FALSE, FALSE, FALSE },
3197         { FALSE, FALSE, FALSE },
3198         { FALSE, FALSE, FALSE },
3199         { FALSE, FALSE, TRUE },
3200
3201         { FALSE, FALSE, FALSE },
3202         { FALSE, FALSE, TRUE },
3203         { FALSE, FALSE, FALSE },
3204         { FALSE, FALSE, FALSE },
3205         { FALSE, FALSE, FALSE },
3206         { FALSE, FALSE, TRUE },
3207         { FALSE, FALSE, FALSE },
3208         { FALSE, FALSE, FALSE }
3209 };
3210
3211 static int last_stop_in_template [32] = {
3212         -1, 2, 1, 2, -1, 2, -1, -1,
3213         -1, 2, 0, 2, -1, 2, -1, 2,
3214         -1, 2, -1, 2, -1, -1, -1, 2,
3215         -1, 2, -1, -1, -1, 2, -1, -1
3216 };
3217
3218 static guint64 nops_for_ins_types [6] = {
3219         IA64_NOP_I,
3220         IA64_NOP_I,
3221         IA64_NOP_M,
3222         IA64_NOP_F,
3223         IA64_NOP_B,
3224         IA64_NOP_X
3225 };
3226
3227 #define ITYPE_MATCH(itype1, itype2) (((itype1) == (itype2)) || (((itype2) == IA64_INS_TYPE_A) && (((itype1) == IA64_INS_TYPE_I) || ((itype1) == IA64_INS_TYPE_M))))
3228
3229 /*
3230  * Debugging support
3231  */
3232
3233 #if 0
3234 #define DEBUG_INS_SCHED(a) do { a; } while (0)
3235 #else
3236 #define DEBUG_INS_SCHED(a)
3237 #endif
3238
3239 static void
3240 ia64_analyze_deps (Ia64CodegenState *code, int *deps_start, int *stops)
3241 {
3242         int i, pos, ins_index, current_deps_start, current_ins_start, reg;
3243         guint8 *deps = code->dep_info;
3244         gboolean need_stop, no_stop;
3245
3246         for (i = 0; i < code->nins; ++i)
3247                 stops [i] = FALSE;
3248
3249         ins_index = 0;
3250         current_deps_start = 0;
3251         current_ins_start = 0;
3252         deps_start [ins_index] = current_ins_start;
3253         pos = 0;
3254         no_stop = FALSE;
3255         DEBUG_INS_SCHED (printf ("BEGIN.\n"));
3256         while (pos < code->dep_info_pos) {
3257                 need_stop = FALSE;
3258                 switch (deps [pos]) {
3259                 case IA64_END_OF_INS:
3260                         ins_index ++;
3261                         current_ins_start = pos + 2;
3262                         deps_start [ins_index] = current_ins_start;
3263                         no_stop = FALSE;
3264                         DEBUG_INS_SCHED (printf ("(%d) END INS.\n", ins_index - 1));
3265                         break;
3266                 case IA64_NONE:
3267                         break;
3268                 case IA64_READ_GR:
3269                         reg = deps [pos + 1];
3270
3271                         DEBUG_INS_SCHED (printf ("READ GR: %d\n", reg));
3272                         for (i = current_deps_start; i < current_ins_start; i += 2)
3273                                 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3274                                         need_stop = TRUE;
3275                         break;
3276                 case IA64_WRITE_GR:
3277                         reg = code->dep_info [pos + 1];
3278
3279                         DEBUG_INS_SCHED (printf ("WRITE GR: %d\n", reg));
3280                         for (i = current_deps_start; i < current_ins_start; i += 2)
3281                                 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3282                                         need_stop = TRUE;
3283                         break;
3284                 case IA64_READ_PR:
3285                         reg = deps [pos + 1];
3286
3287                         DEBUG_INS_SCHED (printf ("READ PR: %d\n", reg));
3288                         for (i = current_deps_start; i < current_ins_start; i += 2)
3289                                 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3290                                         need_stop = TRUE;
3291                         break;
3292                 case IA64_READ_PR_BRANCH:
3293                         reg = deps [pos + 1];
3294
3295                         /* Writes to prs by non-float instructions are visible to branches */
3296                         DEBUG_INS_SCHED (printf ("READ PR BRANCH: %d\n", reg));
3297                         for (i = current_deps_start; i < current_ins_start; i += 2)
3298                                 if (deps [i] == IA64_WRITE_PR_FLOAT && deps [i + 1] == reg)
3299                                         need_stop = TRUE;
3300                         break;
3301                 case IA64_WRITE_PR:
3302                         reg = code->dep_info [pos + 1];
3303
3304                         DEBUG_INS_SCHED (printf ("WRITE PR: %d\n", reg));
3305                         for (i = current_deps_start; i < current_ins_start; i += 2)
3306                                 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3307                                         need_stop = TRUE;
3308                         break;
3309                 case IA64_WRITE_PR_FLOAT:
3310                         reg = code->dep_info [pos + 1];
3311
3312                         DEBUG_INS_SCHED (printf ("WRITE PR FP: %d\n", reg));
3313                         for (i = current_deps_start; i < current_ins_start; i += 2)
3314                                 if (((deps [i] == IA64_WRITE_GR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3315                                         need_stop = TRUE;
3316                         break;
3317                 case IA64_READ_BR:
3318                         reg = deps [pos + 1];
3319
3320                         DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3321                         for (i = current_deps_start; i < current_ins_start; i += 2)
3322                                 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3323                                         need_stop = TRUE;
3324                         break;
3325                 case IA64_WRITE_BR:
3326                         reg = code->dep_info [pos + 1];
3327
3328                         DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3329                         for (i = current_deps_start; i < current_ins_start; i += 2)
3330                                 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3331                                         need_stop = TRUE;
3332                         break;
3333                 case IA64_READ_BR_BRANCH:
3334                         reg = deps [pos + 1];
3335
3336                         /* Writes to brs are visible to branches */
3337                         DEBUG_INS_SCHED (printf ("READ BR BRACH: %d\n", reg));
3338                         break;
3339                 case IA64_READ_FR:
3340                         reg = deps [pos + 1];
3341
3342                         DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3343                         for (i = current_deps_start; i < current_ins_start; i += 2)
3344                                 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3345                                         need_stop = TRUE;
3346                         break;
3347                 case IA64_WRITE_FR:
3348                         reg = code->dep_info [pos + 1];
3349
3350                         DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3351                         for (i = current_deps_start; i < current_ins_start; i += 2)
3352                                 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3353                                         need_stop = TRUE;
3354                         break;
3355                 case IA64_READ_AR:
3356                         reg = deps [pos + 1];
3357
3358                         DEBUG_INS_SCHED (printf ("READ AR: %d\n", reg));
3359                         for (i = current_deps_start; i < current_ins_start; i += 2)
3360                                 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3361                                         need_stop = TRUE;
3362                         break;
3363                 case IA64_WRITE_AR:
3364                         reg = code->dep_info [pos + 1];
3365
3366                         DEBUG_INS_SCHED (printf ("WRITE AR: %d\n", reg));
3367                         for (i = current_deps_start; i < current_ins_start; i += 2)
3368                                 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3369                                         need_stop = TRUE;
3370                         break;
3371                 case IA64_NO_STOP:
3372                         /*
3373                          * Explicitly indicate that a stop is not required. Useful for
3374                          * example when two predicated instructions with negated predicates
3375                          * write the same registers.
3376                          */
3377                         no_stop = TRUE;
3378                         break;
3379                 default:
3380                         g_assert_not_reached ();
3381                 }
3382                 pos += 2;
3383
3384                 if (need_stop && !no_stop) {
3385                         g_assert (ins_index > 0);
3386                         stops [ins_index - 1] = 1;
3387
3388                         DEBUG_INS_SCHED (printf ("STOP\n"));
3389                         current_deps_start = current_ins_start;
3390
3391                         /* Skip remaining deps for this instruction */
3392                         while (deps [pos] != IA64_END_OF_INS)
3393                                 pos += 2;
3394                 }
3395         }
3396
3397         if (code->nins > 0) {
3398                 /* No dependency info for the last instruction */
3399                 stops [code->nins - 1] = 1;
3400         }
3401
3402         deps_start [code->nins] = code->dep_info_pos;
3403 }
3404
3405 static void
3406 ia64_real_emit_bundle (Ia64CodegenState *code, int *deps_start, int *stops, int n, guint64 template, guint64 ins1, guint64 ins2, guint64 ins3, guint8 nops)
3407 {
3408         int stop_pos, i, deps_to_shift, dep_shift;
3409
3410         g_assert (n <= code->nins);
3411
3412         // if (n > 1) printf ("FOUND: %ld.\n", template);
3413
3414         ia64_emit_bundle_template (code, template, ins1, ins2, ins3);
3415
3416         stop_pos = last_stop_in_template [template] + 1;
3417         if (stop_pos > n)
3418                 stop_pos = n;
3419
3420         /* Compute the number of 'real' instructions before the stop */
3421         deps_to_shift = stop_pos;
3422         if (stop_pos >= 3 && (nops & (1 << 2)))
3423                 deps_to_shift --;
3424         if (stop_pos >= 2 && (nops & (1 << 1)))
3425                 deps_to_shift --;
3426         if (stop_pos >= 1 && (nops & (1 << 0)))
3427                 deps_to_shift --;
3428
3429         /*
3430          * We have to keep some dependencies whose instructions have been shifted
3431          * out of the buffer. So nullify the end_of_ins markers in the dependency
3432          * array.
3433          */
3434         for (i = deps_start [deps_to_shift]; i < deps_start [n]; i += 2)
3435                 if (code->dep_info [i] == IA64_END_OF_INS)
3436                         code->dep_info [i] = IA64_NONE;
3437
3438         g_assert (deps_start [deps_to_shift] <= code->dep_info_pos);
3439         memcpy (code->dep_info, &code->dep_info [deps_start [deps_to_shift]], code->dep_info_pos - deps_start [deps_to_shift]);
3440         code->dep_info_pos = code->dep_info_pos - deps_start [deps_to_shift];
3441
3442         dep_shift = deps_start [deps_to_shift];
3443         for (i = 0; i < code->nins + 1 - n; ++i)
3444                 deps_start [i] = deps_start [n + i] - dep_shift;
3445
3446         /* Determine the exact positions of instructions with unwind ops */
3447         if (code->unw_op_count) {
3448                 int ins_pos [16];
3449                 int curr_ins, curr_ins_pos;
3450
3451                 curr_ins = 0;
3452                 curr_ins_pos = ((code->buf - code->region_start - 16) / 16) * 3;
3453                 for (i = 0; i < 3; ++i) {
3454                         if (! (nops & (1 << i))) {
3455                                 ins_pos [curr_ins] = curr_ins_pos + i;
3456                                 curr_ins ++;
3457                         }
3458                 }
3459
3460                 for (i = code->unw_op_pos; i < code->unw_op_count; ++i) {
3461                         if (code->unw_ops_pos [i] < n) {
3462                                 code->unw_ops [i].when = ins_pos [code->unw_ops_pos [i]];
3463                                 //printf ("UNW-OP: %d -> %d\n", code->unw_ops_pos [i], code->unw_ops [i].when);
3464                         }
3465                 }
3466                 if (code->unw_op_pos < code->unw_op_count)
3467                         code->unw_op_pos += n;
3468         }
3469
3470         if (n == code->nins) {
3471                 code->template = 0;
3472                 code->nins = 0;
3473         }
3474         else {
3475                 memcpy (&code->instructions [0], &code->instructions [n], (code->nins - n) * sizeof (guint64));
3476                 memcpy (&code->itypes [0], &code->itypes [n], (code->nins - n) * sizeof (int));
3477                 memcpy (&stops [0], &stops [n], (code->nins - n) * sizeof (int));
3478                 code->nins -= n;
3479         }
3480 }
3481
3482 void
3483 ia64_emit_bundle (Ia64CodegenState *code, gboolean flush)
3484 {
3485         int i, ins_type, template, nins_to_emit;
3486         int deps_start [16];
3487         int stops [16];
3488         gboolean found;
3489
3490         /*
3491          * We implement a simple scheduler which tries to put three instructions
3492          * per bundle, then two, then one.
3493          */
3494         ia64_analyze_deps (code, deps_start, stops);
3495
3496         if ((code->nins >= 3) && !code->one_ins_per_bundle) {
3497                 /* Find a suitable template */
3498                 for (template = 0; template < 32; ++template) {
3499                         if (stops_in_template [template][0] != stops [0] ||
3500                                 stops_in_template [template][1] != stops [1] ||
3501                                 stops_in_template [template][2] != stops [2])
3502                                 continue;
3503
3504                         found = TRUE;
3505                         for (i = 0; i < 3; ++i) {
3506                                 ins_type = ins_types_in_template [template][i];
3507                                 switch (code->itypes [i]) {
3508                                 case IA64_INS_TYPE_A:
3509                                         found &= (ins_type == IA64_INS_TYPE_I) || (ins_type == IA64_INS_TYPE_M);
3510                                         break;
3511                                 default:
3512                                         found &= (ins_type == code->itypes [i]);
3513                                         break;
3514                                 }
3515                         }
3516
3517                         if (found)
3518                                 found = debug_ins_sched ();
3519
3520                         if (found) {
3521                                 ia64_real_emit_bundle (code, deps_start, stops, 3, template, code->instructions [0], code->instructions [1], code->instructions [2], 0);
3522                                 break;
3523                         }
3524                 }
3525         }
3526
3527         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3528                 /* Wait for more instructions */
3529                 return;
3530
3531         /* If it didn't work out, try putting two instructions into one bundle */
3532         if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3533                 /* Try a nop at the end */
3534                 for (template = 0; template < 32; ++template) {
3535                         if (stops_in_template [template][0] != stops [0] ||
3536                                 ((stops_in_template [template][1] != stops [1]) &&
3537                                  (stops_in_template [template][2] != stops [1])))
3538
3539                                 continue;
3540
3541                         if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3542                                 !ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [1]))
3543                                 continue;
3544
3545                         if (!debug_ins_sched ())
3546                                 continue;
3547
3548                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], code->instructions [1], nops_for_ins_types [ins_types_in_template [template][2]], 1 << 2);
3549                         break;
3550                 }
3551         }
3552
3553         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3554                 /* Wait for more instructions */
3555                 return;
3556
3557         if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3558                 /* Try a nop in the middle */
3559                 for (template = 0; template < 32; ++template) {
3560                         if (((stops_in_template [template][0] != stops [0]) &&
3561                                  (stops_in_template [template][1] != stops [0])) ||
3562                                 stops_in_template [template][2] != stops [1])
3563                                 continue;
3564
3565                         if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3566                                 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3567                                 continue;
3568
3569                         if (!debug_ins_sched ())
3570                                 continue;
3571
3572                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], nops_for_ins_types [ins_types_in_template [template][1]], code->instructions [1], 1 << 1);
3573                         break;
3574                 }
3575         }
3576
3577         if ((code->nins >= 2) && flush && !code->one_ins_per_bundle) {
3578                 /* Try a nop at the beginning */
3579                 for (template = 0; template < 32; ++template) {
3580                         if ((stops_in_template [template][1] != stops [0]) ||
3581                                 (stops_in_template [template][2] != stops [1]))
3582                                 continue;
3583
3584                         if (!ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [0]) ||
3585                                 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3586                                 continue;
3587
3588                         if (!debug_ins_sched ())
3589                                 continue;
3590
3591                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, nops_for_ins_types [ins_types_in_template [template][0]], code->instructions [0], code->instructions [1], 1 << 0);
3592                         break;
3593                 }
3594         }
3595
3596         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3597                 /* Wait for more instructions */
3598                 return;
3599
3600         if (flush)
3601                 nins_to_emit = code->nins;
3602         else
3603                 nins_to_emit = 1;
3604
3605         while (nins_to_emit > 0) {
3606                 if (!debug_ins_sched ())
3607                         stops [0] = 1;
3608                 switch (code->itypes [0]) {
3609                 case IA64_INS_TYPE_A:
3610                         if (stops [0])
3611                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3612                         else
3613                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3614                         break;
3615                 case IA64_INS_TYPE_I:
3616                         if (stops [0])
3617                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3618                         else
3619                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3620                         break;
3621                 case IA64_INS_TYPE_M:
3622                         if (stops [0])
3623                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3624                         else
3625                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3626                         break;
3627                 case IA64_INS_TYPE_B:
3628                         if (stops [0])
3629                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIBS, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3630                         else
3631                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIB, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3632                         break;
3633                 case IA64_INS_TYPE_F:
3634                         if (stops [0])
3635                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3636                         else
3637                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFI, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3638                         break;
3639                 case IA64_INS_TYPE_LX:
3640                         if (stops [0] || stops [1])
3641                                 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLXS, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3642                         else
3643                                 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLX, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3644                         nins_to_emit --;
3645                         break;
3646                 default:
3647                         g_assert_not_reached ();
3648                 }
3649                 nins_to_emit --;
3650         }
3651 }
3652
3653 unw_dyn_region_info_t*
3654 mono_ia64_create_unwind_region (Ia64CodegenState *code)
3655 {
3656         unw_dyn_region_info_t *r;
3657
3658         g_assert (code->nins == 0);
3659         r = g_malloc0 (_U_dyn_region_info_size (code->unw_op_count));
3660         memcpy (&r->op, &code->unw_ops, sizeof (unw_dyn_op_t) * code->unw_op_count);
3661         r->op_count = code->unw_op_count;
3662         r->insn_count = ((code->buf - code->region_start) >> 4) * 3;
3663         code->unw_op_count = 0;
3664         code->unw_op_pos = 0;
3665         code->region_start = code->buf;
3666
3667         return r;
3668 }
3669
3670 static void
3671 ia64_patch (unsigned char* code, gpointer target)
3672 {
3673         int template, i;
3674         guint64 instructions [3];
3675         guint8 gen_buf [16];
3676         Ia64CodegenState gen;
3677         int ins_to_skip;
3678         gboolean found;
3679
3680         /*
3681          * code encodes both the position inside the buffer and code.nins when
3682          * the instruction was emitted.
3683          */
3684         ins_to_skip = (guint64)code % 16;
3685         code = (unsigned char*)((guint64)code & ~15);
3686
3687         /*
3688          * Search for the first instruction which is 'patchable', skipping
3689          * ins_to_skip instructions.
3690          */
3691
3692         while (TRUE) {
3693
3694         template = ia64_bundle_template (code);
3695         instructions [0] = ia64_bundle_ins1 (code);
3696         instructions [1] = ia64_bundle_ins2 (code);
3697         instructions [2] = ia64_bundle_ins3 (code);
3698
3699         ia64_codegen_init (gen, gen_buf);
3700
3701         found = FALSE;
3702         for (i = 0; i < 3; ++i) {
3703                 guint64 ins = instructions [i];
3704                 int opcode = ia64_ins_opcode (ins);
3705
3706                 if (ins == nops_for_ins_types [ins_types_in_template [template][i]])
3707                         continue;
3708
3709                 if (ins_to_skip) {
3710                         ins_to_skip --;
3711                         continue;
3712                 }
3713
3714                 switch (ins_types_in_template [template][i]) {
3715                 case IA64_INS_TYPE_A:
3716                 case IA64_INS_TYPE_M:
3717                         if ((opcode == 8) && (ia64_ins_x2a (ins) == 2) && (ia64_ins_ve (ins) == 0)) {
3718                                 /* adds */
3719                                 ia64_adds_imm_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), (guint64)target, ia64_ins_r3 (ins));
3720                                 instructions [i] = gen.instructions [0];
3721                                 found = TRUE;
3722                         }
3723                         else
3724                                 NOT_IMPLEMENTED;
3725                         break;
3726                 case IA64_INS_TYPE_B:
3727                         if ((opcode == 4) && (ia64_ins_btype (ins) == 0)) {
3728                                 /* br.cond */
3729                                 gint64 disp = ((guint8*)target - code) >> 4;
3730
3731                                 /* FIXME: hints */
3732                                 ia64_br_cond_hint_pred (gen, ia64_ins_qp (ins), disp, 0, 0, 0);
3733
3734                                 instructions [i] = gen.instructions [0];
3735                                 found = TRUE;
3736                         }
3737                         else if (opcode == 5) {
3738                                 /* br.call */
3739                                 gint64 disp = ((guint8*)target - code) >> 4;
3740
3741                                 /* FIXME: hints */
3742                                 ia64_br_call_hint_pred (gen, ia64_ins_qp (ins), ia64_ins_b1 (ins), disp, 0, 0, 0);
3743                                 instructions [i] = gen.instructions [0];
3744                                 found = TRUE;
3745                         }
3746                         else
3747                                 NOT_IMPLEMENTED;
3748                         break;
3749                 case IA64_INS_TYPE_LX:
3750                         if (i == 1)
3751                                 break;
3752
3753                         if ((opcode == 6) && (ia64_ins_vc (ins) == 0)) {
3754                                 /* movl */
3755                                 ia64_movl_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), target);
3756                                 instructions [1] = gen.instructions [0];
3757                                 instructions [2] = gen.instructions [1];
3758                                 found = TRUE;
3759                         }
3760                         else
3761                                 NOT_IMPLEMENTED;
3762
3763                         break;
3764                 default:
3765                         NOT_IMPLEMENTED;
3766                 }
3767
3768                 if (found) {
3769                         /* Rewrite code */
3770                         ia64_codegen_init (gen, code);
3771                         ia64_emit_bundle_template (&gen, template, instructions [0], instructions [1], instructions [2]);
3772                         return;
3773                 }
3774         }
3775
3776         code += 16;
3777         }
3778 }
3779
3780 void
3781 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3782 {
3783         MonoJumpInfo *patch_info;
3784
3785         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3786                 unsigned char *ip = patch_info->ip.i + code;
3787                 const unsigned char *target;
3788
3789                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3790
3791                 if (patch_info->type == MONO_PATCH_INFO_NONE)
3792                         continue;
3793                 if (mono_compile_aot) {
3794                         NOT_IMPLEMENTED;
3795                 }
3796
3797                 ia64_patch (ip, (gpointer)target);
3798         }
3799 }
3800
3801 guint8 *
3802 mono_arch_emit_prolog (MonoCompile *cfg)
3803 {
3804         MonoMethod *method = cfg->method;
3805         MonoMethodSignature *sig;
3806         MonoInst *inst;
3807         int alloc_size, pos, i;
3808         Ia64CodegenState code;
3809         CallInfo *cinfo;
3810
3811         sig = mono_method_signature (method);
3812         pos = 0;
3813
3814         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
3815
3816         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 512);
3817
3818         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3819                 cfg->code_size += 1024;
3820         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3821                 cfg->code_size += 1024;
3822
3823         cfg->native_code = g_malloc (cfg->code_size);
3824
3825         ia64_codegen_init (code, cfg->native_code);
3826
3827         alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
3828         if (cfg->param_area)
3829                 alloc_size += cfg->param_area;
3830         if (alloc_size)
3831                 /* scratch area */
3832                 alloc_size += 16;
3833         alloc_size = ALIGN_TO (alloc_size, MONO_ARCH_FRAME_ALIGNMENT);
3834
3835         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
3836                 /* Force sp to be saved/restored */
3837                 alloc_size += MONO_ARCH_FRAME_ALIGNMENT;
3838
3839         cfg->arch.stack_alloc_size = alloc_size;
3840
3841         pos = 0;
3842
3843         if (method->save_lmf) {
3844                 /* No LMF on IA64 */
3845         }
3846
3847         alloc_size -= pos;
3848
3849         ia64_unw_save_reg (code, UNW_IA64_AR_PFS, UNW_IA64_GR + cfg->arch.reg_saved_ar_pfs);
3850         ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3851         ia64_unw_save_reg (code, UNW_IA64_RP, UNW_IA64_GR + cfg->arch.reg_saved_b0);
3852         ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3853
3854         if ((alloc_size || cinfo->stack_usage) && !cfg->arch.omit_fp) {
3855                 ia64_unw_save_reg (code, UNW_IA64_SP, UNW_IA64_GR + cfg->arch.reg_saved_sp);
3856                 ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3857                 if (cfg->frame_reg != cfg->arch.reg_saved_sp)
3858                         ia64_mov (code, cfg->frame_reg, IA64_SP);
3859         }
3860
3861         if (alloc_size) {
3862 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3863                 int pagesize = getpagesize ();
3864
3865                 if (alloc_size >= pagesize) {
3866                         gint32 remaining_size = alloc_size;
3867
3868                         /* Generate stack touching code */
3869                         ia64_mov (code, GP_SCRATCH_REG, IA64_SP);
3870                         while (remaining_size >= pagesize) {
3871                                 ia64_movl (code, GP_SCRATCH_REG2, pagesize);
3872                                 ia64_sub (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3873                                 ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
3874                                 remaining_size -= pagesize;
3875                         }
3876                 }
3877 #endif
3878                 if (ia64_is_imm14 (-alloc_size)) {
3879                         if (cfg->arch.omit_fp)
3880                                 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3881                         ia64_adds_imm (code, IA64_SP, (-alloc_size), IA64_SP);
3882                 }
3883                 else {
3884                         ia64_movl (code, GP_SCRATCH_REG, -alloc_size);
3885                         if (cfg->arch.omit_fp)
3886                                 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3887                         ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
3888                 }
3889         }
3890
3891         ia64_begin_bundle (code);
3892
3893         /* Initialize unwind info */
3894         cfg->arch.r_pro = mono_ia64_create_unwind_region (&code);
3895
3896         if (sig->ret->type != MONO_TYPE_VOID) {
3897                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
3898                         /* Save volatile arguments to the stack */
3899                         NOT_IMPLEMENTED;
3900                 }
3901         }
3902
3903         /* Keep this in sync with emit_load_volatile_arguments */
3904         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3905                 ArgInfo *ainfo = cinfo->args + i;
3906                 gint32 stack_offset;
3907                 MonoType *arg_type;
3908
3909                 inst = cfg->args [i];
3910
3911                 if (sig->hasthis && (i == 0))
3912                         arg_type = &mono_defaults.object_class->byval_arg;
3913                 else
3914                         arg_type = sig->params [i - sig->hasthis];
3915
3916                 arg_type = mono_type_get_underlying_type (arg_type);
3917
3918                 stack_offset = ainfo->offset + ARGS_OFFSET;
3919
3920                 /*
3921                  * FIXME: Native code might pass non register sized integers
3922                  * without initializing the upper bits.
3923                  */
3924                 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED && !arg_type->byref && ainfo->storage == ArgInIReg) {
3925                         int reg = cfg->arch.reg_in0 + ainfo->reg;
3926
3927                         switch (mono_type_to_load_membase (cfg, arg_type)) {
3928                         case OP_LOADI1_MEMBASE:
3929                                 ia64_sxt1 (code, reg, reg);
3930                                 break;
3931                         case OP_LOADU1_MEMBASE:
3932                                 ia64_zxt1 (code, reg, reg);
3933                                 break;
3934                         case OP_LOADI2_MEMBASE:
3935                                 ia64_sxt2 (code, reg, reg);
3936                                 break;
3937                         case OP_LOADU2_MEMBASE:
3938                                 ia64_zxt2 (code, reg, reg);
3939                                 break;
3940                         default:
3941                                 break;
3942                         }
3943                 }
3944
3945                 /* Save volatile arguments to the stack */
3946                 if (inst->opcode != OP_REGVAR) {
3947                         switch (ainfo->storage) {
3948                         case ArgInIReg:
3949                         case ArgInFloatReg:
3950                         case ArgInFloatRegR4:
3951                                 g_assert (inst->opcode == OP_REGOFFSET);
3952                                 if (ia64_is_adds_imm (inst->inst_offset))
3953                                         ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3954                                 else {
3955                                         ia64_movl (code, GP_SCRATCH_REG2, inst->inst_offset);
3956                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3957                                 }
3958                                 if (arg_type->byref)
3959                                         ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3960                                 else {
3961                                         switch (arg_type->type) {
3962                                         case MONO_TYPE_R4:
3963                                                 ia64_stfs_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3964                                                 break;
3965                                         case MONO_TYPE_R8:
3966                                                 ia64_stfd_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3967                                                 break;
3968                                         default:
3969                                                 ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3970                                                 break;
3971                                         }
3972                                 }
3973                                 break;
3974                         case ArgOnStack:
3975                                 break;
3976                         case ArgAggregate:
3977                                 if (ainfo->nslots != ainfo->nregs)
3978                                         NOT_IMPLEMENTED;
3979
3980                                 g_assert (inst->opcode == OP_REGOFFSET);
3981                                 ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3982                                 for (i = 0; i < ainfo->nregs; ++i) {
3983                                         switch (ainfo->atype) {
3984                                         case AggregateNormal:
3985                                                 ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg + i, sizeof (gpointer), 0);
3986                                                 break;
3987                                         case AggregateSingleHFA:
3988                                                 ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, 4, 0);
3989                                                 break;
3990                                         case AggregateDoubleHFA:
3991                                                 ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, sizeof (gpointer), 0);
3992                                                 break;
3993                                         default:
3994                                                 NOT_IMPLEMENTED;
3995                                         }
3996                                 }
3997                                 break;
3998                         default:
3999                                 g_assert_not_reached ();
4000                         }
4001                 }
4002
4003                 if (inst->opcode == OP_REGVAR) {
4004                         /* Argument allocated to (non-volatile) register */
4005                         switch (ainfo->storage) {
4006                         case ArgInIReg:
4007                                 if (inst->dreg != cfg->arch.reg_in0 + ainfo->reg)
4008                                         ia64_mov (code, inst->dreg, cfg->arch.reg_in0 + ainfo->reg);
4009                                 break;
4010                         case ArgOnStack:
4011                                 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
4012                                 ia64_ld8 (code, inst->dreg, GP_SCRATCH_REG);
4013                                 break;
4014                         default:
4015                                 NOT_IMPLEMENTED;
4016                         }
4017                 }
4018         }
4019
4020         if (method->save_lmf) {
4021                 /* No LMF on IA64 */
4022         }
4023
4024         ia64_codegen_close (code);
4025
4026         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4027                 code.buf = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code.buf, TRUE);
4028
4029         cfg->code_len = code.buf - cfg->native_code;
4030
4031         g_assert (cfg->code_len < cfg->code_size);
4032
4033         cfg->arch.prolog_end_offset = cfg->code_len;
4034
4035         return code.buf;
4036 }
4037
4038 void
4039 mono_arch_emit_epilog (MonoCompile *cfg)
4040 {
4041         MonoMethod *method = cfg->method;
4042         int i, pos;
4043         int max_epilog_size = 16 * 4;
4044         Ia64CodegenState code;
4045         guint8 *buf;
4046         CallInfo *cinfo;
4047         ArgInfo *ainfo;
4048
4049         if (mono_jit_trace_calls != NULL)
4050                 max_epilog_size += 1024;
4051
4052         cfg->arch.epilog_begin_offset = cfg->code_len;
4053
4054         while (cfg->code_len + max_epilog_size > cfg->code_size) {
4055                 cfg->code_size *= 2;
4056                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4057                 mono_jit_stats.code_reallocs++;
4058         }
4059
4060         /* FIXME: Emit unwind info */
4061
4062         buf = cfg->native_code + cfg->code_len;
4063
4064         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4065                 buf = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, buf, TRUE);
4066
4067         ia64_codegen_init (code, buf);
4068
4069         /* the code restoring the registers must be kept in sync with OP_JMP */
4070         pos = 0;
4071
4072         if (method->save_lmf) {
4073                 /* No LMF on IA64 */
4074         }
4075
4076         /* Load returned vtypes into registers if needed */
4077         cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
4078         ainfo = &cinfo->ret;
4079         switch (ainfo->storage) {
4080         case ArgAggregate:
4081                 if (ainfo->nslots != ainfo->nregs)
4082                         NOT_IMPLEMENTED;
4083
4084                 g_assert (cfg->ret->opcode == OP_REGOFFSET);
4085                 ia64_adds_imm (code, GP_SCRATCH_REG, cfg->ret->inst_offset, cfg->ret->inst_basereg);
4086                 for (i = 0; i < ainfo->nregs; ++i) {
4087                         switch (ainfo->atype) {
4088                         case AggregateNormal:
4089                                 ia64_ld8_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4090                                 break;
4091                         case AggregateSingleHFA:
4092                                 ia64_ldfs_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, 4, 0);
4093                                 break;
4094                         case AggregateDoubleHFA:
4095                                 ia64_ldfd_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4096                                 break;
4097                         default:
4098                                 g_assert_not_reached ();
4099                         }
4100                 }
4101                 break;
4102         default:
4103                 break;
4104         }
4105
4106         ia64_begin_bundle (code);
4107
4108         code.region_start = cfg->native_code;
4109
4110         /* Label the unwind state at the start of the exception throwing region */
4111         //ia64_unw_label_state (code, 1234);
4112
4113         if (cfg->arch.stack_alloc_size) {
4114                 if (cfg->arch.omit_fp) {
4115                         if (ia64_is_imm14 (cfg->arch.stack_alloc_size)) {
4116                                 ia64_unw_pop_frames (code, 1);
4117                                 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
4118                         } else {
4119                                 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
4120                                 ia64_unw_pop_frames (code, 1);
4121                                 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
4122                         }
4123                 }
4124                 else {
4125                         ia64_unw_pop_frames (code, 1);
4126                         ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
4127                 }
4128         }
4129         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
4130         ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
4131         ia64_br_ret_reg (code, IA64_B0);
4132
4133         ia64_codegen_close (code);
4134
4135         cfg->arch.r_epilog = mono_ia64_create_unwind_region (&code);
4136         cfg->arch.r_pro->next = cfg->arch.r_epilog;
4137
4138         cfg->code_len = code.buf - cfg->native_code;
4139
4140         g_assert (cfg->code_len < cfg->code_size);
4141 }
4142
4143 void
4144 mono_arch_emit_exceptions (MonoCompile *cfg)
4145 {
4146         MonoJumpInfo *patch_info;
4147         int i, nthrows;
4148         Ia64CodegenState code;
4149         gboolean empty = TRUE;
4150         //unw_dyn_region_info_t *r_exceptions;
4151         MonoClass *exc_classes [16];
4152         guint8 *exc_throw_start [16], *exc_throw_end [16];
4153         guint32 code_size = 0;
4154
4155         /* Compute needed space */
4156         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4157                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4158                         code_size += 256;
4159                 if (patch_info->type == MONO_PATCH_INFO_R8)
4160                         code_size += 8 + 7; /* sizeof (double) + alignment */
4161                 if (patch_info->type == MONO_PATCH_INFO_R4)
4162                         code_size += 4 + 7; /* sizeof (float) + alignment */
4163         }
4164
4165         if (code_size == 0)
4166                 return;
4167
4168         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4169                 cfg->code_size *= 2;
4170                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4171                 mono_jit_stats.code_reallocs++;
4172         }
4173
4174         ia64_codegen_init (code, cfg->native_code + cfg->code_len);
4175
4176         /* The unwind state here is the same as before the epilog */
4177         //ia64_unw_copy_state (code, 1234);
4178
4179         /* add code to raise exceptions */
4180         /* FIXME: Optimize this */
4181         nthrows = 0;
4182         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4183                 switch (patch_info->type) {
4184                 case MONO_PATCH_INFO_EXC: {
4185                         MonoClass *exc_class;
4186                         guint8* throw_ip;
4187                         guint8* buf;
4188                         guint64 exc_token_index;
4189
4190                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4191                         g_assert (exc_class);
4192                         exc_token_index = mono_metadata_token_index (exc_class->type_token);
4193                         throw_ip = cfg->native_code + patch_info->ip.i;
4194
4195                         ia64_begin_bundle (code);
4196
4197                         ia64_patch (cfg->native_code + patch_info->ip.i, code.buf);
4198
4199                         /* Find a throw sequence for the same exception class */
4200                         for (i = 0; i < nthrows; ++i)
4201                                 if (exc_classes [i] == exc_class)
4202                                         break;
4203
4204                         if (i < nthrows) {
4205                                 gint64 offset = exc_throw_end [i] - 16 - throw_ip;
4206
4207                                 if (ia64_is_adds_imm (offset))
4208                                         ia64_adds_imm (code, cfg->arch.reg_out0 + 1, offset, IA64_R0);
4209                                 else
4210                                         ia64_movl (code, cfg->arch.reg_out0 + 1, offset);
4211
4212                                 buf = code.buf + code.nins;
4213                                 ia64_br_cond_pred (code, 0, 0);
4214                                 ia64_begin_bundle (code);
4215                                 ia64_patch (buf, exc_throw_start [i]);
4216
4217                                 patch_info->type = MONO_PATCH_INFO_NONE;
4218                         }
4219                         else {
4220                                 /* Arg1 */
4221                                 buf = code.buf;
4222                                 ia64_movl (code, cfg->arch.reg_out0 + 1, 0);
4223
4224                                 ia64_begin_bundle (code);
4225
4226                                 if (nthrows < 16) {
4227                                         exc_classes [nthrows] = exc_class;
4228                                         exc_throw_start [nthrows] = code.buf;
4229                                 }
4230
4231                                 /* Arg2 */
4232                                 if (ia64_is_adds_imm (exc_token_index))
4233                                         ia64_adds_imm (code, cfg->arch.reg_out0 + 0, exc_token_index, IA64_R0);
4234                                 else
4235                                         ia64_movl (code, cfg->arch.reg_out0 + 0, exc_token_index);
4236
4237                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4238                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4239                                 patch_info->ip.i = code.buf + code.nins - cfg->native_code;
4240
4241                                 /* Indirect call */
4242                                 ia64_movl (code, GP_SCRATCH_REG, 0);
4243                                 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
4244                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
4245                                 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
4246
4247                                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
4248
4249                                 /* Patch up the throw offset */
4250                                 ia64_begin_bundle (code);
4251
4252                                 ia64_patch (buf, (gpointer)(code.buf - 16 - throw_ip));
4253
4254                                 if (nthrows < 16) {
4255                                         exc_throw_end [nthrows] = code.buf;
4256                                         nthrows ++;
4257                                 }
4258                         }
4259
4260                         empty = FALSE;
4261                         break;
4262                 }
4263                 default:
4264                         break;
4265                 }
4266         }
4267
4268         if (!empty)
4269                 /* The unwinder needs this to work */
4270                 ia64_break_i (code, 0);
4271
4272         ia64_codegen_close (code);
4273
4274         /* FIXME: */
4275         //r_exceptions = mono_ia64_create_unwind_region (&code);
4276         //cfg->arch.r_epilog = r_exceptions;
4277
4278         cfg->code_len = code.buf - cfg->native_code;
4279
4280         g_assert (cfg->code_len < cfg->code_size);
4281 }
4282
4283 void*
4284 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4285 {
4286         Ia64CodegenState code;
4287         CallInfo *cinfo = NULL;
4288         MonoMethodSignature *sig;
4289         MonoInst *ins;
4290         int i, n, stack_area = 0;
4291
4292         ia64_codegen_init (code, p);
4293
4294         /* Keep this in sync with mono_arch_get_argument_info */
4295
4296         if (enable_arguments) {
4297                 /* Allocate a new area on the stack and save arguments there */
4298                 sig = mono_method_signature (cfg->method);
4299
4300                 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4301
4302                 n = sig->param_count + sig->hasthis;
4303
4304                 stack_area = ALIGN_TO (n * 8, 16);
4305
4306                 if (n) {
4307                         ia64_movl (code, GP_SCRATCH_REG, stack_area);
4308
4309                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4310
4311                         /* FIXME: Allocate out registers */
4312
4313                         ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_SP);
4314
4315                         /* Required by the ABI */
4316                         ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4317
4318                         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4319                         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4320
4321                         /* Save arguments to the stack */
4322                         for (i = 0; i < n; ++i) {
4323                                 ins = cfg->args [i];
4324
4325                                 if (ins->opcode == OP_REGVAR) {
4326                                         ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4327                                         ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4328                                         ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
4329                                 }
4330                                 else {
4331                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
4332                                         ia64_add (code, GP_SCRATCH_REG, ins->inst_basereg, GP_SCRATCH_REG);
4333                                         ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
4334                                         ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4335                                         ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4336                                         ia64_st8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG2);
4337                                 }
4338                         }
4339                 }
4340                 else
4341                         ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4342         }
4343         else
4344                 ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4345
4346         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4347         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4348
4349         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4350
4351         if (enable_arguments && stack_area) {
4352                 ia64_movl (code, GP_SCRATCH_REG, stack_area);
4353
4354                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4355
4356                 ia64_adds_imm (code, IA64_SP, 16, IA64_SP);
4357         }
4358
4359         ia64_codegen_close (code);
4360
4361         return code.buf;
4362 }
4363
4364 void*
4365 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4366 {
4367         Ia64CodegenState code;
4368         CallInfo *cinfo = NULL;
4369         MonoMethod *method = cfg->method;
4370         MonoMethodSignature *sig = mono_method_signature (cfg->method);
4371
4372         ia64_codegen_init (code, p);
4373
4374         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4375
4376         /* Save return value + pass it to func */
4377         switch (cinfo->ret.storage) {
4378         case ArgNone:
4379                 break;
4380         case ArgInIReg:
4381                 ia64_mov (code, cfg->arch.reg_saved_return_val, cinfo->ret.reg);
4382                 ia64_mov (code, cfg->arch.reg_out0 + 1, cinfo->ret.reg);
4383                 break;
4384         case ArgInFloatReg:
4385                 ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4386                 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4387                 ia64_stfd_hint (code, GP_SCRATCH_REG, cinfo->ret.reg, 0);
4388                 ia64_fmov (code, 8 + 1, cinfo->ret.reg);
4389                 break;
4390         case ArgValuetypeAddrInIReg:
4391                 ia64_mov (code, cfg->arch.reg_out0 + 1, cfg->arch.reg_in0 + cinfo->ret.reg);
4392                 break;
4393         case ArgAggregate:
4394                 NOT_IMPLEMENTED;
4395                 break;
4396         default:
4397                 break;
4398         }
4399
4400         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, method);
4401         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4402         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4403
4404         /* Restore return value */
4405         switch (cinfo->ret.storage) {
4406         case ArgNone:
4407                 break;
4408         case ArgInIReg:
4409                 ia64_mov (code, cinfo->ret.reg, cfg->arch.reg_saved_return_val);
4410                 break;
4411         case ArgInFloatReg:
4412                 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4413                 ia64_ldfd (code, cinfo->ret.reg, GP_SCRATCH_REG);
4414                 break;
4415         case ArgValuetypeAddrInIReg:
4416                 break;
4417         case ArgAggregate:
4418                 break;
4419         default:
4420                 break;
4421         }
4422
4423         ia64_codegen_close (code);
4424
4425         return code.buf;
4426 }
4427
4428 void
4429 mono_arch_save_unwind_info (MonoCompile *cfg)
4430 {
4431         unw_dyn_info_t *di;
4432
4433         /* FIXME: Unregister this for dynamic methods */
4434
4435         di = g_malloc0 (sizeof (unw_dyn_info_t));
4436         di->start_ip = (unw_word_t) cfg->native_code;
4437         di->end_ip = (unw_word_t) cfg->native_code + cfg->code_len;
4438         di->gp = 0;
4439         di->format = UNW_INFO_FORMAT_DYNAMIC;
4440         di->u.pi.name_ptr = (unw_word_t)mono_method_full_name (cfg->method, TRUE);
4441         di->u.pi.regions = cfg->arch.r_pro;
4442
4443         _U_dyn_register (di);
4444
4445         /*
4446         {
4447                 unw_dyn_region_info_t *region = di->u.pi.regions;
4448
4449                 printf ("Unwind info for method %s:\n", mono_method_full_name (cfg->method, TRUE));
4450                 while (region) {
4451                         printf ("    [Region: %d]\n", region->insn_count);
4452                         region = region->next;
4453                 }
4454         }
4455         */
4456 }
4457
4458 void
4459 mono_arch_flush_icache (guint8 *code, gint size)
4460 {
4461         guint8* p = (guint8*)((guint64)code & ~(0x3f));
4462         guint8* end = (guint8*)((guint64)code + size);
4463
4464 #ifdef __INTEL_COMPILER
4465         /* icc doesn't define an fc.i instrinsic, but fc==fc.i on itanium 2 */
4466         while (p < end) {
4467                 __fc ((guint64)p);
4468                 p += 32;
4469         }
4470 #else
4471         while (p < end) {
4472                 __asm__ __volatile__ ("fc.i %0"::"r"(p));
4473                 /* FIXME: This could be increased to 128 on some cpus */
4474                 p += 32;
4475         }
4476 #endif
4477 }
4478
4479 void
4480 mono_arch_flush_register_windows (void)
4481 {
4482         /* Not needed because of libunwind */
4483 }
4484
4485 gboolean
4486 mono_arch_is_inst_imm (gint64 imm)
4487 {
4488         /* The lowering pass will take care of it */
4489
4490         return TRUE;
4491 }
4492
4493 /*
4494  * Determine whenever the trap whose info is in SIGINFO is caused by
4495  * integer overflow.
4496  */
4497 gboolean
4498 mono_arch_is_int_overflow (void *sigctx, void *info)
4499 {
4500         /* Division is emulated with explicit overflow checks */
4501         return FALSE;
4502 }
4503
4504 guint32
4505 mono_arch_get_patch_offset (guint8 *code)
4506 {
4507         NOT_IMPLEMENTED;
4508
4509         return 0;
4510 }
4511
4512 gpointer
4513 mono_arch_get_vcall_slot (guint8* code, gpointer *regs, int *displacement)
4514 {
4515         guint8 *bundle2 = code - 48;
4516         guint8 *bundle3 = code - 32;
4517         guint8 *bundle4 = code - 16;
4518         guint64 ins21 = ia64_bundle_ins1 (bundle2);
4519         guint64 ins22 = ia64_bundle_ins2 (bundle2);
4520         guint64 ins23 = ia64_bundle_ins3 (bundle2);
4521         guint64 ins31 = ia64_bundle_ins1 (bundle3);
4522         guint64 ins32 = ia64_bundle_ins2 (bundle3);
4523         guint64 ins33 = ia64_bundle_ins3 (bundle3);
4524         guint64 ins41 = ia64_bundle_ins1 (bundle4);
4525         guint64 ins42 = ia64_bundle_ins2 (bundle4);
4526         guint64 ins43 = ia64_bundle_ins3 (bundle4);
4527
4528         /*
4529          * Virtual calls are made with:
4530          *
4531          * [MII]       ld8 r31=[r8]
4532          *             nop.i 0x0
4533          *             nop.i 0x0;;
4534          * [MII]       nop.m 0x0
4535          *             mov.sptk b6=r31,0x2000000000f32a80
4536          *             nop.i 0x0
4537          * [MII]       nop.m 0x0
4538          *             nop.i 0x123456
4539          *             nop.i 0x0
4540          * [MIB]       nop.m 0x0
4541          *             nop.i 0x0
4542          *             br.call.sptk.few b0=b6;;
4543          */
4544
4545         if (((ia64_bundle_template (bundle3) == IA64_TEMPLATE_MII) ||
4546                  (ia64_bundle_template (bundle3) == IA64_TEMPLATE_MIIS)) &&
4547                 (ia64_bundle_template (bundle4) == IA64_TEMPLATE_MIBS) &&
4548                 (ins31 == IA64_NOP_M) &&
4549                 (ia64_ins_opcode (ins32) == 0) && (ia64_ins_x3 (ins32) == 0) && (ia64_ins_x6 (ins32) == 0x1) && (ia64_ins_y (ins32) == 0) &&
4550                 (ins33 == IA64_NOP_I) &&
4551                 (ins41 == IA64_NOP_M) &&
4552                 (ins42 == IA64_NOP_I) &&
4553                 (ia64_ins_opcode (ins43) == 1) && (ia64_ins_b1 (ins43) == 0) && (ia64_ins_b2 (ins43) == 6) &&
4554                 ((ins32 >> 6) & 0xfffff) == 0x12345) {
4555                 g_assert (ins21 == IA64_NOP_M);
4556                 g_assert (ins23 == IA64_NOP_I);
4557                 g_assert (ia64_ins_opcode (ins22) == 0);
4558                 g_assert (ia64_ins_x3 (ins22) == 7);
4559                 g_assert (ia64_ins_x (ins22) == 0);
4560                 g_assert (ia64_ins_b1 (ins22) == IA64_B6);
4561
4562                 *displacement = (gssize)regs [IA64_R8] - (gssize)regs [IA64_R11];
4563
4564                 return regs [IA64_R11];
4565         }
4566
4567         return NULL;
4568 }
4569
4570 gpointer*
4571 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
4572 {
4573         gpointer vt;
4574         int displacement;
4575         vt = mono_arch_get_vcall_slot (code, regs, &displacement);
4576         if (!vt)
4577                 return NULL;
4578         return (gpointer*)(gpointer)((char*)vt + displacement);
4579 }
4580
4581 gpointer*
4582 mono_arch_get_delegate_method_ptr_addr (guint8* code, gpointer *regs)
4583 {
4584         NOT_IMPLEMENTED;
4585
4586         return NULL;
4587 }
4588
4589 void
4590 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
4591 {
4592 }
4593
4594 void
4595 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4596 {
4597 }
4598
4599 #ifdef MONO_ARCH_HAVE_IMT
4600
4601 /*
4602  * LOCKING: called with the domain lock held
4603  */
4604 gpointer
4605 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
4606         gpointer fail_tramp)
4607 {
4608         int i;
4609         int size = 0;
4610         guint8 *start, *buf;
4611         Ia64CodegenState code;
4612
4613         g_assert (!fail_tramp);
4614
4615         size = count * 256;
4616         buf = g_malloc0 (size);
4617         ia64_codegen_init (code, buf);
4618
4619         /* IA64_R9 contains the IMT method */
4620
4621         for (i = 0; i < count; ++i) {
4622                 MonoIMTCheckItem *item = imt_entries [i];
4623                 ia64_begin_bundle (code);
4624                 item->code_target = (guint8*)code.buf + code.nins;
4625                 if (item->is_equals) {
4626                         if (item->check_target_idx) {
4627                                 if (!item->compare_done) {
4628                                         ia64_movl (code, GP_SCRATCH_REG, item->key);
4629                                         ia64_cmp_eq (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4630                                 }
4631                                 item->jmp_code = (guint8*)code.buf + code.nins;
4632                                 ia64_br_cond_pred (code, 7, 0);
4633
4634                                 ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4635                                 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4636                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4637                                 ia64_br_cond_reg (code, IA64_B6);
4638                         } else {
4639                                 /* enable the commented code to assert on wrong method */
4640 #if ENABLE_WRONG_METHOD_CHECK
4641                                 g_assert_not_reached ();
4642 #endif
4643                                 ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4644                                 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4645                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4646                                 ia64_br_cond_reg (code, IA64_B6);
4647 #if ENABLE_WRONG_METHOD_CHECK
4648                                 g_assert_not_reached ();
4649 #endif
4650                         }
4651                 } else {
4652                         ia64_movl (code, GP_SCRATCH_REG, item->key);
4653                         ia64_cmp_geu (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4654                         item->jmp_code = (guint8*)code.buf + code.nins;
4655                         ia64_br_cond_pred (code, 6, 0);
4656                 }
4657         }
4658         /* patch the branches to get to the target items */
4659         for (i = 0; i < count; ++i) {
4660                 MonoIMTCheckItem *item = imt_entries [i];
4661                 if (item->jmp_code) {
4662                         if (item->check_target_idx) {
4663                                 ia64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
4664                         }
4665                 }
4666         }
4667
4668         ia64_codegen_close (code);
4669         g_assert (code.buf - buf <= size);
4670
4671         size = code.buf - buf;
4672         start = mono_domain_code_reserve (domain, size);
4673         memcpy (start, buf, size);
4674
4675         mono_arch_flush_icache (start, size);
4676
4677         mono_stats.imt_thunks_size += size;
4678
4679         return start;
4680 }
4681
4682 MonoMethod*
4683 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
4684 {
4685         return regs [IA64_R9];
4686 }
4687
4688 void
4689 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
4690 {
4691         /* Done by the implementation of the CALL_MEMBASE opcodes */
4692 }
4693 #endif
4694
4695 gpointer
4696 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, gssize *regs, guint8 *code)
4697 {
4698         return (gpointer)regs [IA64_R10];
4699 }
4700
4701 MonoObject*
4702 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
4703 {
4704         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), (gssize*)regs, NULL);
4705 }
4706
4707 gpointer
4708 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
4709 {
4710         return NULL;
4711 }
4712
4713 MonoInst*
4714 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4715 {
4716         MonoInst *ins = NULL;
4717
4718         if (cmethod->klass->image == mono_defaults.corlib &&
4719                 (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
4720                 (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
4721
4722                 /*
4723                  * We don't use the generic version in mini_emit_inst_for_method () since we
4724                  * ia64 has atomic_add_imm opcodes.
4725                  */
4726                 if (strcmp (cmethod->name, "Increment") == 0) {
4727                         guint32 opcode;
4728
4729                         if (fsig->params [0]->type == MONO_TYPE_I4)
4730                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4731                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4732                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4733                         else
4734                                 g_assert_not_reached ();
4735                         MONO_INST_NEW (cfg, ins, opcode);
4736                         ins->dreg = mono_alloc_preg (cfg);
4737                         ins->inst_imm = 1;
4738                         ins->inst_basereg = args [0]->dreg;
4739                         ins->inst_offset = 0;
4740                         MONO_ADD_INS (cfg->cbb, ins);
4741                 } else if (strcmp (cmethod->name, "Decrement") == 0) {
4742                         guint32 opcode;
4743
4744                         if (fsig->params [0]->type == MONO_TYPE_I4)
4745                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4746                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4747                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4748                         else
4749                                 g_assert_not_reached ();
4750                         MONO_INST_NEW (cfg, ins, opcode);
4751                         ins->dreg = mono_alloc_preg (cfg);
4752                         ins->inst_imm = -1;
4753                         ins->inst_basereg = args [0]->dreg;
4754                         ins->inst_offset = 0;
4755                         MONO_ADD_INS (cfg->cbb, ins);
4756                 } else if (strcmp (cmethod->name, "Add") == 0) {
4757                         guint32 opcode;
4758                         gboolean is_imm = FALSE;
4759                         gint64 imm = 0;
4760
4761                         if ((args [1]->opcode == OP_ICONST) || (args [1]->opcode == OP_I8CONST)) {
4762                                 imm = (args [1]->opcode == OP_ICONST) ? args [1]->inst_c0 : args [1]->inst_l;
4763
4764                                 is_imm = (imm == 1 || imm == 4 || imm == 8 || imm == 16 || imm == -1 || imm == -4 || imm == -8 || imm == -16);
4765                         }
4766
4767                         if (is_imm) {
4768                                 if (fsig->params [0]->type == MONO_TYPE_I4)
4769                                         opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4770                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
4771                                         opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4772                                 else
4773                                         g_assert_not_reached ();
4774
4775                                 MONO_INST_NEW (cfg, ins, opcode);
4776                                 ins->dreg = mono_alloc_ireg (cfg);
4777                                 ins->inst_basereg = args [0]->dreg;
4778                                 ins->inst_offset = 0;
4779                                 ins->inst_imm = imm;
4780                                 ins->type = (opcode == OP_ATOMIC_ADD_IMM_NEW_I4) ? STACK_I4 : STACK_I8;
4781                         } else {
4782                                 if (fsig->params [0]->type == MONO_TYPE_I4)
4783                                         opcode = OP_ATOMIC_ADD_NEW_I4;
4784                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
4785                                         opcode = OP_ATOMIC_ADD_NEW_I8;
4786                                 else
4787                                         g_assert_not_reached ();
4788
4789                                 MONO_INST_NEW (cfg, ins, opcode);
4790                                 ins->dreg = mono_alloc_ireg (cfg);
4791                                 ins->inst_basereg = args [0]->dreg;
4792                                 ins->inst_offset = 0;
4793                                 ins->sreg2 = args [1]->dreg;
4794                                 ins->type = (opcode == OP_ATOMIC_ADD_NEW_I4) ? STACK_I4 : STACK_I8;
4795                         }
4796                         MONO_ADD_INS (cfg->cbb, ins);
4797                 }
4798         }
4799
4800         return ins;
4801 }
4802
4803 gboolean
4804 mono_arch_print_tree (MonoInst *tree, int arity)
4805 {
4806         return 0;
4807 }
4808
4809 MonoInst*
4810 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
4811 {
4812         return mono_get_domain_intrinsic (cfg);
4813 }
4814
4815 MonoInst*
4816 mono_arch_get_thread_intrinsic (MonoCompile* cfg)
4817 {
4818         return mono_get_thread_intrinsic (cfg);
4819 }
4820
4821 gpointer
4822 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
4823 {
4824         /* FIXME: implement */
4825         g_assert_not_reached ();
4826 }