2 * mini-ia64.c: IA64 backend for the Mono code generator
5 * Zoltan Varga (vargaz@gmail.com)
7 * (C) 2003 Ximian, Inc.
15 #ifdef __INTEL_COMPILER
16 #include <ia64intrin.h>
19 #include <mono/metadata/appdomain.h>
20 #include <mono/metadata/debug-helpers.h>
21 #include <mono/metadata/threads.h>
22 #include <mono/metadata/profiler-private.h>
23 #include <mono/utils/mono-math.h>
24 #include <mono/utils/mono-hwcap.h>
27 #include "mini-ia64.h"
29 #include "jit-icalls.h"
32 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
34 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
37 * IA64 register usage:
38 * - local registers are used for global register allocation
39 * - r8..r11, r14..r30 is used for local register allocation
40 * - r31 is a scratch register used within opcode implementations
41 * - FIXME: Use out registers as well
42 * - the first three locals are used for saving ar.pfst, b0, and sp
43 * - compare instructions allways set p6 and p7
47 * There are a lot of places where generated code is disassembled/patched.
48 * The automatic bundling of instructions done by the code generation macros
49 * could complicate things, so it is best to call
50 * ia64_codegen_set_one_ins_per_bundle () at those places.
53 #define ARGS_OFFSET 16
55 #define GP_SCRATCH_REG 31
56 #define GP_SCRATCH_REG2 30
57 #define FP_SCRATCH_REG 32
58 #define FP_SCRATCH_REG2 33
60 #define LOOP_ALIGNMENT 8
61 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
63 static const char* gregs [] = {
64 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
65 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
66 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29",
67 "r30", "r31", "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
68 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", "r48", "r49",
69 "r50", "r51", "r52", "r53", "r54", "r55", "r56", "r57", "r58", "r59",
70 "r60", "r61", "r62", "r63", "r64", "r65", "r66", "r67", "r68", "r69",
71 "r70", "r71", "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
72 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", "r88", "r89",
73 "r90", "r91", "r92", "r93", "r94", "r95", "r96", "r97", "r98", "r99",
74 "r100", "r101", "r102", "r103", "r104", "r105", "r106", "r107", "r108", "r109",
75 "r110", "r111", "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
76 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127"
80 mono_arch_regname (int reg)
88 static const char* fregs [] = {
89 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
90 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
91 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
92 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
93 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
94 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
95 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69",
96 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
97 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89",
98 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99",
99 "f100", "f101", "f102", "f103", "f104", "f105", "f106", "f107", "f108", "f109",
100 "f110", "f111", "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
101 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127"
105 mono_arch_fregname (int reg)
114 debug_ins_sched (void)
117 return mono_debug_count ();
127 return mono_debug_count ();
134 ia64_patch (unsigned char* code, gpointer target);
141 ArgValuetypeAddrInIReg,
159 /* Only if storage == ArgAggregate */
169 gboolean need_stack_align;
170 gboolean vtype_retaddr;
171 /* The index of the vret arg in the argument list */
178 #define DEBUG(a) if (cfg->verbose_level > 1) a
183 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
185 ainfo->offset = *stack_size;
187 if (*gr >= PARAM_REGS) {
188 ainfo->storage = ArgOnStack;
189 (*stack_size) += sizeof (gpointer);
192 ainfo->storage = ArgInIReg;
198 #define FLOAT_PARAM_REGS 8
201 add_float (guint32 *gr, guint32 *fr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
203 ainfo->offset = *stack_size;
205 if (*gr >= PARAM_REGS) {
206 ainfo->storage = ArgOnStack;
207 (*stack_size) += sizeof (gpointer);
210 ainfo->storage = is_double ? ArgInFloatReg : ArgInFloatRegR4;
211 ainfo->reg = 8 + *fr;
218 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
220 guint32 *gr, guint32 *fr, guint32 *stack_size)
224 MonoMarshalType *info;
225 gboolean is_hfa = TRUE;
226 guint32 hfa_type = 0;
228 klass = mono_class_from_mono_type (type);
229 if (type->type == MONO_TYPE_TYPEDBYREF)
230 size = 3 * sizeof (gpointer);
231 else if (sig->pinvoke)
232 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
234 size = mini_type_stack_size (&klass->byval_arg, NULL);
236 if (!sig->pinvoke || (size == 0)) {
237 /* Allways pass in memory */
238 ainfo->offset = *stack_size;
239 *stack_size += ALIGN_TO (size, 8);
240 ainfo->storage = ArgOnStack;
245 /* Determine whenever it is a HFA (Homogeneous Floating Point Aggregate) */
246 info = mono_marshal_load_type_info (klass);
248 for (i = 0; i < info->num_fields; ++i) {
249 guint32 ftype = info->fields [i].field->type->type;
250 if (!(info->fields [i].field->type->byref) &&
251 ((ftype == MONO_TYPE_R4) || (ftype == MONO_TYPE_R8))) {
254 else if (hfa_type != ftype)
263 ainfo->storage = ArgAggregate;
264 ainfo->atype = AggregateNormal;
267 ainfo->atype = hfa_type == MONO_TYPE_R4 ? AggregateSingleHFA : AggregateDoubleHFA;
269 if (info->num_fields <= 8) {
271 ainfo->nregs = info->num_fields;
272 ainfo->nslots = ainfo->nregs;
278 if ((*fr) + info->num_fields > 8)
281 ainfo->reg = 8 + (*fr);
282 ainfo->nregs = info->num_fields;
283 ainfo->nslots = ainfo->nregs;
284 (*fr) += info->num_fields;
285 if (ainfo->atype == AggregateSingleHFA) {
287 * FIXME: Have to keep track of the parameter slot number, which is
288 * not the same as *gr.
290 (*gr) += ALIGN_TO (info->num_fields, 2) / 2;
292 (*gr) += info->num_fields;
298 /* This also handles returning of TypedByRef used by some icalls */
301 ainfo->reg = IA64_R8;
302 ainfo->nregs = (size + 7) / 8;
303 ainfo->nslots = ainfo->nregs;
310 ainfo->offset = *stack_size;
311 ainfo->nslots = (size + 7) / 8;
313 if (((*gr) + ainfo->nslots) <= 8) {
314 /* Fits entirely in registers */
315 ainfo->nregs = ainfo->nslots;
316 (*gr) += ainfo->nregs;
320 ainfo->nregs = 8 - (*gr);
322 (*stack_size) += (ainfo->nslots - ainfo->nregs) * 8;
328 * Obtain information about a call according to the calling convention.
329 * For IA64, see the "Itanium Software Conventions and Runtime Architecture
330 * Gude" document for more information.
333 get_call_info (MonoCompile *cfg, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
335 guint32 i, gr, fr, pstart;
337 int n = sig->hasthis + sig->param_count;
338 guint32 stack_size = 0;
342 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
344 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
351 ret_type = mini_get_underlying_type (sig->ret);
352 switch (ret_type->type) {
353 case MONO_TYPE_BOOLEAN:
364 case MONO_TYPE_FNPTR:
365 case MONO_TYPE_CLASS:
366 case MONO_TYPE_OBJECT:
367 case MONO_TYPE_SZARRAY:
368 case MONO_TYPE_ARRAY:
369 case MONO_TYPE_STRING:
370 cinfo->ret.storage = ArgInIReg;
371 cinfo->ret.reg = IA64_R8;
375 cinfo->ret.storage = ArgInIReg;
376 cinfo->ret.reg = IA64_R8;
380 cinfo->ret.storage = ArgInFloatReg;
383 case MONO_TYPE_GENERICINST:
384 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
385 cinfo->ret.storage = ArgInIReg;
386 cinfo->ret.reg = IA64_R8;
390 case MONO_TYPE_VALUETYPE:
391 case MONO_TYPE_TYPEDBYREF: {
392 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
394 if (sig->ret->byref) {
395 /* This seems to happen with ldfld wrappers */
396 cinfo->ret.storage = ArgInIReg;
398 add_valuetype (sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
399 if (cinfo->ret.storage == ArgOnStack) {
400 /* The caller passes the address where the value is stored */
401 cinfo->vtype_retaddr = TRUE;
407 cinfo->ret.storage = ArgNone;
410 g_error ("Can't handle as return value 0x%x", sig->ret->type);
416 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
417 * the first argument, allowing 'this' to be always passed in the first arg reg.
418 * Also do this if the first argument is a reference type, since virtual calls
419 * are sometimes made using calli without sig->hasthis set, like in the delegate
422 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
424 add_general (&gr, &stack_size, cinfo->args + 0);
426 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
429 add_general (&gr, &stack_size, &cinfo->ret);
430 if (cinfo->ret.storage == ArgInIReg)
431 cinfo->ret.storage = ArgValuetypeAddrInIReg;
432 cinfo->vret_arg_index = 1;
436 add_general (&gr, &stack_size, cinfo->args + 0);
438 if (cinfo->vtype_retaddr) {
439 add_general (&gr, &stack_size, &cinfo->ret);
440 if (cinfo->ret.storage == ArgInIReg)
441 cinfo->ret.storage = ArgValuetypeAddrInIReg;
445 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
447 fr = FLOAT_PARAM_REGS;
449 /* Emit the signature cookie just before the implicit arguments */
450 add_general (&gr, &stack_size, &cinfo->sig_cookie);
453 for (i = pstart; i < sig->param_count; ++i) {
454 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
457 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
458 /* We allways pass the sig cookie on the stack for simplicity */
460 * Prevent implicit arguments + the sig cookie from being passed
464 fr = FLOAT_PARAM_REGS;
466 /* Emit the signature cookie just before the implicit arguments */
467 add_general (&gr, &stack_size, &cinfo->sig_cookie);
470 if (sig->params [i]->byref) {
471 add_general (&gr, &stack_size, ainfo);
474 ptype = mini_get_underlying_type (sig->params [i]);
475 switch (ptype->type) {
476 case MONO_TYPE_BOOLEAN:
479 add_general (&gr, &stack_size, ainfo);
484 add_general (&gr, &stack_size, ainfo);
488 add_general (&gr, &stack_size, ainfo);
493 case MONO_TYPE_FNPTR:
494 case MONO_TYPE_CLASS:
495 case MONO_TYPE_OBJECT:
496 case MONO_TYPE_STRING:
497 case MONO_TYPE_SZARRAY:
498 case MONO_TYPE_ARRAY:
499 add_general (&gr, &stack_size, ainfo);
501 case MONO_TYPE_GENERICINST:
502 if (!mono_type_generic_inst_is_valuetype (ptype)) {
503 add_general (&gr, &stack_size, ainfo);
507 case MONO_TYPE_VALUETYPE:
508 case MONO_TYPE_TYPEDBYREF:
510 /* We allways pass valuetypes on the stack */
511 add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
515 add_general (&gr, &stack_size, ainfo);
518 add_float (&gr, &fr, &stack_size, ainfo, FALSE);
521 add_float (&gr, &fr, &stack_size, ainfo, TRUE);
524 g_assert_not_reached ();
528 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
530 fr = FLOAT_PARAM_REGS;
532 /* Emit the signature cookie just before the implicit arguments */
533 add_general (&gr, &stack_size, &cinfo->sig_cookie);
536 cinfo->stack_usage = stack_size;
537 cinfo->reg_usage = gr;
538 cinfo->freg_usage = fr;
543 * mono_arch_get_argument_info:
544 * @csig: a method signature
545 * @param_count: the number of parameters to consider
546 * @arg_info: an array to store the result infos
548 * Gathers information on parameters such as size, alignment and
549 * padding. arg_info should be large enought to hold param_count + 1 entries.
551 * Returns the size of the argument area on the stack.
554 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
557 CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
558 guint32 args_size = cinfo->stack_usage;
560 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
562 arg_info [0].offset = 0;
565 for (k = 0; k < param_count; k++) {
566 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
568 arg_info [k + 1].size = 0;
577 * Initialize the cpu to execute managed code.
580 mono_arch_cpu_init (void)
585 * Initialize architecture specific code.
588 mono_arch_init (void)
593 * Cleanup architecture specific code.
596 mono_arch_cleanup (void)
601 mono_arch_have_fast_tls (void)
607 * This function returns the optimizations supported on this cpu.
610 mono_arch_cpu_optimizations (guint32 *exclude_mask)
618 * This function test for all SIMD functions supported.
620 * Returns a bitmask corresponding to all supported versions.
624 mono_arch_cpu_enumerate_simd_versions (void)
626 /* SIMD is currently unimplemented */
631 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
635 MonoMethodSignature *sig;
636 MonoMethodHeader *header;
639 header = cfg->header;
641 sig = mono_method_signature (cfg->method);
643 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
645 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
646 MonoInst *ins = cfg->args [i];
648 ArgInfo *ainfo = &cinfo->args [i];
650 if (ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT))
653 if (ainfo->storage == ArgInIReg) {
654 /* The input registers are non-volatile */
655 ins->opcode = OP_REGVAR;
656 ins->dreg = 32 + ainfo->reg;
660 for (i = 0; i < cfg->num_varinfo; i++) {
661 MonoInst *ins = cfg->varinfo [i];
662 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
665 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
668 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
669 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
672 if (mono_is_regsize_var (ins->inst_vtype)) {
673 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
674 g_assert (i == vmv->idx);
675 vars = g_list_prepend (vars, vmv);
679 vars = mono_varlist_sort (cfg, vars, 0);
685 mono_ia64_alloc_stacked_registers (MonoCompile *cfg)
688 guint32 reserved_regs;
689 MonoMethodHeader *header;
691 if (cfg->arch.reg_local0 > 0)
695 cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (cfg->method), FALSE);
697 header = cfg->header;
699 /* Some registers are reserved for use by the prolog/epilog */
700 reserved_regs = header->num_clauses ? 4 : 3;
702 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
703 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
704 /* One registers is needed by instrument_epilog to save the return value */
706 if (cinfo->reg_usage < 2)
707 /* Number of arguments passed to function call in instrument_prolog */
708 cinfo->reg_usage = 2;
711 cfg->arch.reg_in0 = 32;
712 cfg->arch.reg_local0 = cfg->arch.reg_in0 + cinfo->reg_usage + reserved_regs;
713 cfg->arch.reg_out0 = cfg->arch.reg_local0 + 16;
715 cfg->arch.reg_saved_ar_pfs = cfg->arch.reg_local0 - 1;
716 cfg->arch.reg_saved_b0 = cfg->arch.reg_local0 - 2;
717 cfg->arch.reg_fp = cfg->arch.reg_local0 - 3;
720 * Frames without handlers save sp to fp, frames with handlers save it into
721 * a dedicated register.
723 if (header->num_clauses)
724 cfg->arch.reg_saved_sp = cfg->arch.reg_local0 - 4;
726 cfg->arch.reg_saved_sp = cfg->arch.reg_fp;
728 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
729 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
730 cfg->arch.reg_saved_return_val = cfg->arch.reg_local0 - reserved_regs;
734 * Need to allocate at least 2 out register for use by OP_THROW / the system
735 * exception throwing code.
737 cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, 2);
741 mono_arch_get_global_int_regs (MonoCompile *cfg)
746 mono_ia64_alloc_stacked_registers (cfg);
748 for (i = cfg->arch.reg_local0; i < cfg->arch.reg_out0; ++i) {
751 regs = g_list_prepend (regs, (gpointer)(gssize)(i));
758 * mono_arch_regalloc_cost:
760 * Return the cost, in number of memory references, of the action of
761 * allocating the variable VMV into a register during global register
765 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
767 /* FIXME: Increase costs linearly to avoid using all local registers */
773 mono_arch_allocate_vars (MonoCompile *cfg)
775 MonoMethodSignature *sig;
776 MonoMethodHeader *header;
779 guint32 locals_stack_size, locals_stack_align;
783 header = cfg->header;
785 sig = mono_method_signature (cfg->method);
787 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
790 * Determine whenever the frame pointer can be eliminated.
791 * FIXME: Remove some of the restrictions.
793 cfg->arch.omit_fp = TRUE;
795 if (!debug_omit_fp ())
796 cfg->arch.omit_fp = FALSE;
798 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
799 cfg->arch.omit_fp = FALSE;
800 if (header->num_clauses)
801 cfg->arch.omit_fp = FALSE;
803 cfg->arch.omit_fp = FALSE;
804 if ((sig->ret->type != MONO_TYPE_VOID) && (cinfo->ret.storage == ArgAggregate))
805 cfg->arch.omit_fp = FALSE;
806 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
807 cfg->arch.omit_fp = FALSE;
808 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
809 ArgInfo *ainfo = &cinfo->args [i];
811 if (ainfo->storage == ArgOnStack) {
813 * The stack offset can only be determined when the frame
816 cfg->arch.omit_fp = FALSE;
820 mono_ia64_alloc_stacked_registers (cfg);
823 * We use the ABI calling conventions for managed code as well.
824 * Exception: valuetypes are never passed or returned in registers.
827 if (cfg->arch.omit_fp) {
828 cfg->flags |= MONO_CFG_HAS_SPILLUP;
829 cfg->frame_reg = IA64_SP;
830 offset = ARGS_OFFSET;
833 /* Locals are allocated backwards from %fp */
834 cfg->frame_reg = cfg->arch.reg_fp;
838 if (cfg->method->save_lmf) {
842 if (sig->ret->type != MONO_TYPE_VOID) {
843 switch (cinfo->ret.storage) {
845 cfg->ret->opcode = OP_REGVAR;
846 cfg->ret->inst_c0 = cinfo->ret.reg;
849 cfg->ret->opcode = OP_REGVAR;
850 cfg->ret->inst_c0 = cinfo->ret.reg;
852 case ArgValuetypeAddrInIReg:
853 cfg->vret_addr->opcode = OP_REGVAR;
854 cfg->vret_addr->dreg = cfg->arch.reg_in0 + cinfo->ret.reg;
857 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
858 if (cfg->arch.omit_fp)
859 g_assert_not_reached ();
860 offset = ALIGN_TO (offset, 8);
861 offset += cinfo->ret.nslots * 8;
862 cfg->ret->opcode = OP_REGOFFSET;
863 cfg->ret->inst_basereg = cfg->frame_reg;
864 cfg->ret->inst_offset = - offset;
867 g_assert_not_reached ();
869 cfg->ret->dreg = cfg->ret->inst_c0;
872 /* Allocate locals */
873 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE : TRUE, &locals_stack_size, &locals_stack_align);
874 if (locals_stack_align) {
875 offset = ALIGN_TO (offset, locals_stack_align);
877 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
878 if (offsets [i] != -1) {
879 MonoInst *inst = cfg->varinfo [i];
880 inst->opcode = OP_REGOFFSET;
881 inst->inst_basereg = cfg->frame_reg;
882 if (cfg->arch.omit_fp)
883 inst->inst_offset = (offset + offsets [i]);
885 inst->inst_offset = - (offset + offsets [i]);
886 // printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
889 offset += locals_stack_size;
891 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
892 if (cfg->arch.omit_fp)
893 g_assert_not_reached ();
894 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
895 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
898 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
899 inst = cfg->args [i];
900 if (inst->opcode != OP_REGVAR) {
901 ArgInfo *ainfo = &cinfo->args [i];
902 gboolean inreg = TRUE;
905 if (sig->hasthis && (i == 0))
906 arg_type = &mono_defaults.object_class->byval_arg;
908 arg_type = sig->params [i - sig->hasthis];
910 /* FIXME: VOLATILE is only set if the liveness pass runs */
911 if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
914 inst->opcode = OP_REGOFFSET;
916 switch (ainfo->storage) {
918 inst->opcode = OP_REGVAR;
919 inst->dreg = cfg->arch.reg_in0 + ainfo->reg;
922 case ArgInFloatRegR4:
924 * Since float regs are volatile, we save the arguments to
925 * the stack in the prolog.
930 if (cfg->arch.omit_fp)
931 g_assert_not_reached ();
932 inst->opcode = OP_REGOFFSET;
933 inst->inst_basereg = cfg->frame_reg;
934 inst->inst_offset = ARGS_OFFSET + ainfo->offset;
943 if (!inreg && (ainfo->storage != ArgOnStack)) {
946 inst->opcode = OP_REGOFFSET;
947 inst->inst_basereg = cfg->frame_reg;
948 /* These arguments are saved to the stack in the prolog */
949 switch (ainfo->storage) {
951 if (ainfo->atype == AggregateSingleHFA)
952 size = ainfo->nslots * 4;
954 size = ainfo->nslots * 8;
957 size = sizeof (gpointer);
961 offset = ALIGN_TO (offset, sizeof (gpointer));
963 if (cfg->arch.omit_fp) {
964 inst->inst_offset = offset;
968 inst->inst_offset = - offset;
975 * FIXME: This doesn't work because some variables are allocated during local
979 if (cfg->arch.omit_fp && offset == 16)
983 cfg->stack_offset = offset;
987 mono_arch_create_vars (MonoCompile *cfg)
989 MonoMethodSignature *sig;
992 sig = mono_method_signature (cfg->method);
994 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
996 if (cinfo->ret.storage == ArgAggregate)
997 cfg->ret_var_is_local = TRUE;
998 if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
999 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1000 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1001 printf ("vret_addr = ");
1002 mono_print_ins (cfg->vret_addr);
1008 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1012 MONO_INST_NEW (cfg, arg, OP_NOP);
1013 arg->sreg1 = tree->dreg;
1017 arg->opcode = OP_MOVE;
1018 arg->dreg = mono_alloc_ireg (cfg);
1020 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, FALSE);
1023 arg->opcode = OP_FMOVE;
1024 arg->dreg = mono_alloc_freg (cfg);
1026 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1028 case ArgInFloatRegR4:
1029 arg->opcode = OP_FCONV_TO_R4;
1030 arg->dreg = mono_alloc_freg (cfg);
1032 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1035 g_assert_not_reached ();
1038 MONO_ADD_INS (cfg->cbb, arg);
1042 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1044 MonoMethodSignature *tmp_sig;
1046 /* Emit the signature cookie just before the implicit arguments */
1048 /* FIXME: Add support for signature tokens to AOT */
1049 cfg->disable_aot = TRUE;
1051 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1054 * mono_ArgIterator_Setup assumes the signature cookie is
1055 * passed first and all the arguments which were before it are
1056 * passed on the stack after the signature. So compensate by
1057 * passing a different signature.
1059 tmp_sig = mono_metadata_signature_dup (call->signature);
1060 tmp_sig->param_count -= call->signature->sentinelpos;
1061 tmp_sig->sentinelpos = 0;
1062 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1064 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1065 sig_arg->dreg = mono_alloc_ireg (cfg);
1066 sig_arg->inst_p0 = tmp_sig;
1067 MONO_ADD_INS (cfg->cbb, sig_arg);
1069 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + cinfo->sig_cookie.offset, sig_arg->dreg);
1073 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1076 MonoMethodSignature *sig;
1077 int i, n, stack_size;
1083 mono_ia64_alloc_stacked_registers (cfg);
1085 sig = call->signature;
1086 n = sig->param_count + sig->hasthis;
1088 cinfo = get_call_info (cfg, cfg->mempool, sig, sig->pinvoke);
1090 if (cinfo->ret.storage == ArgAggregate) {
1095 * The valuetype is in registers after the call, need to be copied
1096 * to the stack. Save the address to a local here, so the call
1097 * instruction can access it.
1099 local = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1100 local->flags |= MONO_INST_VOLATILE;
1101 cfg->arch.ret_var_addr_local = local;
1103 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1104 vtarg->sreg1 = call->vret_var->dreg;
1105 vtarg->dreg = local->dreg;
1106 MONO_ADD_INS (cfg->cbb, vtarg);
1109 if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1110 add_outarg_reg (cfg, call, ArgInIReg, cfg->arch.reg_out0 + cinfo->ret.reg, call->vret_var);
1113 for (i = 0; i < n; ++i) {
1116 ainfo = cinfo->args + i;
1118 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1119 /* Emit the signature cookie just before the implicit arguments */
1120 emit_sig_cookie (cfg, call, cinfo);
1123 in = call->args [i];
1125 if (sig->hasthis && (i == 0))
1126 arg_type = &mono_defaults.object_class->byval_arg;
1128 arg_type = sig->params [i - sig->hasthis];
1130 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(arg_type))) {
1134 if (arg_type->type == MONO_TYPE_TYPEDBYREF) {
1135 size = sizeof (MonoTypedRef);
1136 align = sizeof (gpointer);
1138 else if (sig->pinvoke)
1139 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1142 * Other backends use mono_type_stack_size (), but that
1143 * aligns the size to 8, which is larger than the size of
1144 * the source, leading to reads of invalid memory if the
1145 * source is at the end of address space.
1147 size = mono_class_value_size (in->klass, &align);
1153 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1154 arg->sreg1 = in->dreg;
1155 arg->klass = in->klass;
1156 arg->backend.size = size;
1157 arg->inst_p0 = call;
1158 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1159 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1161 MONO_ADD_INS (cfg->cbb, arg);
1165 switch (ainfo->storage) {
1167 add_outarg_reg (cfg, call, ainfo->storage, cfg->arch.reg_out0 + ainfo->reg, in);
1170 case ArgInFloatRegR4:
1171 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1174 if (arg_type->type == MONO_TYPE_R4 && !arg_type->byref)
1175 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1176 else if (arg_type->type == MONO_TYPE_R8 && !arg_type->byref)
1177 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1179 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1182 g_assert_not_reached ();
1187 /* Handle the case where there are no implicit arguments */
1188 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1189 emit_sig_cookie (cfg, call, cinfo);
1192 call->stack_usage = cinfo->stack_usage;
1193 cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, cinfo->reg_usage);
1197 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1199 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1200 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1201 int size = ins->backend.size;
1203 if (ainfo->storage == ArgAggregate) {
1204 MonoInst *load, *store;
1208 * Part of the structure is passed in registers.
1210 for (i = 0; i < ainfo->nregs; ++i) {
1211 slot = ainfo->reg + i;
1213 if (ainfo->atype == AggregateSingleHFA) {
1214 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
1215 load->inst_basereg = src->dreg;
1216 load->inst_offset = i * 4;
1217 load->dreg = mono_alloc_freg (cfg);
1219 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1220 } else if (ainfo->atype == AggregateDoubleHFA) {
1221 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
1222 load->inst_basereg = src->dreg;
1223 load->inst_offset = i * 8;
1224 load->dreg = mono_alloc_freg (cfg);
1226 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1228 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1229 load->inst_basereg = src->dreg;
1230 load->inst_offset = i * 8;
1231 load->dreg = mono_alloc_ireg (cfg);
1233 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, cfg->arch.reg_out0 + ainfo->reg + i, FALSE);
1235 MONO_ADD_INS (cfg->cbb, load);
1239 * Part of the structure is passed on the stack.
1241 for (i = ainfo->nregs; i < ainfo->nslots; ++i) {
1242 slot = ainfo->reg + i;
1244 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1245 load->inst_basereg = src->dreg;
1246 load->inst_offset = i * sizeof (gpointer);
1247 load->dreg = mono_alloc_preg (cfg);
1248 MONO_ADD_INS (cfg->cbb, load);
1250 MONO_INST_NEW (cfg, store, OP_STOREI8_MEMBASE_REG);
1251 store->sreg1 = load->dreg;
1252 store->inst_destbasereg = IA64_SP;
1253 store->inst_offset = 16 + ainfo->offset + (slot - 8) * 8;
1254 MONO_ADD_INS (cfg->cbb, store);
1257 mini_emit_memcpy (cfg, IA64_SP, 16 + ainfo->offset, src->dreg, 0, size, 4);
1262 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1264 CallInfo *cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
1266 switch (cinfo->ret.storage) {
1268 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1271 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1274 g_assert_not_reached ();
1279 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1284 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1286 MonoInst *ins, *n, *last_ins = NULL;
1289 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1290 switch (ins->opcode) {
1298 if (ins->dreg == ins->sreg1) {
1299 MONO_DELETE_INS (bb, ins);
1305 * OP_MOVE sreg, dreg
1306 * OP_MOVE dreg, sreg
1308 if (last_ins && last_ins->opcode == OP_MOVE &&
1309 ins->sreg1 == last_ins->dreg &&
1310 ins->dreg == last_ins->sreg1) {
1311 MONO_DELETE_INS (bb, ins);
1317 /* remove unnecessary multiplication with 1 */
1318 if (ins->inst_imm == 1) {
1319 if (ins->dreg != ins->sreg1) {
1320 ins->opcode = OP_MOVE;
1322 MONO_DELETE_INS (bb, ins);
1332 bb->last_ins = last_ins;
1335 int cond_to_ia64_cmp [][3] = {
1336 {OP_IA64_CMP_EQ, OP_IA64_CMP4_EQ, OP_IA64_FCMP_EQ},
1337 {OP_IA64_CMP_NE, OP_IA64_CMP4_NE, OP_IA64_FCMP_NE},
1338 {OP_IA64_CMP_LE, OP_IA64_CMP4_LE, OP_IA64_FCMP_LE},
1339 {OP_IA64_CMP_GE, OP_IA64_CMP4_GE, OP_IA64_FCMP_GE},
1340 {OP_IA64_CMP_LT, OP_IA64_CMP4_LT, OP_IA64_FCMP_LT},
1341 {OP_IA64_CMP_GT, OP_IA64_CMP4_GT, OP_IA64_FCMP_GT},
1342 {OP_IA64_CMP_LE_UN, OP_IA64_CMP4_LE_UN, OP_IA64_FCMP_LE_UN},
1343 {OP_IA64_CMP_GE_UN, OP_IA64_CMP4_GE_UN, OP_IA64_FCMP_GE_UN},
1344 {OP_IA64_CMP_LT_UN, OP_IA64_CMP4_LT_UN, OP_IA64_FCMP_LT_UN},
1345 {OP_IA64_CMP_GT_UN, OP_IA64_CMP4_GT_UN, OP_IA64_FCMP_GT_UN}
1349 opcode_to_ia64_cmp (int opcode, int cmp_opcode)
1351 return cond_to_ia64_cmp [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1354 int cond_to_ia64_cmp_imm [][3] = {
1355 {OP_IA64_CMP_EQ_IMM, OP_IA64_CMP4_EQ_IMM, 0},
1356 {OP_IA64_CMP_NE_IMM, OP_IA64_CMP4_NE_IMM, 0},
1357 {OP_IA64_CMP_GE_IMM, OP_IA64_CMP4_GE_IMM, 0},
1358 {OP_IA64_CMP_LE_IMM, OP_IA64_CMP4_LE_IMM, 0},
1359 {OP_IA64_CMP_GT_IMM, OP_IA64_CMP4_GT_IMM, 0},
1360 {OP_IA64_CMP_LT_IMM, OP_IA64_CMP4_LT_IMM, 0},
1361 {OP_IA64_CMP_GE_UN_IMM, OP_IA64_CMP4_GE_UN_IMM, 0},
1362 {OP_IA64_CMP_LE_UN_IMM, OP_IA64_CMP4_LE_UN_IMM, 0},
1363 {OP_IA64_CMP_GT_UN_IMM, OP_IA64_CMP4_GT_UN_IMM, 0},
1364 {OP_IA64_CMP_LT_UN_IMM, OP_IA64_CMP4_LT_UN_IMM, 0},
1368 opcode_to_ia64_cmp_imm (int opcode, int cmp_opcode)
1370 /* The condition needs to be reversed */
1371 return cond_to_ia64_cmp_imm [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1374 #define NEW_INS(cfg,dest,op) do { \
1375 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
1376 (dest)->opcode = (op); \
1377 mono_bblock_insert_after_ins (bb, last_ins, (dest)); \
1378 last_ins = (dest); \
1382 * mono_arch_lowering_pass:
1384 * Converts complex opcodes into simpler ones so that each IR instruction
1385 * corresponds to one machine instruction.
1388 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1390 MonoInst *ins, *n, *next, *temp, *temp2, *temp3, *last_ins = NULL;
1393 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1394 switch (ins->opcode) {
1395 case OP_STOREI1_MEMBASE_IMM:
1396 case OP_STOREI2_MEMBASE_IMM:
1397 case OP_STOREI4_MEMBASE_IMM:
1398 case OP_STOREI8_MEMBASE_IMM:
1399 case OP_STORE_MEMBASE_IMM:
1400 /* There are no store_membase instructions on ia64 */
1401 if (ins->inst_offset == 0) {
1403 } else if (ia64_is_imm14 (ins->inst_offset)) {
1404 NEW_INS (cfg, temp2, OP_ADD_IMM);
1405 temp2->sreg1 = ins->inst_destbasereg;
1406 temp2->inst_imm = ins->inst_offset;
1407 temp2->dreg = mono_alloc_ireg (cfg);
1410 NEW_INS (cfg, temp, OP_I8CONST);
1411 temp->inst_c0 = ins->inst_offset;
1412 temp->dreg = mono_alloc_ireg (cfg);
1414 NEW_INS (cfg, temp2, OP_LADD);
1415 temp2->sreg1 = ins->inst_destbasereg;
1416 temp2->sreg2 = temp->dreg;
1417 temp2->dreg = mono_alloc_ireg (cfg);
1420 switch (ins->opcode) {
1421 case OP_STOREI1_MEMBASE_IMM:
1422 ins->opcode = OP_STOREI1_MEMBASE_REG;
1424 case OP_STOREI2_MEMBASE_IMM:
1425 ins->opcode = OP_STOREI2_MEMBASE_REG;
1427 case OP_STOREI4_MEMBASE_IMM:
1428 ins->opcode = OP_STOREI4_MEMBASE_REG;
1430 case OP_STOREI8_MEMBASE_IMM:
1431 case OP_STORE_MEMBASE_IMM:
1432 ins->opcode = OP_STOREI8_MEMBASE_REG;
1435 g_assert_not_reached ();
1438 if (ins->inst_imm == 0)
1439 ins->sreg1 = IA64_R0;
1441 NEW_INS (cfg, temp3, OP_I8CONST);
1442 temp3->inst_c0 = ins->inst_imm;
1443 temp3->dreg = mono_alloc_ireg (cfg);
1444 ins->sreg1 = temp3->dreg;
1447 ins->inst_offset = 0;
1449 ins->inst_destbasereg = temp2->dreg;
1451 case OP_STOREI1_MEMBASE_REG:
1452 case OP_STOREI2_MEMBASE_REG:
1453 case OP_STOREI4_MEMBASE_REG:
1454 case OP_STOREI8_MEMBASE_REG:
1455 case OP_STORER4_MEMBASE_REG:
1456 case OP_STORER8_MEMBASE_REG:
1457 case OP_STORE_MEMBASE_REG:
1458 /* There are no store_membase instructions on ia64 */
1459 if (ins->inst_offset == 0) {
1462 else if (ia64_is_imm14 (ins->inst_offset)) {
1463 NEW_INS (cfg, temp2, OP_ADD_IMM);
1464 temp2->sreg1 = ins->inst_destbasereg;
1465 temp2->inst_imm = ins->inst_offset;
1466 temp2->dreg = mono_alloc_ireg (cfg);
1469 NEW_INS (cfg, temp, OP_I8CONST);
1470 temp->inst_c0 = ins->inst_offset;
1471 temp->dreg = mono_alloc_ireg (cfg);
1472 NEW_INS (cfg, temp2, OP_LADD);
1473 temp2->sreg1 = ins->inst_destbasereg;
1474 temp2->sreg2 = temp->dreg;
1475 temp2->dreg = mono_alloc_ireg (cfg);
1478 ins->inst_offset = 0;
1479 ins->inst_destbasereg = temp2->dreg;
1481 case OP_LOADI1_MEMBASE:
1482 case OP_LOADU1_MEMBASE:
1483 case OP_LOADI2_MEMBASE:
1484 case OP_LOADU2_MEMBASE:
1485 case OP_LOADI4_MEMBASE:
1486 case OP_LOADU4_MEMBASE:
1487 case OP_LOADI8_MEMBASE:
1488 case OP_LOAD_MEMBASE:
1489 case OP_LOADR4_MEMBASE:
1490 case OP_LOADR8_MEMBASE:
1491 case OP_ATOMIC_EXCHANGE_I4:
1492 case OP_ATOMIC_EXCHANGE_I8:
1493 case OP_ATOMIC_ADD_I4:
1494 case OP_ATOMIC_ADD_I8:
1495 case OP_ATOMIC_ADD_IMM_I4:
1496 case OP_ATOMIC_ADD_IMM_I8:
1497 /* There are no membase instructions on ia64 */
1498 if (ins->inst_offset == 0) {
1501 else if (ia64_is_imm14 (ins->inst_offset)) {
1502 NEW_INS (cfg, temp2, OP_ADD_IMM);
1503 temp2->sreg1 = ins->inst_basereg;
1504 temp2->inst_imm = ins->inst_offset;
1505 temp2->dreg = mono_alloc_ireg (cfg);
1508 NEW_INS (cfg, temp, OP_I8CONST);
1509 temp->inst_c0 = ins->inst_offset;
1510 temp->dreg = mono_alloc_ireg (cfg);
1511 NEW_INS (cfg, temp2, OP_LADD);
1512 temp2->sreg1 = ins->inst_basereg;
1513 temp2->sreg2 = temp->dreg;
1514 temp2->dreg = mono_alloc_ireg (cfg);
1517 ins->inst_offset = 0;
1518 ins->inst_basereg = temp2->dreg;
1538 case OP_ISHR_UN_IMM:
1539 case OP_LSHR_UN_IMM: {
1540 gboolean is_imm = FALSE;
1541 gboolean switched = FALSE;
1543 if (ins->opcode == OP_AND_IMM && ins->inst_imm == 255) {
1544 ins->opcode = OP_ZEXT_I1;
1548 switch (ins->opcode) {
1552 is_imm = ia64_is_imm14 (ins->inst_imm);
1557 is_imm = ia64_is_imm14 (- (ins->inst_imm));
1559 /* A = B - IMM -> A = B + (-IMM) */
1560 ins->inst_imm = - ins->inst_imm;
1561 ins->opcode = OP_IADD_IMM;
1572 is_imm = ia64_is_imm8 (ins->inst_imm);
1581 case OP_ISHR_UN_IMM:
1582 case OP_LSHR_UN_IMM:
1583 is_imm = (ins->inst_imm >= 0) && (ins->inst_imm < 64);
1591 ins->sreg2 = ins->sreg1;
1595 if (mono_op_imm_to_op (ins->opcode) == -1)
1596 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
1597 ins->opcode = mono_op_imm_to_op (ins->opcode);
1599 if (ins->inst_imm == 0)
1600 ins->sreg2 = IA64_R0;
1602 NEW_INS (cfg, temp, OP_I8CONST);
1603 temp->inst_c0 = ins->inst_imm;
1604 temp->dreg = mono_alloc_ireg (cfg);
1605 ins->sreg2 = temp->dreg;
1609 case OP_COMPARE_IMM:
1610 case OP_ICOMPARE_IMM:
1611 case OP_LCOMPARE_IMM: {
1612 /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1618 /* Branch opts can eliminate the branch */
1619 if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1625 * The compare_imm instructions have switched up arguments, and
1626 * some of them take an imm between -127 and 128.
1629 cond = mono_opcode_to_cond (next->opcode);
1630 if ((cond == CMP_LT) || (cond == CMP_GE))
1631 imm = ia64_is_imm8 (ins->inst_imm - 1);
1632 else if ((cond == CMP_LT_UN) || (cond == CMP_GE_UN))
1633 imm = ia64_is_imm8 (ins->inst_imm - 1) && (ins->inst_imm > 0);
1635 imm = ia64_is_imm8 (ins->inst_imm);
1638 ins->opcode = opcode_to_ia64_cmp_imm (next->opcode, ins->opcode);
1639 ins->sreg2 = ins->sreg1;
1642 ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1644 if (ins->inst_imm == 0)
1645 ins->sreg2 = IA64_R0;
1647 NEW_INS (cfg, temp, OP_I8CONST);
1648 temp->inst_c0 = ins->inst_imm;
1649 temp->dreg = mono_alloc_ireg (cfg);
1650 ins->sreg2 = temp->dreg;
1654 if (MONO_IS_COND_BRANCH_OP (next)) {
1655 next->opcode = OP_IA64_BR_COND;
1656 next->inst_target_bb = next->inst_true_bb;
1657 } else if (MONO_IS_COND_EXC (next)) {
1658 next->opcode = OP_IA64_COND_EXC;
1659 } else if (MONO_IS_SETCC (next)) {
1660 next->opcode = OP_IA64_CSET;
1662 printf ("%s\n", mono_inst_name (next->opcode));
1672 /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1676 /* Branch opts can eliminate the branch */
1677 if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1682 ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1684 if (MONO_IS_COND_BRANCH_OP (next)) {
1685 next->opcode = OP_IA64_BR_COND;
1686 next->inst_target_bb = next->inst_true_bb;
1687 } else if (MONO_IS_COND_EXC (next)) {
1688 next->opcode = OP_IA64_COND_EXC;
1689 } else if (MONO_IS_SETCC (next)) {
1690 next->opcode = OP_IA64_CSET;
1692 printf ("%s\n", mono_inst_name (next->opcode));
1703 /* The front end removes the fcompare, so introduce it again */
1704 NEW_INS (cfg, temp, opcode_to_ia64_cmp (ins->opcode, OP_FCOMPARE));
1705 temp->sreg1 = ins->sreg1;
1706 temp->sreg2 = ins->sreg2;
1708 ins->opcode = OP_IA64_CSET;
1709 MONO_INST_NULLIFY_SREGS (ins);
1715 gboolean found = FALSE;
1716 int shl_op = ins->opcode == OP_IMUL_IMM ? OP_ISHL_IMM : OP_SHL_IMM;
1718 /* First the easy cases */
1719 if (ins->inst_imm == 1) {
1720 ins->opcode = OP_MOVE;
1723 for (i = 1; i < 64; ++i)
1724 if (ins->inst_imm == (((gint64)1) << i)) {
1725 ins->opcode = shl_op;
1731 /* This could be optimized */
1734 for (i = 0; i < 64; ++i) {
1735 if (ins->inst_imm & (((gint64)1) << i)) {
1736 NEW_INS (cfg, temp, shl_op);
1737 temp->dreg = mono_alloc_ireg (cfg);
1738 temp->sreg1 = ins->sreg1;
1742 sum_reg = temp->dreg;
1744 NEW_INS (cfg, temp2, OP_LADD);
1745 temp2->dreg = mono_alloc_ireg (cfg);
1746 temp2->sreg1 = sum_reg;
1747 temp2->sreg2 = temp->dreg;
1748 sum_reg = temp2->dreg;
1752 ins->opcode = OP_MOVE;
1753 ins->sreg1 = sum_reg;
1757 case OP_LCONV_TO_OVF_U4:
1758 NEW_INS (cfg, temp, OP_IA64_CMP4_LT);
1759 temp->sreg1 = ins->sreg1;
1760 temp->sreg2 = IA64_R0;
1762 NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1763 temp->inst_p1 = (char*)"OverflowException";
1765 ins->opcode = OP_MOVE;
1767 case OP_LCONV_TO_OVF_I4_UN:
1768 NEW_INS (cfg, temp, OP_ICONST);
1769 temp->inst_c0 = 0x7fffffff;
1770 temp->dreg = mono_alloc_ireg (cfg);
1772 NEW_INS (cfg, temp2, OP_IA64_CMP4_GT_UN);
1773 temp2->sreg1 = ins->sreg1;
1774 temp2->sreg2 = temp->dreg;
1776 NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1777 temp->inst_p1 = (char*)"OverflowException";
1779 ins->opcode = OP_MOVE;
1781 case OP_FCONV_TO_I4:
1782 case OP_FCONV_TO_I2:
1783 case OP_FCONV_TO_U2:
1784 case OP_FCONV_TO_I1:
1785 case OP_FCONV_TO_U1:
1786 NEW_INS (cfg, temp, OP_FCONV_TO_I8);
1787 temp->sreg1 = ins->sreg1;
1788 temp->dreg = ins->dreg;
1790 switch (ins->opcode) {
1791 case OP_FCONV_TO_I4:
1792 ins->opcode = OP_SEXT_I4;
1794 case OP_FCONV_TO_I2:
1795 ins->opcode = OP_SEXT_I2;
1797 case OP_FCONV_TO_U2:
1798 ins->opcode = OP_ZEXT_I4;
1800 case OP_FCONV_TO_I1:
1801 ins->opcode = OP_SEXT_I1;
1803 case OP_FCONV_TO_U1:
1804 ins->opcode = OP_ZEXT_I1;
1807 g_assert_not_reached ();
1809 ins->sreg1 = ins->dreg;
1817 bb->last_ins = last_ins;
1819 bb->max_vreg = cfg->next_vreg;
1823 * emit_load_volatile_arguments:
1825 * Load volatile arguments from the stack to the original input registers.
1826 * Required before a tail call.
1828 static Ia64CodegenState
1829 emit_load_volatile_arguments (MonoCompile *cfg, Ia64CodegenState code)
1831 MonoMethod *method = cfg->method;
1832 MonoMethodSignature *sig;
1837 /* FIXME: Generate intermediate code instead */
1839 sig = mono_method_signature (method);
1841 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
1843 /* This is the opposite of the code in emit_prolog */
1844 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1845 ArgInfo *ainfo = cinfo->args + i;
1846 gint32 stack_offset;
1849 ins = cfg->args [i];
1851 if (sig->hasthis && (i == 0))
1852 arg_type = &mono_defaults.object_class->byval_arg;
1854 arg_type = sig->params [i - sig->hasthis];
1856 arg_type = mini_get_underlying_type (arg_type);
1858 stack_offset = ainfo->offset + ARGS_OFFSET;
1860 /* Save volatile arguments to the stack */
1861 if (ins->opcode != OP_REGVAR) {
1862 switch (ainfo->storage) {
1865 /* FIXME: big offsets */
1866 g_assert (ins->opcode == OP_REGOFFSET);
1867 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
1868 if (arg_type->byref)
1869 ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1871 switch (arg_type->type) {
1873 ia64_ldfs (code, ainfo->reg, GP_SCRATCH_REG);
1876 ia64_ldfd (code, ainfo->reg, GP_SCRATCH_REG);
1879 ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1891 if (ins->opcode == OP_REGVAR) {
1892 /* Argument allocated to (non-volatile) register */
1893 switch (ainfo->storage) {
1895 if (ins->dreg != cfg->arch.reg_in0 + ainfo->reg)
1896 ia64_mov (code, cfg->arch.reg_in0 + ainfo->reg, ins->dreg);
1899 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
1900 ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
1911 static Ia64CodegenState
1912 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, Ia64CodegenState code)
1917 /* Move return value to the target register */
1918 switch (ins->opcode) {
1920 case OP_VOIDCALL_REG:
1921 case OP_VOIDCALL_MEMBASE:
1925 case OP_CALL_MEMBASE:
1928 case OP_LCALL_MEMBASE:
1929 g_assert (ins->dreg == IA64_R8);
1933 case OP_FCALL_MEMBASE:
1934 g_assert (ins->dreg == 8);
1935 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4)
1936 ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
1940 case OP_VCALL_MEMBASE:
1943 case OP_VCALL2_MEMBASE: {
1946 cinfo = get_call_info (cfg, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
1947 storage = cinfo->ret.storage;
1949 if (storage == ArgAggregate) {
1950 MonoInst *local = (MonoInst*)cfg->arch.ret_var_addr_local;
1952 /* Load address of stack space allocated for the return value */
1953 ia64_movl (code, GP_SCRATCH_REG, local->inst_offset);
1954 ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, local->inst_basereg);
1955 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
1957 for (i = 0; i < cinfo->ret.nregs; ++i) {
1958 switch (cinfo->ret.atype) {
1959 case AggregateNormal:
1960 ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1962 case AggregateSingleHFA:
1963 ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 4, 0);
1965 case AggregateDoubleHFA:
1966 ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1969 g_assert_not_reached ();
1976 g_assert_not_reached ();
1982 #define add_patch_info(cfg,code,patch_type,data) do { \
1983 mono_add_patch_info (cfg, code.buf + code.nins - cfg->native_code, patch_type, data); \
1986 #define emit_cond_system_exception(cfg,code,exc_name,predicate) do { \
1987 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1989 add_patch_info (cfg, code, MONO_PATCH_INFO_EXC, exc_name); \
1991 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, tins->inst_true_bb); \
1992 ia64_br_cond_pred (code, (predicate), 0); \
1995 static Ia64CodegenState
1996 emit_call (MonoCompile *cfg, Ia64CodegenState code, guint32 patch_type, gconstpointer data)
1998 add_patch_info (cfg, code, patch_type, data);
2000 if ((patch_type == MONO_PATCH_INFO_ABS) || (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD)) {
2002 /* mono_arch_patch_callsite will patch this */
2003 ia64_movl (code, GP_SCRATCH_REG, 0);
2004 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
2005 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2006 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
2007 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2010 /* Can't use a direct call since the displacement might be too small */
2011 /* mono_arch_patch_callsite will patch this */
2012 ia64_movl (code, GP_SCRATCH_REG, 0);
2013 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2014 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2020 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2023 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2028 Ia64CodegenState code;
2029 guint8 *code_start = cfg->native_code + cfg->code_len;
2030 MonoInst *last_ins = NULL;
2031 guint last_offset = 0;
2034 if (cfg->opt & MONO_OPT_LOOP) {
2038 if (cfg->verbose_level > 2)
2039 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2041 cpos = bb->max_offset;
2043 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2047 offset = code_start - cfg->native_code;
2049 ia64_codegen_init (code, code_start);
2052 if (strstr (cfg->method->name, "conv_ovf_i1") && (bb->block_num == 2))
2056 MONO_BB_FOR_EACH_INS (bb, ins) {
2057 offset = code.buf - cfg->native_code;
2059 max_len = ((int)(((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN])) + 128;
2061 while (offset + max_len + 16 > cfg->code_size) {
2062 ia64_codegen_close (code);
2064 offset = code.buf - cfg->native_code;
2066 cfg->code_size *= 2;
2067 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2068 code_start = cfg->native_code + offset;
2069 cfg->stat_code_reallocs++;
2071 ia64_codegen_init (code, code_start);
2074 mono_debug_record_line_number (cfg, ins, offset);
2076 switch (ins->opcode) {
2079 if (ia64_is_imm14 (ins->inst_c0))
2080 ia64_adds_imm (code, ins->dreg, ins->inst_c0, IA64_R0);
2082 ia64_movl (code, ins->dreg, ins->inst_c0);
2085 add_patch_info (cfg, code, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2086 ia64_movl (code, ins->dreg, 0);
2089 ia64_mov (code, ins->dreg, ins->sreg1);
2092 case OP_IA64_BR_COND: {
2094 if (ins->opcode == OP_IA64_BR_COND)
2096 if (ins->inst_target_bb->native_offset) {
2097 guint8 *pos = code.buf + code.nins;
2099 ia64_br_cond_pred (code, pred, 0);
2100 ia64_begin_bundle (code);
2101 ia64_patch (pos, cfg->native_code + ins->inst_target_bb->native_offset);
2103 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2104 ia64_br_cond_pred (code, pred, 0);
2109 ia64_begin_bundle (code);
2110 ins->inst_c0 = code.buf - cfg->native_code;
2113 case OP_RELAXED_NOP:
2115 case OP_DUMMY_STORE:
2116 case OP_NOT_REACHED:
2120 ia64_mov_to_br (code, IA64_B6, ins->sreg1);
2121 ia64_br_cond_reg (code, IA64_B6);
2125 ia64_add (code, ins->dreg, ins->sreg1, ins->sreg2);
2129 ia64_sub (code, ins->dreg, ins->sreg1, ins->sreg2);
2133 ia64_and (code, ins->dreg, ins->sreg1, ins->sreg2);
2137 ia64_or (code, ins->dreg, ins->sreg1, ins->sreg2);
2141 ia64_xor (code, ins->dreg, ins->sreg1, ins->sreg2);
2145 ia64_sub (code, ins->dreg, IA64_R0, ins->sreg1);
2149 ia64_andcm_imm (code, ins->dreg, -1, ins->sreg1);
2153 ia64_shl (code, ins->dreg, ins->sreg1, ins->sreg2);
2156 ia64_sxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2157 ia64_shr (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2160 ia64_shr (code, ins->dreg, ins->sreg1, ins->sreg2);
2163 ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2164 ia64_shr_u (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2167 ia64_shr_u (code, ins->dreg, ins->sreg1, ins->sreg2);
2170 /* p6 and p7 is set if there is signed/unsigned overflow */
2172 /* Set p8-p9 == (sreg2 > 0) */
2173 ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2175 ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2177 /* (sreg2 > 0) && (res < ins->sreg1) => signed overflow */
2178 ia64_cmp4_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2179 /* (sreg2 <= 0) && (res > ins->sreg1) => signed overflow */
2180 ia64_cmp4_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2182 /* res <u sreg1 => unsigned overflow */
2183 ia64_cmp4_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2185 /* FIXME: Predicate this since this is a side effect */
2186 ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2189 /* p6 and p7 is set if there is signed/unsigned overflow */
2191 /* Set p8-p9 == (sreg2 > 0) */
2192 ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2194 ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2196 /* (sreg2 > 0) && (res > ins->sreg1) => signed overflow */
2197 ia64_cmp4_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2198 /* (sreg2 <= 0) && (res < ins->sreg1) => signed overflow */
2199 ia64_cmp4_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2201 /* sreg1 <u sreg2 => unsigned overflow */
2202 ia64_cmp4_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2204 /* FIXME: Predicate this since this is a side effect */
2205 ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2208 /* Same as OP_IADDCC */
2209 ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2211 ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2213 ia64_cmp_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2214 ia64_cmp_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2216 ia64_cmp_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2218 ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2221 /* Same as OP_ISUBCC */
2223 ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2225 ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2227 ia64_cmp_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2228 ia64_cmp_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2230 ia64_cmp_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2232 ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2237 ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2242 ia64_and_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2246 ia64_or_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2250 ia64_xor_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2255 ia64_shl_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2259 ia64_shr_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2262 g_assert (ins->inst_imm <= 64);
2263 ia64_extr (code, ins->dreg, ins->sreg1, ins->inst_imm, 32 - ins->inst_imm);
2265 case OP_ISHR_UN_IMM:
2266 ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2267 ia64_shr_u_imm (code, ins->dreg, GP_SCRATCH_REG, ins->inst_imm);
2269 case OP_LSHR_UN_IMM:
2270 ia64_shr_u_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2273 /* Based on gcc code */
2274 ia64_setf_sig (code, FP_SCRATCH_REG, ins->sreg1);
2275 ia64_setf_sig (code, FP_SCRATCH_REG2, ins->sreg2);
2276 ia64_xmpy_l (code, FP_SCRATCH_REG, FP_SCRATCH_REG, FP_SCRATCH_REG2);
2277 ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2280 case OP_STOREI1_MEMBASE_REG:
2281 ia64_st1_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2283 case OP_STOREI2_MEMBASE_REG:
2284 ia64_st2_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2286 case OP_STOREI4_MEMBASE_REG:
2287 ia64_st4_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2289 case OP_STOREI8_MEMBASE_REG:
2290 case OP_STORE_MEMBASE_REG:
2291 if (ins->inst_offset != 0) {
2292 /* This is generated by local regalloc */
2293 if (ia64_is_imm14 (ins->inst_offset)) {
2294 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2296 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2297 ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2299 ins->inst_destbasereg = GP_SCRATCH_REG;
2301 ia64_st8_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2304 case OP_IA64_STOREI1_MEMBASE_INC_REG:
2305 ia64_st1_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 1, 0);
2307 case OP_IA64_STOREI2_MEMBASE_INC_REG:
2308 ia64_st2_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 2, 0);
2310 case OP_IA64_STOREI4_MEMBASE_INC_REG:
2311 ia64_st4_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 4, 0);
2313 case OP_IA64_STOREI8_MEMBASE_INC_REG:
2314 ia64_st8_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 8, 0);
2317 case OP_LOADU1_MEMBASE:
2318 ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2320 case OP_LOADU2_MEMBASE:
2321 ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2323 case OP_LOADU4_MEMBASE:
2324 ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2326 case OP_LOADI1_MEMBASE:
2327 ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2328 ia64_sxt1 (code, ins->dreg, ins->dreg);
2330 case OP_LOADI2_MEMBASE:
2331 ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2332 ia64_sxt2 (code, ins->dreg, ins->dreg);
2334 case OP_LOADI4_MEMBASE:
2335 ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2336 ia64_sxt4 (code, ins->dreg, ins->dreg);
2338 case OP_LOAD_MEMBASE:
2339 case OP_LOADI8_MEMBASE:
2340 if (ins->inst_offset != 0) {
2341 /* This is generated by local regalloc */
2342 if (ia64_is_imm14 (ins->inst_offset)) {
2343 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2345 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2346 ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2348 ins->inst_basereg = GP_SCRATCH_REG;
2350 ia64_ld8 (code, ins->dreg, ins->inst_basereg);
2353 case OP_IA64_LOADU1_MEMBASE_INC:
2354 ia64_ld1_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 1, 0);
2356 case OP_IA64_LOADU2_MEMBASE_INC:
2357 ia64_ld2_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 2, 0);
2359 case OP_IA64_LOADU4_MEMBASE_INC:
2360 ia64_ld4_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 4, 0);
2362 case OP_IA64_LOADI8_MEMBASE_INC:
2363 ia64_ld8_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 8, 0);
2367 ia64_sxt1 (code, ins->dreg, ins->sreg1);
2370 ia64_sxt2 (code, ins->dreg, ins->sreg1);
2373 ia64_sxt4 (code, ins->dreg, ins->sreg1);
2376 ia64_zxt1 (code, ins->dreg, ins->sreg1);
2379 ia64_zxt2 (code, ins->dreg, ins->sreg1);
2382 ia64_zxt4 (code, ins->dreg, ins->sreg1);
2385 /* Compare opcodes */
2386 case OP_IA64_CMP4_EQ:
2387 ia64_cmp4_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2389 case OP_IA64_CMP4_NE:
2390 ia64_cmp4_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2392 case OP_IA64_CMP4_LE:
2393 ia64_cmp4_le (code, 6, 7, ins->sreg1, ins->sreg2);
2395 case OP_IA64_CMP4_LT:
2396 ia64_cmp4_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2398 case OP_IA64_CMP4_GE:
2399 ia64_cmp4_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2401 case OP_IA64_CMP4_GT:
2402 ia64_cmp4_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2404 case OP_IA64_CMP4_LT_UN:
2405 ia64_cmp4_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2407 case OP_IA64_CMP4_LE_UN:
2408 ia64_cmp4_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2410 case OP_IA64_CMP4_GT_UN:
2411 ia64_cmp4_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2413 case OP_IA64_CMP4_GE_UN:
2414 ia64_cmp4_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2416 case OP_IA64_CMP_EQ:
2417 ia64_cmp_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2419 case OP_IA64_CMP_NE:
2420 ia64_cmp_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2422 case OP_IA64_CMP_LE:
2423 ia64_cmp_le (code, 6, 7, ins->sreg1, ins->sreg2);
2425 case OP_IA64_CMP_LT:
2426 ia64_cmp_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2428 case OP_IA64_CMP_GE:
2429 ia64_cmp_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2431 case OP_IA64_CMP_GT:
2432 ia64_cmp_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2434 case OP_IA64_CMP_GT_UN:
2435 ia64_cmp_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2437 case OP_IA64_CMP_LT_UN:
2438 ia64_cmp_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2440 case OP_IA64_CMP_GE_UN:
2441 ia64_cmp_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2443 case OP_IA64_CMP_LE_UN:
2444 ia64_cmp_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2446 case OP_IA64_CMP4_EQ_IMM:
2447 ia64_cmp4_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2449 case OP_IA64_CMP4_NE_IMM:
2450 ia64_cmp4_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2452 case OP_IA64_CMP4_LE_IMM:
2453 ia64_cmp4_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2455 case OP_IA64_CMP4_LT_IMM:
2456 ia64_cmp4_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2458 case OP_IA64_CMP4_GE_IMM:
2459 ia64_cmp4_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2461 case OP_IA64_CMP4_GT_IMM:
2462 ia64_cmp4_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2464 case OP_IA64_CMP4_LT_UN_IMM:
2465 ia64_cmp4_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2467 case OP_IA64_CMP4_LE_UN_IMM:
2468 ia64_cmp4_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2470 case OP_IA64_CMP4_GT_UN_IMM:
2471 ia64_cmp4_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2473 case OP_IA64_CMP4_GE_UN_IMM:
2474 ia64_cmp4_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2476 case OP_IA64_CMP_EQ_IMM:
2477 ia64_cmp_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2479 case OP_IA64_CMP_NE_IMM:
2480 ia64_cmp_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2482 case OP_IA64_CMP_LE_IMM:
2483 ia64_cmp_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2485 case OP_IA64_CMP_LT_IMM:
2486 ia64_cmp_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2488 case OP_IA64_CMP_GE_IMM:
2489 ia64_cmp_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2491 case OP_IA64_CMP_GT_IMM:
2492 ia64_cmp_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2494 case OP_IA64_CMP_GT_UN_IMM:
2495 ia64_cmp_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2497 case OP_IA64_CMP_LT_UN_IMM:
2498 ia64_cmp_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2500 case OP_IA64_CMP_GE_UN_IMM:
2501 ia64_cmp_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2503 case OP_IA64_CMP_LE_UN_IMM:
2504 ia64_cmp_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2506 case OP_IA64_FCMP_EQ:
2507 ia64_fcmp_eq_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2509 case OP_IA64_FCMP_NE:
2510 ia64_fcmp_ne_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2512 case OP_IA64_FCMP_LT:
2513 ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2515 case OP_IA64_FCMP_GT:
2516 ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2518 case OP_IA64_FCMP_LE:
2519 ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2521 case OP_IA64_FCMP_GE:
2522 ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2524 case OP_IA64_FCMP_GT_UN:
2525 ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2526 ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2528 case OP_IA64_FCMP_LT_UN:
2529 ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2530 ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2532 case OP_IA64_FCMP_GE_UN:
2533 ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2534 ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2536 case OP_IA64_FCMP_LE_UN:
2537 ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2538 ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2541 case OP_COND_EXC_IOV:
2542 case OP_COND_EXC_OV:
2543 emit_cond_system_exception (cfg, code, "OverflowException", 6);
2545 case OP_COND_EXC_IC:
2547 emit_cond_system_exception (cfg, code, "OverflowException", 7);
2549 case OP_IA64_COND_EXC:
2550 emit_cond_system_exception (cfg, code, ins->inst_p1, 6);
2553 ia64_mov_pred (code, 7, ins->dreg, IA64_R0);
2554 ia64_no_stop (code);
2555 ia64_add1_pred (code, 6, ins->dreg, IA64_R0, IA64_R0);
2557 case OP_ICONV_TO_I1:
2558 case OP_LCONV_TO_I1:
2559 /* FIXME: Is this needed ? */
2560 ia64_sxt1 (code, ins->dreg, ins->sreg1);
2562 case OP_ICONV_TO_I2:
2563 case OP_LCONV_TO_I2:
2564 /* FIXME: Is this needed ? */
2565 ia64_sxt2 (code, ins->dreg, ins->sreg1);
2567 case OP_LCONV_TO_I4:
2568 /* FIXME: Is this needed ? */
2569 ia64_sxt4 (code, ins->dreg, ins->sreg1);
2571 case OP_ICONV_TO_U1:
2572 case OP_LCONV_TO_U1:
2573 /* FIXME: Is this needed */
2574 ia64_zxt1 (code, ins->dreg, ins->sreg1);
2576 case OP_ICONV_TO_U2:
2577 case OP_LCONV_TO_U2:
2578 /* FIXME: Is this needed */
2579 ia64_zxt2 (code, ins->dreg, ins->sreg1);
2581 case OP_LCONV_TO_U4:
2582 /* FIXME: Is this needed */
2583 ia64_zxt4 (code, ins->dreg, ins->sreg1);
2585 case OP_ICONV_TO_I8:
2587 case OP_LCONV_TO_I8:
2589 ia64_sxt4 (code, ins->dreg, ins->sreg1);
2591 case OP_LCONV_TO_U8:
2593 ia64_zxt4 (code, ins->dreg, ins->sreg1);
2600 double d = *(double *)ins->inst_p0;
2602 if ((d == 0.0) && (mono_signbit (d) == 0))
2603 ia64_fmov (code, ins->dreg, 0);
2605 ia64_fmov (code, ins->dreg, 1);
2607 add_patch_info (cfg, code, MONO_PATCH_INFO_R8, ins->inst_p0);
2608 ia64_movl (code, GP_SCRATCH_REG, 0);
2609 ia64_ldfd (code, ins->dreg, GP_SCRATCH_REG);
2614 float f = *(float *)ins->inst_p0;
2616 if ((f == 0.0) && (mono_signbit (f) == 0))
2617 ia64_fmov (code, ins->dreg, 0);
2619 ia64_fmov (code, ins->dreg, 1);
2621 add_patch_info (cfg, code, MONO_PATCH_INFO_R4, ins->inst_p0);
2622 ia64_movl (code, GP_SCRATCH_REG, 0);
2623 ia64_ldfs (code, ins->dreg, GP_SCRATCH_REG);
2628 ia64_fmov (code, ins->dreg, ins->sreg1);
2630 case OP_STORER8_MEMBASE_REG:
2631 if (ins->inst_offset != 0) {
2632 /* This is generated by local regalloc */
2633 if (ia64_is_imm14 (ins->inst_offset)) {
2634 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2636 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2637 ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2639 ins->inst_destbasereg = GP_SCRATCH_REG;
2641 ia64_stfd_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2643 case OP_STORER4_MEMBASE_REG:
2644 ia64_fnorm_s_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2645 ia64_stfs_hint (code, ins->inst_destbasereg, FP_SCRATCH_REG, 0);
2647 case OP_LOADR8_MEMBASE:
2648 if (ins->inst_offset != 0) {
2649 /* This is generated by local regalloc */
2650 if (ia64_is_imm14 (ins->inst_offset)) {
2651 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2653 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2654 ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2656 ins->inst_basereg = GP_SCRATCH_REG;
2658 ia64_ldfd (code, ins->dreg, ins->inst_basereg);
2660 case OP_LOADR4_MEMBASE:
2661 ia64_ldfs (code, ins->dreg, ins->inst_basereg);
2662 ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2664 case OP_ICONV_TO_R4:
2665 case OP_LCONV_TO_R4:
2666 ia64_setf_sig (code, ins->dreg, ins->sreg1);
2667 ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2668 ia64_fnorm_s_sf (code, ins->dreg, ins->dreg, 0);
2670 case OP_ICONV_TO_R8:
2671 case OP_LCONV_TO_R8:
2672 ia64_setf_sig (code, ins->dreg, ins->sreg1);
2673 ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2674 ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2676 case OP_FCONV_TO_R4:
2677 ia64_fnorm_s_sf (code, ins->dreg, ins->sreg1, 0);
2679 case OP_FCONV_TO_I8:
2681 ia64_fcvt_fx_trunc_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2682 ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2685 ia64_fma_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2688 ia64_fms_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2691 ia64_fma_d_sf (code, ins->dreg, ins->sreg1, ins->sreg2, 0, 0);
2694 ia64_fmerge_ns (code, ins->dreg, ins->sreg1, ins->sreg1);
2698 ia64_fclass_m (code, 6, 7, ins->sreg1, 0x080);
2699 emit_cond_system_exception (cfg, code, "OverflowException", 6);
2701 ia64_fclass_m (code, 6, 7, ins->sreg1, 0x040);
2702 emit_cond_system_exception (cfg, code, "OverflowException", 6);
2703 /* Positive infinity */
2704 ia64_fclass_m (code, 6, 7, ins->sreg1, 0x021);
2705 emit_cond_system_exception (cfg, code, "OverflowException", 6);
2706 /* Negative infinity */
2707 ia64_fclass_m (code, 6, 7, ins->sreg1, 0x022);
2708 emit_cond_system_exception (cfg, code, "OverflowException", 6);
2713 /* ensure ins->sreg1 is not NULL */
2714 /* Can't use ld8 as this could be a vtype address */
2715 ia64_ld1 (code, GP_SCRATCH_REG, ins->sreg1);
2718 ia64_adds_imm (code, GP_SCRATCH_REG, cfg->sig_cookie, cfg->frame_reg);
2719 ia64_st8 (code, ins->sreg1, GP_SCRATCH_REG);
2727 call = (MonoCallInst*)ins;
2729 if (ins->flags & MONO_INST_HAS_METHOD)
2730 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2732 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2734 code = emit_move_return_value (cfg, ins, code);
2742 case OP_VOIDCALL_REG: {
2743 MonoCallInst *call = (MonoCallInst*)ins;
2748 * mono_arch_get_this_arg_from_call () needs to find the this argument in a global
2751 cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2752 out_reg = cfg->arch.reg_out0;
2753 ia64_mov (code, IA64_R10, out_reg);
2756 ia64_mov (code, IA64_R8, ins->sreg1);
2757 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, IA64_R8, 8);
2758 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2759 ia64_ld8 (code, IA64_GP, IA64_R8);
2760 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2762 code = emit_move_return_value (cfg, ins, code);
2765 case OP_FCALL_MEMBASE:
2766 case OP_LCALL_MEMBASE:
2767 case OP_VCALL_MEMBASE:
2768 case OP_VCALL2_MEMBASE:
2769 case OP_VOIDCALL_MEMBASE:
2770 case OP_CALL_MEMBASE: {
2771 MonoCallInst *call = (MonoCallInst*)ins;
2775 ia64_mov (code, IA64_R11, ins->sreg1);
2776 if (ia64_is_imm14 (ins->inst_offset))
2777 ia64_adds_imm (code, IA64_R8, ins->inst_offset, ins->sreg1);
2779 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2780 ia64_add (code, IA64_R8, GP_SCRATCH_REG, ins->sreg1);
2783 if (call->method && ins->inst_offset < 0) {
2785 * This is a possible IMT call so save the IMT method in a global
2786 * register where mono_arch_find_imt_method () and its friends can
2789 ia64_movl (code, IA64_R9, call->method);
2793 * mono_arch_find_this_arg () needs to find the this argument in a global
2796 cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2797 out_reg = cfg->arch.reg_out0;
2798 ia64_mov (code, IA64_R10, out_reg);
2800 ia64_ld8 (code, GP_SCRATCH_REG, IA64_R8);
2802 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2804 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2806 code = emit_move_return_value (cfg, ins, code);
2811 * Keep in sync with the code in emit_epilog.
2814 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2817 g_assert (!cfg->method->save_lmf);
2819 /* Load arguments into their original registers */
2820 code = emit_load_volatile_arguments (cfg, code);
2822 if (cfg->arch.stack_alloc_size) {
2823 if (cfg->arch.omit_fp) {
2824 if (ia64_is_imm14 (cfg->arch.stack_alloc_size))
2825 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
2827 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
2828 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
2832 ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
2834 ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
2835 ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
2837 add_patch_info (cfg, code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2838 ia64_movl (code, GP_SCRATCH_REG, 0);
2839 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2840 ia64_br_cond_reg (code, IA64_B6);
2845 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, mono_break);
2851 /* FIXME: Sigaltstack support */
2853 /* keep alignment */
2854 ia64_adds_imm (code, GP_SCRATCH_REG, MONO_ARCH_LOCALLOC_ALIGNMENT - 1, ins->sreg1);
2855 ia64_movl (code, GP_SCRATCH_REG2, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
2856 ia64_and (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2858 ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2860 ia64_mov (code, ins->dreg, IA64_SP);
2862 /* An area at sp is reserved by the ABI for parameter passing */
2863 abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_LOCALLOC_ALIGNMENT);
2864 if (ia64_is_adds_imm (abi_offset))
2865 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2867 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2868 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2871 if (ins->flags & MONO_INST_INIT) {
2873 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2875 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2878 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2879 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2880 ia64_br_cond_pred (code, 8, -2);
2882 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2884 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2889 case OP_LOCALLOC_IMM: {
2892 /* FIXME: Sigaltstack support */
2894 gssize size = ins->inst_imm;
2895 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
2897 if (ia64_is_adds_imm (size))
2898 ia64_adds_imm (code, GP_SCRATCH_REG, size, IA64_R0);
2900 ia64_movl (code, GP_SCRATCH_REG, size);
2902 ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2903 ia64_mov (code, ins->dreg, IA64_SP);
2905 /* An area at sp is reserved by the ABI for parameter passing */
2906 abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_FRAME_ALIGNMENT);
2907 if (ia64_is_adds_imm (abi_offset))
2908 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2910 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2911 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2914 if (ins->flags & MONO_INST_INIT) {
2916 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2918 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2921 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2922 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2923 ia64_br_cond_pred (code, 8, -2);
2925 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2927 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2932 /* Synchronization */
2933 case OP_MEMORY_BARRIER:
2936 case OP_ATOMIC_ADD_IMM_I4:
2937 g_assert (ins->inst_offset == 0);
2938 ia64_fetchadd4_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2939 ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2941 case OP_ATOMIC_ADD_IMM_I8:
2942 g_assert (ins->inst_offset == 0);
2943 ia64_fetchadd8_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2944 ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2946 case OP_ATOMIC_EXCHANGE_I4:
2947 ia64_xchg4_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2948 ia64_sxt4 (code, ins->dreg, ins->dreg);
2950 case OP_ATOMIC_EXCHANGE_I8:
2951 ia64_xchg8_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2953 case OP_ATOMIC_ADD_I4: {
2954 guint8 *label, *buf;
2956 /* From libatomic_ops */
2959 ia64_begin_bundle (code);
2960 label = code.buf + code.nins;
2961 ia64_ld4_acq (code, GP_SCRATCH_REG, ins->sreg1);
2962 ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2963 ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2964 ia64_cmpxchg4_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2965 ia64_cmp4_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2966 buf = code.buf + code.nins;
2967 ia64_br_cond_pred (code, 7, 0);
2968 ia64_begin_bundle (code);
2969 ia64_patch (buf, label);
2970 ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2973 case OP_ATOMIC_ADD_I8: {
2974 guint8 *label, *buf;
2976 /* From libatomic_ops */
2979 ia64_begin_bundle (code);
2980 label = code.buf + code.nins;
2981 ia64_ld8_acq (code, GP_SCRATCH_REG, ins->sreg1);
2982 ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2983 ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2984 ia64_cmpxchg8_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2985 ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2986 buf = code.buf + code.nins;
2987 ia64_br_cond_pred (code, 7, 0);
2988 ia64_begin_bundle (code);
2989 ia64_patch (buf, label);
2990 ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2994 /* Exception handling */
2995 case OP_CALL_HANDLER:
2997 * Using a call instruction would mess up the register stack, so
2998 * save the return address to a register and use a
3001 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3002 ia64_mov (code, IA64_R15, IA64_R0);
3003 ia64_mov_from_ip (code, GP_SCRATCH_REG);
3004 /* Add the length of OP_CALL_HANDLER */
3005 ia64_adds_imm (code, GP_SCRATCH_REG, 5 * 16, GP_SCRATCH_REG);
3006 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3007 ia64_movl (code, GP_SCRATCH_REG2, 0);
3008 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
3009 ia64_br_cond_reg (code, IA64_B6);
3011 //mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3012 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3014 case OP_START_HANDLER: {
3016 * We receive the return address in GP_SCRATCH_REG.
3018 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3021 * R15 determines our caller. It is used since it is writable using
3023 * R15 == 0 means we are called by OP_CALL_HANDLER or via resume_context ()
3024 * R15 != 0 means we are called by call_filter ().
3026 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3027 ia64_cmp_eq (code, 6, 7, IA64_R15, IA64_R0);
3029 ia64_br_cond_pred (code, 6, 6);
3032 * Called by call_filter:
3033 * Allocate a new stack frame, and set the fp register from the
3034 * value passed in by the caller.
3035 * We allocate a similar frame as is done by the prolog, so
3036 * if an exception is thrown while executing the filter, the
3037 * unwinder can unwind through the filter frame using the unwind
3038 * info for the prolog.
3040 ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3041 ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3042 ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3043 ia64_mov (code, cfg->frame_reg, IA64_R15);
3044 /* Signal to endfilter that we are called by call_filter */
3045 ia64_mov (code, GP_SCRATCH_REG, IA64_R0);
3047 /* Branch target: */
3048 if (ia64_is_imm14 (spvar->inst_offset))
3049 ia64_adds_imm (code, GP_SCRATCH_REG2, spvar->inst_offset, cfg->frame_reg);
3051 ia64_movl (code, GP_SCRATCH_REG2, spvar->inst_offset);
3052 ia64_add (code, GP_SCRATCH_REG2, cfg->frame_reg, GP_SCRATCH_REG2);
3055 /* Save the return address */
3056 ia64_st8_hint (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 0);
3057 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3062 case OP_ENDFILTER: {
3063 /* FIXME: Return the value in ENDFILTER */
3064 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3066 /* Load the return address */
3067 if (ia64_is_imm14 (spvar->inst_offset)) {
3068 ia64_adds_imm (code, GP_SCRATCH_REG, spvar->inst_offset, cfg->frame_reg);
3070 ia64_movl (code, GP_SCRATCH_REG, spvar->inst_offset);
3071 ia64_add (code, GP_SCRATCH_REG, cfg->frame_reg, GP_SCRATCH_REG);
3073 ia64_ld8_hint (code, GP_SCRATCH_REG, GP_SCRATCH_REG, 0);
3076 ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, IA64_R0);
3077 ia64_br_cond_pred (code, 7, 4);
3079 /* Called by call_filter */
3081 ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
3082 ia64_mov_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
3083 ia64_br_ret_reg (code, IA64_B0);
3085 /* Called by CALL_HANDLER */
3086 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
3087 ia64_br_cond_reg (code, IA64_B6);
3091 ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3092 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3093 (gpointer)"mono_arch_throw_exception");
3096 * This might be the last instruction in the method, so add a dummy
3097 * instruction so the unwinder will work.
3099 ia64_break_i (code, 0);
3102 ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3103 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3104 (gpointer)"mono_arch_rethrow_exception");
3106 ia64_break_i (code, 0);
3108 case OP_GC_SAFE_POINT:
3112 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3113 g_assert_not_reached ();
3116 if ((code.buf - cfg->native_code - offset) > max_len) {
3117 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3118 mono_inst_name (ins->opcode), max_len, code.buf - cfg->native_code - offset);
3119 g_assert_not_reached ();
3125 last_offset = offset;
3128 ia64_codegen_close (code);
3130 cfg->code_len = code.buf - cfg->native_code;
3134 mono_arch_register_lowlevel_calls (void)
3138 static Ia64InsType ins_types_in_template [32][3] = {
3139 {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3140 {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3141 {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3142 {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3143 {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3144 {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3147 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3148 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3149 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3150 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3151 {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3152 {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3153 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3154 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3155 {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3156 {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3157 {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3158 {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3161 {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3162 {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3163 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3164 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3167 {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3168 {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3173 static gboolean stops_in_template [32][3] = {
3174 { FALSE, FALSE, FALSE },
3175 { FALSE, FALSE, TRUE },
3176 { FALSE, TRUE, FALSE },
3177 { FALSE, TRUE, TRUE },
3178 { FALSE, FALSE, FALSE },
3179 { FALSE, FALSE, TRUE },
3180 { FALSE, FALSE, FALSE },
3181 { FALSE, FALSE, FALSE },
3183 { FALSE, FALSE, FALSE },
3184 { FALSE, FALSE, TRUE },
3185 { TRUE, FALSE, FALSE },
3186 { TRUE, FALSE, TRUE },
3187 { FALSE, FALSE, FALSE },
3188 { FALSE, FALSE, TRUE },
3189 { FALSE, FALSE, FALSE },
3190 { FALSE, FALSE, TRUE },
3192 { FALSE, FALSE, FALSE },
3193 { FALSE, FALSE, TRUE },
3194 { FALSE, FALSE, FALSE },
3195 { FALSE, FALSE, TRUE },
3196 { FALSE, FALSE, FALSE },
3197 { FALSE, FALSE, FALSE },
3198 { FALSE, FALSE, FALSE },
3199 { FALSE, FALSE, TRUE },
3201 { FALSE, FALSE, FALSE },
3202 { FALSE, FALSE, TRUE },
3203 { FALSE, FALSE, FALSE },
3204 { FALSE, FALSE, FALSE },
3205 { FALSE, FALSE, FALSE },
3206 { FALSE, FALSE, TRUE },
3207 { FALSE, FALSE, FALSE },
3208 { FALSE, FALSE, FALSE }
3211 static int last_stop_in_template [32] = {
3212 -1, 2, 1, 2, -1, 2, -1, -1,
3213 -1, 2, 0, 2, -1, 2, -1, 2,
3214 -1, 2, -1, 2, -1, -1, -1, 2,
3215 -1, 2, -1, -1, -1, 2, -1, -1
3218 static guint64 nops_for_ins_types [6] = {
3227 #define ITYPE_MATCH(itype1, itype2) (((itype1) == (itype2)) || (((itype2) == IA64_INS_TYPE_A) && (((itype1) == IA64_INS_TYPE_I) || ((itype1) == IA64_INS_TYPE_M))))
3234 #define DEBUG_INS_SCHED(a) do { a; } while (0)
3236 #define DEBUG_INS_SCHED(a)
3240 ia64_analyze_deps (Ia64CodegenState *code, int *deps_start, int *stops)
3242 int i, pos, ins_index, current_deps_start, current_ins_start, reg;
3243 guint8 *deps = code->dep_info;
3244 gboolean need_stop, no_stop;
3246 for (i = 0; i < code->nins; ++i)
3250 current_deps_start = 0;
3251 current_ins_start = 0;
3252 deps_start [ins_index] = current_ins_start;
3255 DEBUG_INS_SCHED (printf ("BEGIN.\n"));
3256 while (pos < code->dep_info_pos) {
3258 switch (deps [pos]) {
3259 case IA64_END_OF_INS:
3261 current_ins_start = pos + 2;
3262 deps_start [ins_index] = current_ins_start;
3264 DEBUG_INS_SCHED (printf ("(%d) END INS.\n", ins_index - 1));
3269 reg = deps [pos + 1];
3271 DEBUG_INS_SCHED (printf ("READ GR: %d\n", reg));
3272 for (i = current_deps_start; i < current_ins_start; i += 2)
3273 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3277 reg = code->dep_info [pos + 1];
3279 DEBUG_INS_SCHED (printf ("WRITE GR: %d\n", reg));
3280 for (i = current_deps_start; i < current_ins_start; i += 2)
3281 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3285 reg = deps [pos + 1];
3287 DEBUG_INS_SCHED (printf ("READ PR: %d\n", reg));
3288 for (i = current_deps_start; i < current_ins_start; i += 2)
3289 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3292 case IA64_READ_PR_BRANCH:
3293 reg = deps [pos + 1];
3295 /* Writes to prs by non-float instructions are visible to branches */
3296 DEBUG_INS_SCHED (printf ("READ PR BRANCH: %d\n", reg));
3297 for (i = current_deps_start; i < current_ins_start; i += 2)
3298 if (deps [i] == IA64_WRITE_PR_FLOAT && deps [i + 1] == reg)
3302 reg = code->dep_info [pos + 1];
3304 DEBUG_INS_SCHED (printf ("WRITE PR: %d\n", reg));
3305 for (i = current_deps_start; i < current_ins_start; i += 2)
3306 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3309 case IA64_WRITE_PR_FLOAT:
3310 reg = code->dep_info [pos + 1];
3312 DEBUG_INS_SCHED (printf ("WRITE PR FP: %d\n", reg));
3313 for (i = current_deps_start; i < current_ins_start; i += 2)
3314 if (((deps [i] == IA64_WRITE_GR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3318 reg = deps [pos + 1];
3320 DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3321 for (i = current_deps_start; i < current_ins_start; i += 2)
3322 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3326 reg = code->dep_info [pos + 1];
3328 DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3329 for (i = current_deps_start; i < current_ins_start; i += 2)
3330 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3333 case IA64_READ_BR_BRANCH:
3334 reg = deps [pos + 1];
3336 /* Writes to brs are visible to branches */
3337 DEBUG_INS_SCHED (printf ("READ BR BRACH: %d\n", reg));
3340 reg = deps [pos + 1];
3342 DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3343 for (i = current_deps_start; i < current_ins_start; i += 2)
3344 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3348 reg = code->dep_info [pos + 1];
3350 DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3351 for (i = current_deps_start; i < current_ins_start; i += 2)
3352 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3356 reg = deps [pos + 1];
3358 DEBUG_INS_SCHED (printf ("READ AR: %d\n", reg));
3359 for (i = current_deps_start; i < current_ins_start; i += 2)
3360 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3364 reg = code->dep_info [pos + 1];
3366 DEBUG_INS_SCHED (printf ("WRITE AR: %d\n", reg));
3367 for (i = current_deps_start; i < current_ins_start; i += 2)
3368 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3373 * Explicitly indicate that a stop is not required. Useful for
3374 * example when two predicated instructions with negated predicates
3375 * write the same registers.
3380 g_assert_not_reached ();
3384 if (need_stop && !no_stop) {
3385 g_assert (ins_index > 0);
3386 stops [ins_index - 1] = 1;
3388 DEBUG_INS_SCHED (printf ("STOP\n"));
3389 current_deps_start = current_ins_start;
3391 /* Skip remaining deps for this instruction */
3392 while (deps [pos] != IA64_END_OF_INS)
3397 if (code->nins > 0) {
3398 /* No dependency info for the last instruction */
3399 stops [code->nins - 1] = 1;
3402 deps_start [code->nins] = code->dep_info_pos;
3406 ia64_real_emit_bundle (Ia64CodegenState *code, int *deps_start, int *stops, int n, guint64 template, guint64 ins1, guint64 ins2, guint64 ins3, guint8 nops)
3408 int stop_pos, i, deps_to_shift, dep_shift;
3410 g_assert (n <= code->nins);
3412 // if (n > 1) printf ("FOUND: %ld.\n", template);
3414 ia64_emit_bundle_template (code, template, ins1, ins2, ins3);
3416 stop_pos = last_stop_in_template [template] + 1;
3420 /* Compute the number of 'real' instructions before the stop */
3421 deps_to_shift = stop_pos;
3422 if (stop_pos >= 3 && (nops & (1 << 2)))
3424 if (stop_pos >= 2 && (nops & (1 << 1)))
3426 if (stop_pos >= 1 && (nops & (1 << 0)))
3430 * We have to keep some dependencies whose instructions have been shifted
3431 * out of the buffer. So nullify the end_of_ins markers in the dependency
3434 for (i = deps_start [deps_to_shift]; i < deps_start [n]; i += 2)
3435 if (code->dep_info [i] == IA64_END_OF_INS)
3436 code->dep_info [i] = IA64_NONE;
3438 g_assert (deps_start [deps_to_shift] <= code->dep_info_pos);
3439 memcpy (code->dep_info, &code->dep_info [deps_start [deps_to_shift]], code->dep_info_pos - deps_start [deps_to_shift]);
3440 code->dep_info_pos = code->dep_info_pos - deps_start [deps_to_shift];
3442 dep_shift = deps_start [deps_to_shift];
3443 for (i = 0; i < code->nins + 1 - n; ++i)
3444 deps_start [i] = deps_start [n + i] - dep_shift;
3446 /* Determine the exact positions of instructions with unwind ops */
3447 if (code->unw_op_count) {
3449 int curr_ins, curr_ins_pos;
3452 curr_ins_pos = ((code->buf - code->region_start - 16) / 16) * 3;
3453 for (i = 0; i < 3; ++i) {
3454 if (! (nops & (1 << i))) {
3455 ins_pos [curr_ins] = curr_ins_pos + i;
3460 for (i = code->unw_op_pos; i < code->unw_op_count; ++i) {
3461 if (code->unw_ops_pos [i] < n) {
3462 code->unw_ops [i].when = ins_pos [code->unw_ops_pos [i]];
3463 //printf ("UNW-OP: %d -> %d\n", code->unw_ops_pos [i], code->unw_ops [i].when);
3466 if (code->unw_op_pos < code->unw_op_count)
3467 code->unw_op_pos += n;
3470 if (n == code->nins) {
3475 memcpy (&code->instructions [0], &code->instructions [n], (code->nins - n) * sizeof (guint64));
3476 memcpy (&code->itypes [0], &code->itypes [n], (code->nins - n) * sizeof (int));
3477 memcpy (&stops [0], &stops [n], (code->nins - n) * sizeof (int));
3483 ia64_emit_bundle (Ia64CodegenState *code, gboolean flush)
3485 int i, ins_type, template, nins_to_emit;
3486 int deps_start [16];
3491 * We implement a simple scheduler which tries to put three instructions
3492 * per bundle, then two, then one.
3494 ia64_analyze_deps (code, deps_start, stops);
3496 if ((code->nins >= 3) && !code->one_ins_per_bundle) {
3497 /* Find a suitable template */
3498 for (template = 0; template < 32; ++template) {
3499 if (stops_in_template [template][0] != stops [0] ||
3500 stops_in_template [template][1] != stops [1] ||
3501 stops_in_template [template][2] != stops [2])
3505 for (i = 0; i < 3; ++i) {
3506 ins_type = ins_types_in_template [template][i];
3507 switch (code->itypes [i]) {
3508 case IA64_INS_TYPE_A:
3509 found &= (ins_type == IA64_INS_TYPE_I) || (ins_type == IA64_INS_TYPE_M);
3512 found &= (ins_type == code->itypes [i]);
3518 found = debug_ins_sched ();
3521 ia64_real_emit_bundle (code, deps_start, stops, 3, template, code->instructions [0], code->instructions [1], code->instructions [2], 0);
3527 if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3528 /* Wait for more instructions */
3531 /* If it didn't work out, try putting two instructions into one bundle */
3532 if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3533 /* Try a nop at the end */
3534 for (template = 0; template < 32; ++template) {
3535 if (stops_in_template [template][0] != stops [0] ||
3536 ((stops_in_template [template][1] != stops [1]) &&
3537 (stops_in_template [template][2] != stops [1])))
3541 if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3542 !ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [1]))
3545 if (!debug_ins_sched ())
3548 ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], code->instructions [1], nops_for_ins_types [ins_types_in_template [template][2]], 1 << 2);
3553 if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3554 /* Wait for more instructions */
3557 if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3558 /* Try a nop in the middle */
3559 for (template = 0; template < 32; ++template) {
3560 if (((stops_in_template [template][0] != stops [0]) &&
3561 (stops_in_template [template][1] != stops [0])) ||
3562 stops_in_template [template][2] != stops [1])
3565 if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3566 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3569 if (!debug_ins_sched ())
3572 ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], nops_for_ins_types [ins_types_in_template [template][1]], code->instructions [1], 1 << 1);
3577 if ((code->nins >= 2) && flush && !code->one_ins_per_bundle) {
3578 /* Try a nop at the beginning */
3579 for (template = 0; template < 32; ++template) {
3580 if ((stops_in_template [template][1] != stops [0]) ||
3581 (stops_in_template [template][2] != stops [1]))
3584 if (!ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [0]) ||
3585 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3588 if (!debug_ins_sched ())
3591 ia64_real_emit_bundle (code, deps_start, stops, 2, template, nops_for_ins_types [ins_types_in_template [template][0]], code->instructions [0], code->instructions [1], 1 << 0);
3596 if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3597 /* Wait for more instructions */
3601 nins_to_emit = code->nins;
3605 while (nins_to_emit > 0) {
3606 if (!debug_ins_sched ())
3608 switch (code->itypes [0]) {
3609 case IA64_INS_TYPE_A:
3611 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3613 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3615 case IA64_INS_TYPE_I:
3617 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3619 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3621 case IA64_INS_TYPE_M:
3623 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3625 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3627 case IA64_INS_TYPE_B:
3629 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIBS, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3631 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIB, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3633 case IA64_INS_TYPE_F:
3635 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3637 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFI, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3639 case IA64_INS_TYPE_LX:
3640 if (stops [0] || stops [1])
3641 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLXS, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3643 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLX, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3647 g_assert_not_reached ();
3653 unw_dyn_region_info_t*
3654 mono_ia64_create_unwind_region (Ia64CodegenState *code)
3656 unw_dyn_region_info_t *r;
3658 g_assert (code->nins == 0);
3659 r = g_malloc0 (_U_dyn_region_info_size (code->unw_op_count));
3660 memcpy (&r->op, &code->unw_ops, sizeof (unw_dyn_op_t) * code->unw_op_count);
3661 r->op_count = code->unw_op_count;
3662 r->insn_count = ((code->buf - code->region_start) >> 4) * 3;
3663 code->unw_op_count = 0;
3664 code->unw_op_pos = 0;
3665 code->region_start = code->buf;
3671 ia64_patch (unsigned char* code, gpointer target)
3674 guint64 instructions [3];
3675 guint8 gen_buf [16];
3676 Ia64CodegenState gen;
3681 * code encodes both the position inside the buffer and code.nins when
3682 * the instruction was emitted.
3684 ins_to_skip = (guint64)code % 16;
3685 code = (unsigned char*)((guint64)code & ~15);
3688 * Search for the first instruction which is 'patchable', skipping
3689 * ins_to_skip instructions.
3694 template = ia64_bundle_template (code);
3695 instructions [0] = ia64_bundle_ins1 (code);
3696 instructions [1] = ia64_bundle_ins2 (code);
3697 instructions [2] = ia64_bundle_ins3 (code);
3699 ia64_codegen_init (gen, gen_buf);
3702 for (i = 0; i < 3; ++i) {
3703 guint64 ins = instructions [i];
3704 int opcode = ia64_ins_opcode (ins);
3706 if (ins == nops_for_ins_types [ins_types_in_template [template][i]])
3714 switch (ins_types_in_template [template][i]) {
3715 case IA64_INS_TYPE_A:
3716 case IA64_INS_TYPE_M:
3717 if ((opcode == 8) && (ia64_ins_x2a (ins) == 2) && (ia64_ins_ve (ins) == 0)) {
3719 ia64_adds_imm_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), (guint64)target, ia64_ins_r3 (ins));
3720 instructions [i] = gen.instructions [0];
3726 case IA64_INS_TYPE_B:
3727 if ((opcode == 4) && (ia64_ins_btype (ins) == 0)) {
3729 gint64 disp = ((guint8*)target - code) >> 4;
3732 ia64_br_cond_hint_pred (gen, ia64_ins_qp (ins), disp, 0, 0, 0);
3734 instructions [i] = gen.instructions [0];
3737 else if (opcode == 5) {
3739 gint64 disp = ((guint8*)target - code) >> 4;
3742 ia64_br_call_hint_pred (gen, ia64_ins_qp (ins), ia64_ins_b1 (ins), disp, 0, 0, 0);
3743 instructions [i] = gen.instructions [0];
3749 case IA64_INS_TYPE_LX:
3753 if ((opcode == 6) && (ia64_ins_vc (ins) == 0)) {
3755 ia64_movl_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), target);
3756 instructions [1] = gen.instructions [0];
3757 instructions [2] = gen.instructions [1];
3770 ia64_codegen_init (gen, code);
3771 ia64_emit_bundle_template (&gen, template, instructions [0], instructions [1], instructions [2]);
3781 mono_arch_patch_code (MonoCompile *cfg, MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors, MonoError *error)
3783 MonoJumpInfo *patch_info;
3787 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3788 unsigned char *ip = patch_info->ip.i + code;
3789 const unsigned char *target;
3791 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors, error);
3792 return_if_nok (error);
3794 if (patch_info->type == MONO_PATCH_INFO_NONE)
3796 if (mono_compile_aot) {
3800 ia64_patch (ip, (gpointer)target);
3805 mono_arch_emit_prolog (MonoCompile *cfg)
3807 MonoMethod *method = cfg->method;
3808 MonoMethodSignature *sig;
3810 int alloc_size, pos, i;
3811 Ia64CodegenState code;
3814 sig = mono_method_signature (method);
3817 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
3819 cfg->code_size = MAX (cfg->header->code_size * 4, 512);
3821 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3822 cfg->code_size += 1024;
3823 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3824 cfg->code_size += 1024;
3826 cfg->native_code = g_malloc (cfg->code_size);
3828 ia64_codegen_init (code, cfg->native_code);
3830 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
3831 if (cfg->param_area)
3832 alloc_size += cfg->param_area;
3836 alloc_size = ALIGN_TO (alloc_size, MONO_ARCH_FRAME_ALIGNMENT);
3838 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
3839 /* Force sp to be saved/restored */
3840 alloc_size += MONO_ARCH_FRAME_ALIGNMENT;
3842 cfg->arch.stack_alloc_size = alloc_size;
3846 if (method->save_lmf) {
3847 /* No LMF on IA64 */
3852 ia64_unw_save_reg (code, UNW_IA64_AR_PFS, UNW_IA64_GR + cfg->arch.reg_saved_ar_pfs);
3853 ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3854 ia64_unw_save_reg (code, UNW_IA64_RP, UNW_IA64_GR + cfg->arch.reg_saved_b0);
3855 ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3857 if ((alloc_size || cinfo->stack_usage) && !cfg->arch.omit_fp) {
3858 ia64_unw_save_reg (code, UNW_IA64_SP, UNW_IA64_GR + cfg->arch.reg_saved_sp);
3859 ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3860 if (cfg->frame_reg != cfg->arch.reg_saved_sp)
3861 ia64_mov (code, cfg->frame_reg, IA64_SP);
3865 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3866 int pagesize = getpagesize ();
3868 if (alloc_size >= pagesize) {
3869 gint32 remaining_size = alloc_size;
3871 /* Generate stack touching code */
3872 ia64_mov (code, GP_SCRATCH_REG, IA64_SP);
3873 while (remaining_size >= pagesize) {
3874 ia64_movl (code, GP_SCRATCH_REG2, pagesize);
3875 ia64_sub (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3876 ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
3877 remaining_size -= pagesize;
3881 if (ia64_is_imm14 (-alloc_size)) {
3882 if (cfg->arch.omit_fp)
3883 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3884 ia64_adds_imm (code, IA64_SP, (-alloc_size), IA64_SP);
3887 ia64_movl (code, GP_SCRATCH_REG, -alloc_size);
3888 if (cfg->arch.omit_fp)
3889 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3890 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
3894 ia64_begin_bundle (code);
3896 /* Initialize unwind info */
3897 cfg->arch.r_pro = mono_ia64_create_unwind_region (&code);
3899 if (sig->ret->type != MONO_TYPE_VOID) {
3900 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
3901 /* Save volatile arguments to the stack */
3906 /* Keep this in sync with emit_load_volatile_arguments */
3907 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3908 ArgInfo *ainfo = cinfo->args + i;
3909 gint32 stack_offset;
3912 inst = cfg->args [i];
3914 if (sig->hasthis && (i == 0))
3915 arg_type = &mono_defaults.object_class->byval_arg;
3917 arg_type = sig->params [i - sig->hasthis];
3919 arg_type = mini_get_underlying_type (arg_type);
3921 stack_offset = ainfo->offset + ARGS_OFFSET;
3924 * FIXME: Native code might pass non register sized integers
3925 * without initializing the upper bits.
3927 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED && !arg_type->byref && ainfo->storage == ArgInIReg) {
3928 int reg = cfg->arch.reg_in0 + ainfo->reg;
3930 switch (mono_type_to_load_membase (cfg, arg_type)) {
3931 case OP_LOADI1_MEMBASE:
3932 ia64_sxt1 (code, reg, reg);
3934 case OP_LOADU1_MEMBASE:
3935 ia64_zxt1 (code, reg, reg);
3937 case OP_LOADI2_MEMBASE:
3938 ia64_sxt2 (code, reg, reg);
3940 case OP_LOADU2_MEMBASE:
3941 ia64_zxt2 (code, reg, reg);
3948 /* Save volatile arguments to the stack */
3949 if (inst->opcode != OP_REGVAR) {
3950 switch (ainfo->storage) {
3953 case ArgInFloatRegR4:
3954 g_assert (inst->opcode == OP_REGOFFSET);
3955 if (ia64_is_adds_imm (inst->inst_offset))
3956 ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3958 ia64_movl (code, GP_SCRATCH_REG2, inst->inst_offset);
3959 ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3961 if (arg_type->byref)
3962 ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3964 switch (arg_type->type) {
3966 ia64_stfs_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3969 ia64_stfd_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3972 ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3980 if (ainfo->nslots != ainfo->nregs)
3983 g_assert (inst->opcode == OP_REGOFFSET);
3984 ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3985 for (i = 0; i < ainfo->nregs; ++i) {
3986 switch (ainfo->atype) {
3987 case AggregateNormal:
3988 ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg + i, sizeof (gpointer), 0);
3990 case AggregateSingleHFA:
3991 ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, 4, 0);
3993 case AggregateDoubleHFA:
3994 ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, sizeof (gpointer), 0);
4002 g_assert_not_reached ();
4006 if (inst->opcode == OP_REGVAR) {
4007 /* Argument allocated to (non-volatile) register */
4008 switch (ainfo->storage) {
4010 if (inst->dreg != cfg->arch.reg_in0 + ainfo->reg)
4011 ia64_mov (code, inst->dreg, cfg->arch.reg_in0 + ainfo->reg);
4014 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
4015 ia64_ld8 (code, inst->dreg, GP_SCRATCH_REG);
4023 if (method->save_lmf) {
4024 /* No LMF on IA64 */
4027 ia64_codegen_close (code);
4029 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4030 code.buf = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code.buf, TRUE);
4032 cfg->code_len = code.buf - cfg->native_code;
4034 g_assert (cfg->code_len < cfg->code_size);
4036 cfg->arch.prolog_end_offset = cfg->code_len;
4042 mono_arch_emit_epilog (MonoCompile *cfg)
4044 MonoMethod *method = cfg->method;
4046 int max_epilog_size = 16 * 4;
4047 Ia64CodegenState code;
4052 if (mono_jit_trace_calls != NULL)
4053 max_epilog_size += 1024;
4055 cfg->arch.epilog_begin_offset = cfg->code_len;
4057 while (cfg->code_len + max_epilog_size > cfg->code_size) {
4058 cfg->code_size *= 2;
4059 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4060 cfg->stat_code_reallocs++;
4063 /* FIXME: Emit unwind info */
4065 buf = cfg->native_code + cfg->code_len;
4067 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4068 buf = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, buf, TRUE);
4070 ia64_codegen_init (code, buf);
4072 /* the code restoring the registers must be kept in sync with OP_JMP */
4075 if (method->save_lmf) {
4076 /* No LMF on IA64 */
4079 /* Load returned vtypes into registers if needed */
4080 cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
4081 ainfo = &cinfo->ret;
4082 switch (ainfo->storage) {
4084 if (ainfo->nslots != ainfo->nregs)
4087 g_assert (cfg->ret->opcode == OP_REGOFFSET);
4088 ia64_adds_imm (code, GP_SCRATCH_REG, cfg->ret->inst_offset, cfg->ret->inst_basereg);
4089 for (i = 0; i < ainfo->nregs; ++i) {
4090 switch (ainfo->atype) {
4091 case AggregateNormal:
4092 ia64_ld8_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4094 case AggregateSingleHFA:
4095 ia64_ldfs_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, 4, 0);
4097 case AggregateDoubleHFA:
4098 ia64_ldfd_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4101 g_assert_not_reached ();
4109 ia64_begin_bundle (code);
4111 code.region_start = cfg->native_code;
4113 /* Label the unwind state at the start of the exception throwing region */
4114 //ia64_unw_label_state (code, 1234);
4116 if (cfg->arch.stack_alloc_size) {
4117 if (cfg->arch.omit_fp) {
4118 if (ia64_is_imm14 (cfg->arch.stack_alloc_size)) {
4119 ia64_unw_pop_frames (code, 1);
4120 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
4122 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
4123 ia64_unw_pop_frames (code, 1);
4124 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
4128 ia64_unw_pop_frames (code, 1);
4129 ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
4132 ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
4133 ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
4134 ia64_br_ret_reg (code, IA64_B0);
4136 ia64_codegen_close (code);
4138 cfg->arch.r_epilog = mono_ia64_create_unwind_region (&code);
4139 cfg->arch.r_pro->next = cfg->arch.r_epilog;
4141 cfg->code_len = code.buf - cfg->native_code;
4143 g_assert (cfg->code_len < cfg->code_size);
4147 mono_arch_emit_exceptions (MonoCompile *cfg)
4149 MonoJumpInfo *patch_info;
4151 Ia64CodegenState code;
4152 gboolean empty = TRUE;
4153 //unw_dyn_region_info_t *r_exceptions;
4154 MonoClass *exc_classes [16];
4155 guint8 *exc_throw_start [16], *exc_throw_end [16];
4156 guint32 code_size = 0;
4158 /* Compute needed space */
4159 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4160 if (patch_info->type == MONO_PATCH_INFO_EXC)
4162 if (patch_info->type == MONO_PATCH_INFO_R8)
4163 code_size += 8 + 7; /* sizeof (double) + alignment */
4164 if (patch_info->type == MONO_PATCH_INFO_R4)
4165 code_size += 4 + 7; /* sizeof (float) + alignment */
4171 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4172 cfg->code_size *= 2;
4173 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4174 cfg->stat_code_reallocs++;
4177 ia64_codegen_init (code, cfg->native_code + cfg->code_len);
4179 /* The unwind state here is the same as before the epilog */
4180 //ia64_unw_copy_state (code, 1234);
4182 /* add code to raise exceptions */
4183 /* FIXME: Optimize this */
4185 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4186 switch (patch_info->type) {
4187 case MONO_PATCH_INFO_EXC: {
4188 MonoClass *exc_class;
4191 guint64 exc_token_index;
4193 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4194 exc_token_index = mono_metadata_token_index (exc_class->type_token);
4195 throw_ip = cfg->native_code + patch_info->ip.i;
4197 ia64_begin_bundle (code);
4199 ia64_patch (cfg->native_code + patch_info->ip.i, code.buf);
4201 /* Find a throw sequence for the same exception class */
4202 for (i = 0; i < nthrows; ++i)
4203 if (exc_classes [i] == exc_class)
4207 gint64 offset = exc_throw_end [i] - 16 - throw_ip;
4209 if (ia64_is_adds_imm (offset))
4210 ia64_adds_imm (code, cfg->arch.reg_out0 + 1, offset, IA64_R0);
4212 ia64_movl (code, cfg->arch.reg_out0 + 1, offset);
4214 buf = code.buf + code.nins;
4215 ia64_br_cond_pred (code, 0, 0);
4216 ia64_begin_bundle (code);
4217 ia64_patch (buf, exc_throw_start [i]);
4219 patch_info->type = MONO_PATCH_INFO_NONE;
4224 ia64_movl (code, cfg->arch.reg_out0 + 1, 0);
4226 ia64_begin_bundle (code);
4229 exc_classes [nthrows] = exc_class;
4230 exc_throw_start [nthrows] = code.buf;
4234 if (ia64_is_adds_imm (exc_token_index))
4235 ia64_adds_imm (code, cfg->arch.reg_out0 + 0, exc_token_index, IA64_R0);
4237 ia64_movl (code, cfg->arch.reg_out0 + 0, exc_token_index);
4239 patch_info->data.name = "mono_arch_throw_corlib_exception";
4240 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4241 patch_info->ip.i = code.buf + code.nins - cfg->native_code;
4244 ia64_movl (code, GP_SCRATCH_REG, 0);
4245 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
4246 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
4247 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
4249 ia64_br_call_reg (code, IA64_B0, IA64_B6);
4251 /* Patch up the throw offset */
4252 ia64_begin_bundle (code);
4254 ia64_patch (buf, (gpointer)(code.buf - 16 - throw_ip));
4257 exc_throw_end [nthrows] = code.buf;
4271 /* The unwinder needs this to work */
4272 ia64_break_i (code, 0);
4274 ia64_codegen_close (code);
4277 //r_exceptions = mono_ia64_create_unwind_region (&code);
4278 //cfg->arch.r_epilog = r_exceptions;
4280 cfg->code_len = code.buf - cfg->native_code;
4282 g_assert (cfg->code_len < cfg->code_size);
4286 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4288 Ia64CodegenState code;
4289 CallInfo *cinfo = NULL;
4290 MonoMethodSignature *sig;
4292 int i, n, stack_area = 0;
4294 ia64_codegen_init (code, p);
4296 /* Keep this in sync with mono_arch_get_argument_info */
4298 if (enable_arguments) {
4299 /* Allocate a new area on the stack and save arguments there */
4300 sig = mono_method_signature (cfg->method);
4302 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4304 n = sig->param_count + sig->hasthis;
4306 stack_area = ALIGN_TO (n * 8, 16);
4309 ia64_movl (code, GP_SCRATCH_REG, stack_area);
4311 ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4313 /* FIXME: Allocate out registers */
4315 ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_SP);
4317 /* Required by the ABI */
4318 ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4320 add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4321 ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4323 /* Save arguments to the stack */
4324 for (i = 0; i < n; ++i) {
4325 ins = cfg->args [i];
4327 if (ins->opcode == OP_REGVAR) {
4328 ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4329 ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4330 ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
4333 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
4334 ia64_add (code, GP_SCRATCH_REG, ins->inst_basereg, GP_SCRATCH_REG);
4335 ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
4336 ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4337 ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4338 ia64_st8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG2);
4343 ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4346 ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4348 add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4349 ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4351 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4353 if (enable_arguments && stack_area) {
4354 ia64_movl (code, GP_SCRATCH_REG, stack_area);
4356 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4358 ia64_adds_imm (code, IA64_SP, 16, IA64_SP);
4361 ia64_codegen_close (code);
4367 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
4369 Ia64CodegenState code;
4370 CallInfo *cinfo = NULL;
4371 MonoMethod *method = cfg->method;
4372 MonoMethodSignature *sig = mono_method_signature (cfg->method);
4374 ia64_codegen_init (code, p);
4376 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4378 /* Save return value + pass it to func */
4379 switch (cinfo->ret.storage) {
4383 ia64_mov (code, cfg->arch.reg_saved_return_val, cinfo->ret.reg);
4384 ia64_mov (code, cfg->arch.reg_out0 + 1, cinfo->ret.reg);
4387 ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4388 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4389 ia64_stfd_hint (code, GP_SCRATCH_REG, cinfo->ret.reg, 0);
4390 ia64_fmov (code, 8 + 1, cinfo->ret.reg);
4392 case ArgValuetypeAddrInIReg:
4393 ia64_mov (code, cfg->arch.reg_out0 + 1, cfg->arch.reg_in0 + cinfo->ret.reg);
4402 add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, method);
4403 ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4404 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4406 /* Restore return value */
4407 switch (cinfo->ret.storage) {
4411 ia64_mov (code, cinfo->ret.reg, cfg->arch.reg_saved_return_val);
4414 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4415 ia64_ldfd (code, cinfo->ret.reg, GP_SCRATCH_REG);
4417 case ArgValuetypeAddrInIReg:
4425 ia64_codegen_close (code);
4431 mono_arch_save_unwind_info (MonoCompile *cfg)
4435 /* FIXME: Unregister this for dynamic methods */
4437 di = g_malloc0 (sizeof (unw_dyn_info_t));
4438 di->start_ip = (unw_word_t) cfg->native_code;
4439 di->end_ip = (unw_word_t) cfg->native_code + cfg->code_len;
4441 di->format = UNW_INFO_FORMAT_DYNAMIC;
4442 di->u.pi.name_ptr = (unw_word_t)mono_method_full_name (cfg->method, TRUE);
4443 di->u.pi.regions = cfg->arch.r_pro;
4445 _U_dyn_register (di);
4449 unw_dyn_region_info_t *region = di->u.pi.regions;
4451 printf ("Unwind info for method %s:\n", mono_method_full_name (cfg->method, TRUE));
4453 printf (" [Region: %d]\n", region->insn_count);
4454 region = region->next;
4461 mono_arch_flush_icache (guint8 *code, gint size)
4463 guint8* p = (guint8*)((guint64)code & ~(0x3f));
4464 guint8* end = (guint8*)((guint64)code + size);
4466 #ifdef __INTEL_COMPILER
4467 /* icc doesn't define an fc.i instrinsic, but fc==fc.i on itanium 2 */
4474 __asm__ __volatile__ ("fc.i %0"::"r"(p));
4475 /* FIXME: This could be increased to 128 on some cpus */
4482 mono_arch_flush_register_windows (void)
4484 /* Not needed because of libunwind */
4488 mono_arch_is_inst_imm (gint64 imm)
4490 /* The lowering pass will take care of it */
4496 * Determine whenever the trap whose info is in SIGINFO is caused by
4500 mono_arch_is_int_overflow (void *sigctx, void *info)
4502 /* Division is emulated with explicit overflow checks */
4507 mono_arch_get_patch_offset (guint8 *code)
4515 mono_arch_get_delegate_method_ptr_addr (guint8* code, mgreg_t *regs)
4523 mono_arch_finish_init (void)
4528 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4533 * LOCKING: called with the domain lock held
4536 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
4537 gpointer fail_tramp)
4541 guint8 *start, *buf;
4542 Ia64CodegenState code;
4545 buf = g_malloc0 (size);
4546 ia64_codegen_init (code, buf);
4548 /* IA64_R9 contains the IMT method */
4550 for (i = 0; i < count; ++i) {
4551 MonoIMTCheckItem *item = imt_entries [i];
4552 ia64_begin_bundle (code);
4553 item->code_target = (guint8*)code.buf + code.nins;
4554 if (item->is_equals) {
4555 gboolean fail_case = !item->check_target_idx && fail_tramp;
4557 if (item->check_target_idx || fail_case) {
4558 if (!item->compare_done || fail_case) {
4559 ia64_movl (code, GP_SCRATCH_REG, item->key);
4560 ia64_cmp_eq (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4562 item->jmp_code = (guint8*)code.buf + code.nins;
4563 ia64_br_cond_pred (code, 7, 0);
4565 if (item->has_target_code) {
4566 ia64_movl (code, GP_SCRATCH_REG, item->value.target_code);
4568 ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4569 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4571 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4572 ia64_br_cond_reg (code, IA64_B6);
4575 ia64_begin_bundle (code);
4576 ia64_patch (item->jmp_code, (guint8*)code.buf + code.nins);
4577 ia64_movl (code, GP_SCRATCH_REG, fail_tramp);
4578 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4579 ia64_br_cond_reg (code, IA64_B6);
4580 item->jmp_code = NULL;
4583 /* enable the commented code to assert on wrong method */
4584 #if ENABLE_WRONG_METHOD_CHECK
4585 g_assert_not_reached ();
4587 ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4588 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4589 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4590 ia64_br_cond_reg (code, IA64_B6);
4591 #if ENABLE_WRONG_METHOD_CHECK
4592 g_assert_not_reached ();
4596 ia64_movl (code, GP_SCRATCH_REG, item->key);
4597 ia64_cmp_geu (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4598 item->jmp_code = (guint8*)code.buf + code.nins;
4599 ia64_br_cond_pred (code, 6, 0);
4602 /* patch the branches to get to the target items */
4603 for (i = 0; i < count; ++i) {
4604 MonoIMTCheckItem *item = imt_entries [i];
4605 if (item->jmp_code) {
4606 if (item->check_target_idx) {
4607 ia64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
4612 ia64_codegen_close (code);
4613 g_assert (code.buf - buf <= size);
4615 size = code.buf - buf;
4617 start = mono_method_alloc_generic_virtual_trampoline (domain, size + 16);
4618 start = (gpointer)ALIGN_TO (start, 16);
4620 start = mono_domain_code_reserve (domain, size);
4622 memcpy (start, buf, size);
4624 mono_arch_flush_icache (start, size);
4626 mono_stats.imt_thunks_size += size;
4628 mono_tramp_info_register (mono_tramp_info_create (NULL, start, size, NULL, NULL), domain);
4634 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
4636 return (MonoMethod*)regs [IA64_R9];
4640 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
4642 return (gpointer)regs [IA64_R10];
4646 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
4652 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
4658 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4660 MonoInst *ins = NULL;
4662 if (cmethod->klass->image == mono_defaults.corlib &&
4663 (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
4664 (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
4667 * We don't use the generic version in mini_emit_inst_for_method () since we
4668 * ia64 has atomic_add_imm opcodes.
4670 if (strcmp (cmethod->name, "Increment") == 0) {
4673 if (fsig->params [0]->type == MONO_TYPE_I4)
4674 opcode = OP_ATOMIC_ADD_IMM_I4;
4675 else if (fsig->params [0]->type == MONO_TYPE_I8)
4676 opcode = OP_ATOMIC_ADD_IMM_I8;
4678 g_assert_not_reached ();
4679 MONO_INST_NEW (cfg, ins, opcode);
4680 ins->dreg = mono_alloc_preg (cfg);
4682 ins->inst_basereg = args [0]->dreg;
4683 ins->inst_offset = 0;
4684 MONO_ADD_INS (cfg->cbb, ins);
4685 } else if (strcmp (cmethod->name, "Decrement") == 0) {
4688 if (fsig->params [0]->type == MONO_TYPE_I4)
4689 opcode = OP_ATOMIC_ADD_IMM_I4;
4690 else if (fsig->params [0]->type == MONO_TYPE_I8)
4691 opcode = OP_ATOMIC_ADD_IMM_I8;
4693 g_assert_not_reached ();
4694 MONO_INST_NEW (cfg, ins, opcode);
4695 ins->dreg = mono_alloc_preg (cfg);
4697 ins->inst_basereg = args [0]->dreg;
4698 ins->inst_offset = 0;
4699 MONO_ADD_INS (cfg->cbb, ins);
4700 } else if (strcmp (cmethod->name, "Add") == 0) {
4702 gboolean is_imm = FALSE;
4705 if ((args [1]->opcode == OP_ICONST) || (args [1]->opcode == OP_I8CONST)) {
4706 imm = (args [1]->opcode == OP_ICONST) ? args [1]->inst_c0 : args [1]->inst_l;
4708 is_imm = (imm == 1 || imm == 4 || imm == 8 || imm == 16 || imm == -1 || imm == -4 || imm == -8 || imm == -16);
4712 if (fsig->params [0]->type == MONO_TYPE_I4)
4713 opcode = OP_ATOMIC_ADD_IMM_I4;
4714 else if (fsig->params [0]->type == MONO_TYPE_I8)
4715 opcode = OP_ATOMIC_ADD_IMM_I8;
4717 g_assert_not_reached ();
4719 MONO_INST_NEW (cfg, ins, opcode);
4720 ins->dreg = mono_alloc_ireg (cfg);
4721 ins->inst_basereg = args [0]->dreg;
4722 ins->inst_offset = 0;
4723 ins->inst_imm = imm;
4724 ins->type = (opcode == OP_ATOMIC_ADD_IMM_I4) ? STACK_I4 : STACK_I8;
4726 if (fsig->params [0]->type == MONO_TYPE_I4)
4727 opcode = OP_ATOMIC_ADD_I4;
4728 else if (fsig->params [0]->type == MONO_TYPE_I8)
4729 opcode = OP_ATOMIC_ADD_I8;
4731 g_assert_not_reached ();
4733 MONO_INST_NEW (cfg, ins, opcode);
4734 ins->dreg = mono_alloc_ireg (cfg);
4735 ins->inst_basereg = args [0]->dreg;
4736 ins->inst_offset = 0;
4737 ins->sreg2 = args [1]->dreg;
4738 ins->type = (opcode == OP_ATOMIC_ADD_I4) ? STACK_I4 : STACK_I8;
4740 MONO_ADD_INS (cfg->cbb, ins);
4748 mono_arch_print_tree (MonoInst *tree, int arity)
4754 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
4756 /* FIXME: implement */
4757 g_assert_not_reached ();
4761 mono_arch_opcode_supported (int opcode)
4764 case OP_ATOMIC_ADD_I4:
4765 case OP_ATOMIC_ADD_I8:
4766 case OP_ATOMIC_EXCHANGE_I4:
4767 case OP_ATOMIC_EXCHANGE_I8: