2 * mini-ia64.c: IA64 backend for the Mono code generator
5 * Zoltan Varga (vargaz@gmail.com)
7 * (C) 2003 Ximian, Inc.
15 #ifdef __INTEL_COMPILER
16 #include <ia64intrin.h>
19 #include <mono/metadata/appdomain.h>
20 #include <mono/metadata/debug-helpers.h>
21 #include <mono/metadata/threads.h>
22 #include <mono/metadata/profiler-private.h>
23 #include <mono/utils/mono-math.h>
24 #include <mono/utils/mono-hwcap-ia64.h>
27 #include "mini-ia64.h"
29 #include "jit-icalls.h"
32 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
34 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
37 * IA64 register usage:
38 * - local registers are used for global register allocation
39 * - r8..r11, r14..r30 is used for local register allocation
40 * - r31 is a scratch register used within opcode implementations
41 * - FIXME: Use out registers as well
42 * - the first three locals are used for saving ar.pfst, b0, and sp
43 * - compare instructions allways set p6 and p7
47 * There are a lot of places where generated code is disassembled/patched.
48 * The automatic bundling of instructions done by the code generation macros
49 * could complicate things, so it is best to call
50 * ia64_codegen_set_one_ins_per_bundle () at those places.
53 #define ARGS_OFFSET 16
55 #define GP_SCRATCH_REG 31
56 #define GP_SCRATCH_REG2 30
57 #define FP_SCRATCH_REG 32
58 #define FP_SCRATCH_REG2 33
60 #define LOOP_ALIGNMENT 8
61 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
63 static const char* gregs [] = {
64 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
65 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
66 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29",
67 "r30", "r31", "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
68 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", "r48", "r49",
69 "r50", "r51", "r52", "r53", "r54", "r55", "r56", "r57", "r58", "r59",
70 "r60", "r61", "r62", "r63", "r64", "r65", "r66", "r67", "r68", "r69",
71 "r70", "r71", "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
72 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", "r88", "r89",
73 "r90", "r91", "r92", "r93", "r94", "r95", "r96", "r97", "r98", "r99",
74 "r100", "r101", "r102", "r103", "r104", "r105", "r106", "r107", "r108", "r109",
75 "r110", "r111", "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
76 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127"
80 mono_arch_regname (int reg)
88 static const char* fregs [] = {
89 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
90 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
91 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
92 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
93 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
94 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
95 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69",
96 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
97 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89",
98 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99",
99 "f100", "f101", "f102", "f103", "f104", "f105", "f106", "f107", "f108", "f109",
100 "f110", "f111", "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
101 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127"
105 mono_arch_fregname (int reg)
114 debug_ins_sched (void)
117 return mono_debug_count ();
127 return mono_debug_count ();
134 ia64_patch (unsigned char* code, gpointer target);
141 ArgValuetypeAddrInIReg,
159 /* Only if storage == ArgAggregate */
169 gboolean need_stack_align;
170 gboolean vtype_retaddr;
171 /* The index of the vret arg in the argument list */
178 #define DEBUG(a) if (cfg->verbose_level > 1) a
183 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
185 ainfo->offset = *stack_size;
187 if (*gr >= PARAM_REGS) {
188 ainfo->storage = ArgOnStack;
189 (*stack_size) += sizeof (gpointer);
192 ainfo->storage = ArgInIReg;
198 #define FLOAT_PARAM_REGS 8
201 add_float (guint32 *gr, guint32 *fr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
203 ainfo->offset = *stack_size;
205 if (*gr >= PARAM_REGS) {
206 ainfo->storage = ArgOnStack;
207 (*stack_size) += sizeof (gpointer);
210 ainfo->storage = is_double ? ArgInFloatReg : ArgInFloatRegR4;
211 ainfo->reg = 8 + *fr;
218 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
220 guint32 *gr, guint32 *fr, guint32 *stack_size)
224 MonoMarshalType *info;
225 gboolean is_hfa = TRUE;
226 guint32 hfa_type = 0;
228 klass = mono_class_from_mono_type (type);
229 if (type->type == MONO_TYPE_TYPEDBYREF)
230 size = 3 * sizeof (gpointer);
231 else if (sig->pinvoke)
232 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
234 size = mini_type_stack_size (&klass->byval_arg, NULL);
236 if (!sig->pinvoke || (size == 0)) {
237 /* Allways pass in memory */
238 ainfo->offset = *stack_size;
239 *stack_size += ALIGN_TO (size, 8);
240 ainfo->storage = ArgOnStack;
245 /* Determine whenever it is a HFA (Homogeneous Floating Point Aggregate) */
246 info = mono_marshal_load_type_info (klass);
248 for (i = 0; i < info->num_fields; ++i) {
249 guint32 ftype = info->fields [i].field->type->type;
250 if (!(info->fields [i].field->type->byref) &&
251 ((ftype == MONO_TYPE_R4) || (ftype == MONO_TYPE_R8))) {
254 else if (hfa_type != ftype)
263 ainfo->storage = ArgAggregate;
264 ainfo->atype = AggregateNormal;
267 ainfo->atype = hfa_type == MONO_TYPE_R4 ? AggregateSingleHFA : AggregateDoubleHFA;
269 if (info->num_fields <= 8) {
271 ainfo->nregs = info->num_fields;
272 ainfo->nslots = ainfo->nregs;
278 if ((*fr) + info->num_fields > 8)
281 ainfo->reg = 8 + (*fr);
282 ainfo->nregs = info->num_fields;
283 ainfo->nslots = ainfo->nregs;
284 (*fr) += info->num_fields;
285 if (ainfo->atype == AggregateSingleHFA) {
287 * FIXME: Have to keep track of the parameter slot number, which is
288 * not the same as *gr.
290 (*gr) += ALIGN_TO (info->num_fields, 2) / 2;
292 (*gr) += info->num_fields;
298 /* This also handles returning of TypedByRef used by some icalls */
301 ainfo->reg = IA64_R8;
302 ainfo->nregs = (size + 7) / 8;
303 ainfo->nslots = ainfo->nregs;
310 ainfo->offset = *stack_size;
311 ainfo->nslots = (size + 7) / 8;
313 if (((*gr) + ainfo->nslots) <= 8) {
314 /* Fits entirely in registers */
315 ainfo->nregs = ainfo->nslots;
316 (*gr) += ainfo->nregs;
320 ainfo->nregs = 8 - (*gr);
322 (*stack_size) += (ainfo->nslots - ainfo->nregs) * 8;
328 * Obtain information about a call according to the calling convention.
329 * For IA64, see the "Itanium Software Conventions and Runtime Architecture
330 * Gude" document for more information.
333 get_call_info (MonoCompile *cfg, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
335 guint32 i, gr, fr, pstart;
337 int n = sig->hasthis + sig->param_count;
338 guint32 stack_size = 0;
342 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
344 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
351 ret_type = mini_get_underlying_type (sig->ret);
352 switch (ret_type->type) {
353 case MONO_TYPE_BOOLEAN:
364 case MONO_TYPE_FNPTR:
365 case MONO_TYPE_CLASS:
366 case MONO_TYPE_OBJECT:
367 case MONO_TYPE_SZARRAY:
368 case MONO_TYPE_ARRAY:
369 case MONO_TYPE_STRING:
370 cinfo->ret.storage = ArgInIReg;
371 cinfo->ret.reg = IA64_R8;
375 cinfo->ret.storage = ArgInIReg;
376 cinfo->ret.reg = IA64_R8;
380 cinfo->ret.storage = ArgInFloatReg;
383 case MONO_TYPE_GENERICINST:
384 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
385 cinfo->ret.storage = ArgInIReg;
386 cinfo->ret.reg = IA64_R8;
390 case MONO_TYPE_VALUETYPE:
391 case MONO_TYPE_TYPEDBYREF: {
392 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
394 if (sig->ret->byref) {
395 /* This seems to happen with ldfld wrappers */
396 cinfo->ret.storage = ArgInIReg;
398 add_valuetype (sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
399 if (cinfo->ret.storage == ArgOnStack) {
400 /* The caller passes the address where the value is stored */
401 cinfo->vtype_retaddr = TRUE;
407 cinfo->ret.storage = ArgNone;
410 g_error ("Can't handle as return value 0x%x", sig->ret->type);
416 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
417 * the first argument, allowing 'this' to be always passed in the first arg reg.
418 * Also do this if the first argument is a reference type, since virtual calls
419 * are sometimes made using calli without sig->hasthis set, like in the delegate
422 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
424 add_general (&gr, &stack_size, cinfo->args + 0);
426 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
429 add_general (&gr, &stack_size, &cinfo->ret);
430 if (cinfo->ret.storage == ArgInIReg)
431 cinfo->ret.storage = ArgValuetypeAddrInIReg;
432 cinfo->vret_arg_index = 1;
436 add_general (&gr, &stack_size, cinfo->args + 0);
438 if (cinfo->vtype_retaddr) {
439 add_general (&gr, &stack_size, &cinfo->ret);
440 if (cinfo->ret.storage == ArgInIReg)
441 cinfo->ret.storage = ArgValuetypeAddrInIReg;
445 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
447 fr = FLOAT_PARAM_REGS;
449 /* Emit the signature cookie just before the implicit arguments */
450 add_general (&gr, &stack_size, &cinfo->sig_cookie);
453 for (i = pstart; i < sig->param_count; ++i) {
454 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
457 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
458 /* We allways pass the sig cookie on the stack for simplicity */
460 * Prevent implicit arguments + the sig cookie from being passed
464 fr = FLOAT_PARAM_REGS;
466 /* Emit the signature cookie just before the implicit arguments */
467 add_general (&gr, &stack_size, &cinfo->sig_cookie);
470 if (sig->params [i]->byref) {
471 add_general (&gr, &stack_size, ainfo);
474 ptype = mini_get_underlying_type (sig->params [i]);
475 switch (ptype->type) {
476 case MONO_TYPE_BOOLEAN:
479 add_general (&gr, &stack_size, ainfo);
484 add_general (&gr, &stack_size, ainfo);
488 add_general (&gr, &stack_size, ainfo);
493 case MONO_TYPE_FNPTR:
494 case MONO_TYPE_CLASS:
495 case MONO_TYPE_OBJECT:
496 case MONO_TYPE_STRING:
497 case MONO_TYPE_SZARRAY:
498 case MONO_TYPE_ARRAY:
499 add_general (&gr, &stack_size, ainfo);
501 case MONO_TYPE_GENERICINST:
502 if (!mono_type_generic_inst_is_valuetype (ptype)) {
503 add_general (&gr, &stack_size, ainfo);
507 case MONO_TYPE_VALUETYPE:
508 case MONO_TYPE_TYPEDBYREF:
510 /* We allways pass valuetypes on the stack */
511 add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
515 add_general (&gr, &stack_size, ainfo);
518 add_float (&gr, &fr, &stack_size, ainfo, FALSE);
521 add_float (&gr, &fr, &stack_size, ainfo, TRUE);
524 g_assert_not_reached ();
528 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
530 fr = FLOAT_PARAM_REGS;
532 /* Emit the signature cookie just before the implicit arguments */
533 add_general (&gr, &stack_size, &cinfo->sig_cookie);
536 cinfo->stack_usage = stack_size;
537 cinfo->reg_usage = gr;
538 cinfo->freg_usage = fr;
543 * mono_arch_get_argument_info:
544 * @csig: a method signature
545 * @param_count: the number of parameters to consider
546 * @arg_info: an array to store the result infos
548 * Gathers information on parameters such as size, alignment and
549 * padding. arg_info should be large enought to hold param_count + 1 entries.
551 * Returns the size of the argument area on the stack.
554 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
557 CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
558 guint32 args_size = cinfo->stack_usage;
560 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
562 arg_info [0].offset = 0;
565 for (k = 0; k < param_count; k++) {
566 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
568 arg_info [k + 1].size = 0;
577 * Initialize the cpu to execute managed code.
580 mono_arch_cpu_init (void)
585 * Initialize architecture specific code.
588 mono_arch_init (void)
593 * Cleanup architecture specific code.
596 mono_arch_cleanup (void)
601 * This function returns the optimizations supported on this cpu.
604 mono_arch_cpu_optimizations (guint32 *exclude_mask)
612 * This function test for all SIMD functions supported.
614 * Returns a bitmask corresponding to all supported versions.
618 mono_arch_cpu_enumerate_simd_versions (void)
620 /* SIMD is currently unimplemented */
625 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
629 MonoMethodSignature *sig;
630 MonoMethodHeader *header;
633 header = cfg->header;
635 sig = mono_method_signature (cfg->method);
637 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
639 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
640 MonoInst *ins = cfg->args [i];
642 ArgInfo *ainfo = &cinfo->args [i];
644 if (ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT))
647 if (ainfo->storage == ArgInIReg) {
648 /* The input registers are non-volatile */
649 ins->opcode = OP_REGVAR;
650 ins->dreg = 32 + ainfo->reg;
654 for (i = 0; i < cfg->num_varinfo; i++) {
655 MonoInst *ins = cfg->varinfo [i];
656 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
659 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
662 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
663 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
666 if (mono_is_regsize_var (ins->inst_vtype)) {
667 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
668 g_assert (i == vmv->idx);
669 vars = g_list_prepend (vars, vmv);
673 vars = mono_varlist_sort (cfg, vars, 0);
679 mono_ia64_alloc_stacked_registers (MonoCompile *cfg)
682 guint32 reserved_regs;
683 MonoMethodHeader *header;
685 if (cfg->arch.reg_local0 > 0)
689 cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (cfg->method), FALSE);
691 header = cfg->header;
693 /* Some registers are reserved for use by the prolog/epilog */
694 reserved_regs = header->num_clauses ? 4 : 3;
696 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
697 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
698 /* One registers is needed by instrument_epilog to save the return value */
700 if (cinfo->reg_usage < 2)
701 /* Number of arguments passed to function call in instrument_prolog */
702 cinfo->reg_usage = 2;
705 cfg->arch.reg_in0 = 32;
706 cfg->arch.reg_local0 = cfg->arch.reg_in0 + cinfo->reg_usage + reserved_regs;
707 cfg->arch.reg_out0 = cfg->arch.reg_local0 + 16;
709 cfg->arch.reg_saved_ar_pfs = cfg->arch.reg_local0 - 1;
710 cfg->arch.reg_saved_b0 = cfg->arch.reg_local0 - 2;
711 cfg->arch.reg_fp = cfg->arch.reg_local0 - 3;
714 * Frames without handlers save sp to fp, frames with handlers save it into
715 * a dedicated register.
717 if (header->num_clauses)
718 cfg->arch.reg_saved_sp = cfg->arch.reg_local0 - 4;
720 cfg->arch.reg_saved_sp = cfg->arch.reg_fp;
722 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
723 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
724 cfg->arch.reg_saved_return_val = cfg->arch.reg_local0 - reserved_regs;
728 * Need to allocate at least 2 out register for use by OP_THROW / the system
729 * exception throwing code.
731 cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, 2);
735 mono_arch_get_global_int_regs (MonoCompile *cfg)
740 mono_ia64_alloc_stacked_registers (cfg);
742 for (i = cfg->arch.reg_local0; i < cfg->arch.reg_out0; ++i) {
745 regs = g_list_prepend (regs, (gpointer)(gssize)(i));
752 * mono_arch_regalloc_cost:
754 * Return the cost, in number of memory references, of the action of
755 * allocating the variable VMV into a register during global register
759 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
761 /* FIXME: Increase costs linearly to avoid using all local registers */
767 mono_arch_allocate_vars (MonoCompile *cfg)
769 MonoMethodSignature *sig;
770 MonoMethodHeader *header;
773 guint32 locals_stack_size, locals_stack_align;
777 header = cfg->header;
779 sig = mono_method_signature (cfg->method);
781 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
784 * Determine whenever the frame pointer can be eliminated.
785 * FIXME: Remove some of the restrictions.
787 cfg->arch.omit_fp = TRUE;
789 if (!debug_omit_fp ())
790 cfg->arch.omit_fp = FALSE;
792 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
793 cfg->arch.omit_fp = FALSE;
794 if (header->num_clauses)
795 cfg->arch.omit_fp = FALSE;
797 cfg->arch.omit_fp = FALSE;
798 if ((sig->ret->type != MONO_TYPE_VOID) && (cinfo->ret.storage == ArgAggregate))
799 cfg->arch.omit_fp = FALSE;
800 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
801 cfg->arch.omit_fp = FALSE;
802 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
803 ArgInfo *ainfo = &cinfo->args [i];
805 if (ainfo->storage == ArgOnStack) {
807 * The stack offset can only be determined when the frame
810 cfg->arch.omit_fp = FALSE;
814 mono_ia64_alloc_stacked_registers (cfg);
817 * We use the ABI calling conventions for managed code as well.
818 * Exception: valuetypes are never passed or returned in registers.
821 if (cfg->arch.omit_fp) {
822 cfg->flags |= MONO_CFG_HAS_SPILLUP;
823 cfg->frame_reg = IA64_SP;
824 offset = ARGS_OFFSET;
827 /* Locals are allocated backwards from %fp */
828 cfg->frame_reg = cfg->arch.reg_fp;
832 if (cfg->method->save_lmf) {
836 if (sig->ret->type != MONO_TYPE_VOID) {
837 switch (cinfo->ret.storage) {
839 cfg->ret->opcode = OP_REGVAR;
840 cfg->ret->inst_c0 = cinfo->ret.reg;
843 cfg->ret->opcode = OP_REGVAR;
844 cfg->ret->inst_c0 = cinfo->ret.reg;
846 case ArgValuetypeAddrInIReg:
847 cfg->vret_addr->opcode = OP_REGVAR;
848 cfg->vret_addr->dreg = cfg->arch.reg_in0 + cinfo->ret.reg;
851 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
852 if (cfg->arch.omit_fp)
853 g_assert_not_reached ();
854 offset = ALIGN_TO (offset, 8);
855 offset += cinfo->ret.nslots * 8;
856 cfg->ret->opcode = OP_REGOFFSET;
857 cfg->ret->inst_basereg = cfg->frame_reg;
858 cfg->ret->inst_offset = - offset;
861 g_assert_not_reached ();
863 cfg->ret->dreg = cfg->ret->inst_c0;
866 /* Allocate locals */
867 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE : TRUE, &locals_stack_size, &locals_stack_align);
868 if (locals_stack_align) {
869 offset = ALIGN_TO (offset, locals_stack_align);
871 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
872 if (offsets [i] != -1) {
873 MonoInst *inst = cfg->varinfo [i];
874 inst->opcode = OP_REGOFFSET;
875 inst->inst_basereg = cfg->frame_reg;
876 if (cfg->arch.omit_fp)
877 inst->inst_offset = (offset + offsets [i]);
879 inst->inst_offset = - (offset + offsets [i]);
880 // printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
883 offset += locals_stack_size;
885 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
886 if (cfg->arch.omit_fp)
887 g_assert_not_reached ();
888 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
889 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
892 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
893 inst = cfg->args [i];
894 if (inst->opcode != OP_REGVAR) {
895 ArgInfo *ainfo = &cinfo->args [i];
896 gboolean inreg = TRUE;
899 if (sig->hasthis && (i == 0))
900 arg_type = &mono_defaults.object_class->byval_arg;
902 arg_type = sig->params [i - sig->hasthis];
904 /* FIXME: VOLATILE is only set if the liveness pass runs */
905 if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
908 inst->opcode = OP_REGOFFSET;
910 switch (ainfo->storage) {
912 inst->opcode = OP_REGVAR;
913 inst->dreg = cfg->arch.reg_in0 + ainfo->reg;
916 case ArgInFloatRegR4:
918 * Since float regs are volatile, we save the arguments to
919 * the stack in the prolog.
924 if (cfg->arch.omit_fp)
925 g_assert_not_reached ();
926 inst->opcode = OP_REGOFFSET;
927 inst->inst_basereg = cfg->frame_reg;
928 inst->inst_offset = ARGS_OFFSET + ainfo->offset;
937 if (!inreg && (ainfo->storage != ArgOnStack)) {
940 inst->opcode = OP_REGOFFSET;
941 inst->inst_basereg = cfg->frame_reg;
942 /* These arguments are saved to the stack in the prolog */
943 switch (ainfo->storage) {
945 if (ainfo->atype == AggregateSingleHFA)
946 size = ainfo->nslots * 4;
948 size = ainfo->nslots * 8;
951 size = sizeof (gpointer);
955 offset = ALIGN_TO (offset, sizeof (gpointer));
957 if (cfg->arch.omit_fp) {
958 inst->inst_offset = offset;
962 inst->inst_offset = - offset;
969 * FIXME: This doesn't work because some variables are allocated during local
973 if (cfg->arch.omit_fp && offset == 16)
977 cfg->stack_offset = offset;
981 mono_arch_create_vars (MonoCompile *cfg)
983 MonoMethodSignature *sig;
986 sig = mono_method_signature (cfg->method);
988 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
990 if (cinfo->ret.storage == ArgAggregate)
991 cfg->ret_var_is_local = TRUE;
992 if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
993 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
994 if (G_UNLIKELY (cfg->verbose_level > 1)) {
995 printf ("vret_addr = ");
996 mono_print_ins (cfg->vret_addr);
1002 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1006 MONO_INST_NEW (cfg, arg, OP_NOP);
1007 arg->sreg1 = tree->dreg;
1011 arg->opcode = OP_MOVE;
1012 arg->dreg = mono_alloc_ireg (cfg);
1014 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, FALSE);
1017 arg->opcode = OP_FMOVE;
1018 arg->dreg = mono_alloc_freg (cfg);
1020 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1022 case ArgInFloatRegR4:
1023 arg->opcode = OP_FCONV_TO_R4;
1024 arg->dreg = mono_alloc_freg (cfg);
1026 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1029 g_assert_not_reached ();
1032 MONO_ADD_INS (cfg->cbb, arg);
1036 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1038 MonoMethodSignature *tmp_sig;
1040 /* Emit the signature cookie just before the implicit arguments */
1042 /* FIXME: Add support for signature tokens to AOT */
1043 cfg->disable_aot = TRUE;
1045 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1048 * mono_ArgIterator_Setup assumes the signature cookie is
1049 * passed first and all the arguments which were before it are
1050 * passed on the stack after the signature. So compensate by
1051 * passing a different signature.
1053 tmp_sig = mono_metadata_signature_dup (call->signature);
1054 tmp_sig->param_count -= call->signature->sentinelpos;
1055 tmp_sig->sentinelpos = 0;
1056 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1058 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1059 sig_arg->dreg = mono_alloc_ireg (cfg);
1060 sig_arg->inst_p0 = tmp_sig;
1061 MONO_ADD_INS (cfg->cbb, sig_arg);
1063 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + cinfo->sig_cookie.offset, sig_arg->dreg);
1067 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1070 MonoMethodSignature *sig;
1071 int i, n, stack_size;
1077 mono_ia64_alloc_stacked_registers (cfg);
1079 sig = call->signature;
1080 n = sig->param_count + sig->hasthis;
1082 cinfo = get_call_info (cfg, cfg->mempool, sig, sig->pinvoke);
1084 if (cinfo->ret.storage == ArgAggregate) {
1089 * The valuetype is in registers after the call, need to be copied
1090 * to the stack. Save the address to a local here, so the call
1091 * instruction can access it.
1093 local = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1094 local->flags |= MONO_INST_VOLATILE;
1095 cfg->arch.ret_var_addr_local = local;
1097 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1098 vtarg->sreg1 = call->vret_var->dreg;
1099 vtarg->dreg = local->dreg;
1100 MONO_ADD_INS (cfg->cbb, vtarg);
1103 if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1104 add_outarg_reg (cfg, call, ArgInIReg, cfg->arch.reg_out0 + cinfo->ret.reg, call->vret_var);
1107 for (i = 0; i < n; ++i) {
1110 ainfo = cinfo->args + i;
1112 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1113 /* Emit the signature cookie just before the implicit arguments */
1114 emit_sig_cookie (cfg, call, cinfo);
1117 in = call->args [i];
1119 if (sig->hasthis && (i == 0))
1120 arg_type = &mono_defaults.object_class->byval_arg;
1122 arg_type = sig->params [i - sig->hasthis];
1124 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(arg_type))) {
1128 if (arg_type->type == MONO_TYPE_TYPEDBYREF) {
1129 size = sizeof (MonoTypedRef);
1130 align = sizeof (gpointer);
1132 else if (sig->pinvoke)
1133 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1136 * Other backends use mono_type_stack_size (), but that
1137 * aligns the size to 8, which is larger than the size of
1138 * the source, leading to reads of invalid memory if the
1139 * source is at the end of address space.
1141 size = mono_class_value_size (in->klass, &align);
1147 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1148 arg->sreg1 = in->dreg;
1149 arg->klass = in->klass;
1150 arg->backend.size = size;
1151 arg->inst_p0 = call;
1152 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1153 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1155 MONO_ADD_INS (cfg->cbb, arg);
1159 switch (ainfo->storage) {
1161 add_outarg_reg (cfg, call, ainfo->storage, cfg->arch.reg_out0 + ainfo->reg, in);
1164 case ArgInFloatRegR4:
1165 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1168 if (arg_type->type == MONO_TYPE_R4 && !arg_type->byref)
1169 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1170 else if (arg_type->type == MONO_TYPE_R8 && !arg_type->byref)
1171 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1173 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1176 g_assert_not_reached ();
1181 /* Handle the case where there are no implicit arguments */
1182 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1183 emit_sig_cookie (cfg, call, cinfo);
1186 call->stack_usage = cinfo->stack_usage;
1187 cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, cinfo->reg_usage);
1191 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1193 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1194 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1195 int size = ins->backend.size;
1197 if (ainfo->storage == ArgAggregate) {
1198 MonoInst *load, *store;
1202 * Part of the structure is passed in registers.
1204 for (i = 0; i < ainfo->nregs; ++i) {
1205 slot = ainfo->reg + i;
1207 if (ainfo->atype == AggregateSingleHFA) {
1208 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
1209 load->inst_basereg = src->dreg;
1210 load->inst_offset = i * 4;
1211 load->dreg = mono_alloc_freg (cfg);
1213 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1214 } else if (ainfo->atype == AggregateDoubleHFA) {
1215 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
1216 load->inst_basereg = src->dreg;
1217 load->inst_offset = i * 8;
1218 load->dreg = mono_alloc_freg (cfg);
1220 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1222 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1223 load->inst_basereg = src->dreg;
1224 load->inst_offset = i * 8;
1225 load->dreg = mono_alloc_ireg (cfg);
1227 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, cfg->arch.reg_out0 + ainfo->reg + i, FALSE);
1229 MONO_ADD_INS (cfg->cbb, load);
1233 * Part of the structure is passed on the stack.
1235 for (i = ainfo->nregs; i < ainfo->nslots; ++i) {
1236 slot = ainfo->reg + i;
1238 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1239 load->inst_basereg = src->dreg;
1240 load->inst_offset = i * sizeof (gpointer);
1241 load->dreg = mono_alloc_preg (cfg);
1242 MONO_ADD_INS (cfg->cbb, load);
1244 MONO_INST_NEW (cfg, store, OP_STOREI8_MEMBASE_REG);
1245 store->sreg1 = load->dreg;
1246 store->inst_destbasereg = IA64_SP;
1247 store->inst_offset = 16 + ainfo->offset + (slot - 8) * 8;
1248 MONO_ADD_INS (cfg->cbb, store);
1251 mini_emit_memcpy (cfg, IA64_SP, 16 + ainfo->offset, src->dreg, 0, size, 4);
1256 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1258 CallInfo *cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
1260 switch (cinfo->ret.storage) {
1262 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1265 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1268 g_assert_not_reached ();
1273 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1278 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1280 MonoInst *ins, *n, *last_ins = NULL;
1283 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1284 switch (ins->opcode) {
1292 if (ins->dreg == ins->sreg1) {
1293 MONO_DELETE_INS (bb, ins);
1299 * OP_MOVE sreg, dreg
1300 * OP_MOVE dreg, sreg
1302 if (last_ins && last_ins->opcode == OP_MOVE &&
1303 ins->sreg1 == last_ins->dreg &&
1304 ins->dreg == last_ins->sreg1) {
1305 MONO_DELETE_INS (bb, ins);
1311 /* remove unnecessary multiplication with 1 */
1312 if (ins->inst_imm == 1) {
1313 if (ins->dreg != ins->sreg1) {
1314 ins->opcode = OP_MOVE;
1316 MONO_DELETE_INS (bb, ins);
1326 bb->last_ins = last_ins;
1329 int cond_to_ia64_cmp [][3] = {
1330 {OP_IA64_CMP_EQ, OP_IA64_CMP4_EQ, OP_IA64_FCMP_EQ},
1331 {OP_IA64_CMP_NE, OP_IA64_CMP4_NE, OP_IA64_FCMP_NE},
1332 {OP_IA64_CMP_LE, OP_IA64_CMP4_LE, OP_IA64_FCMP_LE},
1333 {OP_IA64_CMP_GE, OP_IA64_CMP4_GE, OP_IA64_FCMP_GE},
1334 {OP_IA64_CMP_LT, OP_IA64_CMP4_LT, OP_IA64_FCMP_LT},
1335 {OP_IA64_CMP_GT, OP_IA64_CMP4_GT, OP_IA64_FCMP_GT},
1336 {OP_IA64_CMP_LE_UN, OP_IA64_CMP4_LE_UN, OP_IA64_FCMP_LE_UN},
1337 {OP_IA64_CMP_GE_UN, OP_IA64_CMP4_GE_UN, OP_IA64_FCMP_GE_UN},
1338 {OP_IA64_CMP_LT_UN, OP_IA64_CMP4_LT_UN, OP_IA64_FCMP_LT_UN},
1339 {OP_IA64_CMP_GT_UN, OP_IA64_CMP4_GT_UN, OP_IA64_FCMP_GT_UN}
1343 opcode_to_ia64_cmp (int opcode, int cmp_opcode)
1345 return cond_to_ia64_cmp [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1348 int cond_to_ia64_cmp_imm [][3] = {
1349 {OP_IA64_CMP_EQ_IMM, OP_IA64_CMP4_EQ_IMM, 0},
1350 {OP_IA64_CMP_NE_IMM, OP_IA64_CMP4_NE_IMM, 0},
1351 {OP_IA64_CMP_GE_IMM, OP_IA64_CMP4_GE_IMM, 0},
1352 {OP_IA64_CMP_LE_IMM, OP_IA64_CMP4_LE_IMM, 0},
1353 {OP_IA64_CMP_GT_IMM, OP_IA64_CMP4_GT_IMM, 0},
1354 {OP_IA64_CMP_LT_IMM, OP_IA64_CMP4_LT_IMM, 0},
1355 {OP_IA64_CMP_GE_UN_IMM, OP_IA64_CMP4_GE_UN_IMM, 0},
1356 {OP_IA64_CMP_LE_UN_IMM, OP_IA64_CMP4_LE_UN_IMM, 0},
1357 {OP_IA64_CMP_GT_UN_IMM, OP_IA64_CMP4_GT_UN_IMM, 0},
1358 {OP_IA64_CMP_LT_UN_IMM, OP_IA64_CMP4_LT_UN_IMM, 0},
1362 opcode_to_ia64_cmp_imm (int opcode, int cmp_opcode)
1364 /* The condition needs to be reversed */
1365 return cond_to_ia64_cmp_imm [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1368 #define NEW_INS(cfg,dest,op) do { \
1369 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
1370 (dest)->opcode = (op); \
1371 mono_bblock_insert_after_ins (bb, last_ins, (dest)); \
1372 last_ins = (dest); \
1376 * mono_arch_lowering_pass:
1378 * Converts complex opcodes into simpler ones so that each IR instruction
1379 * corresponds to one machine instruction.
1382 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1384 MonoInst *ins, *n, *next, *temp, *temp2, *temp3, *last_ins = NULL;
1387 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1388 switch (ins->opcode) {
1389 case OP_STOREI1_MEMBASE_IMM:
1390 case OP_STOREI2_MEMBASE_IMM:
1391 case OP_STOREI4_MEMBASE_IMM:
1392 case OP_STOREI8_MEMBASE_IMM:
1393 case OP_STORE_MEMBASE_IMM:
1394 /* There are no store_membase instructions on ia64 */
1395 if (ins->inst_offset == 0) {
1397 } else if (ia64_is_imm14 (ins->inst_offset)) {
1398 NEW_INS (cfg, temp2, OP_ADD_IMM);
1399 temp2->sreg1 = ins->inst_destbasereg;
1400 temp2->inst_imm = ins->inst_offset;
1401 temp2->dreg = mono_alloc_ireg (cfg);
1404 NEW_INS (cfg, temp, OP_I8CONST);
1405 temp->inst_c0 = ins->inst_offset;
1406 temp->dreg = mono_alloc_ireg (cfg);
1408 NEW_INS (cfg, temp2, OP_LADD);
1409 temp2->sreg1 = ins->inst_destbasereg;
1410 temp2->sreg2 = temp->dreg;
1411 temp2->dreg = mono_alloc_ireg (cfg);
1414 switch (ins->opcode) {
1415 case OP_STOREI1_MEMBASE_IMM:
1416 ins->opcode = OP_STOREI1_MEMBASE_REG;
1418 case OP_STOREI2_MEMBASE_IMM:
1419 ins->opcode = OP_STOREI2_MEMBASE_REG;
1421 case OP_STOREI4_MEMBASE_IMM:
1422 ins->opcode = OP_STOREI4_MEMBASE_REG;
1424 case OP_STOREI8_MEMBASE_IMM:
1425 case OP_STORE_MEMBASE_IMM:
1426 ins->opcode = OP_STOREI8_MEMBASE_REG;
1429 g_assert_not_reached ();
1432 if (ins->inst_imm == 0)
1433 ins->sreg1 = IA64_R0;
1435 NEW_INS (cfg, temp3, OP_I8CONST);
1436 temp3->inst_c0 = ins->inst_imm;
1437 temp3->dreg = mono_alloc_ireg (cfg);
1438 ins->sreg1 = temp3->dreg;
1441 ins->inst_offset = 0;
1443 ins->inst_destbasereg = temp2->dreg;
1445 case OP_STOREI1_MEMBASE_REG:
1446 case OP_STOREI2_MEMBASE_REG:
1447 case OP_STOREI4_MEMBASE_REG:
1448 case OP_STOREI8_MEMBASE_REG:
1449 case OP_STORER4_MEMBASE_REG:
1450 case OP_STORER8_MEMBASE_REG:
1451 case OP_STORE_MEMBASE_REG:
1452 /* There are no store_membase instructions on ia64 */
1453 if (ins->inst_offset == 0) {
1456 else if (ia64_is_imm14 (ins->inst_offset)) {
1457 NEW_INS (cfg, temp2, OP_ADD_IMM);
1458 temp2->sreg1 = ins->inst_destbasereg;
1459 temp2->inst_imm = ins->inst_offset;
1460 temp2->dreg = mono_alloc_ireg (cfg);
1463 NEW_INS (cfg, temp, OP_I8CONST);
1464 temp->inst_c0 = ins->inst_offset;
1465 temp->dreg = mono_alloc_ireg (cfg);
1466 NEW_INS (cfg, temp2, OP_LADD);
1467 temp2->sreg1 = ins->inst_destbasereg;
1468 temp2->sreg2 = temp->dreg;
1469 temp2->dreg = mono_alloc_ireg (cfg);
1472 ins->inst_offset = 0;
1473 ins->inst_destbasereg = temp2->dreg;
1475 case OP_LOADI1_MEMBASE:
1476 case OP_LOADU1_MEMBASE:
1477 case OP_LOADI2_MEMBASE:
1478 case OP_LOADU2_MEMBASE:
1479 case OP_LOADI4_MEMBASE:
1480 case OP_LOADU4_MEMBASE:
1481 case OP_LOADI8_MEMBASE:
1482 case OP_LOAD_MEMBASE:
1483 case OP_LOADR4_MEMBASE:
1484 case OP_LOADR8_MEMBASE:
1485 case OP_ATOMIC_EXCHANGE_I4:
1486 case OP_ATOMIC_EXCHANGE_I8:
1487 case OP_ATOMIC_ADD_I4:
1488 case OP_ATOMIC_ADD_I8:
1489 case OP_ATOMIC_ADD_IMM_I4:
1490 case OP_ATOMIC_ADD_IMM_I8:
1491 /* There are no membase instructions on ia64 */
1492 if (ins->inst_offset == 0) {
1495 else if (ia64_is_imm14 (ins->inst_offset)) {
1496 NEW_INS (cfg, temp2, OP_ADD_IMM);
1497 temp2->sreg1 = ins->inst_basereg;
1498 temp2->inst_imm = ins->inst_offset;
1499 temp2->dreg = mono_alloc_ireg (cfg);
1502 NEW_INS (cfg, temp, OP_I8CONST);
1503 temp->inst_c0 = ins->inst_offset;
1504 temp->dreg = mono_alloc_ireg (cfg);
1505 NEW_INS (cfg, temp2, OP_LADD);
1506 temp2->sreg1 = ins->inst_basereg;
1507 temp2->sreg2 = temp->dreg;
1508 temp2->dreg = mono_alloc_ireg (cfg);
1511 ins->inst_offset = 0;
1512 ins->inst_basereg = temp2->dreg;
1532 case OP_ISHR_UN_IMM:
1533 case OP_LSHR_UN_IMM: {
1534 gboolean is_imm = FALSE;
1535 gboolean switched = FALSE;
1537 if (ins->opcode == OP_AND_IMM && ins->inst_imm == 255) {
1538 ins->opcode = OP_ZEXT_I1;
1542 switch (ins->opcode) {
1546 is_imm = ia64_is_imm14 (ins->inst_imm);
1551 is_imm = ia64_is_imm14 (- (ins->inst_imm));
1553 /* A = B - IMM -> A = B + (-IMM) */
1554 ins->inst_imm = - ins->inst_imm;
1555 ins->opcode = OP_IADD_IMM;
1566 is_imm = ia64_is_imm8 (ins->inst_imm);
1575 case OP_ISHR_UN_IMM:
1576 case OP_LSHR_UN_IMM:
1577 is_imm = (ins->inst_imm >= 0) && (ins->inst_imm < 64);
1585 ins->sreg2 = ins->sreg1;
1589 ins->opcode = mono_op_imm_to_op (ins->opcode);
1591 if (ins->inst_imm == 0)
1592 ins->sreg2 = IA64_R0;
1594 NEW_INS (cfg, temp, OP_I8CONST);
1595 temp->inst_c0 = ins->inst_imm;
1596 temp->dreg = mono_alloc_ireg (cfg);
1597 ins->sreg2 = temp->dreg;
1601 case OP_COMPARE_IMM:
1602 case OP_ICOMPARE_IMM:
1603 case OP_LCOMPARE_IMM: {
1604 /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1610 /* Branch opts can eliminate the branch */
1611 if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1617 * The compare_imm instructions have switched up arguments, and
1618 * some of them take an imm between -127 and 128.
1621 cond = mono_opcode_to_cond (next->opcode);
1622 if ((cond == CMP_LT) || (cond == CMP_GE))
1623 imm = ia64_is_imm8 (ins->inst_imm - 1);
1624 else if ((cond == CMP_LT_UN) || (cond == CMP_GE_UN))
1625 imm = ia64_is_imm8 (ins->inst_imm - 1) && (ins->inst_imm > 0);
1627 imm = ia64_is_imm8 (ins->inst_imm);
1630 ins->opcode = opcode_to_ia64_cmp_imm (next->opcode, ins->opcode);
1631 ins->sreg2 = ins->sreg1;
1634 ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1636 if (ins->inst_imm == 0)
1637 ins->sreg2 = IA64_R0;
1639 NEW_INS (cfg, temp, OP_I8CONST);
1640 temp->inst_c0 = ins->inst_imm;
1641 temp->dreg = mono_alloc_ireg (cfg);
1642 ins->sreg2 = temp->dreg;
1646 if (MONO_IS_COND_BRANCH_OP (next)) {
1647 next->opcode = OP_IA64_BR_COND;
1648 next->inst_target_bb = next->inst_true_bb;
1649 } else if (MONO_IS_COND_EXC (next)) {
1650 next->opcode = OP_IA64_COND_EXC;
1651 } else if (MONO_IS_SETCC (next)) {
1652 next->opcode = OP_IA64_CSET;
1654 printf ("%s\n", mono_inst_name (next->opcode));
1664 /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1668 /* Branch opts can eliminate the branch */
1669 if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1674 ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1676 if (MONO_IS_COND_BRANCH_OP (next)) {
1677 next->opcode = OP_IA64_BR_COND;
1678 next->inst_target_bb = next->inst_true_bb;
1679 } else if (MONO_IS_COND_EXC (next)) {
1680 next->opcode = OP_IA64_COND_EXC;
1681 } else if (MONO_IS_SETCC (next)) {
1682 next->opcode = OP_IA64_CSET;
1684 printf ("%s\n", mono_inst_name (next->opcode));
1695 /* The front end removes the fcompare, so introduce it again */
1696 NEW_INS (cfg, temp, opcode_to_ia64_cmp (ins->opcode, OP_FCOMPARE));
1697 temp->sreg1 = ins->sreg1;
1698 temp->sreg2 = ins->sreg2;
1700 ins->opcode = OP_IA64_CSET;
1701 MONO_INST_NULLIFY_SREGS (ins);
1707 gboolean found = FALSE;
1708 int shl_op = ins->opcode == OP_IMUL_IMM ? OP_ISHL_IMM : OP_SHL_IMM;
1710 /* First the easy cases */
1711 if (ins->inst_imm == 1) {
1712 ins->opcode = OP_MOVE;
1715 for (i = 1; i < 64; ++i)
1716 if (ins->inst_imm == (((gint64)1) << i)) {
1717 ins->opcode = shl_op;
1723 /* This could be optimized */
1726 for (i = 0; i < 64; ++i) {
1727 if (ins->inst_imm & (((gint64)1) << i)) {
1728 NEW_INS (cfg, temp, shl_op);
1729 temp->dreg = mono_alloc_ireg (cfg);
1730 temp->sreg1 = ins->sreg1;
1734 sum_reg = temp->dreg;
1736 NEW_INS (cfg, temp2, OP_LADD);
1737 temp2->dreg = mono_alloc_ireg (cfg);
1738 temp2->sreg1 = sum_reg;
1739 temp2->sreg2 = temp->dreg;
1740 sum_reg = temp2->dreg;
1744 ins->opcode = OP_MOVE;
1745 ins->sreg1 = sum_reg;
1749 case OP_LCONV_TO_OVF_U4:
1750 NEW_INS (cfg, temp, OP_IA64_CMP4_LT);
1751 temp->sreg1 = ins->sreg1;
1752 temp->sreg2 = IA64_R0;
1754 NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1755 temp->inst_p1 = (char*)"OverflowException";
1757 ins->opcode = OP_MOVE;
1759 case OP_LCONV_TO_OVF_I4_UN:
1760 NEW_INS (cfg, temp, OP_ICONST);
1761 temp->inst_c0 = 0x7fffffff;
1762 temp->dreg = mono_alloc_ireg (cfg);
1764 NEW_INS (cfg, temp2, OP_IA64_CMP4_GT_UN);
1765 temp2->sreg1 = ins->sreg1;
1766 temp2->sreg2 = temp->dreg;
1768 NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1769 temp->inst_p1 = (char*)"OverflowException";
1771 ins->opcode = OP_MOVE;
1773 case OP_FCONV_TO_I4:
1774 case OP_FCONV_TO_I2:
1775 case OP_FCONV_TO_U2:
1776 case OP_FCONV_TO_I1:
1777 case OP_FCONV_TO_U1:
1778 NEW_INS (cfg, temp, OP_FCONV_TO_I8);
1779 temp->sreg1 = ins->sreg1;
1780 temp->dreg = ins->dreg;
1782 switch (ins->opcode) {
1783 case OP_FCONV_TO_I4:
1784 ins->opcode = OP_SEXT_I4;
1786 case OP_FCONV_TO_I2:
1787 ins->opcode = OP_SEXT_I2;
1789 case OP_FCONV_TO_U2:
1790 ins->opcode = OP_ZEXT_I4;
1792 case OP_FCONV_TO_I1:
1793 ins->opcode = OP_SEXT_I1;
1795 case OP_FCONV_TO_U1:
1796 ins->opcode = OP_ZEXT_I1;
1799 g_assert_not_reached ();
1801 ins->sreg1 = ins->dreg;
1809 bb->last_ins = last_ins;
1811 bb->max_vreg = cfg->next_vreg;
1815 * emit_load_volatile_arguments:
1817 * Load volatile arguments from the stack to the original input registers.
1818 * Required before a tail call.
1820 static Ia64CodegenState
1821 emit_load_volatile_arguments (MonoCompile *cfg, Ia64CodegenState code)
1823 MonoMethod *method = cfg->method;
1824 MonoMethodSignature *sig;
1829 /* FIXME: Generate intermediate code instead */
1831 sig = mono_method_signature (method);
1833 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
1835 /* This is the opposite of the code in emit_prolog */
1836 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1837 ArgInfo *ainfo = cinfo->args + i;
1838 gint32 stack_offset;
1841 ins = cfg->args [i];
1843 if (sig->hasthis && (i == 0))
1844 arg_type = &mono_defaults.object_class->byval_arg;
1846 arg_type = sig->params [i - sig->hasthis];
1848 arg_type = mini_get_underlying_type (arg_type);
1850 stack_offset = ainfo->offset + ARGS_OFFSET;
1852 /* Save volatile arguments to the stack */
1853 if (ins->opcode != OP_REGVAR) {
1854 switch (ainfo->storage) {
1857 /* FIXME: big offsets */
1858 g_assert (ins->opcode == OP_REGOFFSET);
1859 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
1860 if (arg_type->byref)
1861 ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1863 switch (arg_type->type) {
1865 ia64_ldfs (code, ainfo->reg, GP_SCRATCH_REG);
1868 ia64_ldfd (code, ainfo->reg, GP_SCRATCH_REG);
1871 ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1883 if (ins->opcode == OP_REGVAR) {
1884 /* Argument allocated to (non-volatile) register */
1885 switch (ainfo->storage) {
1887 if (ins->dreg != cfg->arch.reg_in0 + ainfo->reg)
1888 ia64_mov (code, cfg->arch.reg_in0 + ainfo->reg, ins->dreg);
1891 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
1892 ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
1903 static Ia64CodegenState
1904 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, Ia64CodegenState code)
1909 /* Move return value to the target register */
1910 switch (ins->opcode) {
1912 case OP_VOIDCALL_REG:
1913 case OP_VOIDCALL_MEMBASE:
1917 case OP_CALL_MEMBASE:
1920 case OP_LCALL_MEMBASE:
1921 g_assert (ins->dreg == IA64_R8);
1925 case OP_FCALL_MEMBASE:
1926 g_assert (ins->dreg == 8);
1927 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4)
1928 ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
1932 case OP_VCALL_MEMBASE:
1935 case OP_VCALL2_MEMBASE: {
1938 cinfo = get_call_info (cfg, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
1939 storage = cinfo->ret.storage;
1941 if (storage == ArgAggregate) {
1942 MonoInst *local = (MonoInst*)cfg->arch.ret_var_addr_local;
1944 /* Load address of stack space allocated for the return value */
1945 ia64_movl (code, GP_SCRATCH_REG, local->inst_offset);
1946 ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, local->inst_basereg);
1947 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
1949 for (i = 0; i < cinfo->ret.nregs; ++i) {
1950 switch (cinfo->ret.atype) {
1951 case AggregateNormal:
1952 ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1954 case AggregateSingleHFA:
1955 ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 4, 0);
1957 case AggregateDoubleHFA:
1958 ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1961 g_assert_not_reached ();
1968 g_assert_not_reached ();
1974 #define add_patch_info(cfg,code,patch_type,data) do { \
1975 mono_add_patch_info (cfg, code.buf + code.nins - cfg->native_code, patch_type, data); \
1978 #define emit_cond_system_exception(cfg,code,exc_name,predicate) do { \
1979 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1981 add_patch_info (cfg, code, MONO_PATCH_INFO_EXC, exc_name); \
1983 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, tins->inst_true_bb); \
1984 ia64_br_cond_pred (code, (predicate), 0); \
1987 static Ia64CodegenState
1988 emit_call (MonoCompile *cfg, Ia64CodegenState code, guint32 patch_type, gconstpointer data)
1990 add_patch_info (cfg, code, patch_type, data);
1992 if ((patch_type == MONO_PATCH_INFO_ABS) || (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD)) {
1994 /* mono_arch_patch_callsite will patch this */
1995 ia64_movl (code, GP_SCRATCH_REG, 0);
1996 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
1997 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
1998 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
1999 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2002 /* Can't use a direct call since the displacement might be too small */
2003 /* mono_arch_patch_callsite will patch this */
2004 ia64_movl (code, GP_SCRATCH_REG, 0);
2005 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2006 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2012 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2015 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2020 Ia64CodegenState code;
2021 guint8 *code_start = cfg->native_code + cfg->code_len;
2022 MonoInst *last_ins = NULL;
2023 guint last_offset = 0;
2026 if (cfg->opt & MONO_OPT_LOOP) {
2030 if (cfg->verbose_level > 2)
2031 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2033 cpos = bb->max_offset;
2035 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2039 offset = code_start - cfg->native_code;
2041 ia64_codegen_init (code, code_start);
2044 if (strstr (cfg->method->name, "conv_ovf_i1") && (bb->block_num == 2))
2048 MONO_BB_FOR_EACH_INS (bb, ins) {
2049 offset = code.buf - cfg->native_code;
2051 max_len = ((int)(((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN])) + 128;
2053 while (offset + max_len + 16 > cfg->code_size) {
2054 ia64_codegen_close (code);
2056 offset = code.buf - cfg->native_code;
2058 cfg->code_size *= 2;
2059 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2060 code_start = cfg->native_code + offset;
2061 cfg->stat_code_reallocs++;
2063 ia64_codegen_init (code, code_start);
2066 mono_debug_record_line_number (cfg, ins, offset);
2068 switch (ins->opcode) {
2071 if (ia64_is_imm14 (ins->inst_c0))
2072 ia64_adds_imm (code, ins->dreg, ins->inst_c0, IA64_R0);
2074 ia64_movl (code, ins->dreg, ins->inst_c0);
2077 add_patch_info (cfg, code, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2078 ia64_movl (code, ins->dreg, 0);
2081 ia64_mov (code, ins->dreg, ins->sreg1);
2084 case OP_IA64_BR_COND: {
2086 if (ins->opcode == OP_IA64_BR_COND)
2088 if (ins->inst_target_bb->native_offset) {
2089 guint8 *pos = code.buf + code.nins;
2091 ia64_br_cond_pred (code, pred, 0);
2092 ia64_begin_bundle (code);
2093 ia64_patch (pos, cfg->native_code + ins->inst_target_bb->native_offset);
2095 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2096 ia64_br_cond_pred (code, pred, 0);
2101 ia64_begin_bundle (code);
2102 ins->inst_c0 = code.buf - cfg->native_code;
2105 case OP_RELAXED_NOP:
2107 case OP_DUMMY_STORE:
2108 case OP_NOT_REACHED:
2112 ia64_mov_to_br (code, IA64_B6, ins->sreg1);
2113 ia64_br_cond_reg (code, IA64_B6);
2117 ia64_add (code, ins->dreg, ins->sreg1, ins->sreg2);
2121 ia64_sub (code, ins->dreg, ins->sreg1, ins->sreg2);
2125 ia64_and (code, ins->dreg, ins->sreg1, ins->sreg2);
2129 ia64_or (code, ins->dreg, ins->sreg1, ins->sreg2);
2133 ia64_xor (code, ins->dreg, ins->sreg1, ins->sreg2);
2137 ia64_sub (code, ins->dreg, IA64_R0, ins->sreg1);
2141 ia64_andcm_imm (code, ins->dreg, -1, ins->sreg1);
2145 ia64_shl (code, ins->dreg, ins->sreg1, ins->sreg2);
2148 ia64_sxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2149 ia64_shr (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2152 ia64_shr (code, ins->dreg, ins->sreg1, ins->sreg2);
2155 ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2156 ia64_shr_u (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2159 ia64_shr_u (code, ins->dreg, ins->sreg1, ins->sreg2);
2162 /* p6 and p7 is set if there is signed/unsigned overflow */
2164 /* Set p8-p9 == (sreg2 > 0) */
2165 ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2167 ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2169 /* (sreg2 > 0) && (res < ins->sreg1) => signed overflow */
2170 ia64_cmp4_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2171 /* (sreg2 <= 0) && (res > ins->sreg1) => signed overflow */
2172 ia64_cmp4_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2174 /* res <u sreg1 => unsigned overflow */
2175 ia64_cmp4_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2177 /* FIXME: Predicate this since this is a side effect */
2178 ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2181 /* p6 and p7 is set if there is signed/unsigned overflow */
2183 /* Set p8-p9 == (sreg2 > 0) */
2184 ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2186 ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2188 /* (sreg2 > 0) && (res > ins->sreg1) => signed overflow */
2189 ia64_cmp4_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2190 /* (sreg2 <= 0) && (res < ins->sreg1) => signed overflow */
2191 ia64_cmp4_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2193 /* sreg1 <u sreg2 => unsigned overflow */
2194 ia64_cmp4_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2196 /* FIXME: Predicate this since this is a side effect */
2197 ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2200 /* Same as OP_IADDCC */
2201 ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2203 ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2205 ia64_cmp_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2206 ia64_cmp_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2208 ia64_cmp_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2210 ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2213 /* Same as OP_ISUBCC */
2215 ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2217 ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2219 ia64_cmp_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2220 ia64_cmp_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2222 ia64_cmp_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2224 ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2229 ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2234 ia64_and_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2238 ia64_or_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2242 ia64_xor_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2247 ia64_shl_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2251 ia64_shr_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2254 g_assert (ins->inst_imm <= 64);
2255 ia64_extr (code, ins->dreg, ins->sreg1, ins->inst_imm, 32 - ins->inst_imm);
2257 case OP_ISHR_UN_IMM:
2258 ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2259 ia64_shr_u_imm (code, ins->dreg, GP_SCRATCH_REG, ins->inst_imm);
2261 case OP_LSHR_UN_IMM:
2262 ia64_shr_u_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2265 /* Based on gcc code */
2266 ia64_setf_sig (code, FP_SCRATCH_REG, ins->sreg1);
2267 ia64_setf_sig (code, FP_SCRATCH_REG2, ins->sreg2);
2268 ia64_xmpy_l (code, FP_SCRATCH_REG, FP_SCRATCH_REG, FP_SCRATCH_REG2);
2269 ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2272 case OP_STOREI1_MEMBASE_REG:
2273 ia64_st1_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2275 case OP_STOREI2_MEMBASE_REG:
2276 ia64_st2_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2278 case OP_STOREI4_MEMBASE_REG:
2279 ia64_st4_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2281 case OP_STOREI8_MEMBASE_REG:
2282 case OP_STORE_MEMBASE_REG:
2283 if (ins->inst_offset != 0) {
2284 /* This is generated by local regalloc */
2285 if (ia64_is_imm14 (ins->inst_offset)) {
2286 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2288 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2289 ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2291 ins->inst_destbasereg = GP_SCRATCH_REG;
2293 ia64_st8_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2296 case OP_IA64_STOREI1_MEMBASE_INC_REG:
2297 ia64_st1_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 1, 0);
2299 case OP_IA64_STOREI2_MEMBASE_INC_REG:
2300 ia64_st2_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 2, 0);
2302 case OP_IA64_STOREI4_MEMBASE_INC_REG:
2303 ia64_st4_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 4, 0);
2305 case OP_IA64_STOREI8_MEMBASE_INC_REG:
2306 ia64_st8_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 8, 0);
2309 case OP_LOADU1_MEMBASE:
2310 ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2312 case OP_LOADU2_MEMBASE:
2313 ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2315 case OP_LOADU4_MEMBASE:
2316 ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2318 case OP_LOADI1_MEMBASE:
2319 ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2320 ia64_sxt1 (code, ins->dreg, ins->dreg);
2322 case OP_LOADI2_MEMBASE:
2323 ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2324 ia64_sxt2 (code, ins->dreg, ins->dreg);
2326 case OP_LOADI4_MEMBASE:
2327 ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2328 ia64_sxt4 (code, ins->dreg, ins->dreg);
2330 case OP_LOAD_MEMBASE:
2331 case OP_LOADI8_MEMBASE:
2332 if (ins->inst_offset != 0) {
2333 /* This is generated by local regalloc */
2334 if (ia64_is_imm14 (ins->inst_offset)) {
2335 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2337 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2338 ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2340 ins->inst_basereg = GP_SCRATCH_REG;
2342 ia64_ld8 (code, ins->dreg, ins->inst_basereg);
2345 case OP_IA64_LOADU1_MEMBASE_INC:
2346 ia64_ld1_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 1, 0);
2348 case OP_IA64_LOADU2_MEMBASE_INC:
2349 ia64_ld2_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 2, 0);
2351 case OP_IA64_LOADU4_MEMBASE_INC:
2352 ia64_ld4_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 4, 0);
2354 case OP_IA64_LOADI8_MEMBASE_INC:
2355 ia64_ld8_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 8, 0);
2359 ia64_sxt1 (code, ins->dreg, ins->sreg1);
2362 ia64_sxt2 (code, ins->dreg, ins->sreg1);
2365 ia64_sxt4 (code, ins->dreg, ins->sreg1);
2368 ia64_zxt1 (code, ins->dreg, ins->sreg1);
2371 ia64_zxt2 (code, ins->dreg, ins->sreg1);
2374 ia64_zxt4 (code, ins->dreg, ins->sreg1);
2377 /* Compare opcodes */
2378 case OP_IA64_CMP4_EQ:
2379 ia64_cmp4_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2381 case OP_IA64_CMP4_NE:
2382 ia64_cmp4_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2384 case OP_IA64_CMP4_LE:
2385 ia64_cmp4_le (code, 6, 7, ins->sreg1, ins->sreg2);
2387 case OP_IA64_CMP4_LT:
2388 ia64_cmp4_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2390 case OP_IA64_CMP4_GE:
2391 ia64_cmp4_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2393 case OP_IA64_CMP4_GT:
2394 ia64_cmp4_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2396 case OP_IA64_CMP4_LT_UN:
2397 ia64_cmp4_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2399 case OP_IA64_CMP4_LE_UN:
2400 ia64_cmp4_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2402 case OP_IA64_CMP4_GT_UN:
2403 ia64_cmp4_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2405 case OP_IA64_CMP4_GE_UN:
2406 ia64_cmp4_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2408 case OP_IA64_CMP_EQ:
2409 ia64_cmp_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2411 case OP_IA64_CMP_NE:
2412 ia64_cmp_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2414 case OP_IA64_CMP_LE:
2415 ia64_cmp_le (code, 6, 7, ins->sreg1, ins->sreg2);
2417 case OP_IA64_CMP_LT:
2418 ia64_cmp_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2420 case OP_IA64_CMP_GE:
2421 ia64_cmp_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2423 case OP_IA64_CMP_GT:
2424 ia64_cmp_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2426 case OP_IA64_CMP_GT_UN:
2427 ia64_cmp_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2429 case OP_IA64_CMP_LT_UN:
2430 ia64_cmp_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2432 case OP_IA64_CMP_GE_UN:
2433 ia64_cmp_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2435 case OP_IA64_CMP_LE_UN:
2436 ia64_cmp_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2438 case OP_IA64_CMP4_EQ_IMM:
2439 ia64_cmp4_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2441 case OP_IA64_CMP4_NE_IMM:
2442 ia64_cmp4_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2444 case OP_IA64_CMP4_LE_IMM:
2445 ia64_cmp4_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2447 case OP_IA64_CMP4_LT_IMM:
2448 ia64_cmp4_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2450 case OP_IA64_CMP4_GE_IMM:
2451 ia64_cmp4_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2453 case OP_IA64_CMP4_GT_IMM:
2454 ia64_cmp4_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2456 case OP_IA64_CMP4_LT_UN_IMM:
2457 ia64_cmp4_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2459 case OP_IA64_CMP4_LE_UN_IMM:
2460 ia64_cmp4_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2462 case OP_IA64_CMP4_GT_UN_IMM:
2463 ia64_cmp4_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2465 case OP_IA64_CMP4_GE_UN_IMM:
2466 ia64_cmp4_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2468 case OP_IA64_CMP_EQ_IMM:
2469 ia64_cmp_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2471 case OP_IA64_CMP_NE_IMM:
2472 ia64_cmp_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2474 case OP_IA64_CMP_LE_IMM:
2475 ia64_cmp_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2477 case OP_IA64_CMP_LT_IMM:
2478 ia64_cmp_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2480 case OP_IA64_CMP_GE_IMM:
2481 ia64_cmp_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2483 case OP_IA64_CMP_GT_IMM:
2484 ia64_cmp_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2486 case OP_IA64_CMP_GT_UN_IMM:
2487 ia64_cmp_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2489 case OP_IA64_CMP_LT_UN_IMM:
2490 ia64_cmp_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2492 case OP_IA64_CMP_GE_UN_IMM:
2493 ia64_cmp_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2495 case OP_IA64_CMP_LE_UN_IMM:
2496 ia64_cmp_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2498 case OP_IA64_FCMP_EQ:
2499 ia64_fcmp_eq_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2501 case OP_IA64_FCMP_NE:
2502 ia64_fcmp_ne_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2504 case OP_IA64_FCMP_LT:
2505 ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2507 case OP_IA64_FCMP_GT:
2508 ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2510 case OP_IA64_FCMP_LE:
2511 ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2513 case OP_IA64_FCMP_GE:
2514 ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2516 case OP_IA64_FCMP_GT_UN:
2517 ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2518 ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2520 case OP_IA64_FCMP_LT_UN:
2521 ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2522 ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2524 case OP_IA64_FCMP_GE_UN:
2525 ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2526 ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2528 case OP_IA64_FCMP_LE_UN:
2529 ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2530 ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2533 case OP_COND_EXC_IOV:
2534 case OP_COND_EXC_OV:
2535 emit_cond_system_exception (cfg, code, "OverflowException", 6);
2537 case OP_COND_EXC_IC:
2539 emit_cond_system_exception (cfg, code, "OverflowException", 7);
2541 case OP_IA64_COND_EXC:
2542 emit_cond_system_exception (cfg, code, ins->inst_p1, 6);
2545 ia64_mov_pred (code, 7, ins->dreg, IA64_R0);
2546 ia64_no_stop (code);
2547 ia64_add1_pred (code, 6, ins->dreg, IA64_R0, IA64_R0);
2549 case OP_ICONV_TO_I1:
2550 case OP_LCONV_TO_I1:
2551 /* FIXME: Is this needed ? */
2552 ia64_sxt1 (code, ins->dreg, ins->sreg1);
2554 case OP_ICONV_TO_I2:
2555 case OP_LCONV_TO_I2:
2556 /* FIXME: Is this needed ? */
2557 ia64_sxt2 (code, ins->dreg, ins->sreg1);
2559 case OP_LCONV_TO_I4:
2560 /* FIXME: Is this needed ? */
2561 ia64_sxt4 (code, ins->dreg, ins->sreg1);
2563 case OP_ICONV_TO_U1:
2564 case OP_LCONV_TO_U1:
2565 /* FIXME: Is this needed */
2566 ia64_zxt1 (code, ins->dreg, ins->sreg1);
2568 case OP_ICONV_TO_U2:
2569 case OP_LCONV_TO_U2:
2570 /* FIXME: Is this needed */
2571 ia64_zxt2 (code, ins->dreg, ins->sreg1);
2573 case OP_LCONV_TO_U4:
2574 /* FIXME: Is this needed */
2575 ia64_zxt4 (code, ins->dreg, ins->sreg1);
2577 case OP_ICONV_TO_I8:
2579 case OP_LCONV_TO_I8:
2581 ia64_sxt4 (code, ins->dreg, ins->sreg1);
2583 case OP_LCONV_TO_U8:
2585 ia64_zxt4 (code, ins->dreg, ins->sreg1);
2592 double d = *(double *)ins->inst_p0;
2594 if ((d == 0.0) && (mono_signbit (d) == 0))
2595 ia64_fmov (code, ins->dreg, 0);
2597 ia64_fmov (code, ins->dreg, 1);
2599 add_patch_info (cfg, code, MONO_PATCH_INFO_R8, ins->inst_p0);
2600 ia64_movl (code, GP_SCRATCH_REG, 0);
2601 ia64_ldfd (code, ins->dreg, GP_SCRATCH_REG);
2606 float f = *(float *)ins->inst_p0;
2608 if ((f == 0.0) && (mono_signbit (f) == 0))
2609 ia64_fmov (code, ins->dreg, 0);
2611 ia64_fmov (code, ins->dreg, 1);
2613 add_patch_info (cfg, code, MONO_PATCH_INFO_R4, ins->inst_p0);
2614 ia64_movl (code, GP_SCRATCH_REG, 0);
2615 ia64_ldfs (code, ins->dreg, GP_SCRATCH_REG);
2620 ia64_fmov (code, ins->dreg, ins->sreg1);
2622 case OP_STORER8_MEMBASE_REG:
2623 if (ins->inst_offset != 0) {
2624 /* This is generated by local regalloc */
2625 if (ia64_is_imm14 (ins->inst_offset)) {
2626 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2628 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2629 ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2631 ins->inst_destbasereg = GP_SCRATCH_REG;
2633 ia64_stfd_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2635 case OP_STORER4_MEMBASE_REG:
2636 ia64_fnorm_s_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2637 ia64_stfs_hint (code, ins->inst_destbasereg, FP_SCRATCH_REG, 0);
2639 case OP_LOADR8_MEMBASE:
2640 if (ins->inst_offset != 0) {
2641 /* This is generated by local regalloc */
2642 if (ia64_is_imm14 (ins->inst_offset)) {
2643 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2645 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2646 ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2648 ins->inst_basereg = GP_SCRATCH_REG;
2650 ia64_ldfd (code, ins->dreg, ins->inst_basereg);
2652 case OP_LOADR4_MEMBASE:
2653 ia64_ldfs (code, ins->dreg, ins->inst_basereg);
2654 ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2656 case OP_ICONV_TO_R4:
2657 case OP_LCONV_TO_R4:
2658 ia64_setf_sig (code, ins->dreg, ins->sreg1);
2659 ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2660 ia64_fnorm_s_sf (code, ins->dreg, ins->dreg, 0);
2662 case OP_ICONV_TO_R8:
2663 case OP_LCONV_TO_R8:
2664 ia64_setf_sig (code, ins->dreg, ins->sreg1);
2665 ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2666 ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2668 case OP_FCONV_TO_R4:
2669 ia64_fnorm_s_sf (code, ins->dreg, ins->sreg1, 0);
2671 case OP_FCONV_TO_I8:
2673 ia64_fcvt_fx_trunc_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2674 ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2677 ia64_fma_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2680 ia64_fms_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2683 ia64_fma_d_sf (code, ins->dreg, ins->sreg1, ins->sreg2, 0, 0);
2686 ia64_fmerge_ns (code, ins->dreg, ins->sreg1, ins->sreg1);
2690 ia64_fclass_m (code, 6, 7, ins->sreg1, 0x080);
2691 emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2693 ia64_fclass_m (code, 6, 7, ins->sreg1, 0x040);
2694 emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2695 /* Positive infinity */
2696 ia64_fclass_m (code, 6, 7, ins->sreg1, 0x021);
2697 emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2698 /* Negative infinity */
2699 ia64_fclass_m (code, 6, 7, ins->sreg1, 0x022);
2700 emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2705 /* ensure ins->sreg1 is not NULL */
2706 /* Can't use ld8 as this could be a vtype address */
2707 ia64_ld1 (code, GP_SCRATCH_REG, ins->sreg1);
2710 ia64_adds_imm (code, GP_SCRATCH_REG, cfg->sig_cookie, cfg->frame_reg);
2711 ia64_st8 (code, ins->sreg1, GP_SCRATCH_REG);
2719 call = (MonoCallInst*)ins;
2721 if (ins->flags & MONO_INST_HAS_METHOD)
2722 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2724 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2726 code = emit_move_return_value (cfg, ins, code);
2734 case OP_VOIDCALL_REG: {
2735 MonoCallInst *call = (MonoCallInst*)ins;
2740 * mono_arch_get_this_arg_from_call () needs to find the this argument in a global
2743 cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2744 out_reg = cfg->arch.reg_out0;
2745 ia64_mov (code, IA64_R10, out_reg);
2748 ia64_mov (code, IA64_R8, ins->sreg1);
2749 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, IA64_R8, 8);
2750 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2751 ia64_ld8 (code, IA64_GP, IA64_R8);
2752 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2754 code = emit_move_return_value (cfg, ins, code);
2757 case OP_FCALL_MEMBASE:
2758 case OP_LCALL_MEMBASE:
2759 case OP_VCALL_MEMBASE:
2760 case OP_VCALL2_MEMBASE:
2761 case OP_VOIDCALL_MEMBASE:
2762 case OP_CALL_MEMBASE: {
2763 MonoCallInst *call = (MonoCallInst*)ins;
2767 ia64_mov (code, IA64_R11, ins->sreg1);
2768 if (ia64_is_imm14 (ins->inst_offset))
2769 ia64_adds_imm (code, IA64_R8, ins->inst_offset, ins->sreg1);
2771 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2772 ia64_add (code, IA64_R8, GP_SCRATCH_REG, ins->sreg1);
2775 if (call->method && ins->inst_offset < 0) {
2777 * This is a possible IMT call so save the IMT method in a global
2778 * register where mono_arch_find_imt_method () and its friends can
2781 ia64_movl (code, IA64_R9, call->method);
2785 * mono_arch_find_this_arg () needs to find the this argument in a global
2788 cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2789 out_reg = cfg->arch.reg_out0;
2790 ia64_mov (code, IA64_R10, out_reg);
2792 ia64_ld8 (code, GP_SCRATCH_REG, IA64_R8);
2794 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2796 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2798 code = emit_move_return_value (cfg, ins, code);
2803 * Keep in sync with the code in emit_epilog.
2806 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2809 g_assert (!cfg->method->save_lmf);
2811 /* Load arguments into their original registers */
2812 code = emit_load_volatile_arguments (cfg, code);
2814 if (cfg->arch.stack_alloc_size) {
2815 if (cfg->arch.omit_fp) {
2816 if (ia64_is_imm14 (cfg->arch.stack_alloc_size))
2817 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
2819 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
2820 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
2824 ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
2826 ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
2827 ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
2829 add_patch_info (cfg, code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2830 ia64_movl (code, GP_SCRATCH_REG, 0);
2831 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2832 ia64_br_cond_reg (code, IA64_B6);
2837 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, mono_break);
2843 /* FIXME: Sigaltstack support */
2845 /* keep alignment */
2846 ia64_adds_imm (code, GP_SCRATCH_REG, MONO_ARCH_LOCALLOC_ALIGNMENT - 1, ins->sreg1);
2847 ia64_movl (code, GP_SCRATCH_REG2, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
2848 ia64_and (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2850 ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2852 ia64_mov (code, ins->dreg, IA64_SP);
2854 /* An area at sp is reserved by the ABI for parameter passing */
2855 abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_LOCALLOC_ALIGNMENT);
2856 if (ia64_is_adds_imm (abi_offset))
2857 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2859 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2860 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2863 if (ins->flags & MONO_INST_INIT) {
2865 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2867 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2870 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2871 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2872 ia64_br_cond_pred (code, 8, -2);
2874 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2876 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2881 case OP_LOCALLOC_IMM: {
2884 /* FIXME: Sigaltstack support */
2886 gssize size = ins->inst_imm;
2887 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
2889 if (ia64_is_adds_imm (size))
2890 ia64_adds_imm (code, GP_SCRATCH_REG, size, IA64_R0);
2892 ia64_movl (code, GP_SCRATCH_REG, size);
2894 ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2895 ia64_mov (code, ins->dreg, IA64_SP);
2897 /* An area at sp is reserved by the ABI for parameter passing */
2898 abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_FRAME_ALIGNMENT);
2899 if (ia64_is_adds_imm (abi_offset))
2900 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2902 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2903 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2906 if (ins->flags & MONO_INST_INIT) {
2908 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2910 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2913 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2914 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2915 ia64_br_cond_pred (code, 8, -2);
2917 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2919 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2925 ia64_adds_imm (code, ins->dreg, ins->inst_offset, IA64_TP);
2926 ia64_ld8 (code, ins->dreg, ins->dreg);
2929 /* Synchronization */
2930 case OP_MEMORY_BARRIER:
2933 case OP_ATOMIC_ADD_IMM_I4:
2934 g_assert (ins->inst_offset == 0);
2935 ia64_fetchadd4_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2936 ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2938 case OP_ATOMIC_ADD_IMM_I8:
2939 g_assert (ins->inst_offset == 0);
2940 ia64_fetchadd8_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2941 ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2943 case OP_ATOMIC_EXCHANGE_I4:
2944 ia64_xchg4_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2945 ia64_sxt4 (code, ins->dreg, ins->dreg);
2947 case OP_ATOMIC_EXCHANGE_I8:
2948 ia64_xchg8_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2950 case OP_ATOMIC_ADD_I4: {
2951 guint8 *label, *buf;
2953 /* From libatomic_ops */
2956 ia64_begin_bundle (code);
2957 label = code.buf + code.nins;
2958 ia64_ld4_acq (code, GP_SCRATCH_REG, ins->sreg1);
2959 ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2960 ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2961 ia64_cmpxchg4_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2962 ia64_cmp4_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2963 buf = code.buf + code.nins;
2964 ia64_br_cond_pred (code, 7, 0);
2965 ia64_begin_bundle (code);
2966 ia64_patch (buf, label);
2967 ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2970 case OP_ATOMIC_ADD_I8: {
2971 guint8 *label, *buf;
2973 /* From libatomic_ops */
2976 ia64_begin_bundle (code);
2977 label = code.buf + code.nins;
2978 ia64_ld8_acq (code, GP_SCRATCH_REG, ins->sreg1);
2979 ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2980 ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2981 ia64_cmpxchg8_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2982 ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2983 buf = code.buf + code.nins;
2984 ia64_br_cond_pred (code, 7, 0);
2985 ia64_begin_bundle (code);
2986 ia64_patch (buf, label);
2987 ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2991 /* Exception handling */
2992 case OP_CALL_HANDLER:
2994 * Using a call instruction would mess up the register stack, so
2995 * save the return address to a register and use a
2998 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2999 ia64_mov (code, IA64_R15, IA64_R0);
3000 ia64_mov_from_ip (code, GP_SCRATCH_REG);
3001 /* Add the length of OP_CALL_HANDLER */
3002 ia64_adds_imm (code, GP_SCRATCH_REG, 5 * 16, GP_SCRATCH_REG);
3003 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3004 ia64_movl (code, GP_SCRATCH_REG2, 0);
3005 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
3006 ia64_br_cond_reg (code, IA64_B6);
3008 //mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3009 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3011 case OP_START_HANDLER: {
3013 * We receive the return address in GP_SCRATCH_REG.
3015 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3018 * R15 determines our caller. It is used since it is writable using
3020 * R15 == 0 means we are called by OP_CALL_HANDLER or via resume_context ()
3021 * R15 != 0 means we are called by call_filter ().
3023 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3024 ia64_cmp_eq (code, 6, 7, IA64_R15, IA64_R0);
3026 ia64_br_cond_pred (code, 6, 6);
3029 * Called by call_filter:
3030 * Allocate a new stack frame, and set the fp register from the
3031 * value passed in by the caller.
3032 * We allocate a similar frame as is done by the prolog, so
3033 * if an exception is thrown while executing the filter, the
3034 * unwinder can unwind through the filter frame using the unwind
3035 * info for the prolog.
3037 ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3038 ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3039 ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3040 ia64_mov (code, cfg->frame_reg, IA64_R15);
3041 /* Signal to endfilter that we are called by call_filter */
3042 ia64_mov (code, GP_SCRATCH_REG, IA64_R0);
3044 /* Branch target: */
3045 if (ia64_is_imm14 (spvar->inst_offset))
3046 ia64_adds_imm (code, GP_SCRATCH_REG2, spvar->inst_offset, cfg->frame_reg);
3048 ia64_movl (code, GP_SCRATCH_REG2, spvar->inst_offset);
3049 ia64_add (code, GP_SCRATCH_REG2, cfg->frame_reg, GP_SCRATCH_REG2);
3052 /* Save the return address */
3053 ia64_st8_hint (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 0);
3054 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3059 case OP_ENDFILTER: {
3060 /* FIXME: Return the value in ENDFILTER */
3061 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3063 /* Load the return address */
3064 if (ia64_is_imm14 (spvar->inst_offset)) {
3065 ia64_adds_imm (code, GP_SCRATCH_REG, spvar->inst_offset, cfg->frame_reg);
3067 ia64_movl (code, GP_SCRATCH_REG, spvar->inst_offset);
3068 ia64_add (code, GP_SCRATCH_REG, cfg->frame_reg, GP_SCRATCH_REG);
3070 ia64_ld8_hint (code, GP_SCRATCH_REG, GP_SCRATCH_REG, 0);
3073 ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, IA64_R0);
3074 ia64_br_cond_pred (code, 7, 4);
3076 /* Called by call_filter */
3078 ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
3079 ia64_mov_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
3080 ia64_br_ret_reg (code, IA64_B0);
3082 /* Called by CALL_HANDLER */
3083 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
3084 ia64_br_cond_reg (code, IA64_B6);
3088 ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3089 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3090 (gpointer)"mono_arch_throw_exception");
3093 * This might be the last instruction in the method, so add a dummy
3094 * instruction so the unwinder will work.
3096 ia64_break_i (code, 0);
3099 ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3100 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3101 (gpointer)"mono_arch_rethrow_exception");
3103 ia64_break_i (code, 0);
3107 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3108 g_assert_not_reached ();
3111 if ((code.buf - cfg->native_code - offset) > max_len) {
3112 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3113 mono_inst_name (ins->opcode), max_len, code.buf - cfg->native_code - offset);
3114 g_assert_not_reached ();
3120 last_offset = offset;
3123 ia64_codegen_close (code);
3125 cfg->code_len = code.buf - cfg->native_code;
3129 mono_arch_register_lowlevel_calls (void)
3133 static Ia64InsType ins_types_in_template [32][3] = {
3134 {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3135 {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3136 {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3137 {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3138 {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3139 {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3142 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3143 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3144 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3145 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3146 {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3147 {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3148 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3149 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3150 {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3151 {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3152 {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3153 {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3156 {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3157 {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3158 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3159 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3162 {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3163 {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3168 static gboolean stops_in_template [32][3] = {
3169 { FALSE, FALSE, FALSE },
3170 { FALSE, FALSE, TRUE },
3171 { FALSE, TRUE, FALSE },
3172 { FALSE, TRUE, TRUE },
3173 { FALSE, FALSE, FALSE },
3174 { FALSE, FALSE, TRUE },
3175 { FALSE, FALSE, FALSE },
3176 { FALSE, FALSE, FALSE },
3178 { FALSE, FALSE, FALSE },
3179 { FALSE, FALSE, TRUE },
3180 { TRUE, FALSE, FALSE },
3181 { TRUE, FALSE, TRUE },
3182 { FALSE, FALSE, FALSE },
3183 { FALSE, FALSE, TRUE },
3184 { FALSE, FALSE, FALSE },
3185 { FALSE, FALSE, TRUE },
3187 { FALSE, FALSE, FALSE },
3188 { FALSE, FALSE, TRUE },
3189 { FALSE, FALSE, FALSE },
3190 { FALSE, FALSE, TRUE },
3191 { FALSE, FALSE, FALSE },
3192 { FALSE, FALSE, FALSE },
3193 { FALSE, FALSE, FALSE },
3194 { FALSE, FALSE, TRUE },
3196 { FALSE, FALSE, FALSE },
3197 { FALSE, FALSE, TRUE },
3198 { FALSE, FALSE, FALSE },
3199 { FALSE, FALSE, FALSE },
3200 { FALSE, FALSE, FALSE },
3201 { FALSE, FALSE, TRUE },
3202 { FALSE, FALSE, FALSE },
3203 { FALSE, FALSE, FALSE }
3206 static int last_stop_in_template [32] = {
3207 -1, 2, 1, 2, -1, 2, -1, -1,
3208 -1, 2, 0, 2, -1, 2, -1, 2,
3209 -1, 2, -1, 2, -1, -1, -1, 2,
3210 -1, 2, -1, -1, -1, 2, -1, -1
3213 static guint64 nops_for_ins_types [6] = {
3222 #define ITYPE_MATCH(itype1, itype2) (((itype1) == (itype2)) || (((itype2) == IA64_INS_TYPE_A) && (((itype1) == IA64_INS_TYPE_I) || ((itype1) == IA64_INS_TYPE_M))))
3229 #define DEBUG_INS_SCHED(a) do { a; } while (0)
3231 #define DEBUG_INS_SCHED(a)
3235 ia64_analyze_deps (Ia64CodegenState *code, int *deps_start, int *stops)
3237 int i, pos, ins_index, current_deps_start, current_ins_start, reg;
3238 guint8 *deps = code->dep_info;
3239 gboolean need_stop, no_stop;
3241 for (i = 0; i < code->nins; ++i)
3245 current_deps_start = 0;
3246 current_ins_start = 0;
3247 deps_start [ins_index] = current_ins_start;
3250 DEBUG_INS_SCHED (printf ("BEGIN.\n"));
3251 while (pos < code->dep_info_pos) {
3253 switch (deps [pos]) {
3254 case IA64_END_OF_INS:
3256 current_ins_start = pos + 2;
3257 deps_start [ins_index] = current_ins_start;
3259 DEBUG_INS_SCHED (printf ("(%d) END INS.\n", ins_index - 1));
3264 reg = deps [pos + 1];
3266 DEBUG_INS_SCHED (printf ("READ GR: %d\n", reg));
3267 for (i = current_deps_start; i < current_ins_start; i += 2)
3268 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3272 reg = code->dep_info [pos + 1];
3274 DEBUG_INS_SCHED (printf ("WRITE GR: %d\n", reg));
3275 for (i = current_deps_start; i < current_ins_start; i += 2)
3276 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3280 reg = deps [pos + 1];
3282 DEBUG_INS_SCHED (printf ("READ PR: %d\n", reg));
3283 for (i = current_deps_start; i < current_ins_start; i += 2)
3284 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3287 case IA64_READ_PR_BRANCH:
3288 reg = deps [pos + 1];
3290 /* Writes to prs by non-float instructions are visible to branches */
3291 DEBUG_INS_SCHED (printf ("READ PR BRANCH: %d\n", reg));
3292 for (i = current_deps_start; i < current_ins_start; i += 2)
3293 if (deps [i] == IA64_WRITE_PR_FLOAT && deps [i + 1] == reg)
3297 reg = code->dep_info [pos + 1];
3299 DEBUG_INS_SCHED (printf ("WRITE PR: %d\n", reg));
3300 for (i = current_deps_start; i < current_ins_start; i += 2)
3301 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3304 case IA64_WRITE_PR_FLOAT:
3305 reg = code->dep_info [pos + 1];
3307 DEBUG_INS_SCHED (printf ("WRITE PR FP: %d\n", reg));
3308 for (i = current_deps_start; i < current_ins_start; i += 2)
3309 if (((deps [i] == IA64_WRITE_GR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3313 reg = deps [pos + 1];
3315 DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3316 for (i = current_deps_start; i < current_ins_start; i += 2)
3317 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3321 reg = code->dep_info [pos + 1];
3323 DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3324 for (i = current_deps_start; i < current_ins_start; i += 2)
3325 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3328 case IA64_READ_BR_BRANCH:
3329 reg = deps [pos + 1];
3331 /* Writes to brs are visible to branches */
3332 DEBUG_INS_SCHED (printf ("READ BR BRACH: %d\n", reg));
3335 reg = deps [pos + 1];
3337 DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3338 for (i = current_deps_start; i < current_ins_start; i += 2)
3339 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3343 reg = code->dep_info [pos + 1];
3345 DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3346 for (i = current_deps_start; i < current_ins_start; i += 2)
3347 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3351 reg = deps [pos + 1];
3353 DEBUG_INS_SCHED (printf ("READ AR: %d\n", reg));
3354 for (i = current_deps_start; i < current_ins_start; i += 2)
3355 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3359 reg = code->dep_info [pos + 1];
3361 DEBUG_INS_SCHED (printf ("WRITE AR: %d\n", reg));
3362 for (i = current_deps_start; i < current_ins_start; i += 2)
3363 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3368 * Explicitly indicate that a stop is not required. Useful for
3369 * example when two predicated instructions with negated predicates
3370 * write the same registers.
3375 g_assert_not_reached ();
3379 if (need_stop && !no_stop) {
3380 g_assert (ins_index > 0);
3381 stops [ins_index - 1] = 1;
3383 DEBUG_INS_SCHED (printf ("STOP\n"));
3384 current_deps_start = current_ins_start;
3386 /* Skip remaining deps for this instruction */
3387 while (deps [pos] != IA64_END_OF_INS)
3392 if (code->nins > 0) {
3393 /* No dependency info for the last instruction */
3394 stops [code->nins - 1] = 1;
3397 deps_start [code->nins] = code->dep_info_pos;
3401 ia64_real_emit_bundle (Ia64CodegenState *code, int *deps_start, int *stops, int n, guint64 template, guint64 ins1, guint64 ins2, guint64 ins3, guint8 nops)
3403 int stop_pos, i, deps_to_shift, dep_shift;
3405 g_assert (n <= code->nins);
3407 // if (n > 1) printf ("FOUND: %ld.\n", template);
3409 ia64_emit_bundle_template (code, template, ins1, ins2, ins3);
3411 stop_pos = last_stop_in_template [template] + 1;
3415 /* Compute the number of 'real' instructions before the stop */
3416 deps_to_shift = stop_pos;
3417 if (stop_pos >= 3 && (nops & (1 << 2)))
3419 if (stop_pos >= 2 && (nops & (1 << 1)))
3421 if (stop_pos >= 1 && (nops & (1 << 0)))
3425 * We have to keep some dependencies whose instructions have been shifted
3426 * out of the buffer. So nullify the end_of_ins markers in the dependency
3429 for (i = deps_start [deps_to_shift]; i < deps_start [n]; i += 2)
3430 if (code->dep_info [i] == IA64_END_OF_INS)
3431 code->dep_info [i] = IA64_NONE;
3433 g_assert (deps_start [deps_to_shift] <= code->dep_info_pos);
3434 memcpy (code->dep_info, &code->dep_info [deps_start [deps_to_shift]], code->dep_info_pos - deps_start [deps_to_shift]);
3435 code->dep_info_pos = code->dep_info_pos - deps_start [deps_to_shift];
3437 dep_shift = deps_start [deps_to_shift];
3438 for (i = 0; i < code->nins + 1 - n; ++i)
3439 deps_start [i] = deps_start [n + i] - dep_shift;
3441 /* Determine the exact positions of instructions with unwind ops */
3442 if (code->unw_op_count) {
3444 int curr_ins, curr_ins_pos;
3447 curr_ins_pos = ((code->buf - code->region_start - 16) / 16) * 3;
3448 for (i = 0; i < 3; ++i) {
3449 if (! (nops & (1 << i))) {
3450 ins_pos [curr_ins] = curr_ins_pos + i;
3455 for (i = code->unw_op_pos; i < code->unw_op_count; ++i) {
3456 if (code->unw_ops_pos [i] < n) {
3457 code->unw_ops [i].when = ins_pos [code->unw_ops_pos [i]];
3458 //printf ("UNW-OP: %d -> %d\n", code->unw_ops_pos [i], code->unw_ops [i].when);
3461 if (code->unw_op_pos < code->unw_op_count)
3462 code->unw_op_pos += n;
3465 if (n == code->nins) {
3470 memcpy (&code->instructions [0], &code->instructions [n], (code->nins - n) * sizeof (guint64));
3471 memcpy (&code->itypes [0], &code->itypes [n], (code->nins - n) * sizeof (int));
3472 memcpy (&stops [0], &stops [n], (code->nins - n) * sizeof (int));
3478 ia64_emit_bundle (Ia64CodegenState *code, gboolean flush)
3480 int i, ins_type, template, nins_to_emit;
3481 int deps_start [16];
3486 * We implement a simple scheduler which tries to put three instructions
3487 * per bundle, then two, then one.
3489 ia64_analyze_deps (code, deps_start, stops);
3491 if ((code->nins >= 3) && !code->one_ins_per_bundle) {
3492 /* Find a suitable template */
3493 for (template = 0; template < 32; ++template) {
3494 if (stops_in_template [template][0] != stops [0] ||
3495 stops_in_template [template][1] != stops [1] ||
3496 stops_in_template [template][2] != stops [2])
3500 for (i = 0; i < 3; ++i) {
3501 ins_type = ins_types_in_template [template][i];
3502 switch (code->itypes [i]) {
3503 case IA64_INS_TYPE_A:
3504 found &= (ins_type == IA64_INS_TYPE_I) || (ins_type == IA64_INS_TYPE_M);
3507 found &= (ins_type == code->itypes [i]);
3513 found = debug_ins_sched ();
3516 ia64_real_emit_bundle (code, deps_start, stops, 3, template, code->instructions [0], code->instructions [1], code->instructions [2], 0);
3522 if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3523 /* Wait for more instructions */
3526 /* If it didn't work out, try putting two instructions into one bundle */
3527 if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3528 /* Try a nop at the end */
3529 for (template = 0; template < 32; ++template) {
3530 if (stops_in_template [template][0] != stops [0] ||
3531 ((stops_in_template [template][1] != stops [1]) &&
3532 (stops_in_template [template][2] != stops [1])))
3536 if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3537 !ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [1]))
3540 if (!debug_ins_sched ())
3543 ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], code->instructions [1], nops_for_ins_types [ins_types_in_template [template][2]], 1 << 2);
3548 if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3549 /* Wait for more instructions */
3552 if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3553 /* Try a nop in the middle */
3554 for (template = 0; template < 32; ++template) {
3555 if (((stops_in_template [template][0] != stops [0]) &&
3556 (stops_in_template [template][1] != stops [0])) ||
3557 stops_in_template [template][2] != stops [1])
3560 if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3561 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3564 if (!debug_ins_sched ())
3567 ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], nops_for_ins_types [ins_types_in_template [template][1]], code->instructions [1], 1 << 1);
3572 if ((code->nins >= 2) && flush && !code->one_ins_per_bundle) {
3573 /* Try a nop at the beginning */
3574 for (template = 0; template < 32; ++template) {
3575 if ((stops_in_template [template][1] != stops [0]) ||
3576 (stops_in_template [template][2] != stops [1]))
3579 if (!ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [0]) ||
3580 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3583 if (!debug_ins_sched ())
3586 ia64_real_emit_bundle (code, deps_start, stops, 2, template, nops_for_ins_types [ins_types_in_template [template][0]], code->instructions [0], code->instructions [1], 1 << 0);
3591 if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3592 /* Wait for more instructions */
3596 nins_to_emit = code->nins;
3600 while (nins_to_emit > 0) {
3601 if (!debug_ins_sched ())
3603 switch (code->itypes [0]) {
3604 case IA64_INS_TYPE_A:
3606 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3608 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3610 case IA64_INS_TYPE_I:
3612 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3614 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3616 case IA64_INS_TYPE_M:
3618 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3620 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3622 case IA64_INS_TYPE_B:
3624 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIBS, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3626 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIB, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3628 case IA64_INS_TYPE_F:
3630 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3632 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFI, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3634 case IA64_INS_TYPE_LX:
3635 if (stops [0] || stops [1])
3636 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLXS, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3638 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLX, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3642 g_assert_not_reached ();
3648 unw_dyn_region_info_t*
3649 mono_ia64_create_unwind_region (Ia64CodegenState *code)
3651 unw_dyn_region_info_t *r;
3653 g_assert (code->nins == 0);
3654 r = g_malloc0 (_U_dyn_region_info_size (code->unw_op_count));
3655 memcpy (&r->op, &code->unw_ops, sizeof (unw_dyn_op_t) * code->unw_op_count);
3656 r->op_count = code->unw_op_count;
3657 r->insn_count = ((code->buf - code->region_start) >> 4) * 3;
3658 code->unw_op_count = 0;
3659 code->unw_op_pos = 0;
3660 code->region_start = code->buf;
3666 ia64_patch (unsigned char* code, gpointer target)
3669 guint64 instructions [3];
3670 guint8 gen_buf [16];
3671 Ia64CodegenState gen;
3676 * code encodes both the position inside the buffer and code.nins when
3677 * the instruction was emitted.
3679 ins_to_skip = (guint64)code % 16;
3680 code = (unsigned char*)((guint64)code & ~15);
3683 * Search for the first instruction which is 'patchable', skipping
3684 * ins_to_skip instructions.
3689 template = ia64_bundle_template (code);
3690 instructions [0] = ia64_bundle_ins1 (code);
3691 instructions [1] = ia64_bundle_ins2 (code);
3692 instructions [2] = ia64_bundle_ins3 (code);
3694 ia64_codegen_init (gen, gen_buf);
3697 for (i = 0; i < 3; ++i) {
3698 guint64 ins = instructions [i];
3699 int opcode = ia64_ins_opcode (ins);
3701 if (ins == nops_for_ins_types [ins_types_in_template [template][i]])
3709 switch (ins_types_in_template [template][i]) {
3710 case IA64_INS_TYPE_A:
3711 case IA64_INS_TYPE_M:
3712 if ((opcode == 8) && (ia64_ins_x2a (ins) == 2) && (ia64_ins_ve (ins) == 0)) {
3714 ia64_adds_imm_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), (guint64)target, ia64_ins_r3 (ins));
3715 instructions [i] = gen.instructions [0];
3721 case IA64_INS_TYPE_B:
3722 if ((opcode == 4) && (ia64_ins_btype (ins) == 0)) {
3724 gint64 disp = ((guint8*)target - code) >> 4;
3727 ia64_br_cond_hint_pred (gen, ia64_ins_qp (ins), disp, 0, 0, 0);
3729 instructions [i] = gen.instructions [0];
3732 else if (opcode == 5) {
3734 gint64 disp = ((guint8*)target - code) >> 4;
3737 ia64_br_call_hint_pred (gen, ia64_ins_qp (ins), ia64_ins_b1 (ins), disp, 0, 0, 0);
3738 instructions [i] = gen.instructions [0];
3744 case IA64_INS_TYPE_LX:
3748 if ((opcode == 6) && (ia64_ins_vc (ins) == 0)) {
3750 ia64_movl_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), target);
3751 instructions [1] = gen.instructions [0];
3752 instructions [2] = gen.instructions [1];
3765 ia64_codegen_init (gen, code);
3766 ia64_emit_bundle_template (&gen, template, instructions [0], instructions [1], instructions [2]);
3776 mono_arch_patch_code (MonoCompile *cfg, MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3778 MonoJumpInfo *patch_info;
3780 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3781 unsigned char *ip = patch_info->ip.i + code;
3782 const unsigned char *target;
3784 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3786 if (patch_info->type == MONO_PATCH_INFO_NONE)
3788 if (mono_compile_aot) {
3792 ia64_patch (ip, (gpointer)target);
3797 mono_arch_emit_prolog (MonoCompile *cfg)
3799 MonoMethod *method = cfg->method;
3800 MonoMethodSignature *sig;
3802 int alloc_size, pos, i;
3803 Ia64CodegenState code;
3806 sig = mono_method_signature (method);
3809 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
3811 cfg->code_size = MAX (cfg->header->code_size * 4, 512);
3813 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3814 cfg->code_size += 1024;
3815 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3816 cfg->code_size += 1024;
3818 cfg->native_code = g_malloc (cfg->code_size);
3820 ia64_codegen_init (code, cfg->native_code);
3822 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
3823 if (cfg->param_area)
3824 alloc_size += cfg->param_area;
3828 alloc_size = ALIGN_TO (alloc_size, MONO_ARCH_FRAME_ALIGNMENT);
3830 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
3831 /* Force sp to be saved/restored */
3832 alloc_size += MONO_ARCH_FRAME_ALIGNMENT;
3834 cfg->arch.stack_alloc_size = alloc_size;
3838 if (method->save_lmf) {
3839 /* No LMF on IA64 */
3844 ia64_unw_save_reg (code, UNW_IA64_AR_PFS, UNW_IA64_GR + cfg->arch.reg_saved_ar_pfs);
3845 ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3846 ia64_unw_save_reg (code, UNW_IA64_RP, UNW_IA64_GR + cfg->arch.reg_saved_b0);
3847 ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3849 if ((alloc_size || cinfo->stack_usage) && !cfg->arch.omit_fp) {
3850 ia64_unw_save_reg (code, UNW_IA64_SP, UNW_IA64_GR + cfg->arch.reg_saved_sp);
3851 ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3852 if (cfg->frame_reg != cfg->arch.reg_saved_sp)
3853 ia64_mov (code, cfg->frame_reg, IA64_SP);
3857 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3858 int pagesize = getpagesize ();
3860 if (alloc_size >= pagesize) {
3861 gint32 remaining_size = alloc_size;
3863 /* Generate stack touching code */
3864 ia64_mov (code, GP_SCRATCH_REG, IA64_SP);
3865 while (remaining_size >= pagesize) {
3866 ia64_movl (code, GP_SCRATCH_REG2, pagesize);
3867 ia64_sub (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3868 ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
3869 remaining_size -= pagesize;
3873 if (ia64_is_imm14 (-alloc_size)) {
3874 if (cfg->arch.omit_fp)
3875 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3876 ia64_adds_imm (code, IA64_SP, (-alloc_size), IA64_SP);
3879 ia64_movl (code, GP_SCRATCH_REG, -alloc_size);
3880 if (cfg->arch.omit_fp)
3881 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3882 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
3886 ia64_begin_bundle (code);
3888 /* Initialize unwind info */
3889 cfg->arch.r_pro = mono_ia64_create_unwind_region (&code);
3891 if (sig->ret->type != MONO_TYPE_VOID) {
3892 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
3893 /* Save volatile arguments to the stack */
3898 /* Keep this in sync with emit_load_volatile_arguments */
3899 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3900 ArgInfo *ainfo = cinfo->args + i;
3901 gint32 stack_offset;
3904 inst = cfg->args [i];
3906 if (sig->hasthis && (i == 0))
3907 arg_type = &mono_defaults.object_class->byval_arg;
3909 arg_type = sig->params [i - sig->hasthis];
3911 arg_type = mini_get_underlying_type (arg_type);
3913 stack_offset = ainfo->offset + ARGS_OFFSET;
3916 * FIXME: Native code might pass non register sized integers
3917 * without initializing the upper bits.
3919 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED && !arg_type->byref && ainfo->storage == ArgInIReg) {
3920 int reg = cfg->arch.reg_in0 + ainfo->reg;
3922 switch (mono_type_to_load_membase (cfg, arg_type)) {
3923 case OP_LOADI1_MEMBASE:
3924 ia64_sxt1 (code, reg, reg);
3926 case OP_LOADU1_MEMBASE:
3927 ia64_zxt1 (code, reg, reg);
3929 case OP_LOADI2_MEMBASE:
3930 ia64_sxt2 (code, reg, reg);
3932 case OP_LOADU2_MEMBASE:
3933 ia64_zxt2 (code, reg, reg);
3940 /* Save volatile arguments to the stack */
3941 if (inst->opcode != OP_REGVAR) {
3942 switch (ainfo->storage) {
3945 case ArgInFloatRegR4:
3946 g_assert (inst->opcode == OP_REGOFFSET);
3947 if (ia64_is_adds_imm (inst->inst_offset))
3948 ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3950 ia64_movl (code, GP_SCRATCH_REG2, inst->inst_offset);
3951 ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3953 if (arg_type->byref)
3954 ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3956 switch (arg_type->type) {
3958 ia64_stfs_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3961 ia64_stfd_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3964 ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3972 if (ainfo->nslots != ainfo->nregs)
3975 g_assert (inst->opcode == OP_REGOFFSET);
3976 ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3977 for (i = 0; i < ainfo->nregs; ++i) {
3978 switch (ainfo->atype) {
3979 case AggregateNormal:
3980 ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg + i, sizeof (gpointer), 0);
3982 case AggregateSingleHFA:
3983 ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, 4, 0);
3985 case AggregateDoubleHFA:
3986 ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, sizeof (gpointer), 0);
3994 g_assert_not_reached ();
3998 if (inst->opcode == OP_REGVAR) {
3999 /* Argument allocated to (non-volatile) register */
4000 switch (ainfo->storage) {
4002 if (inst->dreg != cfg->arch.reg_in0 + ainfo->reg)
4003 ia64_mov (code, inst->dreg, cfg->arch.reg_in0 + ainfo->reg);
4006 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
4007 ia64_ld8 (code, inst->dreg, GP_SCRATCH_REG);
4015 if (method->save_lmf) {
4016 /* No LMF on IA64 */
4019 ia64_codegen_close (code);
4021 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4022 code.buf = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code.buf, TRUE);
4024 cfg->code_len = code.buf - cfg->native_code;
4026 g_assert (cfg->code_len < cfg->code_size);
4028 cfg->arch.prolog_end_offset = cfg->code_len;
4034 mono_arch_emit_epilog (MonoCompile *cfg)
4036 MonoMethod *method = cfg->method;
4038 int max_epilog_size = 16 * 4;
4039 Ia64CodegenState code;
4044 if (mono_jit_trace_calls != NULL)
4045 max_epilog_size += 1024;
4047 cfg->arch.epilog_begin_offset = cfg->code_len;
4049 while (cfg->code_len + max_epilog_size > cfg->code_size) {
4050 cfg->code_size *= 2;
4051 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4052 cfg->stat_code_reallocs++;
4055 /* FIXME: Emit unwind info */
4057 buf = cfg->native_code + cfg->code_len;
4059 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4060 buf = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, buf, TRUE);
4062 ia64_codegen_init (code, buf);
4064 /* the code restoring the registers must be kept in sync with OP_JMP */
4067 if (method->save_lmf) {
4068 /* No LMF on IA64 */
4071 /* Load returned vtypes into registers if needed */
4072 cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
4073 ainfo = &cinfo->ret;
4074 switch (ainfo->storage) {
4076 if (ainfo->nslots != ainfo->nregs)
4079 g_assert (cfg->ret->opcode == OP_REGOFFSET);
4080 ia64_adds_imm (code, GP_SCRATCH_REG, cfg->ret->inst_offset, cfg->ret->inst_basereg);
4081 for (i = 0; i < ainfo->nregs; ++i) {
4082 switch (ainfo->atype) {
4083 case AggregateNormal:
4084 ia64_ld8_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4086 case AggregateSingleHFA:
4087 ia64_ldfs_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, 4, 0);
4089 case AggregateDoubleHFA:
4090 ia64_ldfd_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4093 g_assert_not_reached ();
4101 ia64_begin_bundle (code);
4103 code.region_start = cfg->native_code;
4105 /* Label the unwind state at the start of the exception throwing region */
4106 //ia64_unw_label_state (code, 1234);
4108 if (cfg->arch.stack_alloc_size) {
4109 if (cfg->arch.omit_fp) {
4110 if (ia64_is_imm14 (cfg->arch.stack_alloc_size)) {
4111 ia64_unw_pop_frames (code, 1);
4112 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
4114 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
4115 ia64_unw_pop_frames (code, 1);
4116 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
4120 ia64_unw_pop_frames (code, 1);
4121 ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
4124 ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
4125 ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
4126 ia64_br_ret_reg (code, IA64_B0);
4128 ia64_codegen_close (code);
4130 cfg->arch.r_epilog = mono_ia64_create_unwind_region (&code);
4131 cfg->arch.r_pro->next = cfg->arch.r_epilog;
4133 cfg->code_len = code.buf - cfg->native_code;
4135 g_assert (cfg->code_len < cfg->code_size);
4139 mono_arch_emit_exceptions (MonoCompile *cfg)
4141 MonoJumpInfo *patch_info;
4143 Ia64CodegenState code;
4144 gboolean empty = TRUE;
4145 //unw_dyn_region_info_t *r_exceptions;
4146 MonoClass *exc_classes [16];
4147 guint8 *exc_throw_start [16], *exc_throw_end [16];
4148 guint32 code_size = 0;
4150 /* Compute needed space */
4151 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4152 if (patch_info->type == MONO_PATCH_INFO_EXC)
4154 if (patch_info->type == MONO_PATCH_INFO_R8)
4155 code_size += 8 + 7; /* sizeof (double) + alignment */
4156 if (patch_info->type == MONO_PATCH_INFO_R4)
4157 code_size += 4 + 7; /* sizeof (float) + alignment */
4163 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4164 cfg->code_size *= 2;
4165 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4166 cfg->stat_code_reallocs++;
4169 ia64_codegen_init (code, cfg->native_code + cfg->code_len);
4171 /* The unwind state here is the same as before the epilog */
4172 //ia64_unw_copy_state (code, 1234);
4174 /* add code to raise exceptions */
4175 /* FIXME: Optimize this */
4177 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4178 switch (patch_info->type) {
4179 case MONO_PATCH_INFO_EXC: {
4180 MonoClass *exc_class;
4183 guint64 exc_token_index;
4185 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4186 g_assert (exc_class);
4187 exc_token_index = mono_metadata_token_index (exc_class->type_token);
4188 throw_ip = cfg->native_code + patch_info->ip.i;
4190 ia64_begin_bundle (code);
4192 ia64_patch (cfg->native_code + patch_info->ip.i, code.buf);
4194 /* Find a throw sequence for the same exception class */
4195 for (i = 0; i < nthrows; ++i)
4196 if (exc_classes [i] == exc_class)
4200 gint64 offset = exc_throw_end [i] - 16 - throw_ip;
4202 if (ia64_is_adds_imm (offset))
4203 ia64_adds_imm (code, cfg->arch.reg_out0 + 1, offset, IA64_R0);
4205 ia64_movl (code, cfg->arch.reg_out0 + 1, offset);
4207 buf = code.buf + code.nins;
4208 ia64_br_cond_pred (code, 0, 0);
4209 ia64_begin_bundle (code);
4210 ia64_patch (buf, exc_throw_start [i]);
4212 patch_info->type = MONO_PATCH_INFO_NONE;
4217 ia64_movl (code, cfg->arch.reg_out0 + 1, 0);
4219 ia64_begin_bundle (code);
4222 exc_classes [nthrows] = exc_class;
4223 exc_throw_start [nthrows] = code.buf;
4227 if (ia64_is_adds_imm (exc_token_index))
4228 ia64_adds_imm (code, cfg->arch.reg_out0 + 0, exc_token_index, IA64_R0);
4230 ia64_movl (code, cfg->arch.reg_out0 + 0, exc_token_index);
4232 patch_info->data.name = "mono_arch_throw_corlib_exception";
4233 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4234 patch_info->ip.i = code.buf + code.nins - cfg->native_code;
4237 ia64_movl (code, GP_SCRATCH_REG, 0);
4238 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
4239 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
4240 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
4242 ia64_br_call_reg (code, IA64_B0, IA64_B6);
4244 /* Patch up the throw offset */
4245 ia64_begin_bundle (code);
4247 ia64_patch (buf, (gpointer)(code.buf - 16 - throw_ip));
4250 exc_throw_end [nthrows] = code.buf;
4264 /* The unwinder needs this to work */
4265 ia64_break_i (code, 0);
4267 ia64_codegen_close (code);
4270 //r_exceptions = mono_ia64_create_unwind_region (&code);
4271 //cfg->arch.r_epilog = r_exceptions;
4273 cfg->code_len = code.buf - cfg->native_code;
4275 g_assert (cfg->code_len < cfg->code_size);
4279 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4281 Ia64CodegenState code;
4282 CallInfo *cinfo = NULL;
4283 MonoMethodSignature *sig;
4285 int i, n, stack_area = 0;
4287 ia64_codegen_init (code, p);
4289 /* Keep this in sync with mono_arch_get_argument_info */
4291 if (enable_arguments) {
4292 /* Allocate a new area on the stack and save arguments there */
4293 sig = mono_method_signature (cfg->method);
4295 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4297 n = sig->param_count + sig->hasthis;
4299 stack_area = ALIGN_TO (n * 8, 16);
4302 ia64_movl (code, GP_SCRATCH_REG, stack_area);
4304 ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4306 /* FIXME: Allocate out registers */
4308 ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_SP);
4310 /* Required by the ABI */
4311 ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4313 add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4314 ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4316 /* Save arguments to the stack */
4317 for (i = 0; i < n; ++i) {
4318 ins = cfg->args [i];
4320 if (ins->opcode == OP_REGVAR) {
4321 ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4322 ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4323 ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
4326 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
4327 ia64_add (code, GP_SCRATCH_REG, ins->inst_basereg, GP_SCRATCH_REG);
4328 ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
4329 ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4330 ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4331 ia64_st8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG2);
4336 ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4339 ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4341 add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4342 ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4344 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4346 if (enable_arguments && stack_area) {
4347 ia64_movl (code, GP_SCRATCH_REG, stack_area);
4349 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4351 ia64_adds_imm (code, IA64_SP, 16, IA64_SP);
4354 ia64_codegen_close (code);
4360 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
4362 Ia64CodegenState code;
4363 CallInfo *cinfo = NULL;
4364 MonoMethod *method = cfg->method;
4365 MonoMethodSignature *sig = mono_method_signature (cfg->method);
4367 ia64_codegen_init (code, p);
4369 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4371 /* Save return value + pass it to func */
4372 switch (cinfo->ret.storage) {
4376 ia64_mov (code, cfg->arch.reg_saved_return_val, cinfo->ret.reg);
4377 ia64_mov (code, cfg->arch.reg_out0 + 1, cinfo->ret.reg);
4380 ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4381 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4382 ia64_stfd_hint (code, GP_SCRATCH_REG, cinfo->ret.reg, 0);
4383 ia64_fmov (code, 8 + 1, cinfo->ret.reg);
4385 case ArgValuetypeAddrInIReg:
4386 ia64_mov (code, cfg->arch.reg_out0 + 1, cfg->arch.reg_in0 + cinfo->ret.reg);
4395 add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, method);
4396 ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4397 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4399 /* Restore return value */
4400 switch (cinfo->ret.storage) {
4404 ia64_mov (code, cinfo->ret.reg, cfg->arch.reg_saved_return_val);
4407 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4408 ia64_ldfd (code, cinfo->ret.reg, GP_SCRATCH_REG);
4410 case ArgValuetypeAddrInIReg:
4418 ia64_codegen_close (code);
4424 mono_arch_save_unwind_info (MonoCompile *cfg)
4428 /* FIXME: Unregister this for dynamic methods */
4430 di = g_malloc0 (sizeof (unw_dyn_info_t));
4431 di->start_ip = (unw_word_t) cfg->native_code;
4432 di->end_ip = (unw_word_t) cfg->native_code + cfg->code_len;
4434 di->format = UNW_INFO_FORMAT_DYNAMIC;
4435 di->u.pi.name_ptr = (unw_word_t)mono_method_full_name (cfg->method, TRUE);
4436 di->u.pi.regions = cfg->arch.r_pro;
4438 _U_dyn_register (di);
4442 unw_dyn_region_info_t *region = di->u.pi.regions;
4444 printf ("Unwind info for method %s:\n", mono_method_full_name (cfg->method, TRUE));
4446 printf (" [Region: %d]\n", region->insn_count);
4447 region = region->next;
4454 mono_arch_flush_icache (guint8 *code, gint size)
4456 guint8* p = (guint8*)((guint64)code & ~(0x3f));
4457 guint8* end = (guint8*)((guint64)code + size);
4459 #ifdef __INTEL_COMPILER
4460 /* icc doesn't define an fc.i instrinsic, but fc==fc.i on itanium 2 */
4467 __asm__ __volatile__ ("fc.i %0"::"r"(p));
4468 /* FIXME: This could be increased to 128 on some cpus */
4475 mono_arch_flush_register_windows (void)
4477 /* Not needed because of libunwind */
4481 mono_arch_is_inst_imm (gint64 imm)
4483 /* The lowering pass will take care of it */
4489 * Determine whenever the trap whose info is in SIGINFO is caused by
4493 mono_arch_is_int_overflow (void *sigctx, void *info)
4495 /* Division is emulated with explicit overflow checks */
4500 mono_arch_get_patch_offset (guint8 *code)
4508 mono_arch_get_delegate_method_ptr_addr (guint8* code, mgreg_t *regs)
4516 mono_arch_finish_init (void)
4521 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4526 * LOCKING: called with the domain lock held
4529 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
4530 gpointer fail_tramp)
4534 guint8 *start, *buf;
4535 Ia64CodegenState code;
4538 buf = g_malloc0 (size);
4539 ia64_codegen_init (code, buf);
4541 /* IA64_R9 contains the IMT method */
4543 for (i = 0; i < count; ++i) {
4544 MonoIMTCheckItem *item = imt_entries [i];
4545 ia64_begin_bundle (code);
4546 item->code_target = (guint8*)code.buf + code.nins;
4547 if (item->is_equals) {
4548 gboolean fail_case = !item->check_target_idx && fail_tramp;
4550 if (item->check_target_idx || fail_case) {
4551 if (!item->compare_done || fail_case) {
4552 ia64_movl (code, GP_SCRATCH_REG, item->key);
4553 ia64_cmp_eq (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4555 item->jmp_code = (guint8*)code.buf + code.nins;
4556 ia64_br_cond_pred (code, 7, 0);
4558 if (item->has_target_code) {
4559 ia64_movl (code, GP_SCRATCH_REG, item->value.target_code);
4561 ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4562 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4564 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4565 ia64_br_cond_reg (code, IA64_B6);
4568 ia64_begin_bundle (code);
4569 ia64_patch (item->jmp_code, (guint8*)code.buf + code.nins);
4570 ia64_movl (code, GP_SCRATCH_REG, fail_tramp);
4571 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4572 ia64_br_cond_reg (code, IA64_B6);
4573 item->jmp_code = NULL;
4576 /* enable the commented code to assert on wrong method */
4577 #if ENABLE_WRONG_METHOD_CHECK
4578 g_assert_not_reached ();
4580 ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4581 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4582 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4583 ia64_br_cond_reg (code, IA64_B6);
4584 #if ENABLE_WRONG_METHOD_CHECK
4585 g_assert_not_reached ();
4589 ia64_movl (code, GP_SCRATCH_REG, item->key);
4590 ia64_cmp_geu (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4591 item->jmp_code = (guint8*)code.buf + code.nins;
4592 ia64_br_cond_pred (code, 6, 0);
4595 /* patch the branches to get to the target items */
4596 for (i = 0; i < count; ++i) {
4597 MonoIMTCheckItem *item = imt_entries [i];
4598 if (item->jmp_code) {
4599 if (item->check_target_idx) {
4600 ia64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
4605 ia64_codegen_close (code);
4606 g_assert (code.buf - buf <= size);
4608 size = code.buf - buf;
4610 start = mono_method_alloc_generic_virtual_thunk (domain, size + 16);
4611 start = (gpointer)ALIGN_TO (start, 16);
4613 start = mono_domain_code_reserve (domain, size);
4615 memcpy (start, buf, size);
4617 mono_arch_flush_icache (start, size);
4619 mono_stats.imt_thunks_size += size;
4621 mono_tramp_info_register (mono_tramp_info_create (NULL, start, size, NULL, NULL), domain);
4627 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
4629 return (MonoMethod*)regs [IA64_R9];
4633 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
4635 return (gpointer)regs [IA64_R10];
4639 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
4645 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
4651 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4653 MonoInst *ins = NULL;
4655 if (cmethod->klass->image == mono_defaults.corlib &&
4656 (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
4657 (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
4660 * We don't use the generic version in mini_emit_inst_for_method () since we
4661 * ia64 has atomic_add_imm opcodes.
4663 if (strcmp (cmethod->name, "Increment") == 0) {
4666 if (fsig->params [0]->type == MONO_TYPE_I4)
4667 opcode = OP_ATOMIC_ADD_IMM_I4;
4668 else if (fsig->params [0]->type == MONO_TYPE_I8)
4669 opcode = OP_ATOMIC_ADD_IMM_I8;
4671 g_assert_not_reached ();
4672 MONO_INST_NEW (cfg, ins, opcode);
4673 ins->dreg = mono_alloc_preg (cfg);
4675 ins->inst_basereg = args [0]->dreg;
4676 ins->inst_offset = 0;
4677 MONO_ADD_INS (cfg->cbb, ins);
4678 } else if (strcmp (cmethod->name, "Decrement") == 0) {
4681 if (fsig->params [0]->type == MONO_TYPE_I4)
4682 opcode = OP_ATOMIC_ADD_IMM_I4;
4683 else if (fsig->params [0]->type == MONO_TYPE_I8)
4684 opcode = OP_ATOMIC_ADD_IMM_I8;
4686 g_assert_not_reached ();
4687 MONO_INST_NEW (cfg, ins, opcode);
4688 ins->dreg = mono_alloc_preg (cfg);
4690 ins->inst_basereg = args [0]->dreg;
4691 ins->inst_offset = 0;
4692 MONO_ADD_INS (cfg->cbb, ins);
4693 } else if (strcmp (cmethod->name, "Add") == 0) {
4695 gboolean is_imm = FALSE;
4698 if ((args [1]->opcode == OP_ICONST) || (args [1]->opcode == OP_I8CONST)) {
4699 imm = (args [1]->opcode == OP_ICONST) ? args [1]->inst_c0 : args [1]->inst_l;
4701 is_imm = (imm == 1 || imm == 4 || imm == 8 || imm == 16 || imm == -1 || imm == -4 || imm == -8 || imm == -16);
4705 if (fsig->params [0]->type == MONO_TYPE_I4)
4706 opcode = OP_ATOMIC_ADD_IMM_I4;
4707 else if (fsig->params [0]->type == MONO_TYPE_I8)
4708 opcode = OP_ATOMIC_ADD_IMM_I8;
4710 g_assert_not_reached ();
4712 MONO_INST_NEW (cfg, ins, opcode);
4713 ins->dreg = mono_alloc_ireg (cfg);
4714 ins->inst_basereg = args [0]->dreg;
4715 ins->inst_offset = 0;
4716 ins->inst_imm = imm;
4717 ins->type = (opcode == OP_ATOMIC_ADD_IMM_I4) ? STACK_I4 : STACK_I8;
4719 if (fsig->params [0]->type == MONO_TYPE_I4)
4720 opcode = OP_ATOMIC_ADD_I4;
4721 else if (fsig->params [0]->type == MONO_TYPE_I8)
4722 opcode = OP_ATOMIC_ADD_I8;
4724 g_assert_not_reached ();
4726 MONO_INST_NEW (cfg, ins, opcode);
4727 ins->dreg = mono_alloc_ireg (cfg);
4728 ins->inst_basereg = args [0]->dreg;
4729 ins->inst_offset = 0;
4730 ins->sreg2 = args [1]->dreg;
4731 ins->type = (opcode == OP_ATOMIC_ADD_I4) ? STACK_I4 : STACK_I8;
4733 MONO_ADD_INS (cfg->cbb, ins);
4741 mono_arch_print_tree (MonoInst *tree, int arity)
4747 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
4749 /* FIXME: implement */
4750 g_assert_not_reached ();
4754 mono_arch_opcode_supported (int opcode)
4757 case OP_ATOMIC_ADD_I4:
4758 case OP_ATOMIC_ADD_I8:
4759 case OP_ATOMIC_EXCHANGE_I4:
4760 case OP_ATOMIC_EXCHANGE_I8: