mono/mini/mini-ia64.c

   1 /*
   2  * mini-ia64.c: IA64 backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Zoltan Varga (vargaz@gmail.com)
   6  *
   7  * (C) 2003 Ximian, Inc.
   8  */
   9 #include "mini.h"
  10 #include <string.h>
  11 #include <math.h>
  12 #include <unistd.h>
  13 #include <sys/mman.h>
  14
  15 #ifdef __INTEL_COMPILER
  16 #include <ia64intrin.h>
  17 #endif
  18
  19 #include <mono/metadata/appdomain.h>
  20 #include <mono/metadata/debug-helpers.h>
  21 #include <mono/metadata/threads.h>
  22 #include <mono/metadata/profiler-private.h>
  23 #include <mono/utils/mono-math.h>
  24
  25 #include "trace.h"
  26 #include "mini-ia64.h"
  27 #include "cpu-ia64.h"
  28 #include "jit-icalls.h"
  29 #include "ir-emit.h"
  30
  31 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  32
  33 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  34
  35 /*
  36  * IA64 register usage:
  37  * - local registers are used for global register allocation
  38  * - r8..r11, r14..r30 is used for local register allocation
  39  * - r31 is a scratch register used within opcode implementations
  40  * - FIXME: Use out registers as well
  41  * - the first three locals are used for saving ar.pfst, b0, and sp
  42  * - compare instructions allways set p6 and p7
  43  */
  44
  45 /*
  46  * There are a lot of places where generated code is disassembled/patched.
  47  * The automatic bundling of instructions done by the code generation macros
  48  * could complicate things, so it is best to call
  49  * ia64_codegen_set_one_ins_per_bundle () at those places.
  50  */
  51
  52 #define ARGS_OFFSET 16
  53
  54 #define GP_SCRATCH_REG 31
  55 #define GP_SCRATCH_REG2 30
  56 #define FP_SCRATCH_REG 32
  57 #define FP_SCRATCH_REG2 33
  58
  59 #define LOOP_ALIGNMENT 8
  60 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
  61
  62 static const char* gregs [] = {
  63         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
  64         "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
  65         "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29",
  66         "r30", "r31", "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  67         "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", "r48", "r49",
  68         "r50", "r51", "r52", "r53", "r54", "r55", "r56", "r57", "r58", "r59",
  69         "r60", "r61", "r62", "r63", "r64", "r65", "r66", "r67", "r68", "r69",
  70         "r70", "r71", "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
  71         "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", "r88", "r89",
  72         "r90", "r91", "r92", "r93", "r94", "r95", "r96", "r97", "r98", "r99",
  73         "r100", "r101", "r102", "r103", "r104", "r105", "r106", "r107", "r108", "r109",
  74         "r110", "r111", "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
  75         "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127"
  76 };
  77
  78 const char*
  79 mono_arch_regname (int reg)
  80 {
  81         if (reg < 128)
  82                 return gregs [reg];
  83         else
  84                 return "unknown";
  85 }
  86
  87 static const char* fregs [] = {
  88         "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
  89         "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
  90         "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
  91         "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
  92         "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
  93         "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
  94         "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69",
  95         "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
  96         "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89",
  97         "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99",
  98         "f100", "f101", "f102", "f103", "f104", "f105", "f106", "f107", "f108", "f109",
  99         "f110", "f111", "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
 100         "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127"
 101 };
 102
 103 const char*
 104 mono_arch_fregname (int reg)
 105 {
 106         if (reg < 128)
 107                 return fregs [reg];
 108         else
 109                 return "unknown";
 110 }
 111
 112 G_GNUC_UNUSED static void
 113 break_count (void)
 114 {
 115 }
 116
 117 G_GNUC_UNUSED static gboolean
 118 debug_count (void)
 119 {
 120         static int count = 0;
 121         count ++;
 122
 123         if (count == atoi (getenv ("COUNT"))) {
 124                 break_count ();
 125         }
 126
 127         if (count > atoi (getenv ("COUNT"))) {
 128                 return FALSE;
 129         }
 130
 131         return TRUE;
 132 }
 133
 134 static gboolean
 135 debug_ins_sched (void)
 136 {
 137 #if 0
 138         return debug_count ();
 139 #else
 140         return TRUE;
 141 #endif
 142 }
 143
 144 static gboolean
 145 debug_omit_fp (void)
 146 {
 147 #if 0
 148         return debug_count ();
 149 #else
 150         return TRUE;
 151 #endif
 152 }
 153
 154 static void
 155 ia64_patch (unsigned char* code, gpointer target);
 156
 157 typedef enum {
 158         ArgInIReg,
 159         ArgInFloatReg,
 160         ArgInFloatRegR4,
 161         ArgOnStack,
 162         ArgValuetypeAddrInIReg,
 163         ArgAggregate,
 164         ArgSingleHFA,
 165         ArgDoubleHFA,
 166         ArgNone
 167 } ArgStorage;
 168
 169 typedef enum {
 170         AggregateNormal,
 171         AggregateSingleHFA,
 172         AggregateDoubleHFA
 173 } AggregateType;
 174
 175 typedef struct {
 176         gint16 offset;
 177         gint8  reg;
 178         ArgStorage storage;
 179
 180         /* Only if storage == ArgAggregate */
 181         int nregs, nslots;
 182         AggregateType atype;
 183 } ArgInfo;
 184
 185 typedef struct {
 186         int nargs;
 187         guint32 stack_usage;
 188         guint32 reg_usage;
 189         guint32 freg_usage;
 190         gboolean need_stack_align;
 191         ArgInfo ret;
 192         ArgInfo sig_cookie;
 193         ArgInfo args [1];
 194 } CallInfo;
 195
 196 #define DEBUG(a) if (cfg->verbose_level > 1) a
 197
 198 #define PARAM_REGS 8
 199
 200 static void inline
 201 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 202 {
 203     ainfo->offset = *stack_size;
 204
 205     if (*gr >= PARAM_REGS) {
 206                 ainfo->storage = ArgOnStack;
 207                 (*stack_size) += sizeof (gpointer);
 208     }
 209     else {
 210                 ainfo->storage = ArgInIReg;
 211                 ainfo->reg = *gr;
 212                 *(gr) += 1;
 213     }
 214 }
 215
 216 #define FLOAT_PARAM_REGS 8
 217
 218 static void inline
 219 add_float (guint32 *gr, guint32 *fr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 220 {
 221     ainfo->offset = *stack_size;
 222
 223     if (*gr >= PARAM_REGS) {
 224                 ainfo->storage = ArgOnStack;
 225                 (*stack_size) += sizeof (gpointer);
 226     }
 227     else {
 228                 ainfo->storage = is_double ? ArgInFloatReg : ArgInFloatRegR4;
 229                 ainfo->reg = 8 + *fr;
 230                 (*fr) += 1;
 231                 (*gr) += 1;
 232     }
 233 }
 234
 235 static void
 236 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 237                gboolean is_return,
 238                guint32 *gr, guint32 *fr, guint32 *stack_size)
 239 {
 240         guint32 size, i;
 241         MonoClass *klass;
 242         MonoMarshalType *info;
 243         gboolean is_hfa = TRUE;
 244         guint32 hfa_type = 0;
 245
 246         klass = mono_class_from_mono_type (type);
 247         if (type->type == MONO_TYPE_TYPEDBYREF)
 248                 size = 3 * sizeof (gpointer);
 249         else if (sig->pinvoke)
 250                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 251         else
 252                 size = mini_type_stack_size (gsctx, &klass->byval_arg, NULL);
 253
 254         if (!sig->pinvoke || (size == 0)) {
 255                 /* Allways pass in memory */
 256                 ainfo->offset = *stack_size;
 257                 *stack_size += ALIGN_TO (size, 8);
 258                 ainfo->storage = ArgOnStack;
 259
 260                 return;
 261         }
 262
 263         /* Determine whenever it is a HFA (Homogeneous Floating Point Aggregate) */
 264         info = mono_marshal_load_type_info (klass);
 265         g_assert (info);
 266         for (i = 0; i < info->num_fields; ++i) {
 267                 guint32 ftype = info->fields [i].field->type->type;
 268                 if (!(info->fields [i].field->type->byref) &&
 269                         ((ftype == MONO_TYPE_R4) || (ftype == MONO_TYPE_R8))) {
 270                         if (hfa_type == 0)
 271                                 hfa_type = ftype;
 272                         else if (hfa_type != ftype)
 273                                 is_hfa = FALSE;
 274                 }
 275                 else
 276                         is_hfa = FALSE;
 277         }
 278         if (hfa_type == 0)
 279                 is_hfa = FALSE;
 280
 281         ainfo->storage = ArgAggregate;
 282         ainfo->atype = AggregateNormal;
 283
 284         if (is_hfa) {
 285                 ainfo->atype = hfa_type == MONO_TYPE_R4 ? AggregateSingleHFA : AggregateDoubleHFA;
 286                 if (is_return) {
 287                         if (info->num_fields <= 8) {
 288                                 ainfo->reg = 8;
 289                                 ainfo->nregs = info->num_fields;
 290                                 ainfo->nslots = ainfo->nregs;
 291                                 return;
 292                         }
 293                         /* Fall through */
 294                 }
 295                 else {
 296                         if ((*fr) + info->num_fields > 8)
 297                                 NOT_IMPLEMENTED;
 298
 299                         ainfo->reg = 8 + (*fr);
 300                         ainfo->nregs = info->num_fields;
 301                         ainfo->nslots = ainfo->nregs;
 302                         (*fr) += info->num_fields;
 303                         if (ainfo->atype == AggregateSingleHFA) {
 304                                 /*
 305                                  * FIXME: Have to keep track of the parameter slot number, which is
 306                                  * not the same as *gr.
 307                                  */
 308                                 (*gr) += ALIGN_TO (info->num_fields, 2) / 2;
 309                         } else {
 310                                 (*gr) += info->num_fields;
 311                         }
 312                         return;
 313                 }
 314         }
 315
 316         /* This also handles returning of TypedByRef used by some icalls */
 317         if (is_return) {
 318                 if (size <= 32) {
 319                         ainfo->reg = IA64_R8;
 320                         ainfo->nregs = (size + 7) / 8;
 321                         ainfo->nslots = ainfo->nregs;
 322                         return;
 323                 }
 324                 NOT_IMPLEMENTED;
 325         }
 326
 327         ainfo->reg = (*gr);
 328         ainfo->offset = *stack_size;
 329         ainfo->nslots = (size + 7) / 8;
 330
 331         if (((*gr) + ainfo->nslots) <= 8) {
 332                 /* Fits entirely in registers */
 333                 ainfo->nregs = ainfo->nslots;
 334                 (*gr) += ainfo->nregs;
 335                 return;
 336         }
 337
 338         ainfo->nregs = 8 - (*gr);
 339         (*gr) = 8;
 340         (*stack_size) += (ainfo->nslots - ainfo->nregs) * 8;
 341 }
 342
 343 /*
 344  * get_call_info:
 345  *
 346  *  Obtain information about a call according to the calling convention.
 347  * For IA64, see the "Itanium Software Conventions and Runtime Architecture
 348  * Gude" document for more information.
 349  */
 350 static CallInfo*
 351 get_call_info (MonoCompile *cfg, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 352 {
 353         guint32 i, gr, fr;
 354         MonoType *ret_type;
 355         int n = sig->hasthis + sig->param_count;
 356         guint32 stack_size = 0;
 357         CallInfo *cinfo;
 358         MonoGenericSharingContext *gsctx = cfg ? cfg->generic_sharing_context : NULL;
 359
 360         if (mp)
 361                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 362         else
 363                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 364
 365         gr = 0;
 366         fr = 0;
 367
 368         /* return value */
 369         {
 370                 ret_type = mono_type_get_underlying_type (sig->ret);
 371                 ret_type = mini_get_basic_type_from_generic (gsctx, ret_type);
 372                 switch (ret_type->type) {
 373                 case MONO_TYPE_BOOLEAN:
 374                 case MONO_TYPE_I1:
 375                 case MONO_TYPE_U1:
 376                 case MONO_TYPE_I2:
 377                 case MONO_TYPE_U2:
 378                 case MONO_TYPE_CHAR:
 379                 case MONO_TYPE_I4:
 380                 case MONO_TYPE_U4:
 381                 case MONO_TYPE_I:
 382                 case MONO_TYPE_U:
 383                 case MONO_TYPE_PTR:
 384                 case MONO_TYPE_FNPTR:
 385                 case MONO_TYPE_CLASS:
 386                 case MONO_TYPE_OBJECT:
 387                 case MONO_TYPE_SZARRAY:
 388                 case MONO_TYPE_ARRAY:
 389                 case MONO_TYPE_STRING:
 390                         cinfo->ret.storage = ArgInIReg;
 391                         cinfo->ret.reg = IA64_R8;
 392                         break;
 393                 case MONO_TYPE_U8:
 394                 case MONO_TYPE_I8:
 395                         cinfo->ret.storage = ArgInIReg;
 396                         cinfo->ret.reg = IA64_R8;
 397                         break;
 398                 case MONO_TYPE_R4:
 399                 case MONO_TYPE_R8:
 400                         cinfo->ret.storage = ArgInFloatReg;
 401                         cinfo->ret.reg = 8;
 402                         break;
 403                 case MONO_TYPE_GENERICINST:
 404                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 405                                 cinfo->ret.storage = ArgInIReg;
 406                                 cinfo->ret.reg = IA64_R8;
 407                                 break;
 408                         }
 409                         /* Fall through */
 410                 case MONO_TYPE_VALUETYPE:
 411                 case MONO_TYPE_TYPEDBYREF: {
 412                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 413
 414                         if (sig->ret->byref) {
 415                                 /* This seems to happen with ldfld wrappers */
 416                                 cinfo->ret.storage = ArgInIReg;
 417                         } else {
 418                                 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 419                                 if (cinfo->ret.storage == ArgOnStack)
 420                                         /* The caller passes the address where the value is stored */
 421                                         add_general (&gr, &stack_size, &cinfo->ret);
 422                                 if (cinfo->ret.storage == ArgInIReg)
 423                                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
 424                         }
 425                         break;
 426                 }
 427                 case MONO_TYPE_VOID:
 428                         cinfo->ret.storage = ArgNone;
 429                         break;
 430                 default:
 431                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 432                 }
 433         }
 434
 435         /* this */
 436         if (sig->hasthis)
 437                 add_general (&gr, &stack_size, cinfo->args + 0);
 438
 439         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 440                 gr = PARAM_REGS;
 441                 fr = FLOAT_PARAM_REGS;
 442
 443                 /* Emit the signature cookie just before the implicit arguments */
 444                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 445         }
 446
 447         for (i = 0; i < sig->param_count; ++i) {
 448                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 449                 MonoType *ptype;
 450
 451                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 452                         /* We allways pass the sig cookie on the stack for simplicity */
 453                         /*
 454                          * Prevent implicit arguments + the sig cookie from being passed
 455                          * in registers.
 456                          */
 457                         gr = PARAM_REGS;
 458                         fr = FLOAT_PARAM_REGS;
 459
 460                         /* Emit the signature cookie just before the implicit arguments */
 461                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 462                 }
 463
 464                 if (sig->params [i]->byref) {
 465                         add_general (&gr, &stack_size, ainfo);
 466                         continue;
 467                 }
 468                 ptype = mono_type_get_underlying_type (sig->params [i]);
 469                 ptype = mini_get_basic_type_from_generic (gsctx, ptype);
 470                 switch (ptype->type) {
 471                 case MONO_TYPE_BOOLEAN:
 472                 case MONO_TYPE_I1:
 473                 case MONO_TYPE_U1:
 474                         add_general (&gr, &stack_size, ainfo);
 475                         break;
 476                 case MONO_TYPE_I2:
 477                 case MONO_TYPE_U2:
 478                 case MONO_TYPE_CHAR:
 479                         add_general (&gr, &stack_size, ainfo);
 480                         break;
 481                 case MONO_TYPE_I4:
 482                 case MONO_TYPE_U4:
 483                         add_general (&gr, &stack_size, ainfo);
 484                         break;
 485                 case MONO_TYPE_I:
 486                 case MONO_TYPE_U:
 487                 case MONO_TYPE_PTR:
 488                 case MONO_TYPE_FNPTR:
 489                 case MONO_TYPE_CLASS:
 490                 case MONO_TYPE_OBJECT:
 491                 case MONO_TYPE_STRING:
 492                 case MONO_TYPE_SZARRAY:
 493                 case MONO_TYPE_ARRAY:
 494                         add_general (&gr, &stack_size, ainfo);
 495                         break;
 496                 case MONO_TYPE_GENERICINST:
 497                         if (!mono_type_generic_inst_is_valuetype (sig->params [i])) {
 498                                 add_general (&gr, &stack_size, ainfo);
 499                                 break;
 500                         }
 501                         /* Fall through */
 502                 case MONO_TYPE_VALUETYPE:
 503                 case MONO_TYPE_TYPEDBYREF:
 504                         /* FIXME: */
 505                         /* We allways pass valuetypes on the stack */
 506                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 507                         break;
 508                 case MONO_TYPE_U8:
 509                 case MONO_TYPE_I8:
 510                         add_general (&gr, &stack_size, ainfo);
 511                         break;
 512                 case MONO_TYPE_R4:
 513                         add_float (&gr, &fr, &stack_size, ainfo, FALSE);
 514                         break;
 515                 case MONO_TYPE_R8:
 516                         add_float (&gr, &fr, &stack_size, ainfo, TRUE);
 517                         break;
 518                 default:
 519                         g_assert_not_reached ();
 520                 }
 521         }
 522
 523         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 524                 gr = PARAM_REGS;
 525                 fr = FLOAT_PARAM_REGS;
 526
 527                 /* Emit the signature cookie just before the implicit arguments */
 528                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 529         }
 530
 531         cinfo->stack_usage = stack_size;
 532         cinfo->reg_usage = gr;
 533         cinfo->freg_usage = fr;
 534         return cinfo;
 535 }
 536
 537 /*
 538  * mono_arch_get_argument_info:
 539  * @csig:  a method signature
 540  * @param_count: the number of parameters to consider
 541  * @arg_info: an array to store the result infos
 542  *
 543  * Gathers information on parameters such as size, alignment and
 544  * padding. arg_info should be large enought to hold param_count + 1 entries.
 545  *
 546  * Returns the size of the argument area on the stack.
 547  */
 548 int
 549 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 550 {
 551         int k;
 552         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 553         guint32 args_size = cinfo->stack_usage;
 554
 555         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 556         if (csig->hasthis) {
 557                 arg_info [0].offset = 0;
 558         }
 559
 560         for (k = 0; k < param_count; k++) {
 561                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 562                 /* FIXME: */
 563                 arg_info [k + 1].size = 0;
 564         }
 565
 566         g_free (cinfo);
 567
 568         return args_size;
 569 }
 570
 571 /*
 572  * Initialize the cpu to execute managed code.
 573  */
 574 void
 575 mono_arch_cpu_init (void)
 576 {
 577 }
 578
 579 /*
 580  * Initialize architecture specific code.
 581  */
 582 void
 583 mono_arch_init (void)
 584 {
 585 }
 586
 587 /*
 588  * Cleanup architecture specific code.
 589  */
 590 void
 591 mono_arch_cleanup (void)
 592 {
 593 }
 594
 595 /*
 596  * This function returns the optimizations supported on this cpu.
 597  */
 598 guint32
 599 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 600 {
 601         *exclude_mask = 0;
 602
 603         return 0;
 604 }
 605
 606 GList *
 607 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 608 {
 609         GList *vars = NULL;
 610         int i;
 611         MonoMethodSignature *sig;
 612         MonoMethodHeader *header;
 613         CallInfo *cinfo;
 614
 615         header = mono_method_get_header (cfg->method);
 616
 617         sig = mono_method_signature (cfg->method);
 618
 619         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 620
 621         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 622                 MonoInst *ins = cfg->args [i];
 623
 624                 ArgInfo *ainfo = &cinfo->args [i];
 625
 626                 if (ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 627                         continue;
 628
 629                 if (ainfo->storage == ArgInIReg) {
 630                         /* The input registers are non-volatile */
 631                         ins->opcode = OP_REGVAR;
 632                         ins->dreg = 32 + ainfo->reg;
 633                 }
 634         }
 635
 636         for (i = 0; i < cfg->num_varinfo; i++) {
 637                 MonoInst *ins = cfg->varinfo [i];
 638                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 639
 640                 /* unused vars */
 641                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 642                         continue;
 643
 644                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 645                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 646                         continue;
 647
 648                 if (mono_is_regsize_var (ins->inst_vtype)) {
 649                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 650                         g_assert (i == vmv->idx);
 651                         vars = g_list_prepend (vars, vmv);
 652                 }
 653         }
 654
 655         vars = mono_varlist_sort (cfg, vars, 0);
 656
 657         return vars;
 658 }
 659
 660 static void
 661 mono_ia64_alloc_stacked_registers (MonoCompile *cfg)
 662 {
 663         CallInfo *cinfo;
 664         guint32 reserved_regs;
 665         MonoMethodHeader *header;
 666
 667         if (cfg->arch.reg_local0 > 0)
 668                 /* Already done */
 669                 return;
 670
 671         cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (cfg->method), FALSE);
 672
 673         header = mono_method_get_header (cfg->method);
 674
 675         /* Some registers are reserved for use by the prolog/epilog */
 676         reserved_regs = header->num_clauses ? 4 : 3;
 677
 678         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 679                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
 680                 /* One registers is needed by instrument_epilog to save the return value */
 681                 reserved_regs ++;
 682                 if (cinfo->reg_usage < 2)
 683                         /* Number of arguments passed to function call in instrument_prolog */
 684                         cinfo->reg_usage = 2;
 685         }
 686
 687         cfg->arch.reg_in0 = 32;
 688         cfg->arch.reg_local0 = cfg->arch.reg_in0 + cinfo->reg_usage + reserved_regs;
 689         cfg->arch.reg_out0 = cfg->arch.reg_local0 + 16;
 690
 691         cfg->arch.reg_saved_ar_pfs = cfg->arch.reg_local0 - 1;
 692         cfg->arch.reg_saved_b0 = cfg->arch.reg_local0 - 2;
 693         cfg->arch.reg_fp = cfg->arch.reg_local0 - 3;
 694
 695         /*
 696          * Frames without handlers save sp to fp, frames with handlers save it into
 697          * a dedicated register.
 698          */
 699         if (header->num_clauses)
 700                 cfg->arch.reg_saved_sp = cfg->arch.reg_local0 - 4;
 701         else
 702                 cfg->arch.reg_saved_sp = cfg->arch.reg_fp;
 703
 704         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 705                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
 706                 cfg->arch.reg_saved_return_val = cfg->arch.reg_local0 - reserved_regs;
 707         }
 708
 709         /*
 710          * Need to allocate at least 2 out register for use by OP_THROW / the system
 711          * exception throwing code.
 712          */
 713         cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, 2);
 714 }
 715
 716 GList *
 717 mono_arch_get_global_int_regs (MonoCompile *cfg)
 718 {
 719         GList *regs = NULL;
 720         int i;
 721
 722         mono_ia64_alloc_stacked_registers (cfg);
 723
 724         for (i = cfg->arch.reg_local0; i < cfg->arch.reg_out0; ++i) {
 725                 /* FIXME: regmask */
 726                 g_assert (i < 64);
 727                 regs = g_list_prepend (regs, (gpointer)(gssize)(i));
 728         }
 729
 730         return regs;
 731 }
 732
 733 /*
 734  * mono_arch_regalloc_cost:
 735  *
 736  *  Return the cost, in number of memory references, of the action of
 737  * allocating the variable VMV into a register during global register
 738  * allocation.
 739  */
 740 guint32
 741 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 742 {
 743         /* FIXME: Increase costs linearly to avoid using all local registers */
 744
 745         return 0;
 746 }
 747
 748 void
 749 mono_arch_allocate_vars (MonoCompile *cfg)
 750 {
 751         MonoMethodSignature *sig;
 752         MonoMethodHeader *header;
 753         MonoInst *inst;
 754         int i, offset;
 755         guint32 locals_stack_size, locals_stack_align;
 756         gint32 *offsets;
 757         CallInfo *cinfo;
 758
 759         header = mono_method_get_header (cfg->method);
 760
 761         sig = mono_method_signature (cfg->method);
 762
 763         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 764
 765         /*
 766          * Determine whenever the frame pointer can be eliminated.
 767          * FIXME: Remove some of the restrictions.
 768          */
 769         cfg->arch.omit_fp = TRUE;
 770
 771         if (!debug_omit_fp ())
 772                 cfg->arch.omit_fp = FALSE;
 773
 774         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 775                 cfg->arch.omit_fp = FALSE;
 776         if (header->num_clauses)
 777                 cfg->arch.omit_fp = FALSE;
 778         if (cfg->param_area)
 779                 cfg->arch.omit_fp = FALSE;
 780         if ((sig->ret->type != MONO_TYPE_VOID) && (cinfo->ret.storage == ArgAggregate))
 781                 cfg->arch.omit_fp = FALSE;
 782         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 783                 cfg->arch.omit_fp = FALSE;
 784         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 785                 ArgInfo *ainfo = &cinfo->args [i];
 786
 787                 if (ainfo->storage == ArgOnStack) {
 788                         /*
 789                          * The stack offset can only be determined when the frame
 790                          * size is known.
 791                          */
 792                         cfg->arch.omit_fp = FALSE;
 793                 }
 794         }
 795
 796         mono_ia64_alloc_stacked_registers (cfg);
 797
 798         /*
 799          * We use the ABI calling conventions for managed code as well.
 800          * Exception: valuetypes are never passed or returned in registers.
 801          */
 802
 803         if (cfg->arch.omit_fp) {
 804                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
 805                 cfg->frame_reg = IA64_SP;
 806                 offset = ARGS_OFFSET;
 807         }
 808         else {
 809                 /* Locals are allocated backwards from %fp */
 810                 cfg->frame_reg = cfg->arch.reg_fp;
 811                 offset = 0;
 812         }
 813
 814         if (cfg->method->save_lmf) {
 815                 /* No LMF on IA64 */
 816         }
 817
 818         if (sig->ret->type != MONO_TYPE_VOID) {
 819                 switch (cinfo->ret.storage) {
 820                 case ArgInIReg:
 821                         cfg->ret->opcode = OP_REGVAR;
 822                         cfg->ret->inst_c0 = cinfo->ret.reg;
 823                         break;
 824                 case ArgInFloatReg:
 825                         cfg->ret->opcode = OP_REGVAR;
 826                         cfg->ret->inst_c0 = cinfo->ret.reg;
 827                         break;
 828                 case ArgValuetypeAddrInIReg:
 829                         cfg->vret_addr->opcode = OP_REGVAR;
 830                         cfg->vret_addr->dreg = cfg->arch.reg_in0 + cinfo->ret.reg;
 831                         break;
 832                 case ArgAggregate:
 833                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
 834                         if (cfg->arch.omit_fp)
 835                                 g_assert_not_reached ();
 836                         offset = ALIGN_TO (offset, 8);
 837                         offset += cinfo->ret.nslots * 8;
 838                         cfg->ret->opcode = OP_REGOFFSET;
 839                         cfg->ret->inst_basereg = cfg->frame_reg;
 840                         cfg->ret->inst_offset = - offset;
 841                         break;
 842                 default:
 843                         g_assert_not_reached ();
 844                 }
 845                 cfg->ret->dreg = cfg->ret->inst_c0;
 846         }
 847
 848         /* Allocate locals */
 849         offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE : TRUE, &locals_stack_size, &locals_stack_align);
 850         if (locals_stack_align) {
 851                 offset = ALIGN_TO (offset, locals_stack_align);
 852         }
 853         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
 854                 if (offsets [i] != -1) {
 855                         MonoInst *inst = cfg->varinfo [i];
 856                         inst->opcode = OP_REGOFFSET;
 857                         inst->inst_basereg = cfg->frame_reg;
 858                         if (cfg->arch.omit_fp)
 859                                 inst->inst_offset = (offset + offsets [i]);
 860                         else
 861                                 inst->inst_offset = - (offset + offsets [i]);
 862                         // printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
 863                 }
 864         }
 865         offset += locals_stack_size;
 866
 867         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
 868                 if (cfg->arch.omit_fp)
 869                         g_assert_not_reached ();
 870                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
 871                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
 872         }
 873
 874         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 875                 inst = cfg->args [i];
 876                 if (inst->opcode != OP_REGVAR) {
 877                         ArgInfo *ainfo = &cinfo->args [i];
 878                         gboolean inreg = TRUE;
 879                         MonoType *arg_type;
 880
 881                         if (sig->hasthis && (i == 0))
 882                                 arg_type = &mono_defaults.object_class->byval_arg;
 883                         else
 884                                 arg_type = sig->params [i - sig->hasthis];
 885
 886                         /* FIXME: VOLATILE is only set if the liveness pass runs */
 887                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 888                                 inreg = FALSE;
 889
 890                         inst->opcode = OP_REGOFFSET;
 891
 892                         switch (ainfo->storage) {
 893                         case ArgInIReg:
 894                                 inst->opcode = OP_REGVAR;
 895                                 inst->dreg = cfg->arch.reg_in0 + ainfo->reg;
 896                                 break;
 897                         case ArgInFloatReg:
 898                         case ArgInFloatRegR4:
 899                                 /*
 900                                  * Since float regs are volatile, we save the arguments to
 901                                  * the stack in the prolog.
 902                                  */
 903                                 inreg = FALSE;
 904                                 break;
 905                         case ArgOnStack:
 906                                 if (cfg->arch.omit_fp)
 907                                         g_assert_not_reached ();
 908                                 inst->opcode = OP_REGOFFSET;
 909                                 inst->inst_basereg = cfg->frame_reg;
 910                                 inst->inst_offset = ARGS_OFFSET + ainfo->offset;
 911                                 break;
 912                         case ArgAggregate:
 913                                 inreg = FALSE;
 914                                 break;
 915                         default:
 916                                 NOT_IMPLEMENTED;
 917                         }
 918
 919                         if (!inreg && (ainfo->storage != ArgOnStack)) {
 920                                 guint32 size = 0;
 921
 922                                 inst->opcode = OP_REGOFFSET;
 923                                 inst->inst_basereg = cfg->frame_reg;
 924                                 /* These arguments are saved to the stack in the prolog */
 925                                 switch (ainfo->storage) {
 926                                 case ArgAggregate:
 927                                         if (ainfo->atype == AggregateSingleHFA)
 928                                                 size = ainfo->nslots * 4;
 929                                         else
 930                                                 size = ainfo->nslots * 8;
 931                                         break;
 932                                 default:
 933                                         size = sizeof (gpointer);
 934                                         break;
 935                                 }
 936
 937                                 offset = ALIGN_TO (offset, sizeof (gpointer));
 938
 939                                 if (cfg->arch.omit_fp) {
 940                                         inst->inst_offset = offset;
 941                                         offset += size;
 942                                 } else {
 943                                         offset += size;
 944                                         inst->inst_offset = - offset;
 945                                 }
 946                         }
 947                 }
 948         }
 949
 950         /*
 951          * FIXME: This doesn't work because some variables are allocated during local
 952          * regalloc.
 953          */
 954         /*
 955         if (cfg->arch.omit_fp && offset == 16)
 956                 offset = 0;
 957         */
 958
 959         cfg->stack_offset = offset;
 960 }
 961
 962 void
 963 mono_arch_create_vars (MonoCompile *cfg)
 964 {
 965         MonoMethodSignature *sig;
 966         CallInfo *cinfo;
 967
 968         sig = mono_method_signature (cfg->method);
 969
 970         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 971
 972         if (cinfo->ret.storage == ArgAggregate)
 973                 cfg->ret_var_is_local = TRUE;
 974         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
 975                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
 976                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
 977                         printf ("vret_addr = ");
 978                         mono_print_ins (cfg->vret_addr);
 979                 }
 980         }
 981 }
 982
 983 static void
 984 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
 985 {
 986         MonoInst *arg;
 987
 988         MONO_INST_NEW (cfg, arg, OP_NOP);
 989         arg->sreg1 = tree->dreg;
 990
 991         switch (storage) {
 992         case ArgInIReg:
 993                 arg->opcode = OP_MOVE;
 994                 arg->dreg = mono_alloc_ireg (cfg);
 995
 996                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, FALSE);
 997                 break;
 998         case ArgInFloatReg:
 999                 arg->opcode = OP_FMOVE;
1000                 arg->dreg = mono_alloc_freg (cfg);
1001
1002                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1003                 break;
1004         case ArgInFloatRegR4:
1005                 arg->opcode = OP_FCONV_TO_R4;
1006                 arg->dreg = mono_alloc_freg (cfg);
1007
1008                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1009                 break;
1010         default:
1011                 g_assert_not_reached ();
1012         }
1013
1014         MONO_ADD_INS (cfg->cbb, arg);
1015 }
1016
1017 static void
1018 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1019 {
1020         MonoMethodSignature *tmp_sig;
1021
1022         /* Emit the signature cookie just before the implicit arguments */
1023         MonoInst *sig_arg;
1024         /* FIXME: Add support for signature tokens to AOT */
1025         cfg->disable_aot = TRUE;
1026
1027         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1028
1029         /*
1030          * mono_ArgIterator_Setup assumes the signature cookie is
1031          * passed first and all the arguments which were before it are
1032          * passed on the stack after the signature. So compensate by
1033          * passing a different signature.
1034          */
1035         tmp_sig = mono_metadata_signature_dup (call->signature);
1036         tmp_sig->param_count -= call->signature->sentinelpos;
1037         tmp_sig->sentinelpos = 0;
1038         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1039
1040         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1041         sig_arg->dreg = mono_alloc_ireg (cfg);
1042         sig_arg->inst_p0 = tmp_sig;
1043         MONO_ADD_INS (cfg->cbb, sig_arg);
1044
1045         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + cinfo->sig_cookie.offset, sig_arg->dreg);
1046 }
1047
1048 void
1049 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1050 {
1051         MonoInst *in;
1052         MonoMethodSignature *sig;
1053         int i, n, stack_size;
1054         CallInfo *cinfo;
1055         ArgInfo *ainfo;
1056
1057         stack_size = 0;
1058
1059         mono_ia64_alloc_stacked_registers (cfg);
1060
1061         sig = call->signature;
1062         n = sig->param_count + sig->hasthis;
1063
1064         cinfo = get_call_info (cfg, cfg->mempool, sig, sig->pinvoke);
1065
1066         if (cinfo->ret.storage == ArgAggregate) {
1067                 MonoInst *vtarg;
1068                 MonoInst *local;
1069
1070                 /*
1071                  * The valuetype is in registers after the call, need to be copied
1072                  * to the stack. Save the address to a local here, so the call
1073                  * instruction can access it.
1074                  */
1075                 local = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1076                 local->flags |= MONO_INST_VOLATILE;
1077                 cfg->arch.ret_var_addr_local = local;
1078
1079                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1080                 vtarg->sreg1 = call->vret_var->dreg;
1081                 vtarg->dreg = local->dreg;
1082                 MONO_ADD_INS (cfg->cbb, vtarg);
1083         }
1084
1085         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1086                 add_outarg_reg (cfg, call, ArgInIReg, cfg->arch.reg_out0 + cinfo->ret.reg, call->vret_var);
1087         }
1088
1089         for (i = 0; i < n; ++i) {
1090                 MonoType *arg_type;
1091
1092                 ainfo = cinfo->args + i;
1093
1094                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1095                         /* Emit the signature cookie just before the implicit arguments */
1096                         emit_sig_cookie (cfg, call, cinfo);
1097                 }
1098
1099                 in = call->args [i];
1100
1101                 if (sig->hasthis && (i == 0))
1102                         arg_type = &mono_defaults.object_class->byval_arg;
1103                 else
1104                         arg_type = sig->params [i - sig->hasthis];
1105
1106                 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(arg_type))) {
1107                         guint32 align;
1108                         guint32 size;
1109
1110                         if (arg_type->type == MONO_TYPE_TYPEDBYREF) {
1111                                 size = sizeof (MonoTypedRef);
1112                                 align = sizeof (gpointer);
1113                         }
1114                         else if (sig->pinvoke)
1115                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1116                         else {
1117                                 /*
1118                                  * Other backends use mono_type_stack_size (), but that
1119                                  * aligns the size to 8, which is larger than the size of
1120                                  * the source, leading to reads of invalid memory if the
1121                                  * source is at the end of address space.
1122                                  */
1123                                 size = mono_class_value_size (in->klass, &align);
1124                         }
1125
1126                         if (size > 0) {
1127                                 MonoInst *arg;
1128
1129                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1130                                 arg->sreg1 = in->dreg;
1131                                 arg->klass = in->klass;
1132                                 arg->backend.size = size;
1133                                 arg->inst_p0 = call;
1134                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1135                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1136
1137                                 MONO_ADD_INS (cfg->cbb, arg);
1138                         }
1139                 }
1140                 else {
1141                         switch (ainfo->storage) {
1142                         case ArgInIReg:
1143                                 add_outarg_reg (cfg, call, ainfo->storage, cfg->arch.reg_out0 + ainfo->reg, in);
1144                                 break;
1145                         case ArgInFloatReg:
1146                         case ArgInFloatRegR4:
1147                                 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1148                                 break;
1149                         case ArgOnStack:
1150                                 if (arg_type->type == MONO_TYPE_R4 && !arg_type->byref)
1151                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1152                                 else if (arg_type->type == MONO_TYPE_R8 && !arg_type->byref)
1153                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1154                                 else
1155                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1156                                 break;
1157                         default:
1158                                 g_assert_not_reached ();
1159                         }
1160                 }
1161         }
1162
1163         /* Handle the case where there are no implicit arguments */
1164         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1165                 emit_sig_cookie (cfg, call, cinfo);
1166         }
1167
1168         call->stack_usage = cinfo->stack_usage;
1169         cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, cinfo->reg_usage);
1170 }
1171
1172 void
1173 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1174 {
1175         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1176         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1177         int size = ins->backend.size;
1178
1179         if (ainfo->storage == ArgAggregate) {
1180                 MonoInst *load, *store;
1181                 int i, slot;
1182
1183                 /*
1184                  * Part of the structure is passed in registers.
1185                  */
1186                 for (i = 0; i < ainfo->nregs; ++i) {
1187                         slot = ainfo->reg + i;
1188
1189                         if (ainfo->atype == AggregateSingleHFA) {
1190                                 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
1191                                 load->inst_basereg = src->dreg;
1192                                 load->inst_offset = i * 4;
1193                                 load->dreg = mono_alloc_freg (cfg);
1194
1195                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1196                         } else if (ainfo->atype == AggregateDoubleHFA) {
1197                                 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
1198                                 load->inst_basereg = src->dreg;
1199                                 load->inst_offset = i * 8;
1200                                 load->dreg = mono_alloc_freg (cfg);
1201
1202                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1203                         } else {
1204                                 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1205                                 load->inst_basereg = src->dreg;
1206                                 load->inst_offset = i * 8;
1207                                 load->dreg = mono_alloc_ireg (cfg);
1208
1209                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, cfg->arch.reg_out0 + ainfo->reg + i, FALSE);
1210                         }
1211                         MONO_ADD_INS (cfg->cbb, load);
1212                 }
1213
1214                 /*
1215                  * Part of the structure is passed on the stack.
1216                  */
1217                 for (i = ainfo->nregs; i < ainfo->nslots; ++i) {
1218                         slot = ainfo->reg + i;
1219
1220                         MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1221                         load->inst_basereg = src->dreg;
1222                         load->inst_offset = i * sizeof (gpointer);
1223                         load->dreg = mono_alloc_preg (cfg);
1224                         MONO_ADD_INS (cfg->cbb, load);
1225
1226                         MONO_INST_NEW (cfg, store, OP_STOREI8_MEMBASE_REG);
1227                         store->sreg1 = load->dreg;
1228                         store->inst_destbasereg = IA64_SP;
1229                         store->inst_offset = 16 + ainfo->offset + (slot - 8) * 8;
1230                         MONO_ADD_INS (cfg->cbb, store);
1231                 }
1232         } else {
1233                 mini_emit_memcpy (cfg, IA64_SP, 16 + ainfo->offset, src->dreg, 0, size, 4);
1234         }
1235 }
1236
1237 void
1238 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1239 {
1240         CallInfo *cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
1241
1242         switch (cinfo->ret.storage) {
1243         case ArgInIReg:
1244                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1245                 break;
1246         case ArgInFloatReg:
1247                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1248                 break;
1249         default:
1250                 g_assert_not_reached ();
1251         }
1252 }
1253
1254 void
1255 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1256 {
1257 }
1258
1259 void
1260 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1261 {
1262         MonoInst *ins, *n, *last_ins = NULL;
1263         ins = bb->code;
1264
1265         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1266                 switch (ins->opcode) {
1267                 case OP_MOVE:
1268                 case OP_FMOVE:
1269                         /*
1270                          * Removes:
1271                          *
1272                          * OP_MOVE reg, reg
1273                          */
1274                         if (ins->dreg == ins->sreg1) {
1275                                 MONO_DELETE_INS (bb, ins);
1276                                 continue;
1277                         }
1278                         /*
1279                          * Removes:
1280                          *
1281                          * OP_MOVE sreg, dreg
1282                          * OP_MOVE dreg, sreg
1283                          */
1284                         if (last_ins && last_ins->opcode == OP_MOVE &&
1285                             ins->sreg1 == last_ins->dreg &&
1286                             ins->dreg == last_ins->sreg1) {
1287                                 MONO_DELETE_INS (bb, ins);
1288                                 continue;
1289                         }
1290                         break;
1291                 case OP_MUL_IMM:
1292                 case OP_IMUL_IMM:
1293                         /* remove unnecessary multiplication with 1 */
1294                         if (ins->inst_imm == 1) {
1295                                 if (ins->dreg != ins->sreg1) {
1296                                         ins->opcode = OP_MOVE;
1297                                 } else {
1298                                         MONO_DELETE_INS (bb, ins);
1299                                         continue;
1300                                 }
1301                         }
1302                         break;
1303                 }
1304
1305                 last_ins = ins;
1306                 ins = ins->next;
1307         }
1308         bb->last_ins = last_ins;
1309 }
1310
1311 int cond_to_ia64_cmp [][3] = {
1312         {OP_IA64_CMP_EQ, OP_IA64_CMP4_EQ, OP_IA64_FCMP_EQ},
1313         {OP_IA64_CMP_NE, OP_IA64_CMP4_NE, OP_IA64_FCMP_NE},
1314         {OP_IA64_CMP_LE, OP_IA64_CMP4_LE, OP_IA64_FCMP_LE},
1315         {OP_IA64_CMP_GE, OP_IA64_CMP4_GE, OP_IA64_FCMP_GE},
1316         {OP_IA64_CMP_LT, OP_IA64_CMP4_LT, OP_IA64_FCMP_LT},
1317         {OP_IA64_CMP_GT, OP_IA64_CMP4_GT, OP_IA64_FCMP_GT},
1318         {OP_IA64_CMP_LE_UN, OP_IA64_CMP4_LE_UN, OP_IA64_FCMP_LE_UN},
1319         {OP_IA64_CMP_GE_UN, OP_IA64_CMP4_GE_UN, OP_IA64_FCMP_GE_UN},
1320         {OP_IA64_CMP_LT_UN, OP_IA64_CMP4_LT_UN, OP_IA64_FCMP_LT_UN},
1321         {OP_IA64_CMP_GT_UN, OP_IA64_CMP4_GT_UN, OP_IA64_FCMP_GT_UN}
1322 };
1323
1324 static int
1325 opcode_to_ia64_cmp (int opcode, int cmp_opcode)
1326 {
1327         return cond_to_ia64_cmp [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1328 }
1329
1330 int cond_to_ia64_cmp_imm [][3] = {
1331         {OP_IA64_CMP_EQ_IMM, OP_IA64_CMP4_EQ_IMM, 0},
1332         {OP_IA64_CMP_NE_IMM, OP_IA64_CMP4_NE_IMM, 0},
1333         {OP_IA64_CMP_GE_IMM, OP_IA64_CMP4_GE_IMM, 0},
1334         {OP_IA64_CMP_LE_IMM, OP_IA64_CMP4_LE_IMM, 0},
1335         {OP_IA64_CMP_GT_IMM, OP_IA64_CMP4_GT_IMM, 0},
1336         {OP_IA64_CMP_LT_IMM, OP_IA64_CMP4_LT_IMM, 0},
1337         {OP_IA64_CMP_GE_UN_IMM, OP_IA64_CMP4_GE_UN_IMM, 0},
1338         {OP_IA64_CMP_LE_UN_IMM, OP_IA64_CMP4_LE_UN_IMM, 0},
1339         {OP_IA64_CMP_GT_UN_IMM, OP_IA64_CMP4_GT_UN_IMM, 0},
1340         {OP_IA64_CMP_LT_UN_IMM, OP_IA64_CMP4_LT_UN_IMM, 0},
1341 };
1342
1343 static int
1344 opcode_to_ia64_cmp_imm (int opcode, int cmp_opcode)
1345 {
1346         /* The condition needs to be reversed */
1347         return cond_to_ia64_cmp_imm [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1348 }
1349
1350 #define NEW_INS(cfg,dest,op) do {       \
1351                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1352                 (dest)->opcode = (op);  \
1353         mono_bblock_insert_after_ins (bb, last_ins, (dest)); \
1354         last_ins = (dest); \
1355         } while (0)
1356
1357 /*
1358  * mono_arch_lowering_pass:
1359  *
1360  *  Converts complex opcodes into simpler ones so that each IR instruction
1361  * corresponds to one machine instruction.
1362  */
1363 void
1364 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1365 {
1366         MonoInst *ins, *n, *next, *temp, *temp2, *temp3, *last_ins = NULL;
1367         ins = bb->code;
1368
1369         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1370                 switch (ins->opcode) {
1371                 case OP_STOREI1_MEMBASE_IMM:
1372                 case OP_STOREI2_MEMBASE_IMM:
1373                 case OP_STOREI4_MEMBASE_IMM:
1374                 case OP_STOREI8_MEMBASE_IMM:
1375                 case OP_STORE_MEMBASE_IMM:
1376                         /* There are no store_membase instructions on ia64 */
1377                         if (ins->inst_offset == 0) {
1378                                 temp2 = NULL;
1379                         } else if (ia64_is_imm14 (ins->inst_offset)) {
1380                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1381                                 temp2->sreg1 = ins->inst_destbasereg;
1382                                 temp2->inst_imm = ins->inst_offset;
1383                                 temp2->dreg = mono_alloc_ireg (cfg);
1384                         }
1385                         else {
1386                                 NEW_INS (cfg, temp, OP_I8CONST);
1387                                 temp->inst_c0 = ins->inst_offset;
1388                                 temp->dreg = mono_alloc_ireg (cfg);
1389
1390                                 NEW_INS (cfg, temp2, OP_LADD);
1391                                 temp2->sreg1 = ins->inst_destbasereg;
1392                                 temp2->sreg2 = temp->dreg;
1393                                 temp2->dreg = mono_alloc_ireg (cfg);
1394                         }
1395
1396                         switch (ins->opcode) {
1397                         case OP_STOREI1_MEMBASE_IMM:
1398                                 ins->opcode = OP_STOREI1_MEMBASE_REG;
1399                                 break;
1400                         case OP_STOREI2_MEMBASE_IMM:
1401                                 ins->opcode = OP_STOREI2_MEMBASE_REG;
1402                                 break;
1403                         case OP_STOREI4_MEMBASE_IMM:
1404                                 ins->opcode = OP_STOREI4_MEMBASE_REG;
1405                                 break;
1406                         case OP_STOREI8_MEMBASE_IMM:
1407                         case OP_STORE_MEMBASE_IMM:
1408                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
1409                                 break;
1410                         default:
1411                                 g_assert_not_reached ();
1412                         }
1413
1414                         if (ins->inst_imm == 0)
1415                                 ins->sreg1 = IA64_R0;
1416                         else {
1417                                 NEW_INS (cfg, temp3, OP_I8CONST);
1418                                 temp3->inst_c0 = ins->inst_imm;
1419                                 temp3->dreg = mono_alloc_ireg (cfg);
1420                                 ins->sreg1 = temp3->dreg;
1421                         }
1422
1423                         ins->inst_offset = 0;
1424                         if (temp2)
1425                                 ins->inst_destbasereg = temp2->dreg;
1426                         break;
1427                 case OP_STOREI1_MEMBASE_REG:
1428                 case OP_STOREI2_MEMBASE_REG:
1429                 case OP_STOREI4_MEMBASE_REG:
1430                 case OP_STOREI8_MEMBASE_REG:
1431                 case OP_STORER4_MEMBASE_REG:
1432                 case OP_STORER8_MEMBASE_REG:
1433                 case OP_STORE_MEMBASE_REG:
1434                         /* There are no store_membase instructions on ia64 */
1435                         if (ins->inst_offset == 0) {
1436                                 break;
1437                         }
1438                         else if (ia64_is_imm14 (ins->inst_offset)) {
1439                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1440                                 temp2->sreg1 = ins->inst_destbasereg;
1441                                 temp2->inst_imm = ins->inst_offset;
1442                                 temp2->dreg = mono_alloc_ireg (cfg);
1443                         }
1444                         else {
1445                                 NEW_INS (cfg, temp, OP_I8CONST);
1446                                 temp->inst_c0 = ins->inst_offset;
1447                                 temp->dreg = mono_alloc_ireg (cfg);
1448                                 NEW_INS (cfg, temp2, OP_LADD);
1449                                 temp2->sreg1 = ins->inst_destbasereg;
1450                                 temp2->sreg2 = temp->dreg;
1451                                 temp2->dreg = mono_alloc_ireg (cfg);
1452                         }
1453
1454                         ins->inst_offset = 0;
1455                         ins->inst_destbasereg = temp2->dreg;
1456                         break;
1457                 case OP_LOADI1_MEMBASE:
1458                 case OP_LOADU1_MEMBASE:
1459                 case OP_LOADI2_MEMBASE:
1460                 case OP_LOADU2_MEMBASE:
1461                 case OP_LOADI4_MEMBASE:
1462                 case OP_LOADU4_MEMBASE:
1463                 case OP_LOADI8_MEMBASE:
1464                 case OP_LOAD_MEMBASE:
1465                 case OP_LOADR4_MEMBASE:
1466                 case OP_LOADR8_MEMBASE:
1467                 case OP_ATOMIC_EXCHANGE_I4:
1468                 case OP_ATOMIC_EXCHANGE_I8:
1469                 case OP_ATOMIC_ADD_NEW_I4:
1470                 case OP_ATOMIC_ADD_NEW_I8:
1471                 case OP_ATOMIC_ADD_IMM_NEW_I4:
1472                 case OP_ATOMIC_ADD_IMM_NEW_I8:
1473                         /* There are no membase instructions on ia64 */
1474                         if (ins->inst_offset == 0) {
1475                                 break;
1476                         }
1477                         else if (ia64_is_imm14 (ins->inst_offset)) {
1478                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1479                                 temp2->sreg1 = ins->inst_basereg;
1480                                 temp2->inst_imm = ins->inst_offset;
1481                                 temp2->dreg = mono_alloc_ireg (cfg);
1482                         }
1483                         else {
1484                                 NEW_INS (cfg, temp, OP_I8CONST);
1485                                 temp->inst_c0 = ins->inst_offset;
1486                                 temp->dreg = mono_alloc_ireg (cfg);
1487                                 NEW_INS (cfg, temp2, OP_LADD);
1488                                 temp2->sreg1 = ins->inst_basereg;
1489                                 temp2->sreg2 = temp->dreg;
1490                                 temp2->dreg = mono_alloc_ireg (cfg);
1491                         }
1492
1493                         ins->inst_offset = 0;
1494                         ins->inst_basereg = temp2->dreg;
1495                         break;
1496                 case OP_ADD_IMM:
1497                 case OP_IADD_IMM:
1498                 case OP_LADD_IMM:
1499                 case OP_ISUB_IMM:
1500                 case OP_LSUB_IMM:
1501                 case OP_AND_IMM:
1502                 case OP_IAND_IMM:
1503                 case OP_LAND_IMM:
1504                 case OP_IOR_IMM:
1505                 case OP_LOR_IMM:
1506                 case OP_IXOR_IMM:
1507                 case OP_LXOR_IMM:
1508                 case OP_SHL_IMM:
1509                 case OP_SHR_IMM:
1510                 case OP_ISHL_IMM:
1511                 case OP_LSHL_IMM:
1512                 case OP_ISHR_IMM:
1513                 case OP_LSHR_IMM:
1514                 case OP_ISHR_UN_IMM:
1515                 case OP_LSHR_UN_IMM: {
1516                         gboolean is_imm = FALSE;
1517                         gboolean switched = FALSE;
1518
1519                         if (ins->opcode == OP_AND_IMM && ins->inst_imm == 255) {
1520                                 ins->opcode = OP_ZEXT_I1;
1521                                 break;
1522                         }
1523
1524                         switch (ins->opcode) {
1525                         case OP_ADD_IMM:
1526                         case OP_IADD_IMM:
1527                         case OP_LADD_IMM:
1528                                 is_imm = ia64_is_imm14 (ins->inst_imm);
1529                                 switched = TRUE;
1530                                 break;
1531                         case OP_ISUB_IMM:
1532                         case OP_LSUB_IMM:
1533                                 is_imm = ia64_is_imm14 (- (ins->inst_imm));
1534                                 if (is_imm) {
1535                                         /* A = B - IMM -> A = B + (-IMM) */
1536                                         ins->inst_imm = - ins->inst_imm;
1537                                         ins->opcode = OP_IADD_IMM;
1538                                 }
1539                                 switched = TRUE;
1540                                 break;
1541                         case OP_IAND_IMM:
1542                         case OP_IOR_IMM:
1543                         case OP_IXOR_IMM:
1544                         case OP_AND_IMM:
1545                         case OP_LAND_IMM:
1546                         case OP_LOR_IMM:
1547                         case OP_LXOR_IMM:
1548                                 is_imm = ia64_is_imm8 (ins->inst_imm);
1549                                 switched = TRUE;
1550                                 break;
1551                         case OP_SHL_IMM:
1552                         case OP_SHR_IMM:
1553                         case OP_ISHL_IMM:
1554                         case OP_LSHL_IMM:
1555                         case OP_ISHR_IMM:
1556                         case OP_LSHR_IMM:
1557                         case OP_ISHR_UN_IMM:
1558                         case OP_LSHR_UN_IMM:
1559                                 is_imm = (ins->inst_imm >= 0) && (ins->inst_imm < 64);
1560                                 break;
1561                         default:
1562                                 break;
1563                         }
1564
1565                         if (is_imm) {
1566                                 if (switched)
1567                                         ins->sreg2 = ins->sreg1;
1568                                 break;
1569                         }
1570
1571                         ins->opcode = mono_op_imm_to_op (ins->opcode);
1572
1573                         if (ins->inst_imm == 0)
1574                                 ins->sreg2 = IA64_R0;
1575                         else {
1576                                 NEW_INS (cfg, temp, OP_I8CONST);
1577                                 temp->inst_c0 = ins->inst_imm;
1578                                 temp->dreg = mono_alloc_ireg (cfg);
1579                                 ins->sreg2 = temp->dreg;
1580                         }
1581                         break;
1582                 }
1583                 case OP_COMPARE_IMM:
1584                 case OP_ICOMPARE_IMM:
1585                 case OP_LCOMPARE_IMM: {
1586                         /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1587                         gboolean imm;
1588                         CompRelation cond;
1589
1590                         next = ins->next;
1591
1592                         /* Branch opts can eliminate the branch */
1593                         if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1594                                 NULLIFY_INS (ins);
1595                                 break;
1596                         }
1597
1598                         /*
1599                          * The compare_imm instructions have switched up arguments, and
1600                          * some of them take an imm between -127 and 128.
1601                          */
1602                         next = ins->next;
1603                         cond = mono_opcode_to_cond (next->opcode);
1604                         if ((cond == CMP_LT) || (cond == CMP_GE))
1605                                 imm = ia64_is_imm8 (ins->inst_imm - 1);
1606                         else if ((cond == CMP_LT_UN) || (cond == CMP_GE_UN))
1607                                 imm = ia64_is_imm8 (ins->inst_imm - 1) && (ins->inst_imm > 0);
1608                         else
1609                                 imm = ia64_is_imm8 (ins->inst_imm);
1610
1611                         if (imm) {
1612                                 ins->opcode = opcode_to_ia64_cmp_imm (next->opcode, ins->opcode);
1613                                 ins->sreg2 = ins->sreg1;
1614                         }
1615                         else {
1616                                 ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1617
1618                                 if (ins->inst_imm == 0)
1619                                         ins->sreg2 = IA64_R0;
1620                                 else {
1621                                         NEW_INS (cfg, temp, OP_I8CONST);
1622                                         temp->inst_c0 = ins->inst_imm;
1623                                         temp->dreg = mono_alloc_ireg (cfg);
1624                                         ins->sreg2 = temp->dreg;
1625                                 }
1626                         }
1627
1628                         if (MONO_IS_COND_BRANCH_OP (next)) {
1629                                 next->opcode = OP_IA64_BR_COND;
1630                                 next->inst_target_bb = next->inst_true_bb;
1631                         } else if (MONO_IS_COND_EXC (next)) {
1632                                 next->opcode = OP_IA64_COND_EXC;
1633                         } else if (MONO_IS_SETCC (next)) {
1634                                 next->opcode = OP_IA64_CSET;
1635                         } else {
1636                                 printf ("%s\n", mono_inst_name (next->opcode));
1637                                 NOT_IMPLEMENTED;
1638                         }
1639
1640                         break;
1641                 }
1642                 case OP_COMPARE:
1643                 case OP_ICOMPARE:
1644                 case OP_LCOMPARE:
1645                 case OP_FCOMPARE: {
1646                         /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1647
1648                         next = ins->next;
1649
1650                         /* Branch opts can eliminate the branch */
1651                         if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1652                                 NULLIFY_INS (ins);
1653                                 break;
1654                         }
1655
1656                         ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1657
1658                         if (MONO_IS_COND_BRANCH_OP (next)) {
1659                                 next->opcode = OP_IA64_BR_COND;
1660                                 next->inst_target_bb = next->inst_true_bb;
1661                         } else if (MONO_IS_COND_EXC (next)) {
1662                                 next->opcode = OP_IA64_COND_EXC;
1663                         } else if (MONO_IS_SETCC (next)) {
1664                                 next->opcode = OP_IA64_CSET;
1665                         } else {
1666                                 printf ("%s\n", mono_inst_name (next->opcode));
1667                                 NOT_IMPLEMENTED;
1668                         }
1669
1670                         break;
1671                 }
1672                 case OP_FCEQ:
1673                 case OP_FCGT:
1674                 case OP_FCGT_UN:
1675                 case OP_FCLT:
1676                 case OP_FCLT_UN:
1677                         /* The front end removes the fcompare, so introduce it again */
1678                         NEW_INS (cfg, temp, opcode_to_ia64_cmp (ins->opcode, OP_FCOMPARE));
1679                         temp->sreg1 = ins->sreg1;
1680                         temp->sreg2 = ins->sreg2;
1681
1682                         ins->opcode = OP_IA64_CSET;
1683                         MONO_INST_NULLIFY_SREGS (ins);
1684                         break;
1685                 case OP_MUL_IMM:
1686                 case OP_LMUL_IMM:
1687                 case OP_IMUL_IMM: {
1688                         int i, sum_reg;
1689                         gboolean found = FALSE;
1690                         int shl_op = ins->opcode == OP_IMUL_IMM ? OP_ISHL_IMM : OP_SHL_IMM;
1691
1692                         /* First the easy cases */
1693                         if (ins->inst_imm == 1) {
1694                                 ins->opcode = OP_MOVE;
1695                                 break;
1696                         }
1697                         for (i = 1; i < 64; ++i)
1698                                 if (ins->inst_imm == (((gint64)1) << i)) {
1699                                         ins->opcode = shl_op;
1700                                         ins->inst_imm = i;
1701                                         found = TRUE;
1702                                         break;
1703                                 }
1704
1705                         /* This could be optimized */
1706                         if (!found) {
1707                                 sum_reg = 0;
1708                                 for (i = 0; i < 64; ++i) {
1709                                         if (ins->inst_imm & (((gint64)1) << i)) {
1710                                                 NEW_INS (cfg, temp, shl_op);
1711                                                 temp->dreg = mono_alloc_ireg (cfg);
1712                                                 temp->sreg1 = ins->sreg1;
1713                                                 temp->inst_imm = i;
1714
1715                                                 if (sum_reg == 0)
1716                                                         sum_reg = temp->dreg;
1717                                                 else {
1718                                                         NEW_INS (cfg, temp2, OP_LADD);
1719                                                         temp2->dreg = mono_alloc_ireg (cfg);
1720                                                         temp2->sreg1 = sum_reg;
1721                                                         temp2->sreg2 = temp->dreg;
1722                                                         sum_reg = temp2->dreg;
1723                                                 }
1724                                         }
1725                                 }
1726                                 ins->opcode = OP_MOVE;
1727                                 ins->sreg1 = sum_reg;
1728                         }
1729                         break;
1730                 }
1731                 case OP_LCONV_TO_OVF_U4:
1732                         NEW_INS (cfg, temp, OP_IA64_CMP4_LT);
1733                         temp->sreg1 = ins->sreg1;
1734                         temp->sreg2 = IA64_R0;
1735
1736                         NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1737                         temp->inst_p1 = (char*)"OverflowException";
1738
1739                         ins->opcode = OP_MOVE;
1740                         break;
1741                 case OP_LCONV_TO_OVF_I4_UN:
1742                         NEW_INS (cfg, temp, OP_ICONST);
1743                         temp->inst_c0 = 0x7fffffff;
1744                         temp->dreg = mono_alloc_ireg (cfg);
1745
1746                         NEW_INS (cfg, temp2, OP_IA64_CMP4_GT_UN);
1747                         temp2->sreg1 = ins->sreg1;
1748                         temp2->sreg2 = temp->dreg;
1749
1750                         NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1751                         temp->inst_p1 = (char*)"OverflowException";
1752
1753                         ins->opcode = OP_MOVE;
1754                         break;
1755                 case OP_FCONV_TO_I4:
1756                 case OP_FCONV_TO_I2:
1757                 case OP_FCONV_TO_U2:
1758                 case OP_FCONV_TO_I1:
1759                 case OP_FCONV_TO_U1:
1760                         NEW_INS (cfg, temp, OP_FCONV_TO_I8);
1761                         temp->sreg1 = ins->sreg1;
1762                         temp->dreg = ins->dreg;
1763
1764                         switch (ins->opcode) {
1765                         case OP_FCONV_TO_I4:
1766                                 ins->opcode = OP_SEXT_I4;
1767                                 break;
1768                         case OP_FCONV_TO_I2:
1769                                 ins->opcode = OP_SEXT_I2;
1770                                 break;
1771                         case OP_FCONV_TO_U2:
1772                                 ins->opcode = OP_ZEXT_I4;
1773                                 break;
1774                         case OP_FCONV_TO_I1:
1775                                 ins->opcode = OP_SEXT_I1;
1776                                 break;
1777                         case OP_FCONV_TO_U1:
1778                                 ins->opcode = OP_ZEXT_I1;
1779                                 break;
1780                         default:
1781                                 g_assert_not_reached ();
1782                         }
1783                         ins->sreg1 = ins->dreg;
1784                         break;
1785                 default:
1786                         break;
1787                 }
1788                 last_ins = ins;
1789                 ins = ins->next;
1790         }
1791         bb->last_ins = last_ins;
1792
1793         bb->max_vreg = cfg->next_vreg;
1794 }
1795
1796 /*
1797  * emit_load_volatile_arguments:
1798  *
1799  *  Load volatile arguments from the stack to the original input registers.
1800  * Required before a tail call.
1801  */
1802 static Ia64CodegenState
1803 emit_load_volatile_arguments (MonoCompile *cfg, Ia64CodegenState code)
1804 {
1805         MonoMethod *method = cfg->method;
1806         MonoMethodSignature *sig;
1807         MonoInst *ins;
1808         CallInfo *cinfo;
1809         guint32 i;
1810
1811         /* FIXME: Generate intermediate code instead */
1812
1813         sig = mono_method_signature (method);
1814
1815         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
1816
1817         /* This is the opposite of the code in emit_prolog */
1818         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1819                 ArgInfo *ainfo = cinfo->args + i;
1820                 gint32 stack_offset;
1821                 MonoType *arg_type;
1822
1823                 ins = cfg->args [i];
1824
1825                 if (sig->hasthis && (i == 0))
1826                         arg_type = &mono_defaults.object_class->byval_arg;
1827                 else
1828                         arg_type = sig->params [i - sig->hasthis];
1829
1830                 arg_type = mono_type_get_underlying_type (arg_type);
1831
1832                 stack_offset = ainfo->offset + ARGS_OFFSET;
1833
1834                 /* Save volatile arguments to the stack */
1835                 if (ins->opcode != OP_REGVAR) {
1836                         switch (ainfo->storage) {
1837                         case ArgInIReg:
1838                         case ArgInFloatReg:
1839                                 /* FIXME: big offsets */
1840                                 g_assert (ins->opcode == OP_REGOFFSET);
1841                                 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
1842                                 if (arg_type->byref)
1843                                         ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1844                                 else {
1845                                         switch (arg_type->type) {
1846                                         case MONO_TYPE_R4:
1847                                                 ia64_ldfs (code, ainfo->reg, GP_SCRATCH_REG);
1848                                                 break;
1849                                         case MONO_TYPE_R8:
1850                                                 ia64_ldfd (code, ainfo->reg, GP_SCRATCH_REG);
1851                                                 break;
1852                                         default:
1853                                                 ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1854                                                 break;
1855                                         }
1856                                 }
1857                                 break;
1858                         case ArgOnStack:
1859                                 break;
1860                         default:
1861                                 NOT_IMPLEMENTED;
1862                         }
1863                 }
1864
1865                 if (ins->opcode == OP_REGVAR) {
1866                         /* Argument allocated to (non-volatile) register */
1867                         switch (ainfo->storage) {
1868                         case ArgInIReg:
1869                                 if (ins->dreg != cfg->arch.reg_in0 + ainfo->reg)
1870                                         ia64_mov (code, cfg->arch.reg_in0 + ainfo->reg, ins->dreg);
1871                                 break;
1872                         case ArgOnStack:
1873                                 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
1874                                 ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
1875                                 break;
1876                         default:
1877                                 NOT_IMPLEMENTED;
1878                         }
1879                 }
1880         }
1881
1882         return code;
1883 }
1884
1885 static Ia64CodegenState
1886 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, Ia64CodegenState code)
1887 {
1888         CallInfo *cinfo;
1889         int i;
1890
1891         /* Move return value to the target register */
1892         switch (ins->opcode) {
1893         case OP_VOIDCALL:
1894         case OP_VOIDCALL_REG:
1895         case OP_VOIDCALL_MEMBASE:
1896                 break;
1897         case OP_CALL:
1898         case OP_CALL_REG:
1899         case OP_CALL_MEMBASE:
1900         case OP_LCALL:
1901         case OP_LCALL_REG:
1902         case OP_LCALL_MEMBASE:
1903                 g_assert (ins->dreg == IA64_R8);
1904                 break;
1905         case OP_FCALL:
1906         case OP_FCALL_REG:
1907         case OP_FCALL_MEMBASE:
1908                 g_assert (ins->dreg == 8);
1909                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4)
1910                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
1911                 break;
1912         case OP_VCALL:
1913         case OP_VCALL_REG:
1914         case OP_VCALL_MEMBASE:
1915         case OP_VCALL2:
1916         case OP_VCALL2_REG:
1917         case OP_VCALL2_MEMBASE: {
1918                 ArgStorage storage;
1919
1920                 cinfo = get_call_info (cfg, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
1921                 storage = cinfo->ret.storage;
1922
1923                 if (storage == ArgAggregate) {
1924                         MonoInst *local = (MonoInst*)cfg->arch.ret_var_addr_local;
1925
1926                         /* Load address of stack space allocated for the return value */
1927                         ia64_movl (code, GP_SCRATCH_REG, local->inst_offset);
1928                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, local->inst_basereg);
1929                         ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
1930
1931                         for (i = 0; i < cinfo->ret.nregs; ++i) {
1932                                 switch (cinfo->ret.atype) {
1933                                 case AggregateNormal:
1934                                         ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1935                                         break;
1936                                 case AggregateSingleHFA:
1937                                         ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 4, 0);
1938                                         break;
1939                                 case AggregateDoubleHFA:
1940                                         ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1941                                         break;
1942                                 default:
1943                                         g_assert_not_reached ();
1944                                 }
1945                         }
1946                 }
1947                 break;
1948         }
1949         default:
1950                 g_assert_not_reached ();
1951         }
1952
1953         return code;
1954 }
1955
1956 #define add_patch_info(cfg,code,patch_type,data) do { \
1957         mono_add_patch_info (cfg, code.buf + code.nins - cfg->native_code, patch_type, data); \
1958 } while (0)
1959
1960 #define emit_cond_system_exception(cfg,code,exc_name,predicate) do { \
1961         MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1962     if (tins == NULL) \
1963         add_patch_info (cfg, code, MONO_PATCH_INFO_EXC, exc_name); \
1964     else \
1965                 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, tins->inst_true_bb); \
1966         ia64_br_cond_pred (code, (predicate), 0); \
1967 } while (0)
1968
1969 static Ia64CodegenState
1970 emit_call (MonoCompile *cfg, Ia64CodegenState code, guint32 patch_type, gconstpointer data)
1971 {
1972         add_patch_info (cfg, code, patch_type, data);
1973
1974         if ((patch_type == MONO_PATCH_INFO_ABS) || (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD)) {
1975                 /* Indirect call */
1976                 /* mono_arch_patch_callsite will patch this */
1977                 /* mono_arch_nullify_class_init_trampoline will patch this */
1978                 ia64_movl (code, GP_SCRATCH_REG, 0);
1979                 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
1980                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
1981                 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
1982                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
1983         }
1984         else {
1985                 /* Can't use a direct call since the displacement might be too small */
1986                 /* mono_arch_patch_callsite will patch this */
1987                 ia64_movl (code, GP_SCRATCH_REG, 0);
1988                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
1989                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
1990         }
1991
1992         return code;
1993 }
1994
1995 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
1996
1997 void
1998 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
1999 {
2000         MonoInst *ins;
2001         MonoCallInst *call;
2002         guint offset;
2003         Ia64CodegenState code;
2004         guint8 *code_start = cfg->native_code + cfg->code_len;
2005         MonoInst *last_ins = NULL;
2006         guint last_offset = 0;
2007         int max_len, cpos;
2008
2009         if (cfg->opt & MONO_OPT_LOOP) {
2010                 /* FIXME: */
2011         }
2012
2013         if (cfg->verbose_level > 2)
2014                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2015
2016         cpos = bb->max_offset;
2017
2018         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2019                 NOT_IMPLEMENTED;
2020         }
2021
2022         offset = code_start - cfg->native_code;
2023
2024         ia64_codegen_init (code, code_start);
2025
2026 #if 0
2027         if (strstr (cfg->method->name, "conv_ovf_i1") && (bb->block_num == 2))
2028                 break_count ();
2029 #endif
2030
2031         MONO_BB_FOR_EACH_INS (bb, ins) {
2032                 offset = code.buf - cfg->native_code;
2033
2034                 max_len = ((int)(((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN])) + 128;
2035
2036                 while (offset + max_len + 16 > cfg->code_size) {
2037                         ia64_codegen_close (code);
2038
2039                         offset = code.buf - cfg->native_code;
2040
2041                         cfg->code_size *= 2;
2042                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2043                         code_start = cfg->native_code + offset;
2044                         mono_jit_stats.code_reallocs++;
2045
2046                         ia64_codegen_init (code, code_start);
2047                 }
2048
2049                 mono_debug_record_line_number (cfg, ins, offset);
2050
2051                 switch (ins->opcode) {
2052                 case OP_ICONST:
2053                 case OP_I8CONST:
2054                         if (ia64_is_imm14 (ins->inst_c0))
2055                                 ia64_adds_imm (code, ins->dreg, ins->inst_c0, IA64_R0);
2056                         else
2057                                 ia64_movl (code, ins->dreg, ins->inst_c0);
2058                         break;
2059                 case OP_JUMP_TABLE:
2060                         add_patch_info (cfg, code, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2061                         ia64_movl (code, ins->dreg, 0);
2062                         break;
2063                 case OP_MOVE:
2064                         ia64_mov (code, ins->dreg, ins->sreg1);
2065                         break;
2066                 case OP_BR:
2067                 case OP_IA64_BR_COND: {
2068                         int pred = 0;
2069                         if (ins->opcode == OP_IA64_BR_COND)
2070                                 pred = 6;
2071                         if (ins->inst_target_bb->native_offset) {
2072                                 guint8 *pos = code.buf + code.nins;
2073
2074                                 ia64_br_cond_pred (code, pred, 0);
2075                                 ia64_begin_bundle (code);
2076                                 ia64_patch (pos, cfg->native_code + ins->inst_target_bb->native_offset);
2077                         } else {
2078                                 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2079                                 ia64_br_cond_pred (code, pred, 0);
2080                         }
2081                         break;
2082                 }
2083                 case OP_LABEL:
2084                         ia64_begin_bundle (code);
2085                         ins->inst_c0 = code.buf - cfg->native_code;
2086                         break;
2087                 case OP_NOP:
2088                 case OP_RELAXED_NOP:
2089                 case OP_DUMMY_USE:
2090                 case OP_DUMMY_STORE:
2091                 case OP_NOT_REACHED:
2092                 case OP_NOT_NULL:
2093                         break;
2094                 case OP_BR_REG:
2095                         ia64_mov_to_br (code, IA64_B6, ins->sreg1);
2096                         ia64_br_cond_reg (code, IA64_B6);
2097                         break;
2098                 case OP_IADD:
2099                 case OP_LADD:
2100                         ia64_add (code, ins->dreg, ins->sreg1, ins->sreg2);
2101                         break;
2102                 case OP_ISUB:
2103                 case OP_LSUB:
2104                         ia64_sub (code, ins->dreg, ins->sreg1, ins->sreg2);
2105                         break;
2106                 case OP_IAND:
2107                 case OP_LAND:
2108                         ia64_and (code, ins->dreg, ins->sreg1, ins->sreg2);
2109                         break;
2110                 case OP_IOR:
2111                 case OP_LOR:
2112                         ia64_or (code, ins->dreg, ins->sreg1, ins->sreg2);
2113                         break;
2114                 case OP_IXOR:
2115                 case OP_LXOR:
2116                         ia64_xor (code, ins->dreg, ins->sreg1, ins->sreg2);
2117                         break;
2118                 case OP_INEG:
2119                 case OP_LNEG:
2120                         ia64_sub (code, ins->dreg, IA64_R0, ins->sreg1);
2121                         break;
2122                 case OP_INOT:
2123                 case OP_LNOT:
2124                         ia64_andcm_imm (code, ins->dreg, -1, ins->sreg1);
2125                         break;
2126                 case OP_ISHL:
2127                 case OP_LSHL:
2128                         ia64_shl (code, ins->dreg, ins->sreg1, ins->sreg2);
2129                         break;
2130                 case OP_ISHR:
2131                 case OP_LSHR:
2132                         ia64_shr (code, ins->dreg, ins->sreg1, ins->sreg2);
2133                         break;
2134                 case OP_ISHR_UN:
2135                         ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2136                         ia64_shr_u (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2137                         break;
2138                 case OP_LSHR_UN:
2139                         ia64_shr_u (code, ins->dreg, ins->sreg1, ins->sreg2);
2140                         break;
2141                 case OP_IADDCC:
2142                         /* p6 and p7 is set if there is signed/unsigned overflow */
2143
2144                         /* Set p8-p9 == (sreg2 > 0) */
2145                         ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2146
2147                         ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2148
2149                         /* (sreg2 > 0) && (res < ins->sreg1) => signed overflow */
2150                         ia64_cmp4_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2151                         /* (sreg2 <= 0) && (res > ins->sreg1) => signed overflow */
2152                         ia64_cmp4_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2153
2154                         /* res <u sreg1 => unsigned overflow */
2155                         ia64_cmp4_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2156
2157                         /* FIXME: Predicate this since this is a side effect */
2158                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2159                         break;
2160                 case OP_ISUBCC:
2161                         /* p6 and p7 is set if there is signed/unsigned overflow */
2162
2163                         /* Set p8-p9 == (sreg2 > 0) */
2164                         ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2165
2166                         ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2167
2168                         /* (sreg2 > 0) && (res > ins->sreg1) => signed overflow */
2169                         ia64_cmp4_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2170                         /* (sreg2 <= 0) && (res < ins->sreg1) => signed overflow */
2171                         ia64_cmp4_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2172
2173                         /* sreg1 <u sreg2 => unsigned overflow */
2174                         ia64_cmp4_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2175
2176                         /* FIXME: Predicate this since this is a side effect */
2177                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2178                         break;
2179                 case OP_ADDCC:
2180                         /* Same as OP_IADDCC */
2181                         ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2182
2183                         ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2184
2185                         ia64_cmp_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2186                         ia64_cmp_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2187
2188                         ia64_cmp_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2189
2190                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2191                         break;
2192                 case OP_SUBCC:
2193                         /* Same as OP_ISUBCC */
2194
2195                         ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2196
2197                         ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2198
2199                         ia64_cmp_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2200                         ia64_cmp_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2201
2202                         ia64_cmp_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2203
2204                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2205                         break;
2206                 case OP_ADD_IMM:
2207                 case OP_IADD_IMM:
2208                 case OP_LADD_IMM:
2209                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2210                         break;
2211                 case OP_IAND_IMM:
2212                 case OP_AND_IMM:
2213                 case OP_LAND_IMM:
2214                         ia64_and_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2215                         break;
2216                 case OP_IOR_IMM:
2217                 case OP_LOR_IMM:
2218                         ia64_or_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2219                         break;
2220                 case OP_IXOR_IMM:
2221                 case OP_LXOR_IMM:
2222                         ia64_xor_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2223                         break;
2224                 case OP_SHL_IMM:
2225                 case OP_ISHL_IMM:
2226                 case OP_LSHL_IMM:
2227                         ia64_shl_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2228                         break;
2229                 case OP_SHR_IMM:
2230                 case OP_ISHR_IMM:
2231                 case OP_LSHR_IMM:
2232                         ia64_shr_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2233                         break;
2234                 case OP_ISHR_UN_IMM:
2235                         ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2236                         ia64_shr_u_imm (code, ins->dreg, GP_SCRATCH_REG, ins->inst_imm);
2237                         break;
2238                 case OP_LSHR_UN_IMM:
2239                         ia64_shr_u_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2240                         break;
2241                 case OP_LMUL:
2242                         /* Based on gcc code */
2243                         ia64_setf_sig (code, FP_SCRATCH_REG, ins->sreg1);
2244                         ia64_setf_sig (code, FP_SCRATCH_REG2, ins->sreg2);
2245                         ia64_xmpy_l (code, FP_SCRATCH_REG, FP_SCRATCH_REG, FP_SCRATCH_REG2);
2246                         ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2247                         break;
2248
2249                 case OP_STOREI1_MEMBASE_REG:
2250                         ia64_st1_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2251                         break;
2252                 case OP_STOREI2_MEMBASE_REG:
2253                         ia64_st2_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2254                         break;
2255                 case OP_STOREI4_MEMBASE_REG:
2256                         ia64_st4_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2257                         break;
2258                 case OP_STOREI8_MEMBASE_REG:
2259                 case OP_STORE_MEMBASE_REG:
2260                         if (ins->inst_offset != 0) {
2261                                 /* This is generated by local regalloc */
2262                                 if (ia64_is_imm14 (ins->inst_offset)) {
2263                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2264                                 } else {
2265                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2266                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2267                                 }
2268                                 ins->inst_destbasereg = GP_SCRATCH_REG;
2269                         }
2270                         ia64_st8_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2271                         break;
2272
2273                 case OP_IA64_STOREI1_MEMBASE_INC_REG:
2274                         ia64_st1_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 1, 0);
2275                         break;
2276                 case OP_IA64_STOREI2_MEMBASE_INC_REG:
2277                         ia64_st2_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 2, 0);
2278                         break;
2279                 case OP_IA64_STOREI4_MEMBASE_INC_REG:
2280                         ia64_st4_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 4, 0);
2281                         break;
2282                 case OP_IA64_STOREI8_MEMBASE_INC_REG:
2283                         ia64_st8_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 8, 0);
2284                         break;
2285
2286                 case OP_LOADU1_MEMBASE:
2287                         ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2288                         break;
2289                 case OP_LOADU2_MEMBASE:
2290                         ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2291                         break;
2292                 case OP_LOADU4_MEMBASE:
2293                         ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2294                         break;
2295                 case OP_LOADI1_MEMBASE:
2296                         ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2297                         ia64_sxt1 (code, ins->dreg, ins->dreg);
2298                         break;
2299                 case OP_LOADI2_MEMBASE:
2300                         ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2301                         ia64_sxt2 (code, ins->dreg, ins->dreg);
2302                         break;
2303                 case OP_LOADI4_MEMBASE:
2304                         ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2305                         ia64_sxt4 (code, ins->dreg, ins->dreg);
2306                         break;
2307                 case OP_LOAD_MEMBASE:
2308                 case OP_LOADI8_MEMBASE:
2309                         if (ins->inst_offset != 0) {
2310                                 /* This is generated by local regalloc */
2311                                 if (ia64_is_imm14 (ins->inst_offset)) {
2312                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2313                                 } else {
2314                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2315                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2316                                 }
2317                                 ins->inst_basereg = GP_SCRATCH_REG;
2318                         }
2319                         ia64_ld8 (code, ins->dreg, ins->inst_basereg);
2320                         break;
2321
2322                 case OP_IA64_LOADU1_MEMBASE_INC:
2323                         ia64_ld1_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 1, 0);
2324                         break;
2325                 case OP_IA64_LOADU2_MEMBASE_INC:
2326                         ia64_ld2_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 2, 0);
2327                         break;
2328                 case OP_IA64_LOADU4_MEMBASE_INC:
2329                         ia64_ld4_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 4, 0);
2330                         break;
2331                 case OP_IA64_LOADI8_MEMBASE_INC:
2332                         ia64_ld8_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 8, 0);
2333                         break;
2334
2335                 case OP_SEXT_I1:
2336                         ia64_sxt1 (code, ins->dreg, ins->sreg1);
2337                         break;
2338                 case OP_SEXT_I2:
2339                         ia64_sxt2 (code, ins->dreg, ins->sreg1);
2340                         break;
2341                 case OP_SEXT_I4:
2342                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2343                         break;
2344                 case OP_ZEXT_I1:
2345                         ia64_zxt1 (code, ins->dreg, ins->sreg1);
2346                         break;
2347                 case OP_ZEXT_I2:
2348                         ia64_zxt2 (code, ins->dreg, ins->sreg1);
2349                         break;
2350                 case OP_ZEXT_I4:
2351                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2352                         break;
2353
2354                         /* Compare opcodes */
2355                 case OP_IA64_CMP4_EQ:
2356                         ia64_cmp4_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2357                         break;
2358                 case OP_IA64_CMP4_NE:
2359                         ia64_cmp4_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2360                         break;
2361                 case OP_IA64_CMP4_LE:
2362                         ia64_cmp4_le (code, 6, 7, ins->sreg1, ins->sreg2);
2363                         break;
2364                 case OP_IA64_CMP4_LT:
2365                         ia64_cmp4_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2366                         break;
2367                 case OP_IA64_CMP4_GE:
2368                         ia64_cmp4_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2369                         break;
2370                 case OP_IA64_CMP4_GT:
2371                         ia64_cmp4_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2372                         break;
2373                 case OP_IA64_CMP4_LT_UN:
2374                         ia64_cmp4_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2375                         break;
2376                 case OP_IA64_CMP4_LE_UN:
2377                         ia64_cmp4_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2378                         break;
2379                 case OP_IA64_CMP4_GT_UN:
2380                         ia64_cmp4_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2381                         break;
2382                 case OP_IA64_CMP4_GE_UN:
2383                         ia64_cmp4_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2384                         break;
2385                 case OP_IA64_CMP_EQ:
2386                         ia64_cmp_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2387                         break;
2388                 case OP_IA64_CMP_NE:
2389                         ia64_cmp_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2390                         break;
2391                 case OP_IA64_CMP_LE:
2392                         ia64_cmp_le (code, 6, 7, ins->sreg1, ins->sreg2);
2393                         break;
2394                 case OP_IA64_CMP_LT:
2395                         ia64_cmp_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2396                         break;
2397                 case OP_IA64_CMP_GE:
2398                         ia64_cmp_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2399                         break;
2400                 case OP_IA64_CMP_GT:
2401                         ia64_cmp_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2402                         break;
2403                 case OP_IA64_CMP_GT_UN:
2404                         ia64_cmp_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2405                         break;
2406                 case OP_IA64_CMP_LT_UN:
2407                         ia64_cmp_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2408                         break;
2409                 case OP_IA64_CMP_GE_UN:
2410                         ia64_cmp_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2411                         break;
2412                 case OP_IA64_CMP_LE_UN:
2413                         ia64_cmp_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2414                         break;
2415                 case OP_IA64_CMP4_EQ_IMM:
2416                         ia64_cmp4_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2417                         break;
2418                 case OP_IA64_CMP4_NE_IMM:
2419                         ia64_cmp4_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2420                         break;
2421                 case OP_IA64_CMP4_LE_IMM:
2422                         ia64_cmp4_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2423                         break;
2424                 case OP_IA64_CMP4_LT_IMM:
2425                         ia64_cmp4_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2426                         break;
2427                 case OP_IA64_CMP4_GE_IMM:
2428                         ia64_cmp4_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2429                         break;
2430                 case OP_IA64_CMP4_GT_IMM:
2431                         ia64_cmp4_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2432                         break;
2433                 case OP_IA64_CMP4_LT_UN_IMM:
2434                         ia64_cmp4_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2435                         break;
2436                 case OP_IA64_CMP4_LE_UN_IMM:
2437                         ia64_cmp4_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2438                         break;
2439                 case OP_IA64_CMP4_GT_UN_IMM:
2440                         ia64_cmp4_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2441                         break;
2442                 case OP_IA64_CMP4_GE_UN_IMM:
2443                         ia64_cmp4_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2444                         break;
2445                 case OP_IA64_CMP_EQ_IMM:
2446                         ia64_cmp_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2447                         break;
2448                 case OP_IA64_CMP_NE_IMM:
2449                         ia64_cmp_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2450                         break;
2451                 case OP_IA64_CMP_LE_IMM:
2452                         ia64_cmp_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2453                         break;
2454                 case OP_IA64_CMP_LT_IMM:
2455                         ia64_cmp_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2456                         break;
2457                 case OP_IA64_CMP_GE_IMM:
2458                         ia64_cmp_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2459                         break;
2460                 case OP_IA64_CMP_GT_IMM:
2461                         ia64_cmp_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2462                         break;
2463                 case OP_IA64_CMP_GT_UN_IMM:
2464                         ia64_cmp_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2465                         break;
2466                 case OP_IA64_CMP_LT_UN_IMM:
2467                         ia64_cmp_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2468                         break;
2469                 case OP_IA64_CMP_GE_UN_IMM:
2470                         ia64_cmp_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2471                         break;
2472                 case OP_IA64_CMP_LE_UN_IMM:
2473                         ia64_cmp_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2474                         break;
2475                 case OP_IA64_FCMP_EQ:
2476                         ia64_fcmp_eq_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2477                         break;
2478                 case OP_IA64_FCMP_NE:
2479                         ia64_fcmp_ne_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2480                         break;
2481                 case OP_IA64_FCMP_LT:
2482                         ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2483                         break;
2484                 case OP_IA64_FCMP_GT:
2485                         ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2486                         break;
2487                 case OP_IA64_FCMP_LE:
2488                         ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2489                         break;
2490                 case OP_IA64_FCMP_GE:
2491                         ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2492                         break;
2493                 case OP_IA64_FCMP_GT_UN:
2494                         ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2495                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2496                         break;
2497                 case OP_IA64_FCMP_LT_UN:
2498                         ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2499                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2500                         break;
2501                 case OP_IA64_FCMP_GE_UN:
2502                         ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2503                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2504                         break;
2505                 case OP_IA64_FCMP_LE_UN:
2506                         ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2507                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2508                         break;
2509
2510                 case OP_COND_EXC_IOV:
2511                 case OP_COND_EXC_OV:
2512                         emit_cond_system_exception (cfg, code, "OverflowException", 6);
2513                         break;
2514                 case OP_COND_EXC_IC:
2515                 case OP_COND_EXC_C:
2516                         emit_cond_system_exception (cfg, code, "OverflowException", 7);
2517                         break;
2518                 case OP_IA64_COND_EXC:
2519                         emit_cond_system_exception (cfg, code, ins->inst_p1, 6);
2520                         break;
2521                 case OP_IA64_CSET:
2522                         ia64_mov_pred (code, 7, ins->dreg, IA64_R0);
2523                         ia64_no_stop (code);
2524                         ia64_add1_pred (code, 6, ins->dreg, IA64_R0, IA64_R0);
2525                         break;
2526                 case OP_ICONV_TO_I1:
2527                 case OP_LCONV_TO_I1:
2528                         /* FIXME: Is this needed ? */
2529                         ia64_sxt1 (code, ins->dreg, ins->sreg1);
2530                         break;
2531                 case OP_ICONV_TO_I2:
2532                 case OP_LCONV_TO_I2:
2533                         /* FIXME: Is this needed ? */
2534                         ia64_sxt2 (code, ins->dreg, ins->sreg1);
2535                         break;
2536                 case OP_LCONV_TO_I4:
2537                         /* FIXME: Is this needed ? */
2538                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2539                         break;
2540                 case OP_ICONV_TO_U1:
2541                 case OP_LCONV_TO_U1:
2542                         /* FIXME: Is this needed */
2543                         ia64_zxt1 (code, ins->dreg, ins->sreg1);
2544                         break;
2545                 case OP_ICONV_TO_U2:
2546                 case OP_LCONV_TO_U2:
2547                         /* FIXME: Is this needed */
2548                         ia64_zxt2 (code, ins->dreg, ins->sreg1);
2549                         break;
2550                 case OP_LCONV_TO_U4:
2551                         /* FIXME: Is this needed */
2552                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2553                         break;
2554                 case OP_ICONV_TO_I8:
2555                 case OP_ICONV_TO_I:
2556                 case OP_LCONV_TO_I8:
2557                 case OP_LCONV_TO_I:
2558                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2559                         break;
2560                 case OP_LCONV_TO_U8:
2561                 case OP_LCONV_TO_U:
2562                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2563                         break;
2564
2565                         /*
2566                          * FLOAT OPCODES
2567                          */
2568                 case OP_R8CONST: {
2569                         double d = *(double *)ins->inst_p0;
2570
2571                         if ((d == 0.0) && (mono_signbit (d) == 0))
2572                                 ia64_fmov (code, ins->dreg, 0);
2573                         else if (d == 1.0)
2574                                 ia64_fmov (code, ins->dreg, 1);
2575                         else {
2576                                 add_patch_info (cfg, code, MONO_PATCH_INFO_R8, ins->inst_p0);
2577                                 ia64_movl (code, GP_SCRATCH_REG, 0);
2578                                 ia64_ldfd (code, ins->dreg, GP_SCRATCH_REG);
2579                         }
2580                         break;
2581                 }
2582                 case OP_R4CONST: {
2583                         float f = *(float *)ins->inst_p0;
2584
2585                         if ((f == 0.0) && (mono_signbit (f) == 0))
2586                                 ia64_fmov (code, ins->dreg, 0);
2587                         else if (f == 1.0)
2588                                 ia64_fmov (code, ins->dreg, 1);
2589                         else {
2590                                 add_patch_info (cfg, code, MONO_PATCH_INFO_R4, ins->inst_p0);
2591                                 ia64_movl (code, GP_SCRATCH_REG, 0);
2592                                 ia64_ldfs (code, ins->dreg, GP_SCRATCH_REG);
2593                         }
2594                         break;
2595                 }
2596                 case OP_FMOVE:
2597                         ia64_fmov (code, ins->dreg, ins->sreg1);
2598                         break;
2599                 case OP_STORER8_MEMBASE_REG:
2600                         if (ins->inst_offset != 0) {
2601                                 /* This is generated by local regalloc */
2602                                 if (ia64_is_imm14 (ins->inst_offset)) {
2603                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2604                                 } else {
2605                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2606                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2607                                 }
2608                                 ins->inst_destbasereg = GP_SCRATCH_REG;
2609                         }
2610                         ia64_stfd_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2611                         break;
2612                 case OP_STORER4_MEMBASE_REG:
2613                         ia64_fnorm_s_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2614                         ia64_stfs_hint (code, ins->inst_destbasereg, FP_SCRATCH_REG, 0);
2615                         break;
2616                 case OP_LOADR8_MEMBASE:
2617                         if (ins->inst_offset != 0) {
2618                                 /* This is generated by local regalloc */
2619                                 if (ia64_is_imm14 (ins->inst_offset)) {
2620                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2621                                 } else {
2622                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2623                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2624                                 }
2625                                 ins->inst_basereg = GP_SCRATCH_REG;
2626                         }
2627                         ia64_ldfd (code, ins->dreg, ins->inst_basereg);
2628                         break;
2629                 case OP_LOADR4_MEMBASE:
2630                         ia64_ldfs (code, ins->dreg, ins->inst_basereg);
2631                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2632                         break;
2633                 case OP_ICONV_TO_R4:
2634                 case OP_LCONV_TO_R4:
2635                         ia64_setf_sig (code, ins->dreg, ins->sreg1);
2636                         ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2637                         ia64_fnorm_s_sf (code, ins->dreg, ins->dreg, 0);
2638                         break;
2639                 case OP_ICONV_TO_R8:
2640                 case OP_LCONV_TO_R8:
2641                         ia64_setf_sig (code, ins->dreg, ins->sreg1);
2642                         ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2643                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2644                         break;
2645                 case OP_FCONV_TO_R4:
2646                         ia64_fnorm_s_sf (code, ins->dreg, ins->sreg1, 0);
2647                         break;
2648                 case OP_FCONV_TO_I8:
2649                 case OP_FCONV_TO_I:
2650                         ia64_fcvt_fx_trunc_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2651                         ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2652                         break;
2653                 case OP_FADD:
2654                         ia64_fma_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2655                         break;
2656                 case OP_FSUB:
2657                         ia64_fms_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2658                         break;
2659                 case OP_FMUL:
2660                         ia64_fma_d_sf (code, ins->dreg, ins->sreg1, ins->sreg2, 0, 0);
2661                         break;
2662                 case OP_FNEG:
2663                         ia64_fmerge_ns (code, ins->dreg, ins->sreg1, ins->sreg1);
2664                         break;
2665                 case OP_CKFINITE:
2666                         /* Quiet NaN */
2667                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x080);
2668                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2669                         /* Signaling NaN */
2670                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x040);
2671                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2672                         /* Positive infinity */
2673                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x021);
2674                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2675                         /* Negative infinity */
2676                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x022);
2677                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2678                         break;
2679
2680                 /* Calls */
2681                 case OP_CHECK_THIS:
2682                         /* ensure ins->sreg1 is not NULL */
2683                         ia64_ld8 (code, GP_SCRATCH_REG, ins->sreg1);
2684                         break;
2685                 case OP_ARGLIST:
2686                         ia64_adds_imm (code, GP_SCRATCH_REG, cfg->sig_cookie, cfg->frame_reg);
2687                         ia64_st8 (code, ins->sreg1, GP_SCRATCH_REG);
2688                         break;
2689                 case OP_FCALL:
2690                 case OP_LCALL:
2691                 case OP_VCALL:
2692                 case OP_VCALL2:
2693                 case OP_VOIDCALL:
2694                 case OP_CALL:
2695                         call = (MonoCallInst*)ins;
2696
2697                         if (ins->flags & MONO_INST_HAS_METHOD)
2698                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2699                         else
2700                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2701
2702                         code = emit_move_return_value (cfg, ins, code);
2703                         break;
2704
2705                 case OP_CALL_REG:
2706                 case OP_FCALL_REG:
2707                 case OP_LCALL_REG:
2708                 case OP_VCALL_REG:
2709                 case OP_VCALL2_REG:
2710                 case OP_VOIDCALL_REG: {
2711                         MonoCallInst *call = (MonoCallInst*)ins;
2712                         CallInfo *cinfo;
2713                         int out_reg;
2714
2715                         /*
2716                          * mono_arch_find_this_arg () needs to find the this argument in a global
2717                          * register.
2718                          */
2719                         cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2720                         out_reg = cfg->arch.reg_out0;
2721                         if (cinfo->ret.storage == ArgValuetypeAddrInIReg)
2722                                 out_reg ++;
2723                         ia64_mov (code, IA64_R10, out_reg);
2724
2725                         /* Indirect call */
2726                         ia64_mov (code, IA64_R8, ins->sreg1);
2727                         ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, IA64_R8, 8);
2728                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2729                         ia64_ld8 (code, IA64_GP, IA64_R8);
2730                         ia64_br_call_reg (code, IA64_B0, IA64_B6);
2731
2732                         code = emit_move_return_value (cfg, ins, code);
2733                         break;
2734                 }
2735                 case OP_FCALL_MEMBASE:
2736                 case OP_LCALL_MEMBASE:
2737                 case OP_VCALL_MEMBASE:
2738                 case OP_VCALL2_MEMBASE:
2739                 case OP_VOIDCALL_MEMBASE:
2740                 case OP_CALL_MEMBASE: {
2741                         MonoCallInst *call = (MonoCallInst*)ins;
2742                         CallInfo *cinfo;
2743                         int out_reg;
2744
2745                         /*
2746                          * There are no membase instructions on ia64, but we can't
2747                          * lower this since get_vcall_slot_addr () needs to decode it.
2748                          */
2749
2750                         /* Keep this in synch with get_vcall_slot_addr */
2751                         ia64_mov (code, IA64_R11, ins->sreg1);
2752                         if (ia64_is_imm14 (ins->inst_offset))
2753                                 ia64_adds_imm (code, IA64_R8, ins->inst_offset, ins->sreg1);
2754                         else {
2755                                 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2756                                 ia64_add (code, IA64_R8, GP_SCRATCH_REG, ins->sreg1);
2757                         }
2758
2759                         if (call->method && ins->inst_offset < 0) {
2760                                 /*
2761                                  * This is a possible IMT call so save the IMT method in a global
2762                                  * register where mono_arch_find_imt_method () and its friends can
2763                                  * access it.
2764                                  */
2765                                 ia64_movl (code, IA64_R9, call->method);
2766                         }
2767
2768                         /*
2769                          * mono_arch_find_this_arg () needs to find the this argument in a global
2770                          * register.
2771                          */
2772                         cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2773                         out_reg = cfg->arch.reg_out0;
2774                         if (cinfo->ret.storage == ArgValuetypeAddrInIReg)
2775                                 out_reg ++;
2776                         ia64_mov (code, IA64_R10, out_reg);
2777
2778                         ia64_begin_bundle (code);
2779                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2780
2781                         ia64_ld8 (code, GP_SCRATCH_REG, IA64_R8);
2782
2783                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2784
2785                         /*
2786                          * This nop will tell get_vcall_slot_addr that this is a virtual
2787                          * call.
2788                          */
2789                         ia64_nop_i (code, 0x12345);
2790
2791                         ia64_br_call_reg (code, IA64_B0, IA64_B6);
2792
2793                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2794
2795                         code = emit_move_return_value (cfg, ins, code);
2796                         break;
2797                 }
2798                 case OP_JMP: {
2799                         /*
2800                          * Keep in sync with the code in emit_epilog.
2801                          */
2802
2803                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2804                                 NOT_IMPLEMENTED;
2805
2806                         g_assert (!cfg->method->save_lmf);
2807
2808                         /* Load arguments into their original registers */
2809                         code = emit_load_volatile_arguments (cfg, code);
2810
2811                         if (cfg->arch.stack_alloc_size) {
2812                                 if (cfg->arch.omit_fp) {
2813                                         if (ia64_is_imm14 (cfg->arch.stack_alloc_size))
2814                                                 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
2815                                         else {
2816                                                 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
2817                                                 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
2818                                         }
2819                                 }
2820                                 else
2821                                         ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
2822                         }
2823                         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
2824                         ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
2825
2826                         add_patch_info (cfg, code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2827                         ia64_movl (code, GP_SCRATCH_REG, 0);
2828                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2829                         ia64_br_cond_reg (code, IA64_B6);
2830
2831                         break;
2832                 }
2833                 case OP_BREAK:
2834                         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, mono_break);
2835                         break;
2836
2837                 case OP_LOCALLOC: {
2838                         gint32 abi_offset;
2839
2840                         /* FIXME: Sigaltstack support */
2841
2842                         /* keep alignment */
2843                         ia64_adds_imm (code, GP_SCRATCH_REG, MONO_ARCH_LOCALLOC_ALIGNMENT - 1, ins->sreg1);
2844                         ia64_movl (code, GP_SCRATCH_REG2, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
2845                         ia64_and (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2846
2847                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2848
2849                         ia64_mov (code, ins->dreg, IA64_SP);
2850
2851                         /* An area at sp is reserved by the ABI for parameter passing */
2852                         abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_LOCALLOC_ALIGNMENT);
2853                         if (ia64_is_adds_imm (abi_offset))
2854                                 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2855                         else {
2856                                 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2857                                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2858                         }
2859
2860                         if (ins->flags & MONO_INST_INIT) {
2861                                 /* Upper limit */
2862                                 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2863
2864                                 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2865
2866                                 /* Init loop */
2867                                 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2868                                 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2869                                 ia64_br_cond_pred (code, 8, -2);
2870
2871                                 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2872
2873                                 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2874                         }
2875
2876                         break;
2877                 }
2878                 case OP_LOCALLOC_IMM: {
2879                         gint32 abi_offset;
2880
2881                         /* FIXME: Sigaltstack support */
2882
2883                         gssize size = ins->inst_imm;
2884                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
2885
2886                         if (ia64_is_adds_imm (size))
2887                                 ia64_adds_imm (code, GP_SCRATCH_REG, size, IA64_R0);
2888                         else
2889                                 ia64_movl (code, GP_SCRATCH_REG, size);
2890
2891                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2892                         ia64_mov (code, ins->dreg, IA64_SP);
2893
2894                         /* An area at sp is reserved by the ABI for parameter passing */
2895                         abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_FRAME_ALIGNMENT);
2896                         if (ia64_is_adds_imm (abi_offset))
2897                                 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2898                         else {
2899                                 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2900                                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2901                         }
2902
2903                         if (ins->flags & MONO_INST_INIT) {
2904                                 /* Upper limit */
2905                                 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2906
2907                                 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2908
2909                                 /* Init loop */
2910                                 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2911                                 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2912                                 ia64_br_cond_pred (code, 8, -2);
2913
2914                                 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2915
2916                                 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2917                         }
2918
2919                         break;
2920                 }
2921                 case OP_TLS_GET:
2922                         ia64_adds_imm (code, ins->dreg, ins->inst_offset, IA64_TP);
2923                         ia64_ld8 (code, ins->dreg, ins->dreg);
2924                         break;
2925
2926                         /* Synchronization */
2927                 case OP_MEMORY_BARRIER:
2928                         ia64_mf (code);
2929                         break;
2930                 case OP_ATOMIC_ADD_IMM_NEW_I4:
2931                         g_assert (ins->inst_offset == 0);
2932                         ia64_fetchadd4_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2933                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2934                         break;
2935                 case OP_ATOMIC_ADD_IMM_NEW_I8:
2936                         g_assert (ins->inst_offset == 0);
2937                         ia64_fetchadd8_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2938                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2939                         break;
2940                 case OP_ATOMIC_EXCHANGE_I4:
2941                         ia64_xchg4_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2942                         ia64_sxt4 (code, ins->dreg, ins->dreg);
2943                         break;
2944                 case OP_ATOMIC_EXCHANGE_I8:
2945                         ia64_xchg8_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2946                         break;
2947                 case OP_ATOMIC_ADD_NEW_I4: {
2948                         guint8 *label, *buf;
2949
2950                         /* From libatomic_ops */
2951                         ia64_mf (code);
2952
2953                         ia64_begin_bundle (code);
2954                         label = code.buf + code.nins;
2955                         ia64_ld4_acq (code, GP_SCRATCH_REG, ins->sreg1);
2956                         ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2957                         ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2958                         ia64_cmpxchg4_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2959                         ia64_cmp4_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2960                         buf = code.buf + code.nins;
2961                         ia64_br_cond_pred (code, 7, 0);
2962                         ia64_begin_bundle (code);
2963                         ia64_patch (buf, label);
2964                         ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2965                         break;
2966                 }
2967                 case OP_ATOMIC_ADD_NEW_I8: {
2968                         guint8 *label, *buf;
2969
2970                         /* From libatomic_ops */
2971                         ia64_mf (code);
2972
2973                         ia64_begin_bundle (code);
2974                         label = code.buf + code.nins;
2975                         ia64_ld8_acq (code, GP_SCRATCH_REG, ins->sreg1);
2976                         ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2977                         ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2978                         ia64_cmpxchg8_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2979                         ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2980                         buf = code.buf + code.nins;
2981                         ia64_br_cond_pred (code, 7, 0);
2982                         ia64_begin_bundle (code);
2983                         ia64_patch (buf, label);
2984                         ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2985                         break;
2986                 }
2987
2988                         /* Exception handling */
2989                 case OP_CALL_HANDLER:
2990                         /*
2991                          * Using a call instruction would mess up the register stack, so
2992                          * save the return address to a register and use a
2993                          * branch.
2994                          */
2995                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2996                         ia64_mov (code, IA64_R15, IA64_R0);
2997                         ia64_mov_from_ip (code, GP_SCRATCH_REG);
2998                         /* Add the length of OP_CALL_HANDLER */
2999                         ia64_adds_imm (code, GP_SCRATCH_REG, 5 * 16, GP_SCRATCH_REG);
3000                         add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3001                         ia64_movl (code, GP_SCRATCH_REG2, 0);
3002                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
3003                         ia64_br_cond_reg (code, IA64_B6);
3004                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3005                         break;
3006                 case OP_START_HANDLER: {
3007                         /*
3008                          * We receive the return address in GP_SCRATCH_REG.
3009                          */
3010                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3011
3012                         /*
3013                          * R15 determines our caller. It is used since it is writable using
3014                          * libunwind.
3015                          * R15 == 0 means we are called by OP_CALL_HANDLER or via resume_context ()
3016                          * R15 != 0 means we are called by call_filter ().
3017                          */
3018                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3019                         ia64_cmp_eq (code, 6, 7, IA64_R15, IA64_R0);
3020
3021                         ia64_br_cond_pred (code, 6, 6);
3022
3023                         /*
3024                          * Called by call_filter:
3025                          * Allocate a new stack frame, and set the fp register from the
3026                          * value passed in by the caller.
3027                          * We allocate a similar frame as is done by the prolog, so
3028                          * if an exception is thrown while executing the filter, the
3029                          * unwinder can unwind through the filter frame using the unwind
3030                          * info for the prolog.
3031                          */
3032                         ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3033                         ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3034                         ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3035                         ia64_mov (code, cfg->frame_reg, IA64_R15);
3036                         /* Signal to endfilter that we are called by call_filter */
3037                         ia64_mov (code, GP_SCRATCH_REG, IA64_R0);
3038
3039                         /* Branch target: */
3040                         if (ia64_is_imm14 (spvar->inst_offset))
3041                                 ia64_adds_imm (code, GP_SCRATCH_REG2, spvar->inst_offset, cfg->frame_reg);
3042                         else {
3043                                 ia64_movl (code, GP_SCRATCH_REG2, spvar->inst_offset);
3044                                 ia64_add (code, GP_SCRATCH_REG2, cfg->frame_reg, GP_SCRATCH_REG2);
3045                         }
3046
3047                         /* Save the return address */
3048                         ia64_st8_hint (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 0);
3049                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3050
3051                         break;
3052                 }
3053                 case OP_ENDFINALLY:
3054                 case OP_ENDFILTER: {
3055                         /* FIXME: Return the value in ENDFILTER */
3056                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3057
3058                         /* Load the return address */
3059                         if (ia64_is_imm14 (spvar->inst_offset)) {
3060                                 ia64_adds_imm (code, GP_SCRATCH_REG, spvar->inst_offset, cfg->frame_reg);
3061                         } else {
3062                                 ia64_movl (code, GP_SCRATCH_REG, spvar->inst_offset);
3063                                 ia64_add (code, GP_SCRATCH_REG, cfg->frame_reg, GP_SCRATCH_REG);
3064                         }
3065                         ia64_ld8_hint (code, GP_SCRATCH_REG, GP_SCRATCH_REG, 0);
3066
3067                         /* Test caller */
3068                         ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, IA64_R0);
3069                         ia64_br_cond_pred (code, 7, 4);
3070
3071                         /* Called by call_filter */
3072                         /* Pop frame */
3073                         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
3074                         ia64_mov_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
3075                         ia64_br_ret_reg (code, IA64_B0);
3076
3077                         /* Called by CALL_HANDLER */
3078                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
3079                         ia64_br_cond_reg (code, IA64_B6);
3080                         break;
3081                 }
3082                 case OP_THROW:
3083                         ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3084                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3085                                                           (gpointer)"mono_arch_throw_exception");
3086
3087                         /*
3088                          * This might be the last instruction in the method, so add a dummy
3089                          * instruction so the unwinder will work.
3090                          */
3091                         ia64_break_i (code, 0);
3092                         break;
3093                 case OP_RETHROW:
3094                         ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3095                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3096                                                           (gpointer)"mono_arch_rethrow_exception");
3097
3098                         ia64_break_i (code, 0);
3099                         break;
3100
3101                 default:
3102                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3103                         g_assert_not_reached ();
3104                 }
3105
3106                 if ((code.buf - cfg->native_code - offset) > max_len) {
3107                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3108                                    mono_inst_name (ins->opcode), max_len, code.buf - cfg->native_code - offset);
3109                         g_assert_not_reached ();
3110                 }
3111
3112                 cpos += max_len;
3113
3114                 last_ins = ins;
3115                 last_offset = offset;
3116         }
3117
3118         ia64_codegen_close (code);
3119
3120         cfg->code_len = code.buf - cfg->native_code;
3121 }
3122
3123 void
3124 mono_arch_register_lowlevel_calls (void)
3125 {
3126 }
3127
3128 static Ia64InsType ins_types_in_template [32][3] = {
3129         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3130         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3131         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3132         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3133         {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3134         {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3135         {0, 0, 0},
3136         {0, 0, 0},
3137         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3138         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3139         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3140         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3141         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3142         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3143         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3144         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3145         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3146         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3147         {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3148         {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3149         {0, 0, 0},
3150         {0, 0, 0},
3151         {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3152         {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3153         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3154         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3155         {0, 0, 0},
3156         {0, 0, 0},
3157         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3158         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3159         {0, 0, 0},
3160         {0, 0, 0}
3161 };
3162
3163 static gboolean stops_in_template [32][3] = {
3164         { FALSE, FALSE, FALSE },
3165         { FALSE, FALSE, TRUE },
3166         { FALSE, TRUE, FALSE },
3167         { FALSE, TRUE, TRUE },
3168         { FALSE, FALSE, FALSE },
3169         { FALSE, FALSE, TRUE },
3170         { FALSE, FALSE, FALSE },
3171         { FALSE, FALSE, FALSE },
3172
3173         { FALSE, FALSE, FALSE },
3174         { FALSE, FALSE, TRUE },
3175         { TRUE, FALSE, FALSE },
3176         { TRUE, FALSE, TRUE },
3177         { FALSE, FALSE, FALSE },
3178         { FALSE, FALSE, TRUE },
3179         { FALSE, FALSE, FALSE },
3180         { FALSE, FALSE, TRUE },
3181
3182         { FALSE, FALSE, FALSE },
3183         { FALSE, FALSE, TRUE },
3184         { FALSE, FALSE, FALSE },
3185         { FALSE, FALSE, TRUE },
3186         { FALSE, FALSE, FALSE },
3187         { FALSE, FALSE, FALSE },
3188         { FALSE, FALSE, FALSE },
3189         { FALSE, FALSE, TRUE },
3190
3191         { FALSE, FALSE, FALSE },
3192         { FALSE, FALSE, TRUE },
3193         { FALSE, FALSE, FALSE },
3194         { FALSE, FALSE, FALSE },
3195         { FALSE, FALSE, FALSE },
3196         { FALSE, FALSE, TRUE },
3197         { FALSE, FALSE, FALSE },
3198         { FALSE, FALSE, FALSE }
3199 };
3200
3201 static int last_stop_in_template [32] = {
3202         -1, 2, 1, 2, -1, 2, -1, -1,
3203         -1, 2, 0, 2, -1, 2, -1, 2,
3204         -1, 2, -1, 2, -1, -1, -1, 2,
3205         -1, 2, -1, -1, -1, 2, -1, -1
3206 };
3207
3208 static guint64 nops_for_ins_types [6] = {
3209         IA64_NOP_I,
3210         IA64_NOP_I,
3211         IA64_NOP_M,
3212         IA64_NOP_F,
3213         IA64_NOP_B,
3214         IA64_NOP_X
3215 };
3216
3217 #define ITYPE_MATCH(itype1, itype2) (((itype1) == (itype2)) || (((itype2) == IA64_INS_TYPE_A) && (((itype1) == IA64_INS_TYPE_I) || ((itype1) == IA64_INS_TYPE_M))))
3218
3219 /*
3220  * Debugging support
3221  */
3222
3223 #if 0
3224 #define DEBUG_INS_SCHED(a) do { a; } while (0)
3225 #else
3226 #define DEBUG_INS_SCHED(a)
3227 #endif
3228
3229 static void
3230 ia64_analyze_deps (Ia64CodegenState *code, int *deps_start, int *stops)
3231 {
3232         int i, pos, ins_index, current_deps_start, current_ins_start, reg;
3233         guint8 *deps = code->dep_info;
3234         gboolean need_stop, no_stop;
3235
3236         for (i = 0; i < code->nins; ++i)
3237                 stops [i] = FALSE;
3238
3239         ins_index = 0;
3240         current_deps_start = 0;
3241         current_ins_start = 0;
3242         deps_start [ins_index] = current_ins_start;
3243         pos = 0;
3244         no_stop = FALSE;
3245         DEBUG_INS_SCHED (printf ("BEGIN.\n"));
3246         while (pos < code->dep_info_pos) {
3247                 need_stop = FALSE;
3248                 switch (deps [pos]) {
3249                 case IA64_END_OF_INS:
3250                         ins_index ++;
3251                         current_ins_start = pos + 2;
3252                         deps_start [ins_index] = current_ins_start;
3253                         no_stop = FALSE;
3254                         DEBUG_INS_SCHED (printf ("(%d) END INS.\n", ins_index - 1));
3255                         break;
3256                 case IA64_NONE:
3257                         break;
3258                 case IA64_READ_GR:
3259                         reg = deps [pos + 1];
3260
3261                         DEBUG_INS_SCHED (printf ("READ GR: %d\n", reg));
3262                         for (i = current_deps_start; i < current_ins_start; i += 2)
3263                                 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3264                                         need_stop = TRUE;
3265                         break;
3266                 case IA64_WRITE_GR:
3267                         reg = code->dep_info [pos + 1];
3268
3269                         DEBUG_INS_SCHED (printf ("WRITE GR: %d\n", reg));
3270                         for (i = current_deps_start; i < current_ins_start; i += 2)
3271                                 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3272                                         need_stop = TRUE;
3273                         break;
3274                 case IA64_READ_PR:
3275                         reg = deps [pos + 1];
3276
3277                         DEBUG_INS_SCHED (printf ("READ PR: %d\n", reg));
3278                         for (i = current_deps_start; i < current_ins_start; i += 2)
3279                                 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3280                                         need_stop = TRUE;
3281                         break;
3282                 case IA64_READ_PR_BRANCH:
3283                         reg = deps [pos + 1];
3284
3285                         /* Writes to prs by non-float instructions are visible to branches */
3286                         DEBUG_INS_SCHED (printf ("READ PR BRANCH: %d\n", reg));
3287                         for (i = current_deps_start; i < current_ins_start; i += 2)
3288                                 if (deps [i] == IA64_WRITE_PR_FLOAT && deps [i + 1] == reg)
3289                                         need_stop = TRUE;
3290                         break;
3291                 case IA64_WRITE_PR:
3292                         reg = code->dep_info [pos + 1];
3293
3294                         DEBUG_INS_SCHED (printf ("WRITE PR: %d\n", reg));
3295                         for (i = current_deps_start; i < current_ins_start; i += 2)
3296                                 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3297                                         need_stop = TRUE;
3298                         break;
3299                 case IA64_WRITE_PR_FLOAT:
3300                         reg = code->dep_info [pos + 1];
3301
3302                         DEBUG_INS_SCHED (printf ("WRITE PR FP: %d\n", reg));
3303                         for (i = current_deps_start; i < current_ins_start; i += 2)
3304                                 if (((deps [i] == IA64_WRITE_GR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3305                                         need_stop = TRUE;
3306                         break;
3307                 case IA64_READ_BR:
3308                         reg = deps [pos + 1];
3309
3310                         DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3311                         for (i = current_deps_start; i < current_ins_start; i += 2)
3312                                 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3313                                         need_stop = TRUE;
3314                         break;
3315                 case IA64_WRITE_BR:
3316                         reg = code->dep_info [pos + 1];
3317
3318                         DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3319                         for (i = current_deps_start; i < current_ins_start; i += 2)
3320                                 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3321                                         need_stop = TRUE;
3322                         break;
3323                 case IA64_READ_BR_BRANCH:
3324                         reg = deps [pos + 1];
3325
3326                         /* Writes to brs are visible to branches */
3327                         DEBUG_INS_SCHED (printf ("READ BR BRACH: %d\n", reg));
3328                         break;
3329                 case IA64_READ_FR:
3330                         reg = deps [pos + 1];
3331
3332                         DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3333                         for (i = current_deps_start; i < current_ins_start; i += 2)
3334                                 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3335                                         need_stop = TRUE;
3336                         break;
3337                 case IA64_WRITE_FR:
3338                         reg = code->dep_info [pos + 1];
3339
3340                         DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3341                         for (i = current_deps_start; i < current_ins_start; i += 2)
3342                                 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3343                                         need_stop = TRUE;
3344                         break;
3345                 case IA64_READ_AR:
3346                         reg = deps [pos + 1];
3347
3348                         DEBUG_INS_SCHED (printf ("READ AR: %d\n", reg));
3349                         for (i = current_deps_start; i < current_ins_start; i += 2)
3350                                 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3351                                         need_stop = TRUE;
3352                         break;
3353                 case IA64_WRITE_AR:
3354                         reg = code->dep_info [pos + 1];
3355
3356                         DEBUG_INS_SCHED (printf ("WRITE AR: %d\n", reg));
3357                         for (i = current_deps_start; i < current_ins_start; i += 2)
3358                                 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3359                                         need_stop = TRUE;
3360                         break;
3361                 case IA64_NO_STOP:
3362                         /*
3363                          * Explicitly indicate that a stop is not required. Useful for
3364                          * example when two predicated instructions with negated predicates
3365                          * write the same registers.
3366                          */
3367                         no_stop = TRUE;
3368                         break;
3369                 default:
3370                         g_assert_not_reached ();
3371                 }
3372                 pos += 2;
3373
3374                 if (need_stop && !no_stop) {
3375                         g_assert (ins_index > 0);
3376                         stops [ins_index - 1] = 1;
3377
3378                         DEBUG_INS_SCHED (printf ("STOP\n"));
3379                         current_deps_start = current_ins_start;
3380
3381                         /* Skip remaining deps for this instruction */
3382                         while (deps [pos] != IA64_END_OF_INS)
3383                                 pos += 2;
3384                 }
3385         }
3386
3387         if (code->nins > 0) {
3388                 /* No dependency info for the last instruction */
3389                 stops [code->nins - 1] = 1;
3390         }
3391
3392         deps_start [code->nins] = code->dep_info_pos;
3393 }
3394
3395 static void
3396 ia64_real_emit_bundle (Ia64CodegenState *code, int *deps_start, int *stops, int n, guint64 template, guint64 ins1, guint64 ins2, guint64 ins3, guint8 nops)
3397 {
3398         int stop_pos, i, deps_to_shift, dep_shift;
3399
3400         g_assert (n <= code->nins);
3401
3402         // if (n > 1) printf ("FOUND: %ld.\n", template);
3403
3404         ia64_emit_bundle_template (code, template, ins1, ins2, ins3);
3405
3406         stop_pos = last_stop_in_template [template] + 1;
3407         if (stop_pos > n)
3408                 stop_pos = n;
3409
3410         /* Compute the number of 'real' instructions before the stop */
3411         deps_to_shift = stop_pos;
3412         if (stop_pos >= 3 && (nops & (1 << 2)))
3413                 deps_to_shift --;
3414         if (stop_pos >= 2 && (nops & (1 << 1)))
3415                 deps_to_shift --;
3416         if (stop_pos >= 1 && (nops & (1 << 0)))
3417                 deps_to_shift --;
3418
3419         /*
3420          * We have to keep some dependencies whose instructions have been shifted
3421          * out of the buffer. So nullify the end_of_ins markers in the dependency
3422          * array.
3423          */
3424         for (i = deps_start [deps_to_shift]; i < deps_start [n]; i += 2)
3425                 if (code->dep_info [i] == IA64_END_OF_INS)
3426                         code->dep_info [i] = IA64_NONE;
3427
3428         g_assert (deps_start [deps_to_shift] <= code->dep_info_pos);
3429         memcpy (code->dep_info, &code->dep_info [deps_start [deps_to_shift]], code->dep_info_pos - deps_start [deps_to_shift]);
3430         code->dep_info_pos = code->dep_info_pos - deps_start [deps_to_shift];
3431
3432         dep_shift = deps_start [deps_to_shift];
3433         for (i = 0; i < code->nins + 1 - n; ++i)
3434                 deps_start [i] = deps_start [n + i] - dep_shift;
3435
3436         /* Determine the exact positions of instructions with unwind ops */
3437         if (code->unw_op_count) {
3438                 int ins_pos [16];
3439                 int curr_ins, curr_ins_pos;
3440
3441                 curr_ins = 0;
3442                 curr_ins_pos = ((code->buf - code->region_start - 16) / 16) * 3;
3443                 for (i = 0; i < 3; ++i) {
3444                         if (! (nops & (1 << i))) {
3445                                 ins_pos [curr_ins] = curr_ins_pos + i;
3446                                 curr_ins ++;
3447                         }
3448                 }
3449
3450                 for (i = code->unw_op_pos; i < code->unw_op_count; ++i) {
3451                         if (code->unw_ops_pos [i] < n) {
3452                                 code->unw_ops [i].when = ins_pos [code->unw_ops_pos [i]];
3453                                 //printf ("UNW-OP: %d -> %d\n", code->unw_ops_pos [i], code->unw_ops [i].when);
3454                         }
3455                 }
3456                 if (code->unw_op_pos < code->unw_op_count)
3457                         code->unw_op_pos += n;
3458         }
3459
3460         if (n == code->nins) {
3461                 code->template = 0;
3462                 code->nins = 0;
3463         }
3464         else {
3465                 memcpy (&code->instructions [0], &code->instructions [n], (code->nins - n) * sizeof (guint64));
3466                 memcpy (&code->itypes [0], &code->itypes [n], (code->nins - n) * sizeof (int));
3467                 memcpy (&stops [0], &stops [n], (code->nins - n) * sizeof (int));
3468                 code->nins -= n;
3469         }
3470 }
3471
3472 void
3473 ia64_emit_bundle (Ia64CodegenState *code, gboolean flush)
3474 {
3475         int i, ins_type, template, nins_to_emit;
3476         int deps_start [16];
3477         int stops [16];
3478         gboolean found;
3479
3480         /*
3481          * We implement a simple scheduler which tries to put three instructions
3482          * per bundle, then two, then one.
3483          */
3484         ia64_analyze_deps (code, deps_start, stops);
3485
3486         if ((code->nins >= 3) && !code->one_ins_per_bundle) {
3487                 /* Find a suitable template */
3488                 for (template = 0; template < 32; ++template) {
3489                         if (stops_in_template [template][0] != stops [0] ||
3490                                 stops_in_template [template][1] != stops [1] ||
3491                                 stops_in_template [template][2] != stops [2])
3492                                 continue;
3493
3494                         found = TRUE;
3495                         for (i = 0; i < 3; ++i) {
3496                                 ins_type = ins_types_in_template [template][i];
3497                                 switch (code->itypes [i]) {
3498                                 case IA64_INS_TYPE_A:
3499                                         found &= (ins_type == IA64_INS_TYPE_I) || (ins_type == IA64_INS_TYPE_M);
3500                                         break;
3501                                 default:
3502                                         found &= (ins_type == code->itypes [i]);
3503                                         break;
3504                                 }
3505                         }
3506
3507                         if (found)
3508                                 found = debug_ins_sched ();
3509
3510                         if (found) {
3511                                 ia64_real_emit_bundle (code, deps_start, stops, 3, template, code->instructions [0], code->instructions [1], code->instructions [2], 0);
3512                                 break;
3513                         }
3514                 }
3515         }
3516
3517         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3518                 /* Wait for more instructions */
3519                 return;
3520
3521         /* If it didn't work out, try putting two instructions into one bundle */
3522         if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3523                 /* Try a nop at the end */
3524                 for (template = 0; template < 32; ++template) {
3525                         if (stops_in_template [template][0] != stops [0] ||
3526                                 ((stops_in_template [template][1] != stops [1]) &&
3527                                  (stops_in_template [template][2] != stops [1])))
3528
3529                                 continue;
3530
3531                         if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3532                                 !ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [1]))
3533                                 continue;
3534
3535                         if (!debug_ins_sched ())
3536                                 continue;
3537
3538                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], code->instructions [1], nops_for_ins_types [ins_types_in_template [template][2]], 1 << 2);
3539                         break;
3540                 }
3541         }
3542
3543         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3544                 /* Wait for more instructions */
3545                 return;
3546
3547         if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3548                 /* Try a nop in the middle */
3549                 for (template = 0; template < 32; ++template) {
3550                         if (((stops_in_template [template][0] != stops [0]) &&
3551                                  (stops_in_template [template][1] != stops [0])) ||
3552                                 stops_in_template [template][2] != stops [1])
3553                                 continue;
3554
3555                         if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3556                                 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3557                                 continue;
3558
3559                         if (!debug_ins_sched ())
3560                                 continue;
3561
3562                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], nops_for_ins_types [ins_types_in_template [template][1]], code->instructions [1], 1 << 1);
3563                         break;
3564                 }
3565         }
3566
3567         if ((code->nins >= 2) && flush && !code->one_ins_per_bundle) {
3568                 /* Try a nop at the beginning */
3569                 for (template = 0; template < 32; ++template) {
3570                         if ((stops_in_template [template][1] != stops [0]) ||
3571                                 (stops_in_template [template][2] != stops [1]))
3572                                 continue;
3573
3574                         if (!ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [0]) ||
3575                                 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3576                                 continue;
3577
3578                         if (!debug_ins_sched ())
3579                                 continue;
3580
3581                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, nops_for_ins_types [ins_types_in_template [template][0]], code->instructions [0], code->instructions [1], 1 << 0);
3582                         break;
3583                 }
3584         }
3585
3586         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3587                 /* Wait for more instructions */
3588                 return;
3589
3590         if (flush)
3591                 nins_to_emit = code->nins;
3592         else
3593                 nins_to_emit = 1;
3594
3595         while (nins_to_emit > 0) {
3596                 if (!debug_ins_sched ())
3597                         stops [0] = 1;
3598                 switch (code->itypes [0]) {
3599                 case IA64_INS_TYPE_A:
3600                         if (stops [0])
3601                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3602                         else
3603                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3604                         break;
3605                 case IA64_INS_TYPE_I:
3606                         if (stops [0])
3607                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3608                         else
3609                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3610                         break;
3611                 case IA64_INS_TYPE_M:
3612                         if (stops [0])
3613                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3614                         else
3615                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3616                         break;
3617                 case IA64_INS_TYPE_B:
3618                         if (stops [0])
3619                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIBS, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3620                         else
3621                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIB, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3622                         break;
3623                 case IA64_INS_TYPE_F:
3624                         if (stops [0])
3625                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3626                         else
3627                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFI, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3628                         break;
3629                 case IA64_INS_TYPE_LX:
3630                         if (stops [0] || stops [1])
3631                                 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLXS, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3632                         else
3633                                 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLX, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3634                         nins_to_emit --;
3635                         break;
3636                 default:
3637                         g_assert_not_reached ();
3638                 }
3639                 nins_to_emit --;
3640         }
3641 }
3642
3643 unw_dyn_region_info_t*
3644 mono_ia64_create_unwind_region (Ia64CodegenState *code)
3645 {
3646         unw_dyn_region_info_t *r;
3647
3648         g_assert (code->nins == 0);
3649         r = g_malloc0 (_U_dyn_region_info_size (code->unw_op_count));
3650         memcpy (&r->op, &code->unw_ops, sizeof (unw_dyn_op_t) * code->unw_op_count);
3651         r->op_count = code->unw_op_count;
3652         r->insn_count = ((code->buf - code->region_start) >> 4) * 3;
3653         code->unw_op_count = 0;
3654         code->unw_op_pos = 0;
3655         code->region_start = code->buf;
3656
3657         return r;
3658 }
3659
3660 static void
3661 ia64_patch (unsigned char* code, gpointer target)
3662 {
3663         int template, i;
3664         guint64 instructions [3];
3665         guint8 gen_buf [16];
3666         Ia64CodegenState gen;
3667         int ins_to_skip;
3668         gboolean found;
3669
3670         /*
3671          * code encodes both the position inside the buffer and code.nins when
3672          * the instruction was emitted.
3673          */
3674         ins_to_skip = (guint64)code % 16;
3675         code = (unsigned char*)((guint64)code & ~15);
3676
3677         /*
3678          * Search for the first instruction which is 'patchable', skipping
3679          * ins_to_skip instructions.
3680          */
3681
3682         while (TRUE) {
3683
3684         template = ia64_bundle_template (code);
3685         instructions [0] = ia64_bundle_ins1 (code);
3686         instructions [1] = ia64_bundle_ins2 (code);
3687         instructions [2] = ia64_bundle_ins3 (code);
3688
3689         ia64_codegen_init (gen, gen_buf);
3690
3691         found = FALSE;
3692         for (i = 0; i < 3; ++i) {
3693                 guint64 ins = instructions [i];
3694                 int opcode = ia64_ins_opcode (ins);
3695
3696                 if (ins == nops_for_ins_types [ins_types_in_template [template][i]])
3697                         continue;
3698
3699                 if (ins_to_skip) {
3700                         ins_to_skip --;
3701                         continue;
3702                 }
3703
3704                 switch (ins_types_in_template [template][i]) {
3705                 case IA64_INS_TYPE_A:
3706                 case IA64_INS_TYPE_M:
3707                         if ((opcode == 8) && (ia64_ins_x2a (ins) == 2) && (ia64_ins_ve (ins) == 0)) {
3708                                 /* adds */
3709                                 ia64_adds_imm_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), (guint64)target, ia64_ins_r3 (ins));
3710                                 instructions [i] = gen.instructions [0];
3711                                 found = TRUE;
3712                         }
3713                         else
3714                                 NOT_IMPLEMENTED;
3715                         break;
3716                 case IA64_INS_TYPE_B:
3717                         if ((opcode == 4) && (ia64_ins_btype (ins) == 0)) {
3718                                 /* br.cond */
3719                                 gint64 disp = ((guint8*)target - code) >> 4;
3720
3721                                 /* FIXME: hints */
3722                                 ia64_br_cond_hint_pred (gen, ia64_ins_qp (ins), disp, 0, 0, 0);
3723
3724                                 instructions [i] = gen.instructions [0];
3725                                 found = TRUE;
3726                         }
3727                         else if (opcode == 5) {
3728                                 /* br.call */
3729                                 gint64 disp = ((guint8*)target - code) >> 4;
3730
3731                                 /* FIXME: hints */
3732                                 ia64_br_call_hint_pred (gen, ia64_ins_qp (ins), ia64_ins_b1 (ins), disp, 0, 0, 0);
3733                                 instructions [i] = gen.instructions [0];
3734                                 found = TRUE;
3735                         }
3736                         else
3737                                 NOT_IMPLEMENTED;
3738                         break;
3739                 case IA64_INS_TYPE_LX:
3740                         if (i == 1)
3741                                 break;
3742
3743                         if ((opcode == 6) && (ia64_ins_vc (ins) == 0)) {
3744                                 /* movl */
3745                                 ia64_movl_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), target);
3746                                 instructions [1] = gen.instructions [0];
3747                                 instructions [2] = gen.instructions [1];
3748                                 found = TRUE;
3749                         }
3750                         else
3751                                 NOT_IMPLEMENTED;
3752
3753                         break;
3754                 default:
3755                         NOT_IMPLEMENTED;
3756                 }
3757
3758                 if (found) {
3759                         /* Rewrite code */
3760                         ia64_codegen_init (gen, code);
3761                         ia64_emit_bundle_template (&gen, template, instructions [0], instructions [1], instructions [2]);
3762                         return;
3763                 }
3764         }
3765
3766         code += 16;
3767         }
3768 }
3769
3770 void
3771 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3772 {
3773         MonoJumpInfo *patch_info;
3774
3775         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3776                 unsigned char *ip = patch_info->ip.i + code;
3777                 const unsigned char *target;
3778
3779                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3780
3781                 if (patch_info->type == MONO_PATCH_INFO_NONE)
3782                         continue;
3783                 if (mono_compile_aot) {
3784                         NOT_IMPLEMENTED;
3785                 }
3786
3787                 ia64_patch (ip, (gpointer)target);
3788         }
3789 }
3790
3791 guint8 *
3792 mono_arch_emit_prolog (MonoCompile *cfg)
3793 {
3794         MonoMethod *method = cfg->method;
3795         MonoMethodSignature *sig;
3796         MonoInst *inst;
3797         int alloc_size, pos, i;
3798         Ia64CodegenState code;
3799         CallInfo *cinfo;
3800
3801         sig = mono_method_signature (method);
3802         pos = 0;
3803
3804         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
3805
3806         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 512);
3807
3808         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3809                 cfg->code_size += 1024;
3810         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3811                 cfg->code_size += 1024;
3812
3813         cfg->native_code = g_malloc (cfg->code_size);
3814
3815         ia64_codegen_init (code, cfg->native_code);
3816
3817         alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
3818         if (cfg->param_area)
3819                 alloc_size += cfg->param_area;
3820         if (alloc_size)
3821                 /* scratch area */
3822                 alloc_size += 16;
3823         alloc_size = ALIGN_TO (alloc_size, MONO_ARCH_FRAME_ALIGNMENT);
3824
3825         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
3826                 /* Force sp to be saved/restored */
3827                 alloc_size += MONO_ARCH_FRAME_ALIGNMENT;
3828
3829         cfg->arch.stack_alloc_size = alloc_size;
3830
3831         pos = 0;
3832
3833         if (method->save_lmf) {
3834                 /* No LMF on IA64 */
3835         }
3836
3837         alloc_size -= pos;
3838
3839         ia64_unw_save_reg (code, UNW_IA64_AR_PFS, UNW_IA64_GR + cfg->arch.reg_saved_ar_pfs);
3840         ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3841         ia64_unw_save_reg (code, UNW_IA64_RP, UNW_IA64_GR + cfg->arch.reg_saved_b0);
3842         ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3843
3844         if ((alloc_size || cinfo->stack_usage) && !cfg->arch.omit_fp) {
3845                 ia64_unw_save_reg (code, UNW_IA64_SP, UNW_IA64_GR + cfg->arch.reg_saved_sp);
3846                 ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3847                 if (cfg->frame_reg != cfg->arch.reg_saved_sp)
3848                         ia64_mov (code, cfg->frame_reg, IA64_SP);
3849         }
3850
3851         if (alloc_size) {
3852 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3853                 int pagesize = getpagesize ();
3854
3855                 if (alloc_size >= pagesize) {
3856                         gint32 remaining_size = alloc_size;
3857
3858                         /* Generate stack touching code */
3859                         ia64_mov (code, GP_SCRATCH_REG, IA64_SP);
3860                         while (remaining_size >= pagesize) {
3861                                 ia64_movl (code, GP_SCRATCH_REG2, pagesize);
3862                                 ia64_sub (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3863                                 ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
3864                                 remaining_size -= pagesize;
3865                         }
3866                 }
3867 #endif
3868                 if (ia64_is_imm14 (-alloc_size)) {
3869                         if (cfg->arch.omit_fp)
3870                                 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3871                         ia64_adds_imm (code, IA64_SP, (-alloc_size), IA64_SP);
3872                 }
3873                 else {
3874                         ia64_movl (code, GP_SCRATCH_REG, -alloc_size);
3875                         if (cfg->arch.omit_fp)
3876                                 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3877                         ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
3878                 }
3879         }
3880
3881         ia64_begin_bundle (code);
3882
3883         /* Initialize unwind info */
3884         cfg->arch.r_pro = mono_ia64_create_unwind_region (&code);
3885
3886         if (sig->ret->type != MONO_TYPE_VOID) {
3887                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
3888                         /* Save volatile arguments to the stack */
3889                         NOT_IMPLEMENTED;
3890                 }
3891         }
3892
3893         /* Keep this in sync with emit_load_volatile_arguments */
3894         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3895                 ArgInfo *ainfo = cinfo->args + i;
3896                 gint32 stack_offset;
3897                 MonoType *arg_type;
3898
3899                 inst = cfg->args [i];
3900
3901                 if (sig->hasthis && (i == 0))
3902                         arg_type = &mono_defaults.object_class->byval_arg;
3903                 else
3904                         arg_type = sig->params [i - sig->hasthis];
3905
3906                 arg_type = mono_type_get_underlying_type (arg_type);
3907
3908                 stack_offset = ainfo->offset + ARGS_OFFSET;
3909
3910                 /*
3911                  * FIXME: Native code might pass non register sized integers
3912                  * without initializing the upper bits.
3913                  */
3914                 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED && !arg_type->byref && ainfo->storage == ArgInIReg) {
3915                         int reg = cfg->arch.reg_in0 + ainfo->reg;
3916
3917                         switch (mono_type_to_load_membase (cfg, arg_type)) {
3918                         case OP_LOADI1_MEMBASE:
3919                                 ia64_sxt1 (code, reg, reg);
3920                                 break;
3921                         case OP_LOADU1_MEMBASE:
3922                                 ia64_zxt1 (code, reg, reg);
3923                                 break;
3924                         case OP_LOADI2_MEMBASE:
3925                                 ia64_sxt2 (code, reg, reg);
3926                                 break;
3927                         case OP_LOADU2_MEMBASE:
3928                                 ia64_zxt2 (code, reg, reg);
3929                                 break;
3930                         default:
3931                                 break;
3932                         }
3933                 }
3934
3935                 /* Save volatile arguments to the stack */
3936                 if (inst->opcode != OP_REGVAR) {
3937                         switch (ainfo->storage) {
3938                         case ArgInIReg:
3939                         case ArgInFloatReg:
3940                         case ArgInFloatRegR4:
3941                                 g_assert (inst->opcode == OP_REGOFFSET);
3942                                 if (ia64_is_adds_imm (inst->inst_offset))
3943                                         ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3944                                 else {
3945                                         ia64_movl (code, GP_SCRATCH_REG2, inst->inst_offset);
3946                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3947                                 }
3948                                 if (arg_type->byref)
3949                                         ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3950                                 else {
3951                                         switch (arg_type->type) {
3952                                         case MONO_TYPE_R4:
3953                                                 ia64_stfs_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3954                                                 break;
3955                                         case MONO_TYPE_R8:
3956                                                 ia64_stfd_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3957                                                 break;
3958                                         default:
3959                                                 ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3960                                                 break;
3961                                         }
3962                                 }
3963                                 break;
3964                         case ArgOnStack:
3965                                 break;
3966                         case ArgAggregate:
3967                                 if (ainfo->nslots != ainfo->nregs)
3968                                         NOT_IMPLEMENTED;
3969
3970                                 g_assert (inst->opcode == OP_REGOFFSET);
3971                                 ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3972                                 for (i = 0; i < ainfo->nregs; ++i) {
3973                                         switch (ainfo->atype) {
3974                                         case AggregateNormal:
3975                                                 ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg + i, sizeof (gpointer), 0);
3976                                                 break;
3977                                         case AggregateSingleHFA:
3978                                                 ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, 4, 0);
3979                                                 break;
3980                                         case AggregateDoubleHFA:
3981                                                 ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, sizeof (gpointer), 0);
3982                                                 break;
3983                                         default:
3984                                                 NOT_IMPLEMENTED;
3985                                         }
3986                                 }
3987                                 break;
3988                         default:
3989                                 g_assert_not_reached ();
3990                         }
3991                 }
3992
3993                 if (inst->opcode == OP_REGVAR) {
3994                         /* Argument allocated to (non-volatile) register */
3995                         switch (ainfo->storage) {
3996                         case ArgInIReg:
3997                                 if (inst->dreg != cfg->arch.reg_in0 + ainfo->reg)
3998                                         ia64_mov (code, inst->dreg, cfg->arch.reg_in0 + ainfo->reg);
3999                                 break;
4000                         case ArgOnStack:
4001                                 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
4002                                 ia64_ld8 (code, inst->dreg, GP_SCRATCH_REG);
4003                                 break;
4004                         default:
4005                                 NOT_IMPLEMENTED;
4006                         }
4007                 }
4008         }
4009
4010         if (method->save_lmf) {
4011                 /* No LMF on IA64 */
4012         }
4013
4014         ia64_codegen_close (code);
4015
4016         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4017                 code.buf = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code.buf, TRUE);
4018
4019         cfg->code_len = code.buf - cfg->native_code;
4020
4021         g_assert (cfg->code_len < cfg->code_size);
4022
4023         cfg->arch.prolog_end_offset = cfg->code_len;
4024
4025         return code.buf;
4026 }
4027
4028 void
4029 mono_arch_emit_epilog (MonoCompile *cfg)
4030 {
4031         MonoMethod *method = cfg->method;
4032         int i, pos;
4033         int max_epilog_size = 16 * 4;
4034         Ia64CodegenState code;
4035         guint8 *buf;
4036         CallInfo *cinfo;
4037         ArgInfo *ainfo;
4038
4039         if (mono_jit_trace_calls != NULL)
4040                 max_epilog_size += 1024;
4041
4042         cfg->arch.epilog_begin_offset = cfg->code_len;
4043
4044         while (cfg->code_len + max_epilog_size > cfg->code_size) {
4045                 cfg->code_size *= 2;
4046                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4047                 mono_jit_stats.code_reallocs++;
4048         }
4049
4050         /* FIXME: Emit unwind info */
4051
4052         buf = cfg->native_code + cfg->code_len;
4053
4054         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4055                 buf = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, buf, TRUE);
4056
4057         ia64_codegen_init (code, buf);
4058
4059         /* the code restoring the registers must be kept in sync with OP_JMP */
4060         pos = 0;
4061
4062         if (method->save_lmf) {
4063                 /* No LMF on IA64 */
4064         }
4065
4066         /* Load returned vtypes into registers if needed */
4067         cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
4068         ainfo = &cinfo->ret;
4069         switch (ainfo->storage) {
4070         case ArgAggregate:
4071                 if (ainfo->nslots != ainfo->nregs)
4072                         NOT_IMPLEMENTED;
4073
4074                 g_assert (cfg->ret->opcode == OP_REGOFFSET);
4075                 ia64_adds_imm (code, GP_SCRATCH_REG, cfg->ret->inst_offset, cfg->ret->inst_basereg);
4076                 for (i = 0; i < ainfo->nregs; ++i) {
4077                         switch (ainfo->atype) {
4078                         case AggregateNormal:
4079                                 ia64_ld8_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4080                                 break;
4081                         case AggregateSingleHFA:
4082                                 ia64_ldfs_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, 4, 0);
4083                                 break;
4084                         case AggregateDoubleHFA:
4085                                 ia64_ldfd_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4086                                 break;
4087                         default:
4088                                 g_assert_not_reached ();
4089                         }
4090                 }
4091                 break;
4092         default:
4093                 break;
4094         }
4095
4096         ia64_begin_bundle (code);
4097
4098         code.region_start = cfg->native_code;
4099
4100         /* Label the unwind state at the start of the exception throwing region */
4101         //ia64_unw_label_state (code, 1234);
4102
4103         if (cfg->arch.stack_alloc_size) {
4104                 if (cfg->arch.omit_fp) {
4105                         if (ia64_is_imm14 (cfg->arch.stack_alloc_size)) {
4106                                 ia64_unw_pop_frames (code, 1);
4107                                 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
4108                         } else {
4109                                 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
4110                                 ia64_unw_pop_frames (code, 1);
4111                                 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
4112                         }
4113                 }
4114                 else {
4115                         ia64_unw_pop_frames (code, 1);
4116                         ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
4117                 }
4118         }
4119         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
4120         ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
4121         ia64_br_ret_reg (code, IA64_B0);
4122
4123         ia64_codegen_close (code);
4124
4125         cfg->arch.r_epilog = mono_ia64_create_unwind_region (&code);
4126         cfg->arch.r_pro->next = cfg->arch.r_epilog;
4127
4128         cfg->code_len = code.buf - cfg->native_code;
4129
4130         g_assert (cfg->code_len < cfg->code_size);
4131 }
4132
4133 void
4134 mono_arch_emit_exceptions (MonoCompile *cfg)
4135 {
4136         MonoJumpInfo *patch_info;
4137         int i, nthrows;
4138         Ia64CodegenState code;
4139         gboolean empty = TRUE;
4140         //unw_dyn_region_info_t *r_exceptions;
4141         MonoClass *exc_classes [16];
4142         guint8 *exc_throw_start [16], *exc_throw_end [16];
4143         guint32 code_size = 0;
4144
4145         /* Compute needed space */
4146         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4147                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4148                         code_size += 256;
4149                 if (patch_info->type == MONO_PATCH_INFO_R8)
4150                         code_size += 8 + 7; /* sizeof (double) + alignment */
4151                 if (patch_info->type == MONO_PATCH_INFO_R4)
4152                         code_size += 4 + 7; /* sizeof (float) + alignment */
4153         }
4154
4155         if (code_size == 0)
4156                 return;
4157
4158         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4159                 cfg->code_size *= 2;
4160                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4161                 mono_jit_stats.code_reallocs++;
4162         }
4163
4164         ia64_codegen_init (code, cfg->native_code + cfg->code_len);
4165
4166         /* The unwind state here is the same as before the epilog */
4167         //ia64_unw_copy_state (code, 1234);
4168
4169         /* add code to raise exceptions */
4170         /* FIXME: Optimize this */
4171         nthrows = 0;
4172         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4173                 switch (patch_info->type) {
4174                 case MONO_PATCH_INFO_EXC: {
4175                         MonoClass *exc_class;
4176                         guint8* throw_ip;
4177                         guint8* buf;
4178                         guint64 exc_token_index;
4179
4180                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4181                         g_assert (exc_class);
4182                         exc_token_index = mono_metadata_token_index (exc_class->type_token);
4183                         throw_ip = cfg->native_code + patch_info->ip.i;
4184
4185                         ia64_begin_bundle (code);
4186
4187                         ia64_patch (cfg->native_code + patch_info->ip.i, code.buf);
4188
4189                         /* Find a throw sequence for the same exception class */
4190                         for (i = 0; i < nthrows; ++i)
4191                                 if (exc_classes [i] == exc_class)
4192                                         break;
4193
4194                         if (i < nthrows) {
4195                                 gint64 offset = exc_throw_end [i] - 16 - throw_ip;
4196
4197                                 if (ia64_is_adds_imm (offset))
4198                                         ia64_adds_imm (code, cfg->arch.reg_out0 + 1, offset, IA64_R0);
4199                                 else
4200                                         ia64_movl (code, cfg->arch.reg_out0 + 1, offset);
4201
4202                                 buf = code.buf + code.nins;
4203                                 ia64_br_cond_pred (code, 0, 0);
4204                                 ia64_begin_bundle (code);
4205                                 ia64_patch (buf, exc_throw_start [i]);
4206
4207                                 patch_info->type = MONO_PATCH_INFO_NONE;
4208                         }
4209                         else {
4210                                 /* Arg1 */
4211                                 buf = code.buf;
4212                                 ia64_movl (code, cfg->arch.reg_out0 + 1, 0);
4213
4214                                 ia64_begin_bundle (code);
4215
4216                                 if (nthrows < 16) {
4217                                         exc_classes [nthrows] = exc_class;
4218                                         exc_throw_start [nthrows] = code.buf;
4219                                 }
4220
4221                                 /* Arg2 */
4222                                 if (ia64_is_adds_imm (exc_token_index))
4223                                         ia64_adds_imm (code, cfg->arch.reg_out0 + 0, exc_token_index, IA64_R0);
4224                                 else
4225                                         ia64_movl (code, cfg->arch.reg_out0 + 0, exc_token_index);
4226
4227                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4228                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4229                                 patch_info->ip.i = code.buf + code.nins - cfg->native_code;
4230
4231                                 /* Indirect call */
4232                                 ia64_movl (code, GP_SCRATCH_REG, 0);
4233                                 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
4234                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
4235                                 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
4236
4237                                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
4238
4239                                 /* Patch up the throw offset */
4240                                 ia64_begin_bundle (code);
4241
4242                                 ia64_patch (buf, (gpointer)(code.buf - 16 - throw_ip));
4243
4244                                 if (nthrows < 16) {
4245                                         exc_throw_end [nthrows] = code.buf;
4246                                         nthrows ++;
4247                                 }
4248                         }
4249
4250                         empty = FALSE;
4251                         break;
4252                 }
4253                 default:
4254                         break;
4255                 }
4256         }
4257
4258         if (!empty)
4259                 /* The unwinder needs this to work */
4260                 ia64_break_i (code, 0);
4261
4262         ia64_codegen_close (code);
4263
4264         /* FIXME: */
4265         //r_exceptions = mono_ia64_create_unwind_region (&code);
4266         //cfg->arch.r_epilog = r_exceptions;
4267
4268         cfg->code_len = code.buf - cfg->native_code;
4269
4270         g_assert (cfg->code_len < cfg->code_size);
4271 }
4272
4273 void*
4274 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4275 {
4276         Ia64CodegenState code;
4277         CallInfo *cinfo = NULL;
4278         MonoMethodSignature *sig;
4279         MonoInst *ins;
4280         int i, n, stack_area = 0;
4281
4282         ia64_codegen_init (code, p);
4283
4284         /* Keep this in sync with mono_arch_get_argument_info */
4285
4286         if (enable_arguments) {
4287                 /* Allocate a new area on the stack and save arguments there */
4288                 sig = mono_method_signature (cfg->method);
4289
4290                 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4291
4292                 n = sig->param_count + sig->hasthis;
4293
4294                 stack_area = ALIGN_TO (n * 8, 16);
4295
4296                 if (n) {
4297                         ia64_movl (code, GP_SCRATCH_REG, stack_area);
4298
4299                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4300
4301                         /* FIXME: Allocate out registers */
4302
4303                         ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_SP);
4304
4305                         /* Required by the ABI */
4306                         ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4307
4308                         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4309                         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4310
4311                         /* Save arguments to the stack */
4312                         for (i = 0; i < n; ++i) {
4313                                 ins = cfg->args [i];
4314
4315                                 if (ins->opcode == OP_REGVAR) {
4316                                         ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4317                                         ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4318                                         ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
4319                                 }
4320                                 else {
4321                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
4322                                         ia64_add (code, GP_SCRATCH_REG, ins->inst_basereg, GP_SCRATCH_REG);
4323                                         ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
4324                                         ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4325                                         ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4326                                         ia64_st8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG2);
4327                                 }
4328                         }
4329                 }
4330                 else
4331                         ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4332         }
4333         else
4334                 ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4335
4336         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4337         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4338
4339         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4340
4341         if (enable_arguments && stack_area) {
4342                 ia64_movl (code, GP_SCRATCH_REG, stack_area);
4343
4344                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4345
4346                 ia64_adds_imm (code, IA64_SP, 16, IA64_SP);
4347         }
4348
4349         ia64_codegen_close (code);
4350
4351         return code.buf;
4352 }
4353
4354 void*
4355 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
4356 {
4357         Ia64CodegenState code;
4358         CallInfo *cinfo = NULL;
4359         MonoMethod *method = cfg->method;
4360         MonoMethodSignature *sig = mono_method_signature (cfg->method);
4361
4362         ia64_codegen_init (code, p);
4363
4364         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4365
4366         /* Save return value + pass it to func */
4367         switch (cinfo->ret.storage) {
4368         case ArgNone:
4369                 break;
4370         case ArgInIReg:
4371                 ia64_mov (code, cfg->arch.reg_saved_return_val, cinfo->ret.reg);
4372                 ia64_mov (code, cfg->arch.reg_out0 + 1, cinfo->ret.reg);
4373                 break;
4374         case ArgInFloatReg:
4375                 ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4376                 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4377                 ia64_stfd_hint (code, GP_SCRATCH_REG, cinfo->ret.reg, 0);
4378                 ia64_fmov (code, 8 + 1, cinfo->ret.reg);
4379                 break;
4380         case ArgValuetypeAddrInIReg:
4381                 ia64_mov (code, cfg->arch.reg_out0 + 1, cfg->arch.reg_in0 + cinfo->ret.reg);
4382                 break;
4383         case ArgAggregate:
4384                 NOT_IMPLEMENTED;
4385                 break;
4386         default:
4387                 break;
4388         }
4389
4390         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, method);
4391         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4392         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4393
4394         /* Restore return value */
4395         switch (cinfo->ret.storage) {
4396         case ArgNone:
4397                 break;
4398         case ArgInIReg:
4399                 ia64_mov (code, cinfo->ret.reg, cfg->arch.reg_saved_return_val);
4400                 break;
4401         case ArgInFloatReg:
4402                 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4403                 ia64_ldfd (code, cinfo->ret.reg, GP_SCRATCH_REG);
4404                 break;
4405         case ArgValuetypeAddrInIReg:
4406                 break;
4407         case ArgAggregate:
4408                 break;
4409         default:
4410                 break;
4411         }
4412
4413         ia64_codegen_close (code);
4414
4415         return code.buf;
4416 }
4417
4418 void
4419 mono_arch_save_unwind_info (MonoCompile *cfg)
4420 {
4421         unw_dyn_info_t *di;
4422
4423         /* FIXME: Unregister this for dynamic methods */
4424
4425         di = g_malloc0 (sizeof (unw_dyn_info_t));
4426         di->start_ip = (unw_word_t) cfg->native_code;
4427         di->end_ip = (unw_word_t) cfg->native_code + cfg->code_len;
4428         di->gp = 0;
4429         di->format = UNW_INFO_FORMAT_DYNAMIC;
4430         di->u.pi.name_ptr = (unw_word_t)mono_method_full_name (cfg->method, TRUE);
4431         di->u.pi.regions = cfg->arch.r_pro;
4432
4433         _U_dyn_register (di);
4434
4435         /*
4436         {
4437                 unw_dyn_region_info_t *region = di->u.pi.regions;
4438
4439                 printf ("Unwind info for method %s:\n", mono_method_full_name (cfg->method, TRUE));
4440                 while (region) {
4441                         printf ("    [Region: %d]\n", region->insn_count);
4442                         region = region->next;
4443                 }
4444         }
4445         */
4446 }
4447
4448 void
4449 mono_arch_flush_icache (guint8 *code, gint size)
4450 {
4451         guint8* p = (guint8*)((guint64)code & ~(0x3f));
4452         guint8* end = (guint8*)((guint64)code + size);
4453
4454 #ifdef __INTEL_COMPILER
4455         /* icc doesn't define an fc.i instrinsic, but fc==fc.i on itanium 2 */
4456         while (p < end) {
4457                 __fc ((guint64)p);
4458                 p += 32;
4459         }
4460 #else
4461         while (p < end) {
4462                 __asm__ __volatile__ ("fc.i %0"::"r"(p));
4463                 /* FIXME: This could be increased to 128 on some cpus */
4464                 p += 32;
4465         }
4466 #endif
4467 }
4468
4469 void
4470 mono_arch_flush_register_windows (void)
4471 {
4472         /* Not needed because of libunwind */
4473 }
4474
4475 gboolean
4476 mono_arch_is_inst_imm (gint64 imm)
4477 {
4478         /* The lowering pass will take care of it */
4479
4480         return TRUE;
4481 }
4482
4483 /*
4484  * Determine whenever the trap whose info is in SIGINFO is caused by
4485  * integer overflow.
4486  */
4487 gboolean
4488 mono_arch_is_int_overflow (void *sigctx, void *info)
4489 {
4490         /* Division is emulated with explicit overflow checks */
4491         return FALSE;
4492 }
4493
4494 guint32
4495 mono_arch_get_patch_offset (guint8 *code)
4496 {
4497         NOT_IMPLEMENTED;
4498
4499         return 0;
4500 }
4501
4502 gpointer
4503 mono_arch_get_vcall_slot (guint8* code, mgreg_t *regs, int *displacement)
4504 {
4505         guint8 *bundle2 = code - 48;
4506         guint8 *bundle3 = code - 32;
4507         guint8 *bundle4 = code - 16;
4508         guint64 ins21 = ia64_bundle_ins1 (bundle2);
4509         guint64 ins22 = ia64_bundle_ins2 (bundle2);
4510         guint64 ins23 = ia64_bundle_ins3 (bundle2);
4511         guint64 ins31 = ia64_bundle_ins1 (bundle3);
4512         guint64 ins32 = ia64_bundle_ins2 (bundle3);
4513         guint64 ins33 = ia64_bundle_ins3 (bundle3);
4514         guint64 ins41 = ia64_bundle_ins1 (bundle4);
4515         guint64 ins42 = ia64_bundle_ins2 (bundle4);
4516         guint64 ins43 = ia64_bundle_ins3 (bundle4);
4517
4518         /*
4519          * Virtual calls are made with:
4520          *
4521          * [MII]       ld8 r31=[r8]
4522          *             nop.i 0x0
4523          *             nop.i 0x0;;
4524          * [MII]       nop.m 0x0
4525          *             mov.sptk b6=r31,0x2000000000f32a80
4526          *             nop.i 0x0
4527          * [MII]       nop.m 0x0
4528          *             nop.i 0x123456
4529          *             nop.i 0x0
4530          * [MIB]       nop.m 0x0
4531          *             nop.i 0x0
4532          *             br.call.sptk.few b0=b6;;
4533          */
4534
4535         if (((ia64_bundle_template (bundle3) == IA64_TEMPLATE_MII) ||
4536                  (ia64_bundle_template (bundle3) == IA64_TEMPLATE_MIIS)) &&
4537                 (ia64_bundle_template (bundle4) == IA64_TEMPLATE_MIBS) &&
4538                 (ins31 == IA64_NOP_M) &&
4539                 (ia64_ins_opcode (ins32) == 0) && (ia64_ins_x3 (ins32) == 0) && (ia64_ins_x6 (ins32) == 0x1) && (ia64_ins_y (ins32) == 0) &&
4540                 (ins33 == IA64_NOP_I) &&
4541                 (ins41 == IA64_NOP_M) &&
4542                 (ins42 == IA64_NOP_I) &&
4543                 (ia64_ins_opcode (ins43) == 1) && (ia64_ins_b1 (ins43) == 0) && (ia64_ins_b2 (ins43) == 6) &&
4544                 ((ins32 >> 6) & 0xfffff) == 0x12345) {
4545                 g_assert (ins21 == IA64_NOP_M);
4546                 g_assert (ins23 == IA64_NOP_I);
4547                 g_assert (ia64_ins_opcode (ins22) == 0);
4548                 g_assert (ia64_ins_x3 (ins22) == 7);
4549                 g_assert (ia64_ins_x (ins22) == 0);
4550                 g_assert (ia64_ins_b1 (ins22) == IA64_B6);
4551
4552                 *displacement = (gssize)regs [IA64_R8] - (gssize)regs [IA64_R11];
4553
4554                 return regs [IA64_R11];
4555         }
4556
4557         return NULL;
4558 }
4559
4560 gpointer*
4561 mono_arch_get_delegate_method_ptr_addr (guint8* code, mgreg_t *regs)
4562 {
4563         NOT_IMPLEMENTED;
4564
4565         return NULL;
4566 }
4567
4568 void
4569 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
4570 {
4571 }
4572
4573 void
4574 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4575 {
4576 }
4577
4578 #ifdef MONO_ARCH_HAVE_IMT
4579
4580 /*
4581  * LOCKING: called with the domain lock held
4582  */
4583 gpointer
4584 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
4585         gpointer fail_tramp)
4586 {
4587         int i;
4588         int size = 0;
4589         guint8 *start, *buf;
4590         Ia64CodegenState code;
4591
4592         g_assert (!fail_tramp);
4593
4594         size = count * 256;
4595         buf = g_malloc0 (size);
4596         ia64_codegen_init (code, buf);
4597
4598         /* IA64_R9 contains the IMT method */
4599
4600         for (i = 0; i < count; ++i) {
4601                 MonoIMTCheckItem *item = imt_entries [i];
4602                 ia64_begin_bundle (code);
4603                 item->code_target = (guint8*)code.buf + code.nins;
4604                 if (item->is_equals) {
4605                         if (item->check_target_idx) {
4606                                 if (!item->compare_done) {
4607                                         ia64_movl (code, GP_SCRATCH_REG, item->key);
4608                                         ia64_cmp_eq (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4609                                 }
4610                                 item->jmp_code = (guint8*)code.buf + code.nins;
4611                                 ia64_br_cond_pred (code, 7, 0);
4612
4613                                 ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4614                                 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4615                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4616                                 ia64_br_cond_reg (code, IA64_B6);
4617                         } else {
4618                                 /* enable the commented code to assert on wrong method */
4619 #if ENABLE_WRONG_METHOD_CHECK
4620                                 g_assert_not_reached ();
4621 #endif
4622                                 ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4623                                 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4624                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4625                                 ia64_br_cond_reg (code, IA64_B6);
4626 #if ENABLE_WRONG_METHOD_CHECK
4627                                 g_assert_not_reached ();
4628 #endif
4629                         }
4630                 } else {
4631                         ia64_movl (code, GP_SCRATCH_REG, item->key);
4632                         ia64_cmp_geu (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4633                         item->jmp_code = (guint8*)code.buf + code.nins;
4634                         ia64_br_cond_pred (code, 6, 0);
4635                 }
4636         }
4637         /* patch the branches to get to the target items */
4638         for (i = 0; i < count; ++i) {
4639                 MonoIMTCheckItem *item = imt_entries [i];
4640                 if (item->jmp_code) {
4641                         if (item->check_target_idx) {
4642                                 ia64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
4643                         }
4644                 }
4645         }
4646
4647         ia64_codegen_close (code);
4648         g_assert (code.buf - buf <= size);
4649
4650         size = code.buf - buf;
4651         start = mono_domain_code_reserve (domain, size);
4652         memcpy (start, buf, size);
4653
4654         mono_arch_flush_icache (start, size);
4655
4656         mono_stats.imt_thunks_size += size;
4657
4658         return start;
4659 }
4660
4661 MonoMethod*
4662 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
4663 {
4664         return regs [IA64_R9];
4665 }
4666
4667 void
4668 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
4669 {
4670         /* Done by the implementation of the CALL_MEMBASE opcodes */
4671 }
4672 #endif
4673
4674 gpointer
4675 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, mgreg_t *regs, guint8 *code)
4676 {
4677         return (gpointer)regs [IA64_R10];
4678 }
4679
4680 MonoObject*
4681 mono_arch_find_this_argument (mgreg_t *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
4682 {
4683         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), regs, NULL);
4684 }
4685
4686 gpointer
4687 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
4688 {
4689         return NULL;
4690 }
4691
4692 MonoInst*
4693 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4694 {
4695         MonoInst *ins = NULL;
4696
4697         if (cmethod->klass->image == mono_defaults.corlib &&
4698                 (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
4699                 (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
4700
4701                 /*
4702                  * We don't use the generic version in mini_emit_inst_for_method () since we
4703                  * ia64 has atomic_add_imm opcodes.
4704                  */
4705                 if (strcmp (cmethod->name, "Increment") == 0) {
4706                         guint32 opcode;
4707
4708                         if (fsig->params [0]->type == MONO_TYPE_I4)
4709                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4710                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4711                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4712                         else
4713                                 g_assert_not_reached ();
4714                         MONO_INST_NEW (cfg, ins, opcode);
4715                         ins->dreg = mono_alloc_preg (cfg);
4716                         ins->inst_imm = 1;
4717                         ins->inst_basereg = args [0]->dreg;
4718                         ins->inst_offset = 0;
4719                         MONO_ADD_INS (cfg->cbb, ins);
4720                 } else if (strcmp (cmethod->name, "Decrement") == 0) {
4721                         guint32 opcode;
4722
4723                         if (fsig->params [0]->type == MONO_TYPE_I4)
4724                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4725                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4726                                 opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4727                         else
4728                                 g_assert_not_reached ();
4729                         MONO_INST_NEW (cfg, ins, opcode);
4730                         ins->dreg = mono_alloc_preg (cfg);
4731                         ins->inst_imm = -1;
4732                         ins->inst_basereg = args [0]->dreg;
4733                         ins->inst_offset = 0;
4734                         MONO_ADD_INS (cfg->cbb, ins);
4735                 } else if (strcmp (cmethod->name, "Add") == 0) {
4736                         guint32 opcode;
4737                         gboolean is_imm = FALSE;
4738                         gint64 imm = 0;
4739
4740                         if ((args [1]->opcode == OP_ICONST) || (args [1]->opcode == OP_I8CONST)) {
4741                                 imm = (args [1]->opcode == OP_ICONST) ? args [1]->inst_c0 : args [1]->inst_l;
4742
4743                                 is_imm = (imm == 1 || imm == 4 || imm == 8 || imm == 16 || imm == -1 || imm == -4 || imm == -8 || imm == -16);
4744                         }
4745
4746                         if (is_imm) {
4747                                 if (fsig->params [0]->type == MONO_TYPE_I4)
4748                                         opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4749                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
4750                                         opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4751                                 else
4752                                         g_assert_not_reached ();
4753
4754                                 MONO_INST_NEW (cfg, ins, opcode);
4755                                 ins->dreg = mono_alloc_ireg (cfg);
4756                                 ins->inst_basereg = args [0]->dreg;
4757                                 ins->inst_offset = 0;
4758                                 ins->inst_imm = imm;
4759                                 ins->type = (opcode == OP_ATOMIC_ADD_IMM_NEW_I4) ? STACK_I4 : STACK_I8;
4760                         } else {
4761                                 if (fsig->params [0]->type == MONO_TYPE_I4)
4762                                         opcode = OP_ATOMIC_ADD_NEW_I4;
4763                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
4764                                         opcode = OP_ATOMIC_ADD_NEW_I8;
4765                                 else
4766                                         g_assert_not_reached ();
4767
4768                                 MONO_INST_NEW (cfg, ins, opcode);
4769                                 ins->dreg = mono_alloc_ireg (cfg);
4770                                 ins->inst_basereg = args [0]->dreg;
4771                                 ins->inst_offset = 0;
4772                                 ins->sreg2 = args [1]->dreg;
4773                                 ins->type = (opcode == OP_ATOMIC_ADD_NEW_I4) ? STACK_I4 : STACK_I8;
4774                         }
4775                         MONO_ADD_INS (cfg->cbb, ins);
4776                 }
4777         }
4778
4779         return ins;
4780 }
4781
4782 gboolean
4783 mono_arch_print_tree (MonoInst *tree, int arity)
4784 {
4785         return 0;
4786 }
4787
4788 MonoInst*
4789 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
4790 {
4791         return mono_get_domain_intrinsic (cfg);
4792 }
4793
4794 MonoInst*
4795 mono_arch_get_thread_intrinsic (MonoCompile* cfg)
4796 {
4797         return mono_get_thread_intrinsic (cfg);
4798 }
4799
4800 gpointer
4801 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
4802 {
4803         /* FIXME: implement */
4804         g_assert_not_reached ();
4805 }