mono/mini/mini-ia64.c

   1 /*
   2  * mini-ia64.c: IA64 backend for the Mono code generator
   3  *
   4  * Authors:
   5  *   Zoltan Varga (vargaz@gmail.com)
   6  *
   7  * (C) 2003 Ximian, Inc.
   8  */
   9 #include "mini.h"
  10 #include <string.h>
  11 #include <math.h>
  12 #include <unistd.h>
  13 #include <sys/mman.h>
  14
  15 #ifdef __INTEL_COMPILER
  16 #include <ia64intrin.h>
  17 #endif
  18
  19 #include <mono/metadata/appdomain.h>
  20 #include <mono/metadata/debug-helpers.h>
  21 #include <mono/metadata/threads.h>
  22 #include <mono/metadata/profiler-private.h>
  23 #include <mono/utils/mono-math.h>
  24 #include <mono/utils/mono-hwcap-ia64.h>
  25
  26 #include "trace.h"
  27 #include "mini-ia64.h"
  28 #include "cpu-ia64.h"
  29 #include "jit-icalls.h"
  30 #include "ir-emit.h"
  31
  32 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  33
  34 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  35
  36 /*
  37  * IA64 register usage:
  38  * - local registers are used for global register allocation
  39  * - r8..r11, r14..r30 is used for local register allocation
  40  * - r31 is a scratch register used within opcode implementations
  41  * - FIXME: Use out registers as well
  42  * - the first three locals are used for saving ar.pfst, b0, and sp
  43  * - compare instructions allways set p6 and p7
  44  */
  45
  46 /*
  47  * There are a lot of places where generated code is disassembled/patched.
  48  * The automatic bundling of instructions done by the code generation macros
  49  * could complicate things, so it is best to call
  50  * ia64_codegen_set_one_ins_per_bundle () at those places.
  51  */
  52
  53 #define ARGS_OFFSET 16
  54
  55 #define GP_SCRATCH_REG 31
  56 #define GP_SCRATCH_REG2 30
  57 #define FP_SCRATCH_REG 32
  58 #define FP_SCRATCH_REG2 33
  59
  60 #define LOOP_ALIGNMENT 8
  61 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
  62
  63 static const char* gregs [] = {
  64         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
  65         "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
  66         "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29",
  67         "r30", "r31", "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  68         "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", "r48", "r49",
  69         "r50", "r51", "r52", "r53", "r54", "r55", "r56", "r57", "r58", "r59",
  70         "r60", "r61", "r62", "r63", "r64", "r65", "r66", "r67", "r68", "r69",
  71         "r70", "r71", "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
  72         "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", "r88", "r89",
  73         "r90", "r91", "r92", "r93", "r94", "r95", "r96", "r97", "r98", "r99",
  74         "r100", "r101", "r102", "r103", "r104", "r105", "r106", "r107", "r108", "r109",
  75         "r110", "r111", "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
  76         "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127"
  77 };
  78
  79 const char*
  80 mono_arch_regname (int reg)
  81 {
  82         if (reg < 128)
  83                 return gregs [reg];
  84         else
  85                 return "unknown";
  86 }
  87
  88 static const char* fregs [] = {
  89         "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
  90         "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
  91         "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
  92         "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
  93         "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
  94         "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
  95         "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69",
  96         "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
  97         "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89",
  98         "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99",
  99         "f100", "f101", "f102", "f103", "f104", "f105", "f106", "f107", "f108", "f109",
 100         "f110", "f111", "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
 101         "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127"
 102 };
 103
 104 const char*
 105 mono_arch_fregname (int reg)
 106 {
 107         if (reg < 128)
 108                 return fregs [reg];
 109         else
 110                 return "unknown";
 111 }
 112
 113 static gboolean
 114 debug_ins_sched (void)
 115 {
 116 #if 0
 117         return mono_debug_count ();
 118 #else
 119         return TRUE;
 120 #endif
 121 }
 122
 123 static gboolean
 124 debug_omit_fp (void)
 125 {
 126 #if 0
 127         return mono_debug_count ();
 128 #else
 129         return TRUE;
 130 #endif
 131 }
 132
 133 static void
 134 ia64_patch (unsigned char* code, gpointer target);
 135
 136 typedef enum {
 137         ArgInIReg,
 138         ArgInFloatReg,
 139         ArgInFloatRegR4,
 140         ArgOnStack,
 141         ArgValuetypeAddrInIReg,
 142         ArgAggregate,
 143         ArgSingleHFA,
 144         ArgDoubleHFA,
 145         ArgNone
 146 } ArgStorage;
 147
 148 typedef enum {
 149         AggregateNormal,
 150         AggregateSingleHFA,
 151         AggregateDoubleHFA
 152 } AggregateType;
 153
 154 typedef struct {
 155         gint16 offset;
 156         gint8  reg;
 157         ArgStorage storage;
 158
 159         /* Only if storage == ArgAggregate */
 160         int nregs, nslots;
 161         AggregateType atype;
 162 } ArgInfo;
 163
 164 typedef struct {
 165         int nargs;
 166         guint32 stack_usage;
 167         guint32 reg_usage;
 168         guint32 freg_usage;
 169         gboolean need_stack_align;
 170         gboolean vtype_retaddr;
 171         /* The index of the vret arg in the argument list */
 172         int vret_arg_index;
 173         ArgInfo ret;
 174         ArgInfo sig_cookie;
 175         ArgInfo args [1];
 176 } CallInfo;
 177
 178 #define DEBUG(a) if (cfg->verbose_level > 1) a
 179
 180 #define PARAM_REGS 8
 181
 182 static void inline
 183 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 184 {
 185     ainfo->offset = *stack_size;
 186
 187     if (*gr >= PARAM_REGS) {
 188                 ainfo->storage = ArgOnStack;
 189                 (*stack_size) += sizeof (gpointer);
 190     }
 191     else {
 192                 ainfo->storage = ArgInIReg;
 193                 ainfo->reg = *gr;
 194                 *(gr) += 1;
 195     }
 196 }
 197
 198 #define FLOAT_PARAM_REGS 8
 199
 200 static void inline
 201 add_float (guint32 *gr, guint32 *fr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 202 {
 203     ainfo->offset = *stack_size;
 204
 205     if (*gr >= PARAM_REGS) {
 206                 ainfo->storage = ArgOnStack;
 207                 (*stack_size) += sizeof (gpointer);
 208     }
 209     else {
 210                 ainfo->storage = is_double ? ArgInFloatReg : ArgInFloatRegR4;
 211                 ainfo->reg = 8 + *fr;
 212                 (*fr) += 1;
 213                 (*gr) += 1;
 214     }
 215 }
 216
 217 static void
 218 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 219                gboolean is_return,
 220                guint32 *gr, guint32 *fr, guint32 *stack_size)
 221 {
 222         guint32 size, i;
 223         MonoClass *klass;
 224         MonoMarshalType *info;
 225         gboolean is_hfa = TRUE;
 226         guint32 hfa_type = 0;
 227
 228         klass = mono_class_from_mono_type (type);
 229         if (type->type == MONO_TYPE_TYPEDBYREF)
 230                 size = 3 * sizeof (gpointer);
 231         else if (sig->pinvoke)
 232                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 233         else
 234                 size = mini_type_stack_size (&klass->byval_arg, NULL);
 235
 236         if (!sig->pinvoke || (size == 0)) {
 237                 /* Allways pass in memory */
 238                 ainfo->offset = *stack_size;
 239                 *stack_size += ALIGN_TO (size, 8);
 240                 ainfo->storage = ArgOnStack;
 241
 242                 return;
 243         }
 244
 245         /* Determine whenever it is a HFA (Homogeneous Floating Point Aggregate) */
 246         info = mono_marshal_load_type_info (klass);
 247         g_assert (info);
 248         for (i = 0; i < info->num_fields; ++i) {
 249                 guint32 ftype = info->fields [i].field->type->type;
 250                 if (!(info->fields [i].field->type->byref) &&
 251                         ((ftype == MONO_TYPE_R4) || (ftype == MONO_TYPE_R8))) {
 252                         if (hfa_type == 0)
 253                                 hfa_type = ftype;
 254                         else if (hfa_type != ftype)
 255                                 is_hfa = FALSE;
 256                 }
 257                 else
 258                         is_hfa = FALSE;
 259         }
 260         if (hfa_type == 0)
 261                 is_hfa = FALSE;
 262
 263         ainfo->storage = ArgAggregate;
 264         ainfo->atype = AggregateNormal;
 265
 266         if (is_hfa) {
 267                 ainfo->atype = hfa_type == MONO_TYPE_R4 ? AggregateSingleHFA : AggregateDoubleHFA;
 268                 if (is_return) {
 269                         if (info->num_fields <= 8) {
 270                                 ainfo->reg = 8;
 271                                 ainfo->nregs = info->num_fields;
 272                                 ainfo->nslots = ainfo->nregs;
 273                                 return;
 274                         }
 275                         /* Fall through */
 276                 }
 277                 else {
 278                         if ((*fr) + info->num_fields > 8)
 279                                 NOT_IMPLEMENTED;
 280
 281                         ainfo->reg = 8 + (*fr);
 282                         ainfo->nregs = info->num_fields;
 283                         ainfo->nslots = ainfo->nregs;
 284                         (*fr) += info->num_fields;
 285                         if (ainfo->atype == AggregateSingleHFA) {
 286                                 /*
 287                                  * FIXME: Have to keep track of the parameter slot number, which is
 288                                  * not the same as *gr.
 289                                  */
 290                                 (*gr) += ALIGN_TO (info->num_fields, 2) / 2;
 291                         } else {
 292                                 (*gr) += info->num_fields;
 293                         }
 294                         return;
 295                 }
 296         }
 297
 298         /* This also handles returning of TypedByRef used by some icalls */
 299         if (is_return) {
 300                 if (size <= 32) {
 301                         ainfo->reg = IA64_R8;
 302                         ainfo->nregs = (size + 7) / 8;
 303                         ainfo->nslots = ainfo->nregs;
 304                         return;
 305                 }
 306                 NOT_IMPLEMENTED;
 307         }
 308
 309         ainfo->reg = (*gr);
 310         ainfo->offset = *stack_size;
 311         ainfo->nslots = (size + 7) / 8;
 312
 313         if (((*gr) + ainfo->nslots) <= 8) {
 314                 /* Fits entirely in registers */
 315                 ainfo->nregs = ainfo->nslots;
 316                 (*gr) += ainfo->nregs;
 317                 return;
 318         }
 319
 320         ainfo->nregs = 8 - (*gr);
 321         (*gr) = 8;
 322         (*stack_size) += (ainfo->nslots - ainfo->nregs) * 8;
 323 }
 324
 325 /*
 326  * get_call_info:
 327  *
 328  *  Obtain information about a call according to the calling convention.
 329  * For IA64, see the "Itanium Software Conventions and Runtime Architecture
 330  * Gude" document for more information.
 331  */
 332 static CallInfo*
 333 get_call_info (MonoCompile *cfg, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 334 {
 335         guint32 i, gr, fr, pstart;
 336         MonoType *ret_type;
 337         int n = sig->hasthis + sig->param_count;
 338         guint32 stack_size = 0;
 339         CallInfo *cinfo;
 340
 341         if (mp)
 342                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 343         else
 344                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 345
 346         gr = 0;
 347         fr = 0;
 348
 349         /* return value */
 350         {
 351                 ret_type = mini_get_underlying_type (sig->ret);
 352                 switch (ret_type->type) {
 353                 case MONO_TYPE_BOOLEAN:
 354                 case MONO_TYPE_I1:
 355                 case MONO_TYPE_U1:
 356                 case MONO_TYPE_I2:
 357                 case MONO_TYPE_U2:
 358                 case MONO_TYPE_CHAR:
 359                 case MONO_TYPE_I4:
 360                 case MONO_TYPE_U4:
 361                 case MONO_TYPE_I:
 362                 case MONO_TYPE_U:
 363                 case MONO_TYPE_PTR:
 364                 case MONO_TYPE_FNPTR:
 365                 case MONO_TYPE_CLASS:
 366                 case MONO_TYPE_OBJECT:
 367                 case MONO_TYPE_SZARRAY:
 368                 case MONO_TYPE_ARRAY:
 369                 case MONO_TYPE_STRING:
 370                         cinfo->ret.storage = ArgInIReg;
 371                         cinfo->ret.reg = IA64_R8;
 372                         break;
 373                 case MONO_TYPE_U8:
 374                 case MONO_TYPE_I8:
 375                         cinfo->ret.storage = ArgInIReg;
 376                         cinfo->ret.reg = IA64_R8;
 377                         break;
 378                 case MONO_TYPE_R4:
 379                 case MONO_TYPE_R8:
 380                         cinfo->ret.storage = ArgInFloatReg;
 381                         cinfo->ret.reg = 8;
 382                         break;
 383                 case MONO_TYPE_GENERICINST:
 384                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 385                                 cinfo->ret.storage = ArgInIReg;
 386                                 cinfo->ret.reg = IA64_R8;
 387                                 break;
 388                         }
 389                         /* Fall through */
 390                 case MONO_TYPE_VALUETYPE:
 391                 case MONO_TYPE_TYPEDBYREF: {
 392                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 393
 394                         if (sig->ret->byref) {
 395                                 /* This seems to happen with ldfld wrappers */
 396                                 cinfo->ret.storage = ArgInIReg;
 397                         } else {
 398                                 add_valuetype (sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 399                                 if (cinfo->ret.storage == ArgOnStack) {
 400                                         /* The caller passes the address where the value is stored */
 401                                         cinfo->vtype_retaddr = TRUE;
 402                                 }
 403                         }
 404                         break;
 405                 }
 406                 case MONO_TYPE_VOID:
 407                         cinfo->ret.storage = ArgNone;
 408                         break;
 409                 default:
 410                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 411                 }
 412         }
 413
 414         pstart = 0;
 415         /*
 416          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 417          * the first argument, allowing 'this' to be always passed in the first arg reg.
 418          * Also do this if the first argument is a reference type, since virtual calls
 419          * are sometimes made using calli without sig->hasthis set, like in the delegate
 420          * invoke wrappers.
 421          */
 422         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
 423                 if (sig->hasthis) {
 424                         add_general (&gr, &stack_size, cinfo->args + 0);
 425                 } else {
 426                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 427                         pstart = 1;
 428                 }
 429                 add_general (&gr, &stack_size, &cinfo->ret);
 430                 if (cinfo->ret.storage == ArgInIReg)
 431                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
 432                 cinfo->vret_arg_index = 1;
 433         } else {
 434                 /* this */
 435                 if (sig->hasthis)
 436                         add_general (&gr, &stack_size, cinfo->args + 0);
 437
 438                 if (cinfo->vtype_retaddr) {
 439                         add_general (&gr, &stack_size, &cinfo->ret);
 440                         if (cinfo->ret.storage == ArgInIReg)
 441                                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
 442                 }
 443         }
 444
 445         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 446                 gr = PARAM_REGS;
 447                 fr = FLOAT_PARAM_REGS;
 448
 449                 /* Emit the signature cookie just before the implicit arguments */
 450                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 451         }
 452
 453         for (i = pstart; i < sig->param_count; ++i) {
 454                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 455                 MonoType *ptype;
 456
 457                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 458                         /* We allways pass the sig cookie on the stack for simplicity */
 459                         /*
 460                          * Prevent implicit arguments + the sig cookie from being passed
 461                          * in registers.
 462                          */
 463                         gr = PARAM_REGS;
 464                         fr = FLOAT_PARAM_REGS;
 465
 466                         /* Emit the signature cookie just before the implicit arguments */
 467                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 468                 }
 469
 470                 if (sig->params [i]->byref) {
 471                         add_general (&gr, &stack_size, ainfo);
 472                         continue;
 473                 }
 474                 ptype = mini_get_underlying_type (sig->params [i]);
 475                 switch (ptype->type) {
 476                 case MONO_TYPE_BOOLEAN:
 477                 case MONO_TYPE_I1:
 478                 case MONO_TYPE_U1:
 479                         add_general (&gr, &stack_size, ainfo);
 480                         break;
 481                 case MONO_TYPE_I2:
 482                 case MONO_TYPE_U2:
 483                 case MONO_TYPE_CHAR:
 484                         add_general (&gr, &stack_size, ainfo);
 485                         break;
 486                 case MONO_TYPE_I4:
 487                 case MONO_TYPE_U4:
 488                         add_general (&gr, &stack_size, ainfo);
 489                         break;
 490                 case MONO_TYPE_I:
 491                 case MONO_TYPE_U:
 492                 case MONO_TYPE_PTR:
 493                 case MONO_TYPE_FNPTR:
 494                 case MONO_TYPE_CLASS:
 495                 case MONO_TYPE_OBJECT:
 496                 case MONO_TYPE_STRING:
 497                 case MONO_TYPE_SZARRAY:
 498                 case MONO_TYPE_ARRAY:
 499                         add_general (&gr, &stack_size, ainfo);
 500                         break;
 501                 case MONO_TYPE_GENERICINST:
 502                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 503                                 add_general (&gr, &stack_size, ainfo);
 504                                 break;
 505                         }
 506                         /* Fall through */
 507                 case MONO_TYPE_VALUETYPE:
 508                 case MONO_TYPE_TYPEDBYREF:
 509                         /* FIXME: */
 510                         /* We allways pass valuetypes on the stack */
 511                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 512                         break;
 513                 case MONO_TYPE_U8:
 514                 case MONO_TYPE_I8:
 515                         add_general (&gr, &stack_size, ainfo);
 516                         break;
 517                 case MONO_TYPE_R4:
 518                         add_float (&gr, &fr, &stack_size, ainfo, FALSE);
 519                         break;
 520                 case MONO_TYPE_R8:
 521                         add_float (&gr, &fr, &stack_size, ainfo, TRUE);
 522                         break;
 523                 default:
 524                         g_assert_not_reached ();
 525                 }
 526         }
 527
 528         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 529                 gr = PARAM_REGS;
 530                 fr = FLOAT_PARAM_REGS;
 531
 532                 /* Emit the signature cookie just before the implicit arguments */
 533                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 534         }
 535
 536         cinfo->stack_usage = stack_size;
 537         cinfo->reg_usage = gr;
 538         cinfo->freg_usage = fr;
 539         return cinfo;
 540 }
 541
 542 /*
 543  * mono_arch_get_argument_info:
 544  * @csig:  a method signature
 545  * @param_count: the number of parameters to consider
 546  * @arg_info: an array to store the result infos
 547  *
 548  * Gathers information on parameters such as size, alignment and
 549  * padding. arg_info should be large enought to hold param_count + 1 entries.
 550  *
 551  * Returns the size of the argument area on the stack.
 552  */
 553 int
 554 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 555 {
 556         int k;
 557         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 558         guint32 args_size = cinfo->stack_usage;
 559
 560         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 561         if (csig->hasthis) {
 562                 arg_info [0].offset = 0;
 563         }
 564
 565         for (k = 0; k < param_count; k++) {
 566                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 567                 /* FIXME: */
 568                 arg_info [k + 1].size = 0;
 569         }
 570
 571         g_free (cinfo);
 572
 573         return args_size;
 574 }
 575
 576 /*
 577  * Initialize the cpu to execute managed code.
 578  */
 579 void
 580 mono_arch_cpu_init (void)
 581 {
 582 }
 583
 584 /*
 585  * Initialize architecture specific code.
 586  */
 587 void
 588 mono_arch_init (void)
 589 {
 590 }
 591
 592 /*
 593  * Cleanup architecture specific code.
 594  */
 595 void
 596 mono_arch_cleanup (void)
 597 {
 598 }
 599
 600 /*
 601  * This function returns the optimizations supported on this cpu.
 602  */
 603 guint32
 604 mono_arch_cpu_optimizations (guint32 *exclude_mask)
 605 {
 606         *exclude_mask = 0;
 607
 608         return 0;
 609 }
 610
 611 /*
 612  * This function test for all SIMD functions supported.
 613  *
 614  * Returns a bitmask corresponding to all supported versions.
 615  *
 616  */
 617 guint32
 618 mono_arch_cpu_enumerate_simd_versions (void)
 619 {
 620         /* SIMD is currently unimplemented */
 621         return 0;
 622 }
 623
 624 GList *
 625 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 626 {
 627         GList *vars = NULL;
 628         int i;
 629         MonoMethodSignature *sig;
 630         MonoMethodHeader *header;
 631         CallInfo *cinfo;
 632
 633         header = cfg->header;
 634
 635         sig = mono_method_signature (cfg->method);
 636
 637         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 638
 639         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 640                 MonoInst *ins = cfg->args [i];
 641
 642                 ArgInfo *ainfo = &cinfo->args [i];
 643
 644                 if (ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 645                         continue;
 646
 647                 if (ainfo->storage == ArgInIReg) {
 648                         /* The input registers are non-volatile */
 649                         ins->opcode = OP_REGVAR;
 650                         ins->dreg = 32 + ainfo->reg;
 651                 }
 652         }
 653
 654         for (i = 0; i < cfg->num_varinfo; i++) {
 655                 MonoInst *ins = cfg->varinfo [i];
 656                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 657
 658                 /* unused vars */
 659                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 660                         continue;
 661
 662                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 663                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 664                         continue;
 665
 666                 if (mono_is_regsize_var (ins->inst_vtype)) {
 667                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 668                         g_assert (i == vmv->idx);
 669                         vars = g_list_prepend (vars, vmv);
 670                 }
 671         }
 672
 673         vars = mono_varlist_sort (cfg, vars, 0);
 674
 675         return vars;
 676 }
 677
 678 static void
 679 mono_ia64_alloc_stacked_registers (MonoCompile *cfg)
 680 {
 681         CallInfo *cinfo;
 682         guint32 reserved_regs;
 683         MonoMethodHeader *header;
 684
 685         if (cfg->arch.reg_local0 > 0)
 686                 /* Already done */
 687                 return;
 688
 689         cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (cfg->method), FALSE);
 690
 691         header = cfg->header;
 692
 693         /* Some registers are reserved for use by the prolog/epilog */
 694         reserved_regs = header->num_clauses ? 4 : 3;
 695
 696         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 697                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
 698                 /* One registers is needed by instrument_epilog to save the return value */
 699                 reserved_regs ++;
 700                 if (cinfo->reg_usage < 2)
 701                         /* Number of arguments passed to function call in instrument_prolog */
 702                         cinfo->reg_usage = 2;
 703         }
 704
 705         cfg->arch.reg_in0 = 32;
 706         cfg->arch.reg_local0 = cfg->arch.reg_in0 + cinfo->reg_usage + reserved_regs;
 707         cfg->arch.reg_out0 = cfg->arch.reg_local0 + 16;
 708
 709         cfg->arch.reg_saved_ar_pfs = cfg->arch.reg_local0 - 1;
 710         cfg->arch.reg_saved_b0 = cfg->arch.reg_local0 - 2;
 711         cfg->arch.reg_fp = cfg->arch.reg_local0 - 3;
 712
 713         /*
 714          * Frames without handlers save sp to fp, frames with handlers save it into
 715          * a dedicated register.
 716          */
 717         if (header->num_clauses)
 718                 cfg->arch.reg_saved_sp = cfg->arch.reg_local0 - 4;
 719         else
 720                 cfg->arch.reg_saved_sp = cfg->arch.reg_fp;
 721
 722         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 723                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
 724                 cfg->arch.reg_saved_return_val = cfg->arch.reg_local0 - reserved_regs;
 725         }
 726
 727         /*
 728          * Need to allocate at least 2 out register for use by OP_THROW / the system
 729          * exception throwing code.
 730          */
 731         cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, 2);
 732 }
 733
 734 GList *
 735 mono_arch_get_global_int_regs (MonoCompile *cfg)
 736 {
 737         GList *regs = NULL;
 738         int i;
 739
 740         mono_ia64_alloc_stacked_registers (cfg);
 741
 742         for (i = cfg->arch.reg_local0; i < cfg->arch.reg_out0; ++i) {
 743                 /* FIXME: regmask */
 744                 g_assert (i < 64);
 745                 regs = g_list_prepend (regs, (gpointer)(gssize)(i));
 746         }
 747
 748         return regs;
 749 }
 750
 751 /*
 752  * mono_arch_regalloc_cost:
 753  *
 754  *  Return the cost, in number of memory references, of the action of
 755  * allocating the variable VMV into a register during global register
 756  * allocation.
 757  */
 758 guint32
 759 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 760 {
 761         /* FIXME: Increase costs linearly to avoid using all local registers */
 762
 763         return 0;
 764 }
 765
 766 void
 767 mono_arch_allocate_vars (MonoCompile *cfg)
 768 {
 769         MonoMethodSignature *sig;
 770         MonoMethodHeader *header;
 771         MonoInst *inst;
 772         int i, offset;
 773         guint32 locals_stack_size, locals_stack_align;
 774         gint32 *offsets;
 775         CallInfo *cinfo;
 776
 777         header = cfg->header;
 778
 779         sig = mono_method_signature (cfg->method);
 780
 781         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 782
 783         /*
 784          * Determine whenever the frame pointer can be eliminated.
 785          * FIXME: Remove some of the restrictions.
 786          */
 787         cfg->arch.omit_fp = TRUE;
 788
 789         if (!debug_omit_fp ())
 790                 cfg->arch.omit_fp = FALSE;
 791
 792         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 793                 cfg->arch.omit_fp = FALSE;
 794         if (header->num_clauses)
 795                 cfg->arch.omit_fp = FALSE;
 796         if (cfg->param_area)
 797                 cfg->arch.omit_fp = FALSE;
 798         if ((sig->ret->type != MONO_TYPE_VOID) && (cinfo->ret.storage == ArgAggregate))
 799                 cfg->arch.omit_fp = FALSE;
 800         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 801                 cfg->arch.omit_fp = FALSE;
 802         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 803                 ArgInfo *ainfo = &cinfo->args [i];
 804
 805                 if (ainfo->storage == ArgOnStack) {
 806                         /*
 807                          * The stack offset can only be determined when the frame
 808                          * size is known.
 809                          */
 810                         cfg->arch.omit_fp = FALSE;
 811                 }
 812         }
 813
 814         mono_ia64_alloc_stacked_registers (cfg);
 815
 816         /*
 817          * We use the ABI calling conventions for managed code as well.
 818          * Exception: valuetypes are never passed or returned in registers.
 819          */
 820
 821         if (cfg->arch.omit_fp) {
 822                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
 823                 cfg->frame_reg = IA64_SP;
 824                 offset = ARGS_OFFSET;
 825         }
 826         else {
 827                 /* Locals are allocated backwards from %fp */
 828                 cfg->frame_reg = cfg->arch.reg_fp;
 829                 offset = 0;
 830         }
 831
 832         if (cfg->method->save_lmf) {
 833                 /* No LMF on IA64 */
 834         }
 835
 836         if (sig->ret->type != MONO_TYPE_VOID) {
 837                 switch (cinfo->ret.storage) {
 838                 case ArgInIReg:
 839                         cfg->ret->opcode = OP_REGVAR;
 840                         cfg->ret->inst_c0 = cinfo->ret.reg;
 841                         break;
 842                 case ArgInFloatReg:
 843                         cfg->ret->opcode = OP_REGVAR;
 844                         cfg->ret->inst_c0 = cinfo->ret.reg;
 845                         break;
 846                 case ArgValuetypeAddrInIReg:
 847                         cfg->vret_addr->opcode = OP_REGVAR;
 848                         cfg->vret_addr->dreg = cfg->arch.reg_in0 + cinfo->ret.reg;
 849                         break;
 850                 case ArgAggregate:
 851                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
 852                         if (cfg->arch.omit_fp)
 853                                 g_assert_not_reached ();
 854                         offset = ALIGN_TO (offset, 8);
 855                         offset += cinfo->ret.nslots * 8;
 856                         cfg->ret->opcode = OP_REGOFFSET;
 857                         cfg->ret->inst_basereg = cfg->frame_reg;
 858                         cfg->ret->inst_offset = - offset;
 859                         break;
 860                 default:
 861                         g_assert_not_reached ();
 862                 }
 863                 cfg->ret->dreg = cfg->ret->inst_c0;
 864         }
 865
 866         /* Allocate locals */
 867         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE : TRUE, &locals_stack_size, &locals_stack_align);
 868         if (locals_stack_align) {
 869                 offset = ALIGN_TO (offset, locals_stack_align);
 870         }
 871         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
 872                 if (offsets [i] != -1) {
 873                         MonoInst *inst = cfg->varinfo [i];
 874                         inst->opcode = OP_REGOFFSET;
 875                         inst->inst_basereg = cfg->frame_reg;
 876                         if (cfg->arch.omit_fp)
 877                                 inst->inst_offset = (offset + offsets [i]);
 878                         else
 879                                 inst->inst_offset = - (offset + offsets [i]);
 880                         // printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
 881                 }
 882         }
 883         offset += locals_stack_size;
 884
 885         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
 886                 if (cfg->arch.omit_fp)
 887                         g_assert_not_reached ();
 888                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
 889                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
 890         }
 891
 892         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 893                 inst = cfg->args [i];
 894                 if (inst->opcode != OP_REGVAR) {
 895                         ArgInfo *ainfo = &cinfo->args [i];
 896                         gboolean inreg = TRUE;
 897                         MonoType *arg_type;
 898
 899                         if (sig->hasthis && (i == 0))
 900                                 arg_type = &mono_defaults.object_class->byval_arg;
 901                         else
 902                                 arg_type = sig->params [i - sig->hasthis];
 903
 904                         /* FIXME: VOLATILE is only set if the liveness pass runs */
 905                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 906                                 inreg = FALSE;
 907
 908                         inst->opcode = OP_REGOFFSET;
 909
 910                         switch (ainfo->storage) {
 911                         case ArgInIReg:
 912                                 inst->opcode = OP_REGVAR;
 913                                 inst->dreg = cfg->arch.reg_in0 + ainfo->reg;
 914                                 break;
 915                         case ArgInFloatReg:
 916                         case ArgInFloatRegR4:
 917                                 /*
 918                                  * Since float regs are volatile, we save the arguments to
 919                                  * the stack in the prolog.
 920                                  */
 921                                 inreg = FALSE;
 922                                 break;
 923                         case ArgOnStack:
 924                                 if (cfg->arch.omit_fp)
 925                                         g_assert_not_reached ();
 926                                 inst->opcode = OP_REGOFFSET;
 927                                 inst->inst_basereg = cfg->frame_reg;
 928                                 inst->inst_offset = ARGS_OFFSET + ainfo->offset;
 929                                 break;
 930                         case ArgAggregate:
 931                                 inreg = FALSE;
 932                                 break;
 933                         default:
 934                                 NOT_IMPLEMENTED;
 935                         }
 936
 937                         if (!inreg && (ainfo->storage != ArgOnStack)) {
 938                                 guint32 size = 0;
 939
 940                                 inst->opcode = OP_REGOFFSET;
 941                                 inst->inst_basereg = cfg->frame_reg;
 942                                 /* These arguments are saved to the stack in the prolog */
 943                                 switch (ainfo->storage) {
 944                                 case ArgAggregate:
 945                                         if (ainfo->atype == AggregateSingleHFA)
 946                                                 size = ainfo->nslots * 4;
 947                                         else
 948                                                 size = ainfo->nslots * 8;
 949                                         break;
 950                                 default:
 951                                         size = sizeof (gpointer);
 952                                         break;
 953                                 }
 954
 955                                 offset = ALIGN_TO (offset, sizeof (gpointer));
 956
 957                                 if (cfg->arch.omit_fp) {
 958                                         inst->inst_offset = offset;
 959                                         offset += size;
 960                                 } else {
 961                                         offset += size;
 962                                         inst->inst_offset = - offset;
 963                                 }
 964                         }
 965                 }
 966         }
 967
 968         /*
 969          * FIXME: This doesn't work because some variables are allocated during local
 970          * regalloc.
 971          */
 972         /*
 973         if (cfg->arch.omit_fp && offset == 16)
 974                 offset = 0;
 975         */
 976
 977         cfg->stack_offset = offset;
 978 }
 979
 980 void
 981 mono_arch_create_vars (MonoCompile *cfg)
 982 {
 983         MonoMethodSignature *sig;
 984         CallInfo *cinfo;
 985
 986         sig = mono_method_signature (cfg->method);
 987
 988         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 989
 990         if (cinfo->ret.storage == ArgAggregate)
 991                 cfg->ret_var_is_local = TRUE;
 992         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
 993                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
 994                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
 995                         printf ("vret_addr = ");
 996                         mono_print_ins (cfg->vret_addr);
 997                 }
 998         }
 999 }
1000
1001 static void
1002 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1003 {
1004         MonoInst *arg;
1005
1006         MONO_INST_NEW (cfg, arg, OP_NOP);
1007         arg->sreg1 = tree->dreg;
1008
1009         switch (storage) {
1010         case ArgInIReg:
1011                 arg->opcode = OP_MOVE;
1012                 arg->dreg = mono_alloc_ireg (cfg);
1013
1014                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, FALSE);
1015                 break;
1016         case ArgInFloatReg:
1017                 arg->opcode = OP_FMOVE;
1018                 arg->dreg = mono_alloc_freg (cfg);
1019
1020                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1021                 break;
1022         case ArgInFloatRegR4:
1023                 arg->opcode = OP_FCONV_TO_R4;
1024                 arg->dreg = mono_alloc_freg (cfg);
1025
1026                 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1027                 break;
1028         default:
1029                 g_assert_not_reached ();
1030         }
1031
1032         MONO_ADD_INS (cfg->cbb, arg);
1033 }
1034
1035 static void
1036 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1037 {
1038         MonoMethodSignature *tmp_sig;
1039
1040         /* Emit the signature cookie just before the implicit arguments */
1041         MonoInst *sig_arg;
1042         /* FIXME: Add support for signature tokens to AOT */
1043         cfg->disable_aot = TRUE;
1044
1045         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1046
1047         /*
1048          * mono_ArgIterator_Setup assumes the signature cookie is
1049          * passed first and all the arguments which were before it are
1050          * passed on the stack after the signature. So compensate by
1051          * passing a different signature.
1052          */
1053         tmp_sig = mono_metadata_signature_dup (call->signature);
1054         tmp_sig->param_count -= call->signature->sentinelpos;
1055         tmp_sig->sentinelpos = 0;
1056         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1057
1058         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1059         sig_arg->dreg = mono_alloc_ireg (cfg);
1060         sig_arg->inst_p0 = tmp_sig;
1061         MONO_ADD_INS (cfg->cbb, sig_arg);
1062
1063         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + cinfo->sig_cookie.offset, sig_arg->dreg);
1064 }
1065
1066 void
1067 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1068 {
1069         MonoInst *in;
1070         MonoMethodSignature *sig;
1071         int i, n, stack_size;
1072         CallInfo *cinfo;
1073         ArgInfo *ainfo;
1074
1075         stack_size = 0;
1076
1077         mono_ia64_alloc_stacked_registers (cfg);
1078
1079         sig = call->signature;
1080         n = sig->param_count + sig->hasthis;
1081
1082         cinfo = get_call_info (cfg, cfg->mempool, sig, sig->pinvoke);
1083
1084         if (cinfo->ret.storage == ArgAggregate) {
1085                 MonoInst *vtarg;
1086                 MonoInst *local;
1087
1088                 /*
1089                  * The valuetype is in registers after the call, need to be copied
1090                  * to the stack. Save the address to a local here, so the call
1091                  * instruction can access it.
1092                  */
1093                 local = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1094                 local->flags |= MONO_INST_VOLATILE;
1095                 cfg->arch.ret_var_addr_local = local;
1096
1097                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1098                 vtarg->sreg1 = call->vret_var->dreg;
1099                 vtarg->dreg = local->dreg;
1100                 MONO_ADD_INS (cfg->cbb, vtarg);
1101         }
1102
1103         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1104                 add_outarg_reg (cfg, call, ArgInIReg, cfg->arch.reg_out0 + cinfo->ret.reg, call->vret_var);
1105         }
1106
1107         for (i = 0; i < n; ++i) {
1108                 MonoType *arg_type;
1109
1110                 ainfo = cinfo->args + i;
1111
1112                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1113                         /* Emit the signature cookie just before the implicit arguments */
1114                         emit_sig_cookie (cfg, call, cinfo);
1115                 }
1116
1117                 in = call->args [i];
1118
1119                 if (sig->hasthis && (i == 0))
1120                         arg_type = &mono_defaults.object_class->byval_arg;
1121                 else
1122                         arg_type = sig->params [i - sig->hasthis];
1123
1124                 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(arg_type))) {
1125                         guint32 align;
1126                         guint32 size;
1127
1128                         if (arg_type->type == MONO_TYPE_TYPEDBYREF) {
1129                                 size = sizeof (MonoTypedRef);
1130                                 align = sizeof (gpointer);
1131                         }
1132                         else if (sig->pinvoke)
1133                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1134                         else {
1135                                 /*
1136                                  * Other backends use mono_type_stack_size (), but that
1137                                  * aligns the size to 8, which is larger than the size of
1138                                  * the source, leading to reads of invalid memory if the
1139                                  * source is at the end of address space.
1140                                  */
1141                                 size = mono_class_value_size (in->klass, &align);
1142                         }
1143
1144                         if (size > 0) {
1145                                 MonoInst *arg;
1146
1147                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1148                                 arg->sreg1 = in->dreg;
1149                                 arg->klass = in->klass;
1150                                 arg->backend.size = size;
1151                                 arg->inst_p0 = call;
1152                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1153                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1154
1155                                 MONO_ADD_INS (cfg->cbb, arg);
1156                         }
1157                 }
1158                 else {
1159                         switch (ainfo->storage) {
1160                         case ArgInIReg:
1161                                 add_outarg_reg (cfg, call, ainfo->storage, cfg->arch.reg_out0 + ainfo->reg, in);
1162                                 break;
1163                         case ArgInFloatReg:
1164                         case ArgInFloatRegR4:
1165                                 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1166                                 break;
1167                         case ArgOnStack:
1168                                 if (arg_type->type == MONO_TYPE_R4 && !arg_type->byref)
1169                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1170                                 else if (arg_type->type == MONO_TYPE_R8 && !arg_type->byref)
1171                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1172                                 else
1173                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1174                                 break;
1175                         default:
1176                                 g_assert_not_reached ();
1177                         }
1178                 }
1179         }
1180
1181         /* Handle the case where there are no implicit arguments */
1182         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1183                 emit_sig_cookie (cfg, call, cinfo);
1184         }
1185
1186         call->stack_usage = cinfo->stack_usage;
1187         cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, cinfo->reg_usage);
1188 }
1189
1190 void
1191 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1192 {
1193         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1194         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1195         int size = ins->backend.size;
1196
1197         if (ainfo->storage == ArgAggregate) {
1198                 MonoInst *load, *store;
1199                 int i, slot;
1200
1201                 /*
1202                  * Part of the structure is passed in registers.
1203                  */
1204                 for (i = 0; i < ainfo->nregs; ++i) {
1205                         slot = ainfo->reg + i;
1206
1207                         if (ainfo->atype == AggregateSingleHFA) {
1208                                 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
1209                                 load->inst_basereg = src->dreg;
1210                                 load->inst_offset = i * 4;
1211                                 load->dreg = mono_alloc_freg (cfg);
1212
1213                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1214                         } else if (ainfo->atype == AggregateDoubleHFA) {
1215                                 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
1216                                 load->inst_basereg = src->dreg;
1217                                 load->inst_offset = i * 8;
1218                                 load->dreg = mono_alloc_freg (cfg);
1219
1220                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1221                         } else {
1222                                 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1223                                 load->inst_basereg = src->dreg;
1224                                 load->inst_offset = i * 8;
1225                                 load->dreg = mono_alloc_ireg (cfg);
1226
1227                                 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, cfg->arch.reg_out0 + ainfo->reg + i, FALSE);
1228                         }
1229                         MONO_ADD_INS (cfg->cbb, load);
1230                 }
1231
1232                 /*
1233                  * Part of the structure is passed on the stack.
1234                  */
1235                 for (i = ainfo->nregs; i < ainfo->nslots; ++i) {
1236                         slot = ainfo->reg + i;
1237
1238                         MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1239                         load->inst_basereg = src->dreg;
1240                         load->inst_offset = i * sizeof (gpointer);
1241                         load->dreg = mono_alloc_preg (cfg);
1242                         MONO_ADD_INS (cfg->cbb, load);
1243
1244                         MONO_INST_NEW (cfg, store, OP_STOREI8_MEMBASE_REG);
1245                         store->sreg1 = load->dreg;
1246                         store->inst_destbasereg = IA64_SP;
1247                         store->inst_offset = 16 + ainfo->offset + (slot - 8) * 8;
1248                         MONO_ADD_INS (cfg->cbb, store);
1249                 }
1250         } else {
1251                 mini_emit_memcpy (cfg, IA64_SP, 16 + ainfo->offset, src->dreg, 0, size, 4);
1252         }
1253 }
1254
1255 void
1256 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1257 {
1258         CallInfo *cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
1259
1260         switch (cinfo->ret.storage) {
1261         case ArgInIReg:
1262                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1263                 break;
1264         case ArgInFloatReg:
1265                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1266                 break;
1267         default:
1268                 g_assert_not_reached ();
1269         }
1270 }
1271
1272 void
1273 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1274 {
1275 }
1276
1277 void
1278 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1279 {
1280         MonoInst *ins, *n, *last_ins = NULL;
1281         ins = bb->code;
1282
1283         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1284                 switch (ins->opcode) {
1285                 case OP_MOVE:
1286                 case OP_FMOVE:
1287                         /*
1288                          * Removes:
1289                          *
1290                          * OP_MOVE reg, reg
1291                          */
1292                         if (ins->dreg == ins->sreg1) {
1293                                 MONO_DELETE_INS (bb, ins);
1294                                 continue;
1295                         }
1296                         /*
1297                          * Removes:
1298                          *
1299                          * OP_MOVE sreg, dreg
1300                          * OP_MOVE dreg, sreg
1301                          */
1302                         if (last_ins && last_ins->opcode == OP_MOVE &&
1303                             ins->sreg1 == last_ins->dreg &&
1304                             ins->dreg == last_ins->sreg1) {
1305                                 MONO_DELETE_INS (bb, ins);
1306                                 continue;
1307                         }
1308                         break;
1309                 case OP_MUL_IMM:
1310                 case OP_IMUL_IMM:
1311                         /* remove unnecessary multiplication with 1 */
1312                         if (ins->inst_imm == 1) {
1313                                 if (ins->dreg != ins->sreg1) {
1314                                         ins->opcode = OP_MOVE;
1315                                 } else {
1316                                         MONO_DELETE_INS (bb, ins);
1317                                         continue;
1318                                 }
1319                         }
1320                         break;
1321                 }
1322
1323                 last_ins = ins;
1324                 ins = ins->next;
1325         }
1326         bb->last_ins = last_ins;
1327 }
1328
1329 int cond_to_ia64_cmp [][3] = {
1330         {OP_IA64_CMP_EQ, OP_IA64_CMP4_EQ, OP_IA64_FCMP_EQ},
1331         {OP_IA64_CMP_NE, OP_IA64_CMP4_NE, OP_IA64_FCMP_NE},
1332         {OP_IA64_CMP_LE, OP_IA64_CMP4_LE, OP_IA64_FCMP_LE},
1333         {OP_IA64_CMP_GE, OP_IA64_CMP4_GE, OP_IA64_FCMP_GE},
1334         {OP_IA64_CMP_LT, OP_IA64_CMP4_LT, OP_IA64_FCMP_LT},
1335         {OP_IA64_CMP_GT, OP_IA64_CMP4_GT, OP_IA64_FCMP_GT},
1336         {OP_IA64_CMP_LE_UN, OP_IA64_CMP4_LE_UN, OP_IA64_FCMP_LE_UN},
1337         {OP_IA64_CMP_GE_UN, OP_IA64_CMP4_GE_UN, OP_IA64_FCMP_GE_UN},
1338         {OP_IA64_CMP_LT_UN, OP_IA64_CMP4_LT_UN, OP_IA64_FCMP_LT_UN},
1339         {OP_IA64_CMP_GT_UN, OP_IA64_CMP4_GT_UN, OP_IA64_FCMP_GT_UN}
1340 };
1341
1342 static int
1343 opcode_to_ia64_cmp (int opcode, int cmp_opcode)
1344 {
1345         return cond_to_ia64_cmp [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1346 }
1347
1348 int cond_to_ia64_cmp_imm [][3] = {
1349         {OP_IA64_CMP_EQ_IMM, OP_IA64_CMP4_EQ_IMM, 0},
1350         {OP_IA64_CMP_NE_IMM, OP_IA64_CMP4_NE_IMM, 0},
1351         {OP_IA64_CMP_GE_IMM, OP_IA64_CMP4_GE_IMM, 0},
1352         {OP_IA64_CMP_LE_IMM, OP_IA64_CMP4_LE_IMM, 0},
1353         {OP_IA64_CMP_GT_IMM, OP_IA64_CMP4_GT_IMM, 0},
1354         {OP_IA64_CMP_LT_IMM, OP_IA64_CMP4_LT_IMM, 0},
1355         {OP_IA64_CMP_GE_UN_IMM, OP_IA64_CMP4_GE_UN_IMM, 0},
1356         {OP_IA64_CMP_LE_UN_IMM, OP_IA64_CMP4_LE_UN_IMM, 0},
1357         {OP_IA64_CMP_GT_UN_IMM, OP_IA64_CMP4_GT_UN_IMM, 0},
1358         {OP_IA64_CMP_LT_UN_IMM, OP_IA64_CMP4_LT_UN_IMM, 0},
1359 };
1360
1361 static int
1362 opcode_to_ia64_cmp_imm (int opcode, int cmp_opcode)
1363 {
1364         /* The condition needs to be reversed */
1365         return cond_to_ia64_cmp_imm [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1366 }
1367
1368 #define NEW_INS(cfg,dest,op) do {       \
1369                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1370                 (dest)->opcode = (op);  \
1371         mono_bblock_insert_after_ins (bb, last_ins, (dest)); \
1372         last_ins = (dest); \
1373         } while (0)
1374
1375 /*
1376  * mono_arch_lowering_pass:
1377  *
1378  *  Converts complex opcodes into simpler ones so that each IR instruction
1379  * corresponds to one machine instruction.
1380  */
1381 void
1382 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1383 {
1384         MonoInst *ins, *n, *next, *temp, *temp2, *temp3, *last_ins = NULL;
1385         ins = bb->code;
1386
1387         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1388                 switch (ins->opcode) {
1389                 case OP_STOREI1_MEMBASE_IMM:
1390                 case OP_STOREI2_MEMBASE_IMM:
1391                 case OP_STOREI4_MEMBASE_IMM:
1392                 case OP_STOREI8_MEMBASE_IMM:
1393                 case OP_STORE_MEMBASE_IMM:
1394                         /* There are no store_membase instructions on ia64 */
1395                         if (ins->inst_offset == 0) {
1396                                 temp2 = NULL;
1397                         } else if (ia64_is_imm14 (ins->inst_offset)) {
1398                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1399                                 temp2->sreg1 = ins->inst_destbasereg;
1400                                 temp2->inst_imm = ins->inst_offset;
1401                                 temp2->dreg = mono_alloc_ireg (cfg);
1402                         }
1403                         else {
1404                                 NEW_INS (cfg, temp, OP_I8CONST);
1405                                 temp->inst_c0 = ins->inst_offset;
1406                                 temp->dreg = mono_alloc_ireg (cfg);
1407
1408                                 NEW_INS (cfg, temp2, OP_LADD);
1409                                 temp2->sreg1 = ins->inst_destbasereg;
1410                                 temp2->sreg2 = temp->dreg;
1411                                 temp2->dreg = mono_alloc_ireg (cfg);
1412                         }
1413
1414                         switch (ins->opcode) {
1415                         case OP_STOREI1_MEMBASE_IMM:
1416                                 ins->opcode = OP_STOREI1_MEMBASE_REG;
1417                                 break;
1418                         case OP_STOREI2_MEMBASE_IMM:
1419                                 ins->opcode = OP_STOREI2_MEMBASE_REG;
1420                                 break;
1421                         case OP_STOREI4_MEMBASE_IMM:
1422                                 ins->opcode = OP_STOREI4_MEMBASE_REG;
1423                                 break;
1424                         case OP_STOREI8_MEMBASE_IMM:
1425                         case OP_STORE_MEMBASE_IMM:
1426                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
1427                                 break;
1428                         default:
1429                                 g_assert_not_reached ();
1430                         }
1431
1432                         if (ins->inst_imm == 0)
1433                                 ins->sreg1 = IA64_R0;
1434                         else {
1435                                 NEW_INS (cfg, temp3, OP_I8CONST);
1436                                 temp3->inst_c0 = ins->inst_imm;
1437                                 temp3->dreg = mono_alloc_ireg (cfg);
1438                                 ins->sreg1 = temp3->dreg;
1439                         }
1440
1441                         ins->inst_offset = 0;
1442                         if (temp2)
1443                                 ins->inst_destbasereg = temp2->dreg;
1444                         break;
1445                 case OP_STOREI1_MEMBASE_REG:
1446                 case OP_STOREI2_MEMBASE_REG:
1447                 case OP_STOREI4_MEMBASE_REG:
1448                 case OP_STOREI8_MEMBASE_REG:
1449                 case OP_STORER4_MEMBASE_REG:
1450                 case OP_STORER8_MEMBASE_REG:
1451                 case OP_STORE_MEMBASE_REG:
1452                         /* There are no store_membase instructions on ia64 */
1453                         if (ins->inst_offset == 0) {
1454                                 break;
1455                         }
1456                         else if (ia64_is_imm14 (ins->inst_offset)) {
1457                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1458                                 temp2->sreg1 = ins->inst_destbasereg;
1459                                 temp2->inst_imm = ins->inst_offset;
1460                                 temp2->dreg = mono_alloc_ireg (cfg);
1461                         }
1462                         else {
1463                                 NEW_INS (cfg, temp, OP_I8CONST);
1464                                 temp->inst_c0 = ins->inst_offset;
1465                                 temp->dreg = mono_alloc_ireg (cfg);
1466                                 NEW_INS (cfg, temp2, OP_LADD);
1467                                 temp2->sreg1 = ins->inst_destbasereg;
1468                                 temp2->sreg2 = temp->dreg;
1469                                 temp2->dreg = mono_alloc_ireg (cfg);
1470                         }
1471
1472                         ins->inst_offset = 0;
1473                         ins->inst_destbasereg = temp2->dreg;
1474                         break;
1475                 case OP_LOADI1_MEMBASE:
1476                 case OP_LOADU1_MEMBASE:
1477                 case OP_LOADI2_MEMBASE:
1478                 case OP_LOADU2_MEMBASE:
1479                 case OP_LOADI4_MEMBASE:
1480                 case OP_LOADU4_MEMBASE:
1481                 case OP_LOADI8_MEMBASE:
1482                 case OP_LOAD_MEMBASE:
1483                 case OP_LOADR4_MEMBASE:
1484                 case OP_LOADR8_MEMBASE:
1485                 case OP_ATOMIC_EXCHANGE_I4:
1486                 case OP_ATOMIC_EXCHANGE_I8:
1487                 case OP_ATOMIC_ADD_I4:
1488                 case OP_ATOMIC_ADD_I8:
1489                 case OP_ATOMIC_ADD_IMM_I4:
1490                 case OP_ATOMIC_ADD_IMM_I8:
1491                         /* There are no membase instructions on ia64 */
1492                         if (ins->inst_offset == 0) {
1493                                 break;
1494                         }
1495                         else if (ia64_is_imm14 (ins->inst_offset)) {
1496                                 NEW_INS (cfg, temp2, OP_ADD_IMM);
1497                                 temp2->sreg1 = ins->inst_basereg;
1498                                 temp2->inst_imm = ins->inst_offset;
1499                                 temp2->dreg = mono_alloc_ireg (cfg);
1500                         }
1501                         else {
1502                                 NEW_INS (cfg, temp, OP_I8CONST);
1503                                 temp->inst_c0 = ins->inst_offset;
1504                                 temp->dreg = mono_alloc_ireg (cfg);
1505                                 NEW_INS (cfg, temp2, OP_LADD);
1506                                 temp2->sreg1 = ins->inst_basereg;
1507                                 temp2->sreg2 = temp->dreg;
1508                                 temp2->dreg = mono_alloc_ireg (cfg);
1509                         }
1510
1511                         ins->inst_offset = 0;
1512                         ins->inst_basereg = temp2->dreg;
1513                         break;
1514                 case OP_ADD_IMM:
1515                 case OP_IADD_IMM:
1516                 case OP_LADD_IMM:
1517                 case OP_ISUB_IMM:
1518                 case OP_LSUB_IMM:
1519                 case OP_AND_IMM:
1520                 case OP_IAND_IMM:
1521                 case OP_LAND_IMM:
1522                 case OP_IOR_IMM:
1523                 case OP_LOR_IMM:
1524                 case OP_IXOR_IMM:
1525                 case OP_LXOR_IMM:
1526                 case OP_SHL_IMM:
1527                 case OP_SHR_IMM:
1528                 case OP_ISHL_IMM:
1529                 case OP_LSHL_IMM:
1530                 case OP_ISHR_IMM:
1531                 case OP_LSHR_IMM:
1532                 case OP_ISHR_UN_IMM:
1533                 case OP_LSHR_UN_IMM: {
1534                         gboolean is_imm = FALSE;
1535                         gboolean switched = FALSE;
1536
1537                         if (ins->opcode == OP_AND_IMM && ins->inst_imm == 255) {
1538                                 ins->opcode = OP_ZEXT_I1;
1539                                 break;
1540                         }
1541
1542                         switch (ins->opcode) {
1543                         case OP_ADD_IMM:
1544                         case OP_IADD_IMM:
1545                         case OP_LADD_IMM:
1546                                 is_imm = ia64_is_imm14 (ins->inst_imm);
1547                                 switched = TRUE;
1548                                 break;
1549                         case OP_ISUB_IMM:
1550                         case OP_LSUB_IMM:
1551                                 is_imm = ia64_is_imm14 (- (ins->inst_imm));
1552                                 if (is_imm) {
1553                                         /* A = B - IMM -> A = B + (-IMM) */
1554                                         ins->inst_imm = - ins->inst_imm;
1555                                         ins->opcode = OP_IADD_IMM;
1556                                 }
1557                                 switched = TRUE;
1558                                 break;
1559                         case OP_IAND_IMM:
1560                         case OP_IOR_IMM:
1561                         case OP_IXOR_IMM:
1562                         case OP_AND_IMM:
1563                         case OP_LAND_IMM:
1564                         case OP_LOR_IMM:
1565                         case OP_LXOR_IMM:
1566                                 is_imm = ia64_is_imm8 (ins->inst_imm);
1567                                 switched = TRUE;
1568                                 break;
1569                         case OP_SHL_IMM:
1570                         case OP_SHR_IMM:
1571                         case OP_ISHL_IMM:
1572                         case OP_LSHL_IMM:
1573                         case OP_ISHR_IMM:
1574                         case OP_LSHR_IMM:
1575                         case OP_ISHR_UN_IMM:
1576                         case OP_LSHR_UN_IMM:
1577                                 is_imm = (ins->inst_imm >= 0) && (ins->inst_imm < 64);
1578                                 break;
1579                         default:
1580                                 break;
1581                         }
1582
1583                         if (is_imm) {
1584                                 if (switched)
1585                                         ins->sreg2 = ins->sreg1;
1586                                 break;
1587                         }
1588
1589                         if (mono_op_imm_to_op (ins->opcode) == -1)
1590                                 g_error ("mono_op_imm_to_op failed for %s\n", mono_inst_name (ins->opcode));
1591                         ins->opcode = mono_op_imm_to_op (ins->opcode);
1592
1593                         if (ins->inst_imm == 0)
1594                                 ins->sreg2 = IA64_R0;
1595                         else {
1596                                 NEW_INS (cfg, temp, OP_I8CONST);
1597                                 temp->inst_c0 = ins->inst_imm;
1598                                 temp->dreg = mono_alloc_ireg (cfg);
1599                                 ins->sreg2 = temp->dreg;
1600                         }
1601                         break;
1602                 }
1603                 case OP_COMPARE_IMM:
1604                 case OP_ICOMPARE_IMM:
1605                 case OP_LCOMPARE_IMM: {
1606                         /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1607                         gboolean imm;
1608                         CompRelation cond;
1609
1610                         next = ins->next;
1611
1612                         /* Branch opts can eliminate the branch */
1613                         if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1614                                 NULLIFY_INS (ins);
1615                                 break;
1616                         }
1617
1618                         /*
1619                          * The compare_imm instructions have switched up arguments, and
1620                          * some of them take an imm between -127 and 128.
1621                          */
1622                         next = ins->next;
1623                         cond = mono_opcode_to_cond (next->opcode);
1624                         if ((cond == CMP_LT) || (cond == CMP_GE))
1625                                 imm = ia64_is_imm8 (ins->inst_imm - 1);
1626                         else if ((cond == CMP_LT_UN) || (cond == CMP_GE_UN))
1627                                 imm = ia64_is_imm8 (ins->inst_imm - 1) && (ins->inst_imm > 0);
1628                         else
1629                                 imm = ia64_is_imm8 (ins->inst_imm);
1630
1631                         if (imm) {
1632                                 ins->opcode = opcode_to_ia64_cmp_imm (next->opcode, ins->opcode);
1633                                 ins->sreg2 = ins->sreg1;
1634                         }
1635                         else {
1636                                 ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1637
1638                                 if (ins->inst_imm == 0)
1639                                         ins->sreg2 = IA64_R0;
1640                                 else {
1641                                         NEW_INS (cfg, temp, OP_I8CONST);
1642                                         temp->inst_c0 = ins->inst_imm;
1643                                         temp->dreg = mono_alloc_ireg (cfg);
1644                                         ins->sreg2 = temp->dreg;
1645                                 }
1646                         }
1647
1648                         if (MONO_IS_COND_BRANCH_OP (next)) {
1649                                 next->opcode = OP_IA64_BR_COND;
1650                                 next->inst_target_bb = next->inst_true_bb;
1651                         } else if (MONO_IS_COND_EXC (next)) {
1652                                 next->opcode = OP_IA64_COND_EXC;
1653                         } else if (MONO_IS_SETCC (next)) {
1654                                 next->opcode = OP_IA64_CSET;
1655                         } else {
1656                                 printf ("%s\n", mono_inst_name (next->opcode));
1657                                 NOT_IMPLEMENTED;
1658                         }
1659
1660                         break;
1661                 }
1662                 case OP_COMPARE:
1663                 case OP_ICOMPARE:
1664                 case OP_LCOMPARE:
1665                 case OP_FCOMPARE: {
1666                         /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1667
1668                         next = ins->next;
1669
1670                         /* Branch opts can eliminate the branch */
1671                         if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1672                                 NULLIFY_INS (ins);
1673                                 break;
1674                         }
1675
1676                         ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1677
1678                         if (MONO_IS_COND_BRANCH_OP (next)) {
1679                                 next->opcode = OP_IA64_BR_COND;
1680                                 next->inst_target_bb = next->inst_true_bb;
1681                         } else if (MONO_IS_COND_EXC (next)) {
1682                                 next->opcode = OP_IA64_COND_EXC;
1683                         } else if (MONO_IS_SETCC (next)) {
1684                                 next->opcode = OP_IA64_CSET;
1685                         } else {
1686                                 printf ("%s\n", mono_inst_name (next->opcode));
1687                                 NOT_IMPLEMENTED;
1688                         }
1689
1690                         break;
1691                 }
1692                 case OP_FCEQ:
1693                 case OP_FCGT:
1694                 case OP_FCGT_UN:
1695                 case OP_FCLT:
1696                 case OP_FCLT_UN:
1697                         /* The front end removes the fcompare, so introduce it again */
1698                         NEW_INS (cfg, temp, opcode_to_ia64_cmp (ins->opcode, OP_FCOMPARE));
1699                         temp->sreg1 = ins->sreg1;
1700                         temp->sreg2 = ins->sreg2;
1701
1702                         ins->opcode = OP_IA64_CSET;
1703                         MONO_INST_NULLIFY_SREGS (ins);
1704                         break;
1705                 case OP_MUL_IMM:
1706                 case OP_LMUL_IMM:
1707                 case OP_IMUL_IMM: {
1708                         int i, sum_reg;
1709                         gboolean found = FALSE;
1710                         int shl_op = ins->opcode == OP_IMUL_IMM ? OP_ISHL_IMM : OP_SHL_IMM;
1711
1712                         /* First the easy cases */
1713                         if (ins->inst_imm == 1) {
1714                                 ins->opcode = OP_MOVE;
1715                                 break;
1716                         }
1717                         for (i = 1; i < 64; ++i)
1718                                 if (ins->inst_imm == (((gint64)1) << i)) {
1719                                         ins->opcode = shl_op;
1720                                         ins->inst_imm = i;
1721                                         found = TRUE;
1722                                         break;
1723                                 }
1724
1725                         /* This could be optimized */
1726                         if (!found) {
1727                                 sum_reg = 0;
1728                                 for (i = 0; i < 64; ++i) {
1729                                         if (ins->inst_imm & (((gint64)1) << i)) {
1730                                                 NEW_INS (cfg, temp, shl_op);
1731                                                 temp->dreg = mono_alloc_ireg (cfg);
1732                                                 temp->sreg1 = ins->sreg1;
1733                                                 temp->inst_imm = i;
1734
1735                                                 if (sum_reg == 0)
1736                                                         sum_reg = temp->dreg;
1737                                                 else {
1738                                                         NEW_INS (cfg, temp2, OP_LADD);
1739                                                         temp2->dreg = mono_alloc_ireg (cfg);
1740                                                         temp2->sreg1 = sum_reg;
1741                                                         temp2->sreg2 = temp->dreg;
1742                                                         sum_reg = temp2->dreg;
1743                                                 }
1744                                         }
1745                                 }
1746                                 ins->opcode = OP_MOVE;
1747                                 ins->sreg1 = sum_reg;
1748                         }
1749                         break;
1750                 }
1751                 case OP_LCONV_TO_OVF_U4:
1752                         NEW_INS (cfg, temp, OP_IA64_CMP4_LT);
1753                         temp->sreg1 = ins->sreg1;
1754                         temp->sreg2 = IA64_R0;
1755
1756                         NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1757                         temp->inst_p1 = (char*)"OverflowException";
1758
1759                         ins->opcode = OP_MOVE;
1760                         break;
1761                 case OP_LCONV_TO_OVF_I4_UN:
1762                         NEW_INS (cfg, temp, OP_ICONST);
1763                         temp->inst_c0 = 0x7fffffff;
1764                         temp->dreg = mono_alloc_ireg (cfg);
1765
1766                         NEW_INS (cfg, temp2, OP_IA64_CMP4_GT_UN);
1767                         temp2->sreg1 = ins->sreg1;
1768                         temp2->sreg2 = temp->dreg;
1769
1770                         NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1771                         temp->inst_p1 = (char*)"OverflowException";
1772
1773                         ins->opcode = OP_MOVE;
1774                         break;
1775                 case OP_FCONV_TO_I4:
1776                 case OP_FCONV_TO_I2:
1777                 case OP_FCONV_TO_U2:
1778                 case OP_FCONV_TO_I1:
1779                 case OP_FCONV_TO_U1:
1780                         NEW_INS (cfg, temp, OP_FCONV_TO_I8);
1781                         temp->sreg1 = ins->sreg1;
1782                         temp->dreg = ins->dreg;
1783
1784                         switch (ins->opcode) {
1785                         case OP_FCONV_TO_I4:
1786                                 ins->opcode = OP_SEXT_I4;
1787                                 break;
1788                         case OP_FCONV_TO_I2:
1789                                 ins->opcode = OP_SEXT_I2;
1790                                 break;
1791                         case OP_FCONV_TO_U2:
1792                                 ins->opcode = OP_ZEXT_I4;
1793                                 break;
1794                         case OP_FCONV_TO_I1:
1795                                 ins->opcode = OP_SEXT_I1;
1796                                 break;
1797                         case OP_FCONV_TO_U1:
1798                                 ins->opcode = OP_ZEXT_I1;
1799                                 break;
1800                         default:
1801                                 g_assert_not_reached ();
1802                         }
1803                         ins->sreg1 = ins->dreg;
1804                         break;
1805                 default:
1806                         break;
1807                 }
1808                 last_ins = ins;
1809                 ins = ins->next;
1810         }
1811         bb->last_ins = last_ins;
1812
1813         bb->max_vreg = cfg->next_vreg;
1814 }
1815
1816 /*
1817  * emit_load_volatile_arguments:
1818  *
1819  *  Load volatile arguments from the stack to the original input registers.
1820  * Required before a tail call.
1821  */
1822 static Ia64CodegenState
1823 emit_load_volatile_arguments (MonoCompile *cfg, Ia64CodegenState code)
1824 {
1825         MonoMethod *method = cfg->method;
1826         MonoMethodSignature *sig;
1827         MonoInst *ins;
1828         CallInfo *cinfo;
1829         guint32 i;
1830
1831         /* FIXME: Generate intermediate code instead */
1832
1833         sig = mono_method_signature (method);
1834
1835         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
1836
1837         /* This is the opposite of the code in emit_prolog */
1838         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1839                 ArgInfo *ainfo = cinfo->args + i;
1840                 gint32 stack_offset;
1841                 MonoType *arg_type;
1842
1843                 ins = cfg->args [i];
1844
1845                 if (sig->hasthis && (i == 0))
1846                         arg_type = &mono_defaults.object_class->byval_arg;
1847                 else
1848                         arg_type = sig->params [i - sig->hasthis];
1849
1850                 arg_type = mini_get_underlying_type (arg_type);
1851
1852                 stack_offset = ainfo->offset + ARGS_OFFSET;
1853
1854                 /* Save volatile arguments to the stack */
1855                 if (ins->opcode != OP_REGVAR) {
1856                         switch (ainfo->storage) {
1857                         case ArgInIReg:
1858                         case ArgInFloatReg:
1859                                 /* FIXME: big offsets */
1860                                 g_assert (ins->opcode == OP_REGOFFSET);
1861                                 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
1862                                 if (arg_type->byref)
1863                                         ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1864                                 else {
1865                                         switch (arg_type->type) {
1866                                         case MONO_TYPE_R4:
1867                                                 ia64_ldfs (code, ainfo->reg, GP_SCRATCH_REG);
1868                                                 break;
1869                                         case MONO_TYPE_R8:
1870                                                 ia64_ldfd (code, ainfo->reg, GP_SCRATCH_REG);
1871                                                 break;
1872                                         default:
1873                                                 ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1874                                                 break;
1875                                         }
1876                                 }
1877                                 break;
1878                         case ArgOnStack:
1879                                 break;
1880                         default:
1881                                 NOT_IMPLEMENTED;
1882                         }
1883                 }
1884
1885                 if (ins->opcode == OP_REGVAR) {
1886                         /* Argument allocated to (non-volatile) register */
1887                         switch (ainfo->storage) {
1888                         case ArgInIReg:
1889                                 if (ins->dreg != cfg->arch.reg_in0 + ainfo->reg)
1890                                         ia64_mov (code, cfg->arch.reg_in0 + ainfo->reg, ins->dreg);
1891                                 break;
1892                         case ArgOnStack:
1893                                 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
1894                                 ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
1895                                 break;
1896                         default:
1897                                 NOT_IMPLEMENTED;
1898                         }
1899                 }
1900         }
1901
1902         return code;
1903 }
1904
1905 static Ia64CodegenState
1906 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, Ia64CodegenState code)
1907 {
1908         CallInfo *cinfo;
1909         int i;
1910
1911         /* Move return value to the target register */
1912         switch (ins->opcode) {
1913         case OP_VOIDCALL:
1914         case OP_VOIDCALL_REG:
1915         case OP_VOIDCALL_MEMBASE:
1916                 break;
1917         case OP_CALL:
1918         case OP_CALL_REG:
1919         case OP_CALL_MEMBASE:
1920         case OP_LCALL:
1921         case OP_LCALL_REG:
1922         case OP_LCALL_MEMBASE:
1923                 g_assert (ins->dreg == IA64_R8);
1924                 break;
1925         case OP_FCALL:
1926         case OP_FCALL_REG:
1927         case OP_FCALL_MEMBASE:
1928                 g_assert (ins->dreg == 8);
1929                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4)
1930                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
1931                 break;
1932         case OP_VCALL:
1933         case OP_VCALL_REG:
1934         case OP_VCALL_MEMBASE:
1935         case OP_VCALL2:
1936         case OP_VCALL2_REG:
1937         case OP_VCALL2_MEMBASE: {
1938                 ArgStorage storage;
1939
1940                 cinfo = get_call_info (cfg, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
1941                 storage = cinfo->ret.storage;
1942
1943                 if (storage == ArgAggregate) {
1944                         MonoInst *local = (MonoInst*)cfg->arch.ret_var_addr_local;
1945
1946                         /* Load address of stack space allocated for the return value */
1947                         ia64_movl (code, GP_SCRATCH_REG, local->inst_offset);
1948                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, local->inst_basereg);
1949                         ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
1950
1951                         for (i = 0; i < cinfo->ret.nregs; ++i) {
1952                                 switch (cinfo->ret.atype) {
1953                                 case AggregateNormal:
1954                                         ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1955                                         break;
1956                                 case AggregateSingleHFA:
1957                                         ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 4, 0);
1958                                         break;
1959                                 case AggregateDoubleHFA:
1960                                         ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1961                                         break;
1962                                 default:
1963                                         g_assert_not_reached ();
1964                                 }
1965                         }
1966                 }
1967                 break;
1968         }
1969         default:
1970                 g_assert_not_reached ();
1971         }
1972
1973         return code;
1974 }
1975
1976 #define add_patch_info(cfg,code,patch_type,data) do { \
1977         mono_add_patch_info (cfg, code.buf + code.nins - cfg->native_code, patch_type, data); \
1978 } while (0)
1979
1980 #define emit_cond_system_exception(cfg,code,exc_name,predicate) do { \
1981         MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1982     if (tins == NULL) \
1983         add_patch_info (cfg, code, MONO_PATCH_INFO_EXC, exc_name); \
1984     else \
1985                 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, tins->inst_true_bb); \
1986         ia64_br_cond_pred (code, (predicate), 0); \
1987 } while (0)
1988
1989 static Ia64CodegenState
1990 emit_call (MonoCompile *cfg, Ia64CodegenState code, guint32 patch_type, gconstpointer data)
1991 {
1992         add_patch_info (cfg, code, patch_type, data);
1993
1994         if ((patch_type == MONO_PATCH_INFO_ABS) || (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD)) {
1995                 /* Indirect call */
1996                 /* mono_arch_patch_callsite will patch this */
1997                 ia64_movl (code, GP_SCRATCH_REG, 0);
1998                 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
1999                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2000                 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
2001                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2002         }
2003         else {
2004                 /* Can't use a direct call since the displacement might be too small */
2005                 /* mono_arch_patch_callsite will patch this */
2006                 ia64_movl (code, GP_SCRATCH_REG, 0);
2007                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2008                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2009         }
2010
2011         return code;
2012 }
2013
2014 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2015
2016 void
2017 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2018 {
2019         MonoInst *ins;
2020         MonoCallInst *call;
2021         guint offset;
2022         Ia64CodegenState code;
2023         guint8 *code_start = cfg->native_code + cfg->code_len;
2024         MonoInst *last_ins = NULL;
2025         guint last_offset = 0;
2026         int max_len, cpos;
2027
2028         if (cfg->opt & MONO_OPT_LOOP) {
2029                 /* FIXME: */
2030         }
2031
2032         if (cfg->verbose_level > 2)
2033                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2034
2035         cpos = bb->max_offset;
2036
2037         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2038                 NOT_IMPLEMENTED;
2039         }
2040
2041         offset = code_start - cfg->native_code;
2042
2043         ia64_codegen_init (code, code_start);
2044
2045 #if 0
2046         if (strstr (cfg->method->name, "conv_ovf_i1") && (bb->block_num == 2))
2047                 break_count ();
2048 #endif
2049
2050         MONO_BB_FOR_EACH_INS (bb, ins) {
2051                 offset = code.buf - cfg->native_code;
2052
2053                 max_len = ((int)(((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN])) + 128;
2054
2055                 while (offset + max_len + 16 > cfg->code_size) {
2056                         ia64_codegen_close (code);
2057
2058                         offset = code.buf - cfg->native_code;
2059
2060                         cfg->code_size *= 2;
2061                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2062                         code_start = cfg->native_code + offset;
2063                         cfg->stat_code_reallocs++;
2064
2065                         ia64_codegen_init (code, code_start);
2066                 }
2067
2068                 mono_debug_record_line_number (cfg, ins, offset);
2069
2070                 switch (ins->opcode) {
2071                 case OP_ICONST:
2072                 case OP_I8CONST:
2073                         if (ia64_is_imm14 (ins->inst_c0))
2074                                 ia64_adds_imm (code, ins->dreg, ins->inst_c0, IA64_R0);
2075                         else
2076                                 ia64_movl (code, ins->dreg, ins->inst_c0);
2077                         break;
2078                 case OP_JUMP_TABLE:
2079                         add_patch_info (cfg, code, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2080                         ia64_movl (code, ins->dreg, 0);
2081                         break;
2082                 case OP_MOVE:
2083                         ia64_mov (code, ins->dreg, ins->sreg1);
2084                         break;
2085                 case OP_BR:
2086                 case OP_IA64_BR_COND: {
2087                         int pred = 0;
2088                         if (ins->opcode == OP_IA64_BR_COND)
2089                                 pred = 6;
2090                         if (ins->inst_target_bb->native_offset) {
2091                                 guint8 *pos = code.buf + code.nins;
2092
2093                                 ia64_br_cond_pred (code, pred, 0);
2094                                 ia64_begin_bundle (code);
2095                                 ia64_patch (pos, cfg->native_code + ins->inst_target_bb->native_offset);
2096                         } else {
2097                                 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2098                                 ia64_br_cond_pred (code, pred, 0);
2099                         }
2100                         break;
2101                 }
2102                 case OP_LABEL:
2103                         ia64_begin_bundle (code);
2104                         ins->inst_c0 = code.buf - cfg->native_code;
2105                         break;
2106                 case OP_NOP:
2107                 case OP_RELAXED_NOP:
2108                 case OP_DUMMY_USE:
2109                 case OP_DUMMY_STORE:
2110                 case OP_NOT_REACHED:
2111                 case OP_NOT_NULL:
2112                         break;
2113                 case OP_BR_REG:
2114                         ia64_mov_to_br (code, IA64_B6, ins->sreg1);
2115                         ia64_br_cond_reg (code, IA64_B6);
2116                         break;
2117                 case OP_IADD:
2118                 case OP_LADD:
2119                         ia64_add (code, ins->dreg, ins->sreg1, ins->sreg2);
2120                         break;
2121                 case OP_ISUB:
2122                 case OP_LSUB:
2123                         ia64_sub (code, ins->dreg, ins->sreg1, ins->sreg2);
2124                         break;
2125                 case OP_IAND:
2126                 case OP_LAND:
2127                         ia64_and (code, ins->dreg, ins->sreg1, ins->sreg2);
2128                         break;
2129                 case OP_IOR:
2130                 case OP_LOR:
2131                         ia64_or (code, ins->dreg, ins->sreg1, ins->sreg2);
2132                         break;
2133                 case OP_IXOR:
2134                 case OP_LXOR:
2135                         ia64_xor (code, ins->dreg, ins->sreg1, ins->sreg2);
2136                         break;
2137                 case OP_INEG:
2138                 case OP_LNEG:
2139                         ia64_sub (code, ins->dreg, IA64_R0, ins->sreg1);
2140                         break;
2141                 case OP_INOT:
2142                 case OP_LNOT:
2143                         ia64_andcm_imm (code, ins->dreg, -1, ins->sreg1);
2144                         break;
2145                 case OP_ISHL:
2146                 case OP_LSHL:
2147                         ia64_shl (code, ins->dreg, ins->sreg1, ins->sreg2);
2148                         break;
2149                 case OP_ISHR:
2150                         ia64_sxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2151                         ia64_shr (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2152                         break;
2153                 case OP_LSHR:
2154                         ia64_shr (code, ins->dreg, ins->sreg1, ins->sreg2);
2155                         break;
2156                 case OP_ISHR_UN:
2157                         ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2158                         ia64_shr_u (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2159                         break;
2160                 case OP_LSHR_UN:
2161                         ia64_shr_u (code, ins->dreg, ins->sreg1, ins->sreg2);
2162                         break;
2163                 case OP_IADDCC:
2164                         /* p6 and p7 is set if there is signed/unsigned overflow */
2165
2166                         /* Set p8-p9 == (sreg2 > 0) */
2167                         ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2168
2169                         ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2170
2171                         /* (sreg2 > 0) && (res < ins->sreg1) => signed overflow */
2172                         ia64_cmp4_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2173                         /* (sreg2 <= 0) && (res > ins->sreg1) => signed overflow */
2174                         ia64_cmp4_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2175
2176                         /* res <u sreg1 => unsigned overflow */
2177                         ia64_cmp4_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2178
2179                         /* FIXME: Predicate this since this is a side effect */
2180                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2181                         break;
2182                 case OP_ISUBCC:
2183                         /* p6 and p7 is set if there is signed/unsigned overflow */
2184
2185                         /* Set p8-p9 == (sreg2 > 0) */
2186                         ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2187
2188                         ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2189
2190                         /* (sreg2 > 0) && (res > ins->sreg1) => signed overflow */
2191                         ia64_cmp4_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2192                         /* (sreg2 <= 0) && (res < ins->sreg1) => signed overflow */
2193                         ia64_cmp4_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2194
2195                         /* sreg1 <u sreg2 => unsigned overflow */
2196                         ia64_cmp4_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2197
2198                         /* FIXME: Predicate this since this is a side effect */
2199                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2200                         break;
2201                 case OP_ADDCC:
2202                         /* Same as OP_IADDCC */
2203                         ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2204
2205                         ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2206
2207                         ia64_cmp_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2208                         ia64_cmp_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2209
2210                         ia64_cmp_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2211
2212                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2213                         break;
2214                 case OP_SUBCC:
2215                         /* Same as OP_ISUBCC */
2216
2217                         ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2218
2219                         ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2220
2221                         ia64_cmp_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2222                         ia64_cmp_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2223
2224                         ia64_cmp_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2225
2226                         ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2227                         break;
2228                 case OP_ADD_IMM:
2229                 case OP_IADD_IMM:
2230                 case OP_LADD_IMM:
2231                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2232                         break;
2233                 case OP_IAND_IMM:
2234                 case OP_AND_IMM:
2235                 case OP_LAND_IMM:
2236                         ia64_and_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2237                         break;
2238                 case OP_IOR_IMM:
2239                 case OP_LOR_IMM:
2240                         ia64_or_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2241                         break;
2242                 case OP_IXOR_IMM:
2243                 case OP_LXOR_IMM:
2244                         ia64_xor_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2245                         break;
2246                 case OP_SHL_IMM:
2247                 case OP_ISHL_IMM:
2248                 case OP_LSHL_IMM:
2249                         ia64_shl_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2250                         break;
2251                 case OP_SHR_IMM:
2252                 case OP_LSHR_IMM:
2253                         ia64_shr_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2254                         break;
2255                 case OP_ISHR_IMM:
2256                         g_assert (ins->inst_imm <= 64);
2257                         ia64_extr (code, ins->dreg, ins->sreg1, ins->inst_imm, 32 - ins->inst_imm);
2258                         break;
2259                 case OP_ISHR_UN_IMM:
2260                         ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2261                         ia64_shr_u_imm (code, ins->dreg, GP_SCRATCH_REG, ins->inst_imm);
2262                         break;
2263                 case OP_LSHR_UN_IMM:
2264                         ia64_shr_u_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2265                         break;
2266                 case OP_LMUL:
2267                         /* Based on gcc code */
2268                         ia64_setf_sig (code, FP_SCRATCH_REG, ins->sreg1);
2269                         ia64_setf_sig (code, FP_SCRATCH_REG2, ins->sreg2);
2270                         ia64_xmpy_l (code, FP_SCRATCH_REG, FP_SCRATCH_REG, FP_SCRATCH_REG2);
2271                         ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2272                         break;
2273
2274                 case OP_STOREI1_MEMBASE_REG:
2275                         ia64_st1_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2276                         break;
2277                 case OP_STOREI2_MEMBASE_REG:
2278                         ia64_st2_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2279                         break;
2280                 case OP_STOREI4_MEMBASE_REG:
2281                         ia64_st4_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2282                         break;
2283                 case OP_STOREI8_MEMBASE_REG:
2284                 case OP_STORE_MEMBASE_REG:
2285                         if (ins->inst_offset != 0) {
2286                                 /* This is generated by local regalloc */
2287                                 if (ia64_is_imm14 (ins->inst_offset)) {
2288                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2289                                 } else {
2290                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2291                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2292                                 }
2293                                 ins->inst_destbasereg = GP_SCRATCH_REG;
2294                         }
2295                         ia64_st8_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2296                         break;
2297
2298                 case OP_IA64_STOREI1_MEMBASE_INC_REG:
2299                         ia64_st1_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 1, 0);
2300                         break;
2301                 case OP_IA64_STOREI2_MEMBASE_INC_REG:
2302                         ia64_st2_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 2, 0);
2303                         break;
2304                 case OP_IA64_STOREI4_MEMBASE_INC_REG:
2305                         ia64_st4_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 4, 0);
2306                         break;
2307                 case OP_IA64_STOREI8_MEMBASE_INC_REG:
2308                         ia64_st8_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 8, 0);
2309                         break;
2310
2311                 case OP_LOADU1_MEMBASE:
2312                         ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2313                         break;
2314                 case OP_LOADU2_MEMBASE:
2315                         ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2316                         break;
2317                 case OP_LOADU4_MEMBASE:
2318                         ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2319                         break;
2320                 case OP_LOADI1_MEMBASE:
2321                         ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2322                         ia64_sxt1 (code, ins->dreg, ins->dreg);
2323                         break;
2324                 case OP_LOADI2_MEMBASE:
2325                         ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2326                         ia64_sxt2 (code, ins->dreg, ins->dreg);
2327                         break;
2328                 case OP_LOADI4_MEMBASE:
2329                         ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2330                         ia64_sxt4 (code, ins->dreg, ins->dreg);
2331                         break;
2332                 case OP_LOAD_MEMBASE:
2333                 case OP_LOADI8_MEMBASE:
2334                         if (ins->inst_offset != 0) {
2335                                 /* This is generated by local regalloc */
2336                                 if (ia64_is_imm14 (ins->inst_offset)) {
2337                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2338                                 } else {
2339                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2340                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2341                                 }
2342                                 ins->inst_basereg = GP_SCRATCH_REG;
2343                         }
2344                         ia64_ld8 (code, ins->dreg, ins->inst_basereg);
2345                         break;
2346
2347                 case OP_IA64_LOADU1_MEMBASE_INC:
2348                         ia64_ld1_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 1, 0);
2349                         break;
2350                 case OP_IA64_LOADU2_MEMBASE_INC:
2351                         ia64_ld2_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 2, 0);
2352                         break;
2353                 case OP_IA64_LOADU4_MEMBASE_INC:
2354                         ia64_ld4_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 4, 0);
2355                         break;
2356                 case OP_IA64_LOADI8_MEMBASE_INC:
2357                         ia64_ld8_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 8, 0);
2358                         break;
2359
2360                 case OP_SEXT_I1:
2361                         ia64_sxt1 (code, ins->dreg, ins->sreg1);
2362                         break;
2363                 case OP_SEXT_I2:
2364                         ia64_sxt2 (code, ins->dreg, ins->sreg1);
2365                         break;
2366                 case OP_SEXT_I4:
2367                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2368                         break;
2369                 case OP_ZEXT_I1:
2370                         ia64_zxt1 (code, ins->dreg, ins->sreg1);
2371                         break;
2372                 case OP_ZEXT_I2:
2373                         ia64_zxt2 (code, ins->dreg, ins->sreg1);
2374                         break;
2375                 case OP_ZEXT_I4:
2376                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2377                         break;
2378
2379                         /* Compare opcodes */
2380                 case OP_IA64_CMP4_EQ:
2381                         ia64_cmp4_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2382                         break;
2383                 case OP_IA64_CMP4_NE:
2384                         ia64_cmp4_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2385                         break;
2386                 case OP_IA64_CMP4_LE:
2387                         ia64_cmp4_le (code, 6, 7, ins->sreg1, ins->sreg2);
2388                         break;
2389                 case OP_IA64_CMP4_LT:
2390                         ia64_cmp4_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2391                         break;
2392                 case OP_IA64_CMP4_GE:
2393                         ia64_cmp4_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2394                         break;
2395                 case OP_IA64_CMP4_GT:
2396                         ia64_cmp4_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2397                         break;
2398                 case OP_IA64_CMP4_LT_UN:
2399                         ia64_cmp4_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2400                         break;
2401                 case OP_IA64_CMP4_LE_UN:
2402                         ia64_cmp4_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2403                         break;
2404                 case OP_IA64_CMP4_GT_UN:
2405                         ia64_cmp4_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2406                         break;
2407                 case OP_IA64_CMP4_GE_UN:
2408                         ia64_cmp4_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2409                         break;
2410                 case OP_IA64_CMP_EQ:
2411                         ia64_cmp_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2412                         break;
2413                 case OP_IA64_CMP_NE:
2414                         ia64_cmp_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2415                         break;
2416                 case OP_IA64_CMP_LE:
2417                         ia64_cmp_le (code, 6, 7, ins->sreg1, ins->sreg2);
2418                         break;
2419                 case OP_IA64_CMP_LT:
2420                         ia64_cmp_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2421                         break;
2422                 case OP_IA64_CMP_GE:
2423                         ia64_cmp_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2424                         break;
2425                 case OP_IA64_CMP_GT:
2426                         ia64_cmp_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2427                         break;
2428                 case OP_IA64_CMP_GT_UN:
2429                         ia64_cmp_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2430                         break;
2431                 case OP_IA64_CMP_LT_UN:
2432                         ia64_cmp_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2433                         break;
2434                 case OP_IA64_CMP_GE_UN:
2435                         ia64_cmp_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2436                         break;
2437                 case OP_IA64_CMP_LE_UN:
2438                         ia64_cmp_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2439                         break;
2440                 case OP_IA64_CMP4_EQ_IMM:
2441                         ia64_cmp4_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2442                         break;
2443                 case OP_IA64_CMP4_NE_IMM:
2444                         ia64_cmp4_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2445                         break;
2446                 case OP_IA64_CMP4_LE_IMM:
2447                         ia64_cmp4_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2448                         break;
2449                 case OP_IA64_CMP4_LT_IMM:
2450                         ia64_cmp4_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2451                         break;
2452                 case OP_IA64_CMP4_GE_IMM:
2453                         ia64_cmp4_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2454                         break;
2455                 case OP_IA64_CMP4_GT_IMM:
2456                         ia64_cmp4_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2457                         break;
2458                 case OP_IA64_CMP4_LT_UN_IMM:
2459                         ia64_cmp4_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2460                         break;
2461                 case OP_IA64_CMP4_LE_UN_IMM:
2462                         ia64_cmp4_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2463                         break;
2464                 case OP_IA64_CMP4_GT_UN_IMM:
2465                         ia64_cmp4_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2466                         break;
2467                 case OP_IA64_CMP4_GE_UN_IMM:
2468                         ia64_cmp4_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2469                         break;
2470                 case OP_IA64_CMP_EQ_IMM:
2471                         ia64_cmp_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2472                         break;
2473                 case OP_IA64_CMP_NE_IMM:
2474                         ia64_cmp_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2475                         break;
2476                 case OP_IA64_CMP_LE_IMM:
2477                         ia64_cmp_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2478                         break;
2479                 case OP_IA64_CMP_LT_IMM:
2480                         ia64_cmp_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2481                         break;
2482                 case OP_IA64_CMP_GE_IMM:
2483                         ia64_cmp_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2484                         break;
2485                 case OP_IA64_CMP_GT_IMM:
2486                         ia64_cmp_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2487                         break;
2488                 case OP_IA64_CMP_GT_UN_IMM:
2489                         ia64_cmp_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2490                         break;
2491                 case OP_IA64_CMP_LT_UN_IMM:
2492                         ia64_cmp_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2493                         break;
2494                 case OP_IA64_CMP_GE_UN_IMM:
2495                         ia64_cmp_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2496                         break;
2497                 case OP_IA64_CMP_LE_UN_IMM:
2498                         ia64_cmp_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2499                         break;
2500                 case OP_IA64_FCMP_EQ:
2501                         ia64_fcmp_eq_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2502                         break;
2503                 case OP_IA64_FCMP_NE:
2504                         ia64_fcmp_ne_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2505                         break;
2506                 case OP_IA64_FCMP_LT:
2507                         ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2508                         break;
2509                 case OP_IA64_FCMP_GT:
2510                         ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2511                         break;
2512                 case OP_IA64_FCMP_LE:
2513                         ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2514                         break;
2515                 case OP_IA64_FCMP_GE:
2516                         ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2517                         break;
2518                 case OP_IA64_FCMP_GT_UN:
2519                         ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2520                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2521                         break;
2522                 case OP_IA64_FCMP_LT_UN:
2523                         ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2524                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2525                         break;
2526                 case OP_IA64_FCMP_GE_UN:
2527                         ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2528                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2529                         break;
2530                 case OP_IA64_FCMP_LE_UN:
2531                         ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2532                         ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2533                         break;
2534
2535                 case OP_COND_EXC_IOV:
2536                 case OP_COND_EXC_OV:
2537                         emit_cond_system_exception (cfg, code, "OverflowException", 6);
2538                         break;
2539                 case OP_COND_EXC_IC:
2540                 case OP_COND_EXC_C:
2541                         emit_cond_system_exception (cfg, code, "OverflowException", 7);
2542                         break;
2543                 case OP_IA64_COND_EXC:
2544                         emit_cond_system_exception (cfg, code, ins->inst_p1, 6);
2545                         break;
2546                 case OP_IA64_CSET:
2547                         ia64_mov_pred (code, 7, ins->dreg, IA64_R0);
2548                         ia64_no_stop (code);
2549                         ia64_add1_pred (code, 6, ins->dreg, IA64_R0, IA64_R0);
2550                         break;
2551                 case OP_ICONV_TO_I1:
2552                 case OP_LCONV_TO_I1:
2553                         /* FIXME: Is this needed ? */
2554                         ia64_sxt1 (code, ins->dreg, ins->sreg1);
2555                         break;
2556                 case OP_ICONV_TO_I2:
2557                 case OP_LCONV_TO_I2:
2558                         /* FIXME: Is this needed ? */
2559                         ia64_sxt2 (code, ins->dreg, ins->sreg1);
2560                         break;
2561                 case OP_LCONV_TO_I4:
2562                         /* FIXME: Is this needed ? */
2563                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2564                         break;
2565                 case OP_ICONV_TO_U1:
2566                 case OP_LCONV_TO_U1:
2567                         /* FIXME: Is this needed */
2568                         ia64_zxt1 (code, ins->dreg, ins->sreg1);
2569                         break;
2570                 case OP_ICONV_TO_U2:
2571                 case OP_LCONV_TO_U2:
2572                         /* FIXME: Is this needed */
2573                         ia64_zxt2 (code, ins->dreg, ins->sreg1);
2574                         break;
2575                 case OP_LCONV_TO_U4:
2576                         /* FIXME: Is this needed */
2577                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2578                         break;
2579                 case OP_ICONV_TO_I8:
2580                 case OP_ICONV_TO_I:
2581                 case OP_LCONV_TO_I8:
2582                 case OP_LCONV_TO_I:
2583                         ia64_sxt4 (code, ins->dreg, ins->sreg1);
2584                         break;
2585                 case OP_LCONV_TO_U8:
2586                 case OP_LCONV_TO_U:
2587                         ia64_zxt4 (code, ins->dreg, ins->sreg1);
2588                         break;
2589
2590                         /*
2591                          * FLOAT OPCODES
2592                          */
2593                 case OP_R8CONST: {
2594                         double d = *(double *)ins->inst_p0;
2595
2596                         if ((d == 0.0) && (mono_signbit (d) == 0))
2597                                 ia64_fmov (code, ins->dreg, 0);
2598                         else if (d == 1.0)
2599                                 ia64_fmov (code, ins->dreg, 1);
2600                         else {
2601                                 add_patch_info (cfg, code, MONO_PATCH_INFO_R8, ins->inst_p0);
2602                                 ia64_movl (code, GP_SCRATCH_REG, 0);
2603                                 ia64_ldfd (code, ins->dreg, GP_SCRATCH_REG);
2604                         }
2605                         break;
2606                 }
2607                 case OP_R4CONST: {
2608                         float f = *(float *)ins->inst_p0;
2609
2610                         if ((f == 0.0) && (mono_signbit (f) == 0))
2611                                 ia64_fmov (code, ins->dreg, 0);
2612                         else if (f == 1.0)
2613                                 ia64_fmov (code, ins->dreg, 1);
2614                         else {
2615                                 add_patch_info (cfg, code, MONO_PATCH_INFO_R4, ins->inst_p0);
2616                                 ia64_movl (code, GP_SCRATCH_REG, 0);
2617                                 ia64_ldfs (code, ins->dreg, GP_SCRATCH_REG);
2618                         }
2619                         break;
2620                 }
2621                 case OP_FMOVE:
2622                         ia64_fmov (code, ins->dreg, ins->sreg1);
2623                         break;
2624                 case OP_STORER8_MEMBASE_REG:
2625                         if (ins->inst_offset != 0) {
2626                                 /* This is generated by local regalloc */
2627                                 if (ia64_is_imm14 (ins->inst_offset)) {
2628                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2629                                 } else {
2630                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2631                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2632                                 }
2633                                 ins->inst_destbasereg = GP_SCRATCH_REG;
2634                         }
2635                         ia64_stfd_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2636                         break;
2637                 case OP_STORER4_MEMBASE_REG:
2638                         ia64_fnorm_s_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2639                         ia64_stfs_hint (code, ins->inst_destbasereg, FP_SCRATCH_REG, 0);
2640                         break;
2641                 case OP_LOADR8_MEMBASE:
2642                         if (ins->inst_offset != 0) {
2643                                 /* This is generated by local regalloc */
2644                                 if (ia64_is_imm14 (ins->inst_offset)) {
2645                                         ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2646                                 } else {
2647                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2648                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2649                                 }
2650                                 ins->inst_basereg = GP_SCRATCH_REG;
2651                         }
2652                         ia64_ldfd (code, ins->dreg, ins->inst_basereg);
2653                         break;
2654                 case OP_LOADR4_MEMBASE:
2655                         ia64_ldfs (code, ins->dreg, ins->inst_basereg);
2656                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2657                         break;
2658                 case OP_ICONV_TO_R4:
2659                 case OP_LCONV_TO_R4:
2660                         ia64_setf_sig (code, ins->dreg, ins->sreg1);
2661                         ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2662                         ia64_fnorm_s_sf (code, ins->dreg, ins->dreg, 0);
2663                         break;
2664                 case OP_ICONV_TO_R8:
2665                 case OP_LCONV_TO_R8:
2666                         ia64_setf_sig (code, ins->dreg, ins->sreg1);
2667                         ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2668                         ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2669                         break;
2670                 case OP_FCONV_TO_R4:
2671                         ia64_fnorm_s_sf (code, ins->dreg, ins->sreg1, 0);
2672                         break;
2673                 case OP_FCONV_TO_I8:
2674                 case OP_FCONV_TO_I:
2675                         ia64_fcvt_fx_trunc_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2676                         ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2677                         break;
2678                 case OP_FADD:
2679                         ia64_fma_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2680                         break;
2681                 case OP_FSUB:
2682                         ia64_fms_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2683                         break;
2684                 case OP_FMUL:
2685                         ia64_fma_d_sf (code, ins->dreg, ins->sreg1, ins->sreg2, 0, 0);
2686                         break;
2687                 case OP_FNEG:
2688                         ia64_fmerge_ns (code, ins->dreg, ins->sreg1, ins->sreg1);
2689                         break;
2690                 case OP_CKFINITE:
2691                         /* Quiet NaN */
2692                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x080);
2693                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2694                         /* Signaling NaN */
2695                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x040);
2696                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2697                         /* Positive infinity */
2698                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x021);
2699                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2700                         /* Negative infinity */
2701                         ia64_fclass_m (code, 6, 7, ins->sreg1, 0x022);
2702                         emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2703                         break;
2704
2705                 /* Calls */
2706                 case OP_CHECK_THIS:
2707                         /* ensure ins->sreg1 is not NULL */
2708                         /* Can't use ld8 as this could be a vtype address */
2709                         ia64_ld1 (code, GP_SCRATCH_REG, ins->sreg1);
2710                         break;
2711                 case OP_ARGLIST:
2712                         ia64_adds_imm (code, GP_SCRATCH_REG, cfg->sig_cookie, cfg->frame_reg);
2713                         ia64_st8 (code, ins->sreg1, GP_SCRATCH_REG);
2714                         break;
2715                 case OP_FCALL:
2716                 case OP_LCALL:
2717                 case OP_VCALL:
2718                 case OP_VCALL2:
2719                 case OP_VOIDCALL:
2720                 case OP_CALL:
2721                         call = (MonoCallInst*)ins;
2722
2723                         if (ins->flags & MONO_INST_HAS_METHOD)
2724                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2725                         else
2726                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2727
2728                         code = emit_move_return_value (cfg, ins, code);
2729                         break;
2730
2731                 case OP_CALL_REG:
2732                 case OP_FCALL_REG:
2733                 case OP_LCALL_REG:
2734                 case OP_VCALL_REG:
2735                 case OP_VCALL2_REG:
2736                 case OP_VOIDCALL_REG: {
2737                         MonoCallInst *call = (MonoCallInst*)ins;
2738                         CallInfo *cinfo;
2739                         int out_reg;
2740
2741                         /*
2742                          * mono_arch_get_this_arg_from_call () needs to find the this argument in a global
2743                          * register.
2744                          */
2745                         cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2746                         out_reg = cfg->arch.reg_out0;
2747                         ia64_mov (code, IA64_R10, out_reg);
2748
2749                         /* Indirect call */
2750                         ia64_mov (code, IA64_R8, ins->sreg1);
2751                         ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, IA64_R8, 8);
2752                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2753                         ia64_ld8 (code, IA64_GP, IA64_R8);
2754                         ia64_br_call_reg (code, IA64_B0, IA64_B6);
2755
2756                         code = emit_move_return_value (cfg, ins, code);
2757                         break;
2758                 }
2759                 case OP_FCALL_MEMBASE:
2760                 case OP_LCALL_MEMBASE:
2761                 case OP_VCALL_MEMBASE:
2762                 case OP_VCALL2_MEMBASE:
2763                 case OP_VOIDCALL_MEMBASE:
2764                 case OP_CALL_MEMBASE: {
2765                         MonoCallInst *call = (MonoCallInst*)ins;
2766                         CallInfo *cinfo;
2767                         int out_reg;
2768
2769                         ia64_mov (code, IA64_R11, ins->sreg1);
2770                         if (ia64_is_imm14 (ins->inst_offset))
2771                                 ia64_adds_imm (code, IA64_R8, ins->inst_offset, ins->sreg1);
2772                         else {
2773                                 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2774                                 ia64_add (code, IA64_R8, GP_SCRATCH_REG, ins->sreg1);
2775                         }
2776
2777                         if (call->method && ins->inst_offset < 0) {
2778                                 /*
2779                                  * This is a possible IMT call so save the IMT method in a global
2780                                  * register where mono_arch_find_imt_method () and its friends can
2781                                  * access it.
2782                                  */
2783                                 ia64_movl (code, IA64_R9, call->method);
2784                         }
2785
2786                         /*
2787                          * mono_arch_find_this_arg () needs to find the this argument in a global
2788                          * register.
2789                          */
2790                         cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2791                         out_reg = cfg->arch.reg_out0;
2792                         ia64_mov (code, IA64_R10, out_reg);
2793
2794                         ia64_ld8 (code, GP_SCRATCH_REG, IA64_R8);
2795
2796                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2797
2798                         ia64_br_call_reg (code, IA64_B0, IA64_B6);
2799
2800                         code = emit_move_return_value (cfg, ins, code);
2801                         break;
2802                 }
2803                 case OP_JMP: {
2804                         /*
2805                          * Keep in sync with the code in emit_epilog.
2806                          */
2807
2808                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2809                                 NOT_IMPLEMENTED;
2810
2811                         g_assert (!cfg->method->save_lmf);
2812
2813                         /* Load arguments into their original registers */
2814                         code = emit_load_volatile_arguments (cfg, code);
2815
2816                         if (cfg->arch.stack_alloc_size) {
2817                                 if (cfg->arch.omit_fp) {
2818                                         if (ia64_is_imm14 (cfg->arch.stack_alloc_size))
2819                                                 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
2820                                         else {
2821                                                 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
2822                                                 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
2823                                         }
2824                                 }
2825                                 else
2826                                         ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
2827                         }
2828                         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
2829                         ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
2830
2831                         add_patch_info (cfg, code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2832                         ia64_movl (code, GP_SCRATCH_REG, 0);
2833                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2834                         ia64_br_cond_reg (code, IA64_B6);
2835
2836                         break;
2837                 }
2838                 case OP_BREAK:
2839                         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, mono_break);
2840                         break;
2841
2842                 case OP_LOCALLOC: {
2843                         gint32 abi_offset;
2844
2845                         /* FIXME: Sigaltstack support */
2846
2847                         /* keep alignment */
2848                         ia64_adds_imm (code, GP_SCRATCH_REG, MONO_ARCH_LOCALLOC_ALIGNMENT - 1, ins->sreg1);
2849                         ia64_movl (code, GP_SCRATCH_REG2, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
2850                         ia64_and (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2851
2852                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2853
2854                         ia64_mov (code, ins->dreg, IA64_SP);
2855
2856                         /* An area at sp is reserved by the ABI for parameter passing */
2857                         abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_LOCALLOC_ALIGNMENT);
2858                         if (ia64_is_adds_imm (abi_offset))
2859                                 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2860                         else {
2861                                 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2862                                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2863                         }
2864
2865                         if (ins->flags & MONO_INST_INIT) {
2866                                 /* Upper limit */
2867                                 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2868
2869                                 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2870
2871                                 /* Init loop */
2872                                 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2873                                 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2874                                 ia64_br_cond_pred (code, 8, -2);
2875
2876                                 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2877
2878                                 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2879                         }
2880
2881                         break;
2882                 }
2883                 case OP_LOCALLOC_IMM: {
2884                         gint32 abi_offset;
2885
2886                         /* FIXME: Sigaltstack support */
2887
2888                         gssize size = ins->inst_imm;
2889                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
2890
2891                         if (ia64_is_adds_imm (size))
2892                                 ia64_adds_imm (code, GP_SCRATCH_REG, size, IA64_R0);
2893                         else
2894                                 ia64_movl (code, GP_SCRATCH_REG, size);
2895
2896                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2897                         ia64_mov (code, ins->dreg, IA64_SP);
2898
2899                         /* An area at sp is reserved by the ABI for parameter passing */
2900                         abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_FRAME_ALIGNMENT);
2901                         if (ia64_is_adds_imm (abi_offset))
2902                                 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2903                         else {
2904                                 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2905                                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2906                         }
2907
2908                         if (ins->flags & MONO_INST_INIT) {
2909                                 /* Upper limit */
2910                                 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2911
2912                                 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2913
2914                                 /* Init loop */
2915                                 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2916                                 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2917                                 ia64_br_cond_pred (code, 8, -2);
2918
2919                                 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2920
2921                                 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2922                         }
2923
2924                         break;
2925                 }
2926                 case OP_TLS_GET:
2927                         ia64_adds_imm (code, ins->dreg, ins->inst_offset, IA64_TP);
2928                         ia64_ld8 (code, ins->dreg, ins->dreg);
2929                         break;
2930
2931                         /* Synchronization */
2932                 case OP_MEMORY_BARRIER:
2933                         ia64_mf (code);
2934                         break;
2935                 case OP_ATOMIC_ADD_IMM_I4:
2936                         g_assert (ins->inst_offset == 0);
2937                         ia64_fetchadd4_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2938                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2939                         break;
2940                 case OP_ATOMIC_ADD_IMM_I8:
2941                         g_assert (ins->inst_offset == 0);
2942                         ia64_fetchadd8_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2943                         ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2944                         break;
2945                 case OP_ATOMIC_EXCHANGE_I4:
2946                         ia64_xchg4_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2947                         ia64_sxt4 (code, ins->dreg, ins->dreg);
2948                         break;
2949                 case OP_ATOMIC_EXCHANGE_I8:
2950                         ia64_xchg8_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2951                         break;
2952                 case OP_ATOMIC_ADD_I4: {
2953                         guint8 *label, *buf;
2954
2955                         /* From libatomic_ops */
2956                         ia64_mf (code);
2957
2958                         ia64_begin_bundle (code);
2959                         label = code.buf + code.nins;
2960                         ia64_ld4_acq (code, GP_SCRATCH_REG, ins->sreg1);
2961                         ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2962                         ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2963                         ia64_cmpxchg4_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2964                         ia64_cmp4_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2965                         buf = code.buf + code.nins;
2966                         ia64_br_cond_pred (code, 7, 0);
2967                         ia64_begin_bundle (code);
2968                         ia64_patch (buf, label);
2969                         ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2970                         break;
2971                 }
2972                 case OP_ATOMIC_ADD_I8: {
2973                         guint8 *label, *buf;
2974
2975                         /* From libatomic_ops */
2976                         ia64_mf (code);
2977
2978                         ia64_begin_bundle (code);
2979                         label = code.buf + code.nins;
2980                         ia64_ld8_acq (code, GP_SCRATCH_REG, ins->sreg1);
2981                         ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2982                         ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2983                         ia64_cmpxchg8_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2984                         ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2985                         buf = code.buf + code.nins;
2986                         ia64_br_cond_pred (code, 7, 0);
2987                         ia64_begin_bundle (code);
2988                         ia64_patch (buf, label);
2989                         ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2990                         break;
2991                 }
2992
2993                         /* Exception handling */
2994                 case OP_CALL_HANDLER:
2995                         /*
2996                          * Using a call instruction would mess up the register stack, so
2997                          * save the return address to a register and use a
2998                          * branch.
2999                          */
3000                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3001                         ia64_mov (code, IA64_R15, IA64_R0);
3002                         ia64_mov_from_ip (code, GP_SCRATCH_REG);
3003                         /* Add the length of OP_CALL_HANDLER */
3004                         ia64_adds_imm (code, GP_SCRATCH_REG, 5 * 16, GP_SCRATCH_REG);
3005                         add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3006                         ia64_movl (code, GP_SCRATCH_REG2, 0);
3007                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
3008                         ia64_br_cond_reg (code, IA64_B6);
3009                         // FIXME:
3010                         //mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3011                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3012                         break;
3013                 case OP_START_HANDLER: {
3014                         /*
3015                          * We receive the return address in GP_SCRATCH_REG.
3016                          */
3017                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3018
3019                         /*
3020                          * R15 determines our caller. It is used since it is writable using
3021                          * libunwind.
3022                          * R15 == 0 means we are called by OP_CALL_HANDLER or via resume_context ()
3023                          * R15 != 0 means we are called by call_filter ().
3024                          */
3025                         ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3026                         ia64_cmp_eq (code, 6, 7, IA64_R15, IA64_R0);
3027
3028                         ia64_br_cond_pred (code, 6, 6);
3029
3030                         /*
3031                          * Called by call_filter:
3032                          * Allocate a new stack frame, and set the fp register from the
3033                          * value passed in by the caller.
3034                          * We allocate a similar frame as is done by the prolog, so
3035                          * if an exception is thrown while executing the filter, the
3036                          * unwinder can unwind through the filter frame using the unwind
3037                          * info for the prolog.
3038                          */
3039                         ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3040                         ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3041                         ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3042                         ia64_mov (code, cfg->frame_reg, IA64_R15);
3043                         /* Signal to endfilter that we are called by call_filter */
3044                         ia64_mov (code, GP_SCRATCH_REG, IA64_R0);
3045
3046                         /* Branch target: */
3047                         if (ia64_is_imm14 (spvar->inst_offset))
3048                                 ia64_adds_imm (code, GP_SCRATCH_REG2, spvar->inst_offset, cfg->frame_reg);
3049                         else {
3050                                 ia64_movl (code, GP_SCRATCH_REG2, spvar->inst_offset);
3051                                 ia64_add (code, GP_SCRATCH_REG2, cfg->frame_reg, GP_SCRATCH_REG2);
3052                         }
3053
3054                         /* Save the return address */
3055                         ia64_st8_hint (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 0);
3056                         ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3057
3058                         break;
3059                 }
3060                 case OP_ENDFINALLY:
3061                 case OP_ENDFILTER: {
3062                         /* FIXME: Return the value in ENDFILTER */
3063                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3064
3065                         /* Load the return address */
3066                         if (ia64_is_imm14 (spvar->inst_offset)) {
3067                                 ia64_adds_imm (code, GP_SCRATCH_REG, spvar->inst_offset, cfg->frame_reg);
3068                         } else {
3069                                 ia64_movl (code, GP_SCRATCH_REG, spvar->inst_offset);
3070                                 ia64_add (code, GP_SCRATCH_REG, cfg->frame_reg, GP_SCRATCH_REG);
3071                         }
3072                         ia64_ld8_hint (code, GP_SCRATCH_REG, GP_SCRATCH_REG, 0);
3073
3074                         /* Test caller */
3075                         ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, IA64_R0);
3076                         ia64_br_cond_pred (code, 7, 4);
3077
3078                         /* Called by call_filter */
3079                         /* Pop frame */
3080                         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
3081                         ia64_mov_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
3082                         ia64_br_ret_reg (code, IA64_B0);
3083
3084                         /* Called by CALL_HANDLER */
3085                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
3086                         ia64_br_cond_reg (code, IA64_B6);
3087                         break;
3088                 }
3089                 case OP_THROW:
3090                         ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3091                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3092                                                           (gpointer)"mono_arch_throw_exception");
3093
3094                         /*
3095                          * This might be the last instruction in the method, so add a dummy
3096                          * instruction so the unwinder will work.
3097                          */
3098                         ia64_break_i (code, 0);
3099                         break;
3100                 case OP_RETHROW:
3101                         ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3102                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3103                                                           (gpointer)"mono_arch_rethrow_exception");
3104
3105                         ia64_break_i (code, 0);
3106                         break;
3107                 case OP_GC_SAFE_POINT:
3108                         break;
3109
3110                 default:
3111                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3112                         g_assert_not_reached ();
3113                 }
3114
3115                 if ((code.buf - cfg->native_code - offset) > max_len) {
3116                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3117                                    mono_inst_name (ins->opcode), max_len, code.buf - cfg->native_code - offset);
3118                         g_assert_not_reached ();
3119                 }
3120
3121                 cpos += max_len;
3122
3123                 last_ins = ins;
3124                 last_offset = offset;
3125         }
3126
3127         ia64_codegen_close (code);
3128
3129         cfg->code_len = code.buf - cfg->native_code;
3130 }
3131
3132 void
3133 mono_arch_register_lowlevel_calls (void)
3134 {
3135 }
3136
3137 static Ia64InsType ins_types_in_template [32][3] = {
3138         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3139         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3140         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3141         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3142         {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3143         {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3144         {0, 0, 0},
3145         {0, 0, 0},
3146         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3147         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3148         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3149         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3150         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3151         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3152         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3153         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3154         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3155         {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3156         {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3157         {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3158         {0, 0, 0},
3159         {0, 0, 0},
3160         {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3161         {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3162         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3163         {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3164         {0, 0, 0},
3165         {0, 0, 0},
3166         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3167         {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3168         {0, 0, 0},
3169         {0, 0, 0}
3170 };
3171
3172 static gboolean stops_in_template [32][3] = {
3173         { FALSE, FALSE, FALSE },
3174         { FALSE, FALSE, TRUE },
3175         { FALSE, TRUE, FALSE },
3176         { FALSE, TRUE, TRUE },
3177         { FALSE, FALSE, FALSE },
3178         { FALSE, FALSE, TRUE },
3179         { FALSE, FALSE, FALSE },
3180         { FALSE, FALSE, FALSE },
3181
3182         { FALSE, FALSE, FALSE },
3183         { FALSE, FALSE, TRUE },
3184         { TRUE, FALSE, FALSE },
3185         { TRUE, FALSE, TRUE },
3186         { FALSE, FALSE, FALSE },
3187         { FALSE, FALSE, TRUE },
3188         { FALSE, FALSE, FALSE },
3189         { FALSE, FALSE, TRUE },
3190
3191         { FALSE, FALSE, FALSE },
3192         { FALSE, FALSE, TRUE },
3193         { FALSE, FALSE, FALSE },
3194         { FALSE, FALSE, TRUE },
3195         { FALSE, FALSE, FALSE },
3196         { FALSE, FALSE, FALSE },
3197         { FALSE, FALSE, FALSE },
3198         { FALSE, FALSE, TRUE },
3199
3200         { FALSE, FALSE, FALSE },
3201         { FALSE, FALSE, TRUE },
3202         { FALSE, FALSE, FALSE },
3203         { FALSE, FALSE, FALSE },
3204         { FALSE, FALSE, FALSE },
3205         { FALSE, FALSE, TRUE },
3206         { FALSE, FALSE, FALSE },
3207         { FALSE, FALSE, FALSE }
3208 };
3209
3210 static int last_stop_in_template [32] = {
3211         -1, 2, 1, 2, -1, 2, -1, -1,
3212         -1, 2, 0, 2, -1, 2, -1, 2,
3213         -1, 2, -1, 2, -1, -1, -1, 2,
3214         -1, 2, -1, -1, -1, 2, -1, -1
3215 };
3216
3217 static guint64 nops_for_ins_types [6] = {
3218         IA64_NOP_I,
3219         IA64_NOP_I,
3220         IA64_NOP_M,
3221         IA64_NOP_F,
3222         IA64_NOP_B,
3223         IA64_NOP_X
3224 };
3225
3226 #define ITYPE_MATCH(itype1, itype2) (((itype1) == (itype2)) || (((itype2) == IA64_INS_TYPE_A) && (((itype1) == IA64_INS_TYPE_I) || ((itype1) == IA64_INS_TYPE_M))))
3227
3228 /*
3229  * Debugging support
3230  */
3231
3232 #if 0
3233 #define DEBUG_INS_SCHED(a) do { a; } while (0)
3234 #else
3235 #define DEBUG_INS_SCHED(a)
3236 #endif
3237
3238 static void
3239 ia64_analyze_deps (Ia64CodegenState *code, int *deps_start, int *stops)
3240 {
3241         int i, pos, ins_index, current_deps_start, current_ins_start, reg;
3242         guint8 *deps = code->dep_info;
3243         gboolean need_stop, no_stop;
3244
3245         for (i = 0; i < code->nins; ++i)
3246                 stops [i] = FALSE;
3247
3248         ins_index = 0;
3249         current_deps_start = 0;
3250         current_ins_start = 0;
3251         deps_start [ins_index] = current_ins_start;
3252         pos = 0;
3253         no_stop = FALSE;
3254         DEBUG_INS_SCHED (printf ("BEGIN.\n"));
3255         while (pos < code->dep_info_pos) {
3256                 need_stop = FALSE;
3257                 switch (deps [pos]) {
3258                 case IA64_END_OF_INS:
3259                         ins_index ++;
3260                         current_ins_start = pos + 2;
3261                         deps_start [ins_index] = current_ins_start;
3262                         no_stop = FALSE;
3263                         DEBUG_INS_SCHED (printf ("(%d) END INS.\n", ins_index - 1));
3264                         break;
3265                 case IA64_NONE:
3266                         break;
3267                 case IA64_READ_GR:
3268                         reg = deps [pos + 1];
3269
3270                         DEBUG_INS_SCHED (printf ("READ GR: %d\n", reg));
3271                         for (i = current_deps_start; i < current_ins_start; i += 2)
3272                                 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3273                                         need_stop = TRUE;
3274                         break;
3275                 case IA64_WRITE_GR:
3276                         reg = code->dep_info [pos + 1];
3277
3278                         DEBUG_INS_SCHED (printf ("WRITE GR: %d\n", reg));
3279                         for (i = current_deps_start; i < current_ins_start; i += 2)
3280                                 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3281                                         need_stop = TRUE;
3282                         break;
3283                 case IA64_READ_PR:
3284                         reg = deps [pos + 1];
3285
3286                         DEBUG_INS_SCHED (printf ("READ PR: %d\n", reg));
3287                         for (i = current_deps_start; i < current_ins_start; i += 2)
3288                                 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3289                                         need_stop = TRUE;
3290                         break;
3291                 case IA64_READ_PR_BRANCH:
3292                         reg = deps [pos + 1];
3293
3294                         /* Writes to prs by non-float instructions are visible to branches */
3295                         DEBUG_INS_SCHED (printf ("READ PR BRANCH: %d\n", reg));
3296                         for (i = current_deps_start; i < current_ins_start; i += 2)
3297                                 if (deps [i] == IA64_WRITE_PR_FLOAT && deps [i + 1] == reg)
3298                                         need_stop = TRUE;
3299                         break;
3300                 case IA64_WRITE_PR:
3301                         reg = code->dep_info [pos + 1];
3302
3303                         DEBUG_INS_SCHED (printf ("WRITE PR: %d\n", reg));
3304                         for (i = current_deps_start; i < current_ins_start; i += 2)
3305                                 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3306                                         need_stop = TRUE;
3307                         break;
3308                 case IA64_WRITE_PR_FLOAT:
3309                         reg = code->dep_info [pos + 1];
3310
3311                         DEBUG_INS_SCHED (printf ("WRITE PR FP: %d\n", reg));
3312                         for (i = current_deps_start; i < current_ins_start; i += 2)
3313                                 if (((deps [i] == IA64_WRITE_GR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3314                                         need_stop = TRUE;
3315                         break;
3316                 case IA64_READ_BR:
3317                         reg = deps [pos + 1];
3318
3319                         DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3320                         for (i = current_deps_start; i < current_ins_start; i += 2)
3321                                 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3322                                         need_stop = TRUE;
3323                         break;
3324                 case IA64_WRITE_BR:
3325                         reg = code->dep_info [pos + 1];
3326
3327                         DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3328                         for (i = current_deps_start; i < current_ins_start; i += 2)
3329                                 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3330                                         need_stop = TRUE;
3331                         break;
3332                 case IA64_READ_BR_BRANCH:
3333                         reg = deps [pos + 1];
3334
3335                         /* Writes to brs are visible to branches */
3336                         DEBUG_INS_SCHED (printf ("READ BR BRACH: %d\n", reg));
3337                         break;
3338                 case IA64_READ_FR:
3339                         reg = deps [pos + 1];
3340
3341                         DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3342                         for (i = current_deps_start; i < current_ins_start; i += 2)
3343                                 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3344                                         need_stop = TRUE;
3345                         break;
3346                 case IA64_WRITE_FR:
3347                         reg = code->dep_info [pos + 1];
3348
3349                         DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3350                         for (i = current_deps_start; i < current_ins_start; i += 2)
3351                                 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3352                                         need_stop = TRUE;
3353                         break;
3354                 case IA64_READ_AR:
3355                         reg = deps [pos + 1];
3356
3357                         DEBUG_INS_SCHED (printf ("READ AR: %d\n", reg));
3358                         for (i = current_deps_start; i < current_ins_start; i += 2)
3359                                 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3360                                         need_stop = TRUE;
3361                         break;
3362                 case IA64_WRITE_AR:
3363                         reg = code->dep_info [pos + 1];
3364
3365                         DEBUG_INS_SCHED (printf ("WRITE AR: %d\n", reg));
3366                         for (i = current_deps_start; i < current_ins_start; i += 2)
3367                                 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3368                                         need_stop = TRUE;
3369                         break;
3370                 case IA64_NO_STOP:
3371                         /*
3372                          * Explicitly indicate that a stop is not required. Useful for
3373                          * example when two predicated instructions with negated predicates
3374                          * write the same registers.
3375                          */
3376                         no_stop = TRUE;
3377                         break;
3378                 default:
3379                         g_assert_not_reached ();
3380                 }
3381                 pos += 2;
3382
3383                 if (need_stop && !no_stop) {
3384                         g_assert (ins_index > 0);
3385                         stops [ins_index - 1] = 1;
3386
3387                         DEBUG_INS_SCHED (printf ("STOP\n"));
3388                         current_deps_start = current_ins_start;
3389
3390                         /* Skip remaining deps for this instruction */
3391                         while (deps [pos] != IA64_END_OF_INS)
3392                                 pos += 2;
3393                 }
3394         }
3395
3396         if (code->nins > 0) {
3397                 /* No dependency info for the last instruction */
3398                 stops [code->nins - 1] = 1;
3399         }
3400
3401         deps_start [code->nins] = code->dep_info_pos;
3402 }
3403
3404 static void
3405 ia64_real_emit_bundle (Ia64CodegenState *code, int *deps_start, int *stops, int n, guint64 template, guint64 ins1, guint64 ins2, guint64 ins3, guint8 nops)
3406 {
3407         int stop_pos, i, deps_to_shift, dep_shift;
3408
3409         g_assert (n <= code->nins);
3410
3411         // if (n > 1) printf ("FOUND: %ld.\n", template);
3412
3413         ia64_emit_bundle_template (code, template, ins1, ins2, ins3);
3414
3415         stop_pos = last_stop_in_template [template] + 1;
3416         if (stop_pos > n)
3417                 stop_pos = n;
3418
3419         /* Compute the number of 'real' instructions before the stop */
3420         deps_to_shift = stop_pos;
3421         if (stop_pos >= 3 && (nops & (1 << 2)))
3422                 deps_to_shift --;
3423         if (stop_pos >= 2 && (nops & (1 << 1)))
3424                 deps_to_shift --;
3425         if (stop_pos >= 1 && (nops & (1 << 0)))
3426                 deps_to_shift --;
3427
3428         /*
3429          * We have to keep some dependencies whose instructions have been shifted
3430          * out of the buffer. So nullify the end_of_ins markers in the dependency
3431          * array.
3432          */
3433         for (i = deps_start [deps_to_shift]; i < deps_start [n]; i += 2)
3434                 if (code->dep_info [i] == IA64_END_OF_INS)
3435                         code->dep_info [i] = IA64_NONE;
3436
3437         g_assert (deps_start [deps_to_shift] <= code->dep_info_pos);
3438         memcpy (code->dep_info, &code->dep_info [deps_start [deps_to_shift]], code->dep_info_pos - deps_start [deps_to_shift]);
3439         code->dep_info_pos = code->dep_info_pos - deps_start [deps_to_shift];
3440
3441         dep_shift = deps_start [deps_to_shift];
3442         for (i = 0; i < code->nins + 1 - n; ++i)
3443                 deps_start [i] = deps_start [n + i] - dep_shift;
3444
3445         /* Determine the exact positions of instructions with unwind ops */
3446         if (code->unw_op_count) {
3447                 int ins_pos [16];
3448                 int curr_ins, curr_ins_pos;
3449
3450                 curr_ins = 0;
3451                 curr_ins_pos = ((code->buf - code->region_start - 16) / 16) * 3;
3452                 for (i = 0; i < 3; ++i) {
3453                         if (! (nops & (1 << i))) {
3454                                 ins_pos [curr_ins] = curr_ins_pos + i;
3455                                 curr_ins ++;
3456                         }
3457                 }
3458
3459                 for (i = code->unw_op_pos; i < code->unw_op_count; ++i) {
3460                         if (code->unw_ops_pos [i] < n) {
3461                                 code->unw_ops [i].when = ins_pos [code->unw_ops_pos [i]];
3462                                 //printf ("UNW-OP: %d -> %d\n", code->unw_ops_pos [i], code->unw_ops [i].when);
3463                         }
3464                 }
3465                 if (code->unw_op_pos < code->unw_op_count)
3466                         code->unw_op_pos += n;
3467         }
3468
3469         if (n == code->nins) {
3470                 code->template = 0;
3471                 code->nins = 0;
3472         }
3473         else {
3474                 memcpy (&code->instructions [0], &code->instructions [n], (code->nins - n) * sizeof (guint64));
3475                 memcpy (&code->itypes [0], &code->itypes [n], (code->nins - n) * sizeof (int));
3476                 memcpy (&stops [0], &stops [n], (code->nins - n) * sizeof (int));
3477                 code->nins -= n;
3478         }
3479 }
3480
3481 void
3482 ia64_emit_bundle (Ia64CodegenState *code, gboolean flush)
3483 {
3484         int i, ins_type, template, nins_to_emit;
3485         int deps_start [16];
3486         int stops [16];
3487         gboolean found;
3488
3489         /*
3490          * We implement a simple scheduler which tries to put three instructions
3491          * per bundle, then two, then one.
3492          */
3493         ia64_analyze_deps (code, deps_start, stops);
3494
3495         if ((code->nins >= 3) && !code->one_ins_per_bundle) {
3496                 /* Find a suitable template */
3497                 for (template = 0; template < 32; ++template) {
3498                         if (stops_in_template [template][0] != stops [0] ||
3499                                 stops_in_template [template][1] != stops [1] ||
3500                                 stops_in_template [template][2] != stops [2])
3501                                 continue;
3502
3503                         found = TRUE;
3504                         for (i = 0; i < 3; ++i) {
3505                                 ins_type = ins_types_in_template [template][i];
3506                                 switch (code->itypes [i]) {
3507                                 case IA64_INS_TYPE_A:
3508                                         found &= (ins_type == IA64_INS_TYPE_I) || (ins_type == IA64_INS_TYPE_M);
3509                                         break;
3510                                 default:
3511                                         found &= (ins_type == code->itypes [i]);
3512                                         break;
3513                                 }
3514                         }
3515
3516                         if (found)
3517                                 found = debug_ins_sched ();
3518
3519                         if (found) {
3520                                 ia64_real_emit_bundle (code, deps_start, stops, 3, template, code->instructions [0], code->instructions [1], code->instructions [2], 0);
3521                                 break;
3522                         }
3523                 }
3524         }
3525
3526         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3527                 /* Wait for more instructions */
3528                 return;
3529
3530         /* If it didn't work out, try putting two instructions into one bundle */
3531         if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3532                 /* Try a nop at the end */
3533                 for (template = 0; template < 32; ++template) {
3534                         if (stops_in_template [template][0] != stops [0] ||
3535                                 ((stops_in_template [template][1] != stops [1]) &&
3536                                  (stops_in_template [template][2] != stops [1])))
3537
3538                                 continue;
3539
3540                         if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3541                                 !ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [1]))
3542                                 continue;
3543
3544                         if (!debug_ins_sched ())
3545                                 continue;
3546
3547                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], code->instructions [1], nops_for_ins_types [ins_types_in_template [template][2]], 1 << 2);
3548                         break;
3549                 }
3550         }
3551
3552         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3553                 /* Wait for more instructions */
3554                 return;
3555
3556         if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3557                 /* Try a nop in the middle */
3558                 for (template = 0; template < 32; ++template) {
3559                         if (((stops_in_template [template][0] != stops [0]) &&
3560                                  (stops_in_template [template][1] != stops [0])) ||
3561                                 stops_in_template [template][2] != stops [1])
3562                                 continue;
3563
3564                         if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3565                                 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3566                                 continue;
3567
3568                         if (!debug_ins_sched ())
3569                                 continue;
3570
3571                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], nops_for_ins_types [ins_types_in_template [template][1]], code->instructions [1], 1 << 1);
3572                         break;
3573                 }
3574         }
3575
3576         if ((code->nins >= 2) && flush && !code->one_ins_per_bundle) {
3577                 /* Try a nop at the beginning */
3578                 for (template = 0; template < 32; ++template) {
3579                         if ((stops_in_template [template][1] != stops [0]) ||
3580                                 (stops_in_template [template][2] != stops [1]))
3581                                 continue;
3582
3583                         if (!ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [0]) ||
3584                                 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3585                                 continue;
3586
3587                         if (!debug_ins_sched ())
3588                                 continue;
3589
3590                         ia64_real_emit_bundle (code, deps_start, stops, 2, template, nops_for_ins_types [ins_types_in_template [template][0]], code->instructions [0], code->instructions [1], 1 << 0);
3591                         break;
3592                 }
3593         }
3594
3595         if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3596                 /* Wait for more instructions */
3597                 return;
3598
3599         if (flush)
3600                 nins_to_emit = code->nins;
3601         else
3602                 nins_to_emit = 1;
3603
3604         while (nins_to_emit > 0) {
3605                 if (!debug_ins_sched ())
3606                         stops [0] = 1;
3607                 switch (code->itypes [0]) {
3608                 case IA64_INS_TYPE_A:
3609                         if (stops [0])
3610                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3611                         else
3612                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3613                         break;
3614                 case IA64_INS_TYPE_I:
3615                         if (stops [0])
3616                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3617                         else
3618                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3619                         break;
3620                 case IA64_INS_TYPE_M:
3621                         if (stops [0])
3622                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3623                         else
3624                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3625                         break;
3626                 case IA64_INS_TYPE_B:
3627                         if (stops [0])
3628                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIBS, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3629                         else
3630                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIB, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3631                         break;
3632                 case IA64_INS_TYPE_F:
3633                         if (stops [0])
3634                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3635                         else
3636                                 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFI, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3637                         break;
3638                 case IA64_INS_TYPE_LX:
3639                         if (stops [0] || stops [1])
3640                                 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLXS, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3641                         else
3642                                 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLX, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3643                         nins_to_emit --;
3644                         break;
3645                 default:
3646                         g_assert_not_reached ();
3647                 }
3648                 nins_to_emit --;
3649         }
3650 }
3651
3652 unw_dyn_region_info_t*
3653 mono_ia64_create_unwind_region (Ia64CodegenState *code)
3654 {
3655         unw_dyn_region_info_t *r;
3656
3657         g_assert (code->nins == 0);
3658         r = g_malloc0 (_U_dyn_region_info_size (code->unw_op_count));
3659         memcpy (&r->op, &code->unw_ops, sizeof (unw_dyn_op_t) * code->unw_op_count);
3660         r->op_count = code->unw_op_count;
3661         r->insn_count = ((code->buf - code->region_start) >> 4) * 3;
3662         code->unw_op_count = 0;
3663         code->unw_op_pos = 0;
3664         code->region_start = code->buf;
3665
3666         return r;
3667 }
3668
3669 static void
3670 ia64_patch (unsigned char* code, gpointer target)
3671 {
3672         int template, i;
3673         guint64 instructions [3];
3674         guint8 gen_buf [16];
3675         Ia64CodegenState gen;
3676         int ins_to_skip;
3677         gboolean found;
3678
3679         /*
3680          * code encodes both the position inside the buffer and code.nins when
3681          * the instruction was emitted.
3682          */
3683         ins_to_skip = (guint64)code % 16;
3684         code = (unsigned char*)((guint64)code & ~15);
3685
3686         /*
3687          * Search for the first instruction which is 'patchable', skipping
3688          * ins_to_skip instructions.
3689          */
3690
3691         while (TRUE) {
3692
3693         template = ia64_bundle_template (code);
3694         instructions [0] = ia64_bundle_ins1 (code);
3695         instructions [1] = ia64_bundle_ins2 (code);
3696         instructions [2] = ia64_bundle_ins3 (code);
3697
3698         ia64_codegen_init (gen, gen_buf);
3699
3700         found = FALSE;
3701         for (i = 0; i < 3; ++i) {
3702                 guint64 ins = instructions [i];
3703                 int opcode = ia64_ins_opcode (ins);
3704
3705                 if (ins == nops_for_ins_types [ins_types_in_template [template][i]])
3706                         continue;
3707
3708                 if (ins_to_skip) {
3709                         ins_to_skip --;
3710                         continue;
3711                 }
3712
3713                 switch (ins_types_in_template [template][i]) {
3714                 case IA64_INS_TYPE_A:
3715                 case IA64_INS_TYPE_M:
3716                         if ((opcode == 8) && (ia64_ins_x2a (ins) == 2) && (ia64_ins_ve (ins) == 0)) {
3717                                 /* adds */
3718                                 ia64_adds_imm_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), (guint64)target, ia64_ins_r3 (ins));
3719                                 instructions [i] = gen.instructions [0];
3720                                 found = TRUE;
3721                         }
3722                         else
3723                                 NOT_IMPLEMENTED;
3724                         break;
3725                 case IA64_INS_TYPE_B:
3726                         if ((opcode == 4) && (ia64_ins_btype (ins) == 0)) {
3727                                 /* br.cond */
3728                                 gint64 disp = ((guint8*)target - code) >> 4;
3729
3730                                 /* FIXME: hints */
3731                                 ia64_br_cond_hint_pred (gen, ia64_ins_qp (ins), disp, 0, 0, 0);
3732
3733                                 instructions [i] = gen.instructions [0];
3734                                 found = TRUE;
3735                         }
3736                         else if (opcode == 5) {
3737                                 /* br.call */
3738                                 gint64 disp = ((guint8*)target - code) >> 4;
3739
3740                                 /* FIXME: hints */
3741                                 ia64_br_call_hint_pred (gen, ia64_ins_qp (ins), ia64_ins_b1 (ins), disp, 0, 0, 0);
3742                                 instructions [i] = gen.instructions [0];
3743                                 found = TRUE;
3744                         }
3745                         else
3746                                 NOT_IMPLEMENTED;
3747                         break;
3748                 case IA64_INS_TYPE_LX:
3749                         if (i == 1)
3750                                 break;
3751
3752                         if ((opcode == 6) && (ia64_ins_vc (ins) == 0)) {
3753                                 /* movl */
3754                                 ia64_movl_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), target);
3755                                 instructions [1] = gen.instructions [0];
3756                                 instructions [2] = gen.instructions [1];
3757                                 found = TRUE;
3758                         }
3759                         else
3760                                 NOT_IMPLEMENTED;
3761
3762                         break;
3763                 default:
3764                         NOT_IMPLEMENTED;
3765                 }
3766
3767                 if (found) {
3768                         /* Rewrite code */
3769                         ia64_codegen_init (gen, code);
3770                         ia64_emit_bundle_template (&gen, template, instructions [0], instructions [1], instructions [2]);
3771                         return;
3772                 }
3773         }
3774
3775         code += 16;
3776         }
3777 }
3778
3779 void
3780 mono_arch_patch_code (MonoCompile *cfg, MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3781 {
3782         MonoJumpInfo *patch_info;
3783
3784         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3785                 unsigned char *ip = patch_info->ip.i + code;
3786                 const unsigned char *target;
3787                 MonoError error;
3788
3789                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors, &error);
3790                 mono_error_raise_exception (&error); /* FIXME: don't raise here */
3791
3792                 if (patch_info->type == MONO_PATCH_INFO_NONE)
3793                         continue;
3794                 if (mono_compile_aot) {
3795                         NOT_IMPLEMENTED;
3796                 }
3797
3798                 ia64_patch (ip, (gpointer)target);
3799         }
3800 }
3801
3802 guint8 *
3803 mono_arch_emit_prolog (MonoCompile *cfg)
3804 {
3805         MonoMethod *method = cfg->method;
3806         MonoMethodSignature *sig;
3807         MonoInst *inst;
3808         int alloc_size, pos, i;
3809         Ia64CodegenState code;
3810         CallInfo *cinfo;
3811
3812         sig = mono_method_signature (method);
3813         pos = 0;
3814
3815         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
3816
3817         cfg->code_size =  MAX (cfg->header->code_size * 4, 512);
3818
3819         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3820                 cfg->code_size += 1024;
3821         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3822                 cfg->code_size += 1024;
3823
3824         cfg->native_code = g_malloc (cfg->code_size);
3825
3826         ia64_codegen_init (code, cfg->native_code);
3827
3828         alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
3829         if (cfg->param_area)
3830                 alloc_size += cfg->param_area;
3831         if (alloc_size)
3832                 /* scratch area */
3833                 alloc_size += 16;
3834         alloc_size = ALIGN_TO (alloc_size, MONO_ARCH_FRAME_ALIGNMENT);
3835
3836         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
3837                 /* Force sp to be saved/restored */
3838                 alloc_size += MONO_ARCH_FRAME_ALIGNMENT;
3839
3840         cfg->arch.stack_alloc_size = alloc_size;
3841
3842         pos = 0;
3843
3844         if (method->save_lmf) {
3845                 /* No LMF on IA64 */
3846         }
3847
3848         alloc_size -= pos;
3849
3850         ia64_unw_save_reg (code, UNW_IA64_AR_PFS, UNW_IA64_GR + cfg->arch.reg_saved_ar_pfs);
3851         ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3852         ia64_unw_save_reg (code, UNW_IA64_RP, UNW_IA64_GR + cfg->arch.reg_saved_b0);
3853         ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3854
3855         if ((alloc_size || cinfo->stack_usage) && !cfg->arch.omit_fp) {
3856                 ia64_unw_save_reg (code, UNW_IA64_SP, UNW_IA64_GR + cfg->arch.reg_saved_sp);
3857                 ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3858                 if (cfg->frame_reg != cfg->arch.reg_saved_sp)
3859                         ia64_mov (code, cfg->frame_reg, IA64_SP);
3860         }
3861
3862         if (alloc_size) {
3863 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3864                 int pagesize = getpagesize ();
3865
3866                 if (alloc_size >= pagesize) {
3867                         gint32 remaining_size = alloc_size;
3868
3869                         /* Generate stack touching code */
3870                         ia64_mov (code, GP_SCRATCH_REG, IA64_SP);
3871                         while (remaining_size >= pagesize) {
3872                                 ia64_movl (code, GP_SCRATCH_REG2, pagesize);
3873                                 ia64_sub (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3874                                 ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
3875                                 remaining_size -= pagesize;
3876                         }
3877                 }
3878 #endif
3879                 if (ia64_is_imm14 (-alloc_size)) {
3880                         if (cfg->arch.omit_fp)
3881                                 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3882                         ia64_adds_imm (code, IA64_SP, (-alloc_size), IA64_SP);
3883                 }
3884                 else {
3885                         ia64_movl (code, GP_SCRATCH_REG, -alloc_size);
3886                         if (cfg->arch.omit_fp)
3887                                 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3888                         ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
3889                 }
3890         }
3891
3892         ia64_begin_bundle (code);
3893
3894         /* Initialize unwind info */
3895         cfg->arch.r_pro = mono_ia64_create_unwind_region (&code);
3896
3897         if (sig->ret->type != MONO_TYPE_VOID) {
3898                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
3899                         /* Save volatile arguments to the stack */
3900                         NOT_IMPLEMENTED;
3901                 }
3902         }
3903
3904         /* Keep this in sync with emit_load_volatile_arguments */
3905         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3906                 ArgInfo *ainfo = cinfo->args + i;
3907                 gint32 stack_offset;
3908                 MonoType *arg_type;
3909
3910                 inst = cfg->args [i];
3911
3912                 if (sig->hasthis && (i == 0))
3913                         arg_type = &mono_defaults.object_class->byval_arg;
3914                 else
3915                         arg_type = sig->params [i - sig->hasthis];
3916
3917                 arg_type = mini_get_underlying_type (arg_type);
3918
3919                 stack_offset = ainfo->offset + ARGS_OFFSET;
3920
3921                 /*
3922                  * FIXME: Native code might pass non register sized integers
3923                  * without initializing the upper bits.
3924                  */
3925                 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED && !arg_type->byref && ainfo->storage == ArgInIReg) {
3926                         int reg = cfg->arch.reg_in0 + ainfo->reg;
3927
3928                         switch (mono_type_to_load_membase (cfg, arg_type)) {
3929                         case OP_LOADI1_MEMBASE:
3930                                 ia64_sxt1 (code, reg, reg);
3931                                 break;
3932                         case OP_LOADU1_MEMBASE:
3933                                 ia64_zxt1 (code, reg, reg);
3934                                 break;
3935                         case OP_LOADI2_MEMBASE:
3936                                 ia64_sxt2 (code, reg, reg);
3937                                 break;
3938                         case OP_LOADU2_MEMBASE:
3939                                 ia64_zxt2 (code, reg, reg);
3940                                 break;
3941                         default:
3942                                 break;
3943                         }
3944                 }
3945
3946                 /* Save volatile arguments to the stack */
3947                 if (inst->opcode != OP_REGVAR) {
3948                         switch (ainfo->storage) {
3949                         case ArgInIReg:
3950                         case ArgInFloatReg:
3951                         case ArgInFloatRegR4:
3952                                 g_assert (inst->opcode == OP_REGOFFSET);
3953                                 if (ia64_is_adds_imm (inst->inst_offset))
3954                                         ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3955                                 else {
3956                                         ia64_movl (code, GP_SCRATCH_REG2, inst->inst_offset);
3957                                         ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3958                                 }
3959                                 if (arg_type->byref)
3960                                         ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3961                                 else {
3962                                         switch (arg_type->type) {
3963                                         case MONO_TYPE_R4:
3964                                                 ia64_stfs_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3965                                                 break;
3966                                         case MONO_TYPE_R8:
3967                                                 ia64_stfd_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3968                                                 break;
3969                                         default:
3970                                                 ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3971                                                 break;
3972                                         }
3973                                 }
3974                                 break;
3975                         case ArgOnStack:
3976                                 break;
3977                         case ArgAggregate:
3978                                 if (ainfo->nslots != ainfo->nregs)
3979                                         NOT_IMPLEMENTED;
3980
3981                                 g_assert (inst->opcode == OP_REGOFFSET);
3982                                 ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3983                                 for (i = 0; i < ainfo->nregs; ++i) {
3984                                         switch (ainfo->atype) {
3985                                         case AggregateNormal:
3986                                                 ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg + i, sizeof (gpointer), 0);
3987                                                 break;
3988                                         case AggregateSingleHFA:
3989                                                 ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, 4, 0);
3990                                                 break;
3991                                         case AggregateDoubleHFA:
3992                                                 ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, sizeof (gpointer), 0);
3993                                                 break;
3994                                         default:
3995                                                 NOT_IMPLEMENTED;
3996                                         }
3997                                 }
3998                                 break;
3999                         default:
4000                                 g_assert_not_reached ();
4001                         }
4002                 }
4003
4004                 if (inst->opcode == OP_REGVAR) {
4005                         /* Argument allocated to (non-volatile) register */
4006                         switch (ainfo->storage) {
4007                         case ArgInIReg:
4008                                 if (inst->dreg != cfg->arch.reg_in0 + ainfo->reg)
4009                                         ia64_mov (code, inst->dreg, cfg->arch.reg_in0 + ainfo->reg);
4010                                 break;
4011                         case ArgOnStack:
4012                                 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
4013                                 ia64_ld8 (code, inst->dreg, GP_SCRATCH_REG);
4014                                 break;
4015                         default:
4016                                 NOT_IMPLEMENTED;
4017                         }
4018                 }
4019         }
4020
4021         if (method->save_lmf) {
4022                 /* No LMF on IA64 */
4023         }
4024
4025         ia64_codegen_close (code);
4026
4027         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4028                 code.buf = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code.buf, TRUE);
4029
4030         cfg->code_len = code.buf - cfg->native_code;
4031
4032         g_assert (cfg->code_len < cfg->code_size);
4033
4034         cfg->arch.prolog_end_offset = cfg->code_len;
4035
4036         return code.buf;
4037 }
4038
4039 void
4040 mono_arch_emit_epilog (MonoCompile *cfg)
4041 {
4042         MonoMethod *method = cfg->method;
4043         int i, pos;
4044         int max_epilog_size = 16 * 4;
4045         Ia64CodegenState code;
4046         guint8 *buf;
4047         CallInfo *cinfo;
4048         ArgInfo *ainfo;
4049
4050         if (mono_jit_trace_calls != NULL)
4051                 max_epilog_size += 1024;
4052
4053         cfg->arch.epilog_begin_offset = cfg->code_len;
4054
4055         while (cfg->code_len + max_epilog_size > cfg->code_size) {
4056                 cfg->code_size *= 2;
4057                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4058                 cfg->stat_code_reallocs++;
4059         }
4060
4061         /* FIXME: Emit unwind info */
4062
4063         buf = cfg->native_code + cfg->code_len;
4064
4065         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4066                 buf = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, buf, TRUE);
4067
4068         ia64_codegen_init (code, buf);
4069
4070         /* the code restoring the registers must be kept in sync with OP_JMP */
4071         pos = 0;
4072
4073         if (method->save_lmf) {
4074                 /* No LMF on IA64 */
4075         }
4076
4077         /* Load returned vtypes into registers if needed */
4078         cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
4079         ainfo = &cinfo->ret;
4080         switch (ainfo->storage) {
4081         case ArgAggregate:
4082                 if (ainfo->nslots != ainfo->nregs)
4083                         NOT_IMPLEMENTED;
4084
4085                 g_assert (cfg->ret->opcode == OP_REGOFFSET);
4086                 ia64_adds_imm (code, GP_SCRATCH_REG, cfg->ret->inst_offset, cfg->ret->inst_basereg);
4087                 for (i = 0; i < ainfo->nregs; ++i) {
4088                         switch (ainfo->atype) {
4089                         case AggregateNormal:
4090                                 ia64_ld8_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4091                                 break;
4092                         case AggregateSingleHFA:
4093                                 ia64_ldfs_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, 4, 0);
4094                                 break;
4095                         case AggregateDoubleHFA:
4096                                 ia64_ldfd_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4097                                 break;
4098                         default:
4099                                 g_assert_not_reached ();
4100                         }
4101                 }
4102                 break;
4103         default:
4104                 break;
4105         }
4106
4107         ia64_begin_bundle (code);
4108
4109         code.region_start = cfg->native_code;
4110
4111         /* Label the unwind state at the start of the exception throwing region */
4112         //ia64_unw_label_state (code, 1234);
4113
4114         if (cfg->arch.stack_alloc_size) {
4115                 if (cfg->arch.omit_fp) {
4116                         if (ia64_is_imm14 (cfg->arch.stack_alloc_size)) {
4117                                 ia64_unw_pop_frames (code, 1);
4118                                 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
4119                         } else {
4120                                 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
4121                                 ia64_unw_pop_frames (code, 1);
4122                                 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
4123                         }
4124                 }
4125                 else {
4126                         ia64_unw_pop_frames (code, 1);
4127                         ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
4128                 }
4129         }
4130         ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
4131         ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
4132         ia64_br_ret_reg (code, IA64_B0);
4133
4134         ia64_codegen_close (code);
4135
4136         cfg->arch.r_epilog = mono_ia64_create_unwind_region (&code);
4137         cfg->arch.r_pro->next = cfg->arch.r_epilog;
4138
4139         cfg->code_len = code.buf - cfg->native_code;
4140
4141         g_assert (cfg->code_len < cfg->code_size);
4142 }
4143
4144 void
4145 mono_arch_emit_exceptions (MonoCompile *cfg)
4146 {
4147         MonoJumpInfo *patch_info;
4148         int i, nthrows;
4149         Ia64CodegenState code;
4150         gboolean empty = TRUE;
4151         //unw_dyn_region_info_t *r_exceptions;
4152         MonoClass *exc_classes [16];
4153         guint8 *exc_throw_start [16], *exc_throw_end [16];
4154         guint32 code_size = 0;
4155
4156         /* Compute needed space */
4157         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4158                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4159                         code_size += 256;
4160                 if (patch_info->type == MONO_PATCH_INFO_R8)
4161                         code_size += 8 + 7; /* sizeof (double) + alignment */
4162                 if (patch_info->type == MONO_PATCH_INFO_R4)
4163                         code_size += 4 + 7; /* sizeof (float) + alignment */
4164         }
4165
4166         if (code_size == 0)
4167                 return;
4168
4169         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4170                 cfg->code_size *= 2;
4171                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4172                 cfg->stat_code_reallocs++;
4173         }
4174
4175         ia64_codegen_init (code, cfg->native_code + cfg->code_len);
4176
4177         /* The unwind state here is the same as before the epilog */
4178         //ia64_unw_copy_state (code, 1234);
4179
4180         /* add code to raise exceptions */
4181         /* FIXME: Optimize this */
4182         nthrows = 0;
4183         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4184                 switch (patch_info->type) {
4185                 case MONO_PATCH_INFO_EXC: {
4186                         MonoClass *exc_class;
4187                         guint8* throw_ip;
4188                         guint8* buf;
4189                         guint64 exc_token_index;
4190
4191                         exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4192                         exc_token_index = mono_metadata_token_index (exc_class->type_token);
4193                         throw_ip = cfg->native_code + patch_info->ip.i;
4194
4195                         ia64_begin_bundle (code);
4196
4197                         ia64_patch (cfg->native_code + patch_info->ip.i, code.buf);
4198
4199                         /* Find a throw sequence for the same exception class */
4200                         for (i = 0; i < nthrows; ++i)
4201                                 if (exc_classes [i] == exc_class)
4202                                         break;
4203
4204                         if (i < nthrows) {
4205                                 gint64 offset = exc_throw_end [i] - 16 - throw_ip;
4206
4207                                 if (ia64_is_adds_imm (offset))
4208                                         ia64_adds_imm (code, cfg->arch.reg_out0 + 1, offset, IA64_R0);
4209                                 else
4210                                         ia64_movl (code, cfg->arch.reg_out0 + 1, offset);
4211
4212                                 buf = code.buf + code.nins;
4213                                 ia64_br_cond_pred (code, 0, 0);
4214                                 ia64_begin_bundle (code);
4215                                 ia64_patch (buf, exc_throw_start [i]);
4216
4217                                 patch_info->type = MONO_PATCH_INFO_NONE;
4218                         }
4219                         else {
4220                                 /* Arg1 */
4221                                 buf = code.buf;
4222                                 ia64_movl (code, cfg->arch.reg_out0 + 1, 0);
4223
4224                                 ia64_begin_bundle (code);
4225
4226                                 if (nthrows < 16) {
4227                                         exc_classes [nthrows] = exc_class;
4228                                         exc_throw_start [nthrows] = code.buf;
4229                                 }
4230
4231                                 /* Arg2 */
4232                                 if (ia64_is_adds_imm (exc_token_index))
4233                                         ia64_adds_imm (code, cfg->arch.reg_out0 + 0, exc_token_index, IA64_R0);
4234                                 else
4235                                         ia64_movl (code, cfg->arch.reg_out0 + 0, exc_token_index);
4236
4237                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4238                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4239                                 patch_info->ip.i = code.buf + code.nins - cfg->native_code;
4240
4241                                 /* Indirect call */
4242                                 ia64_movl (code, GP_SCRATCH_REG, 0);
4243                                 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
4244                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
4245                                 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
4246
4247                                 ia64_br_call_reg (code, IA64_B0, IA64_B6);
4248
4249                                 /* Patch up the throw offset */
4250                                 ia64_begin_bundle (code);
4251
4252                                 ia64_patch (buf, (gpointer)(code.buf - 16 - throw_ip));
4253
4254                                 if (nthrows < 16) {
4255                                         exc_throw_end [nthrows] = code.buf;
4256                                         nthrows ++;
4257                                 }
4258                         }
4259
4260                         empty = FALSE;
4261                         break;
4262                 }
4263                 default:
4264                         break;
4265                 }
4266         }
4267
4268         if (!empty)
4269                 /* The unwinder needs this to work */
4270                 ia64_break_i (code, 0);
4271
4272         ia64_codegen_close (code);
4273
4274         /* FIXME: */
4275         //r_exceptions = mono_ia64_create_unwind_region (&code);
4276         //cfg->arch.r_epilog = r_exceptions;
4277
4278         cfg->code_len = code.buf - cfg->native_code;
4279
4280         g_assert (cfg->code_len < cfg->code_size);
4281 }
4282
4283 void*
4284 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4285 {
4286         Ia64CodegenState code;
4287         CallInfo *cinfo = NULL;
4288         MonoMethodSignature *sig;
4289         MonoInst *ins;
4290         int i, n, stack_area = 0;
4291
4292         ia64_codegen_init (code, p);
4293
4294         /* Keep this in sync with mono_arch_get_argument_info */
4295
4296         if (enable_arguments) {
4297                 /* Allocate a new area on the stack and save arguments there */
4298                 sig = mono_method_signature (cfg->method);
4299
4300                 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4301
4302                 n = sig->param_count + sig->hasthis;
4303
4304                 stack_area = ALIGN_TO (n * 8, 16);
4305
4306                 if (n) {
4307                         ia64_movl (code, GP_SCRATCH_REG, stack_area);
4308
4309                         ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4310
4311                         /* FIXME: Allocate out registers */
4312
4313                         ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_SP);
4314
4315                         /* Required by the ABI */
4316                         ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4317
4318                         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4319                         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4320
4321                         /* Save arguments to the stack */
4322                         for (i = 0; i < n; ++i) {
4323                                 ins = cfg->args [i];
4324
4325                                 if (ins->opcode == OP_REGVAR) {
4326                                         ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4327                                         ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4328                                         ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
4329                                 }
4330                                 else {
4331                                         ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
4332                                         ia64_add (code, GP_SCRATCH_REG, ins->inst_basereg, GP_SCRATCH_REG);
4333                                         ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
4334                                         ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4335                                         ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4336                                         ia64_st8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG2);
4337                                 }
4338                         }
4339                 }
4340                 else
4341                         ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4342         }
4343         else
4344                 ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4345
4346         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4347         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4348
4349         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4350
4351         if (enable_arguments && stack_area) {
4352                 ia64_movl (code, GP_SCRATCH_REG, stack_area);
4353
4354                 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4355
4356                 ia64_adds_imm (code, IA64_SP, 16, IA64_SP);
4357         }
4358
4359         ia64_codegen_close (code);
4360
4361         return code.buf;
4362 }
4363
4364 void*
4365 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
4366 {
4367         Ia64CodegenState code;
4368         CallInfo *cinfo = NULL;
4369         MonoMethod *method = cfg->method;
4370         MonoMethodSignature *sig = mono_method_signature (cfg->method);
4371
4372         ia64_codegen_init (code, p);
4373
4374         cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4375
4376         /* Save return value + pass it to func */
4377         switch (cinfo->ret.storage) {
4378         case ArgNone:
4379                 break;
4380         case ArgInIReg:
4381                 ia64_mov (code, cfg->arch.reg_saved_return_val, cinfo->ret.reg);
4382                 ia64_mov (code, cfg->arch.reg_out0 + 1, cinfo->ret.reg);
4383                 break;
4384         case ArgInFloatReg:
4385                 ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4386                 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4387                 ia64_stfd_hint (code, GP_SCRATCH_REG, cinfo->ret.reg, 0);
4388                 ia64_fmov (code, 8 + 1, cinfo->ret.reg);
4389                 break;
4390         case ArgValuetypeAddrInIReg:
4391                 ia64_mov (code, cfg->arch.reg_out0 + 1, cfg->arch.reg_in0 + cinfo->ret.reg);
4392                 break;
4393         case ArgAggregate:
4394                 NOT_IMPLEMENTED;
4395                 break;
4396         default:
4397                 break;
4398         }
4399
4400         add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, method);
4401         ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4402         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4403
4404         /* Restore return value */
4405         switch (cinfo->ret.storage) {
4406         case ArgNone:
4407                 break;
4408         case ArgInIReg:
4409                 ia64_mov (code, cinfo->ret.reg, cfg->arch.reg_saved_return_val);
4410                 break;
4411         case ArgInFloatReg:
4412                 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4413                 ia64_ldfd (code, cinfo->ret.reg, GP_SCRATCH_REG);
4414                 break;
4415         case ArgValuetypeAddrInIReg:
4416                 break;
4417         case ArgAggregate:
4418                 break;
4419         default:
4420                 break;
4421         }
4422
4423         ia64_codegen_close (code);
4424
4425         return code.buf;
4426 }
4427
4428 void
4429 mono_arch_save_unwind_info (MonoCompile *cfg)
4430 {
4431         unw_dyn_info_t *di;
4432
4433         /* FIXME: Unregister this for dynamic methods */
4434
4435         di = g_malloc0 (sizeof (unw_dyn_info_t));
4436         di->start_ip = (unw_word_t) cfg->native_code;
4437         di->end_ip = (unw_word_t) cfg->native_code + cfg->code_len;
4438         di->gp = 0;
4439         di->format = UNW_INFO_FORMAT_DYNAMIC;
4440         di->u.pi.name_ptr = (unw_word_t)mono_method_full_name (cfg->method, TRUE);
4441         di->u.pi.regions = cfg->arch.r_pro;
4442
4443         _U_dyn_register (di);
4444
4445         /*
4446         {
4447                 unw_dyn_region_info_t *region = di->u.pi.regions;
4448
4449                 printf ("Unwind info for method %s:\n", mono_method_full_name (cfg->method, TRUE));
4450                 while (region) {
4451                         printf ("    [Region: %d]\n", region->insn_count);
4452                         region = region->next;
4453                 }
4454         }
4455         */
4456 }
4457
4458 void
4459 mono_arch_flush_icache (guint8 *code, gint size)
4460 {
4461         guint8* p = (guint8*)((guint64)code & ~(0x3f));
4462         guint8* end = (guint8*)((guint64)code + size);
4463
4464 #ifdef __INTEL_COMPILER
4465         /* icc doesn't define an fc.i instrinsic, but fc==fc.i on itanium 2 */
4466         while (p < end) {
4467                 __fc ((guint64)p);
4468                 p += 32;
4469         }
4470 #else
4471         while (p < end) {
4472                 __asm__ __volatile__ ("fc.i %0"::"r"(p));
4473                 /* FIXME: This could be increased to 128 on some cpus */
4474                 p += 32;
4475         }
4476 #endif
4477 }
4478
4479 void
4480 mono_arch_flush_register_windows (void)
4481 {
4482         /* Not needed because of libunwind */
4483 }
4484
4485 gboolean
4486 mono_arch_is_inst_imm (gint64 imm)
4487 {
4488         /* The lowering pass will take care of it */
4489
4490         return TRUE;
4491 }
4492
4493 /*
4494  * Determine whenever the trap whose info is in SIGINFO is caused by
4495  * integer overflow.
4496  */
4497 gboolean
4498 mono_arch_is_int_overflow (void *sigctx, void *info)
4499 {
4500         /* Division is emulated with explicit overflow checks */
4501         return FALSE;
4502 }
4503
4504 guint32
4505 mono_arch_get_patch_offset (guint8 *code)
4506 {
4507         NOT_IMPLEMENTED;
4508
4509         return 0;
4510 }
4511
4512 gpointer*
4513 mono_arch_get_delegate_method_ptr_addr (guint8* code, mgreg_t *regs)
4514 {
4515         NOT_IMPLEMENTED;
4516
4517         return NULL;
4518 }
4519
4520 void
4521 mono_arch_finish_init (void)
4522 {
4523 }
4524
4525 void
4526 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4527 {
4528 }
4529
4530 /*
4531  * LOCKING: called with the domain lock held
4532  */
4533 gpointer
4534 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
4535         gpointer fail_tramp)
4536 {
4537         int i;
4538         int size = 0;
4539         guint8 *start, *buf;
4540         Ia64CodegenState code;
4541
4542         size = count * 256;
4543         buf = g_malloc0 (size);
4544         ia64_codegen_init (code, buf);
4545
4546         /* IA64_R9 contains the IMT method */
4547
4548         for (i = 0; i < count; ++i) {
4549                 MonoIMTCheckItem *item = imt_entries [i];
4550                 ia64_begin_bundle (code);
4551                 item->code_target = (guint8*)code.buf + code.nins;
4552                 if (item->is_equals) {
4553                         gboolean fail_case = !item->check_target_idx && fail_tramp;
4554
4555                         if (item->check_target_idx || fail_case) {
4556                                 if (!item->compare_done || fail_case) {
4557                                         ia64_movl (code, GP_SCRATCH_REG, item->key);
4558                                         ia64_cmp_eq (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4559                                 }
4560                                 item->jmp_code = (guint8*)code.buf + code.nins;
4561                                 ia64_br_cond_pred (code, 7, 0);
4562
4563                                 if (item->has_target_code) {
4564                                         ia64_movl (code, GP_SCRATCH_REG, item->value.target_code);
4565                                 } else {
4566                                         ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4567                                         ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4568                                 }
4569                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4570                                 ia64_br_cond_reg (code, IA64_B6);
4571
4572                                 if (fail_case) {
4573                                         ia64_begin_bundle (code);
4574                                         ia64_patch (item->jmp_code, (guint8*)code.buf + code.nins);
4575                                         ia64_movl (code, GP_SCRATCH_REG, fail_tramp);
4576                                         ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4577                                         ia64_br_cond_reg (code, IA64_B6);
4578                                         item->jmp_code = NULL;
4579                                 }
4580                         } else {
4581                                 /* enable the commented code to assert on wrong method */
4582 #if ENABLE_WRONG_METHOD_CHECK
4583                                 g_assert_not_reached ();
4584 #endif
4585                                 ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4586                                 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4587                                 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4588                                 ia64_br_cond_reg (code, IA64_B6);
4589 #if ENABLE_WRONG_METHOD_CHECK
4590                                 g_assert_not_reached ();
4591 #endif
4592                         }
4593                 } else {
4594                         ia64_movl (code, GP_SCRATCH_REG, item->key);
4595                         ia64_cmp_geu (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4596                         item->jmp_code = (guint8*)code.buf + code.nins;
4597                         ia64_br_cond_pred (code, 6, 0);
4598                 }
4599         }
4600         /* patch the branches to get to the target items */
4601         for (i = 0; i < count; ++i) {
4602                 MonoIMTCheckItem *item = imt_entries [i];
4603                 if (item->jmp_code) {
4604                         if (item->check_target_idx) {
4605                                 ia64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
4606                         }
4607                 }
4608         }
4609
4610         ia64_codegen_close (code);
4611         g_assert (code.buf - buf <= size);
4612
4613         size = code.buf - buf;
4614         if (fail_tramp) {
4615                 start = mono_method_alloc_generic_virtual_thunk (domain, size + 16);
4616                 start = (gpointer)ALIGN_TO (start, 16);
4617         } else {
4618                 start = mono_domain_code_reserve (domain, size);
4619         }
4620         memcpy (start, buf, size);
4621
4622         mono_arch_flush_icache (start, size);
4623
4624         mono_stats.imt_thunks_size += size;
4625
4626         mono_tramp_info_register (mono_tramp_info_create (NULL, start, size, NULL, NULL), domain);
4627
4628         return start;
4629 }
4630
4631 MonoMethod*
4632 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
4633 {
4634         return (MonoMethod*)regs [IA64_R9];
4635 }
4636
4637 gpointer
4638 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
4639 {
4640         return (gpointer)regs [IA64_R10];
4641 }
4642
4643 gpointer
4644 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
4645 {
4646         return NULL;
4647 }
4648
4649 gpointer
4650 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
4651 {
4652         return NULL;
4653 }
4654
4655 MonoInst*
4656 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4657 {
4658         MonoInst *ins = NULL;
4659
4660         if (cmethod->klass->image == mono_defaults.corlib &&
4661                 (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
4662                 (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
4663
4664                 /*
4665                  * We don't use the generic version in mini_emit_inst_for_method () since we
4666                  * ia64 has atomic_add_imm opcodes.
4667                  */
4668                 if (strcmp (cmethod->name, "Increment") == 0) {
4669                         guint32 opcode;
4670
4671                         if (fsig->params [0]->type == MONO_TYPE_I4)
4672                                 opcode = OP_ATOMIC_ADD_IMM_I4;
4673                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4674                                 opcode = OP_ATOMIC_ADD_IMM_I8;
4675                         else
4676                                 g_assert_not_reached ();
4677                         MONO_INST_NEW (cfg, ins, opcode);
4678                         ins->dreg = mono_alloc_preg (cfg);
4679                         ins->inst_imm = 1;
4680                         ins->inst_basereg = args [0]->dreg;
4681                         ins->inst_offset = 0;
4682                         MONO_ADD_INS (cfg->cbb, ins);
4683                 } else if (strcmp (cmethod->name, "Decrement") == 0) {
4684                         guint32 opcode;
4685
4686                         if (fsig->params [0]->type == MONO_TYPE_I4)
4687                                 opcode = OP_ATOMIC_ADD_IMM_I4;
4688                         else if (fsig->params [0]->type == MONO_TYPE_I8)
4689                                 opcode = OP_ATOMIC_ADD_IMM_I8;
4690                         else
4691                                 g_assert_not_reached ();
4692                         MONO_INST_NEW (cfg, ins, opcode);
4693                         ins->dreg = mono_alloc_preg (cfg);
4694                         ins->inst_imm = -1;
4695                         ins->inst_basereg = args [0]->dreg;
4696                         ins->inst_offset = 0;
4697                         MONO_ADD_INS (cfg->cbb, ins);
4698                 } else if (strcmp (cmethod->name, "Add") == 0) {
4699                         guint32 opcode;
4700                         gboolean is_imm = FALSE;
4701                         gint64 imm = 0;
4702
4703                         if ((args [1]->opcode == OP_ICONST) || (args [1]->opcode == OP_I8CONST)) {
4704                                 imm = (args [1]->opcode == OP_ICONST) ? args [1]->inst_c0 : args [1]->inst_l;
4705
4706                                 is_imm = (imm == 1 || imm == 4 || imm == 8 || imm == 16 || imm == -1 || imm == -4 || imm == -8 || imm == -16);
4707                         }
4708
4709                         if (is_imm) {
4710                                 if (fsig->params [0]->type == MONO_TYPE_I4)
4711                                         opcode = OP_ATOMIC_ADD_IMM_I4;
4712                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
4713                                         opcode = OP_ATOMIC_ADD_IMM_I8;
4714                                 else
4715                                         g_assert_not_reached ();
4716
4717                                 MONO_INST_NEW (cfg, ins, opcode);
4718                                 ins->dreg = mono_alloc_ireg (cfg);
4719                                 ins->inst_basereg = args [0]->dreg;
4720                                 ins->inst_offset = 0;
4721                                 ins->inst_imm = imm;
4722                                 ins->type = (opcode == OP_ATOMIC_ADD_IMM_I4) ? STACK_I4 : STACK_I8;
4723                         } else {
4724                                 if (fsig->params [0]->type == MONO_TYPE_I4)
4725                                         opcode = OP_ATOMIC_ADD_I4;
4726                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
4727                                         opcode = OP_ATOMIC_ADD_I8;
4728                                 else
4729                                         g_assert_not_reached ();
4730
4731                                 MONO_INST_NEW (cfg, ins, opcode);
4732                                 ins->dreg = mono_alloc_ireg (cfg);
4733                                 ins->inst_basereg = args [0]->dreg;
4734                                 ins->inst_offset = 0;
4735                                 ins->sreg2 = args [1]->dreg;
4736                                 ins->type = (opcode == OP_ATOMIC_ADD_I4) ? STACK_I4 : STACK_I8;
4737                         }
4738                         MONO_ADD_INS (cfg->cbb, ins);
4739                 }
4740         }
4741
4742         return ins;
4743 }
4744
4745 gboolean
4746 mono_arch_print_tree (MonoInst *tree, int arity)
4747 {
4748         return 0;
4749 }
4750
4751 mgreg_t
4752 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
4753 {
4754         /* FIXME: implement */
4755         g_assert_not_reached ();
4756 }
4757
4758 gboolean
4759 mono_arch_opcode_supported (int opcode)
4760 {
4761         switch (opcode) {
4762         case OP_ATOMIC_ADD_I4:
4763         case OP_ATOMIC_ADD_I8:
4764         case OP_ATOMIC_EXCHANGE_I4:
4765         case OP_ATOMIC_EXCHANGE_I8:
4766                 return TRUE;
4767         default:
4768                 return FALSE;
4769         }
4770 }