2 * mini-ia64.c: IA64 backend for the Mono code generator
5 * Zoltan Varga (vargaz@gmail.com)
7 * (C) 2003 Ximian, Inc.
15 #ifdef __INTEL_COMPILER
16 #include <ia64intrin.h>
19 #include <mono/metadata/appdomain.h>
20 #include <mono/metadata/debug-helpers.h>
21 #include <mono/metadata/threads.h>
22 #include <mono/metadata/profiler-private.h>
23 #include <mono/utils/mono-math.h>
26 #include "mini-ia64.h"
28 #include "jit-icalls.h"
31 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
33 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
36 * IA64 register usage:
37 * - local registers are used for global register allocation
38 * - r8..r11, r14..r30 is used for local register allocation
39 * - r31 is a scratch register used within opcode implementations
40 * - FIXME: Use out registers as well
41 * - the first three locals are used for saving ar.pfst, b0, and sp
42 * - compare instructions allways set p6 and p7
46 * There are a lot of places where generated code is disassembled/patched.
47 * The automatic bundling of instructions done by the code generation macros
48 * could complicate things, so it is best to call
49 * ia64_codegen_set_one_ins_per_bundle () at those places.
52 #define ARGS_OFFSET 16
54 #define GP_SCRATCH_REG 31
55 #define GP_SCRATCH_REG2 30
56 #define FP_SCRATCH_REG 32
57 #define FP_SCRATCH_REG2 33
59 #define LOOP_ALIGNMENT 8
60 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
62 static const char* gregs [] = {
63 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
64 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
65 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29",
66 "r30", "r31", "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
67 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", "r48", "r49",
68 "r50", "r51", "r52", "r53", "r54", "r55", "r56", "r57", "r58", "r59",
69 "r60", "r61", "r62", "r63", "r64", "r65", "r66", "r67", "r68", "r69",
70 "r70", "r71", "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
71 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", "r88", "r89",
72 "r90", "r91", "r92", "r93", "r94", "r95", "r96", "r97", "r98", "r99",
73 "r100", "r101", "r102", "r103", "r104", "r105", "r106", "r107", "r108", "r109",
74 "r110", "r111", "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
75 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127"
79 mono_arch_regname (int reg)
87 static const char* fregs [] = {
88 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
89 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
90 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
91 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
92 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
93 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
94 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69",
95 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
96 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89",
97 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99",
98 "f100", "f101", "f102", "f103", "f104", "f105", "f106", "f107", "f108", "f109",
99 "f110", "f111", "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
100 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127"
104 mono_arch_fregname (int reg)
112 G_GNUC_UNUSED static void
117 G_GNUC_UNUSED static gboolean
120 static int count = 0;
123 if (count == atoi (getenv ("COUNT"))) {
127 if (count > atoi (getenv ("COUNT"))) {
135 debug_ins_sched (void)
138 return debug_count ();
148 return debug_count ();
155 ia64_patch (unsigned char* code, gpointer target);
162 ArgValuetypeAddrInIReg,
180 /* Only if storage == ArgAggregate */
190 gboolean need_stack_align;
196 #define DEBUG(a) if (cfg->verbose_level > 1) a
201 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
203 ainfo->offset = *stack_size;
205 if (*gr >= PARAM_REGS) {
206 ainfo->storage = ArgOnStack;
207 (*stack_size) += sizeof (gpointer);
210 ainfo->storage = ArgInIReg;
216 #define FLOAT_PARAM_REGS 8
219 add_float (guint32 *gr, guint32 *fr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
221 ainfo->offset = *stack_size;
223 if (*gr >= PARAM_REGS) {
224 ainfo->storage = ArgOnStack;
225 (*stack_size) += sizeof (gpointer);
228 ainfo->storage = is_double ? ArgInFloatReg : ArgInFloatRegR4;
229 ainfo->reg = 8 + *fr;
236 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
238 guint32 *gr, guint32 *fr, guint32 *stack_size)
242 MonoMarshalType *info;
243 gboolean is_hfa = TRUE;
244 guint32 hfa_type = 0;
246 klass = mono_class_from_mono_type (type);
247 if (type->type == MONO_TYPE_TYPEDBYREF)
248 size = 3 * sizeof (gpointer);
249 else if (sig->pinvoke)
250 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
252 size = mini_type_stack_size (gsctx, &klass->byval_arg, NULL);
254 if (!sig->pinvoke || (size == 0)) {
255 /* Allways pass in memory */
256 ainfo->offset = *stack_size;
257 *stack_size += ALIGN_TO (size, 8);
258 ainfo->storage = ArgOnStack;
263 /* Determine whenever it is a HFA (Homogeneous Floating Point Aggregate) */
264 info = mono_marshal_load_type_info (klass);
266 for (i = 0; i < info->num_fields; ++i) {
267 guint32 ftype = info->fields [i].field->type->type;
268 if (!(info->fields [i].field->type->byref) &&
269 ((ftype == MONO_TYPE_R4) || (ftype == MONO_TYPE_R8))) {
272 else if (hfa_type != ftype)
281 ainfo->storage = ArgAggregate;
282 ainfo->atype = AggregateNormal;
285 ainfo->atype = hfa_type == MONO_TYPE_R4 ? AggregateSingleHFA : AggregateDoubleHFA;
287 if (info->num_fields <= 8) {
289 ainfo->nregs = info->num_fields;
290 ainfo->nslots = ainfo->nregs;
296 if ((*fr) + info->num_fields > 8)
299 ainfo->reg = 8 + (*fr);
300 ainfo->nregs = info->num_fields;
301 ainfo->nslots = ainfo->nregs;
302 (*fr) += info->num_fields;
303 if (ainfo->atype == AggregateSingleHFA) {
305 * FIXME: Have to keep track of the parameter slot number, which is
306 * not the same as *gr.
308 (*gr) += ALIGN_TO (info->num_fields, 2) / 2;
310 (*gr) += info->num_fields;
316 /* This also handles returning of TypedByRef used by some icalls */
319 ainfo->reg = IA64_R8;
320 ainfo->nregs = (size + 7) / 8;
321 ainfo->nslots = ainfo->nregs;
328 ainfo->offset = *stack_size;
329 ainfo->nslots = (size + 7) / 8;
331 if (((*gr) + ainfo->nslots) <= 8) {
332 /* Fits entirely in registers */
333 ainfo->nregs = ainfo->nslots;
334 (*gr) += ainfo->nregs;
338 ainfo->nregs = 8 - (*gr);
340 (*stack_size) += (ainfo->nslots - ainfo->nregs) * 8;
346 * Obtain information about a call according to the calling convention.
347 * For IA64, see the "Itanium Software Conventions and Runtime Architecture
348 * Gude" document for more information.
351 get_call_info (MonoCompile *cfg, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
355 int n = sig->hasthis + sig->param_count;
356 guint32 stack_size = 0;
358 MonoGenericSharingContext *gsctx = cfg ? cfg->generic_sharing_context : NULL;
361 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
363 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
370 ret_type = mono_type_get_underlying_type (sig->ret);
371 ret_type = mini_get_basic_type_from_generic (gsctx, ret_type);
372 switch (ret_type->type) {
373 case MONO_TYPE_BOOLEAN:
384 case MONO_TYPE_FNPTR:
385 case MONO_TYPE_CLASS:
386 case MONO_TYPE_OBJECT:
387 case MONO_TYPE_SZARRAY:
388 case MONO_TYPE_ARRAY:
389 case MONO_TYPE_STRING:
390 cinfo->ret.storage = ArgInIReg;
391 cinfo->ret.reg = IA64_R8;
395 cinfo->ret.storage = ArgInIReg;
396 cinfo->ret.reg = IA64_R8;
400 cinfo->ret.storage = ArgInFloatReg;
403 case MONO_TYPE_GENERICINST:
404 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
405 cinfo->ret.storage = ArgInIReg;
406 cinfo->ret.reg = IA64_R8;
410 case MONO_TYPE_VALUETYPE:
411 case MONO_TYPE_TYPEDBYREF: {
412 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
414 if (sig->ret->byref) {
415 /* This seems to happen with ldfld wrappers */
416 cinfo->ret.storage = ArgInIReg;
418 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
419 if (cinfo->ret.storage == ArgOnStack)
420 /* The caller passes the address where the value is stored */
421 add_general (&gr, &stack_size, &cinfo->ret);
422 if (cinfo->ret.storage == ArgInIReg)
423 cinfo->ret.storage = ArgValuetypeAddrInIReg;
428 cinfo->ret.storage = ArgNone;
431 g_error ("Can't handle as return value 0x%x", sig->ret->type);
436 * IA64 has MONO_ARCH_THIS_AS_FIRST_ARG defined, but we don't need to really pass
437 * this as first, because this is stored in a non-stacked register by the calling
443 add_general (&gr, &stack_size, cinfo->args + 0);
445 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
447 fr = FLOAT_PARAM_REGS;
449 /* Emit the signature cookie just before the implicit arguments */
450 add_general (&gr, &stack_size, &cinfo->sig_cookie);
453 for (i = 0; i < sig->param_count; ++i) {
454 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
457 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
458 /* We allways pass the sig cookie on the stack for simplicity */
460 * Prevent implicit arguments + the sig cookie from being passed
464 fr = FLOAT_PARAM_REGS;
466 /* Emit the signature cookie just before the implicit arguments */
467 add_general (&gr, &stack_size, &cinfo->sig_cookie);
470 if (sig->params [i]->byref) {
471 add_general (&gr, &stack_size, ainfo);
474 ptype = mono_type_get_underlying_type (sig->params [i]);
475 ptype = mini_get_basic_type_from_generic (gsctx, ptype);
476 switch (ptype->type) {
477 case MONO_TYPE_BOOLEAN:
480 add_general (&gr, &stack_size, ainfo);
485 add_general (&gr, &stack_size, ainfo);
489 add_general (&gr, &stack_size, ainfo);
494 case MONO_TYPE_FNPTR:
495 case MONO_TYPE_CLASS:
496 case MONO_TYPE_OBJECT:
497 case MONO_TYPE_STRING:
498 case MONO_TYPE_SZARRAY:
499 case MONO_TYPE_ARRAY:
500 add_general (&gr, &stack_size, ainfo);
502 case MONO_TYPE_GENERICINST:
503 if (!mono_type_generic_inst_is_valuetype (ptype)) {
504 add_general (&gr, &stack_size, ainfo);
508 case MONO_TYPE_VALUETYPE:
509 case MONO_TYPE_TYPEDBYREF:
511 /* We allways pass valuetypes on the stack */
512 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
516 add_general (&gr, &stack_size, ainfo);
519 add_float (&gr, &fr, &stack_size, ainfo, FALSE);
522 add_float (&gr, &fr, &stack_size, ainfo, TRUE);
525 g_assert_not_reached ();
529 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
531 fr = FLOAT_PARAM_REGS;
533 /* Emit the signature cookie just before the implicit arguments */
534 add_general (&gr, &stack_size, &cinfo->sig_cookie);
537 cinfo->stack_usage = stack_size;
538 cinfo->reg_usage = gr;
539 cinfo->freg_usage = fr;
544 * mono_arch_get_argument_info:
545 * @csig: a method signature
546 * @param_count: the number of parameters to consider
547 * @arg_info: an array to store the result infos
549 * Gathers information on parameters such as size, alignment and
550 * padding. arg_info should be large enought to hold param_count + 1 entries.
552 * Returns the size of the argument area on the stack.
555 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
558 CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
559 guint32 args_size = cinfo->stack_usage;
561 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
563 arg_info [0].offset = 0;
566 for (k = 0; k < param_count; k++) {
567 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
569 arg_info [k + 1].size = 0;
578 * Initialize the cpu to execute managed code.
581 mono_arch_cpu_init (void)
586 * Initialize architecture specific code.
589 mono_arch_init (void)
594 * Cleanup architecture specific code.
597 mono_arch_cleanup (void)
602 * This function returns the optimizations supported on this cpu.
605 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
613 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
617 MonoMethodSignature *sig;
618 MonoMethodHeader *header;
621 header = cfg->header;
623 sig = mono_method_signature (cfg->method);
625 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
627 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
628 MonoInst *ins = cfg->args [i];
630 ArgInfo *ainfo = &cinfo->args [i];
632 if (ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT))
635 if (ainfo->storage == ArgInIReg) {
636 /* The input registers are non-volatile */
637 ins->opcode = OP_REGVAR;
638 ins->dreg = 32 + ainfo->reg;
642 for (i = 0; i < cfg->num_varinfo; i++) {
643 MonoInst *ins = cfg->varinfo [i];
644 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
647 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
650 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
651 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
654 if (mono_is_regsize_var (ins->inst_vtype)) {
655 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
656 g_assert (i == vmv->idx);
657 vars = g_list_prepend (vars, vmv);
661 vars = mono_varlist_sort (cfg, vars, 0);
667 mono_ia64_alloc_stacked_registers (MonoCompile *cfg)
670 guint32 reserved_regs;
671 MonoMethodHeader *header;
673 if (cfg->arch.reg_local0 > 0)
677 cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (cfg->method), FALSE);
679 header = cfg->header;
681 /* Some registers are reserved for use by the prolog/epilog */
682 reserved_regs = header->num_clauses ? 4 : 3;
684 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
685 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
686 /* One registers is needed by instrument_epilog to save the return value */
688 if (cinfo->reg_usage < 2)
689 /* Number of arguments passed to function call in instrument_prolog */
690 cinfo->reg_usage = 2;
693 cfg->arch.reg_in0 = 32;
694 cfg->arch.reg_local0 = cfg->arch.reg_in0 + cinfo->reg_usage + reserved_regs;
695 cfg->arch.reg_out0 = cfg->arch.reg_local0 + 16;
697 cfg->arch.reg_saved_ar_pfs = cfg->arch.reg_local0 - 1;
698 cfg->arch.reg_saved_b0 = cfg->arch.reg_local0 - 2;
699 cfg->arch.reg_fp = cfg->arch.reg_local0 - 3;
702 * Frames without handlers save sp to fp, frames with handlers save it into
703 * a dedicated register.
705 if (header->num_clauses)
706 cfg->arch.reg_saved_sp = cfg->arch.reg_local0 - 4;
708 cfg->arch.reg_saved_sp = cfg->arch.reg_fp;
710 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
711 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)) {
712 cfg->arch.reg_saved_return_val = cfg->arch.reg_local0 - reserved_regs;
716 * Need to allocate at least 2 out register for use by OP_THROW / the system
717 * exception throwing code.
719 cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, 2);
723 mono_arch_get_global_int_regs (MonoCompile *cfg)
728 mono_ia64_alloc_stacked_registers (cfg);
730 for (i = cfg->arch.reg_local0; i < cfg->arch.reg_out0; ++i) {
733 regs = g_list_prepend (regs, (gpointer)(gssize)(i));
740 * mono_arch_regalloc_cost:
742 * Return the cost, in number of memory references, of the action of
743 * allocating the variable VMV into a register during global register
747 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
749 /* FIXME: Increase costs linearly to avoid using all local registers */
755 mono_arch_allocate_vars (MonoCompile *cfg)
757 MonoMethodSignature *sig;
758 MonoMethodHeader *header;
761 guint32 locals_stack_size, locals_stack_align;
765 header = cfg->header;
767 sig = mono_method_signature (cfg->method);
769 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
772 * Determine whenever the frame pointer can be eliminated.
773 * FIXME: Remove some of the restrictions.
775 cfg->arch.omit_fp = TRUE;
777 if (!debug_omit_fp ())
778 cfg->arch.omit_fp = FALSE;
780 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
781 cfg->arch.omit_fp = FALSE;
782 if (header->num_clauses)
783 cfg->arch.omit_fp = FALSE;
785 cfg->arch.omit_fp = FALSE;
786 if ((sig->ret->type != MONO_TYPE_VOID) && (cinfo->ret.storage == ArgAggregate))
787 cfg->arch.omit_fp = FALSE;
788 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
789 cfg->arch.omit_fp = FALSE;
790 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
791 ArgInfo *ainfo = &cinfo->args [i];
793 if (ainfo->storage == ArgOnStack) {
795 * The stack offset can only be determined when the frame
798 cfg->arch.omit_fp = FALSE;
802 mono_ia64_alloc_stacked_registers (cfg);
805 * We use the ABI calling conventions for managed code as well.
806 * Exception: valuetypes are never passed or returned in registers.
809 if (cfg->arch.omit_fp) {
810 cfg->flags |= MONO_CFG_HAS_SPILLUP;
811 cfg->frame_reg = IA64_SP;
812 offset = ARGS_OFFSET;
815 /* Locals are allocated backwards from %fp */
816 cfg->frame_reg = cfg->arch.reg_fp;
820 if (cfg->method->save_lmf) {
824 if (sig->ret->type != MONO_TYPE_VOID) {
825 switch (cinfo->ret.storage) {
827 cfg->ret->opcode = OP_REGVAR;
828 cfg->ret->inst_c0 = cinfo->ret.reg;
831 cfg->ret->opcode = OP_REGVAR;
832 cfg->ret->inst_c0 = cinfo->ret.reg;
834 case ArgValuetypeAddrInIReg:
835 cfg->vret_addr->opcode = OP_REGVAR;
836 cfg->vret_addr->dreg = cfg->arch.reg_in0 + cinfo->ret.reg;
839 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
840 if (cfg->arch.omit_fp)
841 g_assert_not_reached ();
842 offset = ALIGN_TO (offset, 8);
843 offset += cinfo->ret.nslots * 8;
844 cfg->ret->opcode = OP_REGOFFSET;
845 cfg->ret->inst_basereg = cfg->frame_reg;
846 cfg->ret->inst_offset = - offset;
849 g_assert_not_reached ();
851 cfg->ret->dreg = cfg->ret->inst_c0;
854 /* Allocate locals */
855 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE : TRUE, &locals_stack_size, &locals_stack_align);
856 if (locals_stack_align) {
857 offset = ALIGN_TO (offset, locals_stack_align);
859 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
860 if (offsets [i] != -1) {
861 MonoInst *inst = cfg->varinfo [i];
862 inst->opcode = OP_REGOFFSET;
863 inst->inst_basereg = cfg->frame_reg;
864 if (cfg->arch.omit_fp)
865 inst->inst_offset = (offset + offsets [i]);
867 inst->inst_offset = - (offset + offsets [i]);
868 // printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
871 offset += locals_stack_size;
873 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
874 if (cfg->arch.omit_fp)
875 g_assert_not_reached ();
876 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
877 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
880 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
881 inst = cfg->args [i];
882 if (inst->opcode != OP_REGVAR) {
883 ArgInfo *ainfo = &cinfo->args [i];
884 gboolean inreg = TRUE;
887 if (sig->hasthis && (i == 0))
888 arg_type = &mono_defaults.object_class->byval_arg;
890 arg_type = sig->params [i - sig->hasthis];
892 /* FIXME: VOLATILE is only set if the liveness pass runs */
893 if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
896 inst->opcode = OP_REGOFFSET;
898 switch (ainfo->storage) {
900 inst->opcode = OP_REGVAR;
901 inst->dreg = cfg->arch.reg_in0 + ainfo->reg;
904 case ArgInFloatRegR4:
906 * Since float regs are volatile, we save the arguments to
907 * the stack in the prolog.
912 if (cfg->arch.omit_fp)
913 g_assert_not_reached ();
914 inst->opcode = OP_REGOFFSET;
915 inst->inst_basereg = cfg->frame_reg;
916 inst->inst_offset = ARGS_OFFSET + ainfo->offset;
925 if (!inreg && (ainfo->storage != ArgOnStack)) {
928 inst->opcode = OP_REGOFFSET;
929 inst->inst_basereg = cfg->frame_reg;
930 /* These arguments are saved to the stack in the prolog */
931 switch (ainfo->storage) {
933 if (ainfo->atype == AggregateSingleHFA)
934 size = ainfo->nslots * 4;
936 size = ainfo->nslots * 8;
939 size = sizeof (gpointer);
943 offset = ALIGN_TO (offset, sizeof (gpointer));
945 if (cfg->arch.omit_fp) {
946 inst->inst_offset = offset;
950 inst->inst_offset = - offset;
957 * FIXME: This doesn't work because some variables are allocated during local
961 if (cfg->arch.omit_fp && offset == 16)
965 cfg->stack_offset = offset;
969 mono_arch_create_vars (MonoCompile *cfg)
971 MonoMethodSignature *sig;
974 sig = mono_method_signature (cfg->method);
976 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
978 if (cinfo->ret.storage == ArgAggregate)
979 cfg->ret_var_is_local = TRUE;
980 if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
981 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
982 if (G_UNLIKELY (cfg->verbose_level > 1)) {
983 printf ("vret_addr = ");
984 mono_print_ins (cfg->vret_addr);
990 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
994 MONO_INST_NEW (cfg, arg, OP_NOP);
995 arg->sreg1 = tree->dreg;
999 arg->opcode = OP_MOVE;
1000 arg->dreg = mono_alloc_ireg (cfg);
1002 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, FALSE);
1005 arg->opcode = OP_FMOVE;
1006 arg->dreg = mono_alloc_freg (cfg);
1008 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1010 case ArgInFloatRegR4:
1011 arg->opcode = OP_FCONV_TO_R4;
1012 arg->dreg = mono_alloc_freg (cfg);
1014 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, reg, TRUE);
1017 g_assert_not_reached ();
1020 MONO_ADD_INS (cfg->cbb, arg);
1024 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1026 MonoMethodSignature *tmp_sig;
1028 /* Emit the signature cookie just before the implicit arguments */
1030 /* FIXME: Add support for signature tokens to AOT */
1031 cfg->disable_aot = TRUE;
1033 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1036 * mono_ArgIterator_Setup assumes the signature cookie is
1037 * passed first and all the arguments which were before it are
1038 * passed on the stack after the signature. So compensate by
1039 * passing a different signature.
1041 tmp_sig = mono_metadata_signature_dup (call->signature);
1042 tmp_sig->param_count -= call->signature->sentinelpos;
1043 tmp_sig->sentinelpos = 0;
1044 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1046 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1047 sig_arg->dreg = mono_alloc_ireg (cfg);
1048 sig_arg->inst_p0 = tmp_sig;
1049 MONO_ADD_INS (cfg->cbb, sig_arg);
1051 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + cinfo->sig_cookie.offset, sig_arg->dreg);
1055 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1058 MonoMethodSignature *sig;
1059 int i, n, stack_size;
1065 mono_ia64_alloc_stacked_registers (cfg);
1067 sig = call->signature;
1068 n = sig->param_count + sig->hasthis;
1070 cinfo = get_call_info (cfg, cfg->mempool, sig, sig->pinvoke);
1072 if (cinfo->ret.storage == ArgAggregate) {
1077 * The valuetype is in registers after the call, need to be copied
1078 * to the stack. Save the address to a local here, so the call
1079 * instruction can access it.
1081 local = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1082 local->flags |= MONO_INST_VOLATILE;
1083 cfg->arch.ret_var_addr_local = local;
1085 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1086 vtarg->sreg1 = call->vret_var->dreg;
1087 vtarg->dreg = local->dreg;
1088 MONO_ADD_INS (cfg->cbb, vtarg);
1091 if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1092 add_outarg_reg (cfg, call, ArgInIReg, cfg->arch.reg_out0 + cinfo->ret.reg, call->vret_var);
1095 for (i = 0; i < n; ++i) {
1098 ainfo = cinfo->args + i;
1100 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1101 /* Emit the signature cookie just before the implicit arguments */
1102 emit_sig_cookie (cfg, call, cinfo);
1105 in = call->args [i];
1107 if (sig->hasthis && (i == 0))
1108 arg_type = &mono_defaults.object_class->byval_arg;
1110 arg_type = sig->params [i - sig->hasthis];
1112 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(arg_type))) {
1116 if (arg_type->type == MONO_TYPE_TYPEDBYREF) {
1117 size = sizeof (MonoTypedRef);
1118 align = sizeof (gpointer);
1120 else if (sig->pinvoke)
1121 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1124 * Other backends use mono_type_stack_size (), but that
1125 * aligns the size to 8, which is larger than the size of
1126 * the source, leading to reads of invalid memory if the
1127 * source is at the end of address space.
1129 size = mono_class_value_size (in->klass, &align);
1135 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1136 arg->sreg1 = in->dreg;
1137 arg->klass = in->klass;
1138 arg->backend.size = size;
1139 arg->inst_p0 = call;
1140 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1141 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1143 MONO_ADD_INS (cfg->cbb, arg);
1147 switch (ainfo->storage) {
1149 add_outarg_reg (cfg, call, ainfo->storage, cfg->arch.reg_out0 + ainfo->reg, in);
1152 case ArgInFloatRegR4:
1153 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1156 if (arg_type->type == MONO_TYPE_R4 && !arg_type->byref)
1157 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1158 else if (arg_type->type == MONO_TYPE_R8 && !arg_type->byref)
1159 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1161 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STOREI8_MEMBASE_REG, IA64_SP, 16 + ainfo->offset, in->dreg);
1164 g_assert_not_reached ();
1169 /* Handle the case where there are no implicit arguments */
1170 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1171 emit_sig_cookie (cfg, call, cinfo);
1174 call->stack_usage = cinfo->stack_usage;
1175 cfg->arch.n_out_regs = MAX (cfg->arch.n_out_regs, cinfo->reg_usage);
1179 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1181 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1182 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
1183 int size = ins->backend.size;
1185 if (ainfo->storage == ArgAggregate) {
1186 MonoInst *load, *store;
1190 * Part of the structure is passed in registers.
1192 for (i = 0; i < ainfo->nregs; ++i) {
1193 slot = ainfo->reg + i;
1195 if (ainfo->atype == AggregateSingleHFA) {
1196 MONO_INST_NEW (cfg, load, OP_LOADR4_MEMBASE);
1197 load->inst_basereg = src->dreg;
1198 load->inst_offset = i * 4;
1199 load->dreg = mono_alloc_freg (cfg);
1201 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1202 } else if (ainfo->atype == AggregateDoubleHFA) {
1203 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
1204 load->inst_basereg = src->dreg;
1205 load->inst_offset = i * 8;
1206 load->dreg = mono_alloc_freg (cfg);
1208 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, ainfo->reg + i, TRUE);
1210 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1211 load->inst_basereg = src->dreg;
1212 load->inst_offset = i * 8;
1213 load->dreg = mono_alloc_ireg (cfg);
1215 mono_call_inst_add_outarg_reg (cfg, call, load->dreg, cfg->arch.reg_out0 + ainfo->reg + i, FALSE);
1217 MONO_ADD_INS (cfg->cbb, load);
1221 * Part of the structure is passed on the stack.
1223 for (i = ainfo->nregs; i < ainfo->nslots; ++i) {
1224 slot = ainfo->reg + i;
1226 MONO_INST_NEW (cfg, load, OP_LOADI8_MEMBASE);
1227 load->inst_basereg = src->dreg;
1228 load->inst_offset = i * sizeof (gpointer);
1229 load->dreg = mono_alloc_preg (cfg);
1230 MONO_ADD_INS (cfg->cbb, load);
1232 MONO_INST_NEW (cfg, store, OP_STOREI8_MEMBASE_REG);
1233 store->sreg1 = load->dreg;
1234 store->inst_destbasereg = IA64_SP;
1235 store->inst_offset = 16 + ainfo->offset + (slot - 8) * 8;
1236 MONO_ADD_INS (cfg->cbb, store);
1239 mini_emit_memcpy (cfg, IA64_SP, 16 + ainfo->offset, src->dreg, 0, size, 4);
1244 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1246 CallInfo *cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
1248 switch (cinfo->ret.storage) {
1250 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1253 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1256 g_assert_not_reached ();
1261 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1266 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1268 MonoInst *ins, *n, *last_ins = NULL;
1271 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1272 switch (ins->opcode) {
1280 if (ins->dreg == ins->sreg1) {
1281 MONO_DELETE_INS (bb, ins);
1287 * OP_MOVE sreg, dreg
1288 * OP_MOVE dreg, sreg
1290 if (last_ins && last_ins->opcode == OP_MOVE &&
1291 ins->sreg1 == last_ins->dreg &&
1292 ins->dreg == last_ins->sreg1) {
1293 MONO_DELETE_INS (bb, ins);
1299 /* remove unnecessary multiplication with 1 */
1300 if (ins->inst_imm == 1) {
1301 if (ins->dreg != ins->sreg1) {
1302 ins->opcode = OP_MOVE;
1304 MONO_DELETE_INS (bb, ins);
1314 bb->last_ins = last_ins;
1317 int cond_to_ia64_cmp [][3] = {
1318 {OP_IA64_CMP_EQ, OP_IA64_CMP4_EQ, OP_IA64_FCMP_EQ},
1319 {OP_IA64_CMP_NE, OP_IA64_CMP4_NE, OP_IA64_FCMP_NE},
1320 {OP_IA64_CMP_LE, OP_IA64_CMP4_LE, OP_IA64_FCMP_LE},
1321 {OP_IA64_CMP_GE, OP_IA64_CMP4_GE, OP_IA64_FCMP_GE},
1322 {OP_IA64_CMP_LT, OP_IA64_CMP4_LT, OP_IA64_FCMP_LT},
1323 {OP_IA64_CMP_GT, OP_IA64_CMP4_GT, OP_IA64_FCMP_GT},
1324 {OP_IA64_CMP_LE_UN, OP_IA64_CMP4_LE_UN, OP_IA64_FCMP_LE_UN},
1325 {OP_IA64_CMP_GE_UN, OP_IA64_CMP4_GE_UN, OP_IA64_FCMP_GE_UN},
1326 {OP_IA64_CMP_LT_UN, OP_IA64_CMP4_LT_UN, OP_IA64_FCMP_LT_UN},
1327 {OP_IA64_CMP_GT_UN, OP_IA64_CMP4_GT_UN, OP_IA64_FCMP_GT_UN}
1331 opcode_to_ia64_cmp (int opcode, int cmp_opcode)
1333 return cond_to_ia64_cmp [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1336 int cond_to_ia64_cmp_imm [][3] = {
1337 {OP_IA64_CMP_EQ_IMM, OP_IA64_CMP4_EQ_IMM, 0},
1338 {OP_IA64_CMP_NE_IMM, OP_IA64_CMP4_NE_IMM, 0},
1339 {OP_IA64_CMP_GE_IMM, OP_IA64_CMP4_GE_IMM, 0},
1340 {OP_IA64_CMP_LE_IMM, OP_IA64_CMP4_LE_IMM, 0},
1341 {OP_IA64_CMP_GT_IMM, OP_IA64_CMP4_GT_IMM, 0},
1342 {OP_IA64_CMP_LT_IMM, OP_IA64_CMP4_LT_IMM, 0},
1343 {OP_IA64_CMP_GE_UN_IMM, OP_IA64_CMP4_GE_UN_IMM, 0},
1344 {OP_IA64_CMP_LE_UN_IMM, OP_IA64_CMP4_LE_UN_IMM, 0},
1345 {OP_IA64_CMP_GT_UN_IMM, OP_IA64_CMP4_GT_UN_IMM, 0},
1346 {OP_IA64_CMP_LT_UN_IMM, OP_IA64_CMP4_LT_UN_IMM, 0},
1350 opcode_to_ia64_cmp_imm (int opcode, int cmp_opcode)
1352 /* The condition needs to be reversed */
1353 return cond_to_ia64_cmp_imm [mono_opcode_to_cond (opcode)][mono_opcode_to_type (opcode, cmp_opcode)];
1356 #define NEW_INS(cfg,dest,op) do { \
1357 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
1358 (dest)->opcode = (op); \
1359 mono_bblock_insert_after_ins (bb, last_ins, (dest)); \
1360 last_ins = (dest); \
1364 * mono_arch_lowering_pass:
1366 * Converts complex opcodes into simpler ones so that each IR instruction
1367 * corresponds to one machine instruction.
1370 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1372 MonoInst *ins, *n, *next, *temp, *temp2, *temp3, *last_ins = NULL;
1375 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1376 switch (ins->opcode) {
1377 case OP_STOREI1_MEMBASE_IMM:
1378 case OP_STOREI2_MEMBASE_IMM:
1379 case OP_STOREI4_MEMBASE_IMM:
1380 case OP_STOREI8_MEMBASE_IMM:
1381 case OP_STORE_MEMBASE_IMM:
1382 /* There are no store_membase instructions on ia64 */
1383 if (ins->inst_offset == 0) {
1385 } else if (ia64_is_imm14 (ins->inst_offset)) {
1386 NEW_INS (cfg, temp2, OP_ADD_IMM);
1387 temp2->sreg1 = ins->inst_destbasereg;
1388 temp2->inst_imm = ins->inst_offset;
1389 temp2->dreg = mono_alloc_ireg (cfg);
1392 NEW_INS (cfg, temp, OP_I8CONST);
1393 temp->inst_c0 = ins->inst_offset;
1394 temp->dreg = mono_alloc_ireg (cfg);
1396 NEW_INS (cfg, temp2, OP_LADD);
1397 temp2->sreg1 = ins->inst_destbasereg;
1398 temp2->sreg2 = temp->dreg;
1399 temp2->dreg = mono_alloc_ireg (cfg);
1402 switch (ins->opcode) {
1403 case OP_STOREI1_MEMBASE_IMM:
1404 ins->opcode = OP_STOREI1_MEMBASE_REG;
1406 case OP_STOREI2_MEMBASE_IMM:
1407 ins->opcode = OP_STOREI2_MEMBASE_REG;
1409 case OP_STOREI4_MEMBASE_IMM:
1410 ins->opcode = OP_STOREI4_MEMBASE_REG;
1412 case OP_STOREI8_MEMBASE_IMM:
1413 case OP_STORE_MEMBASE_IMM:
1414 ins->opcode = OP_STOREI8_MEMBASE_REG;
1417 g_assert_not_reached ();
1420 if (ins->inst_imm == 0)
1421 ins->sreg1 = IA64_R0;
1423 NEW_INS (cfg, temp3, OP_I8CONST);
1424 temp3->inst_c0 = ins->inst_imm;
1425 temp3->dreg = mono_alloc_ireg (cfg);
1426 ins->sreg1 = temp3->dreg;
1429 ins->inst_offset = 0;
1431 ins->inst_destbasereg = temp2->dreg;
1433 case OP_STOREI1_MEMBASE_REG:
1434 case OP_STOREI2_MEMBASE_REG:
1435 case OP_STOREI4_MEMBASE_REG:
1436 case OP_STOREI8_MEMBASE_REG:
1437 case OP_STORER4_MEMBASE_REG:
1438 case OP_STORER8_MEMBASE_REG:
1439 case OP_STORE_MEMBASE_REG:
1440 /* There are no store_membase instructions on ia64 */
1441 if (ins->inst_offset == 0) {
1444 else if (ia64_is_imm14 (ins->inst_offset)) {
1445 NEW_INS (cfg, temp2, OP_ADD_IMM);
1446 temp2->sreg1 = ins->inst_destbasereg;
1447 temp2->inst_imm = ins->inst_offset;
1448 temp2->dreg = mono_alloc_ireg (cfg);
1451 NEW_INS (cfg, temp, OP_I8CONST);
1452 temp->inst_c0 = ins->inst_offset;
1453 temp->dreg = mono_alloc_ireg (cfg);
1454 NEW_INS (cfg, temp2, OP_LADD);
1455 temp2->sreg1 = ins->inst_destbasereg;
1456 temp2->sreg2 = temp->dreg;
1457 temp2->dreg = mono_alloc_ireg (cfg);
1460 ins->inst_offset = 0;
1461 ins->inst_destbasereg = temp2->dreg;
1463 case OP_LOADI1_MEMBASE:
1464 case OP_LOADU1_MEMBASE:
1465 case OP_LOADI2_MEMBASE:
1466 case OP_LOADU2_MEMBASE:
1467 case OP_LOADI4_MEMBASE:
1468 case OP_LOADU4_MEMBASE:
1469 case OP_LOADI8_MEMBASE:
1470 case OP_LOAD_MEMBASE:
1471 case OP_LOADR4_MEMBASE:
1472 case OP_LOADR8_MEMBASE:
1473 case OP_ATOMIC_EXCHANGE_I4:
1474 case OP_ATOMIC_EXCHANGE_I8:
1475 case OP_ATOMIC_ADD_NEW_I4:
1476 case OP_ATOMIC_ADD_NEW_I8:
1477 case OP_ATOMIC_ADD_IMM_NEW_I4:
1478 case OP_ATOMIC_ADD_IMM_NEW_I8:
1479 /* There are no membase instructions on ia64 */
1480 if (ins->inst_offset == 0) {
1483 else if (ia64_is_imm14 (ins->inst_offset)) {
1484 NEW_INS (cfg, temp2, OP_ADD_IMM);
1485 temp2->sreg1 = ins->inst_basereg;
1486 temp2->inst_imm = ins->inst_offset;
1487 temp2->dreg = mono_alloc_ireg (cfg);
1490 NEW_INS (cfg, temp, OP_I8CONST);
1491 temp->inst_c0 = ins->inst_offset;
1492 temp->dreg = mono_alloc_ireg (cfg);
1493 NEW_INS (cfg, temp2, OP_LADD);
1494 temp2->sreg1 = ins->inst_basereg;
1495 temp2->sreg2 = temp->dreg;
1496 temp2->dreg = mono_alloc_ireg (cfg);
1499 ins->inst_offset = 0;
1500 ins->inst_basereg = temp2->dreg;
1520 case OP_ISHR_UN_IMM:
1521 case OP_LSHR_UN_IMM: {
1522 gboolean is_imm = FALSE;
1523 gboolean switched = FALSE;
1525 if (ins->opcode == OP_AND_IMM && ins->inst_imm == 255) {
1526 ins->opcode = OP_ZEXT_I1;
1530 switch (ins->opcode) {
1534 is_imm = ia64_is_imm14 (ins->inst_imm);
1539 is_imm = ia64_is_imm14 (- (ins->inst_imm));
1541 /* A = B - IMM -> A = B + (-IMM) */
1542 ins->inst_imm = - ins->inst_imm;
1543 ins->opcode = OP_IADD_IMM;
1554 is_imm = ia64_is_imm8 (ins->inst_imm);
1563 case OP_ISHR_UN_IMM:
1564 case OP_LSHR_UN_IMM:
1565 is_imm = (ins->inst_imm >= 0) && (ins->inst_imm < 64);
1573 ins->sreg2 = ins->sreg1;
1577 ins->opcode = mono_op_imm_to_op (ins->opcode);
1579 if (ins->inst_imm == 0)
1580 ins->sreg2 = IA64_R0;
1582 NEW_INS (cfg, temp, OP_I8CONST);
1583 temp->inst_c0 = ins->inst_imm;
1584 temp->dreg = mono_alloc_ireg (cfg);
1585 ins->sreg2 = temp->dreg;
1589 case OP_COMPARE_IMM:
1590 case OP_ICOMPARE_IMM:
1591 case OP_LCOMPARE_IMM: {
1592 /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1598 /* Branch opts can eliminate the branch */
1599 if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1605 * The compare_imm instructions have switched up arguments, and
1606 * some of them take an imm between -127 and 128.
1609 cond = mono_opcode_to_cond (next->opcode);
1610 if ((cond == CMP_LT) || (cond == CMP_GE))
1611 imm = ia64_is_imm8 (ins->inst_imm - 1);
1612 else if ((cond == CMP_LT_UN) || (cond == CMP_GE_UN))
1613 imm = ia64_is_imm8 (ins->inst_imm - 1) && (ins->inst_imm > 0);
1615 imm = ia64_is_imm8 (ins->inst_imm);
1618 ins->opcode = opcode_to_ia64_cmp_imm (next->opcode, ins->opcode);
1619 ins->sreg2 = ins->sreg1;
1622 ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1624 if (ins->inst_imm == 0)
1625 ins->sreg2 = IA64_R0;
1627 NEW_INS (cfg, temp, OP_I8CONST);
1628 temp->inst_c0 = ins->inst_imm;
1629 temp->dreg = mono_alloc_ireg (cfg);
1630 ins->sreg2 = temp->dreg;
1634 if (MONO_IS_COND_BRANCH_OP (next)) {
1635 next->opcode = OP_IA64_BR_COND;
1636 next->inst_target_bb = next->inst_true_bb;
1637 } else if (MONO_IS_COND_EXC (next)) {
1638 next->opcode = OP_IA64_COND_EXC;
1639 } else if (MONO_IS_SETCC (next)) {
1640 next->opcode = OP_IA64_CSET;
1642 printf ("%s\n", mono_inst_name (next->opcode));
1652 /* Instead of compare+b<cond>, ia64 has compare<cond>+br */
1656 /* Branch opts can eliminate the branch */
1657 if (!next || (!(MONO_IS_COND_BRANCH_OP (next) || MONO_IS_COND_EXC (next) || MONO_IS_SETCC (next)))) {
1662 ins->opcode = opcode_to_ia64_cmp (next->opcode, ins->opcode);
1664 if (MONO_IS_COND_BRANCH_OP (next)) {
1665 next->opcode = OP_IA64_BR_COND;
1666 next->inst_target_bb = next->inst_true_bb;
1667 } else if (MONO_IS_COND_EXC (next)) {
1668 next->opcode = OP_IA64_COND_EXC;
1669 } else if (MONO_IS_SETCC (next)) {
1670 next->opcode = OP_IA64_CSET;
1672 printf ("%s\n", mono_inst_name (next->opcode));
1683 /* The front end removes the fcompare, so introduce it again */
1684 NEW_INS (cfg, temp, opcode_to_ia64_cmp (ins->opcode, OP_FCOMPARE));
1685 temp->sreg1 = ins->sreg1;
1686 temp->sreg2 = ins->sreg2;
1688 ins->opcode = OP_IA64_CSET;
1689 MONO_INST_NULLIFY_SREGS (ins);
1695 gboolean found = FALSE;
1696 int shl_op = ins->opcode == OP_IMUL_IMM ? OP_ISHL_IMM : OP_SHL_IMM;
1698 /* First the easy cases */
1699 if (ins->inst_imm == 1) {
1700 ins->opcode = OP_MOVE;
1703 for (i = 1; i < 64; ++i)
1704 if (ins->inst_imm == (((gint64)1) << i)) {
1705 ins->opcode = shl_op;
1711 /* This could be optimized */
1714 for (i = 0; i < 64; ++i) {
1715 if (ins->inst_imm & (((gint64)1) << i)) {
1716 NEW_INS (cfg, temp, shl_op);
1717 temp->dreg = mono_alloc_ireg (cfg);
1718 temp->sreg1 = ins->sreg1;
1722 sum_reg = temp->dreg;
1724 NEW_INS (cfg, temp2, OP_LADD);
1725 temp2->dreg = mono_alloc_ireg (cfg);
1726 temp2->sreg1 = sum_reg;
1727 temp2->sreg2 = temp->dreg;
1728 sum_reg = temp2->dreg;
1732 ins->opcode = OP_MOVE;
1733 ins->sreg1 = sum_reg;
1737 case OP_LCONV_TO_OVF_U4:
1738 NEW_INS (cfg, temp, OP_IA64_CMP4_LT);
1739 temp->sreg1 = ins->sreg1;
1740 temp->sreg2 = IA64_R0;
1742 NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1743 temp->inst_p1 = (char*)"OverflowException";
1745 ins->opcode = OP_MOVE;
1747 case OP_LCONV_TO_OVF_I4_UN:
1748 NEW_INS (cfg, temp, OP_ICONST);
1749 temp->inst_c0 = 0x7fffffff;
1750 temp->dreg = mono_alloc_ireg (cfg);
1752 NEW_INS (cfg, temp2, OP_IA64_CMP4_GT_UN);
1753 temp2->sreg1 = ins->sreg1;
1754 temp2->sreg2 = temp->dreg;
1756 NEW_INS (cfg, temp, OP_IA64_COND_EXC);
1757 temp->inst_p1 = (char*)"OverflowException";
1759 ins->opcode = OP_MOVE;
1761 case OP_FCONV_TO_I4:
1762 case OP_FCONV_TO_I2:
1763 case OP_FCONV_TO_U2:
1764 case OP_FCONV_TO_I1:
1765 case OP_FCONV_TO_U1:
1766 NEW_INS (cfg, temp, OP_FCONV_TO_I8);
1767 temp->sreg1 = ins->sreg1;
1768 temp->dreg = ins->dreg;
1770 switch (ins->opcode) {
1771 case OP_FCONV_TO_I4:
1772 ins->opcode = OP_SEXT_I4;
1774 case OP_FCONV_TO_I2:
1775 ins->opcode = OP_SEXT_I2;
1777 case OP_FCONV_TO_U2:
1778 ins->opcode = OP_ZEXT_I4;
1780 case OP_FCONV_TO_I1:
1781 ins->opcode = OP_SEXT_I1;
1783 case OP_FCONV_TO_U1:
1784 ins->opcode = OP_ZEXT_I1;
1787 g_assert_not_reached ();
1789 ins->sreg1 = ins->dreg;
1797 bb->last_ins = last_ins;
1799 bb->max_vreg = cfg->next_vreg;
1803 * emit_load_volatile_arguments:
1805 * Load volatile arguments from the stack to the original input registers.
1806 * Required before a tail call.
1808 static Ia64CodegenState
1809 emit_load_volatile_arguments (MonoCompile *cfg, Ia64CodegenState code)
1811 MonoMethod *method = cfg->method;
1812 MonoMethodSignature *sig;
1817 /* FIXME: Generate intermediate code instead */
1819 sig = mono_method_signature (method);
1821 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
1823 /* This is the opposite of the code in emit_prolog */
1824 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1825 ArgInfo *ainfo = cinfo->args + i;
1826 gint32 stack_offset;
1829 ins = cfg->args [i];
1831 if (sig->hasthis && (i == 0))
1832 arg_type = &mono_defaults.object_class->byval_arg;
1834 arg_type = sig->params [i - sig->hasthis];
1836 arg_type = mono_type_get_underlying_type (arg_type);
1838 stack_offset = ainfo->offset + ARGS_OFFSET;
1840 /* Save volatile arguments to the stack */
1841 if (ins->opcode != OP_REGVAR) {
1842 switch (ainfo->storage) {
1845 /* FIXME: big offsets */
1846 g_assert (ins->opcode == OP_REGOFFSET);
1847 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
1848 if (arg_type->byref)
1849 ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1851 switch (arg_type->type) {
1853 ia64_ldfs (code, ainfo->reg, GP_SCRATCH_REG);
1856 ia64_ldfd (code, ainfo->reg, GP_SCRATCH_REG);
1859 ia64_ld8 (code, cfg->arch.reg_in0 + ainfo->reg, GP_SCRATCH_REG);
1871 if (ins->opcode == OP_REGVAR) {
1872 /* Argument allocated to (non-volatile) register */
1873 switch (ainfo->storage) {
1875 if (ins->dreg != cfg->arch.reg_in0 + ainfo->reg)
1876 ia64_mov (code, cfg->arch.reg_in0 + ainfo->reg, ins->dreg);
1879 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
1880 ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
1891 static Ia64CodegenState
1892 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, Ia64CodegenState code)
1897 /* Move return value to the target register */
1898 switch (ins->opcode) {
1900 case OP_VOIDCALL_REG:
1901 case OP_VOIDCALL_MEMBASE:
1905 case OP_CALL_MEMBASE:
1908 case OP_LCALL_MEMBASE:
1909 g_assert (ins->dreg == IA64_R8);
1913 case OP_FCALL_MEMBASE:
1914 g_assert (ins->dreg == 8);
1915 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4)
1916 ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
1920 case OP_VCALL_MEMBASE:
1923 case OP_VCALL2_MEMBASE: {
1926 cinfo = get_call_info (cfg, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
1927 storage = cinfo->ret.storage;
1929 if (storage == ArgAggregate) {
1930 MonoInst *local = (MonoInst*)cfg->arch.ret_var_addr_local;
1932 /* Load address of stack space allocated for the return value */
1933 ia64_movl (code, GP_SCRATCH_REG, local->inst_offset);
1934 ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, local->inst_basereg);
1935 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
1937 for (i = 0; i < cinfo->ret.nregs; ++i) {
1938 switch (cinfo->ret.atype) {
1939 case AggregateNormal:
1940 ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1942 case AggregateSingleHFA:
1943 ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 4, 0);
1945 case AggregateDoubleHFA:
1946 ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, cinfo->ret.reg + i, 8, 0);
1949 g_assert_not_reached ();
1956 g_assert_not_reached ();
1962 #define add_patch_info(cfg,code,patch_type,data) do { \
1963 mono_add_patch_info (cfg, code.buf + code.nins - cfg->native_code, patch_type, data); \
1966 #define emit_cond_system_exception(cfg,code,exc_name,predicate) do { \
1967 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1969 add_patch_info (cfg, code, MONO_PATCH_INFO_EXC, exc_name); \
1971 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, tins->inst_true_bb); \
1972 ia64_br_cond_pred (code, (predicate), 0); \
1975 static Ia64CodegenState
1976 emit_call (MonoCompile *cfg, Ia64CodegenState code, guint32 patch_type, gconstpointer data)
1978 add_patch_info (cfg, code, patch_type, data);
1980 if ((patch_type == MONO_PATCH_INFO_ABS) || (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD)) {
1982 /* mono_arch_patch_callsite will patch this */
1983 /* mono_arch_nullify_class_init_trampoline will patch this */
1984 ia64_movl (code, GP_SCRATCH_REG, 0);
1985 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
1986 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
1987 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
1988 ia64_br_call_reg (code, IA64_B0, IA64_B6);
1991 /* Can't use a direct call since the displacement might be too small */
1992 /* mono_arch_patch_callsite will patch this */
1993 ia64_movl (code, GP_SCRATCH_REG, 0);
1994 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
1995 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2001 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2004 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2009 Ia64CodegenState code;
2010 guint8 *code_start = cfg->native_code + cfg->code_len;
2011 MonoInst *last_ins = NULL;
2012 guint last_offset = 0;
2015 if (cfg->opt & MONO_OPT_LOOP) {
2019 if (cfg->verbose_level > 2)
2020 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2022 cpos = bb->max_offset;
2024 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2028 offset = code_start - cfg->native_code;
2030 ia64_codegen_init (code, code_start);
2033 if (strstr (cfg->method->name, "conv_ovf_i1") && (bb->block_num == 2))
2037 MONO_BB_FOR_EACH_INS (bb, ins) {
2038 offset = code.buf - cfg->native_code;
2040 max_len = ((int)(((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN])) + 128;
2042 while (offset + max_len + 16 > cfg->code_size) {
2043 ia64_codegen_close (code);
2045 offset = code.buf - cfg->native_code;
2047 cfg->code_size *= 2;
2048 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2049 code_start = cfg->native_code + offset;
2050 mono_jit_stats.code_reallocs++;
2052 ia64_codegen_init (code, code_start);
2055 mono_debug_record_line_number (cfg, ins, offset);
2057 switch (ins->opcode) {
2060 if (ia64_is_imm14 (ins->inst_c0))
2061 ia64_adds_imm (code, ins->dreg, ins->inst_c0, IA64_R0);
2063 ia64_movl (code, ins->dreg, ins->inst_c0);
2066 add_patch_info (cfg, code, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2067 ia64_movl (code, ins->dreg, 0);
2070 ia64_mov (code, ins->dreg, ins->sreg1);
2073 case OP_IA64_BR_COND: {
2075 if (ins->opcode == OP_IA64_BR_COND)
2077 if (ins->inst_target_bb->native_offset) {
2078 guint8 *pos = code.buf + code.nins;
2080 ia64_br_cond_pred (code, pred, 0);
2081 ia64_begin_bundle (code);
2082 ia64_patch (pos, cfg->native_code + ins->inst_target_bb->native_offset);
2084 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2085 ia64_br_cond_pred (code, pred, 0);
2090 ia64_begin_bundle (code);
2091 ins->inst_c0 = code.buf - cfg->native_code;
2094 case OP_RELAXED_NOP:
2096 case OP_DUMMY_STORE:
2097 case OP_NOT_REACHED:
2101 ia64_mov_to_br (code, IA64_B6, ins->sreg1);
2102 ia64_br_cond_reg (code, IA64_B6);
2106 ia64_add (code, ins->dreg, ins->sreg1, ins->sreg2);
2110 ia64_sub (code, ins->dreg, ins->sreg1, ins->sreg2);
2114 ia64_and (code, ins->dreg, ins->sreg1, ins->sreg2);
2118 ia64_or (code, ins->dreg, ins->sreg1, ins->sreg2);
2122 ia64_xor (code, ins->dreg, ins->sreg1, ins->sreg2);
2126 ia64_sub (code, ins->dreg, IA64_R0, ins->sreg1);
2130 ia64_andcm_imm (code, ins->dreg, -1, ins->sreg1);
2134 ia64_shl (code, ins->dreg, ins->sreg1, ins->sreg2);
2137 ia64_sxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2138 ia64_shr (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2141 ia64_shr (code, ins->dreg, ins->sreg1, ins->sreg2);
2144 ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2145 ia64_shr_u (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2148 ia64_shr_u (code, ins->dreg, ins->sreg1, ins->sreg2);
2151 /* p6 and p7 is set if there is signed/unsigned overflow */
2153 /* Set p8-p9 == (sreg2 > 0) */
2154 ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2156 ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2158 /* (sreg2 > 0) && (res < ins->sreg1) => signed overflow */
2159 ia64_cmp4_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2160 /* (sreg2 <= 0) && (res > ins->sreg1) => signed overflow */
2161 ia64_cmp4_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2163 /* res <u sreg1 => unsigned overflow */
2164 ia64_cmp4_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2166 /* FIXME: Predicate this since this is a side effect */
2167 ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2170 /* p6 and p7 is set if there is signed/unsigned overflow */
2172 /* Set p8-p9 == (sreg2 > 0) */
2173 ia64_cmp4_lt (code, 8, 9, IA64_R0, ins->sreg2);
2175 ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2177 /* (sreg2 > 0) && (res > ins->sreg1) => signed overflow */
2178 ia64_cmp4_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2179 /* (sreg2 <= 0) && (res < ins->sreg1) => signed overflow */
2180 ia64_cmp4_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2182 /* sreg1 <u sreg2 => unsigned overflow */
2183 ia64_cmp4_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2185 /* FIXME: Predicate this since this is a side effect */
2186 ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2189 /* Same as OP_IADDCC */
2190 ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2192 ia64_add (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2194 ia64_cmp_lt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2195 ia64_cmp_lt_pred (code, 9, 6, 10, ins->sreg1, GP_SCRATCH_REG);
2197 ia64_cmp_ltu (code, 7, 10, GP_SCRATCH_REG, ins->sreg1);
2199 ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2202 /* Same as OP_ISUBCC */
2204 ia64_cmp_lt (code, 8, 9, IA64_R0, ins->sreg2);
2206 ia64_sub (code, GP_SCRATCH_REG, ins->sreg1, ins->sreg2);
2208 ia64_cmp_gt_pred (code, 8, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2209 ia64_cmp_lt_pred (code, 9, 6, 10, GP_SCRATCH_REG, ins->sreg1);
2211 ia64_cmp_ltu (code, 7, 10, ins->sreg1, ins->sreg2);
2213 ia64_mov (code, ins->dreg, GP_SCRATCH_REG);
2218 ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2223 ia64_and_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2227 ia64_or_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2231 ia64_xor_imm (code, ins->dreg, ins->inst_imm, ins->sreg1);
2236 ia64_shl_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2240 ia64_shr_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2243 g_assert (ins->inst_imm <= 64);
2244 ia64_extr (code, ins->dreg, ins->sreg1, ins->inst_imm, 32 - ins->inst_imm);
2246 case OP_ISHR_UN_IMM:
2247 ia64_zxt4 (code, GP_SCRATCH_REG, ins->sreg1);
2248 ia64_shr_u_imm (code, ins->dreg, GP_SCRATCH_REG, ins->inst_imm);
2250 case OP_LSHR_UN_IMM:
2251 ia64_shr_u_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
2254 /* Based on gcc code */
2255 ia64_setf_sig (code, FP_SCRATCH_REG, ins->sreg1);
2256 ia64_setf_sig (code, FP_SCRATCH_REG2, ins->sreg2);
2257 ia64_xmpy_l (code, FP_SCRATCH_REG, FP_SCRATCH_REG, FP_SCRATCH_REG2);
2258 ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2261 case OP_STOREI1_MEMBASE_REG:
2262 ia64_st1_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2264 case OP_STOREI2_MEMBASE_REG:
2265 ia64_st2_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2267 case OP_STOREI4_MEMBASE_REG:
2268 ia64_st4_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2270 case OP_STOREI8_MEMBASE_REG:
2271 case OP_STORE_MEMBASE_REG:
2272 if (ins->inst_offset != 0) {
2273 /* This is generated by local regalloc */
2274 if (ia64_is_imm14 (ins->inst_offset)) {
2275 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2277 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2278 ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2280 ins->inst_destbasereg = GP_SCRATCH_REG;
2282 ia64_st8_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2285 case OP_IA64_STOREI1_MEMBASE_INC_REG:
2286 ia64_st1_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 1, 0);
2288 case OP_IA64_STOREI2_MEMBASE_INC_REG:
2289 ia64_st2_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 2, 0);
2291 case OP_IA64_STOREI4_MEMBASE_INC_REG:
2292 ia64_st4_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 4, 0);
2294 case OP_IA64_STOREI8_MEMBASE_INC_REG:
2295 ia64_st8_inc_imm_hint (code, ins->inst_destbasereg, ins->sreg1, 8, 0);
2298 case OP_LOADU1_MEMBASE:
2299 ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2301 case OP_LOADU2_MEMBASE:
2302 ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2304 case OP_LOADU4_MEMBASE:
2305 ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2307 case OP_LOADI1_MEMBASE:
2308 ia64_ld1 (code, ins->dreg, ins->inst_basereg);
2309 ia64_sxt1 (code, ins->dreg, ins->dreg);
2311 case OP_LOADI2_MEMBASE:
2312 ia64_ld2 (code, ins->dreg, ins->inst_basereg);
2313 ia64_sxt2 (code, ins->dreg, ins->dreg);
2315 case OP_LOADI4_MEMBASE:
2316 ia64_ld4 (code, ins->dreg, ins->inst_basereg);
2317 ia64_sxt4 (code, ins->dreg, ins->dreg);
2319 case OP_LOAD_MEMBASE:
2320 case OP_LOADI8_MEMBASE:
2321 if (ins->inst_offset != 0) {
2322 /* This is generated by local regalloc */
2323 if (ia64_is_imm14 (ins->inst_offset)) {
2324 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2326 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2327 ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2329 ins->inst_basereg = GP_SCRATCH_REG;
2331 ia64_ld8 (code, ins->dreg, ins->inst_basereg);
2334 case OP_IA64_LOADU1_MEMBASE_INC:
2335 ia64_ld1_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 1, 0);
2337 case OP_IA64_LOADU2_MEMBASE_INC:
2338 ia64_ld2_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 2, 0);
2340 case OP_IA64_LOADU4_MEMBASE_INC:
2341 ia64_ld4_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 4, 0);
2343 case OP_IA64_LOADI8_MEMBASE_INC:
2344 ia64_ld8_inc_imm_hint (code, ins->dreg, ins->inst_basereg, 8, 0);
2348 ia64_sxt1 (code, ins->dreg, ins->sreg1);
2351 ia64_sxt2 (code, ins->dreg, ins->sreg1);
2354 ia64_sxt4 (code, ins->dreg, ins->sreg1);
2357 ia64_zxt1 (code, ins->dreg, ins->sreg1);
2360 ia64_zxt2 (code, ins->dreg, ins->sreg1);
2363 ia64_zxt4 (code, ins->dreg, ins->sreg1);
2366 /* Compare opcodes */
2367 case OP_IA64_CMP4_EQ:
2368 ia64_cmp4_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2370 case OP_IA64_CMP4_NE:
2371 ia64_cmp4_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2373 case OP_IA64_CMP4_LE:
2374 ia64_cmp4_le (code, 6, 7, ins->sreg1, ins->sreg2);
2376 case OP_IA64_CMP4_LT:
2377 ia64_cmp4_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2379 case OP_IA64_CMP4_GE:
2380 ia64_cmp4_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2382 case OP_IA64_CMP4_GT:
2383 ia64_cmp4_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2385 case OP_IA64_CMP4_LT_UN:
2386 ia64_cmp4_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2388 case OP_IA64_CMP4_LE_UN:
2389 ia64_cmp4_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2391 case OP_IA64_CMP4_GT_UN:
2392 ia64_cmp4_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2394 case OP_IA64_CMP4_GE_UN:
2395 ia64_cmp4_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2397 case OP_IA64_CMP_EQ:
2398 ia64_cmp_eq (code, 6, 7, ins->sreg1, ins->sreg2);
2400 case OP_IA64_CMP_NE:
2401 ia64_cmp_ne (code, 6, 7, ins->sreg1, ins->sreg2);
2403 case OP_IA64_CMP_LE:
2404 ia64_cmp_le (code, 6, 7, ins->sreg1, ins->sreg2);
2406 case OP_IA64_CMP_LT:
2407 ia64_cmp_lt (code, 6, 7, ins->sreg1, ins->sreg2);
2409 case OP_IA64_CMP_GE:
2410 ia64_cmp_ge (code, 6, 7, ins->sreg1, ins->sreg2);
2412 case OP_IA64_CMP_GT:
2413 ia64_cmp_gt (code, 6, 7, ins->sreg1, ins->sreg2);
2415 case OP_IA64_CMP_GT_UN:
2416 ia64_cmp_gtu (code, 6, 7, ins->sreg1, ins->sreg2);
2418 case OP_IA64_CMP_LT_UN:
2419 ia64_cmp_ltu (code, 6, 7, ins->sreg1, ins->sreg2);
2421 case OP_IA64_CMP_GE_UN:
2422 ia64_cmp_geu (code, 6, 7, ins->sreg1, ins->sreg2);
2424 case OP_IA64_CMP_LE_UN:
2425 ia64_cmp_leu (code, 6, 7, ins->sreg1, ins->sreg2);
2427 case OP_IA64_CMP4_EQ_IMM:
2428 ia64_cmp4_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2430 case OP_IA64_CMP4_NE_IMM:
2431 ia64_cmp4_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2433 case OP_IA64_CMP4_LE_IMM:
2434 ia64_cmp4_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2436 case OP_IA64_CMP4_LT_IMM:
2437 ia64_cmp4_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2439 case OP_IA64_CMP4_GE_IMM:
2440 ia64_cmp4_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2442 case OP_IA64_CMP4_GT_IMM:
2443 ia64_cmp4_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2445 case OP_IA64_CMP4_LT_UN_IMM:
2446 ia64_cmp4_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2448 case OP_IA64_CMP4_LE_UN_IMM:
2449 ia64_cmp4_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2451 case OP_IA64_CMP4_GT_UN_IMM:
2452 ia64_cmp4_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2454 case OP_IA64_CMP4_GE_UN_IMM:
2455 ia64_cmp4_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2457 case OP_IA64_CMP_EQ_IMM:
2458 ia64_cmp_eq_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2460 case OP_IA64_CMP_NE_IMM:
2461 ia64_cmp_ne_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2463 case OP_IA64_CMP_LE_IMM:
2464 ia64_cmp_le_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2466 case OP_IA64_CMP_LT_IMM:
2467 ia64_cmp_lt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2469 case OP_IA64_CMP_GE_IMM:
2470 ia64_cmp_ge_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2472 case OP_IA64_CMP_GT_IMM:
2473 ia64_cmp_gt_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2475 case OP_IA64_CMP_GT_UN_IMM:
2476 ia64_cmp_gtu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2478 case OP_IA64_CMP_LT_UN_IMM:
2479 ia64_cmp_ltu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2481 case OP_IA64_CMP_GE_UN_IMM:
2482 ia64_cmp_geu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2484 case OP_IA64_CMP_LE_UN_IMM:
2485 ia64_cmp_leu_imm (code, 6, 7, ins->inst_imm, ins->sreg2);
2487 case OP_IA64_FCMP_EQ:
2488 ia64_fcmp_eq_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2490 case OP_IA64_FCMP_NE:
2491 ia64_fcmp_ne_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2493 case OP_IA64_FCMP_LT:
2494 ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2496 case OP_IA64_FCMP_GT:
2497 ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2499 case OP_IA64_FCMP_LE:
2500 ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2502 case OP_IA64_FCMP_GE:
2503 ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2505 case OP_IA64_FCMP_GT_UN:
2506 ia64_fcmp_gt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2507 ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2509 case OP_IA64_FCMP_LT_UN:
2510 ia64_fcmp_lt_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2511 ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2513 case OP_IA64_FCMP_GE_UN:
2514 ia64_fcmp_ge_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2515 ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2517 case OP_IA64_FCMP_LE_UN:
2518 ia64_fcmp_le_sf (code, 6, 7, ins->sreg1, ins->sreg2, 0);
2519 ia64_fcmp_unord_sf_pred (code, 7, 6, 7, ins->sreg1, ins->sreg2, 0);
2522 case OP_COND_EXC_IOV:
2523 case OP_COND_EXC_OV:
2524 emit_cond_system_exception (cfg, code, "OverflowException", 6);
2526 case OP_COND_EXC_IC:
2528 emit_cond_system_exception (cfg, code, "OverflowException", 7);
2530 case OP_IA64_COND_EXC:
2531 emit_cond_system_exception (cfg, code, ins->inst_p1, 6);
2534 ia64_mov_pred (code, 7, ins->dreg, IA64_R0);
2535 ia64_no_stop (code);
2536 ia64_add1_pred (code, 6, ins->dreg, IA64_R0, IA64_R0);
2538 case OP_ICONV_TO_I1:
2539 case OP_LCONV_TO_I1:
2540 /* FIXME: Is this needed ? */
2541 ia64_sxt1 (code, ins->dreg, ins->sreg1);
2543 case OP_ICONV_TO_I2:
2544 case OP_LCONV_TO_I2:
2545 /* FIXME: Is this needed ? */
2546 ia64_sxt2 (code, ins->dreg, ins->sreg1);
2548 case OP_LCONV_TO_I4:
2549 /* FIXME: Is this needed ? */
2550 ia64_sxt4 (code, ins->dreg, ins->sreg1);
2552 case OP_ICONV_TO_U1:
2553 case OP_LCONV_TO_U1:
2554 /* FIXME: Is this needed */
2555 ia64_zxt1 (code, ins->dreg, ins->sreg1);
2557 case OP_ICONV_TO_U2:
2558 case OP_LCONV_TO_U2:
2559 /* FIXME: Is this needed */
2560 ia64_zxt2 (code, ins->dreg, ins->sreg1);
2562 case OP_LCONV_TO_U4:
2563 /* FIXME: Is this needed */
2564 ia64_zxt4 (code, ins->dreg, ins->sreg1);
2566 case OP_ICONV_TO_I8:
2568 case OP_LCONV_TO_I8:
2570 ia64_sxt4 (code, ins->dreg, ins->sreg1);
2572 case OP_LCONV_TO_U8:
2574 ia64_zxt4 (code, ins->dreg, ins->sreg1);
2581 double d = *(double *)ins->inst_p0;
2583 if ((d == 0.0) && (mono_signbit (d) == 0))
2584 ia64_fmov (code, ins->dreg, 0);
2586 ia64_fmov (code, ins->dreg, 1);
2588 add_patch_info (cfg, code, MONO_PATCH_INFO_R8, ins->inst_p0);
2589 ia64_movl (code, GP_SCRATCH_REG, 0);
2590 ia64_ldfd (code, ins->dreg, GP_SCRATCH_REG);
2595 float f = *(float *)ins->inst_p0;
2597 if ((f == 0.0) && (mono_signbit (f) == 0))
2598 ia64_fmov (code, ins->dreg, 0);
2600 ia64_fmov (code, ins->dreg, 1);
2602 add_patch_info (cfg, code, MONO_PATCH_INFO_R4, ins->inst_p0);
2603 ia64_movl (code, GP_SCRATCH_REG, 0);
2604 ia64_ldfs (code, ins->dreg, GP_SCRATCH_REG);
2609 ia64_fmov (code, ins->dreg, ins->sreg1);
2611 case OP_STORER8_MEMBASE_REG:
2612 if (ins->inst_offset != 0) {
2613 /* This is generated by local regalloc */
2614 if (ia64_is_imm14 (ins->inst_offset)) {
2615 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_destbasereg);
2617 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2618 ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_destbasereg);
2620 ins->inst_destbasereg = GP_SCRATCH_REG;
2622 ia64_stfd_hint (code, ins->inst_destbasereg, ins->sreg1, 0);
2624 case OP_STORER4_MEMBASE_REG:
2625 ia64_fnorm_s_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2626 ia64_stfs_hint (code, ins->inst_destbasereg, FP_SCRATCH_REG, 0);
2628 case OP_LOADR8_MEMBASE:
2629 if (ins->inst_offset != 0) {
2630 /* This is generated by local regalloc */
2631 if (ia64_is_imm14 (ins->inst_offset)) {
2632 ia64_adds_imm (code, GP_SCRATCH_REG, ins->inst_offset, ins->inst_basereg);
2634 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2635 ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, ins->inst_basereg);
2637 ins->inst_basereg = GP_SCRATCH_REG;
2639 ia64_ldfd (code, ins->dreg, ins->inst_basereg);
2641 case OP_LOADR4_MEMBASE:
2642 ia64_ldfs (code, ins->dreg, ins->inst_basereg);
2643 ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2645 case OP_ICONV_TO_R4:
2646 case OP_LCONV_TO_R4:
2647 ia64_setf_sig (code, ins->dreg, ins->sreg1);
2648 ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2649 ia64_fnorm_s_sf (code, ins->dreg, ins->dreg, 0);
2651 case OP_ICONV_TO_R8:
2652 case OP_LCONV_TO_R8:
2653 ia64_setf_sig (code, ins->dreg, ins->sreg1);
2654 ia64_fcvt_xf (code, ins->dreg, ins->dreg);
2655 ia64_fnorm_d_sf (code, ins->dreg, ins->dreg, 0);
2657 case OP_FCONV_TO_R4:
2658 ia64_fnorm_s_sf (code, ins->dreg, ins->sreg1, 0);
2660 case OP_FCONV_TO_I8:
2662 ia64_fcvt_fx_trunc_sf (code, FP_SCRATCH_REG, ins->sreg1, 0);
2663 ia64_getf_sig (code, ins->dreg, FP_SCRATCH_REG);
2666 ia64_fma_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2669 ia64_fms_d_sf (code, ins->dreg, ins->sreg1, 1, ins->sreg2, 0);
2672 ia64_fma_d_sf (code, ins->dreg, ins->sreg1, ins->sreg2, 0, 0);
2675 ia64_fmerge_ns (code, ins->dreg, ins->sreg1, ins->sreg1);
2679 ia64_fclass_m (code, 6, 7, ins->sreg1, 0x080);
2680 emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2682 ia64_fclass_m (code, 6, 7, ins->sreg1, 0x040);
2683 emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2684 /* Positive infinity */
2685 ia64_fclass_m (code, 6, 7, ins->sreg1, 0x021);
2686 emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2687 /* Negative infinity */
2688 ia64_fclass_m (code, 6, 7, ins->sreg1, 0x022);
2689 emit_cond_system_exception (cfg, code, "ArithmeticException", 6);
2694 /* ensure ins->sreg1 is not NULL */
2695 /* Can't use ld8 as this could be a vtype address */
2696 ia64_ld1 (code, GP_SCRATCH_REG, ins->sreg1);
2699 ia64_adds_imm (code, GP_SCRATCH_REG, cfg->sig_cookie, cfg->frame_reg);
2700 ia64_st8 (code, ins->sreg1, GP_SCRATCH_REG);
2708 call = (MonoCallInst*)ins;
2710 if (ins->flags & MONO_INST_HAS_METHOD)
2711 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2713 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2715 code = emit_move_return_value (cfg, ins, code);
2723 case OP_VOIDCALL_REG: {
2724 MonoCallInst *call = (MonoCallInst*)ins;
2729 * mono_arch_find_this_arg () needs to find the this argument in a global
2732 cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2733 out_reg = cfg->arch.reg_out0;
2734 if (cinfo->ret.storage == ArgValuetypeAddrInIReg)
2736 ia64_mov (code, IA64_R10, out_reg);
2739 ia64_mov (code, IA64_R8, ins->sreg1);
2740 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, IA64_R8, 8);
2741 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2742 ia64_ld8 (code, IA64_GP, IA64_R8);
2743 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2745 code = emit_move_return_value (cfg, ins, code);
2748 case OP_FCALL_MEMBASE:
2749 case OP_LCALL_MEMBASE:
2750 case OP_VCALL_MEMBASE:
2751 case OP_VCALL2_MEMBASE:
2752 case OP_VOIDCALL_MEMBASE:
2753 case OP_CALL_MEMBASE: {
2754 MonoCallInst *call = (MonoCallInst*)ins;
2758 ia64_mov (code, IA64_R11, ins->sreg1);
2759 if (ia64_is_imm14 (ins->inst_offset))
2760 ia64_adds_imm (code, IA64_R8, ins->inst_offset, ins->sreg1);
2762 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
2763 ia64_add (code, IA64_R8, GP_SCRATCH_REG, ins->sreg1);
2766 if (call->method && ins->inst_offset < 0) {
2768 * This is a possible IMT call so save the IMT method in a global
2769 * register where mono_arch_find_imt_method () and its friends can
2772 ia64_movl (code, IA64_R9, call->method);
2776 * mono_arch_find_this_arg () needs to find the this argument in a global
2779 cinfo = get_call_info (cfg, cfg->mempool, call->signature, FALSE);
2780 out_reg = cfg->arch.reg_out0;
2781 if (cinfo->ret.storage == ArgValuetypeAddrInIReg)
2783 ia64_mov (code, IA64_R10, out_reg);
2785 ia64_ld8 (code, GP_SCRATCH_REG, IA64_R8);
2787 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2789 ia64_br_call_reg (code, IA64_B0, IA64_B6);
2791 code = emit_move_return_value (cfg, ins, code);
2796 * Keep in sync with the code in emit_epilog.
2799 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2802 g_assert (!cfg->method->save_lmf);
2804 /* Load arguments into their original registers */
2805 code = emit_load_volatile_arguments (cfg, code);
2807 if (cfg->arch.stack_alloc_size) {
2808 if (cfg->arch.omit_fp) {
2809 if (ia64_is_imm14 (cfg->arch.stack_alloc_size))
2810 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
2812 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
2813 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
2817 ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
2819 ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
2820 ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
2822 add_patch_info (cfg, code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2823 ia64_movl (code, GP_SCRATCH_REG, 0);
2824 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
2825 ia64_br_cond_reg (code, IA64_B6);
2830 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, mono_break);
2836 /* FIXME: Sigaltstack support */
2838 /* keep alignment */
2839 ia64_adds_imm (code, GP_SCRATCH_REG, MONO_ARCH_LOCALLOC_ALIGNMENT - 1, ins->sreg1);
2840 ia64_movl (code, GP_SCRATCH_REG2, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
2841 ia64_and (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2843 ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2845 ia64_mov (code, ins->dreg, IA64_SP);
2847 /* An area at sp is reserved by the ABI for parameter passing */
2848 abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_LOCALLOC_ALIGNMENT);
2849 if (ia64_is_adds_imm (abi_offset))
2850 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2852 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2853 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2856 if (ins->flags & MONO_INST_INIT) {
2858 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2860 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2863 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2864 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2865 ia64_br_cond_pred (code, 8, -2);
2867 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2869 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2874 case OP_LOCALLOC_IMM: {
2877 /* FIXME: Sigaltstack support */
2879 gssize size = ins->inst_imm;
2880 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
2882 if (ia64_is_adds_imm (size))
2883 ia64_adds_imm (code, GP_SCRATCH_REG, size, IA64_R0);
2885 ia64_movl (code, GP_SCRATCH_REG, size);
2887 ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
2888 ia64_mov (code, ins->dreg, IA64_SP);
2890 /* An area at sp is reserved by the ABI for parameter passing */
2891 abi_offset = - ALIGN_TO (cfg->param_area + 16, MONO_ARCH_FRAME_ALIGNMENT);
2892 if (ia64_is_adds_imm (abi_offset))
2893 ia64_adds_imm (code, IA64_SP, abi_offset, IA64_SP);
2895 ia64_movl (code, GP_SCRATCH_REG2, abi_offset);
2896 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG2);
2899 if (ins->flags & MONO_INST_INIT) {
2901 ia64_add (code, GP_SCRATCH_REG2, ins->dreg, GP_SCRATCH_REG);
2903 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2906 ia64_st8_inc_imm_hint (code, ins->dreg, IA64_R0, 8, 0);
2907 ia64_cmp_lt (code, 8, 9, ins->dreg, GP_SCRATCH_REG2);
2908 ia64_br_cond_pred (code, 8, -2);
2910 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
2912 ia64_sub (code, ins->dreg, GP_SCRATCH_REG2, GP_SCRATCH_REG);
2918 ia64_adds_imm (code, ins->dreg, ins->inst_offset, IA64_TP);
2919 ia64_ld8 (code, ins->dreg, ins->dreg);
2922 /* Synchronization */
2923 case OP_MEMORY_BARRIER:
2926 case OP_ATOMIC_ADD_IMM_NEW_I4:
2927 g_assert (ins->inst_offset == 0);
2928 ia64_fetchadd4_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2929 ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2931 case OP_ATOMIC_ADD_IMM_NEW_I8:
2932 g_assert (ins->inst_offset == 0);
2933 ia64_fetchadd8_acq_hint (code, ins->dreg, ins->inst_basereg, ins->inst_imm, 0);
2934 ia64_adds_imm (code, ins->dreg, ins->inst_imm, ins->dreg);
2936 case OP_ATOMIC_EXCHANGE_I4:
2937 ia64_xchg4_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2938 ia64_sxt4 (code, ins->dreg, ins->dreg);
2940 case OP_ATOMIC_EXCHANGE_I8:
2941 ia64_xchg8_hint (code, ins->dreg, ins->inst_basereg, ins->sreg2, 0);
2943 case OP_ATOMIC_ADD_NEW_I4: {
2944 guint8 *label, *buf;
2946 /* From libatomic_ops */
2949 ia64_begin_bundle (code);
2950 label = code.buf + code.nins;
2951 ia64_ld4_acq (code, GP_SCRATCH_REG, ins->sreg1);
2952 ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2953 ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2954 ia64_cmpxchg4_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2955 ia64_cmp4_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2956 buf = code.buf + code.nins;
2957 ia64_br_cond_pred (code, 7, 0);
2958 ia64_begin_bundle (code);
2959 ia64_patch (buf, label);
2960 ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2963 case OP_ATOMIC_ADD_NEW_I8: {
2964 guint8 *label, *buf;
2966 /* From libatomic_ops */
2969 ia64_begin_bundle (code);
2970 label = code.buf + code.nins;
2971 ia64_ld8_acq (code, GP_SCRATCH_REG, ins->sreg1);
2972 ia64_add (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, ins->sreg2);
2973 ia64_mov_to_ar_m (code, IA64_CCV, GP_SCRATCH_REG);
2974 ia64_cmpxchg8_acq_hint (code, GP_SCRATCH_REG2, ins->sreg1, GP_SCRATCH_REG2, 0);
2975 ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, GP_SCRATCH_REG2);
2976 buf = code.buf + code.nins;
2977 ia64_br_cond_pred (code, 7, 0);
2978 ia64_begin_bundle (code);
2979 ia64_patch (buf, label);
2980 ia64_add (code, ins->dreg, GP_SCRATCH_REG, ins->sreg2);
2984 /* Exception handling */
2985 case OP_CALL_HANDLER:
2987 * Using a call instruction would mess up the register stack, so
2988 * save the return address to a register and use a
2991 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
2992 ia64_mov (code, IA64_R15, IA64_R0);
2993 ia64_mov_from_ip (code, GP_SCRATCH_REG);
2994 /* Add the length of OP_CALL_HANDLER */
2995 ia64_adds_imm (code, GP_SCRATCH_REG, 5 * 16, GP_SCRATCH_REG);
2996 add_patch_info (cfg, code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
2997 ia64_movl (code, GP_SCRATCH_REG2, 0);
2998 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
2999 ia64_br_cond_reg (code, IA64_B6);
3001 //mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3002 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3004 case OP_START_HANDLER: {
3006 * We receive the return address in GP_SCRATCH_REG.
3008 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3011 * R15 determines our caller. It is used since it is writable using
3013 * R15 == 0 means we are called by OP_CALL_HANDLER or via resume_context ()
3014 * R15 != 0 means we are called by call_filter ().
3016 ia64_codegen_set_one_ins_per_bundle (code, TRUE);
3017 ia64_cmp_eq (code, 6, 7, IA64_R15, IA64_R0);
3019 ia64_br_cond_pred (code, 6, 6);
3022 * Called by call_filter:
3023 * Allocate a new stack frame, and set the fp register from the
3024 * value passed in by the caller.
3025 * We allocate a similar frame as is done by the prolog, so
3026 * if an exception is thrown while executing the filter, the
3027 * unwinder can unwind through the filter frame using the unwind
3028 * info for the prolog.
3030 ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3031 ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3032 ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3033 ia64_mov (code, cfg->frame_reg, IA64_R15);
3034 /* Signal to endfilter that we are called by call_filter */
3035 ia64_mov (code, GP_SCRATCH_REG, IA64_R0);
3037 /* Branch target: */
3038 if (ia64_is_imm14 (spvar->inst_offset))
3039 ia64_adds_imm (code, GP_SCRATCH_REG2, spvar->inst_offset, cfg->frame_reg);
3041 ia64_movl (code, GP_SCRATCH_REG2, spvar->inst_offset);
3042 ia64_add (code, GP_SCRATCH_REG2, cfg->frame_reg, GP_SCRATCH_REG2);
3045 /* Save the return address */
3046 ia64_st8_hint (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 0);
3047 ia64_codegen_set_one_ins_per_bundle (code, FALSE);
3052 case OP_ENDFILTER: {
3053 /* FIXME: Return the value in ENDFILTER */
3054 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3056 /* Load the return address */
3057 if (ia64_is_imm14 (spvar->inst_offset)) {
3058 ia64_adds_imm (code, GP_SCRATCH_REG, spvar->inst_offset, cfg->frame_reg);
3060 ia64_movl (code, GP_SCRATCH_REG, spvar->inst_offset);
3061 ia64_add (code, GP_SCRATCH_REG, cfg->frame_reg, GP_SCRATCH_REG);
3063 ia64_ld8_hint (code, GP_SCRATCH_REG, GP_SCRATCH_REG, 0);
3066 ia64_cmp_eq (code, 6, 7, GP_SCRATCH_REG, IA64_R0);
3067 ia64_br_cond_pred (code, 7, 4);
3069 /* Called by call_filter */
3071 ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
3072 ia64_mov_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
3073 ia64_br_ret_reg (code, IA64_B0);
3075 /* Called by CALL_HANDLER */
3076 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
3077 ia64_br_cond_reg (code, IA64_B6);
3081 ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3082 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3083 (gpointer)"mono_arch_throw_exception");
3086 * This might be the last instruction in the method, so add a dummy
3087 * instruction so the unwinder will work.
3089 ia64_break_i (code, 0);
3092 ia64_mov (code, cfg->arch.reg_out0, ins->sreg1);
3093 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3094 (gpointer)"mono_arch_rethrow_exception");
3096 ia64_break_i (code, 0);
3100 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3101 g_assert_not_reached ();
3104 if ((code.buf - cfg->native_code - offset) > max_len) {
3105 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3106 mono_inst_name (ins->opcode), max_len, code.buf - cfg->native_code - offset);
3107 g_assert_not_reached ();
3113 last_offset = offset;
3116 ia64_codegen_close (code);
3118 cfg->code_len = code.buf - cfg->native_code;
3122 mono_arch_register_lowlevel_calls (void)
3126 static Ia64InsType ins_types_in_template [32][3] = {
3127 {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3128 {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3129 {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3130 {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_I},
3131 {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3132 {IA64_INS_TYPE_M, IA64_INS_TYPE_LX, IA64_INS_TYPE_LX},
3135 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3136 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3137 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3138 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_I},
3139 {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3140 {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_I},
3141 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3142 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_F},
3143 {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3144 {IA64_INS_TYPE_M, IA64_INS_TYPE_I, IA64_INS_TYPE_B},
3145 {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3146 {IA64_INS_TYPE_M, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3149 {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3150 {IA64_INS_TYPE_B, IA64_INS_TYPE_B, IA64_INS_TYPE_B},
3151 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3152 {IA64_INS_TYPE_M, IA64_INS_TYPE_M, IA64_INS_TYPE_B},
3155 {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3156 {IA64_INS_TYPE_M, IA64_INS_TYPE_F, IA64_INS_TYPE_B},
3161 static gboolean stops_in_template [32][3] = {
3162 { FALSE, FALSE, FALSE },
3163 { FALSE, FALSE, TRUE },
3164 { FALSE, TRUE, FALSE },
3165 { FALSE, TRUE, TRUE },
3166 { FALSE, FALSE, FALSE },
3167 { FALSE, FALSE, TRUE },
3168 { FALSE, FALSE, FALSE },
3169 { FALSE, FALSE, FALSE },
3171 { FALSE, FALSE, FALSE },
3172 { FALSE, FALSE, TRUE },
3173 { TRUE, FALSE, FALSE },
3174 { TRUE, FALSE, TRUE },
3175 { FALSE, FALSE, FALSE },
3176 { FALSE, FALSE, TRUE },
3177 { FALSE, FALSE, FALSE },
3178 { FALSE, FALSE, TRUE },
3180 { FALSE, FALSE, FALSE },
3181 { FALSE, FALSE, TRUE },
3182 { FALSE, FALSE, FALSE },
3183 { FALSE, FALSE, TRUE },
3184 { FALSE, FALSE, FALSE },
3185 { FALSE, FALSE, FALSE },
3186 { FALSE, FALSE, FALSE },
3187 { FALSE, FALSE, TRUE },
3189 { FALSE, FALSE, FALSE },
3190 { FALSE, FALSE, TRUE },
3191 { FALSE, FALSE, FALSE },
3192 { FALSE, FALSE, FALSE },
3193 { FALSE, FALSE, FALSE },
3194 { FALSE, FALSE, TRUE },
3195 { FALSE, FALSE, FALSE },
3196 { FALSE, FALSE, FALSE }
3199 static int last_stop_in_template [32] = {
3200 -1, 2, 1, 2, -1, 2, -1, -1,
3201 -1, 2, 0, 2, -1, 2, -1, 2,
3202 -1, 2, -1, 2, -1, -1, -1, 2,
3203 -1, 2, -1, -1, -1, 2, -1, -1
3206 static guint64 nops_for_ins_types [6] = {
3215 #define ITYPE_MATCH(itype1, itype2) (((itype1) == (itype2)) || (((itype2) == IA64_INS_TYPE_A) && (((itype1) == IA64_INS_TYPE_I) || ((itype1) == IA64_INS_TYPE_M))))
3222 #define DEBUG_INS_SCHED(a) do { a; } while (0)
3224 #define DEBUG_INS_SCHED(a)
3228 ia64_analyze_deps (Ia64CodegenState *code, int *deps_start, int *stops)
3230 int i, pos, ins_index, current_deps_start, current_ins_start, reg;
3231 guint8 *deps = code->dep_info;
3232 gboolean need_stop, no_stop;
3234 for (i = 0; i < code->nins; ++i)
3238 current_deps_start = 0;
3239 current_ins_start = 0;
3240 deps_start [ins_index] = current_ins_start;
3243 DEBUG_INS_SCHED (printf ("BEGIN.\n"));
3244 while (pos < code->dep_info_pos) {
3246 switch (deps [pos]) {
3247 case IA64_END_OF_INS:
3249 current_ins_start = pos + 2;
3250 deps_start [ins_index] = current_ins_start;
3252 DEBUG_INS_SCHED (printf ("(%d) END INS.\n", ins_index - 1));
3257 reg = deps [pos + 1];
3259 DEBUG_INS_SCHED (printf ("READ GR: %d\n", reg));
3260 for (i = current_deps_start; i < current_ins_start; i += 2)
3261 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3265 reg = code->dep_info [pos + 1];
3267 DEBUG_INS_SCHED (printf ("WRITE GR: %d\n", reg));
3268 for (i = current_deps_start; i < current_ins_start; i += 2)
3269 if (deps [i] == IA64_WRITE_GR && deps [i + 1] == reg)
3273 reg = deps [pos + 1];
3275 DEBUG_INS_SCHED (printf ("READ PR: %d\n", reg));
3276 for (i = current_deps_start; i < current_ins_start; i += 2)
3277 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3280 case IA64_READ_PR_BRANCH:
3281 reg = deps [pos + 1];
3283 /* Writes to prs by non-float instructions are visible to branches */
3284 DEBUG_INS_SCHED (printf ("READ PR BRANCH: %d\n", reg));
3285 for (i = current_deps_start; i < current_ins_start; i += 2)
3286 if (deps [i] == IA64_WRITE_PR_FLOAT && deps [i + 1] == reg)
3290 reg = code->dep_info [pos + 1];
3292 DEBUG_INS_SCHED (printf ("WRITE PR: %d\n", reg));
3293 for (i = current_deps_start; i < current_ins_start; i += 2)
3294 if (((deps [i] == IA64_WRITE_PR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3297 case IA64_WRITE_PR_FLOAT:
3298 reg = code->dep_info [pos + 1];
3300 DEBUG_INS_SCHED (printf ("WRITE PR FP: %d\n", reg));
3301 for (i = current_deps_start; i < current_ins_start; i += 2)
3302 if (((deps [i] == IA64_WRITE_GR) || (deps [i] == IA64_WRITE_PR_FLOAT)) && deps [i + 1] == reg)
3306 reg = deps [pos + 1];
3308 DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3309 for (i = current_deps_start; i < current_ins_start; i += 2)
3310 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3314 reg = code->dep_info [pos + 1];
3316 DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3317 for (i = current_deps_start; i < current_ins_start; i += 2)
3318 if (deps [i] == IA64_WRITE_BR && deps [i + 1] == reg)
3321 case IA64_READ_BR_BRANCH:
3322 reg = deps [pos + 1];
3324 /* Writes to brs are visible to branches */
3325 DEBUG_INS_SCHED (printf ("READ BR BRACH: %d\n", reg));
3328 reg = deps [pos + 1];
3330 DEBUG_INS_SCHED (printf ("READ BR: %d\n", reg));
3331 for (i = current_deps_start; i < current_ins_start; i += 2)
3332 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3336 reg = code->dep_info [pos + 1];
3338 DEBUG_INS_SCHED (printf ("WRITE BR: %d\n", reg));
3339 for (i = current_deps_start; i < current_ins_start; i += 2)
3340 if (deps [i] == IA64_WRITE_FR && deps [i + 1] == reg)
3344 reg = deps [pos + 1];
3346 DEBUG_INS_SCHED (printf ("READ AR: %d\n", reg));
3347 for (i = current_deps_start; i < current_ins_start; i += 2)
3348 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3352 reg = code->dep_info [pos + 1];
3354 DEBUG_INS_SCHED (printf ("WRITE AR: %d\n", reg));
3355 for (i = current_deps_start; i < current_ins_start; i += 2)
3356 if (deps [i] == IA64_WRITE_AR && deps [i + 1] == reg)
3361 * Explicitly indicate that a stop is not required. Useful for
3362 * example when two predicated instructions with negated predicates
3363 * write the same registers.
3368 g_assert_not_reached ();
3372 if (need_stop && !no_stop) {
3373 g_assert (ins_index > 0);
3374 stops [ins_index - 1] = 1;
3376 DEBUG_INS_SCHED (printf ("STOP\n"));
3377 current_deps_start = current_ins_start;
3379 /* Skip remaining deps for this instruction */
3380 while (deps [pos] != IA64_END_OF_INS)
3385 if (code->nins > 0) {
3386 /* No dependency info for the last instruction */
3387 stops [code->nins - 1] = 1;
3390 deps_start [code->nins] = code->dep_info_pos;
3394 ia64_real_emit_bundle (Ia64CodegenState *code, int *deps_start, int *stops, int n, guint64 template, guint64 ins1, guint64 ins2, guint64 ins3, guint8 nops)
3396 int stop_pos, i, deps_to_shift, dep_shift;
3398 g_assert (n <= code->nins);
3400 // if (n > 1) printf ("FOUND: %ld.\n", template);
3402 ia64_emit_bundle_template (code, template, ins1, ins2, ins3);
3404 stop_pos = last_stop_in_template [template] + 1;
3408 /* Compute the number of 'real' instructions before the stop */
3409 deps_to_shift = stop_pos;
3410 if (stop_pos >= 3 && (nops & (1 << 2)))
3412 if (stop_pos >= 2 && (nops & (1 << 1)))
3414 if (stop_pos >= 1 && (nops & (1 << 0)))
3418 * We have to keep some dependencies whose instructions have been shifted
3419 * out of the buffer. So nullify the end_of_ins markers in the dependency
3422 for (i = deps_start [deps_to_shift]; i < deps_start [n]; i += 2)
3423 if (code->dep_info [i] == IA64_END_OF_INS)
3424 code->dep_info [i] = IA64_NONE;
3426 g_assert (deps_start [deps_to_shift] <= code->dep_info_pos);
3427 memcpy (code->dep_info, &code->dep_info [deps_start [deps_to_shift]], code->dep_info_pos - deps_start [deps_to_shift]);
3428 code->dep_info_pos = code->dep_info_pos - deps_start [deps_to_shift];
3430 dep_shift = deps_start [deps_to_shift];
3431 for (i = 0; i < code->nins + 1 - n; ++i)
3432 deps_start [i] = deps_start [n + i] - dep_shift;
3434 /* Determine the exact positions of instructions with unwind ops */
3435 if (code->unw_op_count) {
3437 int curr_ins, curr_ins_pos;
3440 curr_ins_pos = ((code->buf - code->region_start - 16) / 16) * 3;
3441 for (i = 0; i < 3; ++i) {
3442 if (! (nops & (1 << i))) {
3443 ins_pos [curr_ins] = curr_ins_pos + i;
3448 for (i = code->unw_op_pos; i < code->unw_op_count; ++i) {
3449 if (code->unw_ops_pos [i] < n) {
3450 code->unw_ops [i].when = ins_pos [code->unw_ops_pos [i]];
3451 //printf ("UNW-OP: %d -> %d\n", code->unw_ops_pos [i], code->unw_ops [i].when);
3454 if (code->unw_op_pos < code->unw_op_count)
3455 code->unw_op_pos += n;
3458 if (n == code->nins) {
3463 memcpy (&code->instructions [0], &code->instructions [n], (code->nins - n) * sizeof (guint64));
3464 memcpy (&code->itypes [0], &code->itypes [n], (code->nins - n) * sizeof (int));
3465 memcpy (&stops [0], &stops [n], (code->nins - n) * sizeof (int));
3471 ia64_emit_bundle (Ia64CodegenState *code, gboolean flush)
3473 int i, ins_type, template, nins_to_emit;
3474 int deps_start [16];
3479 * We implement a simple scheduler which tries to put three instructions
3480 * per bundle, then two, then one.
3482 ia64_analyze_deps (code, deps_start, stops);
3484 if ((code->nins >= 3) && !code->one_ins_per_bundle) {
3485 /* Find a suitable template */
3486 for (template = 0; template < 32; ++template) {
3487 if (stops_in_template [template][0] != stops [0] ||
3488 stops_in_template [template][1] != stops [1] ||
3489 stops_in_template [template][2] != stops [2])
3493 for (i = 0; i < 3; ++i) {
3494 ins_type = ins_types_in_template [template][i];
3495 switch (code->itypes [i]) {
3496 case IA64_INS_TYPE_A:
3497 found &= (ins_type == IA64_INS_TYPE_I) || (ins_type == IA64_INS_TYPE_M);
3500 found &= (ins_type == code->itypes [i]);
3506 found = debug_ins_sched ();
3509 ia64_real_emit_bundle (code, deps_start, stops, 3, template, code->instructions [0], code->instructions [1], code->instructions [2], 0);
3515 if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3516 /* Wait for more instructions */
3519 /* If it didn't work out, try putting two instructions into one bundle */
3520 if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3521 /* Try a nop at the end */
3522 for (template = 0; template < 32; ++template) {
3523 if (stops_in_template [template][0] != stops [0] ||
3524 ((stops_in_template [template][1] != stops [1]) &&
3525 (stops_in_template [template][2] != stops [1])))
3529 if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3530 !ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [1]))
3533 if (!debug_ins_sched ())
3536 ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], code->instructions [1], nops_for_ins_types [ins_types_in_template [template][2]], 1 << 2);
3541 if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3542 /* Wait for more instructions */
3545 if ((code->nins >= 2) && !code->one_ins_per_bundle) {
3546 /* Try a nop in the middle */
3547 for (template = 0; template < 32; ++template) {
3548 if (((stops_in_template [template][0] != stops [0]) &&
3549 (stops_in_template [template][1] != stops [0])) ||
3550 stops_in_template [template][2] != stops [1])
3553 if (!ITYPE_MATCH (ins_types_in_template [template][0], code->itypes [0]) ||
3554 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3557 if (!debug_ins_sched ())
3560 ia64_real_emit_bundle (code, deps_start, stops, 2, template, code->instructions [0], nops_for_ins_types [ins_types_in_template [template][1]], code->instructions [1], 1 << 1);
3565 if ((code->nins >= 2) && flush && !code->one_ins_per_bundle) {
3566 /* Try a nop at the beginning */
3567 for (template = 0; template < 32; ++template) {
3568 if ((stops_in_template [template][1] != stops [0]) ||
3569 (stops_in_template [template][2] != stops [1]))
3572 if (!ITYPE_MATCH (ins_types_in_template [template][1], code->itypes [0]) ||
3573 !ITYPE_MATCH (ins_types_in_template [template][2], code->itypes [1]))
3576 if (!debug_ins_sched ())
3579 ia64_real_emit_bundle (code, deps_start, stops, 2, template, nops_for_ins_types [ins_types_in_template [template][0]], code->instructions [0], code->instructions [1], 1 << 0);
3584 if (code->nins < IA64_INS_BUFFER_SIZE && !flush)
3585 /* Wait for more instructions */
3589 nins_to_emit = code->nins;
3593 while (nins_to_emit > 0) {
3594 if (!debug_ins_sched ())
3596 switch (code->itypes [0]) {
3597 case IA64_INS_TYPE_A:
3599 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3601 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3603 case IA64_INS_TYPE_I:
3605 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3607 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3609 case IA64_INS_TYPE_M:
3611 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIIS, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3613 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MII, code->instructions [0], IA64_NOP_I, IA64_NOP_I, 0);
3615 case IA64_INS_TYPE_B:
3617 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIBS, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3619 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MIB, IA64_NOP_M, IA64_NOP_I, code->instructions [0], 0);
3621 case IA64_INS_TYPE_F:
3623 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFIS, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3625 ia64_real_emit_bundle (code, deps_start, stops, 1, IA64_TEMPLATE_MFI, IA64_NOP_M, code->instructions [0], IA64_NOP_I, 0);
3627 case IA64_INS_TYPE_LX:
3628 if (stops [0] || stops [1])
3629 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLXS, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3631 ia64_real_emit_bundle (code, deps_start, stops, 2, IA64_TEMPLATE_MLX, IA64_NOP_M, code->instructions [0], code->instructions [1], 0);
3635 g_assert_not_reached ();
3641 unw_dyn_region_info_t*
3642 mono_ia64_create_unwind_region (Ia64CodegenState *code)
3644 unw_dyn_region_info_t *r;
3646 g_assert (code->nins == 0);
3647 r = g_malloc0 (_U_dyn_region_info_size (code->unw_op_count));
3648 memcpy (&r->op, &code->unw_ops, sizeof (unw_dyn_op_t) * code->unw_op_count);
3649 r->op_count = code->unw_op_count;
3650 r->insn_count = ((code->buf - code->region_start) >> 4) * 3;
3651 code->unw_op_count = 0;
3652 code->unw_op_pos = 0;
3653 code->region_start = code->buf;
3659 ia64_patch (unsigned char* code, gpointer target)
3662 guint64 instructions [3];
3663 guint8 gen_buf [16];
3664 Ia64CodegenState gen;
3669 * code encodes both the position inside the buffer and code.nins when
3670 * the instruction was emitted.
3672 ins_to_skip = (guint64)code % 16;
3673 code = (unsigned char*)((guint64)code & ~15);
3676 * Search for the first instruction which is 'patchable', skipping
3677 * ins_to_skip instructions.
3682 template = ia64_bundle_template (code);
3683 instructions [0] = ia64_bundle_ins1 (code);
3684 instructions [1] = ia64_bundle_ins2 (code);
3685 instructions [2] = ia64_bundle_ins3 (code);
3687 ia64_codegen_init (gen, gen_buf);
3690 for (i = 0; i < 3; ++i) {
3691 guint64 ins = instructions [i];
3692 int opcode = ia64_ins_opcode (ins);
3694 if (ins == nops_for_ins_types [ins_types_in_template [template][i]])
3702 switch (ins_types_in_template [template][i]) {
3703 case IA64_INS_TYPE_A:
3704 case IA64_INS_TYPE_M:
3705 if ((opcode == 8) && (ia64_ins_x2a (ins) == 2) && (ia64_ins_ve (ins) == 0)) {
3707 ia64_adds_imm_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), (guint64)target, ia64_ins_r3 (ins));
3708 instructions [i] = gen.instructions [0];
3714 case IA64_INS_TYPE_B:
3715 if ((opcode == 4) && (ia64_ins_btype (ins) == 0)) {
3717 gint64 disp = ((guint8*)target - code) >> 4;
3720 ia64_br_cond_hint_pred (gen, ia64_ins_qp (ins), disp, 0, 0, 0);
3722 instructions [i] = gen.instructions [0];
3725 else if (opcode == 5) {
3727 gint64 disp = ((guint8*)target - code) >> 4;
3730 ia64_br_call_hint_pred (gen, ia64_ins_qp (ins), ia64_ins_b1 (ins), disp, 0, 0, 0);
3731 instructions [i] = gen.instructions [0];
3737 case IA64_INS_TYPE_LX:
3741 if ((opcode == 6) && (ia64_ins_vc (ins) == 0)) {
3743 ia64_movl_pred (gen, ia64_ins_qp (ins), ia64_ins_r1 (ins), target);
3744 instructions [1] = gen.instructions [0];
3745 instructions [2] = gen.instructions [1];
3758 ia64_codegen_init (gen, code);
3759 ia64_emit_bundle_template (&gen, template, instructions [0], instructions [1], instructions [2]);
3769 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3771 MonoJumpInfo *patch_info;
3773 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3774 unsigned char *ip = patch_info->ip.i + code;
3775 const unsigned char *target;
3777 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3779 if (patch_info->type == MONO_PATCH_INFO_NONE)
3781 if (mono_compile_aot) {
3785 ia64_patch (ip, (gpointer)target);
3790 mono_arch_emit_prolog (MonoCompile *cfg)
3792 MonoMethod *method = cfg->method;
3793 MonoMethodSignature *sig;
3795 int alloc_size, pos, i;
3796 Ia64CodegenState code;
3799 sig = mono_method_signature (method);
3802 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
3804 cfg->code_size = MAX (cfg->header->code_size * 4, 512);
3806 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3807 cfg->code_size += 1024;
3808 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3809 cfg->code_size += 1024;
3811 cfg->native_code = g_malloc (cfg->code_size);
3813 ia64_codegen_init (code, cfg->native_code);
3815 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
3816 if (cfg->param_area)
3817 alloc_size += cfg->param_area;
3821 alloc_size = ALIGN_TO (alloc_size, MONO_ARCH_FRAME_ALIGNMENT);
3823 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
3824 /* Force sp to be saved/restored */
3825 alloc_size += MONO_ARCH_FRAME_ALIGNMENT;
3827 cfg->arch.stack_alloc_size = alloc_size;
3831 if (method->save_lmf) {
3832 /* No LMF on IA64 */
3837 ia64_unw_save_reg (code, UNW_IA64_AR_PFS, UNW_IA64_GR + cfg->arch.reg_saved_ar_pfs);
3838 ia64_alloc (code, cfg->arch.reg_saved_ar_pfs, cfg->arch.reg_local0 - cfg->arch.reg_in0, cfg->arch.reg_out0 - cfg->arch.reg_local0, cfg->arch.n_out_regs, 0);
3839 ia64_unw_save_reg (code, UNW_IA64_RP, UNW_IA64_GR + cfg->arch.reg_saved_b0);
3840 ia64_mov_from_br (code, cfg->arch.reg_saved_b0, IA64_B0);
3842 if ((alloc_size || cinfo->stack_usage) && !cfg->arch.omit_fp) {
3843 ia64_unw_save_reg (code, UNW_IA64_SP, UNW_IA64_GR + cfg->arch.reg_saved_sp);
3844 ia64_mov (code, cfg->arch.reg_saved_sp, IA64_SP);
3845 if (cfg->frame_reg != cfg->arch.reg_saved_sp)
3846 ia64_mov (code, cfg->frame_reg, IA64_SP);
3850 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3851 int pagesize = getpagesize ();
3853 if (alloc_size >= pagesize) {
3854 gint32 remaining_size = alloc_size;
3856 /* Generate stack touching code */
3857 ia64_mov (code, GP_SCRATCH_REG, IA64_SP);
3858 while (remaining_size >= pagesize) {
3859 ia64_movl (code, GP_SCRATCH_REG2, pagesize);
3860 ia64_sub (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3861 ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
3862 remaining_size -= pagesize;
3866 if (ia64_is_imm14 (-alloc_size)) {
3867 if (cfg->arch.omit_fp)
3868 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3869 ia64_adds_imm (code, IA64_SP, (-alloc_size), IA64_SP);
3872 ia64_movl (code, GP_SCRATCH_REG, -alloc_size);
3873 if (cfg->arch.omit_fp)
3874 ia64_unw_add (code, UNW_IA64_SP, (-alloc_size));
3875 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
3879 ia64_begin_bundle (code);
3881 /* Initialize unwind info */
3882 cfg->arch.r_pro = mono_ia64_create_unwind_region (&code);
3884 if (sig->ret->type != MONO_TYPE_VOID) {
3885 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
3886 /* Save volatile arguments to the stack */
3891 /* Keep this in sync with emit_load_volatile_arguments */
3892 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3893 ArgInfo *ainfo = cinfo->args + i;
3894 gint32 stack_offset;
3897 inst = cfg->args [i];
3899 if (sig->hasthis && (i == 0))
3900 arg_type = &mono_defaults.object_class->byval_arg;
3902 arg_type = sig->params [i - sig->hasthis];
3904 arg_type = mono_type_get_underlying_type (arg_type);
3906 stack_offset = ainfo->offset + ARGS_OFFSET;
3909 * FIXME: Native code might pass non register sized integers
3910 * without initializing the upper bits.
3912 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED && !arg_type->byref && ainfo->storage == ArgInIReg) {
3913 int reg = cfg->arch.reg_in0 + ainfo->reg;
3915 switch (mono_type_to_load_membase (cfg, arg_type)) {
3916 case OP_LOADI1_MEMBASE:
3917 ia64_sxt1 (code, reg, reg);
3919 case OP_LOADU1_MEMBASE:
3920 ia64_zxt1 (code, reg, reg);
3922 case OP_LOADI2_MEMBASE:
3923 ia64_sxt2 (code, reg, reg);
3925 case OP_LOADU2_MEMBASE:
3926 ia64_zxt2 (code, reg, reg);
3933 /* Save volatile arguments to the stack */
3934 if (inst->opcode != OP_REGVAR) {
3935 switch (ainfo->storage) {
3938 case ArgInFloatRegR4:
3939 g_assert (inst->opcode == OP_REGOFFSET);
3940 if (ia64_is_adds_imm (inst->inst_offset))
3941 ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3943 ia64_movl (code, GP_SCRATCH_REG2, inst->inst_offset);
3944 ia64_add (code, GP_SCRATCH_REG, GP_SCRATCH_REG, GP_SCRATCH_REG2);
3946 if (arg_type->byref)
3947 ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3949 switch (arg_type->type) {
3951 ia64_stfs_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3954 ia64_stfd_hint (code, GP_SCRATCH_REG, ainfo->reg, 0);
3957 ia64_st8_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg, 0);
3965 if (ainfo->nslots != ainfo->nregs)
3968 g_assert (inst->opcode == OP_REGOFFSET);
3969 ia64_adds_imm (code, GP_SCRATCH_REG, inst->inst_offset, inst->inst_basereg);
3970 for (i = 0; i < ainfo->nregs; ++i) {
3971 switch (ainfo->atype) {
3972 case AggregateNormal:
3973 ia64_st8_inc_imm_hint (code, GP_SCRATCH_REG, cfg->arch.reg_in0 + ainfo->reg + i, sizeof (gpointer), 0);
3975 case AggregateSingleHFA:
3976 ia64_stfs_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, 4, 0);
3978 case AggregateDoubleHFA:
3979 ia64_stfd_inc_imm_hint (code, GP_SCRATCH_REG, ainfo->reg + i, sizeof (gpointer), 0);
3987 g_assert_not_reached ();
3991 if (inst->opcode == OP_REGVAR) {
3992 /* Argument allocated to (non-volatile) register */
3993 switch (ainfo->storage) {
3995 if (inst->dreg != cfg->arch.reg_in0 + ainfo->reg)
3996 ia64_mov (code, inst->dreg, cfg->arch.reg_in0 + ainfo->reg);
3999 ia64_adds_imm (code, GP_SCRATCH_REG, 16 + ainfo->offset, cfg->frame_reg);
4000 ia64_ld8 (code, inst->dreg, GP_SCRATCH_REG);
4008 if (method->save_lmf) {
4009 /* No LMF on IA64 */
4012 ia64_codegen_close (code);
4014 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4015 code.buf = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code.buf, TRUE);
4017 cfg->code_len = code.buf - cfg->native_code;
4019 g_assert (cfg->code_len < cfg->code_size);
4021 cfg->arch.prolog_end_offset = cfg->code_len;
4027 mono_arch_emit_epilog (MonoCompile *cfg)
4029 MonoMethod *method = cfg->method;
4031 int max_epilog_size = 16 * 4;
4032 Ia64CodegenState code;
4037 if (mono_jit_trace_calls != NULL)
4038 max_epilog_size += 1024;
4040 cfg->arch.epilog_begin_offset = cfg->code_len;
4042 while (cfg->code_len + max_epilog_size > cfg->code_size) {
4043 cfg->code_size *= 2;
4044 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4045 mono_jit_stats.code_reallocs++;
4048 /* FIXME: Emit unwind info */
4050 buf = cfg->native_code + cfg->code_len;
4052 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4053 buf = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, buf, TRUE);
4055 ia64_codegen_init (code, buf);
4057 /* the code restoring the registers must be kept in sync with OP_JMP */
4060 if (method->save_lmf) {
4061 /* No LMF on IA64 */
4064 /* Load returned vtypes into registers if needed */
4065 cinfo = get_call_info (cfg, cfg->mempool, mono_method_signature (method), FALSE);
4066 ainfo = &cinfo->ret;
4067 switch (ainfo->storage) {
4069 if (ainfo->nslots != ainfo->nregs)
4072 g_assert (cfg->ret->opcode == OP_REGOFFSET);
4073 ia64_adds_imm (code, GP_SCRATCH_REG, cfg->ret->inst_offset, cfg->ret->inst_basereg);
4074 for (i = 0; i < ainfo->nregs; ++i) {
4075 switch (ainfo->atype) {
4076 case AggregateNormal:
4077 ia64_ld8_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4079 case AggregateSingleHFA:
4080 ia64_ldfs_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, 4, 0);
4082 case AggregateDoubleHFA:
4083 ia64_ldfd_inc_imm_hint (code, ainfo->reg + i, GP_SCRATCH_REG, sizeof (gpointer), 0);
4086 g_assert_not_reached ();
4094 ia64_begin_bundle (code);
4096 code.region_start = cfg->native_code;
4098 /* Label the unwind state at the start of the exception throwing region */
4099 //ia64_unw_label_state (code, 1234);
4101 if (cfg->arch.stack_alloc_size) {
4102 if (cfg->arch.omit_fp) {
4103 if (ia64_is_imm14 (cfg->arch.stack_alloc_size)) {
4104 ia64_unw_pop_frames (code, 1);
4105 ia64_adds_imm (code, IA64_SP, (cfg->arch.stack_alloc_size), IA64_SP);
4107 ia64_movl (code, GP_SCRATCH_REG, cfg->arch.stack_alloc_size);
4108 ia64_unw_pop_frames (code, 1);
4109 ia64_add (code, IA64_SP, GP_SCRATCH_REG, IA64_SP);
4113 ia64_unw_pop_frames (code, 1);
4114 ia64_mov (code, IA64_SP, cfg->arch.reg_saved_sp);
4117 ia64_mov_to_ar_i (code, IA64_PFS, cfg->arch.reg_saved_ar_pfs);
4118 ia64_mov_ret_to_br (code, IA64_B0, cfg->arch.reg_saved_b0);
4119 ia64_br_ret_reg (code, IA64_B0);
4121 ia64_codegen_close (code);
4123 cfg->arch.r_epilog = mono_ia64_create_unwind_region (&code);
4124 cfg->arch.r_pro->next = cfg->arch.r_epilog;
4126 cfg->code_len = code.buf - cfg->native_code;
4128 g_assert (cfg->code_len < cfg->code_size);
4132 mono_arch_emit_exceptions (MonoCompile *cfg)
4134 MonoJumpInfo *patch_info;
4136 Ia64CodegenState code;
4137 gboolean empty = TRUE;
4138 //unw_dyn_region_info_t *r_exceptions;
4139 MonoClass *exc_classes [16];
4140 guint8 *exc_throw_start [16], *exc_throw_end [16];
4141 guint32 code_size = 0;
4143 /* Compute needed space */
4144 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4145 if (patch_info->type == MONO_PATCH_INFO_EXC)
4147 if (patch_info->type == MONO_PATCH_INFO_R8)
4148 code_size += 8 + 7; /* sizeof (double) + alignment */
4149 if (patch_info->type == MONO_PATCH_INFO_R4)
4150 code_size += 4 + 7; /* sizeof (float) + alignment */
4156 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4157 cfg->code_size *= 2;
4158 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4159 mono_jit_stats.code_reallocs++;
4162 ia64_codegen_init (code, cfg->native_code + cfg->code_len);
4164 /* The unwind state here is the same as before the epilog */
4165 //ia64_unw_copy_state (code, 1234);
4167 /* add code to raise exceptions */
4168 /* FIXME: Optimize this */
4170 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4171 switch (patch_info->type) {
4172 case MONO_PATCH_INFO_EXC: {
4173 MonoClass *exc_class;
4176 guint64 exc_token_index;
4178 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4179 g_assert (exc_class);
4180 exc_token_index = mono_metadata_token_index (exc_class->type_token);
4181 throw_ip = cfg->native_code + patch_info->ip.i;
4183 ia64_begin_bundle (code);
4185 ia64_patch (cfg->native_code + patch_info->ip.i, code.buf);
4187 /* Find a throw sequence for the same exception class */
4188 for (i = 0; i < nthrows; ++i)
4189 if (exc_classes [i] == exc_class)
4193 gint64 offset = exc_throw_end [i] - 16 - throw_ip;
4195 if (ia64_is_adds_imm (offset))
4196 ia64_adds_imm (code, cfg->arch.reg_out0 + 1, offset, IA64_R0);
4198 ia64_movl (code, cfg->arch.reg_out0 + 1, offset);
4200 buf = code.buf + code.nins;
4201 ia64_br_cond_pred (code, 0, 0);
4202 ia64_begin_bundle (code);
4203 ia64_patch (buf, exc_throw_start [i]);
4205 patch_info->type = MONO_PATCH_INFO_NONE;
4210 ia64_movl (code, cfg->arch.reg_out0 + 1, 0);
4212 ia64_begin_bundle (code);
4215 exc_classes [nthrows] = exc_class;
4216 exc_throw_start [nthrows] = code.buf;
4220 if (ia64_is_adds_imm (exc_token_index))
4221 ia64_adds_imm (code, cfg->arch.reg_out0 + 0, exc_token_index, IA64_R0);
4223 ia64_movl (code, cfg->arch.reg_out0 + 0, exc_token_index);
4225 patch_info->data.name = "mono_arch_throw_corlib_exception";
4226 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4227 patch_info->ip.i = code.buf + code.nins - cfg->native_code;
4230 ia64_movl (code, GP_SCRATCH_REG, 0);
4231 ia64_ld8_inc_imm (code, GP_SCRATCH_REG2, GP_SCRATCH_REG, 8);
4232 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG2);
4233 ia64_ld8 (code, IA64_GP, GP_SCRATCH_REG);
4235 ia64_br_call_reg (code, IA64_B0, IA64_B6);
4237 /* Patch up the throw offset */
4238 ia64_begin_bundle (code);
4240 ia64_patch (buf, (gpointer)(code.buf - 16 - throw_ip));
4243 exc_throw_end [nthrows] = code.buf;
4257 /* The unwinder needs this to work */
4258 ia64_break_i (code, 0);
4260 ia64_codegen_close (code);
4263 //r_exceptions = mono_ia64_create_unwind_region (&code);
4264 //cfg->arch.r_epilog = r_exceptions;
4266 cfg->code_len = code.buf - cfg->native_code;
4268 g_assert (cfg->code_len < cfg->code_size);
4272 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4274 Ia64CodegenState code;
4275 CallInfo *cinfo = NULL;
4276 MonoMethodSignature *sig;
4278 int i, n, stack_area = 0;
4280 ia64_codegen_init (code, p);
4282 /* Keep this in sync with mono_arch_get_argument_info */
4284 if (enable_arguments) {
4285 /* Allocate a new area on the stack and save arguments there */
4286 sig = mono_method_signature (cfg->method);
4288 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4290 n = sig->param_count + sig->hasthis;
4292 stack_area = ALIGN_TO (n * 8, 16);
4295 ia64_movl (code, GP_SCRATCH_REG, stack_area);
4297 ia64_sub (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4299 /* FIXME: Allocate out registers */
4301 ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_SP);
4303 /* Required by the ABI */
4304 ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4306 add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4307 ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4309 /* Save arguments to the stack */
4310 for (i = 0; i < n; ++i) {
4311 ins = cfg->args [i];
4313 if (ins->opcode == OP_REGVAR) {
4314 ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4315 ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4316 ia64_st8 (code, GP_SCRATCH_REG, ins->dreg);
4319 ia64_movl (code, GP_SCRATCH_REG, ins->inst_offset);
4320 ia64_add (code, GP_SCRATCH_REG, ins->inst_basereg, GP_SCRATCH_REG);
4321 ia64_ld8 (code, GP_SCRATCH_REG2, GP_SCRATCH_REG);
4322 ia64_movl (code, GP_SCRATCH_REG, (i * 8));
4323 ia64_add (code, GP_SCRATCH_REG, cfg->arch.reg_out0 + 1, GP_SCRATCH_REG);
4324 ia64_st8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG2);
4329 ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4332 ia64_mov (code, cfg->arch.reg_out0 + 1, IA64_R0);
4334 add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4335 ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4337 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4339 if (enable_arguments && stack_area) {
4340 ia64_movl (code, GP_SCRATCH_REG, stack_area);
4342 ia64_add (code, IA64_SP, IA64_SP, GP_SCRATCH_REG);
4344 ia64_adds_imm (code, IA64_SP, 16, IA64_SP);
4347 ia64_codegen_close (code);
4353 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
4355 Ia64CodegenState code;
4356 CallInfo *cinfo = NULL;
4357 MonoMethod *method = cfg->method;
4358 MonoMethodSignature *sig = mono_method_signature (cfg->method);
4360 ia64_codegen_init (code, p);
4362 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
4364 /* Save return value + pass it to func */
4365 switch (cinfo->ret.storage) {
4369 ia64_mov (code, cfg->arch.reg_saved_return_val, cinfo->ret.reg);
4370 ia64_mov (code, cfg->arch.reg_out0 + 1, cinfo->ret.reg);
4373 ia64_adds_imm (code, IA64_SP, -16, IA64_SP);
4374 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4375 ia64_stfd_hint (code, GP_SCRATCH_REG, cinfo->ret.reg, 0);
4376 ia64_fmov (code, 8 + 1, cinfo->ret.reg);
4378 case ArgValuetypeAddrInIReg:
4379 ia64_mov (code, cfg->arch.reg_out0 + 1, cfg->arch.reg_in0 + cinfo->ret.reg);
4388 add_patch_info (cfg, code, MONO_PATCH_INFO_METHODCONST, method);
4389 ia64_movl (code, cfg->arch.reg_out0 + 0, 0);
4390 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4392 /* Restore return value */
4393 switch (cinfo->ret.storage) {
4397 ia64_mov (code, cinfo->ret.reg, cfg->arch.reg_saved_return_val);
4400 ia64_adds_imm (code, GP_SCRATCH_REG, 16, IA64_SP);
4401 ia64_ldfd (code, cinfo->ret.reg, GP_SCRATCH_REG);
4403 case ArgValuetypeAddrInIReg:
4411 ia64_codegen_close (code);
4417 mono_arch_save_unwind_info (MonoCompile *cfg)
4421 /* FIXME: Unregister this for dynamic methods */
4423 di = g_malloc0 (sizeof (unw_dyn_info_t));
4424 di->start_ip = (unw_word_t) cfg->native_code;
4425 di->end_ip = (unw_word_t) cfg->native_code + cfg->code_len;
4427 di->format = UNW_INFO_FORMAT_DYNAMIC;
4428 di->u.pi.name_ptr = (unw_word_t)mono_method_full_name (cfg->method, TRUE);
4429 di->u.pi.regions = cfg->arch.r_pro;
4431 _U_dyn_register (di);
4435 unw_dyn_region_info_t *region = di->u.pi.regions;
4437 printf ("Unwind info for method %s:\n", mono_method_full_name (cfg->method, TRUE));
4439 printf (" [Region: %d]\n", region->insn_count);
4440 region = region->next;
4447 mono_arch_flush_icache (guint8 *code, gint size)
4449 guint8* p = (guint8*)((guint64)code & ~(0x3f));
4450 guint8* end = (guint8*)((guint64)code + size);
4452 #ifdef __INTEL_COMPILER
4453 /* icc doesn't define an fc.i instrinsic, but fc==fc.i on itanium 2 */
4460 __asm__ __volatile__ ("fc.i %0"::"r"(p));
4461 /* FIXME: This could be increased to 128 on some cpus */
4468 mono_arch_flush_register_windows (void)
4470 /* Not needed because of libunwind */
4474 mono_arch_is_inst_imm (gint64 imm)
4476 /* The lowering pass will take care of it */
4482 * Determine whenever the trap whose info is in SIGINFO is caused by
4486 mono_arch_is_int_overflow (void *sigctx, void *info)
4488 /* Division is emulated with explicit overflow checks */
4493 mono_arch_get_patch_offset (guint8 *code)
4501 mono_arch_get_delegate_method_ptr_addr (guint8* code, mgreg_t *regs)
4509 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
4514 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
4518 #ifdef MONO_ARCH_HAVE_IMT
4521 * LOCKING: called with the domain lock held
4524 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
4525 gpointer fail_tramp)
4529 guint8 *start, *buf;
4530 Ia64CodegenState code;
4533 buf = g_malloc0 (size);
4534 ia64_codegen_init (code, buf);
4536 /* IA64_R9 contains the IMT method */
4538 for (i = 0; i < count; ++i) {
4539 MonoIMTCheckItem *item = imt_entries [i];
4540 ia64_begin_bundle (code);
4541 item->code_target = (guint8*)code.buf + code.nins;
4542 if (item->is_equals) {
4543 gboolean fail_case = !item->check_target_idx && fail_tramp;
4545 if (item->check_target_idx || fail_case) {
4546 if (!item->compare_done || fail_case) {
4547 ia64_movl (code, GP_SCRATCH_REG, item->key);
4548 ia64_cmp_eq (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4550 item->jmp_code = (guint8*)code.buf + code.nins;
4551 ia64_br_cond_pred (code, 7, 0);
4553 if (item->has_target_code) {
4554 ia64_movl (code, GP_SCRATCH_REG, item->value.target_code);
4556 ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4557 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4559 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4560 ia64_br_cond_reg (code, IA64_B6);
4563 ia64_begin_bundle (code);
4564 ia64_patch (item->jmp_code, (guint8*)code.buf + code.nins);
4565 ia64_movl (code, GP_SCRATCH_REG, fail_tramp);
4566 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4567 ia64_br_cond_reg (code, IA64_B6);
4568 item->jmp_code = NULL;
4571 /* enable the commented code to assert on wrong method */
4572 #if ENABLE_WRONG_METHOD_CHECK
4573 g_assert_not_reached ();
4575 ia64_movl (code, GP_SCRATCH_REG, &(vtable->vtable [item->value.vtable_slot]));
4576 ia64_ld8 (code, GP_SCRATCH_REG, GP_SCRATCH_REG);
4577 ia64_mov_to_br (code, IA64_B6, GP_SCRATCH_REG);
4578 ia64_br_cond_reg (code, IA64_B6);
4579 #if ENABLE_WRONG_METHOD_CHECK
4580 g_assert_not_reached ();
4584 ia64_movl (code, GP_SCRATCH_REG, item->key);
4585 ia64_cmp_geu (code, 6, 7, IA64_R9, GP_SCRATCH_REG);
4586 item->jmp_code = (guint8*)code.buf + code.nins;
4587 ia64_br_cond_pred (code, 6, 0);
4590 /* patch the branches to get to the target items */
4591 for (i = 0; i < count; ++i) {
4592 MonoIMTCheckItem *item = imt_entries [i];
4593 if (item->jmp_code) {
4594 if (item->check_target_idx) {
4595 ia64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
4600 ia64_codegen_close (code);
4601 g_assert (code.buf - buf <= size);
4603 size = code.buf - buf;
4605 start = mono_method_alloc_generic_virtual_thunk (domain, size + 16);
4606 start = (gpointer)ALIGN_TO (start, 16);
4608 start = mono_domain_code_reserve (domain, size);
4610 memcpy (start, buf, size);
4612 mono_arch_flush_icache (start, size);
4614 mono_stats.imt_thunks_size += size;
4620 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
4622 return (MonoMethod*)regs [IA64_R9];
4626 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
4628 /* Done by the implementation of the CALL_MEMBASE opcodes */
4633 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, mgreg_t *regs, guint8 *code)
4635 return (gpointer)regs [IA64_R10];
4639 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
4645 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
4647 MonoInst *ins = NULL;
4649 if (cmethod->klass->image == mono_defaults.corlib &&
4650 (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
4651 (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
4654 * We don't use the generic version in mini_emit_inst_for_method () since we
4655 * ia64 has atomic_add_imm opcodes.
4657 if (strcmp (cmethod->name, "Increment") == 0) {
4660 if (fsig->params [0]->type == MONO_TYPE_I4)
4661 opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4662 else if (fsig->params [0]->type == MONO_TYPE_I8)
4663 opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4665 g_assert_not_reached ();
4666 MONO_INST_NEW (cfg, ins, opcode);
4667 ins->dreg = mono_alloc_preg (cfg);
4669 ins->inst_basereg = args [0]->dreg;
4670 ins->inst_offset = 0;
4671 MONO_ADD_INS (cfg->cbb, ins);
4672 } else if (strcmp (cmethod->name, "Decrement") == 0) {
4675 if (fsig->params [0]->type == MONO_TYPE_I4)
4676 opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4677 else if (fsig->params [0]->type == MONO_TYPE_I8)
4678 opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4680 g_assert_not_reached ();
4681 MONO_INST_NEW (cfg, ins, opcode);
4682 ins->dreg = mono_alloc_preg (cfg);
4684 ins->inst_basereg = args [0]->dreg;
4685 ins->inst_offset = 0;
4686 MONO_ADD_INS (cfg->cbb, ins);
4687 } else if (strcmp (cmethod->name, "Add") == 0) {
4689 gboolean is_imm = FALSE;
4692 if ((args [1]->opcode == OP_ICONST) || (args [1]->opcode == OP_I8CONST)) {
4693 imm = (args [1]->opcode == OP_ICONST) ? args [1]->inst_c0 : args [1]->inst_l;
4695 is_imm = (imm == 1 || imm == 4 || imm == 8 || imm == 16 || imm == -1 || imm == -4 || imm == -8 || imm == -16);
4699 if (fsig->params [0]->type == MONO_TYPE_I4)
4700 opcode = OP_ATOMIC_ADD_IMM_NEW_I4;
4701 else if (fsig->params [0]->type == MONO_TYPE_I8)
4702 opcode = OP_ATOMIC_ADD_IMM_NEW_I8;
4704 g_assert_not_reached ();
4706 MONO_INST_NEW (cfg, ins, opcode);
4707 ins->dreg = mono_alloc_ireg (cfg);
4708 ins->inst_basereg = args [0]->dreg;
4709 ins->inst_offset = 0;
4710 ins->inst_imm = imm;
4711 ins->type = (opcode == OP_ATOMIC_ADD_IMM_NEW_I4) ? STACK_I4 : STACK_I8;
4713 if (fsig->params [0]->type == MONO_TYPE_I4)
4714 opcode = OP_ATOMIC_ADD_NEW_I4;
4715 else if (fsig->params [0]->type == MONO_TYPE_I8)
4716 opcode = OP_ATOMIC_ADD_NEW_I8;
4718 g_assert_not_reached ();
4720 MONO_INST_NEW (cfg, ins, opcode);
4721 ins->dreg = mono_alloc_ireg (cfg);
4722 ins->inst_basereg = args [0]->dreg;
4723 ins->inst_offset = 0;
4724 ins->sreg2 = args [1]->dreg;
4725 ins->type = (opcode == OP_ATOMIC_ADD_NEW_I4) ? STACK_I4 : STACK_I8;
4727 MONO_ADD_INS (cfg->cbb, ins);
4735 mono_arch_print_tree (MonoInst *tree, int arity)
4741 mono_arch_get_domain_intrinsic (MonoCompile* cfg)
4743 return mono_get_domain_intrinsic (cfg);
4747 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
4749 /* FIXME: implement */
4750 g_assert_not_reached ();